hw/pci/pcie.c

   1 /*
   2  * pcie.c
   3  *
   4  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
   5  *                    VA Linux Systems Japan K.K.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qapi/error.h"
  23 #include "qemu-common.h"
  24 #include "hw/pci/pci_bridge.h"
  25 #include "hw/pci/pcie.h"
  26 #include "hw/pci/msix.h"
  27 #include "hw/pci/msi.h"
  28 #include "hw/pci/pci_bus.h"
  29 #include "hw/pci/pcie_regs.h"
  30 #include "qemu/range.h"
  31
  32 //#define DEBUG_PCIE
  33 #ifdef DEBUG_PCIE
  34 # define PCIE_DPRINTF(fmt, ...)                                         \
  35     fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
  36 #else
  37 # define PCIE_DPRINTF(fmt, ...) do {} while (0)
  38 #endif
  39 #define PCIE_DEV_PRINTF(dev, fmt, ...)                                  \
  40     PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
  41
  42
  43 /***************************************************************************
  44  * pci express capability helper functions
  45  */
  46
  47 static void
  48 pcie_cap_v1_fill(PCIDevice *dev, uint8_t port, uint8_t type, uint8_t version)
  49 {
  50     uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
  51     uint8_t *cmask = dev->cmask + dev->exp.exp_cap;
  52
  53     /* capability register
  54     interrupt message number defaults to 0 */
  55     pci_set_word(exp_cap + PCI_EXP_FLAGS,
  56                  ((type << PCI_EXP_FLAGS_TYPE_SHIFT) & PCI_EXP_FLAGS_TYPE) |
  57                  version);
  58
  59     /* device capability register
  60      * table 7-12:
  61      * roll based error reporting bit must be set by all
  62      * Functions conforming to the ECN, PCI Express Base
  63      * Specification, Revision 1.1., or subsequent PCI Express Base
  64      * Specification revisions.
  65      */
  66     pci_set_long(exp_cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER);
  67
  68     pci_set_long(exp_cap + PCI_EXP_LNKCAP,
  69                  (port << PCI_EXP_LNKCAP_PN_SHIFT) |
  70                  PCI_EXP_LNKCAP_ASPMS_0S |
  71                  PCI_EXP_LNK_MLW_1 |
  72                  PCI_EXP_LNK_LS_25);
  73
  74     pci_set_word(exp_cap + PCI_EXP_LNKSTA,
  75                  PCI_EXP_LNK_MLW_1 | PCI_EXP_LNK_LS_25);
  76
  77     if (dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA) {
  78         pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA,
  79                                    PCI_EXP_LNKSTA_DLLLA);
  80     }
  81
  82     /* We changed link status bits over time, and changing them across
  83      * migrations is generally fine as hardware changes them too.
  84      * Let's not bother checking.
  85      */
  86     pci_set_word(cmask + PCI_EXP_LNKSTA, 0);
  87 }
  88
  89 int pcie_cap_init(PCIDevice *dev, uint8_t offset,
  90                   uint8_t type, uint8_t port,
  91                   Error **errp)
  92 {
  93     /* PCIe cap v2 init */
  94     int pos;
  95     uint8_t *exp_cap;
  96
  97     assert(pci_is_express(dev));
  98
  99     pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset,
 100                              PCI_EXP_VER2_SIZEOF, errp);
 101     if (pos < 0) {
 102         return pos;
 103     }
 104     dev->exp.exp_cap = pos;
 105     exp_cap = dev->config + pos;
 106
 107     /* Filling values common with v1 */
 108     pcie_cap_v1_fill(dev, port, type, PCI_EXP_FLAGS_VER2);
 109
 110     /* Filling v2 specific values */
 111     pci_set_long(exp_cap + PCI_EXP_DEVCAP2,
 112                  PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP);
 113
 114     pci_set_word(dev->wmask + pos + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_EETLPPB);
 115
 116     if (dev->cap_present & QEMU_PCIE_EXTCAP_INIT) {
 117         /* read-only to behave like a 'NULL' Extended Capability Header */
 118         pci_set_long(dev->wmask + PCI_CONFIG_SPACE_SIZE, 0);
 119     }
 120
 121     return pos;
 122 }
 123
 124 int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset, uint8_t type,
 125                      uint8_t port)
 126 {
 127     /* PCIe cap v1 init */
 128     int pos;
 129     Error *local_err = NULL;
 130
 131     assert(pci_is_express(dev));
 132
 133     pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset,
 134                              PCI_EXP_VER1_SIZEOF, &local_err);
 135     if (pos < 0) {
 136         error_report_err(local_err);
 137         return pos;
 138     }
 139     dev->exp.exp_cap = pos;
 140
 141     pcie_cap_v1_fill(dev, port, type, PCI_EXP_FLAGS_VER1);
 142
 143     return pos;
 144 }
 145
 146 static int
 147 pcie_endpoint_cap_common_init(PCIDevice *dev, uint8_t offset, uint8_t cap_size)
 148 {
 149     uint8_t type = PCI_EXP_TYPE_ENDPOINT;
 150     Error *local_err = NULL;
 151     int ret;
 152
 153     /*
 154      * Windows guests will report Code 10, device cannot start, if
 155      * a regular Endpoint type is exposed on a root complex.  These
 156      * should instead be Root Complex Integrated Endpoints.
 157      */
 158     if (pci_bus_is_express(pci_get_bus(dev))
 159         && pci_bus_is_root(pci_get_bus(dev))) {
 160         type = PCI_EXP_TYPE_RC_END;
 161     }
 162
 163     if (cap_size == PCI_EXP_VER1_SIZEOF) {
 164         return pcie_cap_v1_init(dev, offset, type, 0);
 165     } else {
 166         ret = pcie_cap_init(dev, offset, type, 0, &local_err);
 167
 168         if (ret < 0) {
 169             error_report_err(local_err);
 170         }
 171
 172         return ret;
 173     }
 174 }
 175
 176 int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset)
 177 {
 178     return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER2_SIZEOF);
 179 }
 180
 181 int pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset)
 182 {
 183     return pcie_endpoint_cap_common_init(dev, offset, PCI_EXP_VER1_SIZEOF);
 184 }
 185
 186 void pcie_cap_exit(PCIDevice *dev)
 187 {
 188     pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER2_SIZEOF);
 189 }
 190
 191 void pcie_cap_v1_exit(PCIDevice *dev)
 192 {
 193     pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER1_SIZEOF);
 194 }
 195
 196 uint8_t pcie_cap_get_type(const PCIDevice *dev)
 197 {
 198     uint32_t pos = dev->exp.exp_cap;
 199     assert(pos > 0);
 200     return (pci_get_word(dev->config + pos + PCI_EXP_FLAGS) &
 201             PCI_EXP_FLAGS_TYPE) >> PCI_EXP_FLAGS_TYPE_SHIFT;
 202 }
 203
 204 /* MSI/MSI-X */
 205 /* pci express interrupt message number */
 206 /* 7.8.2 PCI Express Capabilities Register: Interrupt Message Number */
 207 void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector)
 208 {
 209     uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
 210     assert(vector < 32);
 211     pci_word_test_and_clear_mask(exp_cap + PCI_EXP_FLAGS, PCI_EXP_FLAGS_IRQ);
 212     pci_word_test_and_set_mask(exp_cap + PCI_EXP_FLAGS,
 213                                vector << PCI_EXP_FLAGS_IRQ_SHIFT);
 214 }
 215
 216 uint8_t pcie_cap_flags_get_vector(PCIDevice *dev)
 217 {
 218     return (pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_FLAGS) &
 219             PCI_EXP_FLAGS_IRQ) >> PCI_EXP_FLAGS_IRQ_SHIFT;
 220 }
 221
 222 void pcie_cap_deverr_init(PCIDevice *dev)
 223 {
 224     uint32_t pos = dev->exp.exp_cap;
 225     pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP,
 226                                PCI_EXP_DEVCAP_RBER);
 227     pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL,
 228                                PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
 229                                PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
 230     pci_long_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_DEVSTA,
 231                                PCI_EXP_DEVSTA_CED | PCI_EXP_DEVSTA_NFED |
 232                                PCI_EXP_DEVSTA_FED | PCI_EXP_DEVSTA_URD);
 233 }
 234
 235 void pcie_cap_deverr_reset(PCIDevice *dev)
 236 {
 237     uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL;
 238     pci_long_test_and_clear_mask(devctl,
 239                                  PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
 240                                  PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
 241 }
 242
 243 void pcie_cap_lnkctl_init(PCIDevice *dev)
 244 {
 245     uint32_t pos = dev->exp.exp_cap;
 246     pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_LNKCTL,
 247                                PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_ES);
 248 }
 249
 250 void pcie_cap_lnkctl_reset(PCIDevice *dev)
 251 {
 252     uint8_t *lnkctl = dev->config + dev->exp.exp_cap + PCI_EXP_LNKCTL;
 253     pci_long_test_and_clear_mask(lnkctl,
 254                                  PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_ES);
 255 }
 256
 257 static void hotplug_event_update_event_status(PCIDevice *dev)
 258 {
 259     uint32_t pos = dev->exp.exp_cap;
 260     uint8_t *exp_cap = dev->config + pos;
 261     uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL);
 262     uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
 263
 264     dev->exp.hpev_notified = (sltctl & PCI_EXP_SLTCTL_HPIE) &&
 265         (sltsta & sltctl & PCI_EXP_HP_EV_SUPPORTED);
 266 }
 267
 268 static void hotplug_event_notify(PCIDevice *dev)
 269 {
 270     bool prev = dev->exp.hpev_notified;
 271
 272     hotplug_event_update_event_status(dev);
 273
 274     if (prev == dev->exp.hpev_notified) {
 275         return;
 276     }
 277
 278     /* Note: the logic above does not take into account whether interrupts
 279      * are masked. The result is that interrupt will be sent when it is
 280      * subsequently unmasked. This appears to be legal: Section 6.7.3.4:
 281      * The Port may optionally send an MSI when there are hot-plug events that
 282      * occur while interrupt generation is disabled, and interrupt generation is
 283      * subsequently enabled. */
 284     if (msix_enabled(dev)) {
 285         msix_notify(dev, pcie_cap_flags_get_vector(dev));
 286     } else if (msi_enabled(dev)) {
 287         msi_notify(dev, pcie_cap_flags_get_vector(dev));
 288     } else {
 289         pci_set_irq(dev, dev->exp.hpev_notified);
 290     }
 291 }
 292
 293 static void hotplug_event_clear(PCIDevice *dev)
 294 {
 295     hotplug_event_update_event_status(dev);
 296     if (!msix_enabled(dev) && !msi_enabled(dev) && !dev->exp.hpev_notified) {
 297         pci_irq_deassert(dev);
 298     }
 299 }
 300
 301 /*
 302  * A PCI Express Hot-Plug Event has occurred, so update slot status register
 303  * and notify OS of the event if necessary.
 304  *
 305  * 6.7.3 PCI Express Hot-Plug Events
 306  * 6.7.3.4 Software Notification of Hot-Plug Events
 307  */
 308 static void pcie_cap_slot_event(PCIDevice *dev, PCIExpressHotPlugEvent event)
 309 {
 310     /* Minor optimization: if nothing changed - no event is needed. */
 311     if (pci_word_test_and_set_mask(dev->config + dev->exp.exp_cap +
 312                                    PCI_EXP_SLTSTA, event)) {
 313         return;
 314     }
 315     hotplug_event_notify(dev);
 316 }
 317
 318 static void pcie_cap_slot_hotplug_common(PCIDevice *hotplug_dev,
 319                                          DeviceState *dev,
 320                                          uint8_t **exp_cap, Error **errp)
 321 {
 322     *exp_cap = hotplug_dev->config + hotplug_dev->exp.exp_cap;
 323     uint16_t sltsta = pci_get_word(*exp_cap + PCI_EXP_SLTSTA);
 324
 325     PCIE_DEV_PRINTF(PCI_DEVICE(dev), "hotplug state: 0x%x\n", sltsta);
 326     if (sltsta & PCI_EXP_SLTSTA_EIS) {
 327         /* the slot is electromechanically locked.
 328          * This error is propagated up to qdev and then to HMP/QMP.
 329          */
 330         error_setg_errno(errp, EBUSY, "slot is electromechanically locked");
 331     }
 332 }
 333
 334 void pcie_cap_slot_hotplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
 335                               Error **errp)
 336 {
 337     uint8_t *exp_cap;
 338     PCIDevice *pci_dev = PCI_DEVICE(dev);
 339
 340     pcie_cap_slot_hotplug_common(PCI_DEVICE(hotplug_dev), dev, &exp_cap, errp);
 341
 342     /* Don't send event when device is enabled during qemu machine creation:
 343      * it is present on boot, no hotplug event is necessary. We do send an
 344      * event when the device is disabled later. */
 345     if (!dev->hotplugged) {
 346         pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
 347                                    PCI_EXP_SLTSTA_PDS);
 348         if (pci_dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA) {
 349             pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA,
 350                                        PCI_EXP_LNKSTA_DLLLA);
 351         }
 352         return;
 353     }
 354
 355     /* To enable multifunction hot-plug, we just ensure the function
 356      * 0 added last. When function 0 is added, we set the sltsta and
 357      * inform OS via event notification.
 358      */
 359     if (pci_get_function_0(pci_dev)) {
 360         pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
 361                                    PCI_EXP_SLTSTA_PDS);
 362         if (pci_dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA) {
 363             pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA,
 364                                        PCI_EXP_LNKSTA_DLLLA);
 365         }
 366         pcie_cap_slot_event(PCI_DEVICE(hotplug_dev),
 367                             PCI_EXP_HP_EV_PDC | PCI_EXP_HP_EV_ABP);
 368     }
 369 }
 370
 371 static void pcie_unplug_device(PCIBus *bus, PCIDevice *dev, void *opaque)
 372 {
 373     object_unparent(OBJECT(dev));
 374 }
 375
 376 void pcie_cap_slot_hot_unplug_request_cb(HotplugHandler *hotplug_dev,
 377                                          DeviceState *dev, Error **errp)
 378 {
 379     uint8_t *exp_cap;
 380     PCIDevice *pci_dev = PCI_DEVICE(dev);
 381     PCIBus *bus = pci_get_bus(pci_dev);
 382
 383     pcie_cap_slot_hotplug_common(PCI_DEVICE(hotplug_dev), dev, &exp_cap, errp);
 384
 385     /* In case user cancel the operation of multi-function hot-add,
 386      * remove the function that is unexposed to guest individually,
 387      * without interaction with guest.
 388      */
 389     if (pci_dev->devfn &&
 390         !bus->devices[0]) {
 391         pcie_unplug_device(bus, pci_dev, NULL);
 392
 393         return;
 394     }
 395
 396     pcie_cap_slot_push_attention_button(PCI_DEVICE(hotplug_dev));
 397 }
 398
 399 /* pci express slot for pci express root/downstream port
 400    PCI express capability slot registers */
 401 void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot)
 402 {
 403     uint32_t pos = dev->exp.exp_cap;
 404
 405     pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_FLAGS,
 406                                PCI_EXP_FLAGS_SLOT);
 407
 408     pci_long_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCAP,
 409                                  ~PCI_EXP_SLTCAP_PSN);
 410     pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,
 411                                (slot << PCI_EXP_SLTCAP_PSN_SHIFT) |
 412                                PCI_EXP_SLTCAP_EIP |
 413                                PCI_EXP_SLTCAP_HPS |
 414                                PCI_EXP_SLTCAP_HPC |
 415                                PCI_EXP_SLTCAP_PIP |
 416                                PCI_EXP_SLTCAP_AIP |
 417                                PCI_EXP_SLTCAP_ABP);
 418
 419     if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) {
 420         pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,
 421                                    PCI_EXP_SLTCAP_PCP);
 422         pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL,
 423                                      PCI_EXP_SLTCTL_PCC);
 424         pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
 425                                    PCI_EXP_SLTCTL_PCC);
 426     }
 427
 428     pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL,
 429                                  PCI_EXP_SLTCTL_PIC |
 430                                  PCI_EXP_SLTCTL_AIC);
 431     pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCTL,
 432                                PCI_EXP_SLTCTL_PIC_OFF |
 433                                PCI_EXP_SLTCTL_AIC_OFF);
 434     pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
 435                                PCI_EXP_SLTCTL_PIC |
 436                                PCI_EXP_SLTCTL_AIC |
 437                                PCI_EXP_SLTCTL_HPIE |
 438                                PCI_EXP_SLTCTL_CCIE |
 439                                PCI_EXP_SLTCTL_PDCE |
 440                                PCI_EXP_SLTCTL_ABPE);
 441     /* Although reading PCI_EXP_SLTCTL_EIC returns always 0,
 442      * make the bit writable here in order to detect 1b is written.
 443      * pcie_cap_slot_write_config() test-and-clear the bit, so
 444      * this bit always returns 0 to the guest.
 445      */
 446     pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
 447                                PCI_EXP_SLTCTL_EIC);
 448
 449     pci_word_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_SLTSTA,
 450                                PCI_EXP_HP_EV_SUPPORTED);
 451
 452     dev->exp.hpev_notified = false;
 453
 454     qbus_set_hotplug_handler(BUS(pci_bridge_get_sec_bus(PCI_BRIDGE(dev))),
 455                              DEVICE(dev), NULL);
 456 }
 457
 458 void pcie_cap_slot_reset(PCIDevice *dev)
 459 {
 460     uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
 461     uint8_t port_type = pcie_cap_get_type(dev);
 462
 463     assert(port_type == PCI_EXP_TYPE_DOWNSTREAM ||
 464            port_type == PCI_EXP_TYPE_ROOT_PORT);
 465
 466     PCIE_DEV_PRINTF(dev, "reset\n");
 467
 468     pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
 469                                  PCI_EXP_SLTCTL_EIC |
 470                                  PCI_EXP_SLTCTL_PIC |
 471                                  PCI_EXP_SLTCTL_AIC |
 472                                  PCI_EXP_SLTCTL_HPIE |
 473                                  PCI_EXP_SLTCTL_CCIE |
 474                                  PCI_EXP_SLTCTL_PDCE |
 475                                  PCI_EXP_SLTCTL_ABPE);
 476     pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL,
 477                                PCI_EXP_SLTCTL_AIC_OFF);
 478
 479     if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) {
 480         /* Downstream ports enforce device number 0. */
 481         bool populated = pci_bridge_get_sec_bus(PCI_BRIDGE(dev))->devices[0];
 482         uint16_t pic;
 483
 484         if (populated) {
 485             pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
 486                                          PCI_EXP_SLTCTL_PCC);
 487         } else {
 488             pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL,
 489                                        PCI_EXP_SLTCTL_PCC);
 490         }
 491
 492         pic = populated ? PCI_EXP_SLTCTL_PIC_ON : PCI_EXP_SLTCTL_PIC_OFF;
 493         pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, pic);
 494     }
 495
 496     pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA,
 497                                  PCI_EXP_SLTSTA_EIS |/* on reset,
 498                                                         the lock is released */
 499                                  PCI_EXP_SLTSTA_CC |
 500                                  PCI_EXP_SLTSTA_PDC |
 501                                  PCI_EXP_SLTSTA_ABP);
 502
 503     hotplug_event_update_event_status(dev);
 504 }
 505
 506 void pcie_cap_slot_write_config(PCIDevice *dev,
 507                                 uint32_t addr, uint32_t val, int len)
 508 {
 509     uint32_t pos = dev->exp.exp_cap;
 510     uint8_t *exp_cap = dev->config + pos;
 511     uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
 512
 513     if (ranges_overlap(addr, len, pos + PCI_EXP_SLTSTA, 2)) {
 514         hotplug_event_clear(dev);
 515     }
 516
 517     if (!ranges_overlap(addr, len, pos + PCI_EXP_SLTCTL, 2)) {
 518         return;
 519     }
 520
 521     if (pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
 522                                      PCI_EXP_SLTCTL_EIC)) {
 523         sltsta ^= PCI_EXP_SLTSTA_EIS; /* toggle PCI_EXP_SLTSTA_EIS bit */
 524         pci_set_word(exp_cap + PCI_EXP_SLTSTA, sltsta);
 525         PCIE_DEV_PRINTF(dev, "PCI_EXP_SLTCTL_EIC: "
 526                         "sltsta -> 0x%02"PRIx16"\n",
 527                         sltsta);
 528     }
 529
 530     /*
 531      * If the slot is polulated, power indicator is off and power
 532      * controller is off, it is safe to detach the devices.
 533      */
 534     if ((sltsta & PCI_EXP_SLTSTA_PDS) && (val & PCI_EXP_SLTCTL_PCC) &&
 535         ((val & PCI_EXP_SLTCTL_PIC_OFF) == PCI_EXP_SLTCTL_PIC_OFF)) {
 536         PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
 537         pci_for_each_device(sec_bus, pci_bus_num(sec_bus),
 538                             pcie_unplug_device, NULL);
 539
 540         pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA,
 541                                      PCI_EXP_SLTSTA_PDS);
 542         if (dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA) {
 543             pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKSTA,
 544                                          PCI_EXP_LNKSTA_DLLLA);
 545         }
 546         pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
 547                                        PCI_EXP_SLTSTA_PDC);
 548     }
 549
 550     hotplug_event_notify(dev);
 551
 552     /*
 553      * 6.7.3.2 Command Completed Events
 554      *
 555      * Software issues a command to a hot-plug capable Downstream Port by
 556      * issuing a write transaction that targets any portion of the Port’s Slot
 557      * Control register. A single write to the Slot Control register is
 558      * considered to be a single command, even if the write affects more than
 559      * one field in the Slot Control register. In response to this transaction,
 560      * the Port must carry out the requested actions and then set the
 561      * associated status field for the command completed event. */
 562
 563     /* Real hardware might take a while to complete requested command because
 564      * physical movement would be involved like locking the electromechanical
 565      * lock.  However in our case, command is completed instantaneously above,
 566      * so send a command completion event right now.
 567      */
 568     pcie_cap_slot_event(dev, PCI_EXP_HP_EV_CCI);
 569 }
 570
 571 int pcie_cap_slot_post_load(void *opaque, int version_id)
 572 {
 573     PCIDevice *dev = opaque;
 574     hotplug_event_update_event_status(dev);
 575     return 0;
 576 }
 577
 578 void pcie_cap_slot_push_attention_button(PCIDevice *dev)
 579 {
 580     pcie_cap_slot_event(dev, PCI_EXP_HP_EV_ABP);
 581 }
 582
 583 /* root control/capabilities/status. PME isn't emulated for now */
 584 void pcie_cap_root_init(PCIDevice *dev)
 585 {
 586     pci_set_word(dev->wmask + dev->exp.exp_cap + PCI_EXP_RTCTL,
 587                  PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE |
 588                  PCI_EXP_RTCTL_SEFEE);
 589 }
 590
 591 void pcie_cap_root_reset(PCIDevice *dev)
 592 {
 593     pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_RTCTL, 0);
 594 }
 595
 596 /* function level reset(FLR) */
 597 void pcie_cap_flr_init(PCIDevice *dev)
 598 {
 599     pci_long_test_and_set_mask(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCAP,
 600                                PCI_EXP_DEVCAP_FLR);
 601
 602     /* Although reading BCR_FLR returns always 0,
 603      * the bit is made writable here in order to detect the 1b is written
 604      * pcie_cap_flr_write_config() test-and-clear the bit, so
 605      * this bit always returns 0 to the guest.
 606      */
 607     pci_word_test_and_set_mask(dev->wmask + dev->exp.exp_cap + PCI_EXP_DEVCTL,
 608                                PCI_EXP_DEVCTL_BCR_FLR);
 609 }
 610
 611 void pcie_cap_flr_write_config(PCIDevice *dev,
 612                                uint32_t addr, uint32_t val, int len)
 613 {
 614     uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL;
 615     if (pci_get_word(devctl) & PCI_EXP_DEVCTL_BCR_FLR) {
 616         /* Clear PCI_EXP_DEVCTL_BCR_FLR after invoking the reset handler
 617            so the handler can detect FLR by looking at this bit. */
 618         pci_device_reset(dev);
 619         pci_word_test_and_clear_mask(devctl, PCI_EXP_DEVCTL_BCR_FLR);
 620     }
 621 }
 622
 623 /* Alternative Routing-ID Interpretation (ARI)
 624  * forwarding support for root and downstream ports
 625  */
 626 void pcie_cap_arifwd_init(PCIDevice *dev)
 627 {
 628     uint32_t pos = dev->exp.exp_cap;
 629     pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP2,
 630                                PCI_EXP_DEVCAP2_ARI);
 631     pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL2,
 632                                PCI_EXP_DEVCTL2_ARI);
 633 }
 634
 635 void pcie_cap_arifwd_reset(PCIDevice *dev)
 636 {
 637     uint8_t *devctl2 = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2;
 638     pci_long_test_and_clear_mask(devctl2, PCI_EXP_DEVCTL2_ARI);
 639 }
 640
 641 bool pcie_cap_is_arifwd_enabled(const PCIDevice *dev)
 642 {
 643     if (!pci_is_express(dev)) {
 644         return false;
 645     }
 646     if (!dev->exp.exp_cap) {
 647         return false;
 648     }
 649
 650     return pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) &
 651         PCI_EXP_DEVCTL2_ARI;
 652 }
 653
 654 /**************************************************************************
 655  * pci express extended capability list management functions
 656  * uint16_t ext_cap_id (16 bit)
 657  * uint8_t cap_ver (4 bit)
 658  * uint16_t cap_offset (12 bit)
 659  * uint16_t ext_cap_size
 660  */
 661
 662 /* Passing a cap_id value > 0xffff will return 0 and put end of list in prev */
 663 static uint16_t pcie_find_capability_list(PCIDevice *dev, uint32_t cap_id,
 664                                           uint16_t *prev_p)
 665 {
 666     uint16_t prev = 0;
 667     uint16_t next;
 668     uint32_t header = pci_get_long(dev->config + PCI_CONFIG_SPACE_SIZE);
 669
 670     if (!header) {
 671         /* no extended capability */
 672         next = 0;
 673         goto out;
 674     }
 675     for (next = PCI_CONFIG_SPACE_SIZE; next;
 676          prev = next, next = PCI_EXT_CAP_NEXT(header)) {
 677
 678         assert(next >= PCI_CONFIG_SPACE_SIZE);
 679         assert(next <= PCIE_CONFIG_SPACE_SIZE - 8);
 680
 681         header = pci_get_long(dev->config + next);
 682         if (PCI_EXT_CAP_ID(header) == cap_id) {
 683             break;
 684         }
 685     }
 686
 687 out:
 688     if (prev_p) {
 689         *prev_p = prev;
 690     }
 691     return next;
 692 }
 693
 694 uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id)
 695 {
 696     return pcie_find_capability_list(dev, cap_id, NULL);
 697 }
 698
 699 static void pcie_ext_cap_set_next(PCIDevice *dev, uint16_t pos, uint16_t next)
 700 {
 701     uint32_t header = pci_get_long(dev->config + pos);
 702     assert(!(next & (PCI_EXT_CAP_ALIGN - 1)));
 703     header = (header & ~PCI_EXT_CAP_NEXT_MASK) |
 704         ((next << PCI_EXT_CAP_NEXT_SHIFT) & PCI_EXT_CAP_NEXT_MASK);
 705     pci_set_long(dev->config + pos, header);
 706 }
 707
 708 /*
 709  * Caller must supply valid (offset, size) such that the range wouldn't
 710  * overlap with other capability or other registers.
 711  * This function doesn't check it.
 712  */
 713 void pcie_add_capability(PCIDevice *dev,
 714                          uint16_t cap_id, uint8_t cap_ver,
 715                          uint16_t offset, uint16_t size)
 716 {
 717     assert(offset >= PCI_CONFIG_SPACE_SIZE);
 718     assert(offset < offset + size);
 719     assert(offset + size <= PCIE_CONFIG_SPACE_SIZE);
 720     assert(size >= 8);
 721     assert(pci_is_express(dev));
 722
 723     if (offset != PCI_CONFIG_SPACE_SIZE) {
 724         uint16_t prev;
 725
 726         /*
 727          * 0xffffffff is not a valid cap id (it's a 16 bit field). use
 728          * internally to find the last capability in the linked list.
 729          */
 730         pcie_find_capability_list(dev, 0xffffffff, &prev);
 731         assert(prev >= PCI_CONFIG_SPACE_SIZE);
 732         pcie_ext_cap_set_next(dev, prev, offset);
 733     }
 734     pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, 0));
 735
 736     /* Make capability read-only by default */
 737     memset(dev->wmask + offset, 0, size);
 738     memset(dev->w1cmask + offset, 0, size);
 739     /* Check capability by default */
 740     memset(dev->cmask + offset, 0xFF, size);
 741 }
 742
 743 /**************************************************************************
 744  * pci express extended capability helper functions
 745  */
 746
 747 /* ARI */
 748 void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn)
 749 {
 750     pcie_add_capability(dev, PCI_EXT_CAP_ID_ARI, PCI_ARI_VER,
 751                         offset, PCI_ARI_SIZEOF);
 752     pci_set_long(dev->config + offset + PCI_ARI_CAP, (nextfn & 0xff) << 8);
 753 }
 754
 755 void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_num)
 756 {
 757     static const int pci_dsn_ver = 1;
 758     static const int pci_dsn_cap = 4;
 759
 760     pcie_add_capability(dev, PCI_EXT_CAP_ID_DSN, pci_dsn_ver, offset,
 761                         PCI_EXT_CAP_DSN_SIZEOF);
 762     pci_set_quad(dev->config + offset + pci_dsn_cap, ser_num);
 763 }
 764
 765 void pcie_ats_init(PCIDevice *dev, uint16_t offset)
 766 {
 767     pcie_add_capability(dev, PCI_EXT_CAP_ID_ATS, 0x1,
 768                         offset, PCI_EXT_CAP_ATS_SIZEOF);
 769
 770     dev->exp.ats_cap = offset;
 771
 772     /* Invalidate Queue Depth 0, Page Aligned Request 0 */
 773     pci_set_word(dev->config + offset + PCI_ATS_CAP, 0);
 774     /* STU 0, Disabled by default */
 775     pci_set_word(dev->config + offset + PCI_ATS_CTRL, 0);
 776
 777     pci_set_word(dev->wmask + dev->exp.ats_cap + PCI_ATS_CTRL, 0x800f);
 778 }