hw/piix_pci.c

   1 /*
   2  * QEMU i440FX/PIIX3 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "pc.h"
  27 #include "pci.h"
  28 #include "pci_host.h"
  29 #include "isa.h"
  30 #include "sysbus.h"
  31 #include "range.h"
  32 #include "xen.h"
  33
  34 /*
  35  * I440FX chipset data sheet.
  36  * http://download.intel.com/design/chipsets/datashts/29054901.pdf
  37  */
  38
  39 typedef PCIHostState I440FXState;
  40
  41 #define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
  42 #define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
  43 #define PIIX_PIRQC              0x60
  44
  45 typedef struct PIIX3State {
  46     PCIDevice dev;
  47
  48     /*
  49      * bitmap to track pic levels.
  50      * The pic level is the logical OR of all the PCI irqs mapped to it
  51      * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
  52      *
  53      * PIRQ is mapped to PIC pins, we track it by
  54      * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
  55      * pic_irq * PIIX_NUM_PIRQS + pirq
  56      */
  57 #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
  58 #error "unable to encode pic state in 64bit in pic_levels."
  59 #endif
  60     uint64_t pic_levels;
  61
  62     qemu_irq *pic;
  63
  64     /* This member isn't used. Just for save/load compatibility */
  65     int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
  66 } PIIX3State;
  67
  68 struct PCII440FXState {
  69     PCIDevice dev;
  70     target_phys_addr_t isa_page_descs[384 / 4];
  71     uint8_t smm_enabled;
  72     PIIX3State *piix3;
  73 };
  74
  75
  76 #define I440FX_PAM      0x59
  77 #define I440FX_PAM_SIZE 7
  78 #define I440FX_SMRAM    0x72
  79
  80 static void piix3_set_irq(void *opaque, int pirq, int level);
  81
  82 /* return the global irq number corresponding to a given device irq
  83    pin. We could also use the bus number to have a more precise
  84    mapping. */
  85 static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
  86 {
  87     int slot_addend;
  88     slot_addend = (pci_dev->devfn >> 3) - 1;
  89     return (pci_intx + slot_addend) & 3;
  90 }
  91
  92 static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r)
  93 {
  94     uint32_t addr;
  95
  96     //    printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
  97     switch(r) {
  98     case 3:
  99         /* RAM */
 100         cpu_register_physical_memory(start, end - start,
 101                                      start);
 102         break;
 103     case 1:
 104         /* ROM (XXX: not quite correct) */
 105         cpu_register_physical_memory(start, end - start,
 106                                      start | IO_MEM_ROM);
 107         break;
 108     case 2:
 109     case 0:
 110         /* XXX: should distinguish read/write cases */
 111         for(addr = start; addr < end; addr += 4096) {
 112             cpu_register_physical_memory(addr, 4096,
 113                                          d->isa_page_descs[(addr - 0xa0000) >> 12]);
 114         }
 115         break;
 116     }
 117 }
 118
 119 static void i440fx_update_memory_mappings(PCII440FXState *d)
 120 {
 121     int i, r;
 122     uint32_t smram, addr;
 123
 124     update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3);
 125     for(i = 0; i < 12; i++) {
 126         r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
 127         update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
 128     }
 129     smram = d->dev.config[I440FX_SMRAM];
 130     if ((d->smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
 131         cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
 132     } else {
 133         for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
 134             cpu_register_physical_memory(addr, 4096,
 135                                          d->isa_page_descs[(addr - 0xa0000) >> 12]);
 136         }
 137     }
 138 }
 139
 140 static void i440fx_set_smm(int val, void *arg)
 141 {
 142     PCII440FXState *d = arg;
 143
 144     val = (val != 0);
 145     if (d->smm_enabled != val) {
 146         d->smm_enabled = val;
 147         i440fx_update_memory_mappings(d);
 148     }
 149 }
 150
 151
 152 /* XXX: suppress when better memory API. We make the assumption that
 153    no device (in particular the VGA) changes the memory mappings in
 154    the 0xa0000-0x100000 range */
 155 void i440fx_init_memory_mappings(PCII440FXState *d)
 156 {
 157     int i;
 158     for(i = 0; i < 96; i++) {
 159         d->isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
 160     }
 161 }
 162
 163 static void i440fx_write_config(PCIDevice *dev,
 164                                 uint32_t address, uint32_t val, int len)
 165 {
 166     PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
 167
 168     /* XXX: implement SMRAM.D_LOCK */
 169     pci_default_write_config(dev, address, val, len);
 170     if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
 171         range_covers_byte(address, len, I440FX_SMRAM)) {
 172         i440fx_update_memory_mappings(d);
 173     }
 174 }
 175
 176 static void i440fx_write_config_xen(PCIDevice *dev,
 177                                     uint32_t address, uint32_t val, int len)
 178 {
 179     xen_piix_pci_write_config_client(address, val, len);
 180     i440fx_write_config(dev, address, val, len);
 181 }
 182
 183 static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
 184 {
 185     PCII440FXState *d = opaque;
 186     int ret, i;
 187
 188     ret = pci_device_load(&d->dev, f);
 189     if (ret < 0)
 190         return ret;
 191     i440fx_update_memory_mappings(d);
 192     qemu_get_8s(f, &d->smm_enabled);
 193
 194     if (version_id == 2) {
 195         for (i = 0; i < PIIX_NUM_PIRQS; i++) {
 196             qemu_get_be32(f); /* dummy load for compatibility */
 197         }
 198     }
 199
 200     return 0;
 201 }
 202
 203 static int i440fx_post_load(void *opaque, int version_id)
 204 {
 205     PCII440FXState *d = opaque;
 206
 207     i440fx_update_memory_mappings(d);
 208     return 0;
 209 }
 210
 211 static const VMStateDescription vmstate_i440fx = {
 212     .name = "I440FX",
 213     .version_id = 3,
 214     .minimum_version_id = 3,
 215     .minimum_version_id_old = 1,
 216     .load_state_old = i440fx_load_old,
 217     .post_load = i440fx_post_load,
 218     .fields      = (VMStateField []) {
 219         VMSTATE_PCI_DEVICE(dev, PCII440FXState),
 220         VMSTATE_UINT8(smm_enabled, PCII440FXState),
 221         VMSTATE_END_OF_LIST()
 222     }
 223 };
 224
 225 static int i440fx_pcihost_initfn(SysBusDevice *dev)
 226 {
 227     I440FXState *s = FROM_SYSBUS(I440FXState, dev);
 228
 229     pci_host_conf_register_ioport(0xcf8, s);
 230
 231     pci_host_data_register_ioport(0xcfc, s);
 232     return 0;
 233 }
 234
 235 static int i440fx_initfn(PCIDevice *dev)
 236 {
 237     PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
 238
 239     d->dev.config[I440FX_SMRAM] = 0x02;
 240
 241     cpu_smm_register(&i440fx_set_smm, d);
 242     return 0;
 243 }
 244
 245 static PCIBus *i440fx_common_init(const char *device_name,
 246                                   PCII440FXState **pi440fx_state,
 247                                   int *piix3_devfn,
 248                                   qemu_irq *pic, ram_addr_t ram_size)
 249 {
 250     DeviceState *dev;
 251     PCIBus *b;
 252     PCIDevice *d;
 253     I440FXState *s;
 254     PIIX3State *piix3;
 255
 256     dev = qdev_create(NULL, "i440FX-pcihost");
 257     s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
 258     b = pci_bus_new(&s->busdev.qdev, NULL, 0);
 259     s->bus = b;
 260     qdev_init_nofail(dev);
 261
 262     d = pci_create_simple(b, 0, device_name);
 263     *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
 264
 265     piix3 = DO_UPCAST(PIIX3State, dev,
 266                       pci_create_simple_multifunction(b, -1, true, "PIIX3"));
 267     piix3->pic = pic;
 268
 269     (*pi440fx_state)->piix3 = piix3;
 270
 271     *piix3_devfn = piix3->dev.devfn;
 272
 273     ram_size = ram_size / 8 / 1024 / 1024;
 274     if (ram_size > 255)
 275         ram_size = 255;
 276     (*pi440fx_state)->dev.config[0x57]=ram_size;
 277
 278     return b;
 279 }
 280
 281 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
 282                     qemu_irq *pic, ram_addr_t ram_size)
 283 {
 284     PCIBus *b;
 285
 286     b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, pic, ram_size);
 287     pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, (*pi440fx_state)->piix3,
 288                  PIIX_NUM_PIRQS);
 289
 290     return b;
 291 }
 292
 293 PCIBus *i440fx_xen_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
 294                         qemu_irq *pic, ram_addr_t ram_size)
 295 {
 296     PCIBus *b;
 297
 298     b = i440fx_common_init("i440FX-xen", pi440fx_state, piix3_devfn, pic, ram_size);
 299     pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
 300                  (*pi440fx_state)->piix3, PIIX_NUM_PIRQS);
 301
 302     return b;
 303 }
 304
 305 /* PIIX3 PCI to ISA bridge */
 306 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
 307 {
 308     qemu_set_irq(piix3->pic[pic_irq],
 309                  !!(piix3->pic_levels &
 310                     (((1ULL << PIIX_NUM_PIRQS) - 1) <<
 311                      (pic_irq * PIIX_NUM_PIRQS))));
 312 }
 313
 314 static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
 315 {
 316     int pic_irq;
 317     uint64_t mask;
 318
 319     pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
 320     if (pic_irq >= PIIX_NUM_PIC_IRQS) {
 321         return;
 322     }
 323
 324     mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
 325     piix3->pic_levels &= ~mask;
 326     piix3->pic_levels |= mask * !!level;
 327
 328     piix3_set_irq_pic(piix3, pic_irq);
 329 }
 330
 331 static void piix3_set_irq(void *opaque, int pirq, int level)
 332 {
 333     PIIX3State *piix3 = opaque;
 334     piix3_set_irq_level(piix3, pirq, level);
 335 }
 336
 337 /* irq routing is changed. so rebuild bitmap */
 338 static void piix3_update_irq_levels(PIIX3State *piix3)
 339 {
 340     int pirq;
 341
 342     piix3->pic_levels = 0;
 343     for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
 344         piix3_set_irq_level(piix3, pirq,
 345                             pci_bus_get_irq_level(piix3->dev.bus, pirq));
 346     }
 347 }
 348
 349 static void piix3_write_config(PCIDevice *dev,
 350                                uint32_t address, uint32_t val, int len)
 351 {
 352     pci_default_write_config(dev, address, val, len);
 353     if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
 354         PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev);
 355         int pic_irq;
 356         piix3_update_irq_levels(piix3);
 357         for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
 358             piix3_set_irq_pic(piix3, pic_irq);
 359         }
 360     }
 361 }
 362
 363 static void piix3_reset(void *opaque)
 364 {
 365     PIIX3State *d = opaque;
 366     uint8_t *pci_conf = d->dev.config;
 367
 368     pci_conf[0x04] = 0x07; // master, memory and I/O
 369     pci_conf[0x05] = 0x00;
 370     pci_conf[0x06] = 0x00;
 371     pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
 372     pci_conf[0x4c] = 0x4d;
 373     pci_conf[0x4e] = 0x03;
 374     pci_conf[0x4f] = 0x00;
 375     pci_conf[0x60] = 0x80;
 376     pci_conf[0x61] = 0x80;
 377     pci_conf[0x62] = 0x80;
 378     pci_conf[0x63] = 0x80;
 379     pci_conf[0x69] = 0x02;
 380     pci_conf[0x70] = 0x80;
 381     pci_conf[0x76] = 0x0c;
 382     pci_conf[0x77] = 0x0c;
 383     pci_conf[0x78] = 0x02;
 384     pci_conf[0x79] = 0x00;
 385     pci_conf[0x80] = 0x00;
 386     pci_conf[0x82] = 0x00;
 387     pci_conf[0xa0] = 0x08;
 388     pci_conf[0xa2] = 0x00;
 389     pci_conf[0xa3] = 0x00;
 390     pci_conf[0xa4] = 0x00;
 391     pci_conf[0xa5] = 0x00;
 392     pci_conf[0xa6] = 0x00;
 393     pci_conf[0xa7] = 0x00;
 394     pci_conf[0xa8] = 0x0f;
 395     pci_conf[0xaa] = 0x00;
 396     pci_conf[0xab] = 0x00;
 397     pci_conf[0xac] = 0x00;
 398     pci_conf[0xae] = 0x00;
 399
 400     d->pic_levels = 0;
 401 }
 402
 403 static int piix3_post_load(void *opaque, int version_id)
 404 {
 405     PIIX3State *piix3 = opaque;
 406     piix3_update_irq_levels(piix3);
 407     return 0;
 408 }
 409
 410 static void piix3_pre_save(void *opaque)
 411 {
 412     int i;
 413     PIIX3State *piix3 = opaque;
 414
 415     for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
 416         piix3->pci_irq_levels_vmstate[i] =
 417             pci_bus_get_irq_level(piix3->dev.bus, i);
 418     }
 419 }
 420
 421 static const VMStateDescription vmstate_piix3 = {
 422     .name = "PIIX3",
 423     .version_id = 3,
 424     .minimum_version_id = 2,
 425     .minimum_version_id_old = 2,
 426     .post_load = piix3_post_load,
 427     .pre_save = piix3_pre_save,
 428     .fields      = (VMStateField []) {
 429         VMSTATE_PCI_DEVICE(dev, PIIX3State),
 430         VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
 431                               PIIX_NUM_PIRQS, 3),
 432         VMSTATE_END_OF_LIST()
 433     }
 434 };
 435
 436 static int piix3_initfn(PCIDevice *dev)
 437 {
 438     PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
 439
 440     isa_bus_new(&d->dev.qdev);
 441     qemu_register_reset(piix3_reset, d);
 442     return 0;
 443 }
 444
 445 static PCIDeviceInfo i440fx_info[] = {
 446     {
 447         .qdev.name    = "i440FX",
 448         .qdev.desc    = "Host bridge",
 449         .qdev.size    = sizeof(PCII440FXState),
 450         .qdev.vmsd    = &vmstate_i440fx,
 451         .qdev.no_user = 1,
 452         .no_hotplug   = 1,
 453         .init         = i440fx_initfn,
 454         .config_write = i440fx_write_config,
 455         .vendor_id    = PCI_VENDOR_ID_INTEL,
 456         .device_id    = PCI_DEVICE_ID_INTEL_82441,
 457         .revision     = 0x02,
 458         .class_id     = PCI_CLASS_BRIDGE_HOST,
 459     },{
 460         .qdev.name    = "i440FX-xen",
 461         .qdev.desc    = "Host bridge",
 462         .qdev.size    = sizeof(PCII440FXState),
 463         .qdev.vmsd    = &vmstate_i440fx,
 464         .qdev.no_user = 1,
 465         .init         = i440fx_initfn,
 466         .config_write = i440fx_write_config_xen,
 467     },{
 468         .qdev.name    = "PIIX3",
 469         .qdev.desc    = "ISA bridge",
 470         .qdev.size    = sizeof(PIIX3State),
 471         .qdev.vmsd    = &vmstate_piix3,
 472         .qdev.no_user = 1,
 473         .no_hotplug   = 1,
 474         .init         = piix3_initfn,
 475         .config_write = piix3_write_config,
 476         .vendor_id    = PCI_VENDOR_ID_INTEL,
 477         .device_id    = PCI_DEVICE_ID_INTEL_82371SB_0, // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
 478         .class_id     = PCI_CLASS_BRIDGE_ISA,
 479     },{
 480         /* end of list */
 481     }
 482 };
 483
 484 static SysBusDeviceInfo i440fx_pcihost_info = {
 485     .init         = i440fx_pcihost_initfn,
 486     .qdev.name    = "i440FX-pcihost",
 487     .qdev.fw_name = "pci",
 488     .qdev.size    = sizeof(I440FXState),
 489     .qdev.no_user = 1,
 490 };
 491
 492 static void i440fx_register(void)
 493 {
 494     sysbus_register_withprop(&i440fx_pcihost_info);
 495     pci_qdev_register_many(i440fx_info);
 496 }
 497 device_init(i440fx_register);