2 * QEMU PowerPC PowerNV machine model
4 * Copyright (c) 2016, IBM Corporation.
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "qemu/units.h"
23 #include "qapi/error.h"
24 #include "sysemu/qtest.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/numa.h"
27 #include "sysemu/reset.h"
28 #include "sysemu/runstate.h"
29 #include "sysemu/cpus.h"
30 #include "sysemu/device_tree.h"
31 #include "sysemu/hw_accel.h"
32 #include "target/ppc/cpu.h"
34 #include "hw/ppc/fdt.h"
35 #include "hw/ppc/ppc.h"
36 #include "hw/ppc/pnv.h"
37 #include "hw/ppc/pnv_core.h"
38 #include "hw/loader.h"
40 #include "exec/address-spaces.h"
41 #include "qapi/visitor.h"
42 #include "monitor/monitor.h"
43 #include "hw/intc/intc.h"
44 #include "hw/ipmi/ipmi.h"
45 #include "target/ppc/mmu-hash64.h"
46 #include "hw/pci/msi.h"
48 #include "hw/ppc/xics.h"
49 #include "hw/qdev-properties.h"
50 #include "hw/ppc/pnv_xscom.h"
51 #include "hw/ppc/pnv_pnor.h"
53 #include "hw/isa/isa.h"
54 #include "hw/boards.h"
55 #include "hw/char/serial.h"
56 #include "hw/rtc/mc146818rtc.h"
60 #define FDT_MAX_SIZE (1 * MiB)
62 #define FW_FILE_NAME "skiboot.lid"
63 #define FW_LOAD_ADDR 0x0
64 #define FW_MAX_SIZE (4 * MiB)
66 #define KERNEL_LOAD_ADDR 0x20000000
67 #define KERNEL_MAX_SIZE (256 * MiB)
68 #define INITRD_LOAD_ADDR 0x60000000
69 #define INITRD_MAX_SIZE (256 * MiB)
71 static const char *pnv_chip_core_typename(const PnvChip
*o
)
73 const char *chip_type
= object_class_get_name(object_get_class(OBJECT(o
)));
74 int len
= strlen(chip_type
) - strlen(PNV_CHIP_TYPE_SUFFIX
);
75 char *s
= g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len
, chip_type
);
76 const char *core_type
= object_class_get_name(object_class_by_name(s
));
82 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
83 * 4 * 4 sockets * 12 cores * 8 threads = 1536
89 * Memory nodes are created by hostboot, one for each range of memory
90 * that has a different "affinity". In practice, it means one range
93 static void pnv_dt_memory(void *fdt
, int chip_id
, hwaddr start
, hwaddr size
)
96 uint64_t mem_reg_property
[2];
99 mem_reg_property
[0] = cpu_to_be64(start
);
100 mem_reg_property
[1] = cpu_to_be64(size
);
102 mem_name
= g_strdup_printf("memory@%"HWADDR_PRIx
, start
);
103 off
= fdt_add_subnode(fdt
, 0, mem_name
);
106 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
107 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
108 sizeof(mem_reg_property
))));
109 _FDT((fdt_setprop_cell(fdt
, off
, "ibm,chip-id", chip_id
)));
112 static int get_cpus_node(void *fdt
)
114 int cpus_offset
= fdt_path_offset(fdt
, "/cpus");
116 if (cpus_offset
< 0) {
117 cpus_offset
= fdt_add_subnode(fdt
, 0, "cpus");
119 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#address-cells", 0x1)));
120 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#size-cells", 0x0)));
128 * The PowerNV cores (and threads) need to use real HW ids and not an
129 * incremental index like it has been done on other platforms. This HW
130 * id is stored in the CPU PIR, it is used to create cpu nodes in the
131 * device tree, used in XSCOM to address cores and in interrupt
134 static void pnv_dt_core(PnvChip
*chip
, PnvCore
*pc
, void *fdt
)
136 PowerPCCPU
*cpu
= pc
->threads
[0];
137 CPUState
*cs
= CPU(cpu
);
138 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
139 int smt_threads
= CPU_CORE(pc
)->nr_threads
;
140 CPUPPCState
*env
= &cpu
->env
;
141 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
142 uint32_t servers_prop
[smt_threads
];
144 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
145 0xffffffff, 0xffffffff};
146 uint32_t tbfreq
= PNV_TIMEBASE_FREQ
;
147 uint32_t cpufreq
= 1000000000;
148 uint32_t page_sizes_prop
[64];
149 size_t page_sizes_prop_size
;
150 const uint8_t pa_features
[] = { 24, 0,
151 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
152 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
153 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
154 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
157 int cpus_offset
= get_cpus_node(fdt
);
159 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, pc
->pir
);
160 offset
= fdt_add_subnode(fdt
, cpus_offset
, nodename
);
164 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,chip-id", chip
->chip_id
)));
166 _FDT((fdt_setprop_cell(fdt
, offset
, "reg", pc
->pir
)));
167 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,pir", pc
->pir
)));
168 _FDT((fdt_setprop_string(fdt
, offset
, "device_type", "cpu")));
170 _FDT((fdt_setprop_cell(fdt
, offset
, "cpu-version", env
->spr
[SPR_PVR
])));
171 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-block-size",
172 env
->dcache_line_size
)));
173 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-line-size",
174 env
->dcache_line_size
)));
175 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-block-size",
176 env
->icache_line_size
)));
177 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-line-size",
178 env
->icache_line_size
)));
180 if (pcc
->l1_dcache_size
) {
181 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-size",
182 pcc
->l1_dcache_size
)));
184 warn_report("Unknown L1 dcache size for cpu");
186 if (pcc
->l1_icache_size
) {
187 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-size",
188 pcc
->l1_icache_size
)));
190 warn_report("Unknown L1 icache size for cpu");
193 _FDT((fdt_setprop_cell(fdt
, offset
, "timebase-frequency", tbfreq
)));
194 _FDT((fdt_setprop_cell(fdt
, offset
, "clock-frequency", cpufreq
)));
195 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,slb-size",
196 cpu
->hash64_opts
->slb_size
)));
197 _FDT((fdt_setprop_string(fdt
, offset
, "status", "okay")));
198 _FDT((fdt_setprop(fdt
, offset
, "64-bit", NULL
, 0)));
200 if (env
->spr_cb
[SPR_PURR
].oea_read
) {
201 _FDT((fdt_setprop(fdt
, offset
, "ibm,purr", NULL
, 0)));
204 if (ppc_hash64_has(cpu
, PPC_HASH64_1TSEG
)) {
205 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-segment-sizes",
206 segs
, sizeof(segs
))));
210 * Advertise VMX/VSX (vector extensions) if available
211 * 0 / no property == no vector extensions
212 * 1 == VMX / Altivec available
215 if (env
->insns_flags
& PPC_ALTIVEC
) {
216 uint32_t vmx
= (env
->insns_flags2
& PPC2_VSX
) ? 2 : 1;
218 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", vmx
)));
222 * Advertise DFP (Decimal Floating Point) if available
223 * 0 / no property == no DFP
226 if (env
->insns_flags2
& PPC2_DFP
) {
227 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,dfp", 1)));
230 page_sizes_prop_size
= ppc_create_page_sizes_prop(cpu
, page_sizes_prop
,
231 sizeof(page_sizes_prop
));
232 if (page_sizes_prop_size
) {
233 _FDT((fdt_setprop(fdt
, offset
, "ibm,segment-page-sizes",
234 page_sizes_prop
, page_sizes_prop_size
)));
237 _FDT((fdt_setprop(fdt
, offset
, "ibm,pa-features",
238 pa_features
, sizeof(pa_features
))));
240 /* Build interrupt servers properties */
241 for (i
= 0; i
< smt_threads
; i
++) {
242 servers_prop
[i
] = cpu_to_be32(pc
->pir
+ i
);
244 _FDT((fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-server#s",
245 servers_prop
, sizeof(servers_prop
))));
248 static void pnv_dt_icp(PnvChip
*chip
, void *fdt
, uint32_t pir
,
251 uint64_t addr
= PNV_ICP_BASE(chip
) | (pir
<< 12);
253 const char compat
[] = "IBM,power8-icp\0IBM,ppc-xicp";
254 uint32_t irange
[2], i
, rsize
;
258 irange
[0] = cpu_to_be32(pir
);
259 irange
[1] = cpu_to_be32(nr_threads
);
261 rsize
= sizeof(uint64_t) * 2 * nr_threads
;
262 reg
= g_malloc(rsize
);
263 for (i
= 0; i
< nr_threads
; i
++) {
264 reg
[i
* 2] = cpu_to_be64(addr
| ((pir
+ i
) * 0x1000));
265 reg
[i
* 2 + 1] = cpu_to_be64(0x1000);
268 name
= g_strdup_printf("interrupt-controller@%"PRIX64
, addr
);
269 offset
= fdt_add_subnode(fdt
, 0, name
);
273 _FDT((fdt_setprop(fdt
, offset
, "compatible", compat
, sizeof(compat
))));
274 _FDT((fdt_setprop(fdt
, offset
, "reg", reg
, rsize
)));
275 _FDT((fdt_setprop_string(fdt
, offset
, "device_type",
276 "PowerPC-External-Interrupt-Presentation")));
277 _FDT((fdt_setprop(fdt
, offset
, "interrupt-controller", NULL
, 0)));
278 _FDT((fdt_setprop(fdt
, offset
, "ibm,interrupt-server-ranges",
279 irange
, sizeof(irange
))));
280 _FDT((fdt_setprop_cell(fdt
, offset
, "#interrupt-cells", 1)));
281 _FDT((fdt_setprop_cell(fdt
, offset
, "#address-cells", 0)));
285 static void pnv_chip_power8_dt_populate(PnvChip
*chip
, void *fdt
)
287 static const char compat
[] = "ibm,power8-xscom\0ibm,xscom";
290 pnv_dt_xscom(chip
, fdt
, 0,
291 cpu_to_be64(PNV_XSCOM_BASE(chip
)),
292 cpu_to_be64(PNV_XSCOM_SIZE
),
293 compat
, sizeof(compat
));
295 for (i
= 0; i
< chip
->nr_cores
; i
++) {
296 PnvCore
*pnv_core
= chip
->cores
[i
];
298 pnv_dt_core(chip
, pnv_core
, fdt
);
300 /* Interrupt Control Presenters (ICP). One per core. */
301 pnv_dt_icp(chip
, fdt
, pnv_core
->pir
, CPU_CORE(pnv_core
)->nr_threads
);
304 if (chip
->ram_size
) {
305 pnv_dt_memory(fdt
, chip
->chip_id
, chip
->ram_start
, chip
->ram_size
);
309 static void pnv_chip_power9_dt_populate(PnvChip
*chip
, void *fdt
)
311 static const char compat
[] = "ibm,power9-xscom\0ibm,xscom";
314 pnv_dt_xscom(chip
, fdt
, 0,
315 cpu_to_be64(PNV9_XSCOM_BASE(chip
)),
316 cpu_to_be64(PNV9_XSCOM_SIZE
),
317 compat
, sizeof(compat
));
319 for (i
= 0; i
< chip
->nr_cores
; i
++) {
320 PnvCore
*pnv_core
= chip
->cores
[i
];
322 pnv_dt_core(chip
, pnv_core
, fdt
);
325 if (chip
->ram_size
) {
326 pnv_dt_memory(fdt
, chip
->chip_id
, chip
->ram_start
, chip
->ram_size
);
329 pnv_dt_lpc(chip
, fdt
, 0, PNV9_LPCM_BASE(chip
), PNV9_LPCM_SIZE
);
332 static void pnv_chip_power10_dt_populate(PnvChip
*chip
, void *fdt
)
334 static const char compat
[] = "ibm,power10-xscom\0ibm,xscom";
337 pnv_dt_xscom(chip
, fdt
, 0,
338 cpu_to_be64(PNV10_XSCOM_BASE(chip
)),
339 cpu_to_be64(PNV10_XSCOM_SIZE
),
340 compat
, sizeof(compat
));
342 for (i
= 0; i
< chip
->nr_cores
; i
++) {
343 PnvCore
*pnv_core
= chip
->cores
[i
];
345 pnv_dt_core(chip
, pnv_core
, fdt
);
348 if (chip
->ram_size
) {
349 pnv_dt_memory(fdt
, chip
->chip_id
, chip
->ram_start
, chip
->ram_size
);
352 pnv_dt_lpc(chip
, fdt
, 0, PNV10_LPCM_BASE(chip
), PNV10_LPCM_SIZE
);
355 static void pnv_dt_rtc(ISADevice
*d
, void *fdt
, int lpc_off
)
357 uint32_t io_base
= d
->ioport_id
;
358 uint32_t io_regs
[] = {
360 cpu_to_be32(io_base
),
366 name
= g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d
)), io_base
);
367 node
= fdt_add_subnode(fdt
, lpc_off
, name
);
371 _FDT((fdt_setprop(fdt
, node
, "reg", io_regs
, sizeof(io_regs
))));
372 _FDT((fdt_setprop_string(fdt
, node
, "compatible", "pnpPNP,b00")));
375 static void pnv_dt_serial(ISADevice
*d
, void *fdt
, int lpc_off
)
377 const char compatible
[] = "ns16550\0pnpPNP,501";
378 uint32_t io_base
= d
->ioport_id
;
379 uint32_t io_regs
[] = {
381 cpu_to_be32(io_base
),
387 name
= g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d
)), io_base
);
388 node
= fdt_add_subnode(fdt
, lpc_off
, name
);
392 _FDT((fdt_setprop(fdt
, node
, "reg", io_regs
, sizeof(io_regs
))));
393 _FDT((fdt_setprop(fdt
, node
, "compatible", compatible
,
394 sizeof(compatible
))));
396 _FDT((fdt_setprop_cell(fdt
, node
, "clock-frequency", 1843200)));
397 _FDT((fdt_setprop_cell(fdt
, node
, "current-speed", 115200)));
398 _FDT((fdt_setprop_cell(fdt
, node
, "interrupts", d
->isairq
[0])));
399 _FDT((fdt_setprop_cell(fdt
, node
, "interrupt-parent",
400 fdt_get_phandle(fdt
, lpc_off
))));
402 /* This is needed by Linux */
403 _FDT((fdt_setprop_string(fdt
, node
, "device_type", "serial")));
406 static void pnv_dt_ipmi_bt(ISADevice
*d
, void *fdt
, int lpc_off
)
408 const char compatible
[] = "bt\0ipmi-bt";
410 uint32_t io_regs
[] = {
412 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
419 io_base
= object_property_get_int(OBJECT(d
), "ioport", &error_fatal
);
420 io_regs
[1] = cpu_to_be32(io_base
);
422 irq
= object_property_get_int(OBJECT(d
), "irq", &error_fatal
);
424 name
= g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d
)), io_base
);
425 node
= fdt_add_subnode(fdt
, lpc_off
, name
);
429 _FDT((fdt_setprop(fdt
, node
, "reg", io_regs
, sizeof(io_regs
))));
430 _FDT((fdt_setprop(fdt
, node
, "compatible", compatible
,
431 sizeof(compatible
))));
433 /* Mark it as reserved to avoid Linux trying to claim it */
434 _FDT((fdt_setprop_string(fdt
, node
, "status", "reserved")));
435 _FDT((fdt_setprop_cell(fdt
, node
, "interrupts", irq
)));
436 _FDT((fdt_setprop_cell(fdt
, node
, "interrupt-parent",
437 fdt_get_phandle(fdt
, lpc_off
))));
440 typedef struct ForeachPopulateArgs
{
443 } ForeachPopulateArgs
;
445 static int pnv_dt_isa_device(DeviceState
*dev
, void *opaque
)
447 ForeachPopulateArgs
*args
= opaque
;
448 ISADevice
*d
= ISA_DEVICE(dev
);
450 if (object_dynamic_cast(OBJECT(dev
), TYPE_MC146818_RTC
)) {
451 pnv_dt_rtc(d
, args
->fdt
, args
->offset
);
452 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_ISA_SERIAL
)) {
453 pnv_dt_serial(d
, args
->fdt
, args
->offset
);
454 } else if (object_dynamic_cast(OBJECT(dev
), "isa-ipmi-bt")) {
455 pnv_dt_ipmi_bt(d
, args
->fdt
, args
->offset
);
457 error_report("unknown isa device %s@i%x", qdev_fw_name(dev
),
465 * The default LPC bus of a multichip system is on chip 0. It's
466 * recognized by the firmware (skiboot) using a "primary" property.
468 static void pnv_dt_isa(PnvMachineState
*pnv
, void *fdt
)
470 int isa_offset
= fdt_path_offset(fdt
, pnv
->chips
[0]->dt_isa_nodename
);
471 ForeachPopulateArgs args
= {
473 .offset
= isa_offset
,
477 _FDT((fdt_setprop(fdt
, isa_offset
, "primary", NULL
, 0)));
479 phandle
= qemu_fdt_alloc_phandle(fdt
);
481 _FDT((fdt_setprop_cell(fdt
, isa_offset
, "phandle", phandle
)));
484 * ISA devices are not necessarily parented to the ISA bus so we
485 * can not use object_child_foreach()
487 qbus_walk_children(BUS(pnv
->isa_bus
), pnv_dt_isa_device
, NULL
, NULL
, NULL
,
491 static void pnv_dt_power_mgt(PnvMachineState
*pnv
, void *fdt
)
495 off
= fdt_add_subnode(fdt
, 0, "ibm,opal");
496 off
= fdt_add_subnode(fdt
, off
, "power-mgt");
498 _FDT(fdt_setprop_cell(fdt
, off
, "ibm,enabled-stop-levels", 0xc0000000));
501 static void *pnv_dt_create(MachineState
*machine
)
503 PnvMachineClass
*pmc
= PNV_MACHINE_GET_CLASS(machine
);
504 PnvMachineState
*pnv
= PNV_MACHINE(machine
);
510 fdt
= g_malloc0(FDT_MAX_SIZE
);
511 _FDT((fdt_create_empty_tree(fdt
, FDT_MAX_SIZE
)));
514 _FDT((fdt_add_subnode(fdt
, 0, "qemu")));
517 _FDT((fdt_setprop_cell(fdt
, 0, "#address-cells", 0x2)));
518 _FDT((fdt_setprop_cell(fdt
, 0, "#size-cells", 0x2)));
519 _FDT((fdt_setprop_string(fdt
, 0, "model",
520 "IBM PowerNV (emulated by qemu)")));
521 _FDT((fdt_setprop(fdt
, 0, "compatible", pmc
->compat
, pmc
->compat_size
)));
523 buf
= qemu_uuid_unparse_strdup(&qemu_uuid
);
524 _FDT((fdt_setprop_string(fdt
, 0, "vm,uuid", buf
)));
526 _FDT((fdt_property_string(fdt
, "system-id", buf
)));
530 off
= fdt_add_subnode(fdt
, 0, "chosen");
531 if (machine
->kernel_cmdline
) {
532 _FDT((fdt_setprop_string(fdt
, off
, "bootargs",
533 machine
->kernel_cmdline
)));
536 if (pnv
->initrd_size
) {
537 uint32_t start_prop
= cpu_to_be32(pnv
->initrd_base
);
538 uint32_t end_prop
= cpu_to_be32(pnv
->initrd_base
+ pnv
->initrd_size
);
540 _FDT((fdt_setprop(fdt
, off
, "linux,initrd-start",
541 &start_prop
, sizeof(start_prop
))));
542 _FDT((fdt_setprop(fdt
, off
, "linux,initrd-end",
543 &end_prop
, sizeof(end_prop
))));
546 /* Populate device tree for each chip */
547 for (i
= 0; i
< pnv
->num_chips
; i
++) {
548 PNV_CHIP_GET_CLASS(pnv
->chips
[i
])->dt_populate(pnv
->chips
[i
], fdt
);
551 /* Populate ISA devices on chip 0 */
552 pnv_dt_isa(pnv
, fdt
);
555 pnv_dt_bmc_sensors(pnv
->bmc
, fdt
);
558 /* Create an extra node for power management on machines that support it */
559 if (pmc
->dt_power_mgt
) {
560 pmc
->dt_power_mgt(pnv
, fdt
);
566 static void pnv_powerdown_notify(Notifier
*n
, void *opaque
)
568 PnvMachineState
*pnv
= container_of(n
, PnvMachineState
, powerdown_notifier
);
571 pnv_bmc_powerdown(pnv
->bmc
);
575 static void pnv_reset(MachineState
*machine
)
577 PnvMachineState
*pnv
= PNV_MACHINE(machine
);
581 qemu_devices_reset();
584 * The machine should provide by default an internal BMC simulator.
585 * If not, try to use the BMC device that was provided on the command
588 bmc
= pnv_bmc_find(&error_fatal
);
591 if (!qtest_enabled()) {
592 warn_report("machine has no BMC device. Use '-device "
593 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' "
597 pnv_bmc_set_pnor(bmc
, pnv
->pnor
);
602 fdt
= pnv_dt_create(machine
);
604 /* Pack resulting tree */
605 _FDT((fdt_pack(fdt
)));
607 qemu_fdt_dumpdtb(fdt
, fdt_totalsize(fdt
));
608 cpu_physical_memory_write(PNV_FDT_ADDR
, fdt
, fdt_totalsize(fdt
));
613 static ISABus
*pnv_chip_power8_isa_create(PnvChip
*chip
, Error
**errp
)
615 Pnv8Chip
*chip8
= PNV8_CHIP(chip
);
616 return pnv_lpc_isa_create(&chip8
->lpc
, true, errp
);
619 static ISABus
*pnv_chip_power8nvl_isa_create(PnvChip
*chip
, Error
**errp
)
621 Pnv8Chip
*chip8
= PNV8_CHIP(chip
);
622 return pnv_lpc_isa_create(&chip8
->lpc
, false, errp
);
625 static ISABus
*pnv_chip_power9_isa_create(PnvChip
*chip
, Error
**errp
)
627 Pnv9Chip
*chip9
= PNV9_CHIP(chip
);
628 return pnv_lpc_isa_create(&chip9
->lpc
, false, errp
);
631 static ISABus
*pnv_chip_power10_isa_create(PnvChip
*chip
, Error
**errp
)
633 Pnv10Chip
*chip10
= PNV10_CHIP(chip
);
634 return pnv_lpc_isa_create(&chip10
->lpc
, false, errp
);
637 static ISABus
*pnv_isa_create(PnvChip
*chip
, Error
**errp
)
639 return PNV_CHIP_GET_CLASS(chip
)->isa_create(chip
, errp
);
642 static void pnv_chip_power8_pic_print_info(PnvChip
*chip
, Monitor
*mon
)
644 Pnv8Chip
*chip8
= PNV8_CHIP(chip
);
647 ics_pic_print_info(&chip8
->psi
.ics
, mon
);
648 for (i
= 0; i
< chip
->num_phbs
; i
++) {
649 pnv_phb3_msi_pic_print_info(&chip8
->phbs
[i
].msis
, mon
);
650 ics_pic_print_info(&chip8
->phbs
[i
].lsis
, mon
);
654 static void pnv_chip_power9_pic_print_info(PnvChip
*chip
, Monitor
*mon
)
656 Pnv9Chip
*chip9
= PNV9_CHIP(chip
);
659 pnv_xive_pic_print_info(&chip9
->xive
, mon
);
660 pnv_psi_pic_print_info(&chip9
->psi
, mon
);
662 for (i
= 0; i
< PNV9_CHIP_MAX_PEC
; i
++) {
663 PnvPhb4PecState
*pec
= &chip9
->pecs
[i
];
664 for (j
= 0; j
< pec
->num_stacks
; j
++) {
665 pnv_phb4_pic_print_info(&pec
->stacks
[j
].phb
, mon
);
670 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip
*chip
,
673 return PNV_XSCOM_EX_BASE(core_id
);
676 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip
*chip
,
679 return PNV9_XSCOM_EC_BASE(core_id
);
682 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip
*chip
,
685 return PNV10_XSCOM_EC_BASE(core_id
);
688 static bool pnv_match_cpu(const char *default_type
, const char *cpu_type
)
690 PowerPCCPUClass
*ppc_default
=
691 POWERPC_CPU_CLASS(object_class_by_name(default_type
));
692 PowerPCCPUClass
*ppc
=
693 POWERPC_CPU_CLASS(object_class_by_name(cpu_type
));
695 return ppc_default
->pvr_match(ppc_default
, ppc
->pvr
);
698 static void pnv_ipmi_bt_init(ISABus
*bus
, IPMIBmc
*bmc
, uint32_t irq
)
700 ISADevice
*dev
= isa_new("isa-ipmi-bt");
702 object_property_set_link(OBJECT(dev
), "bmc", OBJECT(bmc
), &error_fatal
);
703 object_property_set_int(OBJECT(dev
), "irq", irq
, &error_fatal
);
704 isa_realize_and_unref(dev
, bus
, &error_fatal
);
707 static void pnv_chip_power10_pic_print_info(PnvChip
*chip
, Monitor
*mon
)
709 Pnv10Chip
*chip10
= PNV10_CHIP(chip
);
711 pnv_psi_pic_print_info(&chip10
->psi
, mon
);
714 static void pnv_init(MachineState
*machine
)
716 PnvMachineState
*pnv
= PNV_MACHINE(machine
);
717 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
722 DriveInfo
*pnor
= drive_get(IF_MTD
, 0, 0);
726 if (machine
->ram_size
< (1 * GiB
)) {
727 warn_report("skiboot may not work with < 1GB of RAM");
729 memory_region_add_subregion(get_system_memory(), 0, machine
->ram
);
732 * Create our simple PNOR device
734 dev
= qdev_new(TYPE_PNV_PNOR
);
736 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(pnor
));
738 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
739 pnv
->pnor
= PNV_PNOR(dev
);
741 /* load skiboot firmware */
742 if (bios_name
== NULL
) {
743 bios_name
= FW_FILE_NAME
;
746 fw_filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
748 error_report("Could not find OPAL firmware '%s'", bios_name
);
752 fw_size
= load_image_targphys(fw_filename
, pnv
->fw_load_addr
, FW_MAX_SIZE
);
754 error_report("Could not load OPAL firmware '%s'", fw_filename
);
760 if (machine
->kernel_filename
) {
763 kernel_size
= load_image_targphys(machine
->kernel_filename
,
764 KERNEL_LOAD_ADDR
, KERNEL_MAX_SIZE
);
765 if (kernel_size
< 0) {
766 error_report("Could not load kernel '%s'",
767 machine
->kernel_filename
);
773 if (machine
->initrd_filename
) {
774 pnv
->initrd_base
= INITRD_LOAD_ADDR
;
775 pnv
->initrd_size
= load_image_targphys(machine
->initrd_filename
,
776 pnv
->initrd_base
, INITRD_MAX_SIZE
);
777 if (pnv
->initrd_size
< 0) {
778 error_report("Could not load initial ram disk '%s'",
779 machine
->initrd_filename
);
784 /* MSIs are supported on this platform */
785 msi_nonbroken
= true;
788 * Check compatibility of the specified CPU with the machine
791 if (!pnv_match_cpu(mc
->default_cpu_type
, machine
->cpu_type
)) {
792 error_report("invalid CPU model '%s' for %s machine",
793 machine
->cpu_type
, mc
->name
);
797 /* Create the processor chips */
798 i
= strlen(machine
->cpu_type
) - strlen(POWERPC_CPU_TYPE_SUFFIX
);
799 chip_typename
= g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
800 i
, machine
->cpu_type
);
801 if (!object_class_by_name(chip_typename
)) {
802 error_report("invalid chip model '%.*s' for %s machine",
803 i
, machine
->cpu_type
, mc
->name
);
808 machine
->smp
.max_cpus
/ (machine
->smp
.cores
* machine
->smp
.threads
);
810 * TODO: should we decide on how many chips we can create based
811 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
813 if (!is_power_of_2(pnv
->num_chips
) || pnv
->num_chips
> 4) {
814 error_report("invalid number of chips: '%d'", pnv
->num_chips
);
815 error_printf("Try '-smp sockets=N'. Valid values are : 1, 2 or 4.\n");
819 pnv
->chips
= g_new0(PnvChip
*, pnv
->num_chips
);
820 for (i
= 0; i
< pnv
->num_chips
; i
++) {
822 Object
*chip
= OBJECT(qdev_new(chip_typename
));
824 pnv
->chips
[i
] = PNV_CHIP(chip
);
827 * TODO: put all the memory in one node on chip 0 until we find a
828 * way to specify different ranges for each chip
831 object_property_set_int(chip
, "ram-size", machine
->ram_size
,
835 snprintf(chip_name
, sizeof(chip_name
), "chip[%d]", PNV_CHIP_HWID(i
));
836 object_property_add_child(OBJECT(pnv
), chip_name
, chip
);
837 object_property_set_int(chip
, "chip-id", PNV_CHIP_HWID(i
),
839 object_property_set_int(chip
, "nr-cores", machine
->smp
.cores
,
841 object_property_set_int(chip
, "nr-threads", machine
->smp
.threads
,
844 * The POWER8 machine use the XICS interrupt interface.
845 * Propagate the XICS fabric to the chip and its controllers.
847 if (object_dynamic_cast(OBJECT(pnv
), TYPE_XICS_FABRIC
)) {
848 object_property_set_link(chip
, "xics", OBJECT(pnv
), &error_abort
);
850 if (object_dynamic_cast(OBJECT(pnv
), TYPE_XIVE_FABRIC
)) {
851 object_property_set_link(chip
, "xive-fabric", OBJECT(pnv
),
854 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip
), &error_fatal
);
856 g_free(chip_typename
);
858 /* Instantiate ISA bus on chip 0 */
859 pnv
->isa_bus
= pnv_isa_create(pnv
->chips
[0], &error_fatal
);
861 /* Create serial port */
862 serial_hds_isa_init(pnv
->isa_bus
, 0, MAX_ISA_SERIAL_PORTS
);
864 /* Create an RTC ISA device too */
865 mc146818_rtc_init(pnv
->isa_bus
, 2000, NULL
);
868 * Create the machine BMC simulator and the IPMI BT device for
869 * communication with the BMC
871 if (defaults_enabled()) {
872 pnv
->bmc
= pnv_bmc_create(pnv
->pnor
);
873 pnv_ipmi_bt_init(pnv
->isa_bus
, pnv
->bmc
, 10);
877 * OpenPOWER systems use a IPMI SEL Event message to notify the
880 pnv
->powerdown_notifier
.notify
= pnv_powerdown_notify
;
881 qemu_register_powerdown_notifier(&pnv
->powerdown_notifier
);
885 * 0:21 Reserved - Read as zeros
890 static uint32_t pnv_chip_core_pir_p8(PnvChip
*chip
, uint32_t core_id
)
892 return (chip
->chip_id
<< 7) | (core_id
<< 3);
895 static void pnv_chip_power8_intc_create(PnvChip
*chip
, PowerPCCPU
*cpu
,
898 Pnv8Chip
*chip8
= PNV8_CHIP(chip
);
899 Error
*local_err
= NULL
;
901 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
903 obj
= icp_create(OBJECT(cpu
), TYPE_PNV_ICP
, chip8
->xics
, &local_err
);
905 error_propagate(errp
, local_err
);
913 static void pnv_chip_power8_intc_reset(PnvChip
*chip
, PowerPCCPU
*cpu
)
915 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
917 icp_reset(ICP(pnv_cpu
->intc
));
920 static void pnv_chip_power8_intc_destroy(PnvChip
*chip
, PowerPCCPU
*cpu
)
922 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
924 icp_destroy(ICP(pnv_cpu
->intc
));
925 pnv_cpu
->intc
= NULL
;
928 static void pnv_chip_power8_intc_print_info(PnvChip
*chip
, PowerPCCPU
*cpu
,
931 icp_pic_print_info(ICP(pnv_cpu_state(cpu
)->intc
), mon
);
935 * 0:48 Reserved - Read as zeroes
938 * 56 Reserved - Read as zero
942 * We only care about the lower bits. uint32_t is fine for the moment.
944 static uint32_t pnv_chip_core_pir_p9(PnvChip
*chip
, uint32_t core_id
)
946 return (chip
->chip_id
<< 8) | (core_id
<< 2);
949 static uint32_t pnv_chip_core_pir_p10(PnvChip
*chip
, uint32_t core_id
)
951 return (chip
->chip_id
<< 8) | (core_id
<< 2);
954 static void pnv_chip_power9_intc_create(PnvChip
*chip
, PowerPCCPU
*cpu
,
957 Pnv9Chip
*chip9
= PNV9_CHIP(chip
);
958 Error
*local_err
= NULL
;
960 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
963 * The core creates its interrupt presenter but the XIVE interrupt
964 * controller object is initialized afterwards. Hopefully, it's
965 * only used at runtime.
967 obj
= xive_tctx_create(OBJECT(cpu
), XIVE_PRESENTER(&chip9
->xive
),
970 error_propagate(errp
, local_err
);
977 static void pnv_chip_power9_intc_reset(PnvChip
*chip
, PowerPCCPU
*cpu
)
979 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
981 xive_tctx_reset(XIVE_TCTX(pnv_cpu
->intc
));
984 static void pnv_chip_power9_intc_destroy(PnvChip
*chip
, PowerPCCPU
*cpu
)
986 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
988 xive_tctx_destroy(XIVE_TCTX(pnv_cpu
->intc
));
989 pnv_cpu
->intc
= NULL
;
992 static void pnv_chip_power9_intc_print_info(PnvChip
*chip
, PowerPCCPU
*cpu
,
995 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu
)->intc
), mon
);
998 static void pnv_chip_power10_intc_create(PnvChip
*chip
, PowerPCCPU
*cpu
,
1001 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
1003 /* Will be defined when the interrupt controller is */
1004 pnv_cpu
->intc
= NULL
;
1007 static void pnv_chip_power10_intc_reset(PnvChip
*chip
, PowerPCCPU
*cpu
)
1012 static void pnv_chip_power10_intc_destroy(PnvChip
*chip
, PowerPCCPU
*cpu
)
1014 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
1016 pnv_cpu
->intc
= NULL
;
1019 static void pnv_chip_power10_intc_print_info(PnvChip
*chip
, PowerPCCPU
*cpu
,
1025 * Allowed core identifiers on a POWER8 Processor Chip :
1034 * <EX7,8 reserved> <reserved>
1036 * EX10 - Venice only
1037 * EX11 - Venice only
1043 #define POWER8E_CORE_MASK (0x7070ull)
1044 #define POWER8_CORE_MASK (0x7e7eull)
1047 * POWER9 has 24 cores, ids starting at 0x0
1049 #define POWER9_CORE_MASK (0xffffffffffffffull)
1052 #define POWER10_CORE_MASK (0xffffffffffffffull)
1054 static void pnv_chip_power8_instance_init(Object
*obj
)
1056 PnvChip
*chip
= PNV_CHIP(obj
);
1057 Pnv8Chip
*chip8
= PNV8_CHIP(obj
);
1058 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(obj
);
1061 object_property_add_link(obj
, "xics", TYPE_XICS_FABRIC
,
1062 (Object
**)&chip8
->xics
,
1063 object_property_allow_set_link
,
1064 OBJ_PROP_LINK_STRONG
);
1066 object_initialize_child(obj
, "psi", &chip8
->psi
, TYPE_PNV8_PSI
);
1068 object_initialize_child(obj
, "lpc", &chip8
->lpc
, TYPE_PNV8_LPC
);
1070 object_initialize_child(obj
, "occ", &chip8
->occ
, TYPE_PNV8_OCC
);
1072 object_initialize_child(obj
, "homer", &chip8
->homer
, TYPE_PNV8_HOMER
);
1074 for (i
= 0; i
< pcc
->num_phbs
; i
++) {
1075 object_initialize_child(obj
, "phb[*]", &chip8
->phbs
[i
], TYPE_PNV_PHB3
);
1079 * Number of PHBs is the chip default
1081 chip
->num_phbs
= pcc
->num_phbs
;
1084 static void pnv_chip_icp_realize(Pnv8Chip
*chip8
, Error
**errp
)
1086 PnvChip
*chip
= PNV_CHIP(chip8
);
1087 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
1091 name
= g_strdup_printf("icp-%x", chip
->chip_id
);
1092 memory_region_init(&chip8
->icp_mmio
, OBJECT(chip
), name
, PNV_ICP_SIZE
);
1093 sysbus_init_mmio(SYS_BUS_DEVICE(chip
), &chip8
->icp_mmio
);
1096 sysbus_mmio_map(SYS_BUS_DEVICE(chip
), 1, PNV_ICP_BASE(chip
));
1098 /* Map the ICP registers for each thread */
1099 for (i
= 0; i
< chip
->nr_cores
; i
++) {
1100 PnvCore
*pnv_core
= chip
->cores
[i
];
1101 int core_hwid
= CPU_CORE(pnv_core
)->core_id
;
1103 for (j
= 0; j
< CPU_CORE(pnv_core
)->nr_threads
; j
++) {
1104 uint32_t pir
= pcc
->core_pir(chip
, core_hwid
) + j
;
1105 PnvICPState
*icp
= PNV_ICP(xics_icp_get(chip8
->xics
, pir
));
1107 memory_region_add_subregion(&chip8
->icp_mmio
, pir
<< 12,
1113 static void pnv_chip_power8_realize(DeviceState
*dev
, Error
**errp
)
1115 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(dev
);
1116 PnvChip
*chip
= PNV_CHIP(dev
);
1117 Pnv8Chip
*chip8
= PNV8_CHIP(dev
);
1118 Pnv8Psi
*psi8
= &chip8
->psi
;
1119 Error
*local_err
= NULL
;
1122 assert(chip8
->xics
);
1124 /* XSCOM bridge is first */
1125 pnv_xscom_realize(chip
, PNV_XSCOM_SIZE
, &local_err
);
1127 error_propagate(errp
, local_err
);
1130 sysbus_mmio_map(SYS_BUS_DEVICE(chip
), 0, PNV_XSCOM_BASE(chip
));
1132 pcc
->parent_realize(dev
, &local_err
);
1134 error_propagate(errp
, local_err
);
1138 /* Processor Service Interface (PSI) Host Bridge */
1139 object_property_set_int(OBJECT(&chip8
->psi
), "bar", PNV_PSIHB_BASE(chip
),
1141 object_property_set_link(OBJECT(&chip8
->psi
), ICS_PROP_XICS
,
1142 OBJECT(chip8
->xics
), &error_abort
);
1143 if (!qdev_realize(DEVICE(&chip8
->psi
), NULL
, &local_err
)) {
1144 error_propagate(errp
, local_err
);
1147 pnv_xscom_add_subregion(chip
, PNV_XSCOM_PSIHB_BASE
,
1148 &PNV_PSI(psi8
)->xscom_regs
);
1150 /* Create LPC controller */
1151 object_property_set_link(OBJECT(&chip8
->lpc
), "psi", OBJECT(&chip8
->psi
),
1153 qdev_realize(DEVICE(&chip8
->lpc
), NULL
, &error_fatal
);
1154 pnv_xscom_add_subregion(chip
, PNV_XSCOM_LPC_BASE
, &chip8
->lpc
.xscom_regs
);
1156 chip
->dt_isa_nodename
= g_strdup_printf("/xscom@%" PRIx64
"/isa@%x",
1157 (uint64_t) PNV_XSCOM_BASE(chip
),
1158 PNV_XSCOM_LPC_BASE
);
1161 * Interrupt Management Area. This is the memory region holding
1162 * all the Interrupt Control Presenter (ICP) registers
1164 pnv_chip_icp_realize(chip8
, &local_err
);
1166 error_propagate(errp
, local_err
);
1170 /* Create the simplified OCC model */
1171 object_property_set_link(OBJECT(&chip8
->occ
), "psi", OBJECT(&chip8
->psi
),
1173 if (!qdev_realize(DEVICE(&chip8
->occ
), NULL
, &local_err
)) {
1174 error_propagate(errp
, local_err
);
1177 pnv_xscom_add_subregion(chip
, PNV_XSCOM_OCC_BASE
, &chip8
->occ
.xscom_regs
);
1179 /* OCC SRAM model */
1180 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip
),
1181 &chip8
->occ
.sram_regs
);
1184 object_property_set_link(OBJECT(&chip8
->homer
), "chip", OBJECT(chip
),
1186 if (!qdev_realize(DEVICE(&chip8
->homer
), NULL
, &local_err
)) {
1187 error_propagate(errp
, local_err
);
1190 /* Homer Xscom region */
1191 pnv_xscom_add_subregion(chip
, PNV_XSCOM_PBA_BASE
, &chip8
->homer
.pba_regs
);
1193 /* Homer mmio region */
1194 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip
),
1195 &chip8
->homer
.regs
);
1197 /* PHB3 controllers */
1198 for (i
= 0; i
< chip
->num_phbs
; i
++) {
1199 PnvPHB3
*phb
= &chip8
->phbs
[i
];
1200 PnvPBCQState
*pbcq
= &phb
->pbcq
;
1202 object_property_set_int(OBJECT(phb
), "index", i
, &error_fatal
);
1203 object_property_set_int(OBJECT(phb
), "chip-id", chip
->chip_id
,
1205 if (!sysbus_realize(SYS_BUS_DEVICE(phb
), &local_err
)) {
1206 error_propagate(errp
, local_err
);
1210 /* Populate the XSCOM address space. */
1211 pnv_xscom_add_subregion(chip
,
1212 PNV_XSCOM_PBCQ_NEST_BASE
+ 0x400 * phb
->phb_id
,
1213 &pbcq
->xscom_nest_regs
);
1214 pnv_xscom_add_subregion(chip
,
1215 PNV_XSCOM_PBCQ_PCI_BASE
+ 0x400 * phb
->phb_id
,
1216 &pbcq
->xscom_pci_regs
);
1217 pnv_xscom_add_subregion(chip
,
1218 PNV_XSCOM_PBCQ_SPCI_BASE
+ 0x040 * phb
->phb_id
,
1219 &pbcq
->xscom_spci_regs
);
1223 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip
*chip
, uint64_t addr
)
1225 addr
&= (PNV_XSCOM_SIZE
- 1);
1226 return ((addr
>> 4) & ~0xfull
) | ((addr
>> 3) & 0xf);
1229 static void pnv_chip_power8e_class_init(ObjectClass
*klass
, void *data
)
1231 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1232 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1234 k
->chip_cfam_id
= 0x221ef04980000000ull
; /* P8 Murano DD2.1 */
1235 k
->cores_mask
= POWER8E_CORE_MASK
;
1237 k
->core_pir
= pnv_chip_core_pir_p8
;
1238 k
->intc_create
= pnv_chip_power8_intc_create
;
1239 k
->intc_reset
= pnv_chip_power8_intc_reset
;
1240 k
->intc_destroy
= pnv_chip_power8_intc_destroy
;
1241 k
->intc_print_info
= pnv_chip_power8_intc_print_info
;
1242 k
->isa_create
= pnv_chip_power8_isa_create
;
1243 k
->dt_populate
= pnv_chip_power8_dt_populate
;
1244 k
->pic_print_info
= pnv_chip_power8_pic_print_info
;
1245 k
->xscom_core_base
= pnv_chip_power8_xscom_core_base
;
1246 k
->xscom_pcba
= pnv_chip_power8_xscom_pcba
;
1247 dc
->desc
= "PowerNV Chip POWER8E";
1249 device_class_set_parent_realize(dc
, pnv_chip_power8_realize
,
1250 &k
->parent_realize
);
1253 static void pnv_chip_power8_class_init(ObjectClass
*klass
, void *data
)
1255 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1256 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1258 k
->chip_cfam_id
= 0x220ea04980000000ull
; /* P8 Venice DD2.0 */
1259 k
->cores_mask
= POWER8_CORE_MASK
;
1261 k
->core_pir
= pnv_chip_core_pir_p8
;
1262 k
->intc_create
= pnv_chip_power8_intc_create
;
1263 k
->intc_reset
= pnv_chip_power8_intc_reset
;
1264 k
->intc_destroy
= pnv_chip_power8_intc_destroy
;
1265 k
->intc_print_info
= pnv_chip_power8_intc_print_info
;
1266 k
->isa_create
= pnv_chip_power8_isa_create
;
1267 k
->dt_populate
= pnv_chip_power8_dt_populate
;
1268 k
->pic_print_info
= pnv_chip_power8_pic_print_info
;
1269 k
->xscom_core_base
= pnv_chip_power8_xscom_core_base
;
1270 k
->xscom_pcba
= pnv_chip_power8_xscom_pcba
;
1271 dc
->desc
= "PowerNV Chip POWER8";
1273 device_class_set_parent_realize(dc
, pnv_chip_power8_realize
,
1274 &k
->parent_realize
);
1277 static void pnv_chip_power8nvl_class_init(ObjectClass
*klass
, void *data
)
1279 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1280 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1282 k
->chip_cfam_id
= 0x120d304980000000ull
; /* P8 Naples DD1.0 */
1283 k
->cores_mask
= POWER8_CORE_MASK
;
1285 k
->core_pir
= pnv_chip_core_pir_p8
;
1286 k
->intc_create
= pnv_chip_power8_intc_create
;
1287 k
->intc_reset
= pnv_chip_power8_intc_reset
;
1288 k
->intc_destroy
= pnv_chip_power8_intc_destroy
;
1289 k
->intc_print_info
= pnv_chip_power8_intc_print_info
;
1290 k
->isa_create
= pnv_chip_power8nvl_isa_create
;
1291 k
->dt_populate
= pnv_chip_power8_dt_populate
;
1292 k
->pic_print_info
= pnv_chip_power8_pic_print_info
;
1293 k
->xscom_core_base
= pnv_chip_power8_xscom_core_base
;
1294 k
->xscom_pcba
= pnv_chip_power8_xscom_pcba
;
1295 dc
->desc
= "PowerNV Chip POWER8NVL";
1297 device_class_set_parent_realize(dc
, pnv_chip_power8_realize
,
1298 &k
->parent_realize
);
1301 static void pnv_chip_power9_instance_init(Object
*obj
)
1303 PnvChip
*chip
= PNV_CHIP(obj
);
1304 Pnv9Chip
*chip9
= PNV9_CHIP(obj
);
1305 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(obj
);
1308 object_initialize_child(obj
, "xive", &chip9
->xive
, TYPE_PNV_XIVE
);
1309 object_property_add_alias(obj
, "xive-fabric", OBJECT(&chip9
->xive
),
1312 object_initialize_child(obj
, "psi", &chip9
->psi
, TYPE_PNV9_PSI
);
1314 object_initialize_child(obj
, "lpc", &chip9
->lpc
, TYPE_PNV9_LPC
);
1316 object_initialize_child(obj
, "occ", &chip9
->occ
, TYPE_PNV9_OCC
);
1318 object_initialize_child(obj
, "homer", &chip9
->homer
, TYPE_PNV9_HOMER
);
1320 for (i
= 0; i
< PNV9_CHIP_MAX_PEC
; i
++) {
1321 object_initialize_child(obj
, "pec[*]", &chip9
->pecs
[i
],
1326 * Number of PHBs is the chip default
1328 chip
->num_phbs
= pcc
->num_phbs
;
1331 static void pnv_chip_quad_realize(Pnv9Chip
*chip9
, Error
**errp
)
1333 PnvChip
*chip
= PNV_CHIP(chip9
);
1336 chip9
->nr_quads
= DIV_ROUND_UP(chip
->nr_cores
, 4);
1337 chip9
->quads
= g_new0(PnvQuad
, chip9
->nr_quads
);
1339 for (i
= 0; i
< chip9
->nr_quads
; i
++) {
1341 PnvQuad
*eq
= &chip9
->quads
[i
];
1342 PnvCore
*pnv_core
= chip
->cores
[i
* 4];
1343 int core_id
= CPU_CORE(pnv_core
)->core_id
;
1345 snprintf(eq_name
, sizeof(eq_name
), "eq[%d]", core_id
);
1346 object_initialize_child_with_props(OBJECT(chip
), eq_name
, eq
,
1347 sizeof(*eq
), TYPE_PNV_QUAD
,
1348 &error_fatal
, NULL
);
1350 object_property_set_int(OBJECT(eq
), "id", core_id
, &error_fatal
);
1351 qdev_realize(DEVICE(eq
), NULL
, &error_fatal
);
1353 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_EQ_BASE(eq
->id
),
1358 static void pnv_chip_power9_phb_realize(PnvChip
*chip
, Error
**errp
)
1360 Pnv9Chip
*chip9
= PNV9_CHIP(chip
);
1361 Error
*local_err
= NULL
;
1365 for (i
= 0; i
< PNV9_CHIP_MAX_PEC
; i
++) {
1366 PnvPhb4PecState
*pec
= &chip9
->pecs
[i
];
1367 PnvPhb4PecClass
*pecc
= PNV_PHB4_PEC_GET_CLASS(pec
);
1368 uint32_t pec_nest_base
;
1369 uint32_t pec_pci_base
;
1371 object_property_set_int(OBJECT(pec
), "index", i
, &error_fatal
);
1377 object_property_set_int(OBJECT(pec
), "num-stacks", i
+ 1,
1379 object_property_set_int(OBJECT(pec
), "chip-id", chip
->chip_id
,
1381 object_property_set_link(OBJECT(pec
), "system-memory",
1382 OBJECT(get_system_memory()), &error_abort
);
1383 if (!qdev_realize(DEVICE(pec
), NULL
, &local_err
)) {
1384 error_propagate(errp
, local_err
);
1388 pec_nest_base
= pecc
->xscom_nest_base(pec
);
1389 pec_pci_base
= pecc
->xscom_pci_base(pec
);
1391 pnv_xscom_add_subregion(chip
, pec_nest_base
, &pec
->nest_regs_mr
);
1392 pnv_xscom_add_subregion(chip
, pec_pci_base
, &pec
->pci_regs_mr
);
1394 for (j
= 0; j
< pec
->num_stacks
&& phb_id
< chip
->num_phbs
;
1396 PnvPhb4PecStack
*stack
= &pec
->stacks
[j
];
1397 Object
*obj
= OBJECT(&stack
->phb
);
1399 object_property_set_int(obj
, "index", phb_id
, &error_fatal
);
1400 object_property_set_int(obj
, "chip-id", chip
->chip_id
,
1402 object_property_set_int(obj
, "version", PNV_PHB4_VERSION
,
1404 object_property_set_int(obj
, "device-id", PNV_PHB4_DEVICE_ID
,
1406 object_property_set_link(obj
, "stack", OBJECT(stack
),
1408 if (!sysbus_realize(SYS_BUS_DEVICE(obj
), &local_err
)) {
1409 error_propagate(errp
, local_err
);
1413 /* Populate the XSCOM address space. */
1414 pnv_xscom_add_subregion(chip
,
1415 pec_nest_base
+ 0x40 * (stack
->stack_no
+ 1),
1416 &stack
->nest_regs_mr
);
1417 pnv_xscom_add_subregion(chip
,
1418 pec_pci_base
+ 0x40 * (stack
->stack_no
+ 1),
1419 &stack
->pci_regs_mr
);
1420 pnv_xscom_add_subregion(chip
,
1421 pec_pci_base
+ PNV9_XSCOM_PEC_PCI_STK0
+
1422 0x40 * stack
->stack_no
,
1423 &stack
->phb_regs_mr
);
1428 static void pnv_chip_power9_realize(DeviceState
*dev
, Error
**errp
)
1430 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(dev
);
1431 Pnv9Chip
*chip9
= PNV9_CHIP(dev
);
1432 PnvChip
*chip
= PNV_CHIP(dev
);
1433 Pnv9Psi
*psi9
= &chip9
->psi
;
1434 Error
*local_err
= NULL
;
1436 /* XSCOM bridge is first */
1437 pnv_xscom_realize(chip
, PNV9_XSCOM_SIZE
, &local_err
);
1439 error_propagate(errp
, local_err
);
1442 sysbus_mmio_map(SYS_BUS_DEVICE(chip
), 0, PNV9_XSCOM_BASE(chip
));
1444 pcc
->parent_realize(dev
, &local_err
);
1446 error_propagate(errp
, local_err
);
1450 pnv_chip_quad_realize(chip9
, &local_err
);
1452 error_propagate(errp
, local_err
);
1456 /* XIVE interrupt controller (POWER9) */
1457 object_property_set_int(OBJECT(&chip9
->xive
), "ic-bar",
1458 PNV9_XIVE_IC_BASE(chip
), &error_fatal
);
1459 object_property_set_int(OBJECT(&chip9
->xive
), "vc-bar",
1460 PNV9_XIVE_VC_BASE(chip
), &error_fatal
);
1461 object_property_set_int(OBJECT(&chip9
->xive
), "pc-bar",
1462 PNV9_XIVE_PC_BASE(chip
), &error_fatal
);
1463 object_property_set_int(OBJECT(&chip9
->xive
), "tm-bar",
1464 PNV9_XIVE_TM_BASE(chip
), &error_fatal
);
1465 object_property_set_link(OBJECT(&chip9
->xive
), "chip", OBJECT(chip
),
1467 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9
->xive
), &local_err
)) {
1468 error_propagate(errp
, local_err
);
1471 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_XIVE_BASE
,
1472 &chip9
->xive
.xscom_regs
);
1474 /* Processor Service Interface (PSI) Host Bridge */
1475 object_property_set_int(OBJECT(&chip9
->psi
), "bar", PNV9_PSIHB_BASE(chip
),
1477 if (!qdev_realize(DEVICE(&chip9
->psi
), NULL
, &local_err
)) {
1478 error_propagate(errp
, local_err
);
1481 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_PSIHB_BASE
,
1482 &PNV_PSI(psi9
)->xscom_regs
);
1485 object_property_set_link(OBJECT(&chip9
->lpc
), "psi", OBJECT(&chip9
->psi
),
1487 if (!qdev_realize(DEVICE(&chip9
->lpc
), NULL
, &local_err
)) {
1488 error_propagate(errp
, local_err
);
1491 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip
),
1492 &chip9
->lpc
.xscom_regs
);
1494 chip
->dt_isa_nodename
= g_strdup_printf("/lpcm-opb@%" PRIx64
"/lpc@0",
1495 (uint64_t) PNV9_LPCM_BASE(chip
));
1497 /* Create the simplified OCC model */
1498 object_property_set_link(OBJECT(&chip9
->occ
), "psi", OBJECT(&chip9
->psi
),
1500 if (!qdev_realize(DEVICE(&chip9
->occ
), NULL
, &local_err
)) {
1501 error_propagate(errp
, local_err
);
1504 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_OCC_BASE
, &chip9
->occ
.xscom_regs
);
1506 /* OCC SRAM model */
1507 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip
),
1508 &chip9
->occ
.sram_regs
);
1511 object_property_set_link(OBJECT(&chip9
->homer
), "chip", OBJECT(chip
),
1513 if (!qdev_realize(DEVICE(&chip9
->homer
), NULL
, &local_err
)) {
1514 error_propagate(errp
, local_err
);
1517 /* Homer Xscom region */
1518 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_PBA_BASE
, &chip9
->homer
.pba_regs
);
1520 /* Homer mmio region */
1521 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip
),
1522 &chip9
->homer
.regs
);
1525 pnv_chip_power9_phb_realize(chip
, &local_err
);
1527 error_propagate(errp
, local_err
);
1532 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip
*chip
, uint64_t addr
)
1534 addr
&= (PNV9_XSCOM_SIZE
- 1);
1538 static void pnv_chip_power9_class_init(ObjectClass
*klass
, void *data
)
1540 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1541 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1543 k
->chip_cfam_id
= 0x220d104900008000ull
; /* P9 Nimbus DD2.0 */
1544 k
->cores_mask
= POWER9_CORE_MASK
;
1545 k
->core_pir
= pnv_chip_core_pir_p9
;
1546 k
->intc_create
= pnv_chip_power9_intc_create
;
1547 k
->intc_reset
= pnv_chip_power9_intc_reset
;
1548 k
->intc_destroy
= pnv_chip_power9_intc_destroy
;
1549 k
->intc_print_info
= pnv_chip_power9_intc_print_info
;
1550 k
->isa_create
= pnv_chip_power9_isa_create
;
1551 k
->dt_populate
= pnv_chip_power9_dt_populate
;
1552 k
->pic_print_info
= pnv_chip_power9_pic_print_info
;
1553 k
->xscom_core_base
= pnv_chip_power9_xscom_core_base
;
1554 k
->xscom_pcba
= pnv_chip_power9_xscom_pcba
;
1555 dc
->desc
= "PowerNV Chip POWER9";
1558 device_class_set_parent_realize(dc
, pnv_chip_power9_realize
,
1559 &k
->parent_realize
);
1562 static void pnv_chip_power10_instance_init(Object
*obj
)
1564 Pnv10Chip
*chip10
= PNV10_CHIP(obj
);
1566 object_initialize_child(obj
, "psi", &chip10
->psi
, TYPE_PNV10_PSI
);
1567 object_initialize_child(obj
, "lpc", &chip10
->lpc
, TYPE_PNV10_LPC
);
1570 static void pnv_chip_power10_realize(DeviceState
*dev
, Error
**errp
)
1572 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(dev
);
1573 PnvChip
*chip
= PNV_CHIP(dev
);
1574 Pnv10Chip
*chip10
= PNV10_CHIP(dev
);
1575 Error
*local_err
= NULL
;
1577 /* XSCOM bridge is first */
1578 pnv_xscom_realize(chip
, PNV10_XSCOM_SIZE
, &local_err
);
1580 error_propagate(errp
, local_err
);
1583 sysbus_mmio_map(SYS_BUS_DEVICE(chip
), 0, PNV10_XSCOM_BASE(chip
));
1585 pcc
->parent_realize(dev
, &local_err
);
1587 error_propagate(errp
, local_err
);
1591 /* Processor Service Interface (PSI) Host Bridge */
1592 object_property_set_int(OBJECT(&chip10
->psi
), "bar",
1593 PNV10_PSIHB_BASE(chip
), &error_fatal
);
1594 if (!qdev_realize(DEVICE(&chip10
->psi
), NULL
, &local_err
)) {
1595 error_propagate(errp
, local_err
);
1598 pnv_xscom_add_subregion(chip
, PNV10_XSCOM_PSIHB_BASE
,
1599 &PNV_PSI(&chip10
->psi
)->xscom_regs
);
1602 object_property_set_link(OBJECT(&chip10
->lpc
), "psi",
1603 OBJECT(&chip10
->psi
), &error_abort
);
1604 if (!qdev_realize(DEVICE(&chip10
->lpc
), NULL
, &local_err
)) {
1605 error_propagate(errp
, local_err
);
1608 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip
),
1609 &chip10
->lpc
.xscom_regs
);
1611 chip
->dt_isa_nodename
= g_strdup_printf("/lpcm-opb@%" PRIx64
"/lpc@0",
1612 (uint64_t) PNV10_LPCM_BASE(chip
));
1615 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip
*chip
, uint64_t addr
)
1617 addr
&= (PNV10_XSCOM_SIZE
- 1);
1621 static void pnv_chip_power10_class_init(ObjectClass
*klass
, void *data
)
1623 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1624 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1626 k
->chip_cfam_id
= 0x120da04900008000ull
; /* P10 DD1.0 (with NX) */
1627 k
->cores_mask
= POWER10_CORE_MASK
;
1628 k
->core_pir
= pnv_chip_core_pir_p10
;
1629 k
->intc_create
= pnv_chip_power10_intc_create
;
1630 k
->intc_reset
= pnv_chip_power10_intc_reset
;
1631 k
->intc_destroy
= pnv_chip_power10_intc_destroy
;
1632 k
->intc_print_info
= pnv_chip_power10_intc_print_info
;
1633 k
->isa_create
= pnv_chip_power10_isa_create
;
1634 k
->dt_populate
= pnv_chip_power10_dt_populate
;
1635 k
->pic_print_info
= pnv_chip_power10_pic_print_info
;
1636 k
->xscom_core_base
= pnv_chip_power10_xscom_core_base
;
1637 k
->xscom_pcba
= pnv_chip_power10_xscom_pcba
;
1638 dc
->desc
= "PowerNV Chip POWER10";
1640 device_class_set_parent_realize(dc
, pnv_chip_power10_realize
,
1641 &k
->parent_realize
);
1644 static void pnv_chip_core_sanitize(PnvChip
*chip
, Error
**errp
)
1646 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
1650 * No custom mask for this chip, let's use the default one from *
1653 if (!chip
->cores_mask
) {
1654 chip
->cores_mask
= pcc
->cores_mask
;
1657 /* filter alien core ids ! some are reserved */
1658 if ((chip
->cores_mask
& pcc
->cores_mask
) != chip
->cores_mask
) {
1659 error_setg(errp
, "warning: invalid core mask for chip Ox%"PRIx64
" !",
1663 chip
->cores_mask
&= pcc
->cores_mask
;
1665 /* now that we have a sane layout, let check the number of cores */
1666 cores_max
= ctpop64(chip
->cores_mask
);
1667 if (chip
->nr_cores
> cores_max
) {
1668 error_setg(errp
, "warning: too many cores for chip ! Limit is %d",
1674 static void pnv_chip_core_realize(PnvChip
*chip
, Error
**errp
)
1676 Error
*error
= NULL
;
1677 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
1678 const char *typename
= pnv_chip_core_typename(chip
);
1680 PnvMachineState
*pnv
= PNV_MACHINE(qdev_get_machine());
1682 if (!object_class_by_name(typename
)) {
1683 error_setg(errp
, "Unable to find PowerNV CPU Core '%s'", typename
);
1688 pnv_chip_core_sanitize(chip
, &error
);
1690 error_propagate(errp
, error
);
1694 chip
->cores
= g_new0(PnvCore
*, chip
->nr_cores
);
1696 for (i
= 0, core_hwid
= 0; (core_hwid
< sizeof(chip
->cores_mask
) * 8)
1697 && (i
< chip
->nr_cores
); core_hwid
++) {
1700 uint64_t xscom_core_base
;
1702 if (!(chip
->cores_mask
& (1ull << core_hwid
))) {
1706 pnv_core
= PNV_CORE(object_new(typename
));
1708 snprintf(core_name
, sizeof(core_name
), "core[%d]", core_hwid
);
1709 object_property_add_child(OBJECT(chip
), core_name
, OBJECT(pnv_core
));
1710 chip
->cores
[i
] = pnv_core
;
1711 object_property_set_int(OBJECT(pnv_core
), "nr-threads",
1712 chip
->nr_threads
, &error_fatal
);
1713 object_property_set_int(OBJECT(pnv_core
), CPU_CORE_PROP_CORE_ID
,
1714 core_hwid
, &error_fatal
);
1715 object_property_set_int(OBJECT(pnv_core
), "pir",
1716 pcc
->core_pir(chip
, core_hwid
), &error_fatal
);
1717 object_property_set_int(OBJECT(pnv_core
), "hrmor", pnv
->fw_load_addr
,
1719 object_property_set_link(OBJECT(pnv_core
), "chip", OBJECT(chip
),
1721 qdev_realize(DEVICE(pnv_core
), NULL
, &error_fatal
);
1723 /* Each core has an XSCOM MMIO region */
1724 xscom_core_base
= pcc
->xscom_core_base(chip
, core_hwid
);
1726 pnv_xscom_add_subregion(chip
, xscom_core_base
,
1727 &pnv_core
->xscom_regs
);
1732 static void pnv_chip_realize(DeviceState
*dev
, Error
**errp
)
1734 PnvChip
*chip
= PNV_CHIP(dev
);
1735 Error
*error
= NULL
;
1738 pnv_chip_core_realize(chip
, &error
);
1740 error_propagate(errp
, error
);
1745 static Property pnv_chip_properties
[] = {
1746 DEFINE_PROP_UINT32("chip-id", PnvChip
, chip_id
, 0),
1747 DEFINE_PROP_UINT64("ram-start", PnvChip
, ram_start
, 0),
1748 DEFINE_PROP_UINT64("ram-size", PnvChip
, ram_size
, 0),
1749 DEFINE_PROP_UINT32("nr-cores", PnvChip
, nr_cores
, 1),
1750 DEFINE_PROP_UINT64("cores-mask", PnvChip
, cores_mask
, 0x0),
1751 DEFINE_PROP_UINT32("nr-threads", PnvChip
, nr_threads
, 1),
1752 DEFINE_PROP_UINT32("num-phbs", PnvChip
, num_phbs
, 0),
1753 DEFINE_PROP_END_OF_LIST(),
1756 static void pnv_chip_class_init(ObjectClass
*klass
, void *data
)
1758 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1760 set_bit(DEVICE_CATEGORY_CPU
, dc
->categories
);
1761 dc
->realize
= pnv_chip_realize
;
1762 device_class_set_props(dc
, pnv_chip_properties
);
1763 dc
->desc
= "PowerNV Chip";
1766 PowerPCCPU
*pnv_chip_find_cpu(PnvChip
*chip
, uint32_t pir
)
1770 for (i
= 0; i
< chip
->nr_cores
; i
++) {
1771 PnvCore
*pc
= chip
->cores
[i
];
1772 CPUCore
*cc
= CPU_CORE(pc
);
1774 for (j
= 0; j
< cc
->nr_threads
; j
++) {
1775 if (ppc_cpu_pir(pc
->threads
[j
]) == pir
) {
1776 return pc
->threads
[j
];
1783 static ICSState
*pnv_ics_get(XICSFabric
*xi
, int irq
)
1785 PnvMachineState
*pnv
= PNV_MACHINE(xi
);
1788 for (i
= 0; i
< pnv
->num_chips
; i
++) {
1789 PnvChip
*chip
= pnv
->chips
[i
];
1790 Pnv8Chip
*chip8
= PNV8_CHIP(pnv
->chips
[i
]);
1792 if (ics_valid_irq(&chip8
->psi
.ics
, irq
)) {
1793 return &chip8
->psi
.ics
;
1795 for (j
= 0; j
< chip
->num_phbs
; j
++) {
1796 if (ics_valid_irq(&chip8
->phbs
[j
].lsis
, irq
)) {
1797 return &chip8
->phbs
[j
].lsis
;
1799 if (ics_valid_irq(ICS(&chip8
->phbs
[j
].msis
), irq
)) {
1800 return ICS(&chip8
->phbs
[j
].msis
);
1807 static void pnv_ics_resend(XICSFabric
*xi
)
1809 PnvMachineState
*pnv
= PNV_MACHINE(xi
);
1812 for (i
= 0; i
< pnv
->num_chips
; i
++) {
1813 PnvChip
*chip
= pnv
->chips
[i
];
1814 Pnv8Chip
*chip8
= PNV8_CHIP(pnv
->chips
[i
]);
1816 ics_resend(&chip8
->psi
.ics
);
1817 for (j
= 0; j
< chip
->num_phbs
; j
++) {
1818 ics_resend(&chip8
->phbs
[j
].lsis
);
1819 ics_resend(ICS(&chip8
->phbs
[j
].msis
));
1824 static ICPState
*pnv_icp_get(XICSFabric
*xi
, int pir
)
1826 PowerPCCPU
*cpu
= ppc_get_vcpu_by_pir(pir
);
1828 return cpu
? ICP(pnv_cpu_state(cpu
)->intc
) : NULL
;
1831 static void pnv_pic_print_info(InterruptStatsProvider
*obj
,
1834 PnvMachineState
*pnv
= PNV_MACHINE(obj
);
1839 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1841 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */
1842 PNV_CHIP_GET_CLASS(pnv
->chips
[0])->intc_print_info(pnv
->chips
[0], cpu
,
1846 for (i
= 0; i
< pnv
->num_chips
; i
++) {
1847 PNV_CHIP_GET_CLASS(pnv
->chips
[i
])->pic_print_info(pnv
->chips
[i
], mon
);
1851 static int pnv_match_nvt(XiveFabric
*xfb
, uint8_t format
,
1852 uint8_t nvt_blk
, uint32_t nvt_idx
,
1853 bool cam_ignore
, uint8_t priority
,
1854 uint32_t logic_serv
,
1855 XiveTCTXMatch
*match
)
1857 PnvMachineState
*pnv
= PNV_MACHINE(xfb
);
1858 int total_count
= 0;
1861 for (i
= 0; i
< pnv
->num_chips
; i
++) {
1862 Pnv9Chip
*chip9
= PNV9_CHIP(pnv
->chips
[i
]);
1863 XivePresenter
*xptr
= XIVE_PRESENTER(&chip9
->xive
);
1864 XivePresenterClass
*xpc
= XIVE_PRESENTER_GET_CLASS(xptr
);
1867 count
= xpc
->match_nvt(xptr
, format
, nvt_blk
, nvt_idx
, cam_ignore
,
1868 priority
, logic_serv
, match
);
1874 total_count
+= count
;
1880 static void pnv_machine_power8_class_init(ObjectClass
*oc
, void *data
)
1882 MachineClass
*mc
= MACHINE_CLASS(oc
);
1883 XICSFabricClass
*xic
= XICS_FABRIC_CLASS(oc
);
1884 PnvMachineClass
*pmc
= PNV_MACHINE_CLASS(oc
);
1885 static const char compat
[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
1887 mc
->desc
= "IBM PowerNV (Non-Virtualized) POWER8";
1888 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power8_v2.0");
1890 xic
->icp_get
= pnv_icp_get
;
1891 xic
->ics_get
= pnv_ics_get
;
1892 xic
->ics_resend
= pnv_ics_resend
;
1894 pmc
->compat
= compat
;
1895 pmc
->compat_size
= sizeof(compat
);
1898 static void pnv_machine_power9_class_init(ObjectClass
*oc
, void *data
)
1900 MachineClass
*mc
= MACHINE_CLASS(oc
);
1901 XiveFabricClass
*xfc
= XIVE_FABRIC_CLASS(oc
);
1902 PnvMachineClass
*pmc
= PNV_MACHINE_CLASS(oc
);
1903 static const char compat
[] = "qemu,powernv9\0ibm,powernv";
1905 mc
->desc
= "IBM PowerNV (Non-Virtualized) POWER9";
1906 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power9_v2.0");
1907 xfc
->match_nvt
= pnv_match_nvt
;
1909 mc
->alias
= "powernv";
1911 pmc
->compat
= compat
;
1912 pmc
->compat_size
= sizeof(compat
);
1913 pmc
->dt_power_mgt
= pnv_dt_power_mgt
;
1916 static void pnv_machine_power10_class_init(ObjectClass
*oc
, void *data
)
1918 MachineClass
*mc
= MACHINE_CLASS(oc
);
1919 PnvMachineClass
*pmc
= PNV_MACHINE_CLASS(oc
);
1920 static const char compat
[] = "qemu,powernv10\0ibm,powernv";
1922 mc
->desc
= "IBM PowerNV (Non-Virtualized) POWER10";
1923 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power10_v1.0");
1925 pmc
->compat
= compat
;
1926 pmc
->compat_size
= sizeof(compat
);
1927 pmc
->dt_power_mgt
= pnv_dt_power_mgt
;
1930 static bool pnv_machine_get_hb(Object
*obj
, Error
**errp
)
1932 PnvMachineState
*pnv
= PNV_MACHINE(obj
);
1934 return !!pnv
->fw_load_addr
;
1937 static void pnv_machine_set_hb(Object
*obj
, bool value
, Error
**errp
)
1939 PnvMachineState
*pnv
= PNV_MACHINE(obj
);
1942 pnv
->fw_load_addr
= 0x8000000;
1946 static void pnv_cpu_do_nmi_on_cpu(CPUState
*cs
, run_on_cpu_data arg
)
1948 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1949 CPUPPCState
*env
= &cpu
->env
;
1951 cpu_synchronize_state(cs
);
1952 ppc_cpu_do_system_reset(cs
);
1953 if (env
->spr
[SPR_SRR1
] & SRR1_WAKESTATE
) {
1955 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the
1956 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100
1959 if (!(env
->spr
[SPR_SRR1
] & SRR1_WAKERESET
)) {
1960 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason");
1961 env
->spr
[SPR_SRR1
] |= SRR1_WAKERESET
;
1965 * For non-powersave system resets, SRR1[42:45] are defined to be
1966 * implementation-dependent. The POWER9 User Manual specifies that
1967 * an external (SCOM driven, which may come from a BMC nmi command or
1968 * another CPU requesting a NMI IPI) system reset exception should be
1969 * 0b0010 (PPC_BIT(44)).
1971 env
->spr
[SPR_SRR1
] |= SRR1_WAKESCOM
;
1975 static void pnv_nmi(NMIState
*n
, int cpu_index
, Error
**errp
)
1980 async_run_on_cpu(cs
, pnv_cpu_do_nmi_on_cpu
, RUN_ON_CPU_NULL
);
1984 static void pnv_machine_class_init(ObjectClass
*oc
, void *data
)
1986 MachineClass
*mc
= MACHINE_CLASS(oc
);
1987 InterruptStatsProviderClass
*ispc
= INTERRUPT_STATS_PROVIDER_CLASS(oc
);
1988 NMIClass
*nc
= NMI_CLASS(oc
);
1990 mc
->desc
= "IBM PowerNV (Non-Virtualized)";
1991 mc
->init
= pnv_init
;
1992 mc
->reset
= pnv_reset
;
1993 mc
->max_cpus
= MAX_CPUS
;
1994 /* Pnv provides a AHCI device for storage */
1995 mc
->block_default_type
= IF_IDE
;
1996 mc
->no_parallel
= 1;
1997 mc
->default_boot_order
= NULL
;
1999 * RAM defaults to less than 2048 for 32-bit hosts, and large
2000 * enough to fit the maximum initrd size at it's load address
2002 mc
->default_ram_size
= INITRD_LOAD_ADDR
+ INITRD_MAX_SIZE
;
2003 mc
->default_ram_id
= "pnv.ram";
2004 ispc
->print_info
= pnv_pic_print_info
;
2005 nc
->nmi_monitor_handler
= pnv_nmi
;
2007 object_class_property_add_bool(oc
, "hb-mode",
2008 pnv_machine_get_hb
, pnv_machine_set_hb
);
2009 object_class_property_set_description(oc
, "hb-mode",
2010 "Use a hostboot like boot loader");
2013 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
2016 .class_init = class_initfn, \
2017 .parent = TYPE_PNV8_CHIP, \
2020 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
2023 .class_init = class_initfn, \
2024 .parent = TYPE_PNV9_CHIP, \
2027 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \
2030 .class_init = class_initfn, \
2031 .parent = TYPE_PNV10_CHIP, \
2034 static const TypeInfo types
[] = {
2036 .name
= MACHINE_TYPE_NAME("powernv10"),
2037 .parent
= TYPE_PNV_MACHINE
,
2038 .class_init
= pnv_machine_power10_class_init
,
2041 .name
= MACHINE_TYPE_NAME("powernv9"),
2042 .parent
= TYPE_PNV_MACHINE
,
2043 .class_init
= pnv_machine_power9_class_init
,
2044 .interfaces
= (InterfaceInfo
[]) {
2045 { TYPE_XIVE_FABRIC
},
2050 .name
= MACHINE_TYPE_NAME("powernv8"),
2051 .parent
= TYPE_PNV_MACHINE
,
2052 .class_init
= pnv_machine_power8_class_init
,
2053 .interfaces
= (InterfaceInfo
[]) {
2054 { TYPE_XICS_FABRIC
},
2059 .name
= TYPE_PNV_MACHINE
,
2060 .parent
= TYPE_MACHINE
,
2062 .instance_size
= sizeof(PnvMachineState
),
2063 .class_init
= pnv_machine_class_init
,
2064 .class_size
= sizeof(PnvMachineClass
),
2065 .interfaces
= (InterfaceInfo
[]) {
2066 { TYPE_INTERRUPT_STATS_PROVIDER
},
2072 .name
= TYPE_PNV_CHIP
,
2073 .parent
= TYPE_SYS_BUS_DEVICE
,
2074 .class_init
= pnv_chip_class_init
,
2075 .instance_size
= sizeof(PnvChip
),
2076 .class_size
= sizeof(PnvChipClass
),
2081 * P10 chip and variants
2084 .name
= TYPE_PNV10_CHIP
,
2085 .parent
= TYPE_PNV_CHIP
,
2086 .instance_init
= pnv_chip_power10_instance_init
,
2087 .instance_size
= sizeof(Pnv10Chip
),
2089 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10
, pnv_chip_power10_class_init
),
2092 * P9 chip and variants
2095 .name
= TYPE_PNV9_CHIP
,
2096 .parent
= TYPE_PNV_CHIP
,
2097 .instance_init
= pnv_chip_power9_instance_init
,
2098 .instance_size
= sizeof(Pnv9Chip
),
2100 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9
, pnv_chip_power9_class_init
),
2103 * P8 chip and variants
2106 .name
= TYPE_PNV8_CHIP
,
2107 .parent
= TYPE_PNV_CHIP
,
2108 .instance_init
= pnv_chip_power8_instance_init
,
2109 .instance_size
= sizeof(Pnv8Chip
),
2111 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8
, pnv_chip_power8_class_init
),
2112 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E
, pnv_chip_power8e_class_init
),
2113 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL
,
2114 pnv_chip_power8nvl_class_init
),