hw/ppc/pnv_occ.c

   1 /*
   2  * QEMU PowerPC PowerNV Emulation of a few OCC related registers
   3  *
   4  * Copyright (c) 2015-2017, IBM Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License, version 2, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include "qemu/osdep.h"
  20 #include "sysemu/sysemu.h"
  21 #include "target/ppc/cpu.h"
  22 #include "qapi/error.h"
  23 #include "qemu/log.h"
  24 #include "qemu/module.h"
  25
  26 #include "hw/ppc/pnv.h"
  27 #include "hw/ppc/pnv_xscom.h"
  28 #include "hw/ppc/pnv_occ.h"
  29
  30 #define OCB_OCI_OCCMISC         0x4020
  31 #define OCB_OCI_OCCMISC_AND     0x4021
  32 #define OCB_OCI_OCCMISC_OR      0x4022
  33
  34 static void pnv_occ_set_misc(PnvOCC *occ, uint64_t val)
  35 {
  36     bool irq_state;
  37     PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ);
  38
  39     val &= 0xffff000000000000ull;
  40
  41     occ->occmisc = val;
  42     irq_state = !!(val >> 63);
  43     pnv_psi_irq_set(occ->psi, poc->psi_irq, irq_state);
  44 }
  45
  46 static uint64_t pnv_occ_power8_xscom_read(void *opaque, hwaddr addr,
  47                                           unsigned size)
  48 {
  49     PnvOCC *occ = PNV_OCC(opaque);
  50     uint32_t offset = addr >> 3;
  51     uint64_t val = 0;
  52
  53     switch (offset) {
  54     case OCB_OCI_OCCMISC:
  55         val = occ->occmisc;
  56         break;
  57     default:
  58         qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
  59                       HWADDR_PRIx "\n", addr >> 3);
  60     }
  61     return val;
  62 }
  63
  64 static void pnv_occ_power8_xscom_write(void *opaque, hwaddr addr,
  65                                        uint64_t val, unsigned size)
  66 {
  67     PnvOCC *occ = PNV_OCC(opaque);
  68     uint32_t offset = addr >> 3;
  69
  70     switch (offset) {
  71     case OCB_OCI_OCCMISC_AND:
  72         pnv_occ_set_misc(occ, occ->occmisc & val);
  73         break;
  74     case OCB_OCI_OCCMISC_OR:
  75         pnv_occ_set_misc(occ, occ->occmisc | val);
  76         break;
  77     case OCB_OCI_OCCMISC:
  78         pnv_occ_set_misc(occ, val);
  79         break;
  80     default:
  81         qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
  82                       HWADDR_PRIx "\n", addr >> 3);
  83     }
  84 }
  85
  86 static const MemoryRegionOps pnv_occ_power8_xscom_ops = {
  87     .read = pnv_occ_power8_xscom_read,
  88     .write = pnv_occ_power8_xscom_write,
  89     .valid.min_access_size = 8,
  90     .valid.max_access_size = 8,
  91     .impl.min_access_size = 8,
  92     .impl.max_access_size = 8,
  93     .endianness = DEVICE_BIG_ENDIAN,
  94 };
  95
  96 static void pnv_occ_power8_class_init(ObjectClass *klass, void *data)
  97 {
  98     PnvOCCClass *poc = PNV_OCC_CLASS(klass);
  99
 100     poc->xscom_size = PNV_XSCOM_OCC_SIZE;
 101     poc->xscom_ops = &pnv_occ_power8_xscom_ops;
 102     poc->psi_irq = PSIHB_IRQ_OCC;
 103 }
 104
 105 static const TypeInfo pnv_occ_power8_type_info = {
 106     .name          = TYPE_PNV8_OCC,
 107     .parent        = TYPE_PNV_OCC,
 108     .instance_size = sizeof(PnvOCC),
 109     .class_init    = pnv_occ_power8_class_init,
 110 };
 111
 112 #define P9_OCB_OCI_OCCMISC              0x6080
 113 #define P9_OCB_OCI_OCCMISC_CLEAR        0x6081
 114 #define P9_OCB_OCI_OCCMISC_OR           0x6082
 115
 116
 117 static uint64_t pnv_occ_power9_xscom_read(void *opaque, hwaddr addr,
 118                                           unsigned size)
 119 {
 120     PnvOCC *occ = PNV_OCC(opaque);
 121     uint32_t offset = addr >> 3;
 122     uint64_t val = 0;
 123
 124     switch (offset) {
 125     case P9_OCB_OCI_OCCMISC:
 126         val = occ->occmisc;
 127         break;
 128     default:
 129         qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
 130                       HWADDR_PRIx "\n", addr >> 3);
 131     }
 132     return val;
 133 }
 134
 135 static void pnv_occ_power9_xscom_write(void *opaque, hwaddr addr,
 136                                        uint64_t val, unsigned size)
 137 {
 138     PnvOCC *occ = PNV_OCC(opaque);
 139     uint32_t offset = addr >> 3;
 140
 141     switch (offset) {
 142     case P9_OCB_OCI_OCCMISC_CLEAR:
 143         pnv_occ_set_misc(occ, 0);
 144         break;
 145     case P9_OCB_OCI_OCCMISC_OR:
 146         pnv_occ_set_misc(occ, occ->occmisc | val);
 147         break;
 148     case P9_OCB_OCI_OCCMISC:
 149         pnv_occ_set_misc(occ, val);
 150        break;
 151     default:
 152         qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
 153                       HWADDR_PRIx "\n", addr >> 3);
 154     }
 155 }
 156
 157 static const MemoryRegionOps pnv_occ_power9_xscom_ops = {
 158     .read = pnv_occ_power9_xscom_read,
 159     .write = pnv_occ_power9_xscom_write,
 160     .valid.min_access_size = 8,
 161     .valid.max_access_size = 8,
 162     .impl.min_access_size = 8,
 163     .impl.max_access_size = 8,
 164     .endianness = DEVICE_BIG_ENDIAN,
 165 };
 166
 167 static void pnv_occ_power9_class_init(ObjectClass *klass, void *data)
 168 {
 169     PnvOCCClass *poc = PNV_OCC_CLASS(klass);
 170
 171     poc->xscom_size = PNV9_XSCOM_OCC_SIZE;
 172     poc->xscom_ops = &pnv_occ_power9_xscom_ops;
 173     poc->psi_irq = PSIHB9_IRQ_OCC;
 174 }
 175
 176 static const TypeInfo pnv_occ_power9_type_info = {
 177     .name          = TYPE_PNV9_OCC,
 178     .parent        = TYPE_PNV_OCC,
 179     .instance_size = sizeof(PnvOCC),
 180     .class_init    = pnv_occ_power9_class_init,
 181 };
 182
 183 static void pnv_occ_realize(DeviceState *dev, Error **errp)
 184 {
 185     PnvOCC *occ = PNV_OCC(dev);
 186     PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ);
 187     Object *obj;
 188     Error *local_err = NULL;
 189
 190     occ->occmisc = 0;
 191
 192     obj = object_property_get_link(OBJECT(dev), "psi", &local_err);
 193     if (!obj) {
 194         error_propagate(errp, local_err);
 195         error_prepend(errp, "required link 'psi' not found: ");
 196         return;
 197     }
 198     occ->psi = PNV_PSI(obj);
 199
 200     /* XScom region for OCC registers */
 201     pnv_xscom_region_init(&occ->xscom_regs, OBJECT(dev), poc->xscom_ops,
 202                           occ, "xscom-occ", poc->xscom_size);
 203 }
 204
 205 static void pnv_occ_class_init(ObjectClass *klass, void *data)
 206 {
 207     DeviceClass *dc = DEVICE_CLASS(klass);
 208
 209     dc->realize = pnv_occ_realize;
 210     dc->desc = "PowerNV OCC Controller";
 211 }
 212
 213 static const TypeInfo pnv_occ_type_info = {
 214     .name          = TYPE_PNV_OCC,
 215     .parent        = TYPE_DEVICE,
 216     .instance_size = sizeof(PnvOCC),
 217     .class_init    = pnv_occ_class_init,
 218     .class_size    = sizeof(PnvOCCClass),
 219     .abstract      = true,
 220 };
 221
 222 static void pnv_occ_register_types(void)
 223 {
 224     type_register_static(&pnv_occ_type_info);
 225     type_register_static(&pnv_occ_power8_type_info);
 226     type_register_static(&pnv_occ_power9_type_info);
 227 }
 228
 229 type_init(pnv_occ_register_types);