2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "qemu/osdep.h"
28 #include "qemu-common.h"
29 #include "qapi/error.h"
30 #include "qapi/visitor.h"
31 #include "sysemu/sysemu.h"
32 #include "sysemu/hostmem.h"
33 #include "sysemu/numa.h"
34 #include "sysemu/qtest.h"
35 #include "sysemu/reset.h"
36 #include "sysemu/runstate.h"
38 #include "hw/fw-path-provider.h"
41 #include "sysemu/device_tree.h"
42 #include "sysemu/cpus.h"
43 #include "sysemu/hw_accel.h"
45 #include "migration/misc.h"
46 #include "migration/qemu-file-types.h"
47 #include "migration/global_state.h"
48 #include "migration/register.h"
49 #include "migration/blocker.h"
50 #include "mmu-hash64.h"
51 #include "mmu-book3s-v3.h"
52 #include "cpu-models.h"
53 #include "hw/core/cpu.h"
55 #include "hw/boards.h"
56 #include "hw/ppc/ppc.h"
57 #include "hw/loader.h"
59 #include "hw/ppc/fdt.h"
60 #include "hw/ppc/spapr.h"
61 #include "hw/ppc/spapr_vio.h"
62 #include "hw/qdev-properties.h"
63 #include "hw/pci-host/spapr.h"
64 #include "hw/pci/msi.h"
66 #include "hw/pci/pci.h"
67 #include "hw/scsi/scsi.h"
68 #include "hw/virtio/virtio-scsi.h"
69 #include "hw/virtio/vhost-scsi-common.h"
71 #include "exec/address-spaces.h"
72 #include "exec/ram_addr.h"
74 #include "qemu/config-file.h"
75 #include "qemu/error-report.h"
78 #include "hw/intc/intc.h"
80 #include "hw/ppc/spapr_cpu_core.h"
81 #include "hw/mem/memory-device.h"
82 #include "hw/ppc/spapr_tpm_proxy.h"
83 #include "hw/ppc/spapr_nvdimm.h"
85 #include "monitor/monitor.h"
89 /* SLOF memory layout:
91 * SLOF raw image loaded at 0, copies its romfs right below the flat
92 * device-tree, then position SLOF itself 31M below that
94 * So we set FW_OVERHEAD to 40MB which should account for all of that
97 * We load our kernel at 4M, leaving space for SLOF initial image
99 #define FDT_MAX_SIZE 0x100000
100 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
101 #define FW_MAX_SIZE 0x400000
102 #define FW_FILE_NAME "slof.bin"
103 #define FW_OVERHEAD 0x2800000
104 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
106 #define MIN_RMA_SLOF 128UL
108 #define PHANDLE_INTC 0x00001111
110 /* These two functions implement the VCPU id numbering: one to compute them
111 * all and one to identify thread 0 of a VCORE. Any change to the first one
112 * is likely to have an impact on the second one, so let's keep them close.
114 static int spapr_vcpu_id(SpaprMachineState
*spapr
, int cpu_index
)
116 MachineState
*ms
= MACHINE(spapr
);
117 unsigned int smp_threads
= ms
->smp
.threads
;
121 (cpu_index
/ smp_threads
) * spapr
->vsmt
+ cpu_index
% smp_threads
;
123 static bool spapr_is_thread0_in_vcore(SpaprMachineState
*spapr
,
127 return spapr_get_vcpu_id(cpu
) % spapr
->vsmt
== 0;
130 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque
)
132 /* Dummy entries correspond to unused ICPState objects in older QEMUs,
133 * and newer QEMUs don't even have them. In both cases, we don't want
134 * to send anything on the wire.
139 static const VMStateDescription pre_2_10_vmstate_dummy_icp
= {
140 .name
= "icp/server",
142 .minimum_version_id
= 1,
143 .needed
= pre_2_10_vmstate_dummy_icp_needed
,
144 .fields
= (VMStateField
[]) {
145 VMSTATE_UNUSED(4), /* uint32_t xirr */
146 VMSTATE_UNUSED(1), /* uint8_t pending_priority */
147 VMSTATE_UNUSED(1), /* uint8_t mfrr */
148 VMSTATE_END_OF_LIST()
152 static void pre_2_10_vmstate_register_dummy_icp(int i
)
154 vmstate_register(NULL
, i
, &pre_2_10_vmstate_dummy_icp
,
155 (void *)(uintptr_t) i
);
158 static void pre_2_10_vmstate_unregister_dummy_icp(int i
)
160 vmstate_unregister(NULL
, &pre_2_10_vmstate_dummy_icp
,
161 (void *)(uintptr_t) i
);
164 int spapr_max_server_number(SpaprMachineState
*spapr
)
166 MachineState
*ms
= MACHINE(spapr
);
169 return DIV_ROUND_UP(ms
->smp
.max_cpus
* spapr
->vsmt
, ms
->smp
.threads
);
172 static int spapr_fixup_cpu_smt_dt(void *fdt
, int offset
, PowerPCCPU
*cpu
,
176 uint32_t servers_prop
[smt_threads
];
177 uint32_t gservers_prop
[smt_threads
* 2];
178 int index
= spapr_get_vcpu_id(cpu
);
180 if (cpu
->compat_pvr
) {
181 ret
= fdt_setprop_cell(fdt
, offset
, "cpu-version", cpu
->compat_pvr
);
187 /* Build interrupt servers and gservers properties */
188 for (i
= 0; i
< smt_threads
; i
++) {
189 servers_prop
[i
] = cpu_to_be32(index
+ i
);
190 /* Hack, direct the group queues back to cpu 0 */
191 gservers_prop
[i
*2] = cpu_to_be32(index
+ i
);
192 gservers_prop
[i
*2 + 1] = 0;
194 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-server#s",
195 servers_prop
, sizeof(servers_prop
));
199 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-gserver#s",
200 gservers_prop
, sizeof(gservers_prop
));
205 static int spapr_fixup_cpu_numa_dt(void *fdt
, int offset
, PowerPCCPU
*cpu
)
207 int index
= spapr_get_vcpu_id(cpu
);
208 uint32_t associativity
[] = {cpu_to_be32(0x5),
212 cpu_to_be32(cpu
->node_id
),
215 /* Advertise NUMA via ibm,associativity */
216 return fdt_setprop(fdt
, offset
, "ibm,associativity", associativity
,
217 sizeof(associativity
));
220 /* Populate the "ibm,pa-features" property */
221 static void spapr_populate_pa_features(SpaprMachineState
*spapr
,
223 void *fdt
, int offset
)
225 uint8_t pa_features_206
[] = { 6, 0,
226 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
227 uint8_t pa_features_207
[] = { 24, 0,
228 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
229 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
230 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
231 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
232 uint8_t pa_features_300
[] = { 66, 0,
233 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
234 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
235 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
237 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
239 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
240 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
241 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
242 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
243 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
244 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
245 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
246 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
247 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
248 /* 42: PM, 44: PC RA, 46: SC vec'd */
249 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
250 /* 48: SIMD, 50: QP BFP, 52: String */
251 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
252 /* 54: DecFP, 56: DecI, 58: SHA */
253 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
254 /* 60: NM atomic, 62: RNG */
255 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
257 uint8_t *pa_features
= NULL
;
260 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_2_06
, 0, cpu
->compat_pvr
)) {
261 pa_features
= pa_features_206
;
262 pa_size
= sizeof(pa_features_206
);
264 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_2_07
, 0, cpu
->compat_pvr
)) {
265 pa_features
= pa_features_207
;
266 pa_size
= sizeof(pa_features_207
);
268 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_3_00
, 0, cpu
->compat_pvr
)) {
269 pa_features
= pa_features_300
;
270 pa_size
= sizeof(pa_features_300
);
276 if (ppc_hash64_has(cpu
, PPC_HASH64_CI_LARGEPAGE
)) {
278 * Note: we keep CI large pages off by default because a 64K capable
279 * guest provisioned with large pages might otherwise try to map a qemu
280 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
281 * even if that qemu runs on a 4k host.
282 * We dd this bit back here if we are confident this is not an issue
284 pa_features
[3] |= 0x20;
286 if ((spapr_get_cap(spapr
, SPAPR_CAP_HTM
) != 0) && pa_size
> 24) {
287 pa_features
[24] |= 0x80; /* Transactional memory support */
289 if (spapr
->cas_pre_isa3_guest
&& pa_size
> 40) {
290 /* Workaround for broken kernels that attempt (guest) radix
291 * mode when they can't handle it, if they see the radix bit set
292 * in pa-features. So hide it from them. */
293 pa_features
[40 + 2] &= ~0x80; /* Radix MMU */
296 _FDT((fdt_setprop(fdt
, offset
, "ibm,pa-features", pa_features
, pa_size
)));
299 static hwaddr
spapr_node0_size(MachineState
*machine
)
301 if (machine
->numa_state
->num_nodes
) {
303 for (i
= 0; i
< machine
->numa_state
->num_nodes
; ++i
) {
304 if (machine
->numa_state
->nodes
[i
].node_mem
) {
305 return MIN(pow2floor(machine
->numa_state
->nodes
[i
].node_mem
),
310 return machine
->ram_size
;
313 static void add_str(GString
*s
, const gchar
*s1
)
315 g_string_append_len(s
, s1
, strlen(s1
) + 1);
318 static int spapr_populate_memory_node(void *fdt
, int nodeid
, hwaddr start
,
321 uint32_t associativity
[] = {
322 cpu_to_be32(0x4), /* length */
323 cpu_to_be32(0x0), cpu_to_be32(0x0),
324 cpu_to_be32(0x0), cpu_to_be32(nodeid
)
327 uint64_t mem_reg_property
[2];
330 mem_reg_property
[0] = cpu_to_be64(start
);
331 mem_reg_property
[1] = cpu_to_be64(size
);
333 sprintf(mem_name
, "memory@%" HWADDR_PRIx
, start
);
334 off
= fdt_add_subnode(fdt
, 0, mem_name
);
336 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
337 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
338 sizeof(mem_reg_property
))));
339 _FDT((fdt_setprop(fdt
, off
, "ibm,associativity", associativity
,
340 sizeof(associativity
))));
344 static int spapr_populate_memory(SpaprMachineState
*spapr
, void *fdt
)
346 MachineState
*machine
= MACHINE(spapr
);
347 hwaddr mem_start
, node_size
;
348 int i
, nb_nodes
= machine
->numa_state
->num_nodes
;
349 NodeInfo
*nodes
= machine
->numa_state
->nodes
;
351 for (i
= 0, mem_start
= 0; i
< nb_nodes
; ++i
) {
352 if (!nodes
[i
].node_mem
) {
355 if (mem_start
>= machine
->ram_size
) {
358 node_size
= nodes
[i
].node_mem
;
359 if (node_size
> machine
->ram_size
- mem_start
) {
360 node_size
= machine
->ram_size
- mem_start
;
364 /* spapr_machine_init() checks for rma_size <= node0_size
366 spapr_populate_memory_node(fdt
, i
, 0, spapr
->rma_size
);
367 mem_start
+= spapr
->rma_size
;
368 node_size
-= spapr
->rma_size
;
370 for ( ; node_size
; ) {
371 hwaddr sizetmp
= pow2floor(node_size
);
373 /* mem_start != 0 here */
374 if (ctzl(mem_start
) < ctzl(sizetmp
)) {
375 sizetmp
= 1ULL << ctzl(mem_start
);
378 spapr_populate_memory_node(fdt
, i
, mem_start
, sizetmp
);
379 node_size
-= sizetmp
;
380 mem_start
+= sizetmp
;
387 static void spapr_populate_cpu_dt(CPUState
*cs
, void *fdt
, int offset
,
388 SpaprMachineState
*spapr
)
390 MachineState
*ms
= MACHINE(spapr
);
391 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
392 CPUPPCState
*env
= &cpu
->env
;
393 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
394 int index
= spapr_get_vcpu_id(cpu
);
395 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
396 0xffffffff, 0xffffffff};
397 uint32_t tbfreq
= kvm_enabled() ? kvmppc_get_tbfreq()
398 : SPAPR_TIMEBASE_FREQ
;
399 uint32_t cpufreq
= kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
400 uint32_t page_sizes_prop
[64];
401 size_t page_sizes_prop_size
;
402 unsigned int smp_threads
= ms
->smp
.threads
;
403 uint32_t vcpus_per_socket
= smp_threads
* ms
->smp
.cores
;
404 uint32_t pft_size_prop
[] = {0, cpu_to_be32(spapr
->htab_shift
)};
405 int compat_smt
= MIN(smp_threads
, ppc_compat_max_vthreads(cpu
));
408 uint32_t radix_AP_encodings
[PPC_PAGE_SIZES_MAX_SZ
];
411 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
, index
);
413 drc_index
= spapr_drc_index(drc
);
414 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,my-drc-index", drc_index
)));
417 _FDT((fdt_setprop_cell(fdt
, offset
, "reg", index
)));
418 _FDT((fdt_setprop_string(fdt
, offset
, "device_type", "cpu")));
420 _FDT((fdt_setprop_cell(fdt
, offset
, "cpu-version", env
->spr
[SPR_PVR
])));
421 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-block-size",
422 env
->dcache_line_size
)));
423 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-line-size",
424 env
->dcache_line_size
)));
425 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-block-size",
426 env
->icache_line_size
)));
427 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-line-size",
428 env
->icache_line_size
)));
430 if (pcc
->l1_dcache_size
) {
431 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-size",
432 pcc
->l1_dcache_size
)));
434 warn_report("Unknown L1 dcache size for cpu");
436 if (pcc
->l1_icache_size
) {
437 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-size",
438 pcc
->l1_icache_size
)));
440 warn_report("Unknown L1 icache size for cpu");
443 _FDT((fdt_setprop_cell(fdt
, offset
, "timebase-frequency", tbfreq
)));
444 _FDT((fdt_setprop_cell(fdt
, offset
, "clock-frequency", cpufreq
)));
445 _FDT((fdt_setprop_cell(fdt
, offset
, "slb-size", cpu
->hash64_opts
->slb_size
)));
446 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,slb-size", cpu
->hash64_opts
->slb_size
)));
447 _FDT((fdt_setprop_string(fdt
, offset
, "status", "okay")));
448 _FDT((fdt_setprop(fdt
, offset
, "64-bit", NULL
, 0)));
450 if (env
->spr_cb
[SPR_PURR
].oea_read
) {
451 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,purr", 1)));
453 if (env
->spr_cb
[SPR_SPURR
].oea_read
) {
454 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,spurr", 1)));
457 if (ppc_hash64_has(cpu
, PPC_HASH64_1TSEG
)) {
458 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-segment-sizes",
459 segs
, sizeof(segs
))));
462 /* Advertise VSX (vector extensions) if available
463 * 1 == VMX / Altivec available
466 * Only CPUs for which we create core types in spapr_cpu_core.c
467 * are possible, and all of those have VMX */
468 if (spapr_get_cap(spapr
, SPAPR_CAP_VSX
) != 0) {
469 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", 2)));
471 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", 1)));
474 /* Advertise DFP (Decimal Floating Point) if available
475 * 0 / no property == no DFP
476 * 1 == DFP available */
477 if (spapr_get_cap(spapr
, SPAPR_CAP_DFP
) != 0) {
478 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,dfp", 1)));
481 page_sizes_prop_size
= ppc_create_page_sizes_prop(cpu
, page_sizes_prop
,
482 sizeof(page_sizes_prop
));
483 if (page_sizes_prop_size
) {
484 _FDT((fdt_setprop(fdt
, offset
, "ibm,segment-page-sizes",
485 page_sizes_prop
, page_sizes_prop_size
)));
488 spapr_populate_pa_features(spapr
, cpu
, fdt
, offset
);
490 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,chip-id",
491 cs
->cpu_index
/ vcpus_per_socket
)));
493 _FDT((fdt_setprop(fdt
, offset
, "ibm,pft-size",
494 pft_size_prop
, sizeof(pft_size_prop
))));
496 if (ms
->numa_state
->num_nodes
> 1) {
497 _FDT(spapr_fixup_cpu_numa_dt(fdt
, offset
, cpu
));
500 _FDT(spapr_fixup_cpu_smt_dt(fdt
, offset
, cpu
, compat_smt
));
502 if (pcc
->radix_page_info
) {
503 for (i
= 0; i
< pcc
->radix_page_info
->count
; i
++) {
504 radix_AP_encodings
[i
] =
505 cpu_to_be32(pcc
->radix_page_info
->entries
[i
]);
507 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-radix-AP-encodings",
509 pcc
->radix_page_info
->count
*
510 sizeof(radix_AP_encodings
[0]))));
514 * We set this property to let the guest know that it can use the large
515 * decrementer and its width in bits.
517 if (spapr_get_cap(spapr
, SPAPR_CAP_LARGE_DECREMENTER
) != SPAPR_CAP_OFF
)
518 _FDT((fdt_setprop_u32(fdt
, offset
, "ibm,dec-bits",
519 pcc
->lrg_decr_bits
)));
522 static void spapr_populate_cpus_dt_node(void *fdt
, SpaprMachineState
*spapr
)
531 cpus_offset
= fdt_add_subnode(fdt
, 0, "cpus");
533 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#address-cells", 0x1)));
534 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#size-cells", 0x0)));
537 * We walk the CPUs in reverse order to ensure that CPU DT nodes
538 * created by fdt_add_subnode() end up in the right order in FDT
539 * for the guest kernel the enumerate the CPUs correctly.
541 * The CPU list cannot be traversed in reverse order, so we need
547 rev
= g_renew(CPUState
*, rev
, n_cpus
+ 1);
551 for (i
= n_cpus
- 1; i
>= 0; i
--) {
552 CPUState
*cs
= rev
[i
];
553 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
554 int index
= spapr_get_vcpu_id(cpu
);
555 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
558 if (!spapr_is_thread0_in_vcore(spapr
, cpu
)) {
562 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, index
);
563 offset
= fdt_add_subnode(fdt
, cpus_offset
, nodename
);
566 spapr_populate_cpu_dt(cs
, fdt
, offset
, spapr
);
572 static int spapr_rng_populate_dt(void *fdt
)
577 node
= qemu_fdt_add_subnode(fdt
, "/ibm,platform-facilities");
581 ret
= fdt_setprop_string(fdt
, node
, "device_type",
582 "ibm,platform-facilities");
583 ret
|= fdt_setprop_cell(fdt
, node
, "#address-cells", 0x1);
584 ret
|= fdt_setprop_cell(fdt
, node
, "#size-cells", 0x0);
586 node
= fdt_add_subnode(fdt
, node
, "ibm,random-v1");
590 ret
|= fdt_setprop_string(fdt
, node
, "compatible", "ibm,random");
595 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList
*list
, ram_addr_t addr
)
597 MemoryDeviceInfoList
*info
;
599 for (info
= list
; info
; info
= info
->next
) {
600 MemoryDeviceInfo
*value
= info
->value
;
602 if (value
&& value
->type
== MEMORY_DEVICE_INFO_KIND_DIMM
) {
603 PCDIMMDeviceInfo
*pcdimm_info
= value
->u
.dimm
.data
;
605 if (addr
>= pcdimm_info
->addr
&&
606 addr
< (pcdimm_info
->addr
+ pcdimm_info
->size
)) {
607 return pcdimm_info
->node
;
615 struct sPAPRDrconfCellV2
{
623 typedef struct DrconfCellQueue
{
624 struct sPAPRDrconfCellV2 cell
;
625 QSIMPLEQ_ENTRY(DrconfCellQueue
) entry
;
628 static DrconfCellQueue
*
629 spapr_get_drconf_cell(uint32_t seq_lmbs
, uint64_t base_addr
,
630 uint32_t drc_index
, uint32_t aa_index
,
633 DrconfCellQueue
*elem
;
635 elem
= g_malloc0(sizeof(*elem
));
636 elem
->cell
.seq_lmbs
= cpu_to_be32(seq_lmbs
);
637 elem
->cell
.base_addr
= cpu_to_be64(base_addr
);
638 elem
->cell
.drc_index
= cpu_to_be32(drc_index
);
639 elem
->cell
.aa_index
= cpu_to_be32(aa_index
);
640 elem
->cell
.flags
= cpu_to_be32(flags
);
645 /* ibm,dynamic-memory-v2 */
646 static int spapr_populate_drmem_v2(SpaprMachineState
*spapr
, void *fdt
,
647 int offset
, MemoryDeviceInfoList
*dimms
)
649 MachineState
*machine
= MACHINE(spapr
);
650 uint8_t *int_buf
, *cur_index
;
652 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
653 uint64_t addr
, cur_addr
, size
;
654 uint32_t nr_boot_lmbs
= (machine
->device_memory
->base
/ lmb_size
);
655 uint64_t mem_end
= machine
->device_memory
->base
+
656 memory_region_size(&machine
->device_memory
->mr
);
657 uint32_t node
, buf_len
, nr_entries
= 0;
659 DrconfCellQueue
*elem
, *next
;
660 MemoryDeviceInfoList
*info
;
661 QSIMPLEQ_HEAD(, DrconfCellQueue
) drconf_queue
662 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue
);
664 /* Entry to cover RAM and the gap area */
665 elem
= spapr_get_drconf_cell(nr_boot_lmbs
, 0, 0, -1,
666 SPAPR_LMB_FLAGS_RESERVED
|
667 SPAPR_LMB_FLAGS_DRC_INVALID
);
668 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
671 cur_addr
= machine
->device_memory
->base
;
672 for (info
= dimms
; info
; info
= info
->next
) {
673 PCDIMMDeviceInfo
*di
= info
->value
->u
.dimm
.data
;
680 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The
681 * area is marked hotpluggable in the next iteration for the bigger
682 * chunk including the NVDIMM occupied area.
684 if (info
->value
->type
== MEMORY_DEVICE_INFO_KIND_NVDIMM
)
687 /* Entry for hot-pluggable area */
688 if (cur_addr
< addr
) {
689 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, cur_addr
/ lmb_size
);
691 elem
= spapr_get_drconf_cell((addr
- cur_addr
) / lmb_size
,
692 cur_addr
, spapr_drc_index(drc
), -1, 0);
693 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
698 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, addr
/ lmb_size
);
700 elem
= spapr_get_drconf_cell(size
/ lmb_size
, addr
,
701 spapr_drc_index(drc
), node
,
702 SPAPR_LMB_FLAGS_ASSIGNED
);
703 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
705 cur_addr
= addr
+ size
;
708 /* Entry for remaining hotpluggable area */
709 if (cur_addr
< mem_end
) {
710 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, cur_addr
/ lmb_size
);
712 elem
= spapr_get_drconf_cell((mem_end
- cur_addr
) / lmb_size
,
713 cur_addr
, spapr_drc_index(drc
), -1, 0);
714 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
718 buf_len
= nr_entries
* sizeof(struct sPAPRDrconfCellV2
) + sizeof(uint32_t);
719 int_buf
= cur_index
= g_malloc0(buf_len
);
720 *(uint32_t *)int_buf
= cpu_to_be32(nr_entries
);
721 cur_index
+= sizeof(nr_entries
);
723 QSIMPLEQ_FOREACH_SAFE(elem
, &drconf_queue
, entry
, next
) {
724 memcpy(cur_index
, &elem
->cell
, sizeof(elem
->cell
));
725 cur_index
+= sizeof(elem
->cell
);
726 QSIMPLEQ_REMOVE(&drconf_queue
, elem
, DrconfCellQueue
, entry
);
730 ret
= fdt_setprop(fdt
, offset
, "ibm,dynamic-memory-v2", int_buf
, buf_len
);
738 /* ibm,dynamic-memory */
739 static int spapr_populate_drmem_v1(SpaprMachineState
*spapr
, void *fdt
,
740 int offset
, MemoryDeviceInfoList
*dimms
)
742 MachineState
*machine
= MACHINE(spapr
);
744 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
745 uint32_t device_lmb_start
= machine
->device_memory
->base
/ lmb_size
;
746 uint32_t nr_lmbs
= (machine
->device_memory
->base
+
747 memory_region_size(&machine
->device_memory
->mr
)) /
749 uint32_t *int_buf
, *cur_index
, buf_len
;
752 * Allocate enough buffer size to fit in ibm,dynamic-memory
754 buf_len
= (nr_lmbs
* SPAPR_DR_LMB_LIST_ENTRY_SIZE
+ 1) * sizeof(uint32_t);
755 cur_index
= int_buf
= g_malloc0(buf_len
);
756 int_buf
[0] = cpu_to_be32(nr_lmbs
);
758 for (i
= 0; i
< nr_lmbs
; i
++) {
759 uint64_t addr
= i
* lmb_size
;
760 uint32_t *dynamic_memory
= cur_index
;
762 if (i
>= device_lmb_start
) {
765 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, i
);
768 dynamic_memory
[0] = cpu_to_be32(addr
>> 32);
769 dynamic_memory
[1] = cpu_to_be32(addr
& 0xffffffff);
770 dynamic_memory
[2] = cpu_to_be32(spapr_drc_index(drc
));
771 dynamic_memory
[3] = cpu_to_be32(0); /* reserved */
772 dynamic_memory
[4] = cpu_to_be32(spapr_pc_dimm_node(dimms
, addr
));
773 if (memory_region_present(get_system_memory(), addr
)) {
774 dynamic_memory
[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED
);
776 dynamic_memory
[5] = cpu_to_be32(0);
780 * LMB information for RMA, boot time RAM and gap b/n RAM and
781 * device memory region -- all these are marked as reserved
782 * and as having no valid DRC.
784 dynamic_memory
[0] = cpu_to_be32(addr
>> 32);
785 dynamic_memory
[1] = cpu_to_be32(addr
& 0xffffffff);
786 dynamic_memory
[2] = cpu_to_be32(0);
787 dynamic_memory
[3] = cpu_to_be32(0); /* reserved */
788 dynamic_memory
[4] = cpu_to_be32(-1);
789 dynamic_memory
[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED
|
790 SPAPR_LMB_FLAGS_DRC_INVALID
);
793 cur_index
+= SPAPR_DR_LMB_LIST_ENTRY_SIZE
;
795 ret
= fdt_setprop(fdt
, offset
, "ibm,dynamic-memory", int_buf
, buf_len
);
804 * Adds ibm,dynamic-reconfiguration-memory node.
805 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
806 * of this device tree node.
808 static int spapr_populate_drconf_memory(SpaprMachineState
*spapr
, void *fdt
)
810 MachineState
*machine
= MACHINE(spapr
);
811 int nb_numa_nodes
= machine
->numa_state
->num_nodes
;
813 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
814 uint32_t prop_lmb_size
[] = {0, cpu_to_be32(lmb_size
)};
815 uint32_t *int_buf
, *cur_index
, buf_len
;
816 int nr_nodes
= nb_numa_nodes
? nb_numa_nodes
: 1;
817 MemoryDeviceInfoList
*dimms
= NULL
;
820 * Don't create the node if there is no device memory
822 if (machine
->ram_size
== machine
->maxram_size
) {
826 offset
= fdt_add_subnode(fdt
, 0, "ibm,dynamic-reconfiguration-memory");
828 ret
= fdt_setprop(fdt
, offset
, "ibm,lmb-size", prop_lmb_size
,
829 sizeof(prop_lmb_size
));
834 ret
= fdt_setprop_cell(fdt
, offset
, "ibm,memory-flags-mask", 0xff);
839 ret
= fdt_setprop_cell(fdt
, offset
, "ibm,memory-preservation-time", 0x0);
844 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */
845 dimms
= qmp_memory_device_list();
846 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_DRMEM_V2
)) {
847 ret
= spapr_populate_drmem_v2(spapr
, fdt
, offset
, dimms
);
849 ret
= spapr_populate_drmem_v1(spapr
, fdt
, offset
, dimms
);
851 qapi_free_MemoryDeviceInfoList(dimms
);
857 /* ibm,associativity-lookup-arrays */
858 buf_len
= (nr_nodes
* 4 + 2) * sizeof(uint32_t);
859 cur_index
= int_buf
= g_malloc0(buf_len
);
860 int_buf
[0] = cpu_to_be32(nr_nodes
);
861 int_buf
[1] = cpu_to_be32(4); /* Number of entries per associativity list */
863 for (i
= 0; i
< nr_nodes
; i
++) {
864 uint32_t associativity
[] = {
870 memcpy(cur_index
, associativity
, sizeof(associativity
));
873 ret
= fdt_setprop(fdt
, offset
, "ibm,associativity-lookup-arrays", int_buf
,
874 (cur_index
- int_buf
) * sizeof(uint32_t));
880 static int spapr_dt_cas_updates(SpaprMachineState
*spapr
, void *fdt
,
881 SpaprOptionVector
*ov5_updates
)
883 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
886 /* Generate ibm,dynamic-reconfiguration-memory node if required */
887 if (spapr_ovec_test(ov5_updates
, OV5_DRCONF_MEMORY
)) {
888 g_assert(smc
->dr_lmb_enabled
);
889 ret
= spapr_populate_drconf_memory(spapr
, fdt
);
895 offset
= fdt_path_offset(fdt
, "/chosen");
897 offset
= fdt_add_subnode(fdt
, 0, "chosen");
902 return spapr_ovec_populate_dt(fdt
, offset
, spapr
->ov5_cas
,
903 "ibm,architecture-vec-5");
906 static void spapr_dt_rtas(SpaprMachineState
*spapr
, void *fdt
)
908 MachineState
*ms
= MACHINE(spapr
);
910 GString
*hypertas
= g_string_sized_new(256);
911 GString
*qemu_hypertas
= g_string_sized_new(256);
912 uint32_t refpoints
[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
913 uint64_t max_device_addr
= MACHINE(spapr
)->device_memory
->base
+
914 memory_region_size(&MACHINE(spapr
)->device_memory
->mr
);
915 uint32_t lrdr_capacity
[] = {
916 cpu_to_be32(max_device_addr
>> 32),
917 cpu_to_be32(max_device_addr
& 0xffffffff),
918 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE
),
919 cpu_to_be32(ms
->smp
.max_cpus
/ ms
->smp
.threads
),
921 uint32_t maxdomain
= cpu_to_be32(spapr
->gpu_numa_id
> 1 ? 1 : 0);
922 uint32_t maxdomains
[] = {
927 cpu_to_be32(spapr
->gpu_numa_id
),
930 _FDT(rtas
= fdt_add_subnode(fdt
, 0, "rtas"));
933 add_str(hypertas
, "hcall-pft");
934 add_str(hypertas
, "hcall-term");
935 add_str(hypertas
, "hcall-dabr");
936 add_str(hypertas
, "hcall-interrupt");
937 add_str(hypertas
, "hcall-tce");
938 add_str(hypertas
, "hcall-vio");
939 add_str(hypertas
, "hcall-splpar");
940 add_str(hypertas
, "hcall-join");
941 add_str(hypertas
, "hcall-bulk");
942 add_str(hypertas
, "hcall-set-mode");
943 add_str(hypertas
, "hcall-sprg0");
944 add_str(hypertas
, "hcall-copy");
945 add_str(hypertas
, "hcall-debug");
946 add_str(hypertas
, "hcall-vphn");
947 add_str(qemu_hypertas
, "hcall-memop1");
949 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
950 add_str(hypertas
, "hcall-multi-tce");
953 if (spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) {
954 add_str(hypertas
, "hcall-hpt-resize");
957 _FDT(fdt_setprop(fdt
, rtas
, "ibm,hypertas-functions",
958 hypertas
->str
, hypertas
->len
));
959 g_string_free(hypertas
, TRUE
);
960 _FDT(fdt_setprop(fdt
, rtas
, "qemu,hypertas-functions",
961 qemu_hypertas
->str
, qemu_hypertas
->len
));
962 g_string_free(qemu_hypertas
, TRUE
);
964 _FDT(fdt_setprop(fdt
, rtas
, "ibm,associativity-reference-points",
965 refpoints
, sizeof(refpoints
)));
967 _FDT(fdt_setprop(fdt
, rtas
, "ibm,max-associativity-domains",
968 maxdomains
, sizeof(maxdomains
)));
970 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-error-log-max",
971 RTAS_ERROR_LOG_MAX
));
972 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-event-scan-rate",
973 RTAS_EVENT_SCAN_RATE
));
975 g_assert(msi_nonbroken
);
976 _FDT(fdt_setprop(fdt
, rtas
, "ibm,change-msix-capable", NULL
, 0));
979 * According to PAPR, rtas ibm,os-term does not guarantee a return
980 * back to the guest cpu.
982 * While an additional ibm,extended-os-term property indicates
983 * that rtas call return will always occur. Set this property.
985 _FDT(fdt_setprop(fdt
, rtas
, "ibm,extended-os-term", NULL
, 0));
987 _FDT(fdt_setprop(fdt
, rtas
, "ibm,lrdr-capacity",
988 lrdr_capacity
, sizeof(lrdr_capacity
)));
990 spapr_dt_rtas_tokens(fdt
, rtas
);
994 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU
995 * and the XIVE features that the guest may request and thus the valid
996 * values for bytes 23..26 of option vector 5:
998 static void spapr_dt_ov5_platform_support(SpaprMachineState
*spapr
, void *fdt
,
1001 PowerPCCPU
*first_ppc_cpu
= POWERPC_CPU(first_cpu
);
1004 23, 0x00, /* XICS / XIVE mode */
1005 24, 0x00, /* Hash/Radix, filled in below. */
1006 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
1007 26, 0x40, /* Radix options: GTSE == yes. */
1010 if (spapr
->irq
->xics
&& spapr
->irq
->xive
) {
1011 val
[1] = SPAPR_OV5_XIVE_BOTH
;
1012 } else if (spapr
->irq
->xive
) {
1013 val
[1] = SPAPR_OV5_XIVE_EXPLOIT
;
1015 assert(spapr
->irq
->xics
);
1016 val
[1] = SPAPR_OV5_XIVE_LEGACY
;
1019 if (!ppc_check_compat(first_ppc_cpu
, CPU_POWERPC_LOGICAL_3_00
, 0,
1020 first_ppc_cpu
->compat_pvr
)) {
1022 * If we're in a pre POWER9 compat mode then the guest should
1023 * do hash and use the legacy interrupt mode
1025 val
[1] = SPAPR_OV5_XIVE_LEGACY
; /* XICS */
1026 val
[3] = 0x00; /* Hash */
1027 } else if (kvm_enabled()) {
1028 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
1029 val
[3] = 0x80; /* OV5_MMU_BOTH */
1030 } else if (kvmppc_has_cap_mmu_radix()) {
1031 val
[3] = 0x40; /* OV5_MMU_RADIX_300 */
1033 val
[3] = 0x00; /* Hash */
1036 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */
1039 _FDT(fdt_setprop(fdt
, chosen
, "ibm,arch-vec-5-platform-support",
1043 static void spapr_dt_chosen(SpaprMachineState
*spapr
, void *fdt
)
1045 MachineState
*machine
= MACHINE(spapr
);
1046 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
1048 const char *boot_device
= machine
->boot_order
;
1049 char *stdout_path
= spapr_vio_stdout_path(spapr
->vio_bus
);
1051 char *bootlist
= get_boot_devices_list(&cb
);
1053 _FDT(chosen
= fdt_add_subnode(fdt
, 0, "chosen"));
1055 if (machine
->kernel_cmdline
&& machine
->kernel_cmdline
[0]) {
1056 _FDT(fdt_setprop_string(fdt
, chosen
, "bootargs",
1057 machine
->kernel_cmdline
));
1059 if (spapr
->initrd_size
) {
1060 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,initrd-start",
1061 spapr
->initrd_base
));
1062 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,initrd-end",
1063 spapr
->initrd_base
+ spapr
->initrd_size
));
1066 if (spapr
->kernel_size
) {
1067 uint64_t kprop
[2] = { cpu_to_be64(spapr
->kernel_addr
),
1068 cpu_to_be64(spapr
->kernel_size
) };
1070 _FDT(fdt_setprop(fdt
, chosen
, "qemu,boot-kernel",
1071 &kprop
, sizeof(kprop
)));
1072 if (spapr
->kernel_le
) {
1073 _FDT(fdt_setprop(fdt
, chosen
, "qemu,boot-kernel-le", NULL
, 0));
1077 _FDT((fdt_setprop_cell(fdt
, chosen
, "qemu,boot-menu", boot_menu
)));
1079 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-width", graphic_width
));
1080 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-height", graphic_height
));
1081 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-depth", graphic_depth
));
1083 if (cb
&& bootlist
) {
1086 for (i
= 0; i
< cb
; i
++) {
1087 if (bootlist
[i
] == '\n') {
1091 _FDT(fdt_setprop_string(fdt
, chosen
, "qemu,boot-list", bootlist
));
1094 if (boot_device
&& strlen(boot_device
)) {
1095 _FDT(fdt_setprop_string(fdt
, chosen
, "qemu,boot-device", boot_device
));
1098 if (!spapr
->has_graphics
&& stdout_path
) {
1100 * "linux,stdout-path" and "stdout" properties are deprecated by linux
1101 * kernel. New platforms should only use the "stdout-path" property. Set
1102 * the new property and continue using older property to remain
1103 * compatible with the existing firmware.
1105 _FDT(fdt_setprop_string(fdt
, chosen
, "linux,stdout-path", stdout_path
));
1106 _FDT(fdt_setprop_string(fdt
, chosen
, "stdout-path", stdout_path
));
1109 /* We can deal with BAR reallocation just fine, advertise it to the guest */
1110 if (smc
->linux_pci_probe
) {
1111 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,pci-probe-only", 0));
1114 spapr_dt_ov5_platform_support(spapr
, fdt
, chosen
);
1116 g_free(stdout_path
);
1120 static void spapr_dt_hypervisor(SpaprMachineState
*spapr
, void *fdt
)
1122 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
1123 * KVM to work under pHyp with some guest co-operation */
1125 uint8_t hypercall
[16];
1127 _FDT(hypervisor
= fdt_add_subnode(fdt
, 0, "hypervisor"));
1128 /* indicate KVM hypercall interface */
1129 _FDT(fdt_setprop_string(fdt
, hypervisor
, "compatible", "linux,kvm"));
1130 if (kvmppc_has_cap_fixup_hcalls()) {
1132 * Older KVM versions with older guest kernels were broken
1133 * with the magic page, don't allow the guest to map it.
1135 if (!kvmppc_get_hypercall(first_cpu
->env_ptr
, hypercall
,
1136 sizeof(hypercall
))) {
1137 _FDT(fdt_setprop(fdt
, hypervisor
, "hcall-instructions",
1138 hypercall
, sizeof(hypercall
)));
1143 void *spapr_build_fdt(SpaprMachineState
*spapr
, bool reset
, size_t space
)
1145 MachineState
*machine
= MACHINE(spapr
);
1146 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1147 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
1153 fdt
= g_malloc0(space
);
1154 _FDT((fdt_create_empty_tree(fdt
, space
)));
1157 _FDT(fdt_setprop_string(fdt
, 0, "device_type", "chrp"));
1158 _FDT(fdt_setprop_string(fdt
, 0, "model", "IBM pSeries (emulated by qemu)"));
1159 _FDT(fdt_setprop_string(fdt
, 0, "compatible", "qemu,pseries"));
1161 /* Guest UUID & Name*/
1162 buf
= qemu_uuid_unparse_strdup(&qemu_uuid
);
1163 _FDT(fdt_setprop_string(fdt
, 0, "vm,uuid", buf
));
1164 if (qemu_uuid_set
) {
1165 _FDT(fdt_setprop_string(fdt
, 0, "system-id", buf
));
1169 if (qemu_get_vm_name()) {
1170 _FDT(fdt_setprop_string(fdt
, 0, "ibm,partition-name",
1171 qemu_get_vm_name()));
1174 /* Host Model & Serial Number */
1175 if (spapr
->host_model
) {
1176 _FDT(fdt_setprop_string(fdt
, 0, "host-model", spapr
->host_model
));
1177 } else if (smc
->broken_host_serial_model
&& kvmppc_get_host_model(&buf
)) {
1178 _FDT(fdt_setprop_string(fdt
, 0, "host-model", buf
));
1182 if (spapr
->host_serial
) {
1183 _FDT(fdt_setprop_string(fdt
, 0, "host-serial", spapr
->host_serial
));
1184 } else if (smc
->broken_host_serial_model
&& kvmppc_get_host_serial(&buf
)) {
1185 _FDT(fdt_setprop_string(fdt
, 0, "host-serial", buf
));
1189 _FDT(fdt_setprop_cell(fdt
, 0, "#address-cells", 2));
1190 _FDT(fdt_setprop_cell(fdt
, 0, "#size-cells", 2));
1192 /* /interrupt controller */
1193 spapr_irq_dt(spapr
, spapr_max_server_number(spapr
), fdt
, PHANDLE_INTC
);
1195 ret
= spapr_populate_memory(spapr
, fdt
);
1197 error_report("couldn't setup memory nodes in fdt");
1202 spapr_dt_vdevice(spapr
->vio_bus
, fdt
);
1204 if (object_resolve_path_type("", TYPE_SPAPR_RNG
, NULL
)) {
1205 ret
= spapr_rng_populate_dt(fdt
);
1207 error_report("could not set up rng device in the fdt");
1212 QLIST_FOREACH(phb
, &spapr
->phbs
, list
) {
1213 ret
= spapr_dt_phb(spapr
, phb
, PHANDLE_INTC
, fdt
, NULL
);
1215 error_report("couldn't setup PCI devices in fdt");
1221 spapr_populate_cpus_dt_node(fdt
, spapr
);
1223 if (smc
->dr_lmb_enabled
) {
1224 _FDT(spapr_dt_drc(fdt
, 0, NULL
, SPAPR_DR_CONNECTOR_TYPE_LMB
));
1227 if (mc
->has_hotpluggable_cpus
) {
1228 int offset
= fdt_path_offset(fdt
, "/cpus");
1229 ret
= spapr_dt_drc(fdt
, offset
, NULL
, SPAPR_DR_CONNECTOR_TYPE_CPU
);
1231 error_report("Couldn't set up CPU DR device tree properties");
1236 /* /event-sources */
1237 spapr_dt_events(spapr
, fdt
);
1240 spapr_dt_rtas(spapr
, fdt
);
1244 spapr_dt_chosen(spapr
, fdt
);
1248 if (kvm_enabled()) {
1249 spapr_dt_hypervisor(spapr
, fdt
);
1252 /* Build memory reserve map */
1254 if (spapr
->kernel_size
) {
1255 _FDT((fdt_add_mem_rsv(fdt
, spapr
->kernel_addr
,
1256 spapr
->kernel_size
)));
1258 if (spapr
->initrd_size
) {
1259 _FDT((fdt_add_mem_rsv(fdt
, spapr
->initrd_base
,
1260 spapr
->initrd_size
)));
1264 /* ibm,client-architecture-support updates */
1265 ret
= spapr_dt_cas_updates(spapr
, fdt
, spapr
->ov5_cas
);
1267 error_report("couldn't setup CAS properties fdt");
1271 if (smc
->dr_phb_enabled
) {
1272 ret
= spapr_dt_drc(fdt
, 0, NULL
, SPAPR_DR_CONNECTOR_TYPE_PHB
);
1274 error_report("Couldn't set up PHB DR device tree properties");
1279 /* NVDIMM devices */
1280 if (mc
->nvdimm_supported
) {
1281 spapr_dt_persistent_memory(fdt
);
1287 static uint64_t translate_kernel_address(void *opaque
, uint64_t addr
)
1289 SpaprMachineState
*spapr
= opaque
;
1291 return (addr
& 0x0fffffff) + spapr
->kernel_addr
;
1294 static void emulate_spapr_hypercall(PPCVirtualHypervisor
*vhyp
,
1297 CPUPPCState
*env
= &cpu
->env
;
1299 /* The TCG path should also be holding the BQL at this point */
1300 g_assert(qemu_mutex_iothread_locked());
1303 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1304 env
->gpr
[3] = H_PRIVILEGE
;
1306 env
->gpr
[3] = spapr_hypercall(cpu
, env
->gpr
[3], &env
->gpr
[4]);
1310 struct LPCRSyncState
{
1315 static void do_lpcr_sync(CPUState
*cs
, run_on_cpu_data arg
)
1317 struct LPCRSyncState
*s
= arg
.host_ptr
;
1318 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1319 CPUPPCState
*env
= &cpu
->env
;
1322 cpu_synchronize_state(cs
);
1323 lpcr
= env
->spr
[SPR_LPCR
];
1326 ppc_store_lpcr(cpu
, lpcr
);
1329 void spapr_set_all_lpcrs(target_ulong value
, target_ulong mask
)
1332 struct LPCRSyncState s
= {
1337 run_on_cpu(cs
, do_lpcr_sync
, RUN_ON_CPU_HOST_PTR(&s
));
1341 static void spapr_get_pate(PPCVirtualHypervisor
*vhyp
, ppc_v3_pate_t
*entry
)
1343 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1345 /* Copy PATE1:GR into PATE0:HR */
1346 entry
->dw0
= spapr
->patb_entry
& PATE0_HR
;
1347 entry
->dw1
= spapr
->patb_entry
;
1350 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1351 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1352 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1353 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1354 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1357 * Get the fd to access the kernel htab, re-opening it if necessary
1359 static int get_htab_fd(SpaprMachineState
*spapr
)
1361 Error
*local_err
= NULL
;
1363 if (spapr
->htab_fd
>= 0) {
1364 return spapr
->htab_fd
;
1367 spapr
->htab_fd
= kvmppc_get_htab_fd(false, 0, &local_err
);
1368 if (spapr
->htab_fd
< 0) {
1369 error_report_err(local_err
);
1372 return spapr
->htab_fd
;
1375 void close_htab_fd(SpaprMachineState
*spapr
)
1377 if (spapr
->htab_fd
>= 0) {
1378 close(spapr
->htab_fd
);
1380 spapr
->htab_fd
= -1;
1383 static hwaddr
spapr_hpt_mask(PPCVirtualHypervisor
*vhyp
)
1385 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1387 return HTAB_SIZE(spapr
) / HASH_PTEG_SIZE_64
- 1;
1390 static target_ulong
spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor
*vhyp
)
1392 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1394 assert(kvm_enabled());
1400 return (target_ulong
)(uintptr_t)spapr
->htab
| (spapr
->htab_shift
- 18);
1403 static const ppc_hash_pte64_t
*spapr_map_hptes(PPCVirtualHypervisor
*vhyp
,
1406 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1407 hwaddr pte_offset
= ptex
* HASH_PTE_SIZE_64
;
1411 * HTAB is controlled by KVM. Fetch into temporary buffer
1413 ppc_hash_pte64_t
*hptes
= g_malloc(n
* HASH_PTE_SIZE_64
);
1414 kvmppc_read_hptes(hptes
, ptex
, n
);
1419 * HTAB is controlled by QEMU. Just point to the internally
1422 return (const ppc_hash_pte64_t
*)(spapr
->htab
+ pte_offset
);
1425 static void spapr_unmap_hptes(PPCVirtualHypervisor
*vhyp
,
1426 const ppc_hash_pte64_t
*hptes
,
1429 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1432 g_free((void *)hptes
);
1435 /* Nothing to do for qemu managed HPT */
1438 void spapr_store_hpte(PowerPCCPU
*cpu
, hwaddr ptex
,
1439 uint64_t pte0
, uint64_t pte1
)
1441 SpaprMachineState
*spapr
= SPAPR_MACHINE(cpu
->vhyp
);
1442 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
;
1445 kvmppc_write_hpte(ptex
, pte0
, pte1
);
1447 if (pte0
& HPTE64_V_VALID
) {
1448 stq_p(spapr
->htab
+ offset
+ HASH_PTE_SIZE_64
/ 2, pte1
);
1450 * When setting valid, we write PTE1 first. This ensures
1451 * proper synchronization with the reading code in
1452 * ppc_hash64_pteg_search()
1455 stq_p(spapr
->htab
+ offset
, pte0
);
1457 stq_p(spapr
->htab
+ offset
, pte0
);
1459 * When clearing it we set PTE0 first. This ensures proper
1460 * synchronization with the reading code in
1461 * ppc_hash64_pteg_search()
1464 stq_p(spapr
->htab
+ offset
+ HASH_PTE_SIZE_64
/ 2, pte1
);
1469 static void spapr_hpte_set_c(PPCVirtualHypervisor
*vhyp
, hwaddr ptex
,
1472 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
+ 15;
1473 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1476 /* There should always be a hash table when this is called */
1477 error_report("spapr_hpte_set_c called with no hash table !");
1481 /* The HW performs a non-atomic byte update */
1482 stb_p(spapr
->htab
+ offset
, (pte1
& 0xff) | 0x80);
1485 static void spapr_hpte_set_r(PPCVirtualHypervisor
*vhyp
, hwaddr ptex
,
1488 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
+ 14;
1489 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1492 /* There should always be a hash table when this is called */
1493 error_report("spapr_hpte_set_r called with no hash table !");
1497 /* The HW performs a non-atomic byte update */
1498 stb_p(spapr
->htab
+ offset
, ((pte1
>> 8) & 0xff) | 0x01);
1501 int spapr_hpt_shift_for_ramsize(uint64_t ramsize
)
1505 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1506 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1507 * that's much more than is needed for Linux guests */
1508 shift
= ctz64(pow2ceil(ramsize
)) - 7;
1509 shift
= MAX(shift
, 18); /* Minimum architected size */
1510 shift
= MIN(shift
, 46); /* Maximum architected size */
1514 void spapr_free_hpt(SpaprMachineState
*spapr
)
1516 g_free(spapr
->htab
);
1518 spapr
->htab_shift
= 0;
1519 close_htab_fd(spapr
);
1522 void spapr_reallocate_hpt(SpaprMachineState
*spapr
, int shift
,
1527 /* Clean up any HPT info from a previous boot */
1528 spapr_free_hpt(spapr
);
1530 rc
= kvmppc_reset_htab(shift
);
1532 /* kernel-side HPT needed, but couldn't allocate one */
1533 error_setg_errno(errp
, errno
,
1534 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1536 /* This is almost certainly fatal, but if the caller really
1537 * wants to carry on with shift == 0, it's welcome to try */
1538 } else if (rc
> 0) {
1539 /* kernel-side HPT allocated */
1542 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1546 spapr
->htab_shift
= shift
;
1549 /* kernel-side HPT not needed, allocate in userspace instead */
1550 size_t size
= 1ULL << shift
;
1553 spapr
->htab
= qemu_memalign(size
, size
);
1555 error_setg_errno(errp
, errno
,
1556 "Could not allocate HPT of order %d", shift
);
1560 memset(spapr
->htab
, 0, size
);
1561 spapr
->htab_shift
= shift
;
1563 for (i
= 0; i
< size
/ HASH_PTE_SIZE_64
; i
++) {
1564 DIRTY_HPTE(HPTE(spapr
->htab
, i
));
1567 /* We're setting up a hash table, so that means we're not radix */
1568 spapr
->patb_entry
= 0;
1569 spapr_set_all_lpcrs(0, LPCR_HR
| LPCR_UPRT
);
1572 void spapr_setup_hpt_and_vrma(SpaprMachineState
*spapr
)
1576 if ((spapr
->resize_hpt
== SPAPR_RESIZE_HPT_DISABLED
)
1577 || (spapr
->cas_reboot
1578 && !spapr_ovec_test(spapr
->ov5_cas
, OV5_HPT_RESIZE
))) {
1579 hpt_shift
= spapr_hpt_shift_for_ramsize(MACHINE(spapr
)->maxram_size
);
1581 uint64_t current_ram_size
;
1583 current_ram_size
= MACHINE(spapr
)->ram_size
+ get_plugged_memory_size();
1584 hpt_shift
= spapr_hpt_shift_for_ramsize(current_ram_size
);
1586 spapr_reallocate_hpt(spapr
, hpt_shift
, &error_fatal
);
1588 if (spapr
->vrma_adjust
) {
1589 spapr
->rma_size
= kvmppc_rma_size(spapr_node0_size(MACHINE(spapr
)),
1594 static int spapr_reset_drcs(Object
*child
, void *opaque
)
1597 (SpaprDrc
*) object_dynamic_cast(child
,
1598 TYPE_SPAPR_DR_CONNECTOR
);
1601 spapr_drc_reset(drc
);
1607 static void spapr_machine_reset(MachineState
*machine
)
1609 SpaprMachineState
*spapr
= SPAPR_MACHINE(machine
);
1610 PowerPCCPU
*first_ppc_cpu
;
1615 kvmppc_svm_off(&error_fatal
);
1616 spapr_caps_apply(spapr
);
1618 first_ppc_cpu
= POWERPC_CPU(first_cpu
);
1619 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
1620 ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
, 0,
1621 spapr
->max_compat_pvr
)) {
1623 * If using KVM with radix mode available, VCPUs can be started
1624 * without a HPT because KVM will start them in radix mode.
1625 * Set the GR bit in PATE so that we know there is no HPT.
1627 spapr
->patb_entry
= PATE1_GR
;
1628 spapr_set_all_lpcrs(LPCR_HR
| LPCR_UPRT
, LPCR_HR
| LPCR_UPRT
);
1630 spapr_setup_hpt_and_vrma(spapr
);
1633 qemu_devices_reset();
1636 * If this reset wasn't generated by CAS, we should reset our
1637 * negotiated options and start from scratch
1639 if (!spapr
->cas_reboot
) {
1640 spapr_ovec_cleanup(spapr
->ov5_cas
);
1641 spapr
->ov5_cas
= spapr_ovec_new();
1643 ppc_set_compat_all(spapr
->max_compat_pvr
, &error_fatal
);
1647 * This is fixing some of the default configuration of the XIVE
1648 * devices. To be called after the reset of the machine devices.
1650 spapr_irq_reset(spapr
, &error_fatal
);
1653 * There is no CAS under qtest. Simulate one to please the code that
1654 * depends on spapr->ov5_cas. This is especially needed to test device
1655 * unplug, so we do that before resetting the DRCs.
1657 if (qtest_enabled()) {
1658 spapr_ovec_cleanup(spapr
->ov5_cas
);
1659 spapr
->ov5_cas
= spapr_ovec_clone(spapr
->ov5
);
1662 /* DRC reset may cause a device to be unplugged. This will cause troubles
1663 * if this device is used by another device (eg, a running vhost backend
1664 * will crash QEMU if the DIMM holding the vring goes away). To avoid such
1665 * situations, we reset DRCs after all devices have been reset.
1667 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs
, NULL
);
1669 spapr_clear_pending_events(spapr
);
1672 * We place the device tree and RTAS just below either the top of the RMA,
1673 * or just below 2GB, whichever is lower, so that it can be
1674 * processed with 32-bit real mode code if necessary
1676 fdt_addr
= MIN(spapr
->rma_size
, RTAS_MAX_ADDR
) - FDT_MAX_SIZE
;
1678 fdt
= spapr_build_fdt(spapr
, true, FDT_MAX_SIZE
);
1682 /* Should only fail if we've built a corrupted tree */
1686 qemu_fdt_dumpdtb(fdt
, fdt_totalsize(fdt
));
1687 cpu_physical_memory_write(fdt_addr
, fdt
, fdt_totalsize(fdt
));
1688 g_free(spapr
->fdt_blob
);
1689 spapr
->fdt_size
= fdt_totalsize(fdt
);
1690 spapr
->fdt_initial_size
= spapr
->fdt_size
;
1691 spapr
->fdt_blob
= fdt
;
1693 /* Set up the entry state */
1694 spapr_cpu_set_entry_state(first_ppc_cpu
, SPAPR_ENTRY_POINT
, fdt_addr
);
1695 first_ppc_cpu
->env
.gpr
[5] = 0;
1697 spapr
->cas_reboot
= false;
1699 spapr
->mc_status
= -1;
1700 spapr
->guest_machine_check_addr
= -1;
1702 /* Signal all vCPUs waiting on this condition */
1703 qemu_cond_broadcast(&spapr
->mc_delivery_cond
);
1705 migrate_del_blocker(spapr
->fwnmi_migration_blocker
);
1708 static void spapr_create_nvram(SpaprMachineState
*spapr
)
1710 DeviceState
*dev
= qdev_create(&spapr
->vio_bus
->bus
, "spapr-nvram");
1711 DriveInfo
*dinfo
= drive_get(IF_PFLASH
, 0, 0);
1714 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
1718 qdev_init_nofail(dev
);
1720 spapr
->nvram
= (struct SpaprNvram
*)dev
;
1723 static void spapr_rtc_create(SpaprMachineState
*spapr
)
1725 object_initialize_child(OBJECT(spapr
), "rtc",
1726 &spapr
->rtc
, sizeof(spapr
->rtc
), TYPE_SPAPR_RTC
,
1727 &error_fatal
, NULL
);
1728 object_property_set_bool(OBJECT(&spapr
->rtc
), true, "realized",
1730 object_property_add_alias(OBJECT(spapr
), "rtc-time", OBJECT(&spapr
->rtc
),
1731 "date", &error_fatal
);
1734 /* Returns whether we want to use VGA or not */
1735 static bool spapr_vga_init(PCIBus
*pci_bus
, Error
**errp
)
1737 switch (vga_interface_type
) {
1745 return pci_vga_init(pci_bus
) != NULL
;
1748 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1753 static int spapr_pre_load(void *opaque
)
1757 rc
= spapr_caps_pre_load(opaque
);
1765 static int spapr_post_load(void *opaque
, int version_id
)
1767 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1770 err
= spapr_caps_post_migration(spapr
);
1776 * In earlier versions, there was no separate qdev for the PAPR
1777 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1778 * So when migrating from those versions, poke the incoming offset
1779 * value into the RTC device
1781 if (version_id
< 3) {
1782 err
= spapr_rtc_import_offset(&spapr
->rtc
, spapr
->rtc_offset
);
1788 if (kvm_enabled() && spapr
->patb_entry
) {
1789 PowerPCCPU
*cpu
= POWERPC_CPU(first_cpu
);
1790 bool radix
= !!(spapr
->patb_entry
& PATE1_GR
);
1791 bool gtse
= !!(cpu
->env
.spr
[SPR_LPCR
] & LPCR_GTSE
);
1794 * Update LPCR:HR and UPRT as they may not be set properly in
1797 spapr_set_all_lpcrs(radix
? (LPCR_HR
| LPCR_UPRT
) : 0,
1798 LPCR_HR
| LPCR_UPRT
);
1800 err
= kvmppc_configure_v3_mmu(cpu
, radix
, gtse
, spapr
->patb_entry
);
1802 error_report("Process table config unsupported by the host");
1807 err
= spapr_irq_post_load(spapr
, version_id
);
1815 static int spapr_pre_save(void *opaque
)
1819 rc
= spapr_caps_pre_save(opaque
);
1827 static bool version_before_3(void *opaque
, int version_id
)
1829 return version_id
< 3;
1832 static bool spapr_pending_events_needed(void *opaque
)
1834 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1835 return !QTAILQ_EMPTY(&spapr
->pending_events
);
1838 static const VMStateDescription vmstate_spapr_event_entry
= {
1839 .name
= "spapr_event_log_entry",
1841 .minimum_version_id
= 1,
1842 .fields
= (VMStateField
[]) {
1843 VMSTATE_UINT32(summary
, SpaprEventLogEntry
),
1844 VMSTATE_UINT32(extended_length
, SpaprEventLogEntry
),
1845 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log
, SpaprEventLogEntry
, 0,
1846 NULL
, extended_length
),
1847 VMSTATE_END_OF_LIST()
1851 static const VMStateDescription vmstate_spapr_pending_events
= {
1852 .name
= "spapr_pending_events",
1854 .minimum_version_id
= 1,
1855 .needed
= spapr_pending_events_needed
,
1856 .fields
= (VMStateField
[]) {
1857 VMSTATE_QTAILQ_V(pending_events
, SpaprMachineState
, 1,
1858 vmstate_spapr_event_entry
, SpaprEventLogEntry
, next
),
1859 VMSTATE_END_OF_LIST()
1863 static bool spapr_ov5_cas_needed(void *opaque
)
1865 SpaprMachineState
*spapr
= opaque
;
1866 SpaprOptionVector
*ov5_mask
= spapr_ovec_new();
1869 /* Prior to the introduction of SpaprOptionVector, we had two option
1870 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1871 * Both of these options encode machine topology into the device-tree
1872 * in such a way that the now-booted OS should still be able to interact
1873 * appropriately with QEMU regardless of what options were actually
1874 * negotiatied on the source side.
1876 * As such, we can avoid migrating the CAS-negotiated options if these
1877 * are the only options available on the current machine/platform.
1878 * Since these are the only options available for pseries-2.7 and
1879 * earlier, this allows us to maintain old->new/new->old migration
1882 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1883 * via default pseries-2.8 machines and explicit command-line parameters.
1884 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1885 * of the actual CAS-negotiated values to continue working properly. For
1886 * example, availability of memory unplug depends on knowing whether
1887 * OV5_HP_EVT was negotiated via CAS.
1889 * Thus, for any cases where the set of available CAS-negotiatable
1890 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
1891 * include the CAS-negotiated options in the migration stream, unless
1892 * if they affect boot time behaviour only.
1894 spapr_ovec_set(ov5_mask
, OV5_FORM1_AFFINITY
);
1895 spapr_ovec_set(ov5_mask
, OV5_DRCONF_MEMORY
);
1896 spapr_ovec_set(ov5_mask
, OV5_DRMEM_V2
);
1898 /* We need extra information if we have any bits outside the mask
1900 cas_needed
= !spapr_ovec_subset(spapr
->ov5
, ov5_mask
);
1902 spapr_ovec_cleanup(ov5_mask
);
1907 static const VMStateDescription vmstate_spapr_ov5_cas
= {
1908 .name
= "spapr_option_vector_ov5_cas",
1910 .minimum_version_id
= 1,
1911 .needed
= spapr_ov5_cas_needed
,
1912 .fields
= (VMStateField
[]) {
1913 VMSTATE_STRUCT_POINTER_V(ov5_cas
, SpaprMachineState
, 1,
1914 vmstate_spapr_ovec
, SpaprOptionVector
),
1915 VMSTATE_END_OF_LIST()
1919 static bool spapr_patb_entry_needed(void *opaque
)
1921 SpaprMachineState
*spapr
= opaque
;
1923 return !!spapr
->patb_entry
;
1926 static const VMStateDescription vmstate_spapr_patb_entry
= {
1927 .name
= "spapr_patb_entry",
1929 .minimum_version_id
= 1,
1930 .needed
= spapr_patb_entry_needed
,
1931 .fields
= (VMStateField
[]) {
1932 VMSTATE_UINT64(patb_entry
, SpaprMachineState
),
1933 VMSTATE_END_OF_LIST()
1937 static bool spapr_irq_map_needed(void *opaque
)
1939 SpaprMachineState
*spapr
= opaque
;
1941 return spapr
->irq_map
&& !bitmap_empty(spapr
->irq_map
, spapr
->irq_map_nr
);
1944 static const VMStateDescription vmstate_spapr_irq_map
= {
1945 .name
= "spapr_irq_map",
1947 .minimum_version_id
= 1,
1948 .needed
= spapr_irq_map_needed
,
1949 .fields
= (VMStateField
[]) {
1950 VMSTATE_BITMAP(irq_map
, SpaprMachineState
, 0, irq_map_nr
),
1951 VMSTATE_END_OF_LIST()
1955 static bool spapr_dtb_needed(void *opaque
)
1957 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(opaque
);
1959 return smc
->update_dt_enabled
;
1962 static int spapr_dtb_pre_load(void *opaque
)
1964 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1966 g_free(spapr
->fdt_blob
);
1967 spapr
->fdt_blob
= NULL
;
1968 spapr
->fdt_size
= 0;
1973 static const VMStateDescription vmstate_spapr_dtb
= {
1974 .name
= "spapr_dtb",
1976 .minimum_version_id
= 1,
1977 .needed
= spapr_dtb_needed
,
1978 .pre_load
= spapr_dtb_pre_load
,
1979 .fields
= (VMStateField
[]) {
1980 VMSTATE_UINT32(fdt_initial_size
, SpaprMachineState
),
1981 VMSTATE_UINT32(fdt_size
, SpaprMachineState
),
1982 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob
, SpaprMachineState
, 0, NULL
,
1984 VMSTATE_END_OF_LIST()
1988 static bool spapr_fwnmi_needed(void *opaque
)
1990 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1992 return spapr
->guest_machine_check_addr
!= -1;
1995 static int spapr_fwnmi_pre_save(void *opaque
)
1997 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
2000 * Check if machine check handling is in progress and print a
2003 if (spapr
->mc_status
!= -1) {
2004 warn_report("A machine check is being handled during migration. The"
2005 "handler may run and log hardware error on the destination");
2011 static const VMStateDescription vmstate_spapr_machine_check
= {
2012 .name
= "spapr_machine_check",
2014 .minimum_version_id
= 1,
2015 .needed
= spapr_fwnmi_needed
,
2016 .pre_save
= spapr_fwnmi_pre_save
,
2017 .fields
= (VMStateField
[]) {
2018 VMSTATE_UINT64(guest_machine_check_addr
, SpaprMachineState
),
2019 VMSTATE_INT32(mc_status
, SpaprMachineState
),
2020 VMSTATE_END_OF_LIST()
2024 static const VMStateDescription vmstate_spapr
= {
2027 .minimum_version_id
= 1,
2028 .pre_load
= spapr_pre_load
,
2029 .post_load
= spapr_post_load
,
2030 .pre_save
= spapr_pre_save
,
2031 .fields
= (VMStateField
[]) {
2032 /* used to be @next_irq */
2033 VMSTATE_UNUSED_BUFFER(version_before_3
, 0, 4),
2036 VMSTATE_UINT64_TEST(rtc_offset
, SpaprMachineState
, version_before_3
),
2038 VMSTATE_PPC_TIMEBASE_V(tb
, SpaprMachineState
, 2),
2039 VMSTATE_END_OF_LIST()
2041 .subsections
= (const VMStateDescription
*[]) {
2042 &vmstate_spapr_ov5_cas
,
2043 &vmstate_spapr_patb_entry
,
2044 &vmstate_spapr_pending_events
,
2045 &vmstate_spapr_cap_htm
,
2046 &vmstate_spapr_cap_vsx
,
2047 &vmstate_spapr_cap_dfp
,
2048 &vmstate_spapr_cap_cfpc
,
2049 &vmstate_spapr_cap_sbbc
,
2050 &vmstate_spapr_cap_ibs
,
2051 &vmstate_spapr_cap_hpt_maxpagesize
,
2052 &vmstate_spapr_irq_map
,
2053 &vmstate_spapr_cap_nested_kvm_hv
,
2055 &vmstate_spapr_cap_large_decr
,
2056 &vmstate_spapr_cap_ccf_assist
,
2057 &vmstate_spapr_cap_fwnmi
,
2058 &vmstate_spapr_machine_check
,
2063 static int htab_save_setup(QEMUFile
*f
, void *opaque
)
2065 SpaprMachineState
*spapr
= opaque
;
2067 /* "Iteration" header */
2068 if (!spapr
->htab_shift
) {
2069 qemu_put_be32(f
, -1);
2071 qemu_put_be32(f
, spapr
->htab_shift
);
2075 spapr
->htab_save_index
= 0;
2076 spapr
->htab_first_pass
= true;
2078 if (spapr
->htab_shift
) {
2079 assert(kvm_enabled());
2087 static void htab_save_chunk(QEMUFile
*f
, SpaprMachineState
*spapr
,
2088 int chunkstart
, int n_valid
, int n_invalid
)
2090 qemu_put_be32(f
, chunkstart
);
2091 qemu_put_be16(f
, n_valid
);
2092 qemu_put_be16(f
, n_invalid
);
2093 qemu_put_buffer(f
, HPTE(spapr
->htab
, chunkstart
),
2094 HASH_PTE_SIZE_64
* n_valid
);
2097 static void htab_save_end_marker(QEMUFile
*f
)
2099 qemu_put_be32(f
, 0);
2100 qemu_put_be16(f
, 0);
2101 qemu_put_be16(f
, 0);
2104 static void htab_save_first_pass(QEMUFile
*f
, SpaprMachineState
*spapr
,
2107 bool has_timeout
= max_ns
!= -1;
2108 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
2109 int index
= spapr
->htab_save_index
;
2110 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
2112 assert(spapr
->htab_first_pass
);
2117 /* Consume invalid HPTEs */
2118 while ((index
< htabslots
)
2119 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2120 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2124 /* Consume valid HPTEs */
2126 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
2127 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2128 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2132 if (index
> chunkstart
) {
2133 int n_valid
= index
- chunkstart
;
2135 htab_save_chunk(f
, spapr
, chunkstart
, n_valid
, 0);
2138 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
2142 } while ((index
< htabslots
) && !qemu_file_rate_limit(f
));
2144 if (index
>= htabslots
) {
2145 assert(index
== htabslots
);
2147 spapr
->htab_first_pass
= false;
2149 spapr
->htab_save_index
= index
;
2152 static int htab_save_later_pass(QEMUFile
*f
, SpaprMachineState
*spapr
,
2155 bool final
= max_ns
< 0;
2156 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
2157 int examined
= 0, sent
= 0;
2158 int index
= spapr
->htab_save_index
;
2159 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
2161 assert(!spapr
->htab_first_pass
);
2164 int chunkstart
, invalidstart
;
2166 /* Consume non-dirty HPTEs */
2167 while ((index
< htabslots
)
2168 && !HPTE_DIRTY(HPTE(spapr
->htab
, index
))) {
2174 /* Consume valid dirty HPTEs */
2175 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
2176 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
2177 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2178 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2183 invalidstart
= index
;
2184 /* Consume invalid dirty HPTEs */
2185 while ((index
< htabslots
) && (index
- invalidstart
< USHRT_MAX
)
2186 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
2187 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2188 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2193 if (index
> chunkstart
) {
2194 int n_valid
= invalidstart
- chunkstart
;
2195 int n_invalid
= index
- invalidstart
;
2197 htab_save_chunk(f
, spapr
, chunkstart
, n_valid
, n_invalid
);
2198 sent
+= index
- chunkstart
;
2200 if (!final
&& (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
2205 if (examined
>= htabslots
) {
2209 if (index
>= htabslots
) {
2210 assert(index
== htabslots
);
2213 } while ((examined
< htabslots
) && (!qemu_file_rate_limit(f
) || final
));
2215 if (index
>= htabslots
) {
2216 assert(index
== htabslots
);
2220 spapr
->htab_save_index
= index
;
2222 return (examined
>= htabslots
) && (sent
== 0) ? 1 : 0;
2225 #define MAX_ITERATION_NS 5000000 /* 5 ms */
2226 #define MAX_KVM_BUF_SIZE 2048
2228 static int htab_save_iterate(QEMUFile
*f
, void *opaque
)
2230 SpaprMachineState
*spapr
= opaque
;
2234 /* Iteration header */
2235 if (!spapr
->htab_shift
) {
2236 qemu_put_be32(f
, -1);
2239 qemu_put_be32(f
, 0);
2243 assert(kvm_enabled());
2245 fd
= get_htab_fd(spapr
);
2250 rc
= kvmppc_save_htab(f
, fd
, MAX_KVM_BUF_SIZE
, MAX_ITERATION_NS
);
2254 } else if (spapr
->htab_first_pass
) {
2255 htab_save_first_pass(f
, spapr
, MAX_ITERATION_NS
);
2257 rc
= htab_save_later_pass(f
, spapr
, MAX_ITERATION_NS
);
2260 htab_save_end_marker(f
);
2265 static int htab_save_complete(QEMUFile
*f
, void *opaque
)
2267 SpaprMachineState
*spapr
= opaque
;
2270 /* Iteration header */
2271 if (!spapr
->htab_shift
) {
2272 qemu_put_be32(f
, -1);
2275 qemu_put_be32(f
, 0);
2281 assert(kvm_enabled());
2283 fd
= get_htab_fd(spapr
);
2288 rc
= kvmppc_save_htab(f
, fd
, MAX_KVM_BUF_SIZE
, -1);
2293 if (spapr
->htab_first_pass
) {
2294 htab_save_first_pass(f
, spapr
, -1);
2296 htab_save_later_pass(f
, spapr
, -1);
2300 htab_save_end_marker(f
);
2305 static int htab_load(QEMUFile
*f
, void *opaque
, int version_id
)
2307 SpaprMachineState
*spapr
= opaque
;
2308 uint32_t section_hdr
;
2310 Error
*local_err
= NULL
;
2312 if (version_id
< 1 || version_id
> 1) {
2313 error_report("htab_load() bad version");
2317 section_hdr
= qemu_get_be32(f
);
2319 if (section_hdr
== -1) {
2320 spapr_free_hpt(spapr
);
2325 /* First section gives the htab size */
2326 spapr_reallocate_hpt(spapr
, section_hdr
, &local_err
);
2328 error_report_err(local_err
);
2335 assert(kvm_enabled());
2337 fd
= kvmppc_get_htab_fd(true, 0, &local_err
);
2339 error_report_err(local_err
);
2346 uint16_t n_valid
, n_invalid
;
2348 index
= qemu_get_be32(f
);
2349 n_valid
= qemu_get_be16(f
);
2350 n_invalid
= qemu_get_be16(f
);
2352 if ((index
== 0) && (n_valid
== 0) && (n_invalid
== 0)) {
2357 if ((index
+ n_valid
+ n_invalid
) >
2358 (HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
)) {
2359 /* Bad index in stream */
2361 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2362 index
, n_valid
, n_invalid
, spapr
->htab_shift
);
2368 qemu_get_buffer(f
, HPTE(spapr
->htab
, index
),
2369 HASH_PTE_SIZE_64
* n_valid
);
2372 memset(HPTE(spapr
->htab
, index
+ n_valid
), 0,
2373 HASH_PTE_SIZE_64
* n_invalid
);
2380 rc
= kvmppc_load_htab_chunk(f
, fd
, index
, n_valid
, n_invalid
);
2395 static void htab_save_cleanup(void *opaque
)
2397 SpaprMachineState
*spapr
= opaque
;
2399 close_htab_fd(spapr
);
2402 static SaveVMHandlers savevm_htab_handlers
= {
2403 .save_setup
= htab_save_setup
,
2404 .save_live_iterate
= htab_save_iterate
,
2405 .save_live_complete_precopy
= htab_save_complete
,
2406 .save_cleanup
= htab_save_cleanup
,
2407 .load_state
= htab_load
,
2410 static void spapr_boot_set(void *opaque
, const char *boot_device
,
2413 MachineState
*machine
= MACHINE(opaque
);
2414 machine
->boot_order
= g_strdup(boot_device
);
2417 static void spapr_create_lmb_dr_connectors(SpaprMachineState
*spapr
)
2419 MachineState
*machine
= MACHINE(spapr
);
2420 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
2421 uint32_t nr_lmbs
= (machine
->maxram_size
- machine
->ram_size
)/lmb_size
;
2424 for (i
= 0; i
< nr_lmbs
; i
++) {
2427 addr
= i
* lmb_size
+ machine
->device_memory
->base
;
2428 spapr_dr_connector_new(OBJECT(spapr
), TYPE_SPAPR_DRC_LMB
,
2434 * If RAM size, maxmem size and individual node mem sizes aren't aligned
2435 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
2436 * since we can't support such unaligned sizes with DRCONF_MEMORY.
2438 static void spapr_validate_node_memory(MachineState
*machine
, Error
**errp
)
2442 if (machine
->ram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
2443 error_setg(errp
, "Memory size 0x" RAM_ADDR_FMT
2444 " is not aligned to %" PRIu64
" MiB",
2446 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2450 if (machine
->maxram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
2451 error_setg(errp
, "Maximum memory size 0x" RAM_ADDR_FMT
2452 " is not aligned to %" PRIu64
" MiB",
2454 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2458 for (i
= 0; i
< machine
->numa_state
->num_nodes
; i
++) {
2459 if (machine
->numa_state
->nodes
[i
].node_mem
% SPAPR_MEMORY_BLOCK_SIZE
) {
2461 "Node %d memory size 0x%" PRIx64
2462 " is not aligned to %" PRIu64
" MiB",
2463 i
, machine
->numa_state
->nodes
[i
].node_mem
,
2464 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2470 /* find cpu slot in machine->possible_cpus by core_id */
2471 static CPUArchId
*spapr_find_cpu_slot(MachineState
*ms
, uint32_t id
, int *idx
)
2473 int index
= id
/ ms
->smp
.threads
;
2475 if (index
>= ms
->possible_cpus
->len
) {
2481 return &ms
->possible_cpus
->cpus
[index
];
2484 static void spapr_set_vsmt_mode(SpaprMachineState
*spapr
, Error
**errp
)
2486 MachineState
*ms
= MACHINE(spapr
);
2487 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
2488 Error
*local_err
= NULL
;
2489 bool vsmt_user
= !!spapr
->vsmt
;
2490 int kvm_smt
= kvmppc_smt_threads();
2492 unsigned int smp_threads
= ms
->smp
.threads
;
2494 if (!kvm_enabled() && (smp_threads
> 1)) {
2495 error_setg(&local_err
, "TCG cannot support more than 1 thread/core "
2496 "on a pseries machine");
2499 if (!is_power_of_2(smp_threads
)) {
2500 error_setg(&local_err
, "Cannot support %d threads/core on a pseries "
2501 "machine because it must be a power of 2", smp_threads
);
2505 /* Detemine the VSMT mode to use: */
2507 if (spapr
->vsmt
< smp_threads
) {
2508 error_setg(&local_err
, "Cannot support VSMT mode %d"
2509 " because it must be >= threads/core (%d)",
2510 spapr
->vsmt
, smp_threads
);
2513 /* In this case, spapr->vsmt has been set by the command line */
2514 } else if (!smc
->smp_threads_vsmt
) {
2516 * Default VSMT value is tricky, because we need it to be as
2517 * consistent as possible (for migration), but this requires
2518 * changing it for at least some existing cases. We pick 8 as
2519 * the value that we'd get with KVM on POWER8, the
2520 * overwhelmingly common case in production systems.
2522 spapr
->vsmt
= MAX(8, smp_threads
);
2524 spapr
->vsmt
= smp_threads
;
2527 /* KVM: If necessary, set the SMT mode: */
2528 if (kvm_enabled() && (spapr
->vsmt
!= kvm_smt
)) {
2529 ret
= kvmppc_set_smt_threads(spapr
->vsmt
);
2531 /* Looks like KVM isn't able to change VSMT mode */
2532 error_setg(&local_err
,
2533 "Failed to set KVM's VSMT mode to %d (errno %d)",
2535 /* We can live with that if the default one is big enough
2536 * for the number of threads, and a submultiple of the one
2537 * we want. In this case we'll waste some vcpu ids, but
2538 * behaviour will be correct */
2539 if ((kvm_smt
>= smp_threads
) && ((spapr
->vsmt
% kvm_smt
) == 0)) {
2540 warn_report_err(local_err
);
2545 error_append_hint(&local_err
,
2546 "On PPC, a VM with %d threads/core"
2547 " on a host with %d threads/core"
2548 " requires the use of VSMT mode %d.\n",
2549 smp_threads
, kvm_smt
, spapr
->vsmt
);
2551 kvmppc_error_append_smt_possible_hint(&local_err
);
2556 /* else TCG: nothing to do currently */
2558 error_propagate(errp
, local_err
);
2561 static void spapr_init_cpus(SpaprMachineState
*spapr
)
2563 MachineState
*machine
= MACHINE(spapr
);
2564 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2565 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
2566 const char *type
= spapr_get_cpu_core_type(machine
->cpu_type
);
2567 const CPUArchIdList
*possible_cpus
;
2568 unsigned int smp_cpus
= machine
->smp
.cpus
;
2569 unsigned int smp_threads
= machine
->smp
.threads
;
2570 unsigned int max_cpus
= machine
->smp
.max_cpus
;
2571 int boot_cores_nr
= smp_cpus
/ smp_threads
;
2574 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
2575 if (mc
->has_hotpluggable_cpus
) {
2576 if (smp_cpus
% smp_threads
) {
2577 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2578 smp_cpus
, smp_threads
);
2581 if (max_cpus
% smp_threads
) {
2582 error_report("max_cpus (%u) must be multiple of threads (%u)",
2583 max_cpus
, smp_threads
);
2587 if (max_cpus
!= smp_cpus
) {
2588 error_report("This machine version does not support CPU hotplug");
2591 boot_cores_nr
= possible_cpus
->len
;
2594 if (smc
->pre_2_10_has_unused_icps
) {
2597 for (i
= 0; i
< spapr_max_server_number(spapr
); i
++) {
2598 /* Dummy entries get deregistered when real ICPState objects
2599 * are registered during CPU core hotplug.
2601 pre_2_10_vmstate_register_dummy_icp(i
);
2605 for (i
= 0; i
< possible_cpus
->len
; i
++) {
2606 int core_id
= i
* smp_threads
;
2608 if (mc
->has_hotpluggable_cpus
) {
2609 spapr_dr_connector_new(OBJECT(spapr
), TYPE_SPAPR_DRC_CPU
,
2610 spapr_vcpu_id(spapr
, core_id
));
2613 if (i
< boot_cores_nr
) {
2614 Object
*core
= object_new(type
);
2615 int nr_threads
= smp_threads
;
2617 /* Handle the partially filled core for older machine types */
2618 if ((i
+ 1) * smp_threads
>= smp_cpus
) {
2619 nr_threads
= smp_cpus
- i
* smp_threads
;
2622 object_property_set_int(core
, nr_threads
, "nr-threads",
2624 object_property_set_int(core
, core_id
, CPU_CORE_PROP_CORE_ID
,
2626 object_property_set_bool(core
, true, "realized", &error_fatal
);
2633 static PCIHostState
*spapr_create_default_phb(void)
2637 dev
= qdev_create(NULL
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
2638 qdev_prop_set_uint32(dev
, "index", 0);
2639 qdev_init_nofail(dev
);
2641 return PCI_HOST_BRIDGE(dev
);
2644 /* pSeries LPAR / sPAPR hardware init */
2645 static void spapr_machine_init(MachineState
*machine
)
2647 SpaprMachineState
*spapr
= SPAPR_MACHINE(machine
);
2648 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
2649 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2650 const char *kernel_filename
= machine
->kernel_filename
;
2651 const char *initrd_filename
= machine
->initrd_filename
;
2654 MemoryRegion
*sysmem
= get_system_memory();
2655 hwaddr node0_size
= spapr_node0_size(machine
);
2656 long load_limit
, fw_size
;
2658 Error
*resize_hpt_err
= NULL
;
2660 msi_nonbroken
= true;
2662 QLIST_INIT(&spapr
->phbs
);
2663 QTAILQ_INIT(&spapr
->pending_dimm_unplugs
);
2665 /* Determine capabilities to run with */
2666 spapr_caps_init(spapr
);
2668 kvmppc_check_papr_resize_hpt(&resize_hpt_err
);
2669 if (spapr
->resize_hpt
== SPAPR_RESIZE_HPT_DEFAULT
) {
2671 * If the user explicitly requested a mode we should either
2672 * supply it, or fail completely (which we do below). But if
2673 * it's not set explicitly, we reset our mode to something
2676 if (resize_hpt_err
) {
2677 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DISABLED
;
2678 error_free(resize_hpt_err
);
2679 resize_hpt_err
= NULL
;
2681 spapr
->resize_hpt
= smc
->resize_hpt_default
;
2685 assert(spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DEFAULT
);
2687 if ((spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) && resize_hpt_err
) {
2689 * User requested HPT resize, but this host can't supply it. Bail out
2691 error_report_err(resize_hpt_err
);
2695 spapr
->rma_size
= node0_size
;
2697 /* With KVM, we don't actually know whether KVM supports an
2698 * unbounded RMA (PR KVM) or is limited by the hash table size
2699 * (HV KVM using VRMA), so we always assume the latter
2701 * In that case, we also limit the initial allocations for RTAS
2702 * etc... to 256M since we have no way to know what the VRMA size
2703 * is going to be as it depends on the size of the hash table
2704 * which isn't determined yet.
2706 if (kvm_enabled()) {
2707 spapr
->vrma_adjust
= 1;
2708 spapr
->rma_size
= MIN(spapr
->rma_size
, 0x10000000);
2711 /* Actually we don't support unbounded RMA anymore since we added
2712 * proper emulation of HV mode. The max we can get is 16G which
2713 * also happens to be what we configure for PAPR mode so make sure
2714 * we don't do anything bigger than that
2716 spapr
->rma_size
= MIN(spapr
->rma_size
, 0x400000000ull
);
2718 if (spapr
->rma_size
> node0_size
) {
2719 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx
")",
2724 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2725 load_limit
= MIN(spapr
->rma_size
, RTAS_MAX_ADDR
) - FW_OVERHEAD
;
2728 * VSMT must be set in order to be able to compute VCPU ids, ie to
2729 * call spapr_max_server_number() or spapr_vcpu_id().
2731 spapr_set_vsmt_mode(spapr
, &error_fatal
);
2733 /* Set up Interrupt Controller before we create the VCPUs */
2734 spapr_irq_init(spapr
, &error_fatal
);
2736 /* Set up containers for ibm,client-architecture-support negotiated options
2738 spapr
->ov5
= spapr_ovec_new();
2739 spapr
->ov5_cas
= spapr_ovec_new();
2741 if (smc
->dr_lmb_enabled
) {
2742 spapr_ovec_set(spapr
->ov5
, OV5_DRCONF_MEMORY
);
2743 spapr_validate_node_memory(machine
, &error_fatal
);
2746 spapr_ovec_set(spapr
->ov5
, OV5_FORM1_AFFINITY
);
2748 /* advertise support for dedicated HP event source to guests */
2749 if (spapr
->use_hotplug_event_source
) {
2750 spapr_ovec_set(spapr
->ov5
, OV5_HP_EVT
);
2753 /* advertise support for HPT resizing */
2754 if (spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) {
2755 spapr_ovec_set(spapr
->ov5
, OV5_HPT_RESIZE
);
2758 /* advertise support for ibm,dyamic-memory-v2 */
2759 spapr_ovec_set(spapr
->ov5
, OV5_DRMEM_V2
);
2761 /* advertise XIVE on POWER9 machines */
2762 if (spapr
->irq
->xive
) {
2763 spapr_ovec_set(spapr
->ov5
, OV5_XIVE_EXPLOIT
);
2767 spapr_init_cpus(spapr
);
2770 * check we don't have a memory-less/cpu-less NUMA node
2771 * Firmware relies on the existing memory/cpu topology to provide the
2772 * NUMA topology to the kernel.
2773 * And the linux kernel needs to know the NUMA topology at start
2774 * to be able to hotplug CPUs later.
2776 if (machine
->numa_state
->num_nodes
) {
2777 for (i
= 0; i
< machine
->numa_state
->num_nodes
; ++i
) {
2778 /* check for memory-less node */
2779 if (machine
->numa_state
->nodes
[i
].node_mem
== 0) {
2782 /* check for cpu-less node */
2784 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
2785 if (cpu
->node_id
== i
) {
2790 /* memory-less and cpu-less node */
2793 "Memory-less/cpu-less nodes are not supported (node %d)",
2803 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node.
2804 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is
2805 * called from vPHB reset handler so we initialize the counter here.
2806 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM
2807 * must be equally distant from any other node.
2808 * The final value of spapr->gpu_numa_id is going to be written to
2809 * max-associativity-domains in spapr_build_fdt().
2811 spapr
->gpu_numa_id
= MAX(1, machine
->numa_state
->num_nodes
);
2813 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&
2814 ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
, 0,
2815 spapr
->max_compat_pvr
)) {
2816 /* KVM and TCG always allow GTSE with radix... */
2817 spapr_ovec_set(spapr
->ov5
, OV5_MMU_RADIX_GTSE
);
2819 /* ... but not with hash (currently). */
2821 if (kvm_enabled()) {
2822 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2823 kvmppc_enable_logical_ci_hcalls();
2824 kvmppc_enable_set_mode_hcall();
2826 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2827 kvmppc_enable_clear_ref_mod_hcalls();
2829 /* Enable H_PAGE_INIT */
2830 kvmppc_enable_h_page_init();
2834 memory_region_add_subregion(sysmem
, 0, machine
->ram
);
2836 /* always allocate the device memory information */
2837 machine
->device_memory
= g_malloc0(sizeof(*machine
->device_memory
));
2839 /* initialize hotplug memory address space */
2840 if (machine
->ram_size
< machine
->maxram_size
) {
2841 ram_addr_t device_mem_size
= machine
->maxram_size
- machine
->ram_size
;
2843 * Limit the number of hotpluggable memory slots to half the number
2844 * slots that KVM supports, leaving the other half for PCI and other
2845 * devices. However ensure that number of slots doesn't drop below 32.
2847 int max_memslots
= kvm_enabled() ? kvm_get_max_memslots() / 2 :
2848 SPAPR_MAX_RAM_SLOTS
;
2850 if (max_memslots
< SPAPR_MAX_RAM_SLOTS
) {
2851 max_memslots
= SPAPR_MAX_RAM_SLOTS
;
2853 if (machine
->ram_slots
> max_memslots
) {
2854 error_report("Specified number of memory slots %"
2855 PRIu64
" exceeds max supported %d",
2856 machine
->ram_slots
, max_memslots
);
2860 machine
->device_memory
->base
= ROUND_UP(machine
->ram_size
,
2861 SPAPR_DEVICE_MEM_ALIGN
);
2862 memory_region_init(&machine
->device_memory
->mr
, OBJECT(spapr
),
2863 "device-memory", device_mem_size
);
2864 memory_region_add_subregion(sysmem
, machine
->device_memory
->base
,
2865 &machine
->device_memory
->mr
);
2868 if (smc
->dr_lmb_enabled
) {
2869 spapr_create_lmb_dr_connectors(spapr
);
2872 if (spapr_get_cap(spapr
, SPAPR_CAP_FWNMI_MCE
) == SPAPR_CAP_ON
) {
2873 /* Create the error string for live migration blocker */
2874 error_setg(&spapr
->fwnmi_migration_blocker
,
2875 "A machine check is being handled during migration. The handler"
2876 "may run and log hardware error on the destination");
2879 if (mc
->nvdimm_supported
) {
2880 spapr_create_nvdimm_dr_connectors(spapr
);
2883 /* Set up RTAS event infrastructure */
2884 spapr_events_init(spapr
);
2886 /* Set up the RTC RTAS interfaces */
2887 spapr_rtc_create(spapr
);
2889 /* Set up VIO bus */
2890 spapr
->vio_bus
= spapr_vio_bus_init();
2892 for (i
= 0; i
< serial_max_hds(); i
++) {
2894 spapr_vty_create(spapr
->vio_bus
, serial_hd(i
));
2898 /* We always have at least the nvram device on VIO */
2899 spapr_create_nvram(spapr
);
2902 * Setup hotplug / dynamic-reconfiguration connectors. top-level
2903 * connectors (described in root DT node's "ibm,drc-types" property)
2904 * are pre-initialized here. additional child connectors (such as
2905 * connectors for a PHBs PCI slots) are added as needed during their
2906 * parent's realization.
2908 if (smc
->dr_phb_enabled
) {
2909 for (i
= 0; i
< SPAPR_MAX_PHBS
; i
++) {
2910 spapr_dr_connector_new(OBJECT(machine
), TYPE_SPAPR_DRC_PHB
, i
);
2915 spapr_pci_rtas_init();
2917 phb
= spapr_create_default_phb();
2919 for (i
= 0; i
< nb_nics
; i
++) {
2920 NICInfo
*nd
= &nd_table
[i
];
2923 nd
->model
= g_strdup("spapr-vlan");
2926 if (g_str_equal(nd
->model
, "spapr-vlan") ||
2927 g_str_equal(nd
->model
, "ibmveth")) {
2928 spapr_vlan_create(spapr
->vio_bus
, nd
);
2930 pci_nic_init_nofail(&nd_table
[i
], phb
->bus
, nd
->model
, NULL
);
2934 for (i
= 0; i
<= drive_get_max_bus(IF_SCSI
); i
++) {
2935 spapr_vscsi_create(spapr
->vio_bus
);
2939 if (spapr_vga_init(phb
->bus
, &error_fatal
)) {
2940 spapr
->has_graphics
= true;
2941 machine
->usb
|= defaults_enabled() && !machine
->usb_disabled
;
2945 if (smc
->use_ohci_by_default
) {
2946 pci_create_simple(phb
->bus
, -1, "pci-ohci");
2948 pci_create_simple(phb
->bus
, -1, "nec-usb-xhci");
2951 if (spapr
->has_graphics
) {
2952 USBBus
*usb_bus
= usb_bus_find(-1);
2954 usb_create_simple(usb_bus
, "usb-kbd");
2955 usb_create_simple(usb_bus
, "usb-mouse");
2959 if (spapr
->rma_size
< (MIN_RMA_SLOF
* MiB
)) {
2961 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
2966 if (kernel_filename
) {
2967 uint64_t lowaddr
= 0;
2969 spapr
->kernel_size
= load_elf(kernel_filename
, NULL
,
2970 translate_kernel_address
, spapr
,
2971 NULL
, &lowaddr
, NULL
, NULL
, 1,
2972 PPC_ELF_MACHINE
, 0, 0);
2973 if (spapr
->kernel_size
== ELF_LOAD_WRONG_ENDIAN
) {
2974 spapr
->kernel_size
= load_elf(kernel_filename
, NULL
,
2975 translate_kernel_address
, spapr
, NULL
,
2976 &lowaddr
, NULL
, NULL
, 0,
2979 spapr
->kernel_le
= spapr
->kernel_size
> 0;
2981 if (spapr
->kernel_size
< 0) {
2982 error_report("error loading %s: %s", kernel_filename
,
2983 load_elf_strerror(spapr
->kernel_size
));
2988 if (initrd_filename
) {
2989 /* Try to locate the initrd in the gap between the kernel
2990 * and the firmware. Add a bit of space just in case
2992 spapr
->initrd_base
= (spapr
->kernel_addr
+ spapr
->kernel_size
2993 + 0x1ffff) & ~0xffff;
2994 spapr
->initrd_size
= load_image_targphys(initrd_filename
,
2997 - spapr
->initrd_base
);
2998 if (spapr
->initrd_size
< 0) {
2999 error_report("could not load initial ram disk '%s'",
3006 if (bios_name
== NULL
) {
3007 bios_name
= FW_FILE_NAME
;
3009 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
3011 error_report("Could not find LPAR firmware '%s'", bios_name
);
3014 fw_size
= load_image_targphys(filename
, 0, FW_MAX_SIZE
);
3016 error_report("Could not load LPAR firmware '%s'", filename
);
3021 /* FIXME: Should register things through the MachineState's qdev
3022 * interface, this is a legacy from the sPAPREnvironment structure
3023 * which predated MachineState but had a similar function */
3024 vmstate_register(NULL
, 0, &vmstate_spapr
, spapr
);
3025 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY
, 1,
3026 &savevm_htab_handlers
, spapr
);
3028 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine
),
3031 qemu_register_boot_set(spapr_boot_set
, spapr
);
3034 * Nothing needs to be done to resume a suspended guest because
3035 * suspending does not change the machine state, so no need for
3036 * a ->wakeup method.
3038 qemu_register_wakeup_support();
3040 if (kvm_enabled()) {
3041 /* to stop and start vmclock */
3042 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change
,
3045 kvmppc_spapr_enable_inkernel_multitce();
3048 qemu_cond_init(&spapr
->mc_delivery_cond
);
3051 static int spapr_kvm_type(MachineState
*machine
, const char *vm_type
)
3057 if (!strcmp(vm_type
, "HV")) {
3061 if (!strcmp(vm_type
, "PR")) {
3065 error_report("Unknown kvm-type specified '%s'", vm_type
);
3070 * Implementation of an interface to adjust firmware path
3071 * for the bootindex property handling.
3073 static char *spapr_get_fw_dev_path(FWPathProvider
*p
, BusState
*bus
,
3076 #define CAST(type, obj, name) \
3077 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
3078 SCSIDevice
*d
= CAST(SCSIDevice
, dev
, TYPE_SCSI_DEVICE
);
3079 SpaprPhbState
*phb
= CAST(SpaprPhbState
, dev
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
3080 VHostSCSICommon
*vsc
= CAST(VHostSCSICommon
, dev
, TYPE_VHOST_SCSI_COMMON
);
3083 void *spapr
= CAST(void, bus
->parent
, "spapr-vscsi");
3084 VirtIOSCSI
*virtio
= CAST(VirtIOSCSI
, bus
->parent
, TYPE_VIRTIO_SCSI
);
3085 USBDevice
*usb
= CAST(USBDevice
, bus
->parent
, TYPE_USB_DEVICE
);
3089 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
3090 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form
3091 * 0x8000 | (target << 8) | (bus << 5) | lun
3092 * (see the "Logical unit addressing format" table in SAM5)
3094 unsigned id
= 0x8000 | (d
->id
<< 8) | (d
->channel
<< 5) | d
->lun
;
3095 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3096 (uint64_t)id
<< 48);
3097 } else if (virtio
) {
3099 * We use SRP luns of the form 01000000 | (target << 8) | lun
3100 * in the top 32 bits of the 64-bit LUN
3101 * Note: the quote above is from SLOF and it is wrong,
3102 * the actual binding is:
3103 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
3105 unsigned id
= 0x1000000 | (d
->id
<< 16) | d
->lun
;
3106 if (d
->lun
>= 256) {
3107 /* Use the LUN "flat space addressing method" */
3110 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3111 (uint64_t)id
<< 32);
3114 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
3115 * in the top 32 bits of the 64-bit LUN
3117 unsigned usb_port
= atoi(usb
->port
->path
);
3118 unsigned id
= 0x1000000 | (usb_port
<< 16) | d
->lun
;
3119 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3120 (uint64_t)id
<< 32);
3125 * SLOF probes the USB devices, and if it recognizes that the device is a
3126 * storage device, it changes its name to "storage" instead of "usb-host",
3127 * and additionally adds a child node for the SCSI LUN, so the correct
3128 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
3130 if (strcmp("usb-host", qdev_fw_name(dev
)) == 0) {
3131 USBDevice
*usbdev
= CAST(USBDevice
, dev
, TYPE_USB_DEVICE
);
3132 if (usb_host_dev_is_scsi_storage(usbdev
)) {
3133 return g_strdup_printf("storage@%s/disk", usbdev
->port
->path
);
3138 /* Replace "pci" with "pci@800000020000000" */
3139 return g_strdup_printf("pci@%"PRIX64
, phb
->buid
);
3143 /* Same logic as virtio above */
3144 unsigned id
= 0x1000000 | (vsc
->target
<< 16) | vsc
->lun
;
3145 return g_strdup_printf("disk@%"PRIX64
, (uint64_t)id
<< 32);
3148 if (g_str_equal("pci-bridge", qdev_fw_name(dev
))) {
3149 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */
3150 PCIDevice
*pcidev
= CAST(PCIDevice
, dev
, TYPE_PCI_DEVICE
);
3151 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev
->devfn
));
3157 static char *spapr_get_kvm_type(Object
*obj
, Error
**errp
)
3159 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3161 return g_strdup(spapr
->kvm_type
);
3164 static void spapr_set_kvm_type(Object
*obj
, const char *value
, Error
**errp
)
3166 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3168 g_free(spapr
->kvm_type
);
3169 spapr
->kvm_type
= g_strdup(value
);
3172 static bool spapr_get_modern_hotplug_events(Object
*obj
, Error
**errp
)
3174 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3176 return spapr
->use_hotplug_event_source
;
3179 static void spapr_set_modern_hotplug_events(Object
*obj
, bool value
,
3182 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3184 spapr
->use_hotplug_event_source
= value
;
3187 static bool spapr_get_msix_emulation(Object
*obj
, Error
**errp
)
3192 static char *spapr_get_resize_hpt(Object
*obj
, Error
**errp
)
3194 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3196 switch (spapr
->resize_hpt
) {
3197 case SPAPR_RESIZE_HPT_DEFAULT
:
3198 return g_strdup("default");
3199 case SPAPR_RESIZE_HPT_DISABLED
:
3200 return g_strdup("disabled");
3201 case SPAPR_RESIZE_HPT_ENABLED
:
3202 return g_strdup("enabled");
3203 case SPAPR_RESIZE_HPT_REQUIRED
:
3204 return g_strdup("required");
3206 g_assert_not_reached();
3209 static void spapr_set_resize_hpt(Object
*obj
, const char *value
, Error
**errp
)
3211 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3213 if (strcmp(value
, "default") == 0) {
3214 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DEFAULT
;
3215 } else if (strcmp(value
, "disabled") == 0) {
3216 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DISABLED
;
3217 } else if (strcmp(value
, "enabled") == 0) {
3218 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_ENABLED
;
3219 } else if (strcmp(value
, "required") == 0) {
3220 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_REQUIRED
;
3222 error_setg(errp
, "Bad value for \"resize-hpt\" property");
3226 static char *spapr_get_ic_mode(Object
*obj
, Error
**errp
)
3228 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3230 if (spapr
->irq
== &spapr_irq_xics_legacy
) {
3231 return g_strdup("legacy");
3232 } else if (spapr
->irq
== &spapr_irq_xics
) {
3233 return g_strdup("xics");
3234 } else if (spapr
->irq
== &spapr_irq_xive
) {
3235 return g_strdup("xive");
3236 } else if (spapr
->irq
== &spapr_irq_dual
) {
3237 return g_strdup("dual");
3239 g_assert_not_reached();
3242 static void spapr_set_ic_mode(Object
*obj
, const char *value
, Error
**errp
)
3244 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3246 if (SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
3247 error_setg(errp
, "This machine only uses the legacy XICS backend, don't pass ic-mode");
3251 /* The legacy IRQ backend can not be set */
3252 if (strcmp(value
, "xics") == 0) {
3253 spapr
->irq
= &spapr_irq_xics
;
3254 } else if (strcmp(value
, "xive") == 0) {
3255 spapr
->irq
= &spapr_irq_xive
;
3256 } else if (strcmp(value
, "dual") == 0) {
3257 spapr
->irq
= &spapr_irq_dual
;
3259 error_setg(errp
, "Bad value for \"ic-mode\" property");
3263 static char *spapr_get_host_model(Object
*obj
, Error
**errp
)
3265 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3267 return g_strdup(spapr
->host_model
);
3270 static void spapr_set_host_model(Object
*obj
, const char *value
, Error
**errp
)
3272 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3274 g_free(spapr
->host_model
);
3275 spapr
->host_model
= g_strdup(value
);
3278 static char *spapr_get_host_serial(Object
*obj
, Error
**errp
)
3280 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3282 return g_strdup(spapr
->host_serial
);
3285 static void spapr_set_host_serial(Object
*obj
, const char *value
, Error
**errp
)
3287 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3289 g_free(spapr
->host_serial
);
3290 spapr
->host_serial
= g_strdup(value
);
3293 static void spapr_instance_init(Object
*obj
)
3295 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3296 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
3298 spapr
->htab_fd
= -1;
3299 spapr
->use_hotplug_event_source
= true;
3300 object_property_add_str(obj
, "kvm-type",
3301 spapr_get_kvm_type
, spapr_set_kvm_type
, NULL
);
3302 object_property_set_description(obj
, "kvm-type",
3303 "Specifies the KVM virtualization mode (HV, PR)",
3305 object_property_add_bool(obj
, "modern-hotplug-events",
3306 spapr_get_modern_hotplug_events
,
3307 spapr_set_modern_hotplug_events
,
3309 object_property_set_description(obj
, "modern-hotplug-events",
3310 "Use dedicated hotplug event mechanism in"
3311 " place of standard EPOW events when possible"
3312 " (required for memory hot-unplug support)",
3314 ppc_compat_add_property(obj
, "max-cpu-compat", &spapr
->max_compat_pvr
,
3315 "Maximum permitted CPU compatibility mode",
3318 object_property_add_str(obj
, "resize-hpt",
3319 spapr_get_resize_hpt
, spapr_set_resize_hpt
, NULL
);
3320 object_property_set_description(obj
, "resize-hpt",
3321 "Resizing of the Hash Page Table (enabled, disabled, required)",
3323 object_property_add_uint32_ptr(obj
, "vsmt",
3324 &spapr
->vsmt
, OBJ_PROP_FLAG_READWRITE
,
3326 object_property_set_description(obj
, "vsmt",
3327 "Virtual SMT: KVM behaves as if this were"
3328 " the host's SMT mode", &error_abort
);
3330 object_property_add_bool(obj
, "vfio-no-msix-emulation",
3331 spapr_get_msix_emulation
, NULL
, NULL
);
3333 object_property_add_uint64_ptr(obj
, "kernel-addr",
3334 &spapr
->kernel_addr
, OBJ_PROP_FLAG_READWRITE
,
3336 object_property_set_description(obj
, "kernel-addr",
3337 stringify(KERNEL_LOAD_ADDR
)
3338 " for -kernel is the default",
3340 spapr
->kernel_addr
= KERNEL_LOAD_ADDR
;
3341 /* The machine class defines the default interrupt controller mode */
3342 spapr
->irq
= smc
->irq
;
3343 object_property_add_str(obj
, "ic-mode", spapr_get_ic_mode
,
3344 spapr_set_ic_mode
, NULL
);
3345 object_property_set_description(obj
, "ic-mode",
3346 "Specifies the interrupt controller mode (xics, xive, dual)",
3349 object_property_add_str(obj
, "host-model",
3350 spapr_get_host_model
, spapr_set_host_model
,
3352 object_property_set_description(obj
, "host-model",
3353 "Host model to advertise in guest device tree", &error_abort
);
3354 object_property_add_str(obj
, "host-serial",
3355 spapr_get_host_serial
, spapr_set_host_serial
,
3357 object_property_set_description(obj
, "host-serial",
3358 "Host serial number to advertise in guest device tree", &error_abort
);
3361 static void spapr_machine_finalizefn(Object
*obj
)
3363 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3365 g_free(spapr
->kvm_type
);
3368 void spapr_do_system_reset_on_cpu(CPUState
*cs
, run_on_cpu_data arg
)
3370 cpu_synchronize_state(cs
);
3371 ppc_cpu_do_system_reset(cs
);
3374 static void spapr_nmi(NMIState
*n
, int cpu_index
, Error
**errp
)
3379 async_run_on_cpu(cs
, spapr_do_system_reset_on_cpu
, RUN_ON_CPU_NULL
);
3383 int spapr_lmb_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
3384 void *fdt
, int *fdt_start_offset
, Error
**errp
)
3389 addr
= spapr_drc_index(drc
) * SPAPR_MEMORY_BLOCK_SIZE
;
3390 node
= object_property_get_uint(OBJECT(drc
->dev
), PC_DIMM_NODE_PROP
,
3392 *fdt_start_offset
= spapr_populate_memory_node(fdt
, node
, addr
,
3393 SPAPR_MEMORY_BLOCK_SIZE
);
3397 static void spapr_add_lmbs(DeviceState
*dev
, uint64_t addr_start
, uint64_t size
,
3398 bool dedicated_hp_event_source
, Error
**errp
)
3401 uint32_t nr_lmbs
= size
/SPAPR_MEMORY_BLOCK_SIZE
;
3403 uint64_t addr
= addr_start
;
3404 bool hotplugged
= spapr_drc_hotplugged(dev
);
3405 Error
*local_err
= NULL
;
3407 for (i
= 0; i
< nr_lmbs
; i
++) {
3408 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3409 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3412 spapr_drc_attach(drc
, dev
, &local_err
);
3414 while (addr
> addr_start
) {
3415 addr
-= SPAPR_MEMORY_BLOCK_SIZE
;
3416 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3417 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3418 spapr_drc_detach(drc
);
3420 error_propagate(errp
, local_err
);
3424 spapr_drc_reset(drc
);
3426 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3428 /* send hotplug notification to the
3429 * guest only in case of hotplugged memory
3432 if (dedicated_hp_event_source
) {
3433 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3434 addr_start
/ SPAPR_MEMORY_BLOCK_SIZE
);
3435 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3437 spapr_drc_index(drc
));
3439 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3445 static void spapr_memory_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3448 Error
*local_err
= NULL
;
3449 SpaprMachineState
*ms
= SPAPR_MACHINE(hotplug_dev
);
3450 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3451 uint64_t size
, addr
, slot
;
3452 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
3454 size
= memory_device_get_region_size(MEMORY_DEVICE(dev
), &error_abort
);
3456 pc_dimm_plug(dimm
, MACHINE(ms
), &local_err
);
3462 addr
= object_property_get_uint(OBJECT(dimm
),
3463 PC_DIMM_ADDR_PROP
, &local_err
);
3467 spapr_add_lmbs(dev
, addr
, size
,
3468 spapr_ovec_test(ms
->ov5_cas
, OV5_HP_EVT
),
3471 slot
= object_property_get_uint(OBJECT(dimm
),
3472 PC_DIMM_SLOT_PROP
, &local_err
);
3476 spapr_add_nvdimm(dev
, slot
, &local_err
);
3486 pc_dimm_unplug(dimm
, MACHINE(ms
));
3488 error_propagate(errp
, local_err
);
3491 static void spapr_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3494 const SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(hotplug_dev
);
3495 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3496 const MachineClass
*mc
= MACHINE_CLASS(smc
);
3497 bool is_nvdimm
= object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
);
3498 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3499 Error
*local_err
= NULL
;
3504 if (!smc
->dr_lmb_enabled
) {
3505 error_setg(errp
, "Memory hotplug not supported for this machine");
3509 if (is_nvdimm
&& !mc
->nvdimm_supported
) {
3510 error_setg(errp
, "NVDIMM hotplug not supported for this machine");
3514 size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
), &local_err
);
3516 error_propagate(errp
, local_err
);
3520 if (!is_nvdimm
&& size
% SPAPR_MEMORY_BLOCK_SIZE
) {
3521 error_setg(errp
, "Hotplugged memory size must be a multiple of "
3522 "%" PRIu64
" MB", SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
3524 } else if (is_nvdimm
) {
3525 spapr_nvdimm_validate_opts(NVDIMM(dev
), size
, &local_err
);
3527 error_propagate(errp
, local_err
);
3532 memdev
= object_property_get_link(OBJECT(dimm
), PC_DIMM_MEMDEV_PROP
,
3534 pagesize
= host_memory_backend_pagesize(MEMORY_BACKEND(memdev
));
3535 spapr_check_pagesize(spapr
, pagesize
, &local_err
);
3537 error_propagate(errp
, local_err
);
3541 pc_dimm_pre_plug(dimm
, MACHINE(hotplug_dev
), NULL
, errp
);
3544 struct SpaprDimmState
{
3547 QTAILQ_ENTRY(SpaprDimmState
) next
;
3550 static SpaprDimmState
*spapr_pending_dimm_unplugs_find(SpaprMachineState
*s
,
3553 SpaprDimmState
*dimm_state
= NULL
;
3555 QTAILQ_FOREACH(dimm_state
, &s
->pending_dimm_unplugs
, next
) {
3556 if (dimm_state
->dimm
== dimm
) {
3563 static SpaprDimmState
*spapr_pending_dimm_unplugs_add(SpaprMachineState
*spapr
,
3567 SpaprDimmState
*ds
= NULL
;
3570 * If this request is for a DIMM whose removal had failed earlier
3571 * (due to guest's refusal to remove the LMBs), we would have this
3572 * dimm already in the pending_dimm_unplugs list. In that
3573 * case don't add again.
3575 ds
= spapr_pending_dimm_unplugs_find(spapr
, dimm
);
3577 ds
= g_malloc0(sizeof(SpaprDimmState
));
3578 ds
->nr_lmbs
= nr_lmbs
;
3580 QTAILQ_INSERT_HEAD(&spapr
->pending_dimm_unplugs
, ds
, next
);
3585 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState
*spapr
,
3586 SpaprDimmState
*dimm_state
)
3588 QTAILQ_REMOVE(&spapr
->pending_dimm_unplugs
, dimm_state
, next
);
3592 static SpaprDimmState
*spapr_recover_pending_dimm_state(SpaprMachineState
*ms
,
3596 uint64_t size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
),
3598 uint32_t nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
3599 uint32_t avail_lmbs
= 0;
3600 uint64_t addr_start
, addr
;
3603 addr_start
= object_property_get_int(OBJECT(dimm
), PC_DIMM_ADDR_PROP
,
3607 for (i
= 0; i
< nr_lmbs
; i
++) {
3608 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3609 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3614 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3617 return spapr_pending_dimm_unplugs_add(ms
, avail_lmbs
, dimm
);
3620 /* Callback to be called during DRC release. */
3621 void spapr_lmb_release(DeviceState
*dev
)
3623 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
3624 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_ctrl
);
3625 SpaprDimmState
*ds
= spapr_pending_dimm_unplugs_find(spapr
, PC_DIMM(dev
));
3627 /* This information will get lost if a migration occurs
3628 * during the unplug process. In this case recover it. */
3630 ds
= spapr_recover_pending_dimm_state(spapr
, PC_DIMM(dev
));
3632 /* The DRC being examined by the caller at least must be counted */
3633 g_assert(ds
->nr_lmbs
);
3636 if (--ds
->nr_lmbs
) {
3641 * Now that all the LMBs have been removed by the guest, call the
3642 * unplug handler chain. This can never fail.
3644 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
3645 object_unparent(OBJECT(dev
));
3648 static void spapr_memory_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3650 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3651 SpaprDimmState
*ds
= spapr_pending_dimm_unplugs_find(spapr
, PC_DIMM(dev
));
3653 pc_dimm_unplug(PC_DIMM(dev
), MACHINE(hotplug_dev
));
3654 object_property_set_bool(OBJECT(dev
), false, "realized", NULL
);
3655 spapr_pending_dimm_unplugs_remove(spapr
, ds
);
3658 static void spapr_memory_unplug_request(HotplugHandler
*hotplug_dev
,
3659 DeviceState
*dev
, Error
**errp
)
3661 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3662 Error
*local_err
= NULL
;
3663 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3665 uint64_t size
, addr_start
, addr
;
3669 if (object_dynamic_cast(OBJECT(dev
), TYPE_NVDIMM
)) {
3670 error_setg(&local_err
,
3671 "nvdimm device hot unplug is not supported yet.");
3675 size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
), &error_abort
);
3676 nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
3678 addr_start
= object_property_get_uint(OBJECT(dimm
), PC_DIMM_ADDR_PROP
,
3685 * An existing pending dimm state for this DIMM means that there is an
3686 * unplug operation in progress, waiting for the spapr_lmb_release
3687 * callback to complete the job (BQL can't cover that far). In this case,
3688 * bail out to avoid detaching DRCs that were already released.
3690 if (spapr_pending_dimm_unplugs_find(spapr
, dimm
)) {
3691 error_setg(&local_err
,
3692 "Memory unplug already in progress for device %s",
3697 spapr_pending_dimm_unplugs_add(spapr
, nr_lmbs
, dimm
);
3700 for (i
= 0; i
< nr_lmbs
; i
++) {
3701 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3702 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3705 spapr_drc_detach(drc
);
3706 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3709 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3710 addr_start
/ SPAPR_MEMORY_BLOCK_SIZE
);
3711 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3712 nr_lmbs
, spapr_drc_index(drc
));
3714 error_propagate(errp
, local_err
);
3717 /* Callback to be called during DRC release. */
3718 void spapr_core_release(DeviceState
*dev
)
3720 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
3722 /* Call the unplug handler chain. This can never fail. */
3723 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
3724 object_unparent(OBJECT(dev
));
3727 static void spapr_core_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3729 MachineState
*ms
= MACHINE(hotplug_dev
);
3730 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(ms
);
3731 CPUCore
*cc
= CPU_CORE(dev
);
3732 CPUArchId
*core_slot
= spapr_find_cpu_slot(ms
, cc
->core_id
, NULL
);
3734 if (smc
->pre_2_10_has_unused_icps
) {
3735 SpaprCpuCore
*sc
= SPAPR_CPU_CORE(OBJECT(dev
));
3738 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3739 CPUState
*cs
= CPU(sc
->threads
[i
]);
3741 pre_2_10_vmstate_register_dummy_icp(cs
->cpu_index
);
3746 core_slot
->cpu
= NULL
;
3747 object_property_set_bool(OBJECT(dev
), false, "realized", NULL
);
3751 void spapr_core_unplug_request(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3754 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3757 CPUCore
*cc
= CPU_CORE(dev
);
3759 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
)) {
3760 error_setg(errp
, "Unable to find CPU core with core-id: %d",
3765 error_setg(errp
, "Boot CPU core may not be unplugged");
3769 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
,
3770 spapr_vcpu_id(spapr
, cc
->core_id
));
3773 if (!spapr_drc_unplug_requested(drc
)) {
3774 spapr_drc_detach(drc
);
3775 spapr_hotplug_req_remove_by_index(drc
);
3779 int spapr_core_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
3780 void *fdt
, int *fdt_start_offset
, Error
**errp
)
3782 SpaprCpuCore
*core
= SPAPR_CPU_CORE(drc
->dev
);
3783 CPUState
*cs
= CPU(core
->threads
[0]);
3784 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
3785 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
3786 int id
= spapr_get_vcpu_id(cpu
);
3790 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, id
);
3791 offset
= fdt_add_subnode(fdt
, 0, nodename
);
3794 spapr_populate_cpu_dt(cs
, fdt
, offset
, spapr
);
3796 *fdt_start_offset
= offset
;
3800 static void spapr_core_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3803 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3804 MachineClass
*mc
= MACHINE_GET_CLASS(spapr
);
3805 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
3806 SpaprCpuCore
*core
= SPAPR_CPU_CORE(OBJECT(dev
));
3807 CPUCore
*cc
= CPU_CORE(dev
);
3810 Error
*local_err
= NULL
;
3811 CPUArchId
*core_slot
;
3813 bool hotplugged
= spapr_drc_hotplugged(dev
);
3816 core_slot
= spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
);
3818 error_setg(errp
, "Unable to find CPU core with core-id: %d",
3822 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
,
3823 spapr_vcpu_id(spapr
, cc
->core_id
));
3825 g_assert(drc
|| !mc
->has_hotpluggable_cpus
);
3828 spapr_drc_attach(drc
, dev
, &local_err
);
3830 error_propagate(errp
, local_err
);
3836 * Send hotplug notification interrupt to the guest only
3837 * in case of hotplugged CPUs.
3839 spapr_hotplug_req_add_by_index(drc
);
3841 spapr_drc_reset(drc
);
3845 core_slot
->cpu
= OBJECT(dev
);
3847 if (smc
->pre_2_10_has_unused_icps
) {
3848 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3849 cs
= CPU(core
->threads
[i
]);
3850 pre_2_10_vmstate_unregister_dummy_icp(cs
->cpu_index
);
3855 * Set compatibility mode to match the boot CPU, which was either set
3856 * by the machine reset code or by CAS.
3859 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3860 ppc_set_compat(core
->threads
[i
], POWERPC_CPU(first_cpu
)->compat_pvr
,
3863 error_propagate(errp
, local_err
);
3870 static void spapr_core_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3873 MachineState
*machine
= MACHINE(OBJECT(hotplug_dev
));
3874 MachineClass
*mc
= MACHINE_GET_CLASS(hotplug_dev
);
3875 Error
*local_err
= NULL
;
3876 CPUCore
*cc
= CPU_CORE(dev
);
3877 const char *base_core_type
= spapr_get_cpu_core_type(machine
->cpu_type
);
3878 const char *type
= object_get_typename(OBJECT(dev
));
3879 CPUArchId
*core_slot
;
3881 unsigned int smp_threads
= machine
->smp
.threads
;
3883 if (dev
->hotplugged
&& !mc
->has_hotpluggable_cpus
) {
3884 error_setg(&local_err
, "CPU hotplug not supported for this machine");
3888 if (strcmp(base_core_type
, type
)) {
3889 error_setg(&local_err
, "CPU core type should be %s", base_core_type
);
3893 if (cc
->core_id
% smp_threads
) {
3894 error_setg(&local_err
, "invalid core id %d", cc
->core_id
);
3899 * In general we should have homogeneous threads-per-core, but old
3900 * (pre hotplug support) machine types allow the last core to have
3901 * reduced threads as a compatibility hack for when we allowed
3902 * total vcpus not a multiple of threads-per-core.
3904 if (mc
->has_hotpluggable_cpus
&& (cc
->nr_threads
!= smp_threads
)) {
3905 error_setg(&local_err
, "invalid nr-threads %d, must be %d",
3906 cc
->nr_threads
, smp_threads
);
3910 core_slot
= spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
);
3912 error_setg(&local_err
, "core id %d out of range", cc
->core_id
);
3916 if (core_slot
->cpu
) {
3917 error_setg(&local_err
, "core %d already populated", cc
->core_id
);
3921 numa_cpu_pre_plug(core_slot
, dev
, &local_err
);
3924 error_propagate(errp
, local_err
);
3927 int spapr_phb_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
3928 void *fdt
, int *fdt_start_offset
, Error
**errp
)
3930 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(drc
->dev
);
3933 intc_phandle
= spapr_irq_get_phandle(spapr
, spapr
->fdt_blob
, errp
);
3934 if (intc_phandle
<= 0) {
3938 if (spapr_dt_phb(spapr
, sphb
, intc_phandle
, fdt
, fdt_start_offset
)) {
3939 error_setg(errp
, "unable to create FDT node for PHB %d", sphb
->index
);
3943 /* generally SLOF creates these, for hotplug it's up to QEMU */
3944 _FDT(fdt_setprop_string(fdt
, *fdt_start_offset
, "name", "pci"));
3949 static void spapr_phb_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3952 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3953 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(dev
);
3954 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
3955 const unsigned windows_supported
= spapr_phb_windows_supported(sphb
);
3957 if (dev
->hotplugged
&& !smc
->dr_phb_enabled
) {
3958 error_setg(errp
, "PHB hotplug not supported for this machine");
3962 if (sphb
->index
== (uint32_t)-1) {
3963 error_setg(errp
, "\"index\" for PAPR PHB is mandatory");
3968 * This will check that sphb->index doesn't exceed the maximum number of
3969 * PHBs for the current machine type.
3971 smc
->phb_placement(spapr
, sphb
->index
,
3972 &sphb
->buid
, &sphb
->io_win_addr
,
3973 &sphb
->mem_win_addr
, &sphb
->mem64_win_addr
,
3974 windows_supported
, sphb
->dma_liobn
,
3975 &sphb
->nv2_gpa_win_addr
, &sphb
->nv2_atsd_win_addr
,
3979 static void spapr_phb_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3982 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3983 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
3984 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(dev
);
3986 bool hotplugged
= spapr_drc_hotplugged(dev
);
3987 Error
*local_err
= NULL
;
3989 if (!smc
->dr_phb_enabled
) {
3993 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_PHB
, sphb
->index
);
3994 /* hotplug hooks should check it's enabled before getting this far */
3997 spapr_drc_attach(drc
, DEVICE(dev
), &local_err
);
3999 error_propagate(errp
, local_err
);
4004 spapr_hotplug_req_add_by_index(drc
);
4006 spapr_drc_reset(drc
);
4010 void spapr_phb_release(DeviceState
*dev
)
4012 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
4014 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
4015 object_unparent(OBJECT(dev
));
4018 static void spapr_phb_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
4020 object_property_set_bool(OBJECT(dev
), false, "realized", NULL
);
4023 static void spapr_phb_unplug_request(HotplugHandler
*hotplug_dev
,
4024 DeviceState
*dev
, Error
**errp
)
4026 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(dev
);
4029 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_PHB
, sphb
->index
);
4032 if (!spapr_drc_unplug_requested(drc
)) {
4033 spapr_drc_detach(drc
);
4034 spapr_hotplug_req_remove_by_index(drc
);
4038 static void spapr_tpm_proxy_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
4041 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4042 SpaprTpmProxy
*tpm_proxy
= SPAPR_TPM_PROXY(dev
);
4044 if (spapr
->tpm_proxy
!= NULL
) {
4045 error_setg(errp
, "Only one TPM proxy can be specified for this machine");
4049 spapr
->tpm_proxy
= tpm_proxy
;
4052 static void spapr_tpm_proxy_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
4054 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4056 object_property_set_bool(OBJECT(dev
), false, "realized", NULL
);
4057 object_unparent(OBJECT(dev
));
4058 spapr
->tpm_proxy
= NULL
;
4061 static void spapr_machine_device_plug(HotplugHandler
*hotplug_dev
,
4062 DeviceState
*dev
, Error
**errp
)
4064 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4065 spapr_memory_plug(hotplug_dev
, dev
, errp
);
4066 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4067 spapr_core_plug(hotplug_dev
, dev
, errp
);
4068 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4069 spapr_phb_plug(hotplug_dev
, dev
, errp
);
4070 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4071 spapr_tpm_proxy_plug(hotplug_dev
, dev
, errp
);
4075 static void spapr_machine_device_unplug(HotplugHandler
*hotplug_dev
,
4076 DeviceState
*dev
, Error
**errp
)
4078 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4079 spapr_memory_unplug(hotplug_dev
, dev
);
4080 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4081 spapr_core_unplug(hotplug_dev
, dev
);
4082 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4083 spapr_phb_unplug(hotplug_dev
, dev
);
4084 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4085 spapr_tpm_proxy_unplug(hotplug_dev
, dev
);
4089 static void spapr_machine_device_unplug_request(HotplugHandler
*hotplug_dev
,
4090 DeviceState
*dev
, Error
**errp
)
4092 SpaprMachineState
*sms
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4093 MachineClass
*mc
= MACHINE_GET_CLASS(sms
);
4094 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4096 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4097 if (spapr_ovec_test(sms
->ov5_cas
, OV5_HP_EVT
)) {
4098 spapr_memory_unplug_request(hotplug_dev
, dev
, errp
);
4100 /* NOTE: this means there is a window after guest reset, prior to
4101 * CAS negotiation, where unplug requests will fail due to the
4102 * capability not being detected yet. This is a bit different than
4103 * the case with PCI unplug, where the events will be queued and
4104 * eventually handled by the guest after boot
4106 error_setg(errp
, "Memory hot unplug not supported for this guest");
4108 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4109 if (!mc
->has_hotpluggable_cpus
) {
4110 error_setg(errp
, "CPU hot unplug not supported on this machine");
4113 spapr_core_unplug_request(hotplug_dev
, dev
, errp
);
4114 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4115 if (!smc
->dr_phb_enabled
) {
4116 error_setg(errp
, "PHB hot unplug not supported on this machine");
4119 spapr_phb_unplug_request(hotplug_dev
, dev
, errp
);
4120 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4121 spapr_tpm_proxy_unplug(hotplug_dev
, dev
);
4125 static void spapr_machine_device_pre_plug(HotplugHandler
*hotplug_dev
,
4126 DeviceState
*dev
, Error
**errp
)
4128 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4129 spapr_memory_pre_plug(hotplug_dev
, dev
, errp
);
4130 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4131 spapr_core_pre_plug(hotplug_dev
, dev
, errp
);
4132 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4133 spapr_phb_pre_plug(hotplug_dev
, dev
, errp
);
4137 static HotplugHandler
*spapr_get_hotplug_handler(MachineState
*machine
,
4140 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
4141 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
) ||
4142 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
) ||
4143 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_TPM_PROXY
)) {
4144 return HOTPLUG_HANDLER(machine
);
4146 if (object_dynamic_cast(OBJECT(dev
), TYPE_PCI_DEVICE
)) {
4147 PCIDevice
*pcidev
= PCI_DEVICE(dev
);
4148 PCIBus
*root
= pci_device_root_bus(pcidev
);
4149 SpaprPhbState
*phb
=
4150 (SpaprPhbState
*)object_dynamic_cast(OBJECT(BUS(root
)->parent
),
4151 TYPE_SPAPR_PCI_HOST_BRIDGE
);
4154 return HOTPLUG_HANDLER(phb
);
4160 static CpuInstanceProperties
4161 spapr_cpu_index_to_props(MachineState
*machine
, unsigned cpu_index
)
4163 CPUArchId
*core_slot
;
4164 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
4166 /* make sure possible_cpu are intialized */
4167 mc
->possible_cpu_arch_ids(machine
);
4168 /* get CPU core slot containing thread that matches cpu_index */
4169 core_slot
= spapr_find_cpu_slot(machine
, cpu_index
, NULL
);
4171 return core_slot
->props
;
4174 static int64_t spapr_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
4176 return idx
/ ms
->smp
.cores
% ms
->numa_state
->num_nodes
;
4179 static const CPUArchIdList
*spapr_possible_cpu_arch_ids(MachineState
*machine
)
4182 unsigned int smp_threads
= machine
->smp
.threads
;
4183 unsigned int smp_cpus
= machine
->smp
.cpus
;
4184 const char *core_type
;
4185 int spapr_max_cores
= machine
->smp
.max_cpus
/ smp_threads
;
4186 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
4188 if (!mc
->has_hotpluggable_cpus
) {
4189 spapr_max_cores
= QEMU_ALIGN_UP(smp_cpus
, smp_threads
) / smp_threads
;
4191 if (machine
->possible_cpus
) {
4192 assert(machine
->possible_cpus
->len
== spapr_max_cores
);
4193 return machine
->possible_cpus
;
4196 core_type
= spapr_get_cpu_core_type(machine
->cpu_type
);
4198 error_report("Unable to find sPAPR CPU Core definition");
4202 machine
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
4203 sizeof(CPUArchId
) * spapr_max_cores
);
4204 machine
->possible_cpus
->len
= spapr_max_cores
;
4205 for (i
= 0; i
< machine
->possible_cpus
->len
; i
++) {
4206 int core_id
= i
* smp_threads
;
4208 machine
->possible_cpus
->cpus
[i
].type
= core_type
;
4209 machine
->possible_cpus
->cpus
[i
].vcpus_count
= smp_threads
;
4210 machine
->possible_cpus
->cpus
[i
].arch_id
= core_id
;
4211 machine
->possible_cpus
->cpus
[i
].props
.has_core_id
= true;
4212 machine
->possible_cpus
->cpus
[i
].props
.core_id
= core_id
;
4214 return machine
->possible_cpus
;
4217 static void spapr_phb_placement(SpaprMachineState
*spapr
, uint32_t index
,
4218 uint64_t *buid
, hwaddr
*pio
,
4219 hwaddr
*mmio32
, hwaddr
*mmio64
,
4220 unsigned n_dma
, uint32_t *liobns
,
4221 hwaddr
*nv2gpa
, hwaddr
*nv2atsd
, Error
**errp
)
4224 * New-style PHB window placement.
4226 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
4227 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
4230 * Some guest kernels can't work with MMIO windows above 1<<46
4231 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
4233 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
4234 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the
4235 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the
4236 * 1TiB 64-bit MMIO windows for each PHB.
4238 const uint64_t base_buid
= 0x800000020000000ULL
;
4241 /* Sanity check natural alignments */
4242 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE
% SPAPR_PCI_MEM64_WIN_SIZE
) != 0);
4243 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT
% SPAPR_PCI_MEM64_WIN_SIZE
) != 0);
4244 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE
% SPAPR_PCI_MEM32_WIN_SIZE
) != 0);
4245 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE
% SPAPR_PCI_IO_WIN_SIZE
) != 0);
4246 /* Sanity check bounds */
4247 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS
* SPAPR_PCI_IO_WIN_SIZE
) >
4248 SPAPR_PCI_MEM32_WIN_SIZE
);
4249 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS
* SPAPR_PCI_MEM32_WIN_SIZE
) >
4250 SPAPR_PCI_MEM64_WIN_SIZE
);
4252 if (index
>= SPAPR_MAX_PHBS
) {
4253 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %llu)",
4254 SPAPR_MAX_PHBS
- 1);
4258 *buid
= base_buid
+ index
;
4259 for (i
= 0; i
< n_dma
; ++i
) {
4260 liobns
[i
] = SPAPR_PCI_LIOBN(index
, i
);
4263 *pio
= SPAPR_PCI_BASE
+ index
* SPAPR_PCI_IO_WIN_SIZE
;
4264 *mmio32
= SPAPR_PCI_BASE
+ (index
+ 1) * SPAPR_PCI_MEM32_WIN_SIZE
;
4265 *mmio64
= SPAPR_PCI_BASE
+ (index
+ 1) * SPAPR_PCI_MEM64_WIN_SIZE
;
4267 *nv2gpa
= SPAPR_PCI_NV2RAM64_WIN_BASE
+ index
* SPAPR_PCI_NV2RAM64_WIN_SIZE
;
4268 *nv2atsd
= SPAPR_PCI_NV2ATSD_WIN_BASE
+ index
* SPAPR_PCI_NV2ATSD_WIN_SIZE
;
4271 static ICSState
*spapr_ics_get(XICSFabric
*dev
, int irq
)
4273 SpaprMachineState
*spapr
= SPAPR_MACHINE(dev
);
4275 return ics_valid_irq(spapr
->ics
, irq
) ? spapr
->ics
: NULL
;
4278 static void spapr_ics_resend(XICSFabric
*dev
)
4280 SpaprMachineState
*spapr
= SPAPR_MACHINE(dev
);
4282 ics_resend(spapr
->ics
);
4285 static ICPState
*spapr_icp_get(XICSFabric
*xi
, int vcpu_id
)
4287 PowerPCCPU
*cpu
= spapr_find_cpu(vcpu_id
);
4289 return cpu
? spapr_cpu_state(cpu
)->icp
: NULL
;
4292 static void spapr_pic_print_info(InterruptStatsProvider
*obj
,
4295 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
4297 spapr_irq_print_info(spapr
, mon
);
4298 monitor_printf(mon
, "irqchip: %s\n",
4299 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated");
4303 * This is a XIVE only operation
4305 static int spapr_match_nvt(XiveFabric
*xfb
, uint8_t format
,
4306 uint8_t nvt_blk
, uint32_t nvt_idx
,
4307 bool cam_ignore
, uint8_t priority
,
4308 uint32_t logic_serv
, XiveTCTXMatch
*match
)
4310 SpaprMachineState
*spapr
= SPAPR_MACHINE(xfb
);
4311 XivePresenter
*xptr
= XIVE_PRESENTER(spapr
->active_intc
);
4312 XivePresenterClass
*xpc
= XIVE_PRESENTER_GET_CLASS(xptr
);
4315 count
= xpc
->match_nvt(xptr
, format
, nvt_blk
, nvt_idx
, cam_ignore
,
4316 priority
, logic_serv
, match
);
4322 * When we implement the save and restore of the thread interrupt
4323 * contexts in the enter/exit CPU handlers of the machine and the
4324 * escalations in QEMU, we should be able to handle non dispatched
4327 * Until this is done, the sPAPR machine should find at least one
4328 * matching context always.
4331 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: NVT %x/%x is not dispatched\n",
4338 int spapr_get_vcpu_id(PowerPCCPU
*cpu
)
4340 return cpu
->vcpu_id
;
4343 void spapr_set_vcpu_id(PowerPCCPU
*cpu
, int cpu_index
, Error
**errp
)
4345 SpaprMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
4346 MachineState
*ms
= MACHINE(spapr
);
4349 vcpu_id
= spapr_vcpu_id(spapr
, cpu_index
);
4351 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id
)) {
4352 error_setg(errp
, "Can't create CPU with id %d in KVM", vcpu_id
);
4353 error_append_hint(errp
, "Adjust the number of cpus to %d "
4354 "or try to raise the number of threads per core\n",
4355 vcpu_id
* ms
->smp
.threads
/ spapr
->vsmt
);
4359 cpu
->vcpu_id
= vcpu_id
;
4362 PowerPCCPU
*spapr_find_cpu(int vcpu_id
)
4367 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
4369 if (spapr_get_vcpu_id(cpu
) == vcpu_id
) {
4377 static void spapr_cpu_exec_enter(PPCVirtualHypervisor
*vhyp
, PowerPCCPU
*cpu
)
4379 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
4381 /* These are only called by TCG, KVM maintains dispatch state */
4383 spapr_cpu
->prod
= false;
4384 if (spapr_cpu
->vpa_addr
) {
4385 CPUState
*cs
= CPU(cpu
);
4388 dispatch
= ldl_be_phys(cs
->as
,
4389 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
);
4391 if ((dispatch
& 1) != 0) {
4392 qemu_log_mask(LOG_GUEST_ERROR
,
4393 "VPA: incorrect dispatch counter value for "
4394 "dispatched partition %u, correcting.\n", dispatch
);
4398 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
, dispatch
);
4402 static void spapr_cpu_exec_exit(PPCVirtualHypervisor
*vhyp
, PowerPCCPU
*cpu
)
4404 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
4406 if (spapr_cpu
->vpa_addr
) {
4407 CPUState
*cs
= CPU(cpu
);
4410 dispatch
= ldl_be_phys(cs
->as
,
4411 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
);
4413 if ((dispatch
& 1) != 1) {
4414 qemu_log_mask(LOG_GUEST_ERROR
,
4415 "VPA: incorrect dispatch counter value for "
4416 "preempted partition %u, correcting.\n", dispatch
);
4420 spapr_cpu
->vpa_addr
+ VPA_DISPATCH_COUNTER
, dispatch
);
4424 static void spapr_machine_class_init(ObjectClass
*oc
, void *data
)
4426 MachineClass
*mc
= MACHINE_CLASS(oc
);
4427 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(oc
);
4428 FWPathProviderClass
*fwc
= FW_PATH_PROVIDER_CLASS(oc
);
4429 NMIClass
*nc
= NMI_CLASS(oc
);
4430 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
4431 PPCVirtualHypervisorClass
*vhc
= PPC_VIRTUAL_HYPERVISOR_CLASS(oc
);
4432 XICSFabricClass
*xic
= XICS_FABRIC_CLASS(oc
);
4433 InterruptStatsProviderClass
*ispc
= INTERRUPT_STATS_PROVIDER_CLASS(oc
);
4434 XiveFabricClass
*xfc
= XIVE_FABRIC_CLASS(oc
);
4436 mc
->desc
= "pSeries Logical Partition (PAPR compliant)";
4437 mc
->ignore_boot_device_suffixes
= true;
4440 * We set up the default / latest behaviour here. The class_init
4441 * functions for the specific versioned machine types can override
4442 * these details for backwards compatibility
4444 mc
->init
= spapr_machine_init
;
4445 mc
->reset
= spapr_machine_reset
;
4446 mc
->block_default_type
= IF_SCSI
;
4447 mc
->max_cpus
= 1024;
4448 mc
->no_parallel
= 1;
4449 mc
->default_boot_order
= "";
4450 mc
->default_ram_size
= 512 * MiB
;
4451 mc
->default_ram_id
= "ppc_spapr.ram";
4452 mc
->default_display
= "std";
4453 mc
->kvm_type
= spapr_kvm_type
;
4454 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
4455 mc
->pci_allow_0_address
= true;
4456 assert(!mc
->get_hotplug_handler
);
4457 mc
->get_hotplug_handler
= spapr_get_hotplug_handler
;
4458 hc
->pre_plug
= spapr_machine_device_pre_plug
;
4459 hc
->plug
= spapr_machine_device_plug
;
4460 mc
->cpu_index_to_instance_props
= spapr_cpu_index_to_props
;
4461 mc
->get_default_cpu_node_id
= spapr_get_default_cpu_node_id
;
4462 mc
->possible_cpu_arch_ids
= spapr_possible_cpu_arch_ids
;
4463 hc
->unplug_request
= spapr_machine_device_unplug_request
;
4464 hc
->unplug
= spapr_machine_device_unplug
;
4466 smc
->dr_lmb_enabled
= true;
4467 smc
->update_dt_enabled
= true;
4468 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power9_v2.0");
4469 mc
->has_hotpluggable_cpus
= true;
4470 mc
->nvdimm_supported
= true;
4471 smc
->resize_hpt_default
= SPAPR_RESIZE_HPT_ENABLED
;
4472 fwc
->get_dev_path
= spapr_get_fw_dev_path
;
4473 nc
->nmi_monitor_handler
= spapr_nmi
;
4474 smc
->phb_placement
= spapr_phb_placement
;
4475 vhc
->hypercall
= emulate_spapr_hypercall
;
4476 vhc
->hpt_mask
= spapr_hpt_mask
;
4477 vhc
->map_hptes
= spapr_map_hptes
;
4478 vhc
->unmap_hptes
= spapr_unmap_hptes
;
4479 vhc
->hpte_set_c
= spapr_hpte_set_c
;
4480 vhc
->hpte_set_r
= spapr_hpte_set_r
;
4481 vhc
->get_pate
= spapr_get_pate
;
4482 vhc
->encode_hpt_for_kvm_pr
= spapr_encode_hpt_for_kvm_pr
;
4483 vhc
->cpu_exec_enter
= spapr_cpu_exec_enter
;
4484 vhc
->cpu_exec_exit
= spapr_cpu_exec_exit
;
4485 xic
->ics_get
= spapr_ics_get
;
4486 xic
->ics_resend
= spapr_ics_resend
;
4487 xic
->icp_get
= spapr_icp_get
;
4488 ispc
->print_info
= spapr_pic_print_info
;
4489 /* Force NUMA node memory size to be a multiple of
4490 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity
4491 * in which LMBs are represented and hot-added
4493 mc
->numa_mem_align_shift
= 28;
4494 mc
->numa_mem_supported
= true;
4495 mc
->auto_enable_numa
= true;
4497 smc
->default_caps
.caps
[SPAPR_CAP_HTM
] = SPAPR_CAP_OFF
;
4498 smc
->default_caps
.caps
[SPAPR_CAP_VSX
] = SPAPR_CAP_ON
;
4499 smc
->default_caps
.caps
[SPAPR_CAP_DFP
] = SPAPR_CAP_ON
;
4500 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_WORKAROUND
;
4501 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_WORKAROUND
;
4502 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_WORKAROUND
;
4503 smc
->default_caps
.caps
[SPAPR_CAP_HPT_MAXPAGESIZE
] = 16; /* 64kiB */
4504 smc
->default_caps
.caps
[SPAPR_CAP_NESTED_KVM_HV
] = SPAPR_CAP_OFF
;
4505 smc
->default_caps
.caps
[SPAPR_CAP_LARGE_DECREMENTER
] = SPAPR_CAP_ON
;
4506 smc
->default_caps
.caps
[SPAPR_CAP_CCF_ASSIST
] = SPAPR_CAP_ON
;
4507 smc
->default_caps
.caps
[SPAPR_CAP_FWNMI_MCE
] = SPAPR_CAP_ON
;
4508 spapr_caps_add_properties(smc
, &error_abort
);
4509 smc
->irq
= &spapr_irq_dual
;
4510 smc
->dr_phb_enabled
= true;
4511 smc
->linux_pci_probe
= true;
4512 smc
->smp_threads_vsmt
= true;
4513 smc
->nr_xirqs
= SPAPR_NR_XIRQS
;
4514 xfc
->match_nvt
= spapr_match_nvt
;
4517 static const TypeInfo spapr_machine_info
= {
4518 .name
= TYPE_SPAPR_MACHINE
,
4519 .parent
= TYPE_MACHINE
,
4521 .instance_size
= sizeof(SpaprMachineState
),
4522 .instance_init
= spapr_instance_init
,
4523 .instance_finalize
= spapr_machine_finalizefn
,
4524 .class_size
= sizeof(SpaprMachineClass
),
4525 .class_init
= spapr_machine_class_init
,
4526 .interfaces
= (InterfaceInfo
[]) {
4527 { TYPE_FW_PATH_PROVIDER
},
4529 { TYPE_HOTPLUG_HANDLER
},
4530 { TYPE_PPC_VIRTUAL_HYPERVISOR
},
4531 { TYPE_XICS_FABRIC
},
4532 { TYPE_INTERRUPT_STATS_PROVIDER
},
4533 { TYPE_XIVE_FABRIC
},
4538 static void spapr_machine_latest_class_options(MachineClass
*mc
)
4540 mc
->alias
= "pseries";
4541 mc
->is_default
= true;
4544 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
4545 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
4548 MachineClass *mc = MACHINE_CLASS(oc); \
4549 spapr_machine_##suffix##_class_options(mc); \
4551 spapr_machine_latest_class_options(mc); \
4554 static const TypeInfo spapr_machine_##suffix##_info = { \
4555 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
4556 .parent = TYPE_SPAPR_MACHINE, \
4557 .class_init = spapr_machine_##suffix##_class_init, \
4559 static void spapr_machine_register_##suffix(void) \
4561 type_register(&spapr_machine_##suffix##_info); \
4563 type_init(spapr_machine_register_##suffix)
4568 static void spapr_machine_5_0_class_options(MachineClass
*mc
)
4570 /* Defaults for the latest behaviour inherited from the base class */
4573 DEFINE_SPAPR_MACHINE(5_0
, "5.0", true);
4578 static void spapr_machine_4_2_class_options(MachineClass
*mc
)
4580 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4582 spapr_machine_5_0_class_options(mc
);
4583 compat_props_add(mc
->compat_props
, hw_compat_4_2
, hw_compat_4_2_len
);
4584 smc
->default_caps
.caps
[SPAPR_CAP_CCF_ASSIST
] = SPAPR_CAP_OFF
;
4585 smc
->default_caps
.caps
[SPAPR_CAP_FWNMI_MCE
] = SPAPR_CAP_OFF
;
4586 mc
->nvdimm_supported
= false;
4589 DEFINE_SPAPR_MACHINE(4_2
, "4.2", false);
4594 static void spapr_machine_4_1_class_options(MachineClass
*mc
)
4596 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4597 static GlobalProperty compat
[] = {
4598 /* Only allow 4kiB and 64kiB IOMMU pagesizes */
4599 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pgsz", "0x11000" },
4602 spapr_machine_4_2_class_options(mc
);
4603 smc
->linux_pci_probe
= false;
4604 smc
->smp_threads_vsmt
= false;
4605 compat_props_add(mc
->compat_props
, hw_compat_4_1
, hw_compat_4_1_len
);
4606 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4609 DEFINE_SPAPR_MACHINE(4_1
, "4.1", false);
4614 static void phb_placement_4_0(SpaprMachineState
*spapr
, uint32_t index
,
4615 uint64_t *buid
, hwaddr
*pio
,
4616 hwaddr
*mmio32
, hwaddr
*mmio64
,
4617 unsigned n_dma
, uint32_t *liobns
,
4618 hwaddr
*nv2gpa
, hwaddr
*nv2atsd
, Error
**errp
)
4620 spapr_phb_placement(spapr
, index
, buid
, pio
, mmio32
, mmio64
, n_dma
, liobns
,
4621 nv2gpa
, nv2atsd
, errp
);
4626 static void spapr_machine_4_0_class_options(MachineClass
*mc
)
4628 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4630 spapr_machine_4_1_class_options(mc
);
4631 compat_props_add(mc
->compat_props
, hw_compat_4_0
, hw_compat_4_0_len
);
4632 smc
->phb_placement
= phb_placement_4_0
;
4633 smc
->irq
= &spapr_irq_xics
;
4634 smc
->pre_4_1_migration
= true;
4637 DEFINE_SPAPR_MACHINE(4_0
, "4.0", false);
4642 static void spapr_machine_3_1_class_options(MachineClass
*mc
)
4644 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4646 spapr_machine_4_0_class_options(mc
);
4647 compat_props_add(mc
->compat_props
, hw_compat_3_1
, hw_compat_3_1_len
);
4649 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power8_v2.0");
4650 smc
->update_dt_enabled
= false;
4651 smc
->dr_phb_enabled
= false;
4652 smc
->broken_host_serial_model
= true;
4653 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_BROKEN
;
4654 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_BROKEN
;
4655 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_BROKEN
;
4656 smc
->default_caps
.caps
[SPAPR_CAP_LARGE_DECREMENTER
] = SPAPR_CAP_OFF
;
4659 DEFINE_SPAPR_MACHINE(3_1
, "3.1", false);
4665 static void spapr_machine_3_0_class_options(MachineClass
*mc
)
4667 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4669 spapr_machine_3_1_class_options(mc
);
4670 compat_props_add(mc
->compat_props
, hw_compat_3_0
, hw_compat_3_0_len
);
4672 smc
->legacy_irq_allocation
= true;
4673 smc
->nr_xirqs
= 0x400;
4674 smc
->irq
= &spapr_irq_xics_legacy
;
4677 DEFINE_SPAPR_MACHINE(3_0
, "3.0", false);
4682 static void spapr_machine_2_12_class_options(MachineClass
*mc
)
4684 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4685 static GlobalProperty compat
[] = {
4686 { TYPE_POWERPC_CPU
, "pre-3.0-migration", "on" },
4687 { TYPE_SPAPR_CPU_CORE
, "pre-3.0-migration", "on" },
4690 spapr_machine_3_0_class_options(mc
);
4691 compat_props_add(mc
->compat_props
, hw_compat_2_12
, hw_compat_2_12_len
);
4692 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4694 /* We depend on kvm_enabled() to choose a default value for the
4695 * hpt-max-page-size capability. Of course we can't do it here
4696 * because this is too early and the HW accelerator isn't initialzed
4697 * yet. Postpone this to machine init (see default_caps_with_cpu()).
4699 smc
->default_caps
.caps
[SPAPR_CAP_HPT_MAXPAGESIZE
] = 0;
4702 DEFINE_SPAPR_MACHINE(2_12
, "2.12", false);
4704 static void spapr_machine_2_12_sxxm_class_options(MachineClass
*mc
)
4706 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4708 spapr_machine_2_12_class_options(mc
);
4709 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_WORKAROUND
;
4710 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_WORKAROUND
;
4711 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_FIXED_CCD
;
4714 DEFINE_SPAPR_MACHINE(2_12_sxxm
, "2.12-sxxm", false);
4720 static void spapr_machine_2_11_class_options(MachineClass
*mc
)
4722 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4724 spapr_machine_2_12_class_options(mc
);
4725 smc
->default_caps
.caps
[SPAPR_CAP_HTM
] = SPAPR_CAP_ON
;
4726 compat_props_add(mc
->compat_props
, hw_compat_2_11
, hw_compat_2_11_len
);
4729 DEFINE_SPAPR_MACHINE(2_11
, "2.11", false);
4735 static void spapr_machine_2_10_class_options(MachineClass
*mc
)
4737 spapr_machine_2_11_class_options(mc
);
4738 compat_props_add(mc
->compat_props
, hw_compat_2_10
, hw_compat_2_10_len
);
4741 DEFINE_SPAPR_MACHINE(2_10
, "2.10", false);
4747 static void spapr_machine_2_9_class_options(MachineClass
*mc
)
4749 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4750 static GlobalProperty compat
[] = {
4751 { TYPE_POWERPC_CPU
, "pre-2.10-migration", "on" },
4754 spapr_machine_2_10_class_options(mc
);
4755 compat_props_add(mc
->compat_props
, hw_compat_2_9
, hw_compat_2_9_len
);
4756 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4757 mc
->numa_auto_assign_ram
= numa_legacy_auto_assign_ram
;
4758 smc
->pre_2_10_has_unused_icps
= true;
4759 smc
->resize_hpt_default
= SPAPR_RESIZE_HPT_DISABLED
;
4762 DEFINE_SPAPR_MACHINE(2_9
, "2.9", false);
4768 static void spapr_machine_2_8_class_options(MachineClass
*mc
)
4770 static GlobalProperty compat
[] = {
4771 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pcie-extended-configuration-space", "off" },
4774 spapr_machine_2_9_class_options(mc
);
4775 compat_props_add(mc
->compat_props
, hw_compat_2_8
, hw_compat_2_8_len
);
4776 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4777 mc
->numa_mem_align_shift
= 23;
4780 DEFINE_SPAPR_MACHINE(2_8
, "2.8", false);
4786 static void phb_placement_2_7(SpaprMachineState
*spapr
, uint32_t index
,
4787 uint64_t *buid
, hwaddr
*pio
,
4788 hwaddr
*mmio32
, hwaddr
*mmio64
,
4789 unsigned n_dma
, uint32_t *liobns
,
4790 hwaddr
*nv2gpa
, hwaddr
*nv2atsd
, Error
**errp
)
4792 /* Legacy PHB placement for pseries-2.7 and earlier machine types */
4793 const uint64_t base_buid
= 0x800000020000000ULL
;
4794 const hwaddr phb_spacing
= 0x1000000000ULL
; /* 64 GiB */
4795 const hwaddr mmio_offset
= 0xa0000000; /* 2 GiB + 512 MiB */
4796 const hwaddr pio_offset
= 0x80000000; /* 2 GiB */
4797 const uint32_t max_index
= 255;
4798 const hwaddr phb0_alignment
= 0x10000000000ULL
; /* 1 TiB */
4800 uint64_t ram_top
= MACHINE(spapr
)->ram_size
;
4801 hwaddr phb0_base
, phb_base
;
4804 /* Do we have device memory? */
4805 if (MACHINE(spapr
)->maxram_size
> ram_top
) {
4806 /* Can't just use maxram_size, because there may be an
4807 * alignment gap between normal and device memory regions
4809 ram_top
= MACHINE(spapr
)->device_memory
->base
+
4810 memory_region_size(&MACHINE(spapr
)->device_memory
->mr
);
4813 phb0_base
= QEMU_ALIGN_UP(ram_top
, phb0_alignment
);
4815 if (index
> max_index
) {
4816 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %u)",
4821 *buid
= base_buid
+ index
;
4822 for (i
= 0; i
< n_dma
; ++i
) {
4823 liobns
[i
] = SPAPR_PCI_LIOBN(index
, i
);
4826 phb_base
= phb0_base
+ index
* phb_spacing
;
4827 *pio
= phb_base
+ pio_offset
;
4828 *mmio32
= phb_base
+ mmio_offset
;
4830 * We don't set the 64-bit MMIO window, relying on the PHB's
4831 * fallback behaviour of automatically splitting a large "32-bit"
4832 * window into contiguous 32-bit and 64-bit windows
4839 static void spapr_machine_2_7_class_options(MachineClass
*mc
)
4841 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4842 static GlobalProperty compat
[] = {
4843 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem_win_size", "0xf80000000", },
4844 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem64_win_size", "0", },
4845 { TYPE_POWERPC_CPU
, "pre-2.8-migration", "on", },
4846 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pre-2.8-migration", "on", },
4849 spapr_machine_2_8_class_options(mc
);
4850 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power7_v2.3");
4851 mc
->default_machine_opts
= "modern-hotplug-events=off";
4852 compat_props_add(mc
->compat_props
, hw_compat_2_7
, hw_compat_2_7_len
);
4853 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4854 smc
->phb_placement
= phb_placement_2_7
;
4857 DEFINE_SPAPR_MACHINE(2_7
, "2.7", false);
4863 static void spapr_machine_2_6_class_options(MachineClass
*mc
)
4865 static GlobalProperty compat
[] = {
4866 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "ddw", "off" },
4869 spapr_machine_2_7_class_options(mc
);
4870 mc
->has_hotpluggable_cpus
= false;
4871 compat_props_add(mc
->compat_props
, hw_compat_2_6
, hw_compat_2_6_len
);
4872 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4875 DEFINE_SPAPR_MACHINE(2_6
, "2.6", false);
4881 static void spapr_machine_2_5_class_options(MachineClass
*mc
)
4883 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4884 static GlobalProperty compat
[] = {
4885 { "spapr-vlan", "use-rx-buffer-pools", "off" },
4888 spapr_machine_2_6_class_options(mc
);
4889 smc
->use_ohci_by_default
= true;
4890 compat_props_add(mc
->compat_props
, hw_compat_2_5
, hw_compat_2_5_len
);
4891 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4894 DEFINE_SPAPR_MACHINE(2_5
, "2.5", false);
4900 static void spapr_machine_2_4_class_options(MachineClass
*mc
)
4902 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4904 spapr_machine_2_5_class_options(mc
);
4905 smc
->dr_lmb_enabled
= false;
4906 compat_props_add(mc
->compat_props
, hw_compat_2_4
, hw_compat_2_4_len
);
4909 DEFINE_SPAPR_MACHINE(2_4
, "2.4", false);
4915 static void spapr_machine_2_3_class_options(MachineClass
*mc
)
4917 static GlobalProperty compat
[] = {
4918 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" },
4920 spapr_machine_2_4_class_options(mc
);
4921 compat_props_add(mc
->compat_props
, hw_compat_2_3
, hw_compat_2_3_len
);
4922 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4924 DEFINE_SPAPR_MACHINE(2_3
, "2.3", false);
4930 static void spapr_machine_2_2_class_options(MachineClass
*mc
)
4932 static GlobalProperty compat
[] = {
4933 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem_win_size", "0x20000000" },
4936 spapr_machine_2_3_class_options(mc
);
4937 compat_props_add(mc
->compat_props
, hw_compat_2_2
, hw_compat_2_2_len
);
4938 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4939 mc
->default_machine_opts
= "modern-hotplug-events=off,suppress-vmdesc=on";
4941 DEFINE_SPAPR_MACHINE(2_2
, "2.2", false);
4947 static void spapr_machine_2_1_class_options(MachineClass
*mc
)
4949 spapr_machine_2_2_class_options(mc
);
4950 compat_props_add(mc
->compat_props
, hw_compat_2_1
, hw_compat_2_1_len
);
4952 DEFINE_SPAPR_MACHINE(2_1
, "2.1", false);
4954 static void spapr_machine_register_types(void)
4956 type_register_static(&spapr_machine_info
);
4959 type_init(spapr_machine_register_types
)