2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "qemu/osdep.h"
28 #include "qemu-common.h"
29 #include "qapi/error.h"
30 #include "qapi/visitor.h"
31 #include "sysemu/sysemu.h"
32 #include "sysemu/numa.h"
33 #include "sysemu/qtest.h"
36 #include "hw/fw-path-provider.h"
39 #include "sysemu/device_tree.h"
40 #include "sysemu/cpus.h"
41 #include "sysemu/hw_accel.h"
43 #include "migration/misc.h"
44 #include "migration/global_state.h"
45 #include "migration/register.h"
46 #include "mmu-hash64.h"
47 #include "mmu-book3s-v3.h"
48 #include "cpu-models.h"
51 #include "hw/boards.h"
52 #include "hw/ppc/ppc.h"
53 #include "hw/loader.h"
55 #include "hw/ppc/fdt.h"
56 #include "hw/ppc/spapr.h"
57 #include "hw/ppc/spapr_vio.h"
58 #include "hw/pci-host/spapr.h"
59 #include "hw/pci/msi.h"
61 #include "hw/pci/pci.h"
62 #include "hw/scsi/scsi.h"
63 #include "hw/virtio/virtio-scsi.h"
64 #include "hw/virtio/vhost-scsi-common.h"
66 #include "exec/address-spaces.h"
67 #include "exec/ram_addr.h"
69 #include "qemu/config-file.h"
70 #include "qemu/error-report.h"
73 #include "hw/intc/intc.h"
75 #include "qemu/cutils.h"
76 #include "hw/ppc/spapr_cpu_core.h"
77 #include "hw/mem/memory-device.h"
81 /* SLOF memory layout:
83 * SLOF raw image loaded at 0, copies its romfs right below the flat
84 * device-tree, then position SLOF itself 31M below that
86 * So we set FW_OVERHEAD to 40MB which should account for all of that
89 * We load our kernel at 4M, leaving space for SLOF initial image
91 #define FDT_MAX_SIZE 0x100000
92 #define RTAS_MAX_SIZE 0x10000
93 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
94 #define FW_MAX_SIZE 0x400000
95 #define FW_FILE_NAME "slof.bin"
96 #define FW_OVERHEAD 0x2800000
97 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
99 #define MIN_RMA_SLOF 128UL
101 #define PHANDLE_INTC 0x00001111
103 /* These two functions implement the VCPU id numbering: one to compute them
104 * all and one to identify thread 0 of a VCORE. Any change to the first one
105 * is likely to have an impact on the second one, so let's keep them close.
107 static int spapr_vcpu_id(SpaprMachineState
*spapr
, int cpu_index
)
109 MachineState
*ms
= MACHINE(spapr
);
110 unsigned int smp_threads
= ms
->smp
.threads
;
114 (cpu_index
/ smp_threads
) * spapr
->vsmt
+ cpu_index
% smp_threads
;
116 static bool spapr_is_thread0_in_vcore(SpaprMachineState
*spapr
,
120 return spapr_get_vcpu_id(cpu
) % spapr
->vsmt
== 0;
123 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque
)
125 /* Dummy entries correspond to unused ICPState objects in older QEMUs,
126 * and newer QEMUs don't even have them. In both cases, we don't want
127 * to send anything on the wire.
132 static const VMStateDescription pre_2_10_vmstate_dummy_icp
= {
133 .name
= "icp/server",
135 .minimum_version_id
= 1,
136 .needed
= pre_2_10_vmstate_dummy_icp_needed
,
137 .fields
= (VMStateField
[]) {
138 VMSTATE_UNUSED(4), /* uint32_t xirr */
139 VMSTATE_UNUSED(1), /* uint8_t pending_priority */
140 VMSTATE_UNUSED(1), /* uint8_t mfrr */
141 VMSTATE_END_OF_LIST()
145 static void pre_2_10_vmstate_register_dummy_icp(int i
)
147 vmstate_register(NULL
, i
, &pre_2_10_vmstate_dummy_icp
,
148 (void *)(uintptr_t) i
);
151 static void pre_2_10_vmstate_unregister_dummy_icp(int i
)
153 vmstate_unregister(NULL
, &pre_2_10_vmstate_dummy_icp
,
154 (void *)(uintptr_t) i
);
157 int spapr_max_server_number(SpaprMachineState
*spapr
)
159 MachineState
*ms
= MACHINE(spapr
);
162 return DIV_ROUND_UP(ms
->smp
.max_cpus
* spapr
->vsmt
, ms
->smp
.threads
);
165 static int spapr_fixup_cpu_smt_dt(void *fdt
, int offset
, PowerPCCPU
*cpu
,
169 uint32_t servers_prop
[smt_threads
];
170 uint32_t gservers_prop
[smt_threads
* 2];
171 int index
= spapr_get_vcpu_id(cpu
);
173 if (cpu
->compat_pvr
) {
174 ret
= fdt_setprop_cell(fdt
, offset
, "cpu-version", cpu
->compat_pvr
);
180 /* Build interrupt servers and gservers properties */
181 for (i
= 0; i
< smt_threads
; i
++) {
182 servers_prop
[i
] = cpu_to_be32(index
+ i
);
183 /* Hack, direct the group queues back to cpu 0 */
184 gservers_prop
[i
*2] = cpu_to_be32(index
+ i
);
185 gservers_prop
[i
*2 + 1] = 0;
187 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-server#s",
188 servers_prop
, sizeof(servers_prop
));
192 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-gserver#s",
193 gservers_prop
, sizeof(gservers_prop
));
198 static int spapr_fixup_cpu_numa_dt(void *fdt
, int offset
, PowerPCCPU
*cpu
)
200 int index
= spapr_get_vcpu_id(cpu
);
201 uint32_t associativity
[] = {cpu_to_be32(0x5),
205 cpu_to_be32(cpu
->node_id
),
208 /* Advertise NUMA via ibm,associativity */
209 return fdt_setprop(fdt
, offset
, "ibm,associativity", associativity
,
210 sizeof(associativity
));
213 /* Populate the "ibm,pa-features" property */
214 static void spapr_populate_pa_features(SpaprMachineState
*spapr
,
216 void *fdt
, int offset
,
219 uint8_t pa_features_206
[] = { 6, 0,
220 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
221 uint8_t pa_features_207
[] = { 24, 0,
222 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
223 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
224 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
225 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
226 uint8_t pa_features_300
[] = { 66, 0,
227 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
228 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
229 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
231 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
233 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
234 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
235 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
236 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
237 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
238 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
239 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
240 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
241 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
242 /* 42: PM, 44: PC RA, 46: SC vec'd */
243 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
244 /* 48: SIMD, 50: QP BFP, 52: String */
245 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
246 /* 54: DecFP, 56: DecI, 58: SHA */
247 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
248 /* 60: NM atomic, 62: RNG */
249 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
251 uint8_t *pa_features
= NULL
;
254 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_2_06
, 0, cpu
->compat_pvr
)) {
255 pa_features
= pa_features_206
;
256 pa_size
= sizeof(pa_features_206
);
258 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_2_07
, 0, cpu
->compat_pvr
)) {
259 pa_features
= pa_features_207
;
260 pa_size
= sizeof(pa_features_207
);
262 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_3_00
, 0, cpu
->compat_pvr
)) {
263 pa_features
= pa_features_300
;
264 pa_size
= sizeof(pa_features_300
);
270 if (ppc_hash64_has(cpu
, PPC_HASH64_CI_LARGEPAGE
)) {
272 * Note: we keep CI large pages off by default because a 64K capable
273 * guest provisioned with large pages might otherwise try to map a qemu
274 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
275 * even if that qemu runs on a 4k host.
276 * We dd this bit back here if we are confident this is not an issue
278 pa_features
[3] |= 0x20;
280 if ((spapr_get_cap(spapr
, SPAPR_CAP_HTM
) != 0) && pa_size
> 24) {
281 pa_features
[24] |= 0x80; /* Transactional memory support */
283 if (legacy_guest
&& pa_size
> 40) {
284 /* Workaround for broken kernels that attempt (guest) radix
285 * mode when they can't handle it, if they see the radix bit set
286 * in pa-features. So hide it from them. */
287 pa_features
[40 + 2] &= ~0x80; /* Radix MMU */
290 _FDT((fdt_setprop(fdt
, offset
, "ibm,pa-features", pa_features
, pa_size
)));
293 static int spapr_fixup_cpu_dt(void *fdt
, SpaprMachineState
*spapr
)
295 MachineState
*ms
= MACHINE(spapr
);
296 int ret
= 0, offset
, cpus_offset
;
299 uint32_t pft_size_prop
[] = {0, cpu_to_be32(spapr
->htab_shift
)};
302 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
303 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
304 int index
= spapr_get_vcpu_id(cpu
);
305 int compat_smt
= MIN(ms
->smp
.threads
, ppc_compat_max_vthreads(cpu
));
307 if (!spapr_is_thread0_in_vcore(spapr
, cpu
)) {
311 snprintf(cpu_model
, 32, "%s@%x", dc
->fw_name
, index
);
313 cpus_offset
= fdt_path_offset(fdt
, "/cpus");
314 if (cpus_offset
< 0) {
315 cpus_offset
= fdt_add_subnode(fdt
, 0, "cpus");
316 if (cpus_offset
< 0) {
320 offset
= fdt_subnode_offset(fdt
, cpus_offset
, cpu_model
);
322 offset
= fdt_add_subnode(fdt
, cpus_offset
, cpu_model
);
328 ret
= fdt_setprop(fdt
, offset
, "ibm,pft-size",
329 pft_size_prop
, sizeof(pft_size_prop
));
334 if (nb_numa_nodes
> 1) {
335 ret
= spapr_fixup_cpu_numa_dt(fdt
, offset
, cpu
);
341 ret
= spapr_fixup_cpu_smt_dt(fdt
, offset
, cpu
, compat_smt
);
346 spapr_populate_pa_features(spapr
, cpu
, fdt
, offset
,
347 spapr
->cas_legacy_guest_workaround
);
352 static hwaddr
spapr_node0_size(MachineState
*machine
)
356 for (i
= 0; i
< nb_numa_nodes
; ++i
) {
357 if (numa_info
[i
].node_mem
) {
358 return MIN(pow2floor(numa_info
[i
].node_mem
),
363 return machine
->ram_size
;
366 static void add_str(GString
*s
, const gchar
*s1
)
368 g_string_append_len(s
, s1
, strlen(s1
) + 1);
371 static int spapr_populate_memory_node(void *fdt
, int nodeid
, hwaddr start
,
374 uint32_t associativity
[] = {
375 cpu_to_be32(0x4), /* length */
376 cpu_to_be32(0x0), cpu_to_be32(0x0),
377 cpu_to_be32(0x0), cpu_to_be32(nodeid
)
380 uint64_t mem_reg_property
[2];
383 mem_reg_property
[0] = cpu_to_be64(start
);
384 mem_reg_property
[1] = cpu_to_be64(size
);
386 sprintf(mem_name
, "memory@" TARGET_FMT_lx
, start
);
387 off
= fdt_add_subnode(fdt
, 0, mem_name
);
389 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
390 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
391 sizeof(mem_reg_property
))));
392 _FDT((fdt_setprop(fdt
, off
, "ibm,associativity", associativity
,
393 sizeof(associativity
))));
397 static int spapr_populate_memory(SpaprMachineState
*spapr
, void *fdt
)
399 MachineState
*machine
= MACHINE(spapr
);
400 hwaddr mem_start
, node_size
;
401 int i
, nb_nodes
= nb_numa_nodes
;
402 NodeInfo
*nodes
= numa_info
;
405 /* No NUMA nodes, assume there is just one node with whole RAM */
406 if (!nb_numa_nodes
) {
408 ramnode
.node_mem
= machine
->ram_size
;
412 for (i
= 0, mem_start
= 0; i
< nb_nodes
; ++i
) {
413 if (!nodes
[i
].node_mem
) {
416 if (mem_start
>= machine
->ram_size
) {
419 node_size
= nodes
[i
].node_mem
;
420 if (node_size
> machine
->ram_size
- mem_start
) {
421 node_size
= machine
->ram_size
- mem_start
;
425 /* spapr_machine_init() checks for rma_size <= node0_size
427 spapr_populate_memory_node(fdt
, i
, 0, spapr
->rma_size
);
428 mem_start
+= spapr
->rma_size
;
429 node_size
-= spapr
->rma_size
;
431 for ( ; node_size
; ) {
432 hwaddr sizetmp
= pow2floor(node_size
);
434 /* mem_start != 0 here */
435 if (ctzl(mem_start
) < ctzl(sizetmp
)) {
436 sizetmp
= 1ULL << ctzl(mem_start
);
439 spapr_populate_memory_node(fdt
, i
, mem_start
, sizetmp
);
440 node_size
-= sizetmp
;
441 mem_start
+= sizetmp
;
448 static void spapr_populate_cpu_dt(CPUState
*cs
, void *fdt
, int offset
,
449 SpaprMachineState
*spapr
)
451 MachineState
*ms
= MACHINE(spapr
);
452 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
453 CPUPPCState
*env
= &cpu
->env
;
454 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
455 int index
= spapr_get_vcpu_id(cpu
);
456 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
457 0xffffffff, 0xffffffff};
458 uint32_t tbfreq
= kvm_enabled() ? kvmppc_get_tbfreq()
459 : SPAPR_TIMEBASE_FREQ
;
460 uint32_t cpufreq
= kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
461 uint32_t page_sizes_prop
[64];
462 size_t page_sizes_prop_size
;
463 unsigned int smp_threads
= ms
->smp
.threads
;
464 uint32_t vcpus_per_socket
= smp_threads
* ms
->smp
.cores
;
465 uint32_t pft_size_prop
[] = {0, cpu_to_be32(spapr
->htab_shift
)};
466 int compat_smt
= MIN(smp_threads
, ppc_compat_max_vthreads(cpu
));
469 uint32_t radix_AP_encodings
[PPC_PAGE_SIZES_MAX_SZ
];
472 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
, index
);
474 drc_index
= spapr_drc_index(drc
);
475 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,my-drc-index", drc_index
)));
478 _FDT((fdt_setprop_cell(fdt
, offset
, "reg", index
)));
479 _FDT((fdt_setprop_string(fdt
, offset
, "device_type", "cpu")));
481 _FDT((fdt_setprop_cell(fdt
, offset
, "cpu-version", env
->spr
[SPR_PVR
])));
482 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-block-size",
483 env
->dcache_line_size
)));
484 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-line-size",
485 env
->dcache_line_size
)));
486 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-block-size",
487 env
->icache_line_size
)));
488 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-line-size",
489 env
->icache_line_size
)));
491 if (pcc
->l1_dcache_size
) {
492 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-size",
493 pcc
->l1_dcache_size
)));
495 warn_report("Unknown L1 dcache size for cpu");
497 if (pcc
->l1_icache_size
) {
498 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-size",
499 pcc
->l1_icache_size
)));
501 warn_report("Unknown L1 icache size for cpu");
504 _FDT((fdt_setprop_cell(fdt
, offset
, "timebase-frequency", tbfreq
)));
505 _FDT((fdt_setprop_cell(fdt
, offset
, "clock-frequency", cpufreq
)));
506 _FDT((fdt_setprop_cell(fdt
, offset
, "slb-size", cpu
->hash64_opts
->slb_size
)));
507 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,slb-size", cpu
->hash64_opts
->slb_size
)));
508 _FDT((fdt_setprop_string(fdt
, offset
, "status", "okay")));
509 _FDT((fdt_setprop(fdt
, offset
, "64-bit", NULL
, 0)));
511 if (env
->spr_cb
[SPR_PURR
].oea_read
) {
512 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,purr", 1)));
514 if (env
->spr_cb
[SPR_SPURR
].oea_read
) {
515 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,spurr", 1)));
518 if (ppc_hash64_has(cpu
, PPC_HASH64_1TSEG
)) {
519 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-segment-sizes",
520 segs
, sizeof(segs
))));
523 /* Advertise VSX (vector extensions) if available
524 * 1 == VMX / Altivec available
527 * Only CPUs for which we create core types in spapr_cpu_core.c
528 * are possible, and all of those have VMX */
529 if (spapr_get_cap(spapr
, SPAPR_CAP_VSX
) != 0) {
530 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", 2)));
532 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", 1)));
535 /* Advertise DFP (Decimal Floating Point) if available
536 * 0 / no property == no DFP
537 * 1 == DFP available */
538 if (spapr_get_cap(spapr
, SPAPR_CAP_DFP
) != 0) {
539 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,dfp", 1)));
542 page_sizes_prop_size
= ppc_create_page_sizes_prop(cpu
, page_sizes_prop
,
543 sizeof(page_sizes_prop
));
544 if (page_sizes_prop_size
) {
545 _FDT((fdt_setprop(fdt
, offset
, "ibm,segment-page-sizes",
546 page_sizes_prop
, page_sizes_prop_size
)));
549 spapr_populate_pa_features(spapr
, cpu
, fdt
, offset
, false);
551 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,chip-id",
552 cs
->cpu_index
/ vcpus_per_socket
)));
554 _FDT((fdt_setprop(fdt
, offset
, "ibm,pft-size",
555 pft_size_prop
, sizeof(pft_size_prop
))));
557 if (nb_numa_nodes
> 1) {
558 _FDT(spapr_fixup_cpu_numa_dt(fdt
, offset
, cpu
));
561 _FDT(spapr_fixup_cpu_smt_dt(fdt
, offset
, cpu
, compat_smt
));
563 if (pcc
->radix_page_info
) {
564 for (i
= 0; i
< pcc
->radix_page_info
->count
; i
++) {
565 radix_AP_encodings
[i
] =
566 cpu_to_be32(pcc
->radix_page_info
->entries
[i
]);
568 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-radix-AP-encodings",
570 pcc
->radix_page_info
->count
*
571 sizeof(radix_AP_encodings
[0]))));
575 * We set this property to let the guest know that it can use the large
576 * decrementer and its width in bits.
578 if (spapr_get_cap(spapr
, SPAPR_CAP_LARGE_DECREMENTER
) != SPAPR_CAP_OFF
)
579 _FDT((fdt_setprop_u32(fdt
, offset
, "ibm,dec-bits",
580 pcc
->lrg_decr_bits
)));
583 static void spapr_populate_cpus_dt_node(void *fdt
, SpaprMachineState
*spapr
)
592 cpus_offset
= fdt_add_subnode(fdt
, 0, "cpus");
594 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#address-cells", 0x1)));
595 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#size-cells", 0x0)));
598 * We walk the CPUs in reverse order to ensure that CPU DT nodes
599 * created by fdt_add_subnode() end up in the right order in FDT
600 * for the guest kernel the enumerate the CPUs correctly.
602 * The CPU list cannot be traversed in reverse order, so we need
608 rev
= g_renew(CPUState
*, rev
, n_cpus
+ 1);
612 for (i
= n_cpus
- 1; i
>= 0; i
--) {
613 CPUState
*cs
= rev
[i
];
614 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
615 int index
= spapr_get_vcpu_id(cpu
);
616 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
619 if (!spapr_is_thread0_in_vcore(spapr
, cpu
)) {
623 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, index
);
624 offset
= fdt_add_subnode(fdt
, cpus_offset
, nodename
);
627 spapr_populate_cpu_dt(cs
, fdt
, offset
, spapr
);
633 static int spapr_rng_populate_dt(void *fdt
)
638 node
= qemu_fdt_add_subnode(fdt
, "/ibm,platform-facilities");
642 ret
= fdt_setprop_string(fdt
, node
, "device_type",
643 "ibm,platform-facilities");
644 ret
|= fdt_setprop_cell(fdt
, node
, "#address-cells", 0x1);
645 ret
|= fdt_setprop_cell(fdt
, node
, "#size-cells", 0x0);
647 node
= fdt_add_subnode(fdt
, node
, "ibm,random-v1");
651 ret
|= fdt_setprop_string(fdt
, node
, "compatible", "ibm,random");
656 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList
*list
, ram_addr_t addr
)
658 MemoryDeviceInfoList
*info
;
660 for (info
= list
; info
; info
= info
->next
) {
661 MemoryDeviceInfo
*value
= info
->value
;
663 if (value
&& value
->type
== MEMORY_DEVICE_INFO_KIND_DIMM
) {
664 PCDIMMDeviceInfo
*pcdimm_info
= value
->u
.dimm
.data
;
666 if (addr
>= pcdimm_info
->addr
&&
667 addr
< (pcdimm_info
->addr
+ pcdimm_info
->size
)) {
668 return pcdimm_info
->node
;
676 struct sPAPRDrconfCellV2
{
684 typedef struct DrconfCellQueue
{
685 struct sPAPRDrconfCellV2 cell
;
686 QSIMPLEQ_ENTRY(DrconfCellQueue
) entry
;
689 static DrconfCellQueue
*
690 spapr_get_drconf_cell(uint32_t seq_lmbs
, uint64_t base_addr
,
691 uint32_t drc_index
, uint32_t aa_index
,
694 DrconfCellQueue
*elem
;
696 elem
= g_malloc0(sizeof(*elem
));
697 elem
->cell
.seq_lmbs
= cpu_to_be32(seq_lmbs
);
698 elem
->cell
.base_addr
= cpu_to_be64(base_addr
);
699 elem
->cell
.drc_index
= cpu_to_be32(drc_index
);
700 elem
->cell
.aa_index
= cpu_to_be32(aa_index
);
701 elem
->cell
.flags
= cpu_to_be32(flags
);
706 /* ibm,dynamic-memory-v2 */
707 static int spapr_populate_drmem_v2(SpaprMachineState
*spapr
, void *fdt
,
708 int offset
, MemoryDeviceInfoList
*dimms
)
710 MachineState
*machine
= MACHINE(spapr
);
711 uint8_t *int_buf
, *cur_index
;
713 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
714 uint64_t addr
, cur_addr
, size
;
715 uint32_t nr_boot_lmbs
= (machine
->device_memory
->base
/ lmb_size
);
716 uint64_t mem_end
= machine
->device_memory
->base
+
717 memory_region_size(&machine
->device_memory
->mr
);
718 uint32_t node
, buf_len
, nr_entries
= 0;
720 DrconfCellQueue
*elem
, *next
;
721 MemoryDeviceInfoList
*info
;
722 QSIMPLEQ_HEAD(, DrconfCellQueue
) drconf_queue
723 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue
);
725 /* Entry to cover RAM and the gap area */
726 elem
= spapr_get_drconf_cell(nr_boot_lmbs
, 0, 0, -1,
727 SPAPR_LMB_FLAGS_RESERVED
|
728 SPAPR_LMB_FLAGS_DRC_INVALID
);
729 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
732 cur_addr
= machine
->device_memory
->base
;
733 for (info
= dimms
; info
; info
= info
->next
) {
734 PCDIMMDeviceInfo
*di
= info
->value
->u
.dimm
.data
;
740 /* Entry for hot-pluggable area */
741 if (cur_addr
< addr
) {
742 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, cur_addr
/ lmb_size
);
744 elem
= spapr_get_drconf_cell((addr
- cur_addr
) / lmb_size
,
745 cur_addr
, spapr_drc_index(drc
), -1, 0);
746 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
751 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, addr
/ lmb_size
);
753 elem
= spapr_get_drconf_cell(size
/ lmb_size
, addr
,
754 spapr_drc_index(drc
), node
,
755 SPAPR_LMB_FLAGS_ASSIGNED
);
756 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
758 cur_addr
= addr
+ size
;
761 /* Entry for remaining hotpluggable area */
762 if (cur_addr
< mem_end
) {
763 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, cur_addr
/ lmb_size
);
765 elem
= spapr_get_drconf_cell((mem_end
- cur_addr
) / lmb_size
,
766 cur_addr
, spapr_drc_index(drc
), -1, 0);
767 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
771 buf_len
= nr_entries
* sizeof(struct sPAPRDrconfCellV2
) + sizeof(uint32_t);
772 int_buf
= cur_index
= g_malloc0(buf_len
);
773 *(uint32_t *)int_buf
= cpu_to_be32(nr_entries
);
774 cur_index
+= sizeof(nr_entries
);
776 QSIMPLEQ_FOREACH_SAFE(elem
, &drconf_queue
, entry
, next
) {
777 memcpy(cur_index
, &elem
->cell
, sizeof(elem
->cell
));
778 cur_index
+= sizeof(elem
->cell
);
779 QSIMPLEQ_REMOVE(&drconf_queue
, elem
, DrconfCellQueue
, entry
);
783 ret
= fdt_setprop(fdt
, offset
, "ibm,dynamic-memory-v2", int_buf
, buf_len
);
791 /* ibm,dynamic-memory */
792 static int spapr_populate_drmem_v1(SpaprMachineState
*spapr
, void *fdt
,
793 int offset
, MemoryDeviceInfoList
*dimms
)
795 MachineState
*machine
= MACHINE(spapr
);
797 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
798 uint32_t device_lmb_start
= machine
->device_memory
->base
/ lmb_size
;
799 uint32_t nr_lmbs
= (machine
->device_memory
->base
+
800 memory_region_size(&machine
->device_memory
->mr
)) /
802 uint32_t *int_buf
, *cur_index
, buf_len
;
805 * Allocate enough buffer size to fit in ibm,dynamic-memory
807 buf_len
= (nr_lmbs
* SPAPR_DR_LMB_LIST_ENTRY_SIZE
+ 1) * sizeof(uint32_t);
808 cur_index
= int_buf
= g_malloc0(buf_len
);
809 int_buf
[0] = cpu_to_be32(nr_lmbs
);
811 for (i
= 0; i
< nr_lmbs
; i
++) {
812 uint64_t addr
= i
* lmb_size
;
813 uint32_t *dynamic_memory
= cur_index
;
815 if (i
>= device_lmb_start
) {
818 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, i
);
821 dynamic_memory
[0] = cpu_to_be32(addr
>> 32);
822 dynamic_memory
[1] = cpu_to_be32(addr
& 0xffffffff);
823 dynamic_memory
[2] = cpu_to_be32(spapr_drc_index(drc
));
824 dynamic_memory
[3] = cpu_to_be32(0); /* reserved */
825 dynamic_memory
[4] = cpu_to_be32(spapr_pc_dimm_node(dimms
, addr
));
826 if (memory_region_present(get_system_memory(), addr
)) {
827 dynamic_memory
[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED
);
829 dynamic_memory
[5] = cpu_to_be32(0);
833 * LMB information for RMA, boot time RAM and gap b/n RAM and
834 * device memory region -- all these are marked as reserved
835 * and as having no valid DRC.
837 dynamic_memory
[0] = cpu_to_be32(addr
>> 32);
838 dynamic_memory
[1] = cpu_to_be32(addr
& 0xffffffff);
839 dynamic_memory
[2] = cpu_to_be32(0);
840 dynamic_memory
[3] = cpu_to_be32(0); /* reserved */
841 dynamic_memory
[4] = cpu_to_be32(-1);
842 dynamic_memory
[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED
|
843 SPAPR_LMB_FLAGS_DRC_INVALID
);
846 cur_index
+= SPAPR_DR_LMB_LIST_ENTRY_SIZE
;
848 ret
= fdt_setprop(fdt
, offset
, "ibm,dynamic-memory", int_buf
, buf_len
);
857 * Adds ibm,dynamic-reconfiguration-memory node.
858 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
859 * of this device tree node.
861 static int spapr_populate_drconf_memory(SpaprMachineState
*spapr
, void *fdt
)
863 MachineState
*machine
= MACHINE(spapr
);
865 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
866 uint32_t prop_lmb_size
[] = {0, cpu_to_be32(lmb_size
)};
867 uint32_t *int_buf
, *cur_index
, buf_len
;
868 int nr_nodes
= nb_numa_nodes
? nb_numa_nodes
: 1;
869 MemoryDeviceInfoList
*dimms
= NULL
;
872 * Don't create the node if there is no device memory
874 if (machine
->ram_size
== machine
->maxram_size
) {
878 offset
= fdt_add_subnode(fdt
, 0, "ibm,dynamic-reconfiguration-memory");
880 ret
= fdt_setprop(fdt
, offset
, "ibm,lmb-size", prop_lmb_size
,
881 sizeof(prop_lmb_size
));
886 ret
= fdt_setprop_cell(fdt
, offset
, "ibm,memory-flags-mask", 0xff);
891 ret
= fdt_setprop_cell(fdt
, offset
, "ibm,memory-preservation-time", 0x0);
896 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */
897 dimms
= qmp_memory_device_list();
898 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_DRMEM_V2
)) {
899 ret
= spapr_populate_drmem_v2(spapr
, fdt
, offset
, dimms
);
901 ret
= spapr_populate_drmem_v1(spapr
, fdt
, offset
, dimms
);
903 qapi_free_MemoryDeviceInfoList(dimms
);
909 /* ibm,associativity-lookup-arrays */
910 buf_len
= (nr_nodes
* 4 + 2) * sizeof(uint32_t);
911 cur_index
= int_buf
= g_malloc0(buf_len
);
912 int_buf
[0] = cpu_to_be32(nr_nodes
);
913 int_buf
[1] = cpu_to_be32(4); /* Number of entries per associativity list */
915 for (i
= 0; i
< nr_nodes
; i
++) {
916 uint32_t associativity
[] = {
922 memcpy(cur_index
, associativity
, sizeof(associativity
));
925 ret
= fdt_setprop(fdt
, offset
, "ibm,associativity-lookup-arrays", int_buf
,
926 (cur_index
- int_buf
) * sizeof(uint32_t));
932 static int spapr_dt_cas_updates(SpaprMachineState
*spapr
, void *fdt
,
933 SpaprOptionVector
*ov5_updates
)
935 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
938 /* Generate ibm,dynamic-reconfiguration-memory node if required */
939 if (spapr_ovec_test(ov5_updates
, OV5_DRCONF_MEMORY
)) {
940 g_assert(smc
->dr_lmb_enabled
);
941 ret
= spapr_populate_drconf_memory(spapr
, fdt
);
947 offset
= fdt_path_offset(fdt
, "/chosen");
949 offset
= fdt_add_subnode(fdt
, 0, "chosen");
954 ret
= spapr_ovec_populate_dt(fdt
, offset
, spapr
->ov5_cas
,
955 "ibm,architecture-vec-5");
961 static bool spapr_hotplugged_dev_before_cas(void)
963 Object
*drc_container
, *obj
;
964 ObjectProperty
*prop
;
965 ObjectPropertyIterator iter
;
967 drc_container
= container_get(object_get_root(), "/dr-connector");
968 object_property_iter_init(&iter
, drc_container
);
969 while ((prop
= object_property_iter_next(&iter
))) {
970 if (!strstart(prop
->type
, "link<", NULL
)) {
973 obj
= object_property_get_link(drc_container
, prop
->name
, NULL
);
974 if (spapr_drc_needed(obj
)) {
981 int spapr_h_cas_compose_response(SpaprMachineState
*spapr
,
982 target_ulong addr
, target_ulong size
,
983 SpaprOptionVector
*ov5_updates
)
985 void *fdt
, *fdt_skel
;
986 SpaprDeviceTreeUpdateHeader hdr
= { .version_id
= 1 };
988 if (spapr_hotplugged_dev_before_cas()) {
992 if (size
< sizeof(hdr
) || size
> FW_MAX_SIZE
) {
993 error_report("SLOF provided an unexpected CAS buffer size "
994 TARGET_FMT_lu
" (min: %zu, max: %u)",
995 size
, sizeof(hdr
), FW_MAX_SIZE
);
1001 /* Create skeleton */
1002 fdt_skel
= g_malloc0(size
);
1003 _FDT((fdt_create(fdt_skel
, size
)));
1004 _FDT((fdt_finish_reservemap(fdt_skel
)));
1005 _FDT((fdt_begin_node(fdt_skel
, "")));
1006 _FDT((fdt_end_node(fdt_skel
)));
1007 _FDT((fdt_finish(fdt_skel
)));
1008 fdt
= g_malloc0(size
);
1009 _FDT((fdt_open_into(fdt_skel
, fdt
, size
)));
1012 /* Fixup cpu nodes */
1013 _FDT((spapr_fixup_cpu_dt(fdt
, spapr
)));
1015 if (spapr_dt_cas_updates(spapr
, fdt
, ov5_updates
)) {
1019 /* Pack resulting tree */
1020 _FDT((fdt_pack(fdt
)));
1022 if (fdt_totalsize(fdt
) + sizeof(hdr
) > size
) {
1023 trace_spapr_cas_failed(size
);
1027 cpu_physical_memory_write(addr
, &hdr
, sizeof(hdr
));
1028 cpu_physical_memory_write(addr
+ sizeof(hdr
), fdt
, fdt_totalsize(fdt
));
1029 trace_spapr_cas_continue(fdt_totalsize(fdt
) + sizeof(hdr
));
1035 static void spapr_dt_rtas(SpaprMachineState
*spapr
, void *fdt
)
1037 MachineState
*ms
= MACHINE(spapr
);
1039 GString
*hypertas
= g_string_sized_new(256);
1040 GString
*qemu_hypertas
= g_string_sized_new(256);
1041 uint32_t refpoints
[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
1042 uint64_t max_device_addr
= MACHINE(spapr
)->device_memory
->base
+
1043 memory_region_size(&MACHINE(spapr
)->device_memory
->mr
);
1044 uint32_t lrdr_capacity
[] = {
1045 cpu_to_be32(max_device_addr
>> 32),
1046 cpu_to_be32(max_device_addr
& 0xffffffff),
1047 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE
),
1048 cpu_to_be32(ms
->smp
.max_cpus
/ ms
->smp
.threads
),
1050 uint32_t maxdomain
= cpu_to_be32(spapr
->gpu_numa_id
> 1 ? 1 : 0);
1051 uint32_t maxdomains
[] = {
1056 cpu_to_be32(spapr
->gpu_numa_id
),
1059 _FDT(rtas
= fdt_add_subnode(fdt
, 0, "rtas"));
1062 add_str(hypertas
, "hcall-pft");
1063 add_str(hypertas
, "hcall-term");
1064 add_str(hypertas
, "hcall-dabr");
1065 add_str(hypertas
, "hcall-interrupt");
1066 add_str(hypertas
, "hcall-tce");
1067 add_str(hypertas
, "hcall-vio");
1068 add_str(hypertas
, "hcall-splpar");
1069 add_str(hypertas
, "hcall-bulk");
1070 add_str(hypertas
, "hcall-set-mode");
1071 add_str(hypertas
, "hcall-sprg0");
1072 add_str(hypertas
, "hcall-copy");
1073 add_str(hypertas
, "hcall-debug");
1074 add_str(hypertas
, "hcall-vphn");
1075 add_str(qemu_hypertas
, "hcall-memop1");
1077 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
1078 add_str(hypertas
, "hcall-multi-tce");
1081 if (spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) {
1082 add_str(hypertas
, "hcall-hpt-resize");
1085 _FDT(fdt_setprop(fdt
, rtas
, "ibm,hypertas-functions",
1086 hypertas
->str
, hypertas
->len
));
1087 g_string_free(hypertas
, TRUE
);
1088 _FDT(fdt_setprop(fdt
, rtas
, "qemu,hypertas-functions",
1089 qemu_hypertas
->str
, qemu_hypertas
->len
));
1090 g_string_free(qemu_hypertas
, TRUE
);
1092 _FDT(fdt_setprop(fdt
, rtas
, "ibm,associativity-reference-points",
1093 refpoints
, sizeof(refpoints
)));
1095 _FDT(fdt_setprop(fdt
, rtas
, "ibm,max-associativity-domains",
1096 maxdomains
, sizeof(maxdomains
)));
1098 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-error-log-max",
1099 RTAS_ERROR_LOG_MAX
));
1100 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-event-scan-rate",
1101 RTAS_EVENT_SCAN_RATE
));
1103 g_assert(msi_nonbroken
);
1104 _FDT(fdt_setprop(fdt
, rtas
, "ibm,change-msix-capable", NULL
, 0));
1107 * According to PAPR, rtas ibm,os-term does not guarantee a return
1108 * back to the guest cpu.
1110 * While an additional ibm,extended-os-term property indicates
1111 * that rtas call return will always occur. Set this property.
1113 _FDT(fdt_setprop(fdt
, rtas
, "ibm,extended-os-term", NULL
, 0));
1115 _FDT(fdt_setprop(fdt
, rtas
, "ibm,lrdr-capacity",
1116 lrdr_capacity
, sizeof(lrdr_capacity
)));
1118 spapr_dt_rtas_tokens(fdt
, rtas
);
1122 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU
1123 * and the XIVE features that the guest may request and thus the valid
1124 * values for bytes 23..26 of option vector 5:
1126 static void spapr_dt_ov5_platform_support(SpaprMachineState
*spapr
, void *fdt
,
1129 PowerPCCPU
*first_ppc_cpu
= POWERPC_CPU(first_cpu
);
1132 23, spapr
->irq
->ov5
, /* Xive mode. */
1133 24, 0x00, /* Hash/Radix, filled in below. */
1134 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
1135 26, 0x40, /* Radix options: GTSE == yes. */
1138 if (!ppc_check_compat(first_ppc_cpu
, CPU_POWERPC_LOGICAL_3_00
, 0,
1139 first_ppc_cpu
->compat_pvr
)) {
1141 * If we're in a pre POWER9 compat mode then the guest should
1142 * do hash and use the legacy interrupt mode
1144 val
[1] = 0x00; /* XICS */
1145 val
[3] = 0x00; /* Hash */
1146 } else if (kvm_enabled()) {
1147 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
1148 val
[3] = 0x80; /* OV5_MMU_BOTH */
1149 } else if (kvmppc_has_cap_mmu_radix()) {
1150 val
[3] = 0x40; /* OV5_MMU_RADIX_300 */
1152 val
[3] = 0x00; /* Hash */
1155 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */
1158 _FDT(fdt_setprop(fdt
, chosen
, "ibm,arch-vec-5-platform-support",
1162 static void spapr_dt_chosen(SpaprMachineState
*spapr
, void *fdt
)
1164 MachineState
*machine
= MACHINE(spapr
);
1166 const char *boot_device
= machine
->boot_order
;
1167 char *stdout_path
= spapr_vio_stdout_path(spapr
->vio_bus
);
1169 char *bootlist
= get_boot_devices_list(&cb
);
1171 _FDT(chosen
= fdt_add_subnode(fdt
, 0, "chosen"));
1173 _FDT(fdt_setprop_string(fdt
, chosen
, "bootargs", machine
->kernel_cmdline
));
1174 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,initrd-start",
1175 spapr
->initrd_base
));
1176 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,initrd-end",
1177 spapr
->initrd_base
+ spapr
->initrd_size
));
1179 if (spapr
->kernel_size
) {
1180 uint64_t kprop
[2] = { cpu_to_be64(KERNEL_LOAD_ADDR
),
1181 cpu_to_be64(spapr
->kernel_size
) };
1183 _FDT(fdt_setprop(fdt
, chosen
, "qemu,boot-kernel",
1184 &kprop
, sizeof(kprop
)));
1185 if (spapr
->kernel_le
) {
1186 _FDT(fdt_setprop(fdt
, chosen
, "qemu,boot-kernel-le", NULL
, 0));
1190 _FDT((fdt_setprop_cell(fdt
, chosen
, "qemu,boot-menu", boot_menu
)));
1192 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-width", graphic_width
));
1193 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-height", graphic_height
));
1194 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-depth", graphic_depth
));
1196 if (cb
&& bootlist
) {
1199 for (i
= 0; i
< cb
; i
++) {
1200 if (bootlist
[i
] == '\n') {
1204 _FDT(fdt_setprop_string(fdt
, chosen
, "qemu,boot-list", bootlist
));
1207 if (boot_device
&& strlen(boot_device
)) {
1208 _FDT(fdt_setprop_string(fdt
, chosen
, "qemu,boot-device", boot_device
));
1211 if (!spapr
->has_graphics
&& stdout_path
) {
1213 * "linux,stdout-path" and "stdout" properties are deprecated by linux
1214 * kernel. New platforms should only use the "stdout-path" property. Set
1215 * the new property and continue using older property to remain
1216 * compatible with the existing firmware.
1218 _FDT(fdt_setprop_string(fdt
, chosen
, "linux,stdout-path", stdout_path
));
1219 _FDT(fdt_setprop_string(fdt
, chosen
, "stdout-path", stdout_path
));
1222 spapr_dt_ov5_platform_support(spapr
, fdt
, chosen
);
1224 g_free(stdout_path
);
1228 static void spapr_dt_hypervisor(SpaprMachineState
*spapr
, void *fdt
)
1230 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
1231 * KVM to work under pHyp with some guest co-operation */
1233 uint8_t hypercall
[16];
1235 _FDT(hypervisor
= fdt_add_subnode(fdt
, 0, "hypervisor"));
1236 /* indicate KVM hypercall interface */
1237 _FDT(fdt_setprop_string(fdt
, hypervisor
, "compatible", "linux,kvm"));
1238 if (kvmppc_has_cap_fixup_hcalls()) {
1240 * Older KVM versions with older guest kernels were broken
1241 * with the magic page, don't allow the guest to map it.
1243 if (!kvmppc_get_hypercall(first_cpu
->env_ptr
, hypercall
,
1244 sizeof(hypercall
))) {
1245 _FDT(fdt_setprop(fdt
, hypervisor
, "hcall-instructions",
1246 hypercall
, sizeof(hypercall
)));
1251 static void *spapr_build_fdt(SpaprMachineState
*spapr
)
1253 MachineState
*machine
= MACHINE(spapr
);
1254 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1255 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
1261 fdt
= g_malloc0(FDT_MAX_SIZE
);
1262 _FDT((fdt_create_empty_tree(fdt
, FDT_MAX_SIZE
)));
1265 _FDT(fdt_setprop_string(fdt
, 0, "device_type", "chrp"));
1266 _FDT(fdt_setprop_string(fdt
, 0, "model", "IBM pSeries (emulated by qemu)"));
1267 _FDT(fdt_setprop_string(fdt
, 0, "compatible", "qemu,pseries"));
1269 /* Guest UUID & Name*/
1270 buf
= qemu_uuid_unparse_strdup(&qemu_uuid
);
1271 _FDT(fdt_setprop_string(fdt
, 0, "vm,uuid", buf
));
1272 if (qemu_uuid_set
) {
1273 _FDT(fdt_setprop_string(fdt
, 0, "system-id", buf
));
1277 if (qemu_get_vm_name()) {
1278 _FDT(fdt_setprop_string(fdt
, 0, "ibm,partition-name",
1279 qemu_get_vm_name()));
1282 /* Host Model & Serial Number */
1283 if (spapr
->host_model
) {
1284 _FDT(fdt_setprop_string(fdt
, 0, "host-model", spapr
->host_model
));
1285 } else if (smc
->broken_host_serial_model
&& kvmppc_get_host_model(&buf
)) {
1286 _FDT(fdt_setprop_string(fdt
, 0, "host-model", buf
));
1290 if (spapr
->host_serial
) {
1291 _FDT(fdt_setprop_string(fdt
, 0, "host-serial", spapr
->host_serial
));
1292 } else if (smc
->broken_host_serial_model
&& kvmppc_get_host_serial(&buf
)) {
1293 _FDT(fdt_setprop_string(fdt
, 0, "host-serial", buf
));
1297 _FDT(fdt_setprop_cell(fdt
, 0, "#address-cells", 2));
1298 _FDT(fdt_setprop_cell(fdt
, 0, "#size-cells", 2));
1300 /* /interrupt controller */
1301 spapr
->irq
->dt_populate(spapr
, spapr_max_server_number(spapr
), fdt
,
1304 ret
= spapr_populate_memory(spapr
, fdt
);
1306 error_report("couldn't setup memory nodes in fdt");
1311 spapr_dt_vdevice(spapr
->vio_bus
, fdt
);
1313 if (object_resolve_path_type("", TYPE_SPAPR_RNG
, NULL
)) {
1314 ret
= spapr_rng_populate_dt(fdt
);
1316 error_report("could not set up rng device in the fdt");
1321 QLIST_FOREACH(phb
, &spapr
->phbs
, list
) {
1322 ret
= spapr_dt_phb(phb
, PHANDLE_INTC
, fdt
, spapr
->irq
->nr_msis
, NULL
);
1324 error_report("couldn't setup PCI devices in fdt");
1330 spapr_populate_cpus_dt_node(fdt
, spapr
);
1332 if (smc
->dr_lmb_enabled
) {
1333 _FDT(spapr_dt_drc(fdt
, 0, NULL
, SPAPR_DR_CONNECTOR_TYPE_LMB
));
1336 if (mc
->has_hotpluggable_cpus
) {
1337 int offset
= fdt_path_offset(fdt
, "/cpus");
1338 ret
= spapr_dt_drc(fdt
, offset
, NULL
, SPAPR_DR_CONNECTOR_TYPE_CPU
);
1340 error_report("Couldn't set up CPU DR device tree properties");
1345 /* /event-sources */
1346 spapr_dt_events(spapr
, fdt
);
1349 spapr_dt_rtas(spapr
, fdt
);
1352 spapr_dt_chosen(spapr
, fdt
);
1355 if (kvm_enabled()) {
1356 spapr_dt_hypervisor(spapr
, fdt
);
1359 /* Build memory reserve map */
1360 if (spapr
->kernel_size
) {
1361 _FDT((fdt_add_mem_rsv(fdt
, KERNEL_LOAD_ADDR
, spapr
->kernel_size
)));
1363 if (spapr
->initrd_size
) {
1364 _FDT((fdt_add_mem_rsv(fdt
, spapr
->initrd_base
, spapr
->initrd_size
)));
1367 /* ibm,client-architecture-support updates */
1368 ret
= spapr_dt_cas_updates(spapr
, fdt
, spapr
->ov5_cas
);
1370 error_report("couldn't setup CAS properties fdt");
1374 if (smc
->dr_phb_enabled
) {
1375 ret
= spapr_dt_drc(fdt
, 0, NULL
, SPAPR_DR_CONNECTOR_TYPE_PHB
);
1377 error_report("Couldn't set up PHB DR device tree properties");
1385 static uint64_t translate_kernel_address(void *opaque
, uint64_t addr
)
1387 return (addr
& 0x0fffffff) + KERNEL_LOAD_ADDR
;
1390 static void emulate_spapr_hypercall(PPCVirtualHypervisor
*vhyp
,
1393 CPUPPCState
*env
= &cpu
->env
;
1395 /* The TCG path should also be holding the BQL at this point */
1396 g_assert(qemu_mutex_iothread_locked());
1399 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1400 env
->gpr
[3] = H_PRIVILEGE
;
1402 env
->gpr
[3] = spapr_hypercall(cpu
, env
->gpr
[3], &env
->gpr
[4]);
1406 struct LPCRSyncState
{
1411 static void do_lpcr_sync(CPUState
*cs
, run_on_cpu_data arg
)
1413 struct LPCRSyncState
*s
= arg
.host_ptr
;
1414 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1415 CPUPPCState
*env
= &cpu
->env
;
1418 cpu_synchronize_state(cs
);
1419 lpcr
= env
->spr
[SPR_LPCR
];
1422 ppc_store_lpcr(cpu
, lpcr
);
1425 void spapr_set_all_lpcrs(target_ulong value
, target_ulong mask
)
1428 struct LPCRSyncState s
= {
1433 run_on_cpu(cs
, do_lpcr_sync
, RUN_ON_CPU_HOST_PTR(&s
));
1437 static void spapr_get_pate(PPCVirtualHypervisor
*vhyp
, ppc_v3_pate_t
*entry
)
1439 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1441 /* Copy PATE1:GR into PATE0:HR */
1442 entry
->dw0
= spapr
->patb_entry
& PATE0_HR
;
1443 entry
->dw1
= spapr
->patb_entry
;
1446 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1447 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1448 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1449 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1450 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1453 * Get the fd to access the kernel htab, re-opening it if necessary
1455 static int get_htab_fd(SpaprMachineState
*spapr
)
1457 Error
*local_err
= NULL
;
1459 if (spapr
->htab_fd
>= 0) {
1460 return spapr
->htab_fd
;
1463 spapr
->htab_fd
= kvmppc_get_htab_fd(false, 0, &local_err
);
1464 if (spapr
->htab_fd
< 0) {
1465 error_report_err(local_err
);
1468 return spapr
->htab_fd
;
1471 void close_htab_fd(SpaprMachineState
*spapr
)
1473 if (spapr
->htab_fd
>= 0) {
1474 close(spapr
->htab_fd
);
1476 spapr
->htab_fd
= -1;
1479 static hwaddr
spapr_hpt_mask(PPCVirtualHypervisor
*vhyp
)
1481 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1483 return HTAB_SIZE(spapr
) / HASH_PTEG_SIZE_64
- 1;
1486 static target_ulong
spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor
*vhyp
)
1488 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1490 assert(kvm_enabled());
1496 return (target_ulong
)(uintptr_t)spapr
->htab
| (spapr
->htab_shift
- 18);
1499 static const ppc_hash_pte64_t
*spapr_map_hptes(PPCVirtualHypervisor
*vhyp
,
1502 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1503 hwaddr pte_offset
= ptex
* HASH_PTE_SIZE_64
;
1507 * HTAB is controlled by KVM. Fetch into temporary buffer
1509 ppc_hash_pte64_t
*hptes
= g_malloc(n
* HASH_PTE_SIZE_64
);
1510 kvmppc_read_hptes(hptes
, ptex
, n
);
1515 * HTAB is controlled by QEMU. Just point to the internally
1518 return (const ppc_hash_pte64_t
*)(spapr
->htab
+ pte_offset
);
1521 static void spapr_unmap_hptes(PPCVirtualHypervisor
*vhyp
,
1522 const ppc_hash_pte64_t
*hptes
,
1525 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1528 g_free((void *)hptes
);
1531 /* Nothing to do for qemu managed HPT */
1534 void spapr_store_hpte(PowerPCCPU
*cpu
, hwaddr ptex
,
1535 uint64_t pte0
, uint64_t pte1
)
1537 SpaprMachineState
*spapr
= SPAPR_MACHINE(cpu
->vhyp
);
1538 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
;
1541 kvmppc_write_hpte(ptex
, pte0
, pte1
);
1543 if (pte0
& HPTE64_V_VALID
) {
1544 stq_p(spapr
->htab
+ offset
+ HASH_PTE_SIZE_64
/ 2, pte1
);
1546 * When setting valid, we write PTE1 first. This ensures
1547 * proper synchronization with the reading code in
1548 * ppc_hash64_pteg_search()
1551 stq_p(spapr
->htab
+ offset
, pte0
);
1553 stq_p(spapr
->htab
+ offset
, pte0
);
1555 * When clearing it we set PTE0 first. This ensures proper
1556 * synchronization with the reading code in
1557 * ppc_hash64_pteg_search()
1560 stq_p(spapr
->htab
+ offset
+ HASH_PTE_SIZE_64
/ 2, pte1
);
1565 static void spapr_hpte_set_c(PPCVirtualHypervisor
*vhyp
, hwaddr ptex
,
1568 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
+ 15;
1569 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1572 /* There should always be a hash table when this is called */
1573 error_report("spapr_hpte_set_c called with no hash table !");
1577 /* The HW performs a non-atomic byte update */
1578 stb_p(spapr
->htab
+ offset
, (pte1
& 0xff) | 0x80);
1581 static void spapr_hpte_set_r(PPCVirtualHypervisor
*vhyp
, hwaddr ptex
,
1584 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
+ 14;
1585 SpaprMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1588 /* There should always be a hash table when this is called */
1589 error_report("spapr_hpte_set_r called with no hash table !");
1593 /* The HW performs a non-atomic byte update */
1594 stb_p(spapr
->htab
+ offset
, ((pte1
>> 8) & 0xff) | 0x01);
1597 int spapr_hpt_shift_for_ramsize(uint64_t ramsize
)
1601 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1602 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1603 * that's much more than is needed for Linux guests */
1604 shift
= ctz64(pow2ceil(ramsize
)) - 7;
1605 shift
= MAX(shift
, 18); /* Minimum architected size */
1606 shift
= MIN(shift
, 46); /* Maximum architected size */
1610 void spapr_free_hpt(SpaprMachineState
*spapr
)
1612 g_free(spapr
->htab
);
1614 spapr
->htab_shift
= 0;
1615 close_htab_fd(spapr
);
1618 void spapr_reallocate_hpt(SpaprMachineState
*spapr
, int shift
,
1623 /* Clean up any HPT info from a previous boot */
1624 spapr_free_hpt(spapr
);
1626 rc
= kvmppc_reset_htab(shift
);
1628 /* kernel-side HPT needed, but couldn't allocate one */
1629 error_setg_errno(errp
, errno
,
1630 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1632 /* This is almost certainly fatal, but if the caller really
1633 * wants to carry on with shift == 0, it's welcome to try */
1634 } else if (rc
> 0) {
1635 /* kernel-side HPT allocated */
1638 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1642 spapr
->htab_shift
= shift
;
1645 /* kernel-side HPT not needed, allocate in userspace instead */
1646 size_t size
= 1ULL << shift
;
1649 spapr
->htab
= qemu_memalign(size
, size
);
1651 error_setg_errno(errp
, errno
,
1652 "Could not allocate HPT of order %d", shift
);
1656 memset(spapr
->htab
, 0, size
);
1657 spapr
->htab_shift
= shift
;
1659 for (i
= 0; i
< size
/ HASH_PTE_SIZE_64
; i
++) {
1660 DIRTY_HPTE(HPTE(spapr
->htab
, i
));
1663 /* We're setting up a hash table, so that means we're not radix */
1664 spapr
->patb_entry
= 0;
1665 spapr_set_all_lpcrs(0, LPCR_HR
| LPCR_UPRT
);
1668 void spapr_setup_hpt_and_vrma(SpaprMachineState
*spapr
)
1672 if ((spapr
->resize_hpt
== SPAPR_RESIZE_HPT_DISABLED
)
1673 || (spapr
->cas_reboot
1674 && !spapr_ovec_test(spapr
->ov5_cas
, OV5_HPT_RESIZE
))) {
1675 hpt_shift
= spapr_hpt_shift_for_ramsize(MACHINE(spapr
)->maxram_size
);
1677 uint64_t current_ram_size
;
1679 current_ram_size
= MACHINE(spapr
)->ram_size
+ get_plugged_memory_size();
1680 hpt_shift
= spapr_hpt_shift_for_ramsize(current_ram_size
);
1682 spapr_reallocate_hpt(spapr
, hpt_shift
, &error_fatal
);
1684 if (spapr
->vrma_adjust
) {
1685 spapr
->rma_size
= kvmppc_rma_size(spapr_node0_size(MACHINE(spapr
)),
1690 static int spapr_reset_drcs(Object
*child
, void *opaque
)
1693 (SpaprDrc
*) object_dynamic_cast(child
,
1694 TYPE_SPAPR_DR_CONNECTOR
);
1697 spapr_drc_reset(drc
);
1703 static void spapr_machine_reset(MachineState
*machine
)
1705 SpaprMachineState
*spapr
= SPAPR_MACHINE(machine
);
1706 PowerPCCPU
*first_ppc_cpu
;
1707 uint32_t rtas_limit
;
1708 hwaddr rtas_addr
, fdt_addr
;
1712 spapr_caps_apply(spapr
);
1714 first_ppc_cpu
= POWERPC_CPU(first_cpu
);
1715 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
1716 ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
, 0,
1717 spapr
->max_compat_pvr
)) {
1719 * If using KVM with radix mode available, VCPUs can be started
1720 * without a HPT because KVM will start them in radix mode.
1721 * Set the GR bit in PATE so that we know there is no HPT.
1723 spapr
->patb_entry
= PATE1_GR
;
1724 spapr_set_all_lpcrs(LPCR_HR
| LPCR_UPRT
, LPCR_HR
| LPCR_UPRT
);
1726 spapr_setup_hpt_and_vrma(spapr
);
1730 * If this reset wasn't generated by CAS, we should reset our
1731 * negotiated options and start from scratch
1733 if (!spapr
->cas_reboot
) {
1734 spapr_ovec_cleanup(spapr
->ov5_cas
);
1735 spapr
->ov5_cas
= spapr_ovec_new();
1737 ppc_set_compat(first_ppc_cpu
, spapr
->max_compat_pvr
, &error_fatal
);
1740 if (!SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
1741 spapr_irq_msi_reset(spapr
);
1745 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node.
1746 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is
1747 * called from vPHB reset handler so we initialize the counter here.
1748 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM
1749 * must be equally distant from any other node.
1750 * The final value of spapr->gpu_numa_id is going to be written to
1751 * max-associativity-domains in spapr_build_fdt().
1753 spapr
->gpu_numa_id
= MAX(1, nb_numa_nodes
);
1754 qemu_devices_reset();
1757 * This is fixing some of the default configuration of the XIVE
1758 * devices. To be called after the reset of the machine devices.
1760 spapr_irq_reset(spapr
, &error_fatal
);
1763 * There is no CAS under qtest. Simulate one to please the code that
1764 * depends on spapr->ov5_cas. This is especially needed to test device
1765 * unplug, so we do that before resetting the DRCs.
1767 if (qtest_enabled()) {
1768 spapr_ovec_cleanup(spapr
->ov5_cas
);
1769 spapr
->ov5_cas
= spapr_ovec_clone(spapr
->ov5
);
1772 /* DRC reset may cause a device to be unplugged. This will cause troubles
1773 * if this device is used by another device (eg, a running vhost backend
1774 * will crash QEMU if the DIMM holding the vring goes away). To avoid such
1775 * situations, we reset DRCs after all devices have been reset.
1777 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs
, NULL
);
1779 spapr_clear_pending_events(spapr
);
1782 * We place the device tree and RTAS just below either the top of the RMA,
1783 * or just below 2GB, whichever is lower, so that it can be
1784 * processed with 32-bit real mode code if necessary
1786 rtas_limit
= MIN(spapr
->rma_size
, RTAS_MAX_ADDR
);
1787 rtas_addr
= rtas_limit
- RTAS_MAX_SIZE
;
1788 fdt_addr
= rtas_addr
- FDT_MAX_SIZE
;
1790 fdt
= spapr_build_fdt(spapr
);
1792 spapr_load_rtas(spapr
, fdt
, rtas_addr
);
1796 /* Should only fail if we've built a corrupted tree */
1799 if (fdt_totalsize(fdt
) > FDT_MAX_SIZE
) {
1800 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1801 fdt_totalsize(fdt
), FDT_MAX_SIZE
);
1806 qemu_fdt_dumpdtb(fdt
, fdt_totalsize(fdt
));
1807 cpu_physical_memory_write(fdt_addr
, fdt
, fdt_totalsize(fdt
));
1808 g_free(spapr
->fdt_blob
);
1809 spapr
->fdt_size
= fdt_totalsize(fdt
);
1810 spapr
->fdt_initial_size
= spapr
->fdt_size
;
1811 spapr
->fdt_blob
= fdt
;
1813 /* Set up the entry state */
1814 spapr_cpu_set_entry_state(first_ppc_cpu
, SPAPR_ENTRY_POINT
, fdt_addr
);
1815 first_ppc_cpu
->env
.gpr
[5] = 0;
1817 spapr
->cas_reboot
= false;
1820 static void spapr_create_nvram(SpaprMachineState
*spapr
)
1822 DeviceState
*dev
= qdev_create(&spapr
->vio_bus
->bus
, "spapr-nvram");
1823 DriveInfo
*dinfo
= drive_get(IF_PFLASH
, 0, 0);
1826 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
1830 qdev_init_nofail(dev
);
1832 spapr
->nvram
= (struct SpaprNvram
*)dev
;
1835 static void spapr_rtc_create(SpaprMachineState
*spapr
)
1837 object_initialize_child(OBJECT(spapr
), "rtc",
1838 &spapr
->rtc
, sizeof(spapr
->rtc
), TYPE_SPAPR_RTC
,
1839 &error_fatal
, NULL
);
1840 object_property_set_bool(OBJECT(&spapr
->rtc
), true, "realized",
1842 object_property_add_alias(OBJECT(spapr
), "rtc-time", OBJECT(&spapr
->rtc
),
1843 "date", &error_fatal
);
1846 /* Returns whether we want to use VGA or not */
1847 static bool spapr_vga_init(PCIBus
*pci_bus
, Error
**errp
)
1849 switch (vga_interface_type
) {
1857 return pci_vga_init(pci_bus
) != NULL
;
1860 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1865 static int spapr_pre_load(void *opaque
)
1869 rc
= spapr_caps_pre_load(opaque
);
1877 static int spapr_post_load(void *opaque
, int version_id
)
1879 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1882 err
= spapr_caps_post_migration(spapr
);
1888 * In earlier versions, there was no separate qdev for the PAPR
1889 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1890 * So when migrating from those versions, poke the incoming offset
1891 * value into the RTC device
1893 if (version_id
< 3) {
1894 err
= spapr_rtc_import_offset(&spapr
->rtc
, spapr
->rtc_offset
);
1900 if (kvm_enabled() && spapr
->patb_entry
) {
1901 PowerPCCPU
*cpu
= POWERPC_CPU(first_cpu
);
1902 bool radix
= !!(spapr
->patb_entry
& PATE1_GR
);
1903 bool gtse
= !!(cpu
->env
.spr
[SPR_LPCR
] & LPCR_GTSE
);
1906 * Update LPCR:HR and UPRT as they may not be set properly in
1909 spapr_set_all_lpcrs(radix
? (LPCR_HR
| LPCR_UPRT
) : 0,
1910 LPCR_HR
| LPCR_UPRT
);
1912 err
= kvmppc_configure_v3_mmu(cpu
, radix
, gtse
, spapr
->patb_entry
);
1914 error_report("Process table config unsupported by the host");
1919 err
= spapr_irq_post_load(spapr
, version_id
);
1927 static int spapr_pre_save(void *opaque
)
1931 rc
= spapr_caps_pre_save(opaque
);
1939 static bool version_before_3(void *opaque
, int version_id
)
1941 return version_id
< 3;
1944 static bool spapr_pending_events_needed(void *opaque
)
1946 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
1947 return !QTAILQ_EMPTY(&spapr
->pending_events
);
1950 static const VMStateDescription vmstate_spapr_event_entry
= {
1951 .name
= "spapr_event_log_entry",
1953 .minimum_version_id
= 1,
1954 .fields
= (VMStateField
[]) {
1955 VMSTATE_UINT32(summary
, SpaprEventLogEntry
),
1956 VMSTATE_UINT32(extended_length
, SpaprEventLogEntry
),
1957 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log
, SpaprEventLogEntry
, 0,
1958 NULL
, extended_length
),
1959 VMSTATE_END_OF_LIST()
1963 static const VMStateDescription vmstate_spapr_pending_events
= {
1964 .name
= "spapr_pending_events",
1966 .minimum_version_id
= 1,
1967 .needed
= spapr_pending_events_needed
,
1968 .fields
= (VMStateField
[]) {
1969 VMSTATE_QTAILQ_V(pending_events
, SpaprMachineState
, 1,
1970 vmstate_spapr_event_entry
, SpaprEventLogEntry
, next
),
1971 VMSTATE_END_OF_LIST()
1975 static bool spapr_ov5_cas_needed(void *opaque
)
1977 SpaprMachineState
*spapr
= opaque
;
1978 SpaprOptionVector
*ov5_mask
= spapr_ovec_new();
1979 SpaprOptionVector
*ov5_legacy
= spapr_ovec_new();
1980 SpaprOptionVector
*ov5_removed
= spapr_ovec_new();
1983 /* Prior to the introduction of SpaprOptionVector, we had two option
1984 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1985 * Both of these options encode machine topology into the device-tree
1986 * in such a way that the now-booted OS should still be able to interact
1987 * appropriately with QEMU regardless of what options were actually
1988 * negotiatied on the source side.
1990 * As such, we can avoid migrating the CAS-negotiated options if these
1991 * are the only options available on the current machine/platform.
1992 * Since these are the only options available for pseries-2.7 and
1993 * earlier, this allows us to maintain old->new/new->old migration
1996 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1997 * via default pseries-2.8 machines and explicit command-line parameters.
1998 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1999 * of the actual CAS-negotiated values to continue working properly. For
2000 * example, availability of memory unplug depends on knowing whether
2001 * OV5_HP_EVT was negotiated via CAS.
2003 * Thus, for any cases where the set of available CAS-negotiatable
2004 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
2005 * include the CAS-negotiated options in the migration stream, unless
2006 * if they affect boot time behaviour only.
2008 spapr_ovec_set(ov5_mask
, OV5_FORM1_AFFINITY
);
2009 spapr_ovec_set(ov5_mask
, OV5_DRCONF_MEMORY
);
2010 spapr_ovec_set(ov5_mask
, OV5_DRMEM_V2
);
2012 /* spapr_ovec_diff returns true if bits were removed. we avoid using
2013 * the mask itself since in the future it's possible "legacy" bits may be
2014 * removed via machine options, which could generate a false positive
2015 * that breaks migration.
2017 spapr_ovec_intersect(ov5_legacy
, spapr
->ov5
, ov5_mask
);
2018 cas_needed
= spapr_ovec_diff(ov5_removed
, spapr
->ov5
, ov5_legacy
);
2020 spapr_ovec_cleanup(ov5_mask
);
2021 spapr_ovec_cleanup(ov5_legacy
);
2022 spapr_ovec_cleanup(ov5_removed
);
2027 static const VMStateDescription vmstate_spapr_ov5_cas
= {
2028 .name
= "spapr_option_vector_ov5_cas",
2030 .minimum_version_id
= 1,
2031 .needed
= spapr_ov5_cas_needed
,
2032 .fields
= (VMStateField
[]) {
2033 VMSTATE_STRUCT_POINTER_V(ov5_cas
, SpaprMachineState
, 1,
2034 vmstate_spapr_ovec
, SpaprOptionVector
),
2035 VMSTATE_END_OF_LIST()
2039 static bool spapr_patb_entry_needed(void *opaque
)
2041 SpaprMachineState
*spapr
= opaque
;
2043 return !!spapr
->patb_entry
;
2046 static const VMStateDescription vmstate_spapr_patb_entry
= {
2047 .name
= "spapr_patb_entry",
2049 .minimum_version_id
= 1,
2050 .needed
= spapr_patb_entry_needed
,
2051 .fields
= (VMStateField
[]) {
2052 VMSTATE_UINT64(patb_entry
, SpaprMachineState
),
2053 VMSTATE_END_OF_LIST()
2057 static bool spapr_irq_map_needed(void *opaque
)
2059 SpaprMachineState
*spapr
= opaque
;
2061 return spapr
->irq_map
&& !bitmap_empty(spapr
->irq_map
, spapr
->irq_map_nr
);
2064 static const VMStateDescription vmstate_spapr_irq_map
= {
2065 .name
= "spapr_irq_map",
2067 .minimum_version_id
= 1,
2068 .needed
= spapr_irq_map_needed
,
2069 .fields
= (VMStateField
[]) {
2070 VMSTATE_BITMAP(irq_map
, SpaprMachineState
, 0, irq_map_nr
),
2071 VMSTATE_END_OF_LIST()
2075 static bool spapr_dtb_needed(void *opaque
)
2077 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(opaque
);
2079 return smc
->update_dt_enabled
;
2082 static int spapr_dtb_pre_load(void *opaque
)
2084 SpaprMachineState
*spapr
= (SpaprMachineState
*)opaque
;
2086 g_free(spapr
->fdt_blob
);
2087 spapr
->fdt_blob
= NULL
;
2088 spapr
->fdt_size
= 0;
2093 static const VMStateDescription vmstate_spapr_dtb
= {
2094 .name
= "spapr_dtb",
2096 .minimum_version_id
= 1,
2097 .needed
= spapr_dtb_needed
,
2098 .pre_load
= spapr_dtb_pre_load
,
2099 .fields
= (VMStateField
[]) {
2100 VMSTATE_UINT32(fdt_initial_size
, SpaprMachineState
),
2101 VMSTATE_UINT32(fdt_size
, SpaprMachineState
),
2102 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob
, SpaprMachineState
, 0, NULL
,
2104 VMSTATE_END_OF_LIST()
2108 static const VMStateDescription vmstate_spapr
= {
2111 .minimum_version_id
= 1,
2112 .pre_load
= spapr_pre_load
,
2113 .post_load
= spapr_post_load
,
2114 .pre_save
= spapr_pre_save
,
2115 .fields
= (VMStateField
[]) {
2116 /* used to be @next_irq */
2117 VMSTATE_UNUSED_BUFFER(version_before_3
, 0, 4),
2120 VMSTATE_UINT64_TEST(rtc_offset
, SpaprMachineState
, version_before_3
),
2122 VMSTATE_PPC_TIMEBASE_V(tb
, SpaprMachineState
, 2),
2123 VMSTATE_END_OF_LIST()
2125 .subsections
= (const VMStateDescription
*[]) {
2126 &vmstate_spapr_ov5_cas
,
2127 &vmstate_spapr_patb_entry
,
2128 &vmstate_spapr_pending_events
,
2129 &vmstate_spapr_cap_htm
,
2130 &vmstate_spapr_cap_vsx
,
2131 &vmstate_spapr_cap_dfp
,
2132 &vmstate_spapr_cap_cfpc
,
2133 &vmstate_spapr_cap_sbbc
,
2134 &vmstate_spapr_cap_ibs
,
2135 &vmstate_spapr_cap_hpt_maxpagesize
,
2136 &vmstate_spapr_irq_map
,
2137 &vmstate_spapr_cap_nested_kvm_hv
,
2139 &vmstate_spapr_cap_large_decr
,
2140 &vmstate_spapr_cap_ccf_assist
,
2145 static int htab_save_setup(QEMUFile
*f
, void *opaque
)
2147 SpaprMachineState
*spapr
= opaque
;
2149 /* "Iteration" header */
2150 if (!spapr
->htab_shift
) {
2151 qemu_put_be32(f
, -1);
2153 qemu_put_be32(f
, spapr
->htab_shift
);
2157 spapr
->htab_save_index
= 0;
2158 spapr
->htab_first_pass
= true;
2160 if (spapr
->htab_shift
) {
2161 assert(kvm_enabled());
2169 static void htab_save_chunk(QEMUFile
*f
, SpaprMachineState
*spapr
,
2170 int chunkstart
, int n_valid
, int n_invalid
)
2172 qemu_put_be32(f
, chunkstart
);
2173 qemu_put_be16(f
, n_valid
);
2174 qemu_put_be16(f
, n_invalid
);
2175 qemu_put_buffer(f
, HPTE(spapr
->htab
, chunkstart
),
2176 HASH_PTE_SIZE_64
* n_valid
);
2179 static void htab_save_end_marker(QEMUFile
*f
)
2181 qemu_put_be32(f
, 0);
2182 qemu_put_be16(f
, 0);
2183 qemu_put_be16(f
, 0);
2186 static void htab_save_first_pass(QEMUFile
*f
, SpaprMachineState
*spapr
,
2189 bool has_timeout
= max_ns
!= -1;
2190 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
2191 int index
= spapr
->htab_save_index
;
2192 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
2194 assert(spapr
->htab_first_pass
);
2199 /* Consume invalid HPTEs */
2200 while ((index
< htabslots
)
2201 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2202 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2206 /* Consume valid HPTEs */
2208 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
2209 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2210 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2214 if (index
> chunkstart
) {
2215 int n_valid
= index
- chunkstart
;
2217 htab_save_chunk(f
, spapr
, chunkstart
, n_valid
, 0);
2220 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
2224 } while ((index
< htabslots
) && !qemu_file_rate_limit(f
));
2226 if (index
>= htabslots
) {
2227 assert(index
== htabslots
);
2229 spapr
->htab_first_pass
= false;
2231 spapr
->htab_save_index
= index
;
2234 static int htab_save_later_pass(QEMUFile
*f
, SpaprMachineState
*spapr
,
2237 bool final
= max_ns
< 0;
2238 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
2239 int examined
= 0, sent
= 0;
2240 int index
= spapr
->htab_save_index
;
2241 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
2243 assert(!spapr
->htab_first_pass
);
2246 int chunkstart
, invalidstart
;
2248 /* Consume non-dirty HPTEs */
2249 while ((index
< htabslots
)
2250 && !HPTE_DIRTY(HPTE(spapr
->htab
, index
))) {
2256 /* Consume valid dirty HPTEs */
2257 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
2258 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
2259 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2260 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2265 invalidstart
= index
;
2266 /* Consume invalid dirty HPTEs */
2267 while ((index
< htabslots
) && (index
- invalidstart
< USHRT_MAX
)
2268 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
2269 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2270 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2275 if (index
> chunkstart
) {
2276 int n_valid
= invalidstart
- chunkstart
;
2277 int n_invalid
= index
- invalidstart
;
2279 htab_save_chunk(f
, spapr
, chunkstart
, n_valid
, n_invalid
);
2280 sent
+= index
- chunkstart
;
2282 if (!final
&& (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
2287 if (examined
>= htabslots
) {
2291 if (index
>= htabslots
) {
2292 assert(index
== htabslots
);
2295 } while ((examined
< htabslots
) && (!qemu_file_rate_limit(f
) || final
));
2297 if (index
>= htabslots
) {
2298 assert(index
== htabslots
);
2302 spapr
->htab_save_index
= index
;
2304 return (examined
>= htabslots
) && (sent
== 0) ? 1 : 0;
2307 #define MAX_ITERATION_NS 5000000 /* 5 ms */
2308 #define MAX_KVM_BUF_SIZE 2048
2310 static int htab_save_iterate(QEMUFile
*f
, void *opaque
)
2312 SpaprMachineState
*spapr
= opaque
;
2316 /* Iteration header */
2317 if (!spapr
->htab_shift
) {
2318 qemu_put_be32(f
, -1);
2321 qemu_put_be32(f
, 0);
2325 assert(kvm_enabled());
2327 fd
= get_htab_fd(spapr
);
2332 rc
= kvmppc_save_htab(f
, fd
, MAX_KVM_BUF_SIZE
, MAX_ITERATION_NS
);
2336 } else if (spapr
->htab_first_pass
) {
2337 htab_save_first_pass(f
, spapr
, MAX_ITERATION_NS
);
2339 rc
= htab_save_later_pass(f
, spapr
, MAX_ITERATION_NS
);
2342 htab_save_end_marker(f
);
2347 static int htab_save_complete(QEMUFile
*f
, void *opaque
)
2349 SpaprMachineState
*spapr
= opaque
;
2352 /* Iteration header */
2353 if (!spapr
->htab_shift
) {
2354 qemu_put_be32(f
, -1);
2357 qemu_put_be32(f
, 0);
2363 assert(kvm_enabled());
2365 fd
= get_htab_fd(spapr
);
2370 rc
= kvmppc_save_htab(f
, fd
, MAX_KVM_BUF_SIZE
, -1);
2375 if (spapr
->htab_first_pass
) {
2376 htab_save_first_pass(f
, spapr
, -1);
2378 htab_save_later_pass(f
, spapr
, -1);
2382 htab_save_end_marker(f
);
2387 static int htab_load(QEMUFile
*f
, void *opaque
, int version_id
)
2389 SpaprMachineState
*spapr
= opaque
;
2390 uint32_t section_hdr
;
2392 Error
*local_err
= NULL
;
2394 if (version_id
< 1 || version_id
> 1) {
2395 error_report("htab_load() bad version");
2399 section_hdr
= qemu_get_be32(f
);
2401 if (section_hdr
== -1) {
2402 spapr_free_hpt(spapr
);
2407 /* First section gives the htab size */
2408 spapr_reallocate_hpt(spapr
, section_hdr
, &local_err
);
2410 error_report_err(local_err
);
2417 assert(kvm_enabled());
2419 fd
= kvmppc_get_htab_fd(true, 0, &local_err
);
2421 error_report_err(local_err
);
2428 uint16_t n_valid
, n_invalid
;
2430 index
= qemu_get_be32(f
);
2431 n_valid
= qemu_get_be16(f
);
2432 n_invalid
= qemu_get_be16(f
);
2434 if ((index
== 0) && (n_valid
== 0) && (n_invalid
== 0)) {
2439 if ((index
+ n_valid
+ n_invalid
) >
2440 (HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
)) {
2441 /* Bad index in stream */
2443 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2444 index
, n_valid
, n_invalid
, spapr
->htab_shift
);
2450 qemu_get_buffer(f
, HPTE(spapr
->htab
, index
),
2451 HASH_PTE_SIZE_64
* n_valid
);
2454 memset(HPTE(spapr
->htab
, index
+ n_valid
), 0,
2455 HASH_PTE_SIZE_64
* n_invalid
);
2462 rc
= kvmppc_load_htab_chunk(f
, fd
, index
, n_valid
, n_invalid
);
2477 static void htab_save_cleanup(void *opaque
)
2479 SpaprMachineState
*spapr
= opaque
;
2481 close_htab_fd(spapr
);
2484 static SaveVMHandlers savevm_htab_handlers
= {
2485 .save_setup
= htab_save_setup
,
2486 .save_live_iterate
= htab_save_iterate
,
2487 .save_live_complete_precopy
= htab_save_complete
,
2488 .save_cleanup
= htab_save_cleanup
,
2489 .load_state
= htab_load
,
2492 static void spapr_boot_set(void *opaque
, const char *boot_device
,
2495 MachineState
*machine
= MACHINE(opaque
);
2496 machine
->boot_order
= g_strdup(boot_device
);
2499 static void spapr_create_lmb_dr_connectors(SpaprMachineState
*spapr
)
2501 MachineState
*machine
= MACHINE(spapr
);
2502 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
2503 uint32_t nr_lmbs
= (machine
->maxram_size
- machine
->ram_size
)/lmb_size
;
2506 for (i
= 0; i
< nr_lmbs
; i
++) {
2509 addr
= i
* lmb_size
+ machine
->device_memory
->base
;
2510 spapr_dr_connector_new(OBJECT(spapr
), TYPE_SPAPR_DRC_LMB
,
2516 * If RAM size, maxmem size and individual node mem sizes aren't aligned
2517 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
2518 * since we can't support such unaligned sizes with DRCONF_MEMORY.
2520 static void spapr_validate_node_memory(MachineState
*machine
, Error
**errp
)
2524 if (machine
->ram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
2525 error_setg(errp
, "Memory size 0x" RAM_ADDR_FMT
2526 " is not aligned to %" PRIu64
" MiB",
2528 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2532 if (machine
->maxram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
2533 error_setg(errp
, "Maximum memory size 0x" RAM_ADDR_FMT
2534 " is not aligned to %" PRIu64
" MiB",
2536 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2540 for (i
= 0; i
< nb_numa_nodes
; i
++) {
2541 if (numa_info
[i
].node_mem
% SPAPR_MEMORY_BLOCK_SIZE
) {
2543 "Node %d memory size 0x%" PRIx64
2544 " is not aligned to %" PRIu64
" MiB",
2545 i
, numa_info
[i
].node_mem
,
2546 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2552 /* find cpu slot in machine->possible_cpus by core_id */
2553 static CPUArchId
*spapr_find_cpu_slot(MachineState
*ms
, uint32_t id
, int *idx
)
2555 int index
= id
/ ms
->smp
.threads
;
2557 if (index
>= ms
->possible_cpus
->len
) {
2563 return &ms
->possible_cpus
->cpus
[index
];
2566 static void spapr_set_vsmt_mode(SpaprMachineState
*spapr
, Error
**errp
)
2568 MachineState
*ms
= MACHINE(spapr
);
2569 Error
*local_err
= NULL
;
2570 bool vsmt_user
= !!spapr
->vsmt
;
2571 int kvm_smt
= kvmppc_smt_threads();
2573 unsigned int smp_threads
= ms
->smp
.threads
;
2575 if (!kvm_enabled() && (smp_threads
> 1)) {
2576 error_setg(&local_err
, "TCG cannot support more than 1 thread/core "
2577 "on a pseries machine");
2580 if (!is_power_of_2(smp_threads
)) {
2581 error_setg(&local_err
, "Cannot support %d threads/core on a pseries "
2582 "machine because it must be a power of 2", smp_threads
);
2586 /* Detemine the VSMT mode to use: */
2588 if (spapr
->vsmt
< smp_threads
) {
2589 error_setg(&local_err
, "Cannot support VSMT mode %d"
2590 " because it must be >= threads/core (%d)",
2591 spapr
->vsmt
, smp_threads
);
2594 /* In this case, spapr->vsmt has been set by the command line */
2597 * Default VSMT value is tricky, because we need it to be as
2598 * consistent as possible (for migration), but this requires
2599 * changing it for at least some existing cases. We pick 8 as
2600 * the value that we'd get with KVM on POWER8, the
2601 * overwhelmingly common case in production systems.
2603 spapr
->vsmt
= MAX(8, smp_threads
);
2606 /* KVM: If necessary, set the SMT mode: */
2607 if (kvm_enabled() && (spapr
->vsmt
!= kvm_smt
)) {
2608 ret
= kvmppc_set_smt_threads(spapr
->vsmt
);
2610 /* Looks like KVM isn't able to change VSMT mode */
2611 error_setg(&local_err
,
2612 "Failed to set KVM's VSMT mode to %d (errno %d)",
2614 /* We can live with that if the default one is big enough
2615 * for the number of threads, and a submultiple of the one
2616 * we want. In this case we'll waste some vcpu ids, but
2617 * behaviour will be correct */
2618 if ((kvm_smt
>= smp_threads
) && ((spapr
->vsmt
% kvm_smt
) == 0)) {
2619 warn_report_err(local_err
);
2624 error_append_hint(&local_err
,
2625 "On PPC, a VM with %d threads/core"
2626 " on a host with %d threads/core"
2627 " requires the use of VSMT mode %d.\n",
2628 smp_threads
, kvm_smt
, spapr
->vsmt
);
2630 kvmppc_hint_smt_possible(&local_err
);
2635 /* else TCG: nothing to do currently */
2637 error_propagate(errp
, local_err
);
2640 static void spapr_init_cpus(SpaprMachineState
*spapr
)
2642 MachineState
*machine
= MACHINE(spapr
);
2643 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2644 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
2645 const char *type
= spapr_get_cpu_core_type(machine
->cpu_type
);
2646 const CPUArchIdList
*possible_cpus
;
2647 unsigned int smp_cpus
= machine
->smp
.cpus
;
2648 unsigned int smp_threads
= machine
->smp
.threads
;
2649 unsigned int max_cpus
= machine
->smp
.max_cpus
;
2650 int boot_cores_nr
= smp_cpus
/ smp_threads
;
2653 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
2654 if (mc
->has_hotpluggable_cpus
) {
2655 if (smp_cpus
% smp_threads
) {
2656 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2657 smp_cpus
, smp_threads
);
2660 if (max_cpus
% smp_threads
) {
2661 error_report("max_cpus (%u) must be multiple of threads (%u)",
2662 max_cpus
, smp_threads
);
2666 if (max_cpus
!= smp_cpus
) {
2667 error_report("This machine version does not support CPU hotplug");
2670 boot_cores_nr
= possible_cpus
->len
;
2673 if (smc
->pre_2_10_has_unused_icps
) {
2676 for (i
= 0; i
< spapr_max_server_number(spapr
); i
++) {
2677 /* Dummy entries get deregistered when real ICPState objects
2678 * are registered during CPU core hotplug.
2680 pre_2_10_vmstate_register_dummy_icp(i
);
2684 for (i
= 0; i
< possible_cpus
->len
; i
++) {
2685 int core_id
= i
* smp_threads
;
2687 if (mc
->has_hotpluggable_cpus
) {
2688 spapr_dr_connector_new(OBJECT(spapr
), TYPE_SPAPR_DRC_CPU
,
2689 spapr_vcpu_id(spapr
, core_id
));
2692 if (i
< boot_cores_nr
) {
2693 Object
*core
= object_new(type
);
2694 int nr_threads
= smp_threads
;
2696 /* Handle the partially filled core for older machine types */
2697 if ((i
+ 1) * smp_threads
>= smp_cpus
) {
2698 nr_threads
= smp_cpus
- i
* smp_threads
;
2701 object_property_set_int(core
, nr_threads
, "nr-threads",
2703 object_property_set_int(core
, core_id
, CPU_CORE_PROP_CORE_ID
,
2705 object_property_set_bool(core
, true, "realized", &error_fatal
);
2712 static PCIHostState
*spapr_create_default_phb(void)
2716 dev
= qdev_create(NULL
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
2717 qdev_prop_set_uint32(dev
, "index", 0);
2718 qdev_init_nofail(dev
);
2720 return PCI_HOST_BRIDGE(dev
);
2723 /* pSeries LPAR / sPAPR hardware init */
2724 static void spapr_machine_init(MachineState
*machine
)
2726 SpaprMachineState
*spapr
= SPAPR_MACHINE(machine
);
2727 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
2728 const char *kernel_filename
= machine
->kernel_filename
;
2729 const char *initrd_filename
= machine
->initrd_filename
;
2732 MemoryRegion
*sysmem
= get_system_memory();
2733 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
2734 hwaddr node0_size
= spapr_node0_size(machine
);
2735 long load_limit
, fw_size
;
2737 Error
*resize_hpt_err
= NULL
;
2739 msi_nonbroken
= true;
2741 QLIST_INIT(&spapr
->phbs
);
2742 QTAILQ_INIT(&spapr
->pending_dimm_unplugs
);
2744 /* Determine capabilities to run with */
2745 spapr_caps_init(spapr
);
2747 kvmppc_check_papr_resize_hpt(&resize_hpt_err
);
2748 if (spapr
->resize_hpt
== SPAPR_RESIZE_HPT_DEFAULT
) {
2750 * If the user explicitly requested a mode we should either
2751 * supply it, or fail completely (which we do below). But if
2752 * it's not set explicitly, we reset our mode to something
2755 if (resize_hpt_err
) {
2756 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DISABLED
;
2757 error_free(resize_hpt_err
);
2758 resize_hpt_err
= NULL
;
2760 spapr
->resize_hpt
= smc
->resize_hpt_default
;
2764 assert(spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DEFAULT
);
2766 if ((spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) && resize_hpt_err
) {
2768 * User requested HPT resize, but this host can't supply it. Bail out
2770 error_report_err(resize_hpt_err
);
2774 spapr
->rma_size
= node0_size
;
2776 /* With KVM, we don't actually know whether KVM supports an
2777 * unbounded RMA (PR KVM) or is limited by the hash table size
2778 * (HV KVM using VRMA), so we always assume the latter
2780 * In that case, we also limit the initial allocations for RTAS
2781 * etc... to 256M since we have no way to know what the VRMA size
2782 * is going to be as it depends on the size of the hash table
2783 * which isn't determined yet.
2785 if (kvm_enabled()) {
2786 spapr
->vrma_adjust
= 1;
2787 spapr
->rma_size
= MIN(spapr
->rma_size
, 0x10000000);
2790 /* Actually we don't support unbounded RMA anymore since we added
2791 * proper emulation of HV mode. The max we can get is 16G which
2792 * also happens to be what we configure for PAPR mode so make sure
2793 * we don't do anything bigger than that
2795 spapr
->rma_size
= MIN(spapr
->rma_size
, 0x400000000ull
);
2797 if (spapr
->rma_size
> node0_size
) {
2798 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx
")",
2803 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2804 load_limit
= MIN(spapr
->rma_size
, RTAS_MAX_ADDR
) - FW_OVERHEAD
;
2807 * VSMT must be set in order to be able to compute VCPU ids, ie to
2808 * call spapr_max_server_number() or spapr_vcpu_id().
2810 spapr_set_vsmt_mode(spapr
, &error_fatal
);
2812 /* Set up Interrupt Controller before we create the VCPUs */
2813 spapr_irq_init(spapr
, &error_fatal
);
2815 /* Set up containers for ibm,client-architecture-support negotiated options
2817 spapr
->ov5
= spapr_ovec_new();
2818 spapr
->ov5_cas
= spapr_ovec_new();
2820 if (smc
->dr_lmb_enabled
) {
2821 spapr_ovec_set(spapr
->ov5
, OV5_DRCONF_MEMORY
);
2822 spapr_validate_node_memory(machine
, &error_fatal
);
2825 spapr_ovec_set(spapr
->ov5
, OV5_FORM1_AFFINITY
);
2827 /* advertise support for dedicated HP event source to guests */
2828 if (spapr
->use_hotplug_event_source
) {
2829 spapr_ovec_set(spapr
->ov5
, OV5_HP_EVT
);
2832 /* advertise support for HPT resizing */
2833 if (spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) {
2834 spapr_ovec_set(spapr
->ov5
, OV5_HPT_RESIZE
);
2837 /* advertise support for ibm,dyamic-memory-v2 */
2838 spapr_ovec_set(spapr
->ov5
, OV5_DRMEM_V2
);
2840 /* advertise XIVE on POWER9 machines */
2841 if (spapr
->irq
->ov5
& (SPAPR_OV5_XIVE_EXPLOIT
| SPAPR_OV5_XIVE_BOTH
)) {
2842 spapr_ovec_set(spapr
->ov5
, OV5_XIVE_EXPLOIT
);
2846 spapr_init_cpus(spapr
);
2848 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&
2849 ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
, 0,
2850 spapr
->max_compat_pvr
)) {
2851 /* KVM and TCG always allow GTSE with radix... */
2852 spapr_ovec_set(spapr
->ov5
, OV5_MMU_RADIX_GTSE
);
2854 /* ... but not with hash (currently). */
2856 if (kvm_enabled()) {
2857 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2858 kvmppc_enable_logical_ci_hcalls();
2859 kvmppc_enable_set_mode_hcall();
2861 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2862 kvmppc_enable_clear_ref_mod_hcalls();
2864 /* Enable H_PAGE_INIT */
2865 kvmppc_enable_h_page_init();
2869 memory_region_allocate_system_memory(ram
, NULL
, "ppc_spapr.ram",
2871 memory_region_add_subregion(sysmem
, 0, ram
);
2873 /* always allocate the device memory information */
2874 machine
->device_memory
= g_malloc0(sizeof(*machine
->device_memory
));
2876 /* initialize hotplug memory address space */
2877 if (machine
->ram_size
< machine
->maxram_size
) {
2878 ram_addr_t device_mem_size
= machine
->maxram_size
- machine
->ram_size
;
2880 * Limit the number of hotpluggable memory slots to half the number
2881 * slots that KVM supports, leaving the other half for PCI and other
2882 * devices. However ensure that number of slots doesn't drop below 32.
2884 int max_memslots
= kvm_enabled() ? kvm_get_max_memslots() / 2 :
2885 SPAPR_MAX_RAM_SLOTS
;
2887 if (max_memslots
< SPAPR_MAX_RAM_SLOTS
) {
2888 max_memslots
= SPAPR_MAX_RAM_SLOTS
;
2890 if (machine
->ram_slots
> max_memslots
) {
2891 error_report("Specified number of memory slots %"
2892 PRIu64
" exceeds max supported %d",
2893 machine
->ram_slots
, max_memslots
);
2897 machine
->device_memory
->base
= ROUND_UP(machine
->ram_size
,
2898 SPAPR_DEVICE_MEM_ALIGN
);
2899 memory_region_init(&machine
->device_memory
->mr
, OBJECT(spapr
),
2900 "device-memory", device_mem_size
);
2901 memory_region_add_subregion(sysmem
, machine
->device_memory
->base
,
2902 &machine
->device_memory
->mr
);
2905 if (smc
->dr_lmb_enabled
) {
2906 spapr_create_lmb_dr_connectors(spapr
);
2909 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, "spapr-rtas.bin");
2911 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
2914 spapr
->rtas_size
= get_image_size(filename
);
2915 if (spapr
->rtas_size
< 0) {
2916 error_report("Could not get size of LPAR rtas '%s'", filename
);
2919 spapr
->rtas_blob
= g_malloc(spapr
->rtas_size
);
2920 if (load_image_size(filename
, spapr
->rtas_blob
, spapr
->rtas_size
) < 0) {
2921 error_report("Could not load LPAR rtas '%s'", filename
);
2924 if (spapr
->rtas_size
> RTAS_MAX_SIZE
) {
2925 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
2926 (size_t)spapr
->rtas_size
, RTAS_MAX_SIZE
);
2931 /* Set up RTAS event infrastructure */
2932 spapr_events_init(spapr
);
2934 /* Set up the RTC RTAS interfaces */
2935 spapr_rtc_create(spapr
);
2937 /* Set up VIO bus */
2938 spapr
->vio_bus
= spapr_vio_bus_init();
2940 for (i
= 0; i
< serial_max_hds(); i
++) {
2942 spapr_vty_create(spapr
->vio_bus
, serial_hd(i
));
2946 /* We always have at least the nvram device on VIO */
2947 spapr_create_nvram(spapr
);
2950 * Setup hotplug / dynamic-reconfiguration connectors. top-level
2951 * connectors (described in root DT node's "ibm,drc-types" property)
2952 * are pre-initialized here. additional child connectors (such as
2953 * connectors for a PHBs PCI slots) are added as needed during their
2954 * parent's realization.
2956 if (smc
->dr_phb_enabled
) {
2957 for (i
= 0; i
< SPAPR_MAX_PHBS
; i
++) {
2958 spapr_dr_connector_new(OBJECT(machine
), TYPE_SPAPR_DRC_PHB
, i
);
2963 spapr_pci_rtas_init();
2965 phb
= spapr_create_default_phb();
2967 for (i
= 0; i
< nb_nics
; i
++) {
2968 NICInfo
*nd
= &nd_table
[i
];
2971 nd
->model
= g_strdup("spapr-vlan");
2974 if (g_str_equal(nd
->model
, "spapr-vlan") ||
2975 g_str_equal(nd
->model
, "ibmveth")) {
2976 spapr_vlan_create(spapr
->vio_bus
, nd
);
2978 pci_nic_init_nofail(&nd_table
[i
], phb
->bus
, nd
->model
, NULL
);
2982 for (i
= 0; i
<= drive_get_max_bus(IF_SCSI
); i
++) {
2983 spapr_vscsi_create(spapr
->vio_bus
);
2987 if (spapr_vga_init(phb
->bus
, &error_fatal
)) {
2988 spapr
->has_graphics
= true;
2989 machine
->usb
|= defaults_enabled() && !machine
->usb_disabled
;
2993 if (smc
->use_ohci_by_default
) {
2994 pci_create_simple(phb
->bus
, -1, "pci-ohci");
2996 pci_create_simple(phb
->bus
, -1, "nec-usb-xhci");
2999 if (spapr
->has_graphics
) {
3000 USBBus
*usb_bus
= usb_bus_find(-1);
3002 usb_create_simple(usb_bus
, "usb-kbd");
3003 usb_create_simple(usb_bus
, "usb-mouse");
3007 if (spapr
->rma_size
< (MIN_RMA_SLOF
* MiB
)) {
3009 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
3014 if (kernel_filename
) {
3015 uint64_t lowaddr
= 0;
3017 spapr
->kernel_size
= load_elf(kernel_filename
, NULL
,
3018 translate_kernel_address
, NULL
,
3019 NULL
, &lowaddr
, NULL
, 1,
3020 PPC_ELF_MACHINE
, 0, 0);
3021 if (spapr
->kernel_size
== ELF_LOAD_WRONG_ENDIAN
) {
3022 spapr
->kernel_size
= load_elf(kernel_filename
, NULL
,
3023 translate_kernel_address
, NULL
, NULL
,
3024 &lowaddr
, NULL
, 0, PPC_ELF_MACHINE
,
3026 spapr
->kernel_le
= spapr
->kernel_size
> 0;
3028 if (spapr
->kernel_size
< 0) {
3029 error_report("error loading %s: %s", kernel_filename
,
3030 load_elf_strerror(spapr
->kernel_size
));
3035 if (initrd_filename
) {
3036 /* Try to locate the initrd in the gap between the kernel
3037 * and the firmware. Add a bit of space just in case
3039 spapr
->initrd_base
= (KERNEL_LOAD_ADDR
+ spapr
->kernel_size
3040 + 0x1ffff) & ~0xffff;
3041 spapr
->initrd_size
= load_image_targphys(initrd_filename
,
3044 - spapr
->initrd_base
);
3045 if (spapr
->initrd_size
< 0) {
3046 error_report("could not load initial ram disk '%s'",
3053 if (bios_name
== NULL
) {
3054 bios_name
= FW_FILE_NAME
;
3056 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
3058 error_report("Could not find LPAR firmware '%s'", bios_name
);
3061 fw_size
= load_image_targphys(filename
, 0, FW_MAX_SIZE
);
3063 error_report("Could not load LPAR firmware '%s'", filename
);
3068 /* FIXME: Should register things through the MachineState's qdev
3069 * interface, this is a legacy from the sPAPREnvironment structure
3070 * which predated MachineState but had a similar function */
3071 vmstate_register(NULL
, 0, &vmstate_spapr
, spapr
);
3072 register_savevm_live(NULL
, "spapr/htab", -1, 1,
3073 &savevm_htab_handlers
, spapr
);
3075 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine
),
3078 qemu_register_boot_set(spapr_boot_set
, spapr
);
3080 if (kvm_enabled()) {
3081 /* to stop and start vmclock */
3082 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change
,
3085 kvmppc_spapr_enable_inkernel_multitce();
3089 static int spapr_kvm_type(MachineState
*machine
, const char *vm_type
)
3095 if (!strcmp(vm_type
, "HV")) {
3099 if (!strcmp(vm_type
, "PR")) {
3103 error_report("Unknown kvm-type specified '%s'", vm_type
);
3108 * Implementation of an interface to adjust firmware path
3109 * for the bootindex property handling.
3111 static char *spapr_get_fw_dev_path(FWPathProvider
*p
, BusState
*bus
,
3114 #define CAST(type, obj, name) \
3115 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
3116 SCSIDevice
*d
= CAST(SCSIDevice
, dev
, TYPE_SCSI_DEVICE
);
3117 SpaprPhbState
*phb
= CAST(SpaprPhbState
, dev
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
3118 VHostSCSICommon
*vsc
= CAST(VHostSCSICommon
, dev
, TYPE_VHOST_SCSI_COMMON
);
3121 void *spapr
= CAST(void, bus
->parent
, "spapr-vscsi");
3122 VirtIOSCSI
*virtio
= CAST(VirtIOSCSI
, bus
->parent
, TYPE_VIRTIO_SCSI
);
3123 USBDevice
*usb
= CAST(USBDevice
, bus
->parent
, TYPE_USB_DEVICE
);
3127 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
3128 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form
3129 * 0x8000 | (target << 8) | (bus << 5) | lun
3130 * (see the "Logical unit addressing format" table in SAM5)
3132 unsigned id
= 0x8000 | (d
->id
<< 8) | (d
->channel
<< 5) | d
->lun
;
3133 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3134 (uint64_t)id
<< 48);
3135 } else if (virtio
) {
3137 * We use SRP luns of the form 01000000 | (target << 8) | lun
3138 * in the top 32 bits of the 64-bit LUN
3139 * Note: the quote above is from SLOF and it is wrong,
3140 * the actual binding is:
3141 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
3143 unsigned id
= 0x1000000 | (d
->id
<< 16) | d
->lun
;
3144 if (d
->lun
>= 256) {
3145 /* Use the LUN "flat space addressing method" */
3148 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3149 (uint64_t)id
<< 32);
3152 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
3153 * in the top 32 bits of the 64-bit LUN
3155 unsigned usb_port
= atoi(usb
->port
->path
);
3156 unsigned id
= 0x1000000 | (usb_port
<< 16) | d
->lun
;
3157 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
3158 (uint64_t)id
<< 32);
3163 * SLOF probes the USB devices, and if it recognizes that the device is a
3164 * storage device, it changes its name to "storage" instead of "usb-host",
3165 * and additionally adds a child node for the SCSI LUN, so the correct
3166 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
3168 if (strcmp("usb-host", qdev_fw_name(dev
)) == 0) {
3169 USBDevice
*usbdev
= CAST(USBDevice
, dev
, TYPE_USB_DEVICE
);
3170 if (usb_host_dev_is_scsi_storage(usbdev
)) {
3171 return g_strdup_printf("storage@%s/disk", usbdev
->port
->path
);
3176 /* Replace "pci" with "pci@800000020000000" */
3177 return g_strdup_printf("pci@%"PRIX64
, phb
->buid
);
3181 /* Same logic as virtio above */
3182 unsigned id
= 0x1000000 | (vsc
->target
<< 16) | vsc
->lun
;
3183 return g_strdup_printf("disk@%"PRIX64
, (uint64_t)id
<< 32);
3186 if (g_str_equal("pci-bridge", qdev_fw_name(dev
))) {
3187 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */
3188 PCIDevice
*pcidev
= CAST(PCIDevice
, dev
, TYPE_PCI_DEVICE
);
3189 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev
->devfn
));
3195 static char *spapr_get_kvm_type(Object
*obj
, Error
**errp
)
3197 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3199 return g_strdup(spapr
->kvm_type
);
3202 static void spapr_set_kvm_type(Object
*obj
, const char *value
, Error
**errp
)
3204 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3206 g_free(spapr
->kvm_type
);
3207 spapr
->kvm_type
= g_strdup(value
);
3210 static bool spapr_get_modern_hotplug_events(Object
*obj
, Error
**errp
)
3212 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3214 return spapr
->use_hotplug_event_source
;
3217 static void spapr_set_modern_hotplug_events(Object
*obj
, bool value
,
3220 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3222 spapr
->use_hotplug_event_source
= value
;
3225 static bool spapr_get_msix_emulation(Object
*obj
, Error
**errp
)
3230 static char *spapr_get_resize_hpt(Object
*obj
, Error
**errp
)
3232 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3234 switch (spapr
->resize_hpt
) {
3235 case SPAPR_RESIZE_HPT_DEFAULT
:
3236 return g_strdup("default");
3237 case SPAPR_RESIZE_HPT_DISABLED
:
3238 return g_strdup("disabled");
3239 case SPAPR_RESIZE_HPT_ENABLED
:
3240 return g_strdup("enabled");
3241 case SPAPR_RESIZE_HPT_REQUIRED
:
3242 return g_strdup("required");
3244 g_assert_not_reached();
3247 static void spapr_set_resize_hpt(Object
*obj
, const char *value
, Error
**errp
)
3249 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3251 if (strcmp(value
, "default") == 0) {
3252 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DEFAULT
;
3253 } else if (strcmp(value
, "disabled") == 0) {
3254 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DISABLED
;
3255 } else if (strcmp(value
, "enabled") == 0) {
3256 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_ENABLED
;
3257 } else if (strcmp(value
, "required") == 0) {
3258 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_REQUIRED
;
3260 error_setg(errp
, "Bad value for \"resize-hpt\" property");
3264 static void spapr_get_vsmt(Object
*obj
, Visitor
*v
, const char *name
,
3265 void *opaque
, Error
**errp
)
3267 visit_type_uint32(v
, name
, (uint32_t *)opaque
, errp
);
3270 static void spapr_set_vsmt(Object
*obj
, Visitor
*v
, const char *name
,
3271 void *opaque
, Error
**errp
)
3273 visit_type_uint32(v
, name
, (uint32_t *)opaque
, errp
);
3276 static char *spapr_get_ic_mode(Object
*obj
, Error
**errp
)
3278 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3280 if (spapr
->irq
== &spapr_irq_xics_legacy
) {
3281 return g_strdup("legacy");
3282 } else if (spapr
->irq
== &spapr_irq_xics
) {
3283 return g_strdup("xics");
3284 } else if (spapr
->irq
== &spapr_irq_xive
) {
3285 return g_strdup("xive");
3286 } else if (spapr
->irq
== &spapr_irq_dual
) {
3287 return g_strdup("dual");
3289 g_assert_not_reached();
3292 static void spapr_set_ic_mode(Object
*obj
, const char *value
, Error
**errp
)
3294 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3296 if (SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
3297 error_setg(errp
, "This machine only uses the legacy XICS backend, don't pass ic-mode");
3301 /* The legacy IRQ backend can not be set */
3302 if (strcmp(value
, "xics") == 0) {
3303 spapr
->irq
= &spapr_irq_xics
;
3304 } else if (strcmp(value
, "xive") == 0) {
3305 spapr
->irq
= &spapr_irq_xive
;
3306 } else if (strcmp(value
, "dual") == 0) {
3307 spapr
->irq
= &spapr_irq_dual
;
3309 error_setg(errp
, "Bad value for \"ic-mode\" property");
3313 static char *spapr_get_host_model(Object
*obj
, Error
**errp
)
3315 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3317 return g_strdup(spapr
->host_model
);
3320 static void spapr_set_host_model(Object
*obj
, const char *value
, Error
**errp
)
3322 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3324 g_free(spapr
->host_model
);
3325 spapr
->host_model
= g_strdup(value
);
3328 static char *spapr_get_host_serial(Object
*obj
, Error
**errp
)
3330 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3332 return g_strdup(spapr
->host_serial
);
3335 static void spapr_set_host_serial(Object
*obj
, const char *value
, Error
**errp
)
3337 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3339 g_free(spapr
->host_serial
);
3340 spapr
->host_serial
= g_strdup(value
);
3343 static void spapr_instance_init(Object
*obj
)
3345 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3346 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
3348 spapr
->htab_fd
= -1;
3349 spapr
->use_hotplug_event_source
= true;
3350 object_property_add_str(obj
, "kvm-type",
3351 spapr_get_kvm_type
, spapr_set_kvm_type
, NULL
);
3352 object_property_set_description(obj
, "kvm-type",
3353 "Specifies the KVM virtualization mode (HV, PR)",
3355 object_property_add_bool(obj
, "modern-hotplug-events",
3356 spapr_get_modern_hotplug_events
,
3357 spapr_set_modern_hotplug_events
,
3359 object_property_set_description(obj
, "modern-hotplug-events",
3360 "Use dedicated hotplug event mechanism in"
3361 " place of standard EPOW events when possible"
3362 " (required for memory hot-unplug support)",
3364 ppc_compat_add_property(obj
, "max-cpu-compat", &spapr
->max_compat_pvr
,
3365 "Maximum permitted CPU compatibility mode",
3368 object_property_add_str(obj
, "resize-hpt",
3369 spapr_get_resize_hpt
, spapr_set_resize_hpt
, NULL
);
3370 object_property_set_description(obj
, "resize-hpt",
3371 "Resizing of the Hash Page Table (enabled, disabled, required)",
3373 object_property_add(obj
, "vsmt", "uint32", spapr_get_vsmt
,
3374 spapr_set_vsmt
, NULL
, &spapr
->vsmt
, &error_abort
);
3375 object_property_set_description(obj
, "vsmt",
3376 "Virtual SMT: KVM behaves as if this were"
3377 " the host's SMT mode", &error_abort
);
3378 object_property_add_bool(obj
, "vfio-no-msix-emulation",
3379 spapr_get_msix_emulation
, NULL
, NULL
);
3381 /* The machine class defines the default interrupt controller mode */
3382 spapr
->irq
= smc
->irq
;
3383 object_property_add_str(obj
, "ic-mode", spapr_get_ic_mode
,
3384 spapr_set_ic_mode
, NULL
);
3385 object_property_set_description(obj
, "ic-mode",
3386 "Specifies the interrupt controller mode (xics, xive, dual)",
3389 object_property_add_str(obj
, "host-model",
3390 spapr_get_host_model
, spapr_set_host_model
,
3392 object_property_set_description(obj
, "host-model",
3393 "Host model to advertise in guest device tree", &error_abort
);
3394 object_property_add_str(obj
, "host-serial",
3395 spapr_get_host_serial
, spapr_set_host_serial
,
3397 object_property_set_description(obj
, "host-serial",
3398 "Host serial number to advertise in guest device tree", &error_abort
);
3401 static void spapr_machine_finalizefn(Object
*obj
)
3403 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
3405 g_free(spapr
->kvm_type
);
3408 void spapr_do_system_reset_on_cpu(CPUState
*cs
, run_on_cpu_data arg
)
3410 cpu_synchronize_state(cs
);
3411 ppc_cpu_do_system_reset(cs
);
3414 static void spapr_nmi(NMIState
*n
, int cpu_index
, Error
**errp
)
3419 async_run_on_cpu(cs
, spapr_do_system_reset_on_cpu
, RUN_ON_CPU_NULL
);
3423 int spapr_lmb_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
3424 void *fdt
, int *fdt_start_offset
, Error
**errp
)
3429 addr
= spapr_drc_index(drc
) * SPAPR_MEMORY_BLOCK_SIZE
;
3430 node
= object_property_get_uint(OBJECT(drc
->dev
), PC_DIMM_NODE_PROP
,
3432 *fdt_start_offset
= spapr_populate_memory_node(fdt
, node
, addr
,
3433 SPAPR_MEMORY_BLOCK_SIZE
);
3437 static void spapr_add_lmbs(DeviceState
*dev
, uint64_t addr_start
, uint64_t size
,
3438 bool dedicated_hp_event_source
, Error
**errp
)
3441 uint32_t nr_lmbs
= size
/SPAPR_MEMORY_BLOCK_SIZE
;
3443 uint64_t addr
= addr_start
;
3444 bool hotplugged
= spapr_drc_hotplugged(dev
);
3445 Error
*local_err
= NULL
;
3447 for (i
= 0; i
< nr_lmbs
; i
++) {
3448 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3449 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3452 spapr_drc_attach(drc
, dev
, &local_err
);
3454 while (addr
> addr_start
) {
3455 addr
-= SPAPR_MEMORY_BLOCK_SIZE
;
3456 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3457 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3458 spapr_drc_detach(drc
);
3460 error_propagate(errp
, local_err
);
3464 spapr_drc_reset(drc
);
3466 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3468 /* send hotplug notification to the
3469 * guest only in case of hotplugged memory
3472 if (dedicated_hp_event_source
) {
3473 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3474 addr_start
/ SPAPR_MEMORY_BLOCK_SIZE
);
3475 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3477 spapr_drc_index(drc
));
3479 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3485 static void spapr_memory_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3488 Error
*local_err
= NULL
;
3489 SpaprMachineState
*ms
= SPAPR_MACHINE(hotplug_dev
);
3490 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3491 uint64_t size
, addr
;
3493 size
= memory_device_get_region_size(MEMORY_DEVICE(dev
), &error_abort
);
3495 pc_dimm_plug(dimm
, MACHINE(ms
), &local_err
);
3500 addr
= object_property_get_uint(OBJECT(dimm
),
3501 PC_DIMM_ADDR_PROP
, &local_err
);
3506 spapr_add_lmbs(dev
, addr
, size
, spapr_ovec_test(ms
->ov5_cas
, OV5_HP_EVT
),
3515 pc_dimm_unplug(dimm
, MACHINE(ms
));
3517 error_propagate(errp
, local_err
);
3520 static void spapr_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3523 const SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(hotplug_dev
);
3524 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3525 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3526 Error
*local_err
= NULL
;
3531 if (!smc
->dr_lmb_enabled
) {
3532 error_setg(errp
, "Memory hotplug not supported for this machine");
3536 size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
), &local_err
);
3538 error_propagate(errp
, local_err
);
3542 if (size
% SPAPR_MEMORY_BLOCK_SIZE
) {
3543 error_setg(errp
, "Hotplugged memory size must be a multiple of "
3544 "%" PRIu64
" MB", SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
3548 memdev
= object_property_get_link(OBJECT(dimm
), PC_DIMM_MEMDEV_PROP
,
3550 pagesize
= host_memory_backend_pagesize(MEMORY_BACKEND(memdev
));
3551 spapr_check_pagesize(spapr
, pagesize
, &local_err
);
3553 error_propagate(errp
, local_err
);
3557 pc_dimm_pre_plug(dimm
, MACHINE(hotplug_dev
), NULL
, errp
);
3560 struct SpaprDimmState
{
3563 QTAILQ_ENTRY(SpaprDimmState
) next
;
3566 static SpaprDimmState
*spapr_pending_dimm_unplugs_find(SpaprMachineState
*s
,
3569 SpaprDimmState
*dimm_state
= NULL
;
3571 QTAILQ_FOREACH(dimm_state
, &s
->pending_dimm_unplugs
, next
) {
3572 if (dimm_state
->dimm
== dimm
) {
3579 static SpaprDimmState
*spapr_pending_dimm_unplugs_add(SpaprMachineState
*spapr
,
3583 SpaprDimmState
*ds
= NULL
;
3586 * If this request is for a DIMM whose removal had failed earlier
3587 * (due to guest's refusal to remove the LMBs), we would have this
3588 * dimm already in the pending_dimm_unplugs list. In that
3589 * case don't add again.
3591 ds
= spapr_pending_dimm_unplugs_find(spapr
, dimm
);
3593 ds
= g_malloc0(sizeof(SpaprDimmState
));
3594 ds
->nr_lmbs
= nr_lmbs
;
3596 QTAILQ_INSERT_HEAD(&spapr
->pending_dimm_unplugs
, ds
, next
);
3601 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState
*spapr
,
3602 SpaprDimmState
*dimm_state
)
3604 QTAILQ_REMOVE(&spapr
->pending_dimm_unplugs
, dimm_state
, next
);
3608 static SpaprDimmState
*spapr_recover_pending_dimm_state(SpaprMachineState
*ms
,
3612 uint64_t size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
),
3614 uint32_t nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
3615 uint32_t avail_lmbs
= 0;
3616 uint64_t addr_start
, addr
;
3619 addr_start
= object_property_get_int(OBJECT(dimm
), PC_DIMM_ADDR_PROP
,
3623 for (i
= 0; i
< nr_lmbs
; i
++) {
3624 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3625 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3630 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3633 return spapr_pending_dimm_unplugs_add(ms
, avail_lmbs
, dimm
);
3636 /* Callback to be called during DRC release. */
3637 void spapr_lmb_release(DeviceState
*dev
)
3639 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
3640 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_ctrl
);
3641 SpaprDimmState
*ds
= spapr_pending_dimm_unplugs_find(spapr
, PC_DIMM(dev
));
3643 /* This information will get lost if a migration occurs
3644 * during the unplug process. In this case recover it. */
3646 ds
= spapr_recover_pending_dimm_state(spapr
, PC_DIMM(dev
));
3648 /* The DRC being examined by the caller at least must be counted */
3649 g_assert(ds
->nr_lmbs
);
3652 if (--ds
->nr_lmbs
) {
3657 * Now that all the LMBs have been removed by the guest, call the
3658 * unplug handler chain. This can never fail.
3660 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
3661 object_unparent(OBJECT(dev
));
3664 static void spapr_memory_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3666 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3667 SpaprDimmState
*ds
= spapr_pending_dimm_unplugs_find(spapr
, PC_DIMM(dev
));
3669 pc_dimm_unplug(PC_DIMM(dev
), MACHINE(hotplug_dev
));
3670 object_property_set_bool(OBJECT(dev
), false, "realized", NULL
);
3671 spapr_pending_dimm_unplugs_remove(spapr
, ds
);
3674 static void spapr_memory_unplug_request(HotplugHandler
*hotplug_dev
,
3675 DeviceState
*dev
, Error
**errp
)
3677 SpaprMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3678 Error
*local_err
= NULL
;
3679 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3681 uint64_t size
, addr_start
, addr
;
3685 size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
), &error_abort
);
3686 nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
3688 addr_start
= object_property_get_uint(OBJECT(dimm
), PC_DIMM_ADDR_PROP
,
3695 * An existing pending dimm state for this DIMM means that there is an
3696 * unplug operation in progress, waiting for the spapr_lmb_release
3697 * callback to complete the job (BQL can't cover that far). In this case,
3698 * bail out to avoid detaching DRCs that were already released.
3700 if (spapr_pending_dimm_unplugs_find(spapr
, dimm
)) {
3701 error_setg(&local_err
,
3702 "Memory unplug already in progress for device %s",
3707 spapr_pending_dimm_unplugs_add(spapr
, nr_lmbs
, dimm
);
3710 for (i
= 0; i
< nr_lmbs
; i
++) {
3711 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3712 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3715 spapr_drc_detach(drc
);
3716 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3719 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3720 addr_start
/ SPAPR_MEMORY_BLOCK_SIZE
);
3721 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3722 nr_lmbs
, spapr_drc_index(drc
));
3724 error_propagate(errp
, local_err
);
3727 /* Callback to be called during DRC release. */
3728 void spapr_core_release(DeviceState
*dev
)
3730 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
3732 /* Call the unplug handler chain. This can never fail. */
3733 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
3734 object_unparent(OBJECT(dev
));
3737 static void spapr_core_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3739 MachineState
*ms
= MACHINE(hotplug_dev
);
3740 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(ms
);
3741 CPUCore
*cc
= CPU_CORE(dev
);
3742 CPUArchId
*core_slot
= spapr_find_cpu_slot(ms
, cc
->core_id
, NULL
);
3744 if (smc
->pre_2_10_has_unused_icps
) {
3745 SpaprCpuCore
*sc
= SPAPR_CPU_CORE(OBJECT(dev
));
3748 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3749 CPUState
*cs
= CPU(sc
->threads
[i
]);
3751 pre_2_10_vmstate_register_dummy_icp(cs
->cpu_index
);
3756 core_slot
->cpu
= NULL
;
3757 object_property_set_bool(OBJECT(dev
), false, "realized", NULL
);
3761 void spapr_core_unplug_request(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3764 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3767 CPUCore
*cc
= CPU_CORE(dev
);
3769 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
)) {
3770 error_setg(errp
, "Unable to find CPU core with core-id: %d",
3775 error_setg(errp
, "Boot CPU core may not be unplugged");
3779 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
,
3780 spapr_vcpu_id(spapr
, cc
->core_id
));
3783 spapr_drc_detach(drc
);
3785 spapr_hotplug_req_remove_by_index(drc
);
3788 int spapr_core_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
3789 void *fdt
, int *fdt_start_offset
, Error
**errp
)
3791 SpaprCpuCore
*core
= SPAPR_CPU_CORE(drc
->dev
);
3792 CPUState
*cs
= CPU(core
->threads
[0]);
3793 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
3794 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
3795 int id
= spapr_get_vcpu_id(cpu
);
3799 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, id
);
3800 offset
= fdt_add_subnode(fdt
, 0, nodename
);
3803 spapr_populate_cpu_dt(cs
, fdt
, offset
, spapr
);
3805 *fdt_start_offset
= offset
;
3809 static void spapr_core_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3812 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3813 MachineClass
*mc
= MACHINE_GET_CLASS(spapr
);
3814 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
3815 SpaprCpuCore
*core
= SPAPR_CPU_CORE(OBJECT(dev
));
3816 CPUCore
*cc
= CPU_CORE(dev
);
3819 Error
*local_err
= NULL
;
3820 CPUArchId
*core_slot
;
3822 bool hotplugged
= spapr_drc_hotplugged(dev
);
3824 core_slot
= spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
);
3826 error_setg(errp
, "Unable to find CPU core with core-id: %d",
3830 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
,
3831 spapr_vcpu_id(spapr
, cc
->core_id
));
3833 g_assert(drc
|| !mc
->has_hotpluggable_cpus
);
3836 spapr_drc_attach(drc
, dev
, &local_err
);
3838 error_propagate(errp
, local_err
);
3844 * Send hotplug notification interrupt to the guest only
3845 * in case of hotplugged CPUs.
3847 spapr_hotplug_req_add_by_index(drc
);
3849 spapr_drc_reset(drc
);
3853 core_slot
->cpu
= OBJECT(dev
);
3855 if (smc
->pre_2_10_has_unused_icps
) {
3858 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3859 cs
= CPU(core
->threads
[i
]);
3860 pre_2_10_vmstate_unregister_dummy_icp(cs
->cpu_index
);
3865 static void spapr_core_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3868 MachineState
*machine
= MACHINE(OBJECT(hotplug_dev
));
3869 MachineClass
*mc
= MACHINE_GET_CLASS(hotplug_dev
);
3870 Error
*local_err
= NULL
;
3871 CPUCore
*cc
= CPU_CORE(dev
);
3872 const char *base_core_type
= spapr_get_cpu_core_type(machine
->cpu_type
);
3873 const char *type
= object_get_typename(OBJECT(dev
));
3874 CPUArchId
*core_slot
;
3876 unsigned int smp_threads
= machine
->smp
.threads
;
3878 if (dev
->hotplugged
&& !mc
->has_hotpluggable_cpus
) {
3879 error_setg(&local_err
, "CPU hotplug not supported for this machine");
3883 if (strcmp(base_core_type
, type
)) {
3884 error_setg(&local_err
, "CPU core type should be %s", base_core_type
);
3888 if (cc
->core_id
% smp_threads
) {
3889 error_setg(&local_err
, "invalid core id %d", cc
->core_id
);
3894 * In general we should have homogeneous threads-per-core, but old
3895 * (pre hotplug support) machine types allow the last core to have
3896 * reduced threads as a compatibility hack for when we allowed
3897 * total vcpus not a multiple of threads-per-core.
3899 if (mc
->has_hotpluggable_cpus
&& (cc
->nr_threads
!= smp_threads
)) {
3900 error_setg(&local_err
, "invalid nr-threads %d, must be %d",
3901 cc
->nr_threads
, smp_threads
);
3905 core_slot
= spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
);
3907 error_setg(&local_err
, "core id %d out of range", cc
->core_id
);
3911 if (core_slot
->cpu
) {
3912 error_setg(&local_err
, "core %d already populated", cc
->core_id
);
3916 numa_cpu_pre_plug(core_slot
, dev
, &local_err
);
3919 error_propagate(errp
, local_err
);
3922 int spapr_phb_dt_populate(SpaprDrc
*drc
, SpaprMachineState
*spapr
,
3923 void *fdt
, int *fdt_start_offset
, Error
**errp
)
3925 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(drc
->dev
);
3928 intc_phandle
= spapr_irq_get_phandle(spapr
, spapr
->fdt_blob
, errp
);
3929 if (intc_phandle
<= 0) {
3933 if (spapr_dt_phb(sphb
, intc_phandle
, fdt
, spapr
->irq
->nr_msis
,
3934 fdt_start_offset
)) {
3935 error_setg(errp
, "unable to create FDT node for PHB %d", sphb
->index
);
3939 /* generally SLOF creates these, for hotplug it's up to QEMU */
3940 _FDT(fdt_setprop_string(fdt
, *fdt_start_offset
, "name", "pci"));
3945 static void spapr_phb_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3948 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3949 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(dev
);
3950 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
3951 const unsigned windows_supported
= spapr_phb_windows_supported(sphb
);
3953 if (dev
->hotplugged
&& !smc
->dr_phb_enabled
) {
3954 error_setg(errp
, "PHB hotplug not supported for this machine");
3958 if (sphb
->index
== (uint32_t)-1) {
3959 error_setg(errp
, "\"index\" for PAPR PHB is mandatory");
3964 * This will check that sphb->index doesn't exceed the maximum number of
3965 * PHBs for the current machine type.
3967 smc
->phb_placement(spapr
, sphb
->index
,
3968 &sphb
->buid
, &sphb
->io_win_addr
,
3969 &sphb
->mem_win_addr
, &sphb
->mem64_win_addr
,
3970 windows_supported
, sphb
->dma_liobn
,
3971 &sphb
->nv2_gpa_win_addr
, &sphb
->nv2_atsd_win_addr
,
3975 static void spapr_phb_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3978 SpaprMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3979 SpaprMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
3980 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(dev
);
3982 bool hotplugged
= spapr_drc_hotplugged(dev
);
3983 Error
*local_err
= NULL
;
3985 if (!smc
->dr_phb_enabled
) {
3989 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_PHB
, sphb
->index
);
3990 /* hotplug hooks should check it's enabled before getting this far */
3993 spapr_drc_attach(drc
, DEVICE(dev
), &local_err
);
3995 error_propagate(errp
, local_err
);
4000 spapr_hotplug_req_add_by_index(drc
);
4002 spapr_drc_reset(drc
);
4006 void spapr_phb_release(DeviceState
*dev
)
4008 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
4010 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
4011 object_unparent(OBJECT(dev
));
4014 static void spapr_phb_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
4016 object_property_set_bool(OBJECT(dev
), false, "realized", NULL
);
4019 static void spapr_phb_unplug_request(HotplugHandler
*hotplug_dev
,
4020 DeviceState
*dev
, Error
**errp
)
4022 SpaprPhbState
*sphb
= SPAPR_PCI_HOST_BRIDGE(dev
);
4025 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_PHB
, sphb
->index
);
4028 if (!spapr_drc_unplug_requested(drc
)) {
4029 spapr_drc_detach(drc
);
4030 spapr_hotplug_req_remove_by_index(drc
);
4034 static void spapr_machine_device_plug(HotplugHandler
*hotplug_dev
,
4035 DeviceState
*dev
, Error
**errp
)
4037 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4038 spapr_memory_plug(hotplug_dev
, dev
, errp
);
4039 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4040 spapr_core_plug(hotplug_dev
, dev
, errp
);
4041 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4042 spapr_phb_plug(hotplug_dev
, dev
, errp
);
4046 static void spapr_machine_device_unplug(HotplugHandler
*hotplug_dev
,
4047 DeviceState
*dev
, Error
**errp
)
4049 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4050 spapr_memory_unplug(hotplug_dev
, dev
);
4051 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4052 spapr_core_unplug(hotplug_dev
, dev
);
4053 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4054 spapr_phb_unplug(hotplug_dev
, dev
);
4058 static void spapr_machine_device_unplug_request(HotplugHandler
*hotplug_dev
,
4059 DeviceState
*dev
, Error
**errp
)
4061 SpaprMachineState
*sms
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
4062 MachineClass
*mc
= MACHINE_GET_CLASS(sms
);
4063 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4065 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4066 if (spapr_ovec_test(sms
->ov5_cas
, OV5_HP_EVT
)) {
4067 spapr_memory_unplug_request(hotplug_dev
, dev
, errp
);
4069 /* NOTE: this means there is a window after guest reset, prior to
4070 * CAS negotiation, where unplug requests will fail due to the
4071 * capability not being detected yet. This is a bit different than
4072 * the case with PCI unplug, where the events will be queued and
4073 * eventually handled by the guest after boot
4075 error_setg(errp
, "Memory hot unplug not supported for this guest");
4077 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4078 if (!mc
->has_hotpluggable_cpus
) {
4079 error_setg(errp
, "CPU hot unplug not supported on this machine");
4082 spapr_core_unplug_request(hotplug_dev
, dev
, errp
);
4083 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4084 if (!smc
->dr_phb_enabled
) {
4085 error_setg(errp
, "PHB hot unplug not supported on this machine");
4088 spapr_phb_unplug_request(hotplug_dev
, dev
, errp
);
4092 static void spapr_machine_device_pre_plug(HotplugHandler
*hotplug_dev
,
4093 DeviceState
*dev
, Error
**errp
)
4095 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
4096 spapr_memory_pre_plug(hotplug_dev
, dev
, errp
);
4097 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
4098 spapr_core_pre_plug(hotplug_dev
, dev
, errp
);
4099 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4100 spapr_phb_pre_plug(hotplug_dev
, dev
, errp
);
4104 static HotplugHandler
*spapr_get_hotplug_handler(MachineState
*machine
,
4107 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
4108 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
) ||
4109 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
4110 return HOTPLUG_HANDLER(machine
);
4112 if (object_dynamic_cast(OBJECT(dev
), TYPE_PCI_DEVICE
)) {
4113 PCIDevice
*pcidev
= PCI_DEVICE(dev
);
4114 PCIBus
*root
= pci_device_root_bus(pcidev
);
4115 SpaprPhbState
*phb
=
4116 (SpaprPhbState
*)object_dynamic_cast(OBJECT(BUS(root
)->parent
),
4117 TYPE_SPAPR_PCI_HOST_BRIDGE
);
4120 return HOTPLUG_HANDLER(phb
);
4126 static CpuInstanceProperties
4127 spapr_cpu_index_to_props(MachineState
*machine
, unsigned cpu_index
)
4129 CPUArchId
*core_slot
;
4130 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
4132 /* make sure possible_cpu are intialized */
4133 mc
->possible_cpu_arch_ids(machine
);
4134 /* get CPU core slot containing thread that matches cpu_index */
4135 core_slot
= spapr_find_cpu_slot(machine
, cpu_index
, NULL
);
4137 return core_slot
->props
;
4140 static int64_t spapr_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
4142 return idx
/ ms
->smp
.cores
% nb_numa_nodes
;
4145 static const CPUArchIdList
*spapr_possible_cpu_arch_ids(MachineState
*machine
)
4148 unsigned int smp_threads
= machine
->smp
.threads
;
4149 unsigned int smp_cpus
= machine
->smp
.cpus
;
4150 const char *core_type
;
4151 int spapr_max_cores
= machine
->smp
.max_cpus
/ smp_threads
;
4152 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
4154 if (!mc
->has_hotpluggable_cpus
) {
4155 spapr_max_cores
= QEMU_ALIGN_UP(smp_cpus
, smp_threads
) / smp_threads
;
4157 if (machine
->possible_cpus
) {
4158 assert(machine
->possible_cpus
->len
== spapr_max_cores
);
4159 return machine
->possible_cpus
;
4162 core_type
= spapr_get_cpu_core_type(machine
->cpu_type
);
4164 error_report("Unable to find sPAPR CPU Core definition");
4168 machine
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
4169 sizeof(CPUArchId
) * spapr_max_cores
);
4170 machine
->possible_cpus
->len
= spapr_max_cores
;
4171 for (i
= 0; i
< machine
->possible_cpus
->len
; i
++) {
4172 int core_id
= i
* smp_threads
;
4174 machine
->possible_cpus
->cpus
[i
].type
= core_type
;
4175 machine
->possible_cpus
->cpus
[i
].vcpus_count
= smp_threads
;
4176 machine
->possible_cpus
->cpus
[i
].arch_id
= core_id
;
4177 machine
->possible_cpus
->cpus
[i
].props
.has_core_id
= true;
4178 machine
->possible_cpus
->cpus
[i
].props
.core_id
= core_id
;
4180 return machine
->possible_cpus
;
4183 static void spapr_phb_placement(SpaprMachineState
*spapr
, uint32_t index
,
4184 uint64_t *buid
, hwaddr
*pio
,
4185 hwaddr
*mmio32
, hwaddr
*mmio64
,
4186 unsigned n_dma
, uint32_t *liobns
,
4187 hwaddr
*nv2gpa
, hwaddr
*nv2atsd
, Error
**errp
)
4190 * New-style PHB window placement.
4192 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
4193 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
4196 * Some guest kernels can't work with MMIO windows above 1<<46
4197 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
4199 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
4200 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the
4201 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the
4202 * 1TiB 64-bit MMIO windows for each PHB.
4204 const uint64_t base_buid
= 0x800000020000000ULL
;
4207 /* Sanity check natural alignments */
4208 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE
% SPAPR_PCI_MEM64_WIN_SIZE
) != 0);
4209 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT
% SPAPR_PCI_MEM64_WIN_SIZE
) != 0);
4210 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE
% SPAPR_PCI_MEM32_WIN_SIZE
) != 0);
4211 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE
% SPAPR_PCI_IO_WIN_SIZE
) != 0);
4212 /* Sanity check bounds */
4213 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS
* SPAPR_PCI_IO_WIN_SIZE
) >
4214 SPAPR_PCI_MEM32_WIN_SIZE
);
4215 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS
* SPAPR_PCI_MEM32_WIN_SIZE
) >
4216 SPAPR_PCI_MEM64_WIN_SIZE
);
4218 if (index
>= SPAPR_MAX_PHBS
) {
4219 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %llu)",
4220 SPAPR_MAX_PHBS
- 1);
4224 *buid
= base_buid
+ index
;
4225 for (i
= 0; i
< n_dma
; ++i
) {
4226 liobns
[i
] = SPAPR_PCI_LIOBN(index
, i
);
4229 *pio
= SPAPR_PCI_BASE
+ index
* SPAPR_PCI_IO_WIN_SIZE
;
4230 *mmio32
= SPAPR_PCI_BASE
+ (index
+ 1) * SPAPR_PCI_MEM32_WIN_SIZE
;
4231 *mmio64
= SPAPR_PCI_BASE
+ (index
+ 1) * SPAPR_PCI_MEM64_WIN_SIZE
;
4233 *nv2gpa
= SPAPR_PCI_NV2RAM64_WIN_BASE
+ index
* SPAPR_PCI_NV2RAM64_WIN_SIZE
;
4234 *nv2atsd
= SPAPR_PCI_NV2ATSD_WIN_BASE
+ index
* SPAPR_PCI_NV2ATSD_WIN_SIZE
;
4237 static ICSState
*spapr_ics_get(XICSFabric
*dev
, int irq
)
4239 SpaprMachineState
*spapr
= SPAPR_MACHINE(dev
);
4241 return ics_valid_irq(spapr
->ics
, irq
) ? spapr
->ics
: NULL
;
4244 static void spapr_ics_resend(XICSFabric
*dev
)
4246 SpaprMachineState
*spapr
= SPAPR_MACHINE(dev
);
4248 ics_resend(spapr
->ics
);
4251 static ICPState
*spapr_icp_get(XICSFabric
*xi
, int vcpu_id
)
4253 PowerPCCPU
*cpu
= spapr_find_cpu(vcpu_id
);
4255 return cpu
? spapr_cpu_state(cpu
)->icp
: NULL
;
4258 static void spapr_pic_print_info(InterruptStatsProvider
*obj
,
4261 SpaprMachineState
*spapr
= SPAPR_MACHINE(obj
);
4263 spapr
->irq
->print_info(spapr
, mon
);
4266 int spapr_get_vcpu_id(PowerPCCPU
*cpu
)
4268 return cpu
->vcpu_id
;
4271 void spapr_set_vcpu_id(PowerPCCPU
*cpu
, int cpu_index
, Error
**errp
)
4273 SpaprMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
4274 MachineState
*ms
= MACHINE(spapr
);
4277 vcpu_id
= spapr_vcpu_id(spapr
, cpu_index
);
4279 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id
)) {
4280 error_setg(errp
, "Can't create CPU with id %d in KVM", vcpu_id
);
4281 error_append_hint(errp
, "Adjust the number of cpus to %d "
4282 "or try to raise the number of threads per core\n",
4283 vcpu_id
* ms
->smp
.threads
/ spapr
->vsmt
);
4287 cpu
->vcpu_id
= vcpu_id
;
4290 PowerPCCPU
*spapr_find_cpu(int vcpu_id
)
4295 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
4297 if (spapr_get_vcpu_id(cpu
) == vcpu_id
) {
4305 static void spapr_machine_class_init(ObjectClass
*oc
, void *data
)
4307 MachineClass
*mc
= MACHINE_CLASS(oc
);
4308 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(oc
);
4309 FWPathProviderClass
*fwc
= FW_PATH_PROVIDER_CLASS(oc
);
4310 NMIClass
*nc
= NMI_CLASS(oc
);
4311 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
4312 PPCVirtualHypervisorClass
*vhc
= PPC_VIRTUAL_HYPERVISOR_CLASS(oc
);
4313 XICSFabricClass
*xic
= XICS_FABRIC_CLASS(oc
);
4314 InterruptStatsProviderClass
*ispc
= INTERRUPT_STATS_PROVIDER_CLASS(oc
);
4316 mc
->desc
= "pSeries Logical Partition (PAPR compliant)";
4317 mc
->ignore_boot_device_suffixes
= true;
4320 * We set up the default / latest behaviour here. The class_init
4321 * functions for the specific versioned machine types can override
4322 * these details for backwards compatibility
4324 mc
->init
= spapr_machine_init
;
4325 mc
->reset
= spapr_machine_reset
;
4326 mc
->block_default_type
= IF_SCSI
;
4327 mc
->max_cpus
= 1024;
4328 mc
->no_parallel
= 1;
4329 mc
->default_boot_order
= "";
4330 mc
->default_ram_size
= 512 * MiB
;
4331 mc
->default_display
= "std";
4332 mc
->kvm_type
= spapr_kvm_type
;
4333 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
4334 mc
->pci_allow_0_address
= true;
4335 assert(!mc
->get_hotplug_handler
);
4336 mc
->get_hotplug_handler
= spapr_get_hotplug_handler
;
4337 hc
->pre_plug
= spapr_machine_device_pre_plug
;
4338 hc
->plug
= spapr_machine_device_plug
;
4339 mc
->cpu_index_to_instance_props
= spapr_cpu_index_to_props
;
4340 mc
->get_default_cpu_node_id
= spapr_get_default_cpu_node_id
;
4341 mc
->possible_cpu_arch_ids
= spapr_possible_cpu_arch_ids
;
4342 hc
->unplug_request
= spapr_machine_device_unplug_request
;
4343 hc
->unplug
= spapr_machine_device_unplug
;
4345 smc
->dr_lmb_enabled
= true;
4346 smc
->update_dt_enabled
= true;
4347 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power9_v2.0");
4348 mc
->has_hotpluggable_cpus
= true;
4349 smc
->resize_hpt_default
= SPAPR_RESIZE_HPT_ENABLED
;
4350 fwc
->get_dev_path
= spapr_get_fw_dev_path
;
4351 nc
->nmi_monitor_handler
= spapr_nmi
;
4352 smc
->phb_placement
= spapr_phb_placement
;
4353 vhc
->hypercall
= emulate_spapr_hypercall
;
4354 vhc
->hpt_mask
= spapr_hpt_mask
;
4355 vhc
->map_hptes
= spapr_map_hptes
;
4356 vhc
->unmap_hptes
= spapr_unmap_hptes
;
4357 vhc
->hpte_set_c
= spapr_hpte_set_c
;
4358 vhc
->hpte_set_r
= spapr_hpte_set_r
;
4359 vhc
->get_pate
= spapr_get_pate
;
4360 vhc
->encode_hpt_for_kvm_pr
= spapr_encode_hpt_for_kvm_pr
;
4361 xic
->ics_get
= spapr_ics_get
;
4362 xic
->ics_resend
= spapr_ics_resend
;
4363 xic
->icp_get
= spapr_icp_get
;
4364 ispc
->print_info
= spapr_pic_print_info
;
4365 /* Force NUMA node memory size to be a multiple of
4366 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity
4367 * in which LMBs are represented and hot-added
4369 mc
->numa_mem_align_shift
= 28;
4371 smc
->default_caps
.caps
[SPAPR_CAP_HTM
] = SPAPR_CAP_OFF
;
4372 smc
->default_caps
.caps
[SPAPR_CAP_VSX
] = SPAPR_CAP_ON
;
4373 smc
->default_caps
.caps
[SPAPR_CAP_DFP
] = SPAPR_CAP_ON
;
4374 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_WORKAROUND
;
4375 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_WORKAROUND
;
4376 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_WORKAROUND
;
4377 smc
->default_caps
.caps
[SPAPR_CAP_HPT_MAXPAGESIZE
] = 16; /* 64kiB */
4378 smc
->default_caps
.caps
[SPAPR_CAP_NESTED_KVM_HV
] = SPAPR_CAP_OFF
;
4379 smc
->default_caps
.caps
[SPAPR_CAP_LARGE_DECREMENTER
] = SPAPR_CAP_ON
;
4380 smc
->default_caps
.caps
[SPAPR_CAP_CCF_ASSIST
] = SPAPR_CAP_OFF
;
4381 spapr_caps_add_properties(smc
, &error_abort
);
4382 smc
->irq
= &spapr_irq_dual
;
4383 smc
->dr_phb_enabled
= true;
4386 static const TypeInfo spapr_machine_info
= {
4387 .name
= TYPE_SPAPR_MACHINE
,
4388 .parent
= TYPE_MACHINE
,
4390 .instance_size
= sizeof(SpaprMachineState
),
4391 .instance_init
= spapr_instance_init
,
4392 .instance_finalize
= spapr_machine_finalizefn
,
4393 .class_size
= sizeof(SpaprMachineClass
),
4394 .class_init
= spapr_machine_class_init
,
4395 .interfaces
= (InterfaceInfo
[]) {
4396 { TYPE_FW_PATH_PROVIDER
},
4398 { TYPE_HOTPLUG_HANDLER
},
4399 { TYPE_PPC_VIRTUAL_HYPERVISOR
},
4400 { TYPE_XICS_FABRIC
},
4401 { TYPE_INTERRUPT_STATS_PROVIDER
},
4406 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
4407 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
4410 MachineClass *mc = MACHINE_CLASS(oc); \
4411 spapr_machine_##suffix##_class_options(mc); \
4413 mc->alias = "pseries"; \
4414 mc->is_default = 1; \
4417 static const TypeInfo spapr_machine_##suffix##_info = { \
4418 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
4419 .parent = TYPE_SPAPR_MACHINE, \
4420 .class_init = spapr_machine_##suffix##_class_init, \
4422 static void spapr_machine_register_##suffix(void) \
4424 type_register(&spapr_machine_##suffix##_info); \
4426 type_init(spapr_machine_register_##suffix)
4431 static void spapr_machine_4_1_class_options(MachineClass
*mc
)
4433 /* Defaults for the latest behaviour inherited from the base class */
4436 DEFINE_SPAPR_MACHINE(4_1
, "4.1", true);
4441 static void phb_placement_4_0(SpaprMachineState
*spapr
, uint32_t index
,
4442 uint64_t *buid
, hwaddr
*pio
,
4443 hwaddr
*mmio32
, hwaddr
*mmio64
,
4444 unsigned n_dma
, uint32_t *liobns
,
4445 hwaddr
*nv2gpa
, hwaddr
*nv2atsd
, Error
**errp
)
4447 spapr_phb_placement(spapr
, index
, buid
, pio
, mmio32
, mmio64
, n_dma
, liobns
,
4448 nv2gpa
, nv2atsd
, errp
);
4453 static void spapr_machine_4_0_class_options(MachineClass
*mc
)
4455 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4457 spapr_machine_4_1_class_options(mc
);
4458 compat_props_add(mc
->compat_props
, hw_compat_4_0
, hw_compat_4_0_len
);
4459 smc
->phb_placement
= phb_placement_4_0
;
4460 smc
->irq
= &spapr_irq_xics
;
4461 smc
->pre_4_1_migration
= true;
4464 DEFINE_SPAPR_MACHINE(4_0
, "4.0", false);
4469 static void spapr_machine_3_1_class_options(MachineClass
*mc
)
4471 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4473 spapr_machine_4_0_class_options(mc
);
4474 compat_props_add(mc
->compat_props
, hw_compat_3_1
, hw_compat_3_1_len
);
4476 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power8_v2.0");
4477 smc
->update_dt_enabled
= false;
4478 smc
->dr_phb_enabled
= false;
4479 smc
->broken_host_serial_model
= true;
4480 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_BROKEN
;
4481 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_BROKEN
;
4482 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_BROKEN
;
4483 smc
->default_caps
.caps
[SPAPR_CAP_LARGE_DECREMENTER
] = SPAPR_CAP_OFF
;
4486 DEFINE_SPAPR_MACHINE(3_1
, "3.1", false);
4492 static void spapr_machine_3_0_class_options(MachineClass
*mc
)
4494 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4496 spapr_machine_3_1_class_options(mc
);
4497 compat_props_add(mc
->compat_props
, hw_compat_3_0
, hw_compat_3_0_len
);
4499 smc
->legacy_irq_allocation
= true;
4500 smc
->irq
= &spapr_irq_xics_legacy
;
4503 DEFINE_SPAPR_MACHINE(3_0
, "3.0", false);
4508 static void spapr_machine_2_12_class_options(MachineClass
*mc
)
4510 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4511 static GlobalProperty compat
[] = {
4512 { TYPE_POWERPC_CPU
, "pre-3.0-migration", "on" },
4513 { TYPE_SPAPR_CPU_CORE
, "pre-3.0-migration", "on" },
4516 spapr_machine_3_0_class_options(mc
);
4517 compat_props_add(mc
->compat_props
, hw_compat_2_12
, hw_compat_2_12_len
);
4518 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4520 /* We depend on kvm_enabled() to choose a default value for the
4521 * hpt-max-page-size capability. Of course we can't do it here
4522 * because this is too early and the HW accelerator isn't initialzed
4523 * yet. Postpone this to machine init (see default_caps_with_cpu()).
4525 smc
->default_caps
.caps
[SPAPR_CAP_HPT_MAXPAGESIZE
] = 0;
4528 DEFINE_SPAPR_MACHINE(2_12
, "2.12", false);
4530 static void spapr_machine_2_12_sxxm_class_options(MachineClass
*mc
)
4532 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4534 spapr_machine_2_12_class_options(mc
);
4535 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_WORKAROUND
;
4536 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_WORKAROUND
;
4537 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_FIXED_CCD
;
4540 DEFINE_SPAPR_MACHINE(2_12_sxxm
, "2.12-sxxm", false);
4546 static void spapr_machine_2_11_class_options(MachineClass
*mc
)
4548 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4550 spapr_machine_2_12_class_options(mc
);
4551 smc
->default_caps
.caps
[SPAPR_CAP_HTM
] = SPAPR_CAP_ON
;
4552 compat_props_add(mc
->compat_props
, hw_compat_2_11
, hw_compat_2_11_len
);
4555 DEFINE_SPAPR_MACHINE(2_11
, "2.11", false);
4561 static void spapr_machine_2_10_class_options(MachineClass
*mc
)
4563 spapr_machine_2_11_class_options(mc
);
4564 compat_props_add(mc
->compat_props
, hw_compat_2_10
, hw_compat_2_10_len
);
4567 DEFINE_SPAPR_MACHINE(2_10
, "2.10", false);
4573 static void spapr_machine_2_9_class_options(MachineClass
*mc
)
4575 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4576 static GlobalProperty compat
[] = {
4577 { TYPE_POWERPC_CPU
, "pre-2.10-migration", "on" },
4580 spapr_machine_2_10_class_options(mc
);
4581 compat_props_add(mc
->compat_props
, hw_compat_2_9
, hw_compat_2_9_len
);
4582 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4583 mc
->numa_auto_assign_ram
= numa_legacy_auto_assign_ram
;
4584 smc
->pre_2_10_has_unused_icps
= true;
4585 smc
->resize_hpt_default
= SPAPR_RESIZE_HPT_DISABLED
;
4588 DEFINE_SPAPR_MACHINE(2_9
, "2.9", false);
4594 static void spapr_machine_2_8_class_options(MachineClass
*mc
)
4596 static GlobalProperty compat
[] = {
4597 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pcie-extended-configuration-space", "off" },
4600 spapr_machine_2_9_class_options(mc
);
4601 compat_props_add(mc
->compat_props
, hw_compat_2_8
, hw_compat_2_8_len
);
4602 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4603 mc
->numa_mem_align_shift
= 23;
4606 DEFINE_SPAPR_MACHINE(2_8
, "2.8", false);
4612 static void phb_placement_2_7(SpaprMachineState
*spapr
, uint32_t index
,
4613 uint64_t *buid
, hwaddr
*pio
,
4614 hwaddr
*mmio32
, hwaddr
*mmio64
,
4615 unsigned n_dma
, uint32_t *liobns
,
4616 hwaddr
*nv2gpa
, hwaddr
*nv2atsd
, Error
**errp
)
4618 /* Legacy PHB placement for pseries-2.7 and earlier machine types */
4619 const uint64_t base_buid
= 0x800000020000000ULL
;
4620 const hwaddr phb_spacing
= 0x1000000000ULL
; /* 64 GiB */
4621 const hwaddr mmio_offset
= 0xa0000000; /* 2 GiB + 512 MiB */
4622 const hwaddr pio_offset
= 0x80000000; /* 2 GiB */
4623 const uint32_t max_index
= 255;
4624 const hwaddr phb0_alignment
= 0x10000000000ULL
; /* 1 TiB */
4626 uint64_t ram_top
= MACHINE(spapr
)->ram_size
;
4627 hwaddr phb0_base
, phb_base
;
4630 /* Do we have device memory? */
4631 if (MACHINE(spapr
)->maxram_size
> ram_top
) {
4632 /* Can't just use maxram_size, because there may be an
4633 * alignment gap between normal and device memory regions
4635 ram_top
= MACHINE(spapr
)->device_memory
->base
+
4636 memory_region_size(&MACHINE(spapr
)->device_memory
->mr
);
4639 phb0_base
= QEMU_ALIGN_UP(ram_top
, phb0_alignment
);
4641 if (index
> max_index
) {
4642 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %u)",
4647 *buid
= base_buid
+ index
;
4648 for (i
= 0; i
< n_dma
; ++i
) {
4649 liobns
[i
] = SPAPR_PCI_LIOBN(index
, i
);
4652 phb_base
= phb0_base
+ index
* phb_spacing
;
4653 *pio
= phb_base
+ pio_offset
;
4654 *mmio32
= phb_base
+ mmio_offset
;
4656 * We don't set the 64-bit MMIO window, relying on the PHB's
4657 * fallback behaviour of automatically splitting a large "32-bit"
4658 * window into contiguous 32-bit and 64-bit windows
4665 static void spapr_machine_2_7_class_options(MachineClass
*mc
)
4667 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4668 static GlobalProperty compat
[] = {
4669 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem_win_size", "0xf80000000", },
4670 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem64_win_size", "0", },
4671 { TYPE_POWERPC_CPU
, "pre-2.8-migration", "on", },
4672 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "pre-2.8-migration", "on", },
4675 spapr_machine_2_8_class_options(mc
);
4676 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power7_v2.3");
4677 mc
->default_machine_opts
= "modern-hotplug-events=off";
4678 compat_props_add(mc
->compat_props
, hw_compat_2_7
, hw_compat_2_7_len
);
4679 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4680 smc
->phb_placement
= phb_placement_2_7
;
4683 DEFINE_SPAPR_MACHINE(2_7
, "2.7", false);
4689 static void spapr_machine_2_6_class_options(MachineClass
*mc
)
4691 static GlobalProperty compat
[] = {
4692 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "ddw", "off" },
4695 spapr_machine_2_7_class_options(mc
);
4696 mc
->has_hotpluggable_cpus
= false;
4697 compat_props_add(mc
->compat_props
, hw_compat_2_6
, hw_compat_2_6_len
);
4698 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4701 DEFINE_SPAPR_MACHINE(2_6
, "2.6", false);
4707 static void spapr_machine_2_5_class_options(MachineClass
*mc
)
4709 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4710 static GlobalProperty compat
[] = {
4711 { "spapr-vlan", "use-rx-buffer-pools", "off" },
4714 spapr_machine_2_6_class_options(mc
);
4715 smc
->use_ohci_by_default
= true;
4716 compat_props_add(mc
->compat_props
, hw_compat_2_5
, hw_compat_2_5_len
);
4717 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4720 DEFINE_SPAPR_MACHINE(2_5
, "2.5", false);
4726 static void spapr_machine_2_4_class_options(MachineClass
*mc
)
4728 SpaprMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4730 spapr_machine_2_5_class_options(mc
);
4731 smc
->dr_lmb_enabled
= false;
4732 compat_props_add(mc
->compat_props
, hw_compat_2_4
, hw_compat_2_4_len
);
4735 DEFINE_SPAPR_MACHINE(2_4
, "2.4", false);
4741 static void spapr_machine_2_3_class_options(MachineClass
*mc
)
4743 static GlobalProperty compat
[] = {
4744 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" },
4746 spapr_machine_2_4_class_options(mc
);
4747 compat_props_add(mc
->compat_props
, hw_compat_2_3
, hw_compat_2_3_len
);
4748 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4750 DEFINE_SPAPR_MACHINE(2_3
, "2.3", false);
4756 static void spapr_machine_2_2_class_options(MachineClass
*mc
)
4758 static GlobalProperty compat
[] = {
4759 { TYPE_SPAPR_PCI_HOST_BRIDGE
, "mem_win_size", "0x20000000" },
4762 spapr_machine_2_3_class_options(mc
);
4763 compat_props_add(mc
->compat_props
, hw_compat_2_2
, hw_compat_2_2_len
);
4764 compat_props_add(mc
->compat_props
, compat
, G_N_ELEMENTS(compat
));
4765 mc
->default_machine_opts
= "modern-hotplug-events=off,suppress-vmdesc=on";
4767 DEFINE_SPAPR_MACHINE(2_2
, "2.2", false);
4773 static void spapr_machine_2_1_class_options(MachineClass
*mc
)
4775 spapr_machine_2_2_class_options(mc
);
4776 compat_props_add(mc
->compat_props
, hw_compat_2_1
, hw_compat_2_1_len
);
4778 DEFINE_SPAPR_MACHINE(2_1
, "2.1", false);
4780 static void spapr_machine_register_types(void)
4782 type_register_static(&spapr_machine_info
);
4785 type_init(spapr_machine_register_types
)