hw/ppc_oldworld.c

   1
   2 /*
   3  * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator
   4  *
   5  * Copyright (c) 2004-2007 Fabrice Bellard
   6  * Copyright (c) 2007 Jocelyn Mayer
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26 #include "hw.h"
  27 #include "ppc.h"
  28 #include "ppc_mac.h"
  29 #include "adb.h"
  30 #include "mac_dbdma.h"
  31 #include "nvram.h"
  32 #include "sysemu.h"
  33 #include "net.h"
  34 #include "isa.h"
  35 #include "pci.h"
  36 #include "boards.h"
  37 #include "fw_cfg.h"
  38 #include "escc.h"
  39 #include "ide.h"
  40 #include "loader.h"
  41 #include "elf.h"
  42 #include "kvm.h"
  43 #include "kvm_ppc.h"
  44 #include "blockdev.h"
  45 #include "exec-memory.h"
  46
  47 #define MAX_IDE_BUS 2
  48 #define CFG_ADDR 0xf0000510
  49
  50 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
  51 {
  52     fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
  53     return 0;
  54 }
  55
  56
  57 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
  58 {
  59     return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
  60 }
  61
  62 static target_phys_addr_t round_page(target_phys_addr_t addr)
  63 {
  64     return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
  65 }
  66
  67 static void ppc_heathrow_reset(void *opaque)
  68 {
  69     PowerPCCPU *cpu = opaque;
  70
  71     cpu_reset(CPU(cpu));
  72 }
  73
  74 static void ppc_heathrow_init(QEMUMachineInitArgs *args)
  75 {
  76     ram_addr_t ram_size = args->ram_size;
  77     const char *cpu_model = args->cpu_model;
  78     const char *kernel_filename = args->kernel_filename;
  79     const char *kernel_cmdline = args->kernel_cmdline;
  80     const char *initrd_filename = args->initrd_filename;
  81     const char *boot_device = args->boot_device;
  82     MemoryRegion *sysmem = get_system_memory();
  83     PowerPCCPU *cpu = NULL;
  84     CPUPPCState *env = NULL;
  85     char *filename;
  86     qemu_irq *pic, **heathrow_irqs;
  87     int linux_boot, i;
  88     MemoryRegion *ram = g_new(MemoryRegion, 1);
  89     MemoryRegion *bios = g_new(MemoryRegion, 1);
  90     uint32_t kernel_base, initrd_base, cmdline_base = 0;
  91     int32_t kernel_size, initrd_size;
  92     PCIBus *pci_bus;
  93     MacIONVRAMState *nvr;
  94     int bios_size;
  95     MemoryRegion *pic_mem, *dbdma_mem, *cuda_mem;
  96     MemoryRegion *escc_mem, *escc_bar = g_new(MemoryRegion, 1), *ide_mem[2];
  97     uint16_t ppc_boot_device;
  98     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
  99     void *fw_cfg;
 100     void *dbdma;
 101
 102     linux_boot = (kernel_filename != NULL);
 103
 104     /* init CPUs */
 105     if (cpu_model == NULL)
 106         cpu_model = "G3";
 107     for (i = 0; i < smp_cpus; i++) {
 108         cpu = cpu_ppc_init(cpu_model);
 109         if (cpu == NULL) {
 110             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 111             exit(1);
 112         }
 113         env = &cpu->env;
 114
 115         /* Set time-base frequency to 16.6 Mhz */
 116         cpu_ppc_tb_init(env,  16600000UL);
 117         qemu_register_reset(ppc_heathrow_reset, cpu);
 118     }
 119
 120     /* allocate RAM */
 121     if (ram_size > (2047 << 20)) {
 122         fprintf(stderr,
 123                 "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n",
 124                 ((unsigned int)ram_size / (1 << 20)));
 125         exit(1);
 126     }
 127
 128     memory_region_init_ram(ram, "ppc_heathrow.ram", ram_size);
 129     vmstate_register_ram_global(ram);
 130     memory_region_add_subregion(sysmem, 0, ram);
 131
 132     /* allocate and load BIOS */
 133     memory_region_init_ram(bios, "ppc_heathrow.bios", BIOS_SIZE);
 134     vmstate_register_ram_global(bios);
 135     if (bios_name == NULL)
 136         bios_name = PROM_FILENAME;
 137     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 138     memory_region_set_readonly(bios, true);
 139     memory_region_add_subregion(sysmem, PROM_ADDR, bios);
 140
 141     /* Load OpenBIOS (ELF) */
 142     if (filename) {
 143         bios_size = load_elf(filename, 0, NULL, NULL, NULL, NULL,
 144                              1, ELF_MACHINE, 0);
 145         g_free(filename);
 146     } else {
 147         bios_size = -1;
 148     }
 149     if (bios_size < 0 || bios_size > BIOS_SIZE) {
 150         hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name);
 151         exit(1);
 152     }
 153
 154     if (linux_boot) {
 155         uint64_t lowaddr = 0;
 156         int bswap_needed;
 157
 158 #ifdef BSWAP_NEEDED
 159         bswap_needed = 1;
 160 #else
 161         bswap_needed = 0;
 162 #endif
 163         kernel_base = KERNEL_LOAD_ADDR;
 164         kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
 165                                NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0);
 166         if (kernel_size < 0)
 167             kernel_size = load_aout(kernel_filename, kernel_base,
 168                                     ram_size - kernel_base, bswap_needed,
 169                                     TARGET_PAGE_SIZE);
 170         if (kernel_size < 0)
 171             kernel_size = load_image_targphys(kernel_filename,
 172                                               kernel_base,
 173                                               ram_size - kernel_base);
 174         if (kernel_size < 0) {
 175             hw_error("qemu: could not load kernel '%s'\n",
 176                       kernel_filename);
 177             exit(1);
 178         }
 179         /* load initrd */
 180         if (initrd_filename) {
 181             initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
 182             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 183                                               ram_size - initrd_base);
 184             if (initrd_size < 0) {
 185                 hw_error("qemu: could not load initial ram disk '%s'\n",
 186                          initrd_filename);
 187                 exit(1);
 188             }
 189             cmdline_base = round_page(initrd_base + initrd_size);
 190         } else {
 191             initrd_base = 0;
 192             initrd_size = 0;
 193             cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
 194         }
 195         ppc_boot_device = 'm';
 196     } else {
 197         kernel_base = 0;
 198         kernel_size = 0;
 199         initrd_base = 0;
 200         initrd_size = 0;
 201         ppc_boot_device = '\0';
 202         for (i = 0; boot_device[i] != '\0'; i++) {
 203             /* TOFIX: for now, the second IDE channel is not properly
 204              *        used by OHW. The Mac floppy disk are not emulated.
 205              *        For now, OHW cannot boot from the network.
 206              */
 207 #if 0
 208             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 209                 ppc_boot_device = boot_device[i];
 210                 break;
 211             }
 212 #else
 213             if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
 214                 ppc_boot_device = boot_device[i];
 215                 break;
 216             }
 217 #endif
 218         }
 219         if (ppc_boot_device == '\0') {
 220             fprintf(stderr, "No valid boot device for G3 Beige machine\n");
 221             exit(1);
 222         }
 223     }
 224
 225     /* Register 2 MB of ISA IO space */
 226     isa_mmio_init(0xfe000000, 0x00200000);
 227
 228     /* XXX: we register only 1 output pin for heathrow PIC */
 229     heathrow_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
 230     heathrow_irqs[0] =
 231         g_malloc0(smp_cpus * sizeof(qemu_irq) * 1);
 232     /* Connect the heathrow PIC outputs to the 6xx bus */
 233     for (i = 0; i < smp_cpus; i++) {
 234         switch (PPC_INPUT(env)) {
 235         case PPC_FLAGS_INPUT_6xx:
 236             heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
 237             heathrow_irqs[i][0] =
 238                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
 239             break;
 240         default:
 241             hw_error("Bus model not supported on OldWorld Mac machine\n");
 242         }
 243     }
 244
 245     /* init basic PC hardware */
 246     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 247         hw_error("Only 6xx bus is supported on heathrow machine\n");
 248     }
 249     pic = heathrow_pic_init(&pic_mem, 1, heathrow_irqs);
 250     pci_bus = pci_grackle_init(0xfec00000, pic,
 251                                get_system_memory(),
 252                                get_system_io());
 253     pci_vga_init(pci_bus);
 254
 255     escc_mem = escc_init(0, pic[0x0f], pic[0x10], serial_hds[0],
 256                                serial_hds[1], ESCC_CLOCK, 4);
 257     memory_region_init_alias(escc_bar, "escc-bar",
 258                              escc_mem, 0, memory_region_size(escc_mem));
 259
 260     for(i = 0; i < nb_nics; i++)
 261         pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
 262
 263
 264     ide_drive_get(hd, MAX_IDE_BUS);
 265
 266     /* First IDE channel is a MAC IDE on the MacIO bus */
 267     dbdma = DBDMA_init(&dbdma_mem);
 268     ide_mem[0] = NULL;
 269     ide_mem[1] = pmac_ide_init(hd, pic[0x0D], dbdma, 0x16, pic[0x02]);
 270
 271     /* Second IDE channel is a CMD646 on the PCI bus */
 272     hd[0] = hd[MAX_IDE_DEVS];
 273     hd[1] = hd[MAX_IDE_DEVS + 1];
 274     hd[3] = hd[2] = NULL;
 275     pci_cmd646_ide_init(pci_bus, hd, 0);
 276
 277     /* cuda also initialize ADB */
 278     cuda_init(&cuda_mem, pic[0x12]);
 279
 280     adb_kbd_init(&adb_bus);
 281     adb_mouse_init(&adb_bus);
 282
 283     nvr = macio_nvram_init(0x2000, 4);
 284     pmac_format_nvram_partition(nvr, 0x2000);
 285
 286     macio_init(pci_bus, PCI_DEVICE_ID_APPLE_343S1201, 1, pic_mem,
 287                dbdma_mem, cuda_mem, nvr, 2, ide_mem, escc_bar);
 288
 289     if (usb_enabled) {
 290         pci_create_simple(pci_bus, -1, "pci-ohci");
 291     }
 292
 293     if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
 294         graphic_depth = 15;
 295
 296     /* No PCI init: the BIOS will do it */
 297
 298     fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
 299     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 300     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 301     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
 302     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
 303     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 304     if (kernel_cmdline) {
 305         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
 306         pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline);
 307     } else {
 308         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
 309     }
 310     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
 311     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 312     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
 313
 314     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
 315     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
 316     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
 317
 318     fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
 319     if (kvm_enabled()) {
 320 #ifdef CONFIG_KVM
 321         uint8_t *hypercall;
 322
 323         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq());
 324         hypercall = g_malloc(16);
 325         kvmppc_get_hypercall(env, hypercall, 16);
 326         fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
 327         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
 328 #endif
 329     } else {
 330         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, get_ticks_per_sec());
 331     }
 332
 333     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 334 }
 335
 336 static QEMUMachine heathrow_machine = {
 337     .name = "g3beige",
 338     .desc = "Heathrow based PowerMAC",
 339     .init = ppc_heathrow_init,
 340     .max_cpus = MAX_CPUS,
 341 #ifndef TARGET_PPC64
 342     .is_default = 1,
 343 #endif
 344 };
 345
 346 static void heathrow_machine_init(void)
 347 {
 348     qemu_register_machine(&heathrow_machine);
 349 }
 350
 351 machine_init(heathrow_machine_init);