hw/remote/proxy.c

   1 /*
   2  * Copyright © 2018, 2021 Oracle and/or its affiliates.
   3  *
   4  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   5  * See the COPYING file in the top-level directory.
   6  *
   7  */
   8
   9 #include "qemu/osdep.h"
  10
  11 #include "hw/remote/proxy.h"
  12 #include "hw/pci/pci.h"
  13 #include "qapi/error.h"
  14 #include "io/channel-util.h"
  15 #include "hw/qdev-properties.h"
  16 #include "monitor/monitor.h"
  17 #include "migration/blocker.h"
  18 #include "qemu/sockets.h"
  19 #include "hw/remote/mpqemu-link.h"
  20 #include "qemu/error-report.h"
  21 #include "hw/remote/proxy-memory-listener.h"
  22 #include "qom/object.h"
  23 #include "qemu/event_notifier.h"
  24 #include "sysemu/kvm.h"
  25
  26 static void probe_pci_info(PCIDevice *dev, Error **errp);
  27 static void proxy_device_reset(DeviceState *dev);
  28
  29 static void proxy_intx_update(PCIDevice *pci_dev)
  30 {
  31     PCIProxyDev *dev = PCI_PROXY_DEV(pci_dev);
  32     PCIINTxRoute route;
  33     int pin = pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
  34
  35     if (dev->virq != -1) {
  36         kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, &dev->intr, dev->virq);
  37         dev->virq = -1;
  38     }
  39
  40     route = pci_device_route_intx_to_irq(pci_dev, pin);
  41
  42     dev->virq = route.irq;
  43
  44     if (dev->virq != -1) {
  45         kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, &dev->intr,
  46                                            &dev->resample, dev->virq);
  47     }
  48 }
  49
  50 static void setup_irqfd(PCIProxyDev *dev)
  51 {
  52     PCIDevice *pci_dev = PCI_DEVICE(dev);
  53     MPQemuMsg msg;
  54     Error *local_err = NULL;
  55
  56     event_notifier_init(&dev->intr, 0);
  57     event_notifier_init(&dev->resample, 0);
  58
  59     memset(&msg, 0, sizeof(MPQemuMsg));
  60     msg.cmd = MPQEMU_CMD_SET_IRQFD;
  61     msg.num_fds = 2;
  62     msg.fds[0] = event_notifier_get_fd(&dev->intr);
  63     msg.fds[1] = event_notifier_get_fd(&dev->resample);
  64     msg.size = 0;
  65
  66     if (!mpqemu_msg_send(&msg, dev->ioc, &local_err)) {
  67         error_report_err(local_err);
  68     }
  69
  70     dev->virq = -1;
  71
  72     proxy_intx_update(pci_dev);
  73
  74     pci_device_set_intx_routing_notifier(pci_dev, proxy_intx_update);
  75 }
  76
  77 static void pci_proxy_dev_realize(PCIDevice *device, Error **errp)
  78 {
  79     ERRP_GUARD();
  80     PCIProxyDev *dev = PCI_PROXY_DEV(device);
  81     uint8_t *pci_conf = device->config;
  82     int fd;
  83
  84     if (!dev->fd) {
  85         error_setg(errp, "fd parameter not specified for %s",
  86                    DEVICE(device)->id);
  87         return;
  88     }
  89
  90     fd = monitor_fd_param(monitor_cur(), dev->fd, errp);
  91     if (fd == -1) {
  92         error_prepend(errp, "proxy: unable to parse fd %s: ", dev->fd);
  93         return;
  94     }
  95
  96     if (!fd_is_socket(fd)) {
  97         error_setg(errp, "proxy: fd %d is not a socket", fd);
  98         close(fd);
  99         return;
 100     }
 101
 102     dev->ioc = qio_channel_new_fd(fd, errp);
 103     if (!dev->ioc) {
 104         close(fd);
 105         return;
 106     }
 107
 108     error_setg(&dev->migration_blocker, "%s does not support migration",
 109                TYPE_PCI_PROXY_DEV);
 110     if (migrate_add_blocker(dev->migration_blocker, errp) < 0) {
 111         error_free(dev->migration_blocker);
 112         object_unref(dev->ioc);
 113         return;
 114     }
 115
 116     qemu_mutex_init(&dev->io_mutex);
 117     qio_channel_set_blocking(dev->ioc, true, NULL);
 118
 119     pci_conf[PCI_LATENCY_TIMER] = 0xff;
 120     pci_conf[PCI_INTERRUPT_PIN] = 0x01;
 121
 122     proxy_memory_listener_configure(&dev->proxy_listener, dev->ioc);
 123
 124     setup_irqfd(dev);
 125
 126     probe_pci_info(PCI_DEVICE(dev), errp);
 127 }
 128
 129 static void pci_proxy_dev_exit(PCIDevice *pdev)
 130 {
 131     PCIProxyDev *dev = PCI_PROXY_DEV(pdev);
 132
 133     if (dev->ioc) {
 134         qio_channel_close(dev->ioc, NULL);
 135     }
 136
 137     migrate_del_blocker(dev->migration_blocker);
 138
 139     error_free(dev->migration_blocker);
 140
 141     proxy_memory_listener_deconfigure(&dev->proxy_listener);
 142
 143     event_notifier_cleanup(&dev->intr);
 144     event_notifier_cleanup(&dev->resample);
 145 }
 146
 147 static void config_op_send(PCIProxyDev *pdev, uint32_t addr, uint32_t *val,
 148                            int len, unsigned int op)
 149 {
 150     MPQemuMsg msg = { 0 };
 151     uint64_t ret = -EINVAL;
 152     Error *local_err = NULL;
 153
 154     msg.cmd = op;
 155     msg.data.pci_conf_data.addr = addr;
 156     msg.data.pci_conf_data.val = (op == MPQEMU_CMD_PCI_CFGWRITE) ? *val : 0;
 157     msg.data.pci_conf_data.len = len;
 158     msg.size = sizeof(PciConfDataMsg);
 159
 160     ret = mpqemu_msg_send_and_await_reply(&msg, pdev, &local_err);
 161     if (local_err) {
 162         error_report_err(local_err);
 163     }
 164
 165     if (ret == UINT64_MAX) {
 166         error_report("Failed to perform PCI config %s operation",
 167                      (op == MPQEMU_CMD_PCI_CFGREAD) ? "READ" : "WRITE");
 168     }
 169
 170     if (op == MPQEMU_CMD_PCI_CFGREAD) {
 171         *val = (uint32_t)ret;
 172     }
 173 }
 174
 175 static uint32_t pci_proxy_read_config(PCIDevice *d, uint32_t addr, int len)
 176 {
 177     uint32_t val;
 178
 179     config_op_send(PCI_PROXY_DEV(d), addr, &val, len, MPQEMU_CMD_PCI_CFGREAD);
 180
 181     return val;
 182 }
 183
 184 static void pci_proxy_write_config(PCIDevice *d, uint32_t addr, uint32_t val,
 185                                    int len)
 186 {
 187     /*
 188      * Some of the functions access the copy of remote device's PCI config
 189      * space which is cached in the proxy device. Therefore, maintain
 190      * it updated.
 191      */
 192     pci_default_write_config(d, addr, val, len);
 193
 194     config_op_send(PCI_PROXY_DEV(d), addr, &val, len, MPQEMU_CMD_PCI_CFGWRITE);
 195 }
 196
 197 static Property proxy_properties[] = {
 198     DEFINE_PROP_STRING("fd", PCIProxyDev, fd),
 199     DEFINE_PROP_END_OF_LIST(),
 200 };
 201
 202 static void pci_proxy_dev_class_init(ObjectClass *klass, void *data)
 203 {
 204     DeviceClass *dc = DEVICE_CLASS(klass);
 205     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 206
 207     k->realize = pci_proxy_dev_realize;
 208     k->exit = pci_proxy_dev_exit;
 209     k->config_read = pci_proxy_read_config;
 210     k->config_write = pci_proxy_write_config;
 211
 212     dc->reset = proxy_device_reset;
 213
 214     device_class_set_props(dc, proxy_properties);
 215 }
 216
 217 static const TypeInfo pci_proxy_dev_type_info = {
 218     .name          = TYPE_PCI_PROXY_DEV,
 219     .parent        = TYPE_PCI_DEVICE,
 220     .instance_size = sizeof(PCIProxyDev),
 221     .class_init    = pci_proxy_dev_class_init,
 222     .interfaces = (InterfaceInfo[]) {
 223         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 224         { },
 225     },
 226 };
 227
 228 static void pci_proxy_dev_register_types(void)
 229 {
 230     type_register_static(&pci_proxy_dev_type_info);
 231 }
 232
 233 type_init(pci_proxy_dev_register_types)
 234
 235 static void send_bar_access_msg(PCIProxyDev *pdev, MemoryRegion *mr,
 236                                 bool write, hwaddr addr, uint64_t *val,
 237                                 unsigned size, bool memory)
 238 {
 239     MPQemuMsg msg = { 0 };
 240     long ret = -EINVAL;
 241     Error *local_err = NULL;
 242
 243     msg.size = sizeof(BarAccessMsg);
 244     msg.data.bar_access.addr = mr->addr + addr;
 245     msg.data.bar_access.size = size;
 246     msg.data.bar_access.memory = memory;
 247
 248     if (write) {
 249         msg.cmd = MPQEMU_CMD_BAR_WRITE;
 250         msg.data.bar_access.val = *val;
 251     } else {
 252         msg.cmd = MPQEMU_CMD_BAR_READ;
 253     }
 254
 255     ret = mpqemu_msg_send_and_await_reply(&msg, pdev, &local_err);
 256     if (local_err) {
 257         error_report_err(local_err);
 258     }
 259
 260     if (!write) {
 261         *val = ret;
 262     }
 263 }
 264
 265 static void proxy_bar_write(void *opaque, hwaddr addr, uint64_t val,
 266                             unsigned size)
 267 {
 268     ProxyMemoryRegion *pmr = opaque;
 269
 270     send_bar_access_msg(pmr->dev, &pmr->mr, true, addr, &val, size,
 271                         pmr->memory);
 272 }
 273
 274 static uint64_t proxy_bar_read(void *opaque, hwaddr addr, unsigned size)
 275 {
 276     ProxyMemoryRegion *pmr = opaque;
 277     uint64_t val;
 278
 279     send_bar_access_msg(pmr->dev, &pmr->mr, false, addr, &val, size,
 280                         pmr->memory);
 281
 282     return val;
 283 }
 284
 285 const MemoryRegionOps proxy_mr_ops = {
 286     .read = proxy_bar_read,
 287     .write = proxy_bar_write,
 288     .endianness = DEVICE_NATIVE_ENDIAN,
 289     .impl = {
 290         .min_access_size = 1,
 291         .max_access_size = 8,
 292     },
 293 };
 294
 295 static void probe_pci_info(PCIDevice *dev, Error **errp)
 296 {
 297     PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
 298     uint32_t orig_val, new_val, base_class, val;
 299     PCIProxyDev *pdev = PCI_PROXY_DEV(dev);
 300     DeviceClass *dc = DEVICE_CLASS(pc);
 301     uint8_t type;
 302     int i, size;
 303
 304     config_op_send(pdev, PCI_VENDOR_ID, &val, 2, MPQEMU_CMD_PCI_CFGREAD);
 305     pc->vendor_id = (uint16_t)val;
 306
 307     config_op_send(pdev, PCI_DEVICE_ID, &val, 2, MPQEMU_CMD_PCI_CFGREAD);
 308     pc->device_id = (uint16_t)val;
 309
 310     config_op_send(pdev, PCI_CLASS_DEVICE, &val, 2, MPQEMU_CMD_PCI_CFGREAD);
 311     pc->class_id = (uint16_t)val;
 312
 313     config_op_send(pdev, PCI_SUBSYSTEM_ID, &val, 2, MPQEMU_CMD_PCI_CFGREAD);
 314     pc->subsystem_id = (uint16_t)val;
 315
 316     base_class = pc->class_id >> 4;
 317     switch (base_class) {
 318     case PCI_BASE_CLASS_BRIDGE:
 319         set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 320         break;
 321     case PCI_BASE_CLASS_STORAGE:
 322         set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 323         break;
 324     case PCI_BASE_CLASS_NETWORK:
 325     case PCI_BASE_CLASS_WIRELESS:
 326         set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
 327         break;
 328     case PCI_BASE_CLASS_INPUT:
 329         set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
 330         break;
 331     case PCI_BASE_CLASS_DISPLAY:
 332         set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
 333         break;
 334     case PCI_BASE_CLASS_PROCESSOR:
 335         set_bit(DEVICE_CATEGORY_CPU, dc->categories);
 336         break;
 337     default:
 338         set_bit(DEVICE_CATEGORY_MISC, dc->categories);
 339         break;
 340     }
 341
 342     for (i = 0; i < PCI_NUM_REGIONS; i++) {
 343         config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &orig_val, 4,
 344                        MPQEMU_CMD_PCI_CFGREAD);
 345         new_val = 0xffffffff;
 346         config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &new_val, 4,
 347                        MPQEMU_CMD_PCI_CFGWRITE);
 348         config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &new_val, 4,
 349                        MPQEMU_CMD_PCI_CFGREAD);
 350         size = (~(new_val & 0xFFFFFFF0)) + 1;
 351         config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &orig_val, 4,
 352                        MPQEMU_CMD_PCI_CFGWRITE);
 353         type = (new_val & 0x1) ?
 354                    PCI_BASE_ADDRESS_SPACE_IO : PCI_BASE_ADDRESS_SPACE_MEMORY;
 355
 356         if (size) {
 357             g_autofree char *name = g_strdup_printf("bar-region-%d", i);
 358             pdev->region[i].dev = pdev;
 359             pdev->region[i].present = true;
 360             if (type == PCI_BASE_ADDRESS_SPACE_MEMORY) {
 361                 pdev->region[i].memory = true;
 362             }
 363             memory_region_init_io(&pdev->region[i].mr, OBJECT(pdev),
 364                                   &proxy_mr_ops, &pdev->region[i],
 365                                   name, size);
 366             pci_register_bar(dev, i, type, &pdev->region[i].mr);
 367         }
 368     }
 369 }
 370
 371 static void proxy_device_reset(DeviceState *dev)
 372 {
 373     PCIProxyDev *pdev = PCI_PROXY_DEV(dev);
 374     MPQemuMsg msg = { 0 };
 375     Error *local_err = NULL;
 376
 377     msg.cmd = MPQEMU_CMD_DEVICE_RESET;
 378     msg.size = 0;
 379
 380     mpqemu_msg_send_and_await_reply(&msg, pdev, &local_err);
 381     if (local_err) {
 382         error_report_err(local_err);
 383     }
 384
 385 }