2 * SiFive PLIC (Platform Level Interrupt Controller)
4 * Copyright (c) 2017 SiFive, Inc.
6 * This provides a parameterizable interrupt controller based on SiFive's PLIC.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "qemu/error-report.h"
24 #include "hw/sysbus.h"
25 #include "hw/pci/msi.h"
26 #include "target/riscv/cpu.h"
27 #include "sysemu/sysemu.h"
28 #include "hw/riscv/sifive_plic.h"
30 #define RISCV_DEBUG_PLIC 0
32 static PLICMode
char_to_mode(char c
)
35 case 'U': return PLICMode_U
;
36 case 'S': return PLICMode_S
;
37 case 'H': return PLICMode_H
;
38 case 'M': return PLICMode_M
;
40 error_report("plic: invalid mode '%c'", c
);
45 static char mode_to_char(PLICMode m
)
48 case PLICMode_U
: return 'U';
49 case PLICMode_S
: return 'S';
50 case PLICMode_H
: return 'H';
51 case PLICMode_M
: return 'M';
56 static void sifive_plic_print_state(SiFivePLICState
*plic
)
62 qemu_log("pending : ");
63 for (i
= plic
->bitfield_words
- 1; i
>= 0; i
--) {
64 qemu_log("%08x", plic
->pending
[i
]);
69 qemu_log("claimed : ");
70 for (i
= plic
->bitfield_words
- 1; i
>= 0; i
--) {
71 qemu_log("%08x", plic
->claimed
[i
]);
75 for (addrid
= 0; addrid
< plic
->num_addrs
; addrid
++) {
76 qemu_log("hart%d-%c enable: ",
77 plic
->addr_config
[addrid
].hartid
,
78 mode_to_char(plic
->addr_config
[addrid
].mode
));
79 for (i
= plic
->bitfield_words
- 1; i
>= 0; i
--) {
80 qemu_log("%08x", plic
->enable
[addrid
* plic
->bitfield_words
+ i
]);
86 static uint32_t atomic_set_masked(uint32_t *a
, uint32_t mask
, uint32_t value
)
88 uint32_t old
, new, cmp
= atomic_read(a
);
92 new = (old
& ~mask
) | (value
& mask
);
93 cmp
= atomic_cmpxchg(a
, old
, new);
99 static void sifive_plic_set_pending(SiFivePLICState
*plic
, int irq
, bool level
)
101 atomic_set_masked(&plic
->pending
[irq
>> 5], 1 << (irq
& 31), -!!level
);
104 static void sifive_plic_set_claimed(SiFivePLICState
*plic
, int irq
, bool level
)
106 atomic_set_masked(&plic
->claimed
[irq
>> 5], 1 << (irq
& 31), -!!level
);
109 static int sifive_plic_irqs_pending(SiFivePLICState
*plic
, uint32_t addrid
)
112 for (i
= 0; i
< plic
->bitfield_words
; i
++) {
113 uint32_t pending_enabled_not_claimed
=
114 (plic
->pending
[i
] & ~plic
->claimed
[i
]) &
115 plic
->enable
[addrid
* plic
->bitfield_words
+ i
];
116 if (!pending_enabled_not_claimed
) {
119 for (j
= 0; j
< 32; j
++) {
120 int irq
= (i
<< 5) + j
;
121 uint32_t prio
= plic
->source_priority
[irq
];
122 int enabled
= pending_enabled_not_claimed
& (1 << j
);
123 if (enabled
&& prio
> plic
->target_priority
[addrid
]) {
131 static void sifive_plic_update(SiFivePLICState
*plic
)
135 /* raise irq on harts where this irq is enabled */
136 for (addrid
= 0; addrid
< plic
->num_addrs
; addrid
++) {
137 uint32_t hartid
= plic
->addr_config
[addrid
].hartid
;
138 PLICMode mode
= plic
->addr_config
[addrid
].mode
;
139 CPUState
*cpu
= qemu_get_cpu(hartid
);
140 CPURISCVState
*env
= cpu
? cpu
->env_ptr
: NULL
;
144 int level
= sifive_plic_irqs_pending(plic
, addrid
);
147 riscv_cpu_update_mip(RISCV_CPU(cpu
), MIP_MEIP
, BOOL_TO_MASK(level
));
150 riscv_cpu_update_mip(RISCV_CPU(cpu
), MIP_SEIP
, BOOL_TO_MASK(level
));
157 if (RISCV_DEBUG_PLIC
) {
158 sifive_plic_print_state(plic
);
162 void sifive_plic_raise_irq(SiFivePLICState
*plic
, uint32_t irq
)
164 sifive_plic_set_pending(plic
, irq
, true);
165 sifive_plic_update(plic
);
168 void sifive_plic_lower_irq(SiFivePLICState
*plic
, uint32_t irq
)
170 sifive_plic_set_pending(plic
, irq
, false);
171 sifive_plic_update(plic
);
174 static uint32_t sifive_plic_claim(SiFivePLICState
*plic
, uint32_t addrid
)
177 for (i
= 0; i
< plic
->bitfield_words
; i
++) {
178 uint32_t pending_enabled_not_claimed
=
179 (plic
->pending
[i
] & ~plic
->claimed
[i
]) &
180 plic
->enable
[addrid
* plic
->bitfield_words
+ i
];
181 if (!pending_enabled_not_claimed
) {
184 for (j
= 0; j
< 32; j
++) {
185 int irq
= (i
<< 5) + j
;
186 uint32_t prio
= plic
->source_priority
[irq
];
187 int enabled
= pending_enabled_not_claimed
& (1 << j
);
188 if (enabled
&& prio
> plic
->target_priority
[addrid
]) {
189 sifive_plic_set_pending(plic
, irq
, false);
190 sifive_plic_set_claimed(plic
, irq
, true);
198 static uint64_t sifive_plic_read(void *opaque
, hwaddr addr
, unsigned size
)
200 SiFivePLICState
*plic
= opaque
;
202 /* writes must be 4 byte words */
203 if ((addr
& 0x3) != 0) {
207 if (addr
>= plic
->priority_base
&& /* 4 bytes per source */
208 addr
< plic
->priority_base
+ (plic
->num_sources
<< 2))
210 uint32_t irq
= ((addr
- plic
->priority_base
) >> 2) + 1;
211 if (RISCV_DEBUG_PLIC
) {
212 qemu_log("plic: read priority: irq=%d priority=%d\n",
213 irq
, plic
->source_priority
[irq
]);
215 return plic
->source_priority
[irq
];
216 } else if (addr
>= plic
->pending_base
&& /* 1 bit per source */
217 addr
< plic
->pending_base
+ (plic
->num_sources
>> 3))
219 uint32_t word
= (addr
- plic
->pending_base
) >> 2;
220 if (RISCV_DEBUG_PLIC
) {
221 qemu_log("plic: read pending: word=%d value=%d\n",
222 word
, plic
->pending
[word
]);
224 return plic
->pending
[word
];
225 } else if (addr
>= plic
->enable_base
&& /* 1 bit per source */
226 addr
< plic
->enable_base
+ plic
->num_addrs
* plic
->enable_stride
)
228 uint32_t addrid
= (addr
- plic
->enable_base
) / plic
->enable_stride
;
229 uint32_t wordid
= (addr
& (plic
->enable_stride
- 1)) >> 2;
230 if (wordid
< plic
->bitfield_words
) {
231 if (RISCV_DEBUG_PLIC
) {
232 qemu_log("plic: read enable: hart%d-%c word=%d value=%x\n",
233 plic
->addr_config
[addrid
].hartid
,
234 mode_to_char(plic
->addr_config
[addrid
].mode
), wordid
,
235 plic
->enable
[addrid
* plic
->bitfield_words
+ wordid
]);
237 return plic
->enable
[addrid
* plic
->bitfield_words
+ wordid
];
239 } else if (addr
>= plic
->context_base
&& /* 1 bit per source */
240 addr
< plic
->context_base
+ plic
->num_addrs
* plic
->context_stride
)
242 uint32_t addrid
= (addr
- plic
->context_base
) / plic
->context_stride
;
243 uint32_t contextid
= (addr
& (plic
->context_stride
- 1));
244 if (contextid
== 0) {
245 if (RISCV_DEBUG_PLIC
) {
246 qemu_log("plic: read priority: hart%d-%c priority=%x\n",
247 plic
->addr_config
[addrid
].hartid
,
248 mode_to_char(plic
->addr_config
[addrid
].mode
),
249 plic
->target_priority
[addrid
]);
251 return plic
->target_priority
[addrid
];
252 } else if (contextid
== 4) {
253 uint32_t value
= sifive_plic_claim(plic
, addrid
);
254 if (RISCV_DEBUG_PLIC
) {
255 qemu_log("plic: read claim: hart%d-%c irq=%x\n",
256 plic
->addr_config
[addrid
].hartid
,
257 mode_to_char(plic
->addr_config
[addrid
].mode
),
259 sifive_plic_print_state(plic
);
266 error_report("plic: invalid register read: %08x", (uint32_t)addr
);
270 static void sifive_plic_write(void *opaque
, hwaddr addr
, uint64_t value
,
273 SiFivePLICState
*plic
= opaque
;
275 /* writes must be 4 byte words */
276 if ((addr
& 0x3) != 0) {
280 if (addr
>= plic
->priority_base
&& /* 4 bytes per source */
281 addr
< plic
->priority_base
+ (plic
->num_sources
<< 2))
283 uint32_t irq
= ((addr
- plic
->priority_base
) >> 2) + 1;
284 plic
->source_priority
[irq
] = value
& 7;
285 if (RISCV_DEBUG_PLIC
) {
286 qemu_log("plic: write priority: irq=%d priority=%d\n",
287 irq
, plic
->source_priority
[irq
]);
290 } else if (addr
>= plic
->pending_base
&& /* 1 bit per source */
291 addr
< plic
->pending_base
+ (plic
->num_sources
>> 3))
293 error_report("plic: invalid pending write: %08x", (uint32_t)addr
);
295 } else if (addr
>= plic
->enable_base
&& /* 1 bit per source */
296 addr
< plic
->enable_base
+ plic
->num_addrs
* plic
->enable_stride
)
298 uint32_t addrid
= (addr
- plic
->enable_base
) / plic
->enable_stride
;
299 uint32_t wordid
= (addr
& (plic
->enable_stride
- 1)) >> 2;
300 if (wordid
< plic
->bitfield_words
) {
301 plic
->enable
[addrid
* plic
->bitfield_words
+ wordid
] = value
;
302 if (RISCV_DEBUG_PLIC
) {
303 qemu_log("plic: write enable: hart%d-%c word=%d value=%x\n",
304 plic
->addr_config
[addrid
].hartid
,
305 mode_to_char(plic
->addr_config
[addrid
].mode
), wordid
,
306 plic
->enable
[addrid
* plic
->bitfield_words
+ wordid
]);
310 } else if (addr
>= plic
->context_base
&& /* 4 bytes per reg */
311 addr
< plic
->context_base
+ plic
->num_addrs
* plic
->context_stride
)
313 uint32_t addrid
= (addr
- plic
->context_base
) / plic
->context_stride
;
314 uint32_t contextid
= (addr
& (plic
->context_stride
- 1));
315 if (contextid
== 0) {
316 if (RISCV_DEBUG_PLIC
) {
317 qemu_log("plic: write priority: hart%d-%c priority=%x\n",
318 plic
->addr_config
[addrid
].hartid
,
319 mode_to_char(plic
->addr_config
[addrid
].mode
),
320 plic
->target_priority
[addrid
]);
322 if (value
<= plic
->num_priorities
) {
323 plic
->target_priority
[addrid
] = value
;
324 sifive_plic_update(plic
);
327 } else if (contextid
== 4) {
328 if (RISCV_DEBUG_PLIC
) {
329 qemu_log("plic: write claim: hart%d-%c irq=%x\n",
330 plic
->addr_config
[addrid
].hartid
,
331 mode_to_char(plic
->addr_config
[addrid
].mode
),
334 if (value
< plic
->num_sources
) {
335 sifive_plic_set_claimed(plic
, value
, false);
336 sifive_plic_update(plic
);
343 error_report("plic: invalid register write: %08x", (uint32_t)addr
);
346 static const MemoryRegionOps sifive_plic_ops
= {
347 .read
= sifive_plic_read
,
348 .write
= sifive_plic_write
,
349 .endianness
= DEVICE_LITTLE_ENDIAN
,
351 .min_access_size
= 4,
356 static Property sifive_plic_properties
[] = {
357 DEFINE_PROP_STRING("hart-config", SiFivePLICState
, hart_config
),
358 DEFINE_PROP_UINT32("num-sources", SiFivePLICState
, num_sources
, 0),
359 DEFINE_PROP_UINT32("num-priorities", SiFivePLICState
, num_priorities
, 0),
360 DEFINE_PROP_UINT32("priority-base", SiFivePLICState
, priority_base
, 0),
361 DEFINE_PROP_UINT32("pending-base", SiFivePLICState
, pending_base
, 0),
362 DEFINE_PROP_UINT32("enable-base", SiFivePLICState
, enable_base
, 0),
363 DEFINE_PROP_UINT32("enable-stride", SiFivePLICState
, enable_stride
, 0),
364 DEFINE_PROP_UINT32("context-base", SiFivePLICState
, context_base
, 0),
365 DEFINE_PROP_UINT32("context-stride", SiFivePLICState
, context_stride
, 0),
366 DEFINE_PROP_UINT32("aperture-size", SiFivePLICState
, aperture_size
, 0),
367 DEFINE_PROP_END_OF_LIST(),
371 * parse PLIC hart/mode address offset config
373 * "M" 1 hart with M mode
374 * "MS,MS" 2 harts, 0-1 with M and S mode
375 * "M,MS,MS,MS,MS" 5 harts, 0 with M mode, 1-5 with M and S mode
377 static void parse_hart_config(SiFivePLICState
*plic
)
379 int addrid
, hartid
, modes
;
383 /* count and validate hart/mode combinations */
384 addrid
= 0, hartid
= 0, modes
= 0;
385 p
= plic
->hart_config
;
388 addrid
+= ctpop8(modes
);
392 int m
= 1 << char_to_mode(c
);
393 if (modes
== (modes
| m
)) {
394 error_report("plic: duplicate mode '%c' in config: %s",
395 c
, plic
->hart_config
);
402 addrid
+= ctpop8(modes
);
406 /* store hart/mode combinations */
407 plic
->num_addrs
= addrid
;
408 plic
->addr_config
= g_new(PLICAddr
, plic
->num_addrs
);
409 addrid
= 0, hartid
= 0;
410 p
= plic
->hart_config
;
415 plic
->addr_config
[addrid
].addrid
= addrid
;
416 plic
->addr_config
[addrid
].hartid
= hartid
;
417 plic
->addr_config
[addrid
].mode
= char_to_mode(c
);
423 static void sifive_plic_irq_request(void *opaque
, int irq
, int level
)
425 SiFivePLICState
*plic
= opaque
;
426 if (RISCV_DEBUG_PLIC
) {
427 qemu_log("sifive_plic_irq_request: irq=%d level=%d\n", irq
, level
);
429 sifive_plic_set_pending(plic
, irq
, level
> 0);
430 sifive_plic_update(plic
);
433 static void sifive_plic_realize(DeviceState
*dev
, Error
**errp
)
435 SiFivePLICState
*plic
= SIFIVE_PLIC(dev
);
438 memory_region_init_io(&plic
->mmio
, OBJECT(dev
), &sifive_plic_ops
, plic
,
439 TYPE_SIFIVE_PLIC
, plic
->aperture_size
);
440 parse_hart_config(plic
);
441 plic
->bitfield_words
= (plic
->num_sources
+ 31) >> 5;
442 plic
->source_priority
= g_new0(uint32_t, plic
->num_sources
);
443 plic
->target_priority
= g_new(uint32_t, plic
->num_addrs
);
444 plic
->pending
= g_new0(uint32_t, plic
->bitfield_words
);
445 plic
->claimed
= g_new0(uint32_t, plic
->bitfield_words
);
446 plic
->enable
= g_new0(uint32_t, plic
->bitfield_words
* plic
->num_addrs
);
447 sysbus_init_mmio(SYS_BUS_DEVICE(dev
), &plic
->mmio
);
448 qdev_init_gpio_in(dev
, sifive_plic_irq_request
, plic
->num_sources
);
450 /* We can't allow the supervisor to control SEIP as this would allow the
451 * supervisor to clear a pending external interrupt which will result in
452 * lost a interrupt in the case a PLIC is attached. The SEIP bit must be
453 * hardware controlled when a PLIC is attached.
455 for (i
= 0; i
< smp_cpus
; i
++) {
456 RISCVCPU
*cpu
= RISCV_CPU(qemu_get_cpu(i
));
457 if (riscv_cpu_claim_interrupts(cpu
, MIP_SEIP
) < 0) {
458 error_report("SEIP already claimed");
463 msi_nonbroken
= true;
466 static void sifive_plic_class_init(ObjectClass
*klass
, void *data
)
468 DeviceClass
*dc
= DEVICE_CLASS(klass
);
470 dc
->props
= sifive_plic_properties
;
471 dc
->realize
= sifive_plic_realize
;
474 static const TypeInfo sifive_plic_info
= {
475 .name
= TYPE_SIFIVE_PLIC
,
476 .parent
= TYPE_SYS_BUS_DEVICE
,
477 .instance_size
= sizeof(SiFivePLICState
),
478 .class_init
= sifive_plic_class_init
,
481 static void sifive_plic_register_types(void)
483 type_register_static(&sifive_plic_info
);
486 type_init(sifive_plic_register_types
)
489 * Create PLIC device.
491 DeviceState
*sifive_plic_create(hwaddr addr
, char *hart_config
,
492 uint32_t num_sources
, uint32_t num_priorities
,
493 uint32_t priority_base
, uint32_t pending_base
,
494 uint32_t enable_base
, uint32_t enable_stride
,
495 uint32_t context_base
, uint32_t context_stride
,
496 uint32_t aperture_size
)
498 DeviceState
*dev
= qdev_create(NULL
, TYPE_SIFIVE_PLIC
);
499 assert(enable_stride
== (enable_stride
& -enable_stride
));
500 assert(context_stride
== (context_stride
& -context_stride
));
501 qdev_prop_set_string(dev
, "hart-config", hart_config
);
502 qdev_prop_set_uint32(dev
, "num-sources", num_sources
);
503 qdev_prop_set_uint32(dev
, "num-priorities", num_priorities
);
504 qdev_prop_set_uint32(dev
, "priority-base", priority_base
);
505 qdev_prop_set_uint32(dev
, "pending-base", pending_base
);
506 qdev_prop_set_uint32(dev
, "enable-base", enable_base
);
507 qdev_prop_set_uint32(dev
, "enable-stride", enable_stride
);
508 qdev_prop_set_uint32(dev
, "context-base", context_base
);
509 qdev_prop_set_uint32(dev
, "context-stride", context_stride
);
510 qdev_prop_set_uint32(dev
, "aperture-size", aperture_size
);
511 qdev_init_nofail(dev
);
512 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, addr
);