hw/riscv/virt.c

   1 /*
   2  * QEMU RISC-V VirtIO Board
   3  *
   4  * Copyright (c) 2017 SiFive, Inc.
   5  *
   6  * RISC-V machine with 16550a UART and VirtIO MMIO
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms and conditions of the GNU General Public License,
  10  * version 2 or later, as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qemu/units.h"
  23 #include "qemu/log.h"
  24 #include "qemu/error-report.h"
  25 #include "qapi/error.h"
  26 #include "hw/boards.h"
  27 #include "hw/loader.h"
  28 #include "hw/sysbus.h"
  29 #include "hw/qdev-properties.h"
  30 #include "hw/char/serial.h"
  31 #include "target/riscv/cpu.h"
  32 #include "hw/riscv/riscv_hart.h"
  33 #include "hw/riscv/sifive_plic.h"
  34 #include "hw/riscv/sifive_clint.h"
  35 #include "hw/riscv/sifive_test.h"
  36 #include "hw/riscv/virt.h"
  37 #include "hw/riscv/boot.h"
  38 #include "chardev/char.h"
  39 #include "sysemu/arch_init.h"
  40 #include "sysemu/device_tree.h"
  41 #include "sysemu/sysemu.h"
  42 #include "exec/address-spaces.h"
  43 #include "hw/pci/pci.h"
  44 #include "hw/pci-host/gpex.h"
  45
  46 #include <libfdt.h>
  47
  48 #if defined(TARGET_RISCV32)
  49 # define BIOS_FILENAME "opensbi-riscv32-virt-fw_jump.bin"
  50 #else
  51 # define BIOS_FILENAME "opensbi-riscv64-virt-fw_jump.bin"
  52 #endif
  53
  54 static const struct MemmapEntry {
  55     hwaddr base;
  56     hwaddr size;
  57 } virt_memmap[] = {
  58     [VIRT_DEBUG] =       {        0x0,         0x100 },
  59     [VIRT_MROM] =        {     0x1000,       0x11000 },
  60     [VIRT_TEST] =        {   0x100000,        0x1000 },
  61     [VIRT_RTC] =         {   0x101000,        0x1000 },
  62     [VIRT_CLINT] =       {  0x2000000,       0x10000 },
  63     [VIRT_PLIC] =        {  0xc000000,     0x4000000 },
  64     [VIRT_UART0] =       { 0x10000000,         0x100 },
  65     [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
  66     [VIRT_FLASH] =       { 0x20000000,     0x4000000 },
  67     [VIRT_DRAM] =        { 0x80000000,           0x0 },
  68     [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
  69     [VIRT_PCIE_PIO] =    { 0x03000000,    0x00010000 },
  70     [VIRT_PCIE_ECAM] =   { 0x30000000,    0x10000000 },
  71 };
  72
  73 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
  74
  75 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s,
  76                                        const char *name,
  77                                        const char *alias_prop_name)
  78 {
  79     /*
  80      * Create a single flash device.  We use the same parameters as
  81      * the flash devices on the ARM virt board.
  82      */
  83     DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
  84
  85     qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
  86     qdev_prop_set_uint8(dev, "width", 4);
  87     qdev_prop_set_uint8(dev, "device-width", 2);
  88     qdev_prop_set_bit(dev, "big-endian", false);
  89     qdev_prop_set_uint16(dev, "id0", 0x89);
  90     qdev_prop_set_uint16(dev, "id1", 0x18);
  91     qdev_prop_set_uint16(dev, "id2", 0x00);
  92     qdev_prop_set_uint16(dev, "id3", 0x00);
  93     qdev_prop_set_string(dev, "name", name);
  94
  95     object_property_add_child(OBJECT(s), name, OBJECT(dev));
  96     object_property_add_alias(OBJECT(s), alias_prop_name,
  97                               OBJECT(dev), "drive");
  98
  99     return PFLASH_CFI01(dev);
 100 }
 101
 102 static void virt_flash_create(RISCVVirtState *s)
 103 {
 104     s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0");
 105     s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1");
 106 }
 107
 108 static void virt_flash_map1(PFlashCFI01 *flash,
 109                             hwaddr base, hwaddr size,
 110                             MemoryRegion *sysmem)
 111 {
 112     DeviceState *dev = DEVICE(flash);
 113
 114     assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
 115     assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
 116     qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
 117     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 118
 119     memory_region_add_subregion(sysmem, base,
 120                                 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
 121                                                        0));
 122 }
 123
 124 static void virt_flash_map(RISCVVirtState *s,
 125                            MemoryRegion *sysmem)
 126 {
 127     hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
 128     hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
 129
 130     virt_flash_map1(s->flash[0], flashbase, flashsize,
 131                     sysmem);
 132     virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize,
 133                     sysmem);
 134 }
 135
 136 static void create_pcie_irq_map(void *fdt, char *nodename,
 137                                 uint32_t plic_phandle)
 138 {
 139     int pin, dev;
 140     uint32_t
 141         full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {};
 142     uint32_t *irq_map = full_irq_map;
 143
 144     /* This code creates a standard swizzle of interrupts such that
 145      * each device's first interrupt is based on it's PCI_SLOT number.
 146      * (See pci_swizzle_map_irq_fn())
 147      *
 148      * We only need one entry per interrupt in the table (not one per
 149      * possible slot) seeing the interrupt-map-mask will allow the table
 150      * to wrap to any number of devices.
 151      */
 152     for (dev = 0; dev < GPEX_NUM_IRQS; dev++) {
 153         int devfn = dev * 0x8;
 154
 155         for (pin = 0; pin < GPEX_NUM_IRQS; pin++) {
 156             int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
 157             int i = 0;
 158
 159             irq_map[i] = cpu_to_be32(devfn << 8);
 160
 161             i += FDT_PCI_ADDR_CELLS;
 162             irq_map[i] = cpu_to_be32(pin + 1);
 163
 164             i += FDT_PCI_INT_CELLS;
 165             irq_map[i++] = cpu_to_be32(plic_phandle);
 166
 167             i += FDT_PLIC_ADDR_CELLS;
 168             irq_map[i] = cpu_to_be32(irq_nr);
 169
 170             irq_map += FDT_INT_MAP_WIDTH;
 171         }
 172     }
 173
 174     qemu_fdt_setprop(fdt, nodename, "interrupt-map",
 175                      full_irq_map, sizeof(full_irq_map));
 176
 177     qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
 178                            0x1800, 0, 0, 0x7);
 179 }
 180
 181 static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
 182     uint64_t mem_size, const char *cmdline)
 183 {
 184     void *fdt;
 185     int cpu, i;
 186     uint32_t *cells;
 187     char *nodename;
 188     uint32_t plic_phandle, test_phandle, phandle = 1;
 189     hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
 190     hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
 191
 192     fdt = s->fdt = create_device_tree(&s->fdt_size);
 193     if (!fdt) {
 194         error_report("create_device_tree() failed");
 195         exit(1);
 196     }
 197
 198     qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu");
 199     qemu_fdt_setprop_string(fdt, "/", "compatible", "riscv-virtio");
 200     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
 201     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
 202
 203     qemu_fdt_add_subnode(fdt, "/soc");
 204     qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
 205     qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
 206     qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
 207     qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
 208
 209     nodename = g_strdup_printf("/memory@%lx",
 210         (long)memmap[VIRT_DRAM].base);
 211     qemu_fdt_add_subnode(fdt, nodename);
 212     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 213         memmap[VIRT_DRAM].base >> 32, memmap[VIRT_DRAM].base,
 214         mem_size >> 32, mem_size);
 215     qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
 216     g_free(nodename);
 217
 218     qemu_fdt_add_subnode(fdt, "/cpus");
 219     qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
 220                           SIFIVE_CLINT_TIMEBASE_FREQ);
 221     qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
 222     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
 223
 224     for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
 225         int cpu_phandle = phandle++;
 226         int intc_phandle;
 227         nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
 228         char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 229         char *isa = riscv_isa_string(&s->soc.harts[cpu]);
 230         qemu_fdt_add_subnode(fdt, nodename);
 231 #if defined(TARGET_RISCV32)
 232         qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
 233 #else
 234         qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
 235 #endif
 236         qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
 237         qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
 238         qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
 239         qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
 240         qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
 241         qemu_fdt_setprop_cell(fdt, nodename, "phandle", cpu_phandle);
 242         intc_phandle = phandle++;
 243         qemu_fdt_add_subnode(fdt, intc);
 244         qemu_fdt_setprop_cell(fdt, intc, "phandle", intc_phandle);
 245         qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
 246         qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
 247         qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
 248         g_free(isa);
 249         g_free(intc);
 250         g_free(nodename);
 251     }
 252
 253     /* Add cpu-topology node */
 254     qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
 255     qemu_fdt_add_subnode(fdt, "/cpus/cpu-map/cluster0");
 256     for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
 257         char *core_nodename = g_strdup_printf("/cpus/cpu-map/cluster0/core%d",
 258                                               cpu);
 259         char *cpu_nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
 260         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, cpu_nodename);
 261         qemu_fdt_add_subnode(fdt, core_nodename);
 262         qemu_fdt_setprop_cell(fdt, core_nodename, "cpu", intc_phandle);
 263         g_free(core_nodename);
 264         g_free(cpu_nodename);
 265     }
 266
 267     cells =  g_new0(uint32_t, s->soc.num_harts * 4);
 268     for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
 269         nodename =
 270             g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 271         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
 272         cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
 273         cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
 274         cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
 275         cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
 276         g_free(nodename);
 277     }
 278     nodename = g_strdup_printf("/soc/clint@%lx",
 279         (long)memmap[VIRT_CLINT].base);
 280     qemu_fdt_add_subnode(fdt, nodename);
 281     qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
 282     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 283         0x0, memmap[VIRT_CLINT].base,
 284         0x0, memmap[VIRT_CLINT].size);
 285     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
 286         cells, s->soc.num_harts * sizeof(uint32_t) * 4);
 287     g_free(cells);
 288     g_free(nodename);
 289
 290     plic_phandle = phandle++;
 291     cells =  g_new0(uint32_t, s->soc.num_harts * 4);
 292     for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
 293         nodename =
 294             g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 295         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
 296         cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
 297         cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
 298         cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
 299         cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
 300         g_free(nodename);
 301     }
 302     nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
 303         (long)memmap[VIRT_PLIC].base);
 304     qemu_fdt_add_subnode(fdt, nodename);
 305     qemu_fdt_setprop_cell(fdt, nodename, "#address-cells",
 306                           FDT_PLIC_ADDR_CELLS);
 307     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells",
 308                           FDT_PLIC_INT_CELLS);
 309     qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
 310     qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
 311     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
 312         cells, s->soc.num_harts * sizeof(uint32_t) * 4);
 313     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 314         0x0, memmap[VIRT_PLIC].base,
 315         0x0, memmap[VIRT_PLIC].size);
 316     qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV);
 317     qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
 318     plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
 319     g_free(cells);
 320     g_free(nodename);
 321
 322     for (i = 0; i < VIRTIO_COUNT; i++) {
 323         nodename = g_strdup_printf("/virtio_mmio@%lx",
 324             (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
 325         qemu_fdt_add_subnode(fdt, nodename);
 326         qemu_fdt_setprop_string(fdt, nodename, "compatible", "virtio,mmio");
 327         qemu_fdt_setprop_cells(fdt, nodename, "reg",
 328             0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
 329             0x0, memmap[VIRT_VIRTIO].size);
 330         qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 331         qemu_fdt_setprop_cell(fdt, nodename, "interrupts", VIRTIO_IRQ + i);
 332         g_free(nodename);
 333     }
 334
 335     nodename = g_strdup_printf("/soc/pci@%lx",
 336         (long) memmap[VIRT_PCIE_ECAM].base);
 337     qemu_fdt_add_subnode(fdt, nodename);
 338     qemu_fdt_setprop_cell(fdt, nodename, "#address-cells",
 339                           FDT_PCI_ADDR_CELLS);
 340     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells",
 341                           FDT_PCI_INT_CELLS);
 342     qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0x2);
 343     qemu_fdt_setprop_string(fdt, nodename, "compatible",
 344                             "pci-host-ecam-generic");
 345     qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci");
 346     qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0);
 347     qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0,
 348                            memmap[VIRT_PCIE_ECAM].size /
 349                                PCIE_MMCFG_SIZE_MIN - 1);
 350     qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
 351     qemu_fdt_setprop_cells(fdt, nodename, "reg", 0, memmap[VIRT_PCIE_ECAM].base,
 352                            0, memmap[VIRT_PCIE_ECAM].size);
 353     qemu_fdt_setprop_sized_cells(fdt, nodename, "ranges",
 354         1, FDT_PCI_RANGE_IOPORT, 2, 0,
 355         2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,
 356         1, FDT_PCI_RANGE_MMIO,
 357         2, memmap[VIRT_PCIE_MMIO].base,
 358         2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size);
 359     create_pcie_irq_map(fdt, nodename, plic_phandle);
 360     g_free(nodename);
 361
 362     test_phandle = phandle++;
 363     nodename = g_strdup_printf("/test@%lx",
 364         (long)memmap[VIRT_TEST].base);
 365     qemu_fdt_add_subnode(fdt, nodename);
 366     {
 367         const char compat[] = "sifive,test1\0sifive,test0\0syscon";
 368         qemu_fdt_setprop(fdt, nodename, "compatible", compat, sizeof(compat));
 369     }
 370     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 371         0x0, memmap[VIRT_TEST].base,
 372         0x0, memmap[VIRT_TEST].size);
 373     qemu_fdt_setprop_cell(fdt, nodename, "phandle", test_phandle);
 374     test_phandle = qemu_fdt_get_phandle(fdt, nodename);
 375     g_free(nodename);
 376
 377     nodename = g_strdup_printf("/reboot");
 378     qemu_fdt_add_subnode(fdt, nodename);
 379     qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-reboot");
 380     qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_phandle);
 381     qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0);
 382     qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_RESET);
 383     g_free(nodename);
 384
 385     nodename = g_strdup_printf("/poweroff");
 386     qemu_fdt_add_subnode(fdt, nodename);
 387     qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-poweroff");
 388     qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_phandle);
 389     qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0);
 390     qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_PASS);
 391     g_free(nodename);
 392
 393     nodename = g_strdup_printf("/uart@%lx",
 394         (long)memmap[VIRT_UART0].base);
 395     qemu_fdt_add_subnode(fdt, nodename);
 396     qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a");
 397     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 398         0x0, memmap[VIRT_UART0].base,
 399         0x0, memmap[VIRT_UART0].size);
 400     qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400);
 401     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 402     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", UART0_IRQ);
 403
 404     qemu_fdt_add_subnode(fdt, "/chosen");
 405     qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
 406     if (cmdline) {
 407         qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
 408     }
 409     g_free(nodename);
 410
 411     nodename = g_strdup_printf("/rtc@%lx",
 412         (long)memmap[VIRT_RTC].base);
 413     qemu_fdt_add_subnode(fdt, nodename);
 414     qemu_fdt_setprop_string(fdt, nodename, "compatible",
 415         "google,goldfish-rtc");
 416     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 417         0x0, memmap[VIRT_RTC].base,
 418         0x0, memmap[VIRT_RTC].size);
 419     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 420     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", RTC_IRQ);
 421     g_free(nodename);
 422
 423     nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
 424     qemu_fdt_add_subnode(s->fdt, nodename);
 425     qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "cfi-flash");
 426     qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg",
 427                                  2, flashbase, 2, flashsize,
 428                                  2, flashbase + flashsize, 2, flashsize);
 429     qemu_fdt_setprop_cell(s->fdt, nodename, "bank-width", 4);
 430     g_free(nodename);
 431 }
 432
 433
 434 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
 435                                           hwaddr ecam_base, hwaddr ecam_size,
 436                                           hwaddr mmio_base, hwaddr mmio_size,
 437                                           hwaddr pio_base,
 438                                           DeviceState *plic, bool link_up)
 439 {
 440     DeviceState *dev;
 441     MemoryRegion *ecam_alias, *ecam_reg;
 442     MemoryRegion *mmio_alias, *mmio_reg;
 443     qemu_irq irq;
 444     int i;
 445
 446     dev = qdev_new(TYPE_GPEX_HOST);
 447
 448     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 449
 450     ecam_alias = g_new0(MemoryRegion, 1);
 451     ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
 452     memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
 453                              ecam_reg, 0, ecam_size);
 454     memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias);
 455
 456     mmio_alias = g_new0(MemoryRegion, 1);
 457     mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
 458     memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
 459                              mmio_reg, mmio_base, mmio_size);
 460     memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias);
 461
 462     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);
 463
 464     for (i = 0; i < GPEX_NUM_IRQS; i++) {
 465         irq = qdev_get_gpio_in(plic, PCIE_IRQ + i);
 466
 467         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
 468         gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
 469     }
 470
 471     return dev;
 472 }
 473
 474 static void virt_machine_init(MachineState *machine)
 475 {
 476     const struct MemmapEntry *memmap = virt_memmap;
 477     RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
 478     MemoryRegion *system_memory = get_system_memory();
 479     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
 480     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
 481     char *plic_hart_config;
 482     size_t plic_hart_config_len;
 483     target_ulong start_addr = memmap[VIRT_DRAM].base;
 484     int i;
 485     unsigned int smp_cpus = machine->smp.cpus;
 486
 487     /* Initialize SOC */
 488     object_initialize_child(OBJECT(machine), "soc", &s->soc,
 489                             TYPE_RISCV_HART_ARRAY);
 490     object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type,
 491                             &error_abort);
 492     object_property_set_int(OBJECT(&s->soc), "num-harts", smp_cpus,
 493                             &error_abort);
 494     sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_abort);
 495
 496     /* register system main memory (actual RAM) */
 497     memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram",
 498                            machine->ram_size, &error_fatal);
 499     memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
 500         main_mem);
 501
 502     /* create device tree */
 503     create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
 504
 505     /* boot rom */
 506     memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
 507                            memmap[VIRT_MROM].size, &error_fatal);
 508     memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
 509                                 mask_rom);
 510
 511     riscv_find_and_load_firmware(machine, BIOS_FILENAME,
 512                                  memmap[VIRT_DRAM].base, NULL);
 513
 514     if (machine->kernel_filename) {
 515         uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
 516                                                   NULL);
 517
 518         if (machine->initrd_filename) {
 519             hwaddr start;
 520             hwaddr end = riscv_load_initrd(machine->initrd_filename,
 521                                            machine->ram_size, kernel_entry,
 522                                            &start);
 523             qemu_fdt_setprop_cell(s->fdt, "/chosen",
 524                                   "linux,initrd-start", start);
 525             qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
 526                                   end);
 527         }
 528     }
 529
 530     if (drive_get(IF_PFLASH, 0, 0)) {
 531         /*
 532          * Pflash was supplied, let's overwrite the address we jump to after
 533          * reset to the base of the flash.
 534          */
 535         start_addr = virt_memmap[VIRT_FLASH].base;
 536     }
 537
 538     /* reset vector */
 539     uint32_t reset_vec[8] = {
 540         0x00000297,                  /* 1:  auipc  t0, %pcrel_hi(dtb) */
 541         0x02028593,                  /*     addi   a1, t0, %pcrel_lo(1b) */
 542         0xf1402573,                  /*     csrr   a0, mhartid  */
 543 #if defined(TARGET_RISCV32)
 544         0x0182a283,                  /*     lw     t0, 24(t0) */
 545 #elif defined(TARGET_RISCV64)
 546         0x0182b283,                  /*     ld     t0, 24(t0) */
 547 #endif
 548         0x00028067,                  /*     jr     t0 */
 549         0x00000000,
 550         start_addr,                  /* start: .dword */
 551         0x00000000,
 552                                      /* dtb: */
 553     };
 554
 555     /* copy in the reset vector in little_endian byte order */
 556     for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
 557         reset_vec[i] = cpu_to_le32(reset_vec[i]);
 558     }
 559     rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
 560                           memmap[VIRT_MROM].base, &address_space_memory);
 561
 562     /* copy in the device tree */
 563     if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
 564             memmap[VIRT_MROM].size - sizeof(reset_vec)) {
 565         error_report("not enough space to store device-tree");
 566         exit(1);
 567     }
 568     qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
 569     rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
 570                           memmap[VIRT_MROM].base + sizeof(reset_vec),
 571                           &address_space_memory);
 572
 573     /* create PLIC hart topology configuration string */
 574     plic_hart_config_len = (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpus;
 575     plic_hart_config = g_malloc0(plic_hart_config_len);
 576     for (i = 0; i < smp_cpus; i++) {
 577         if (i != 0) {
 578             strncat(plic_hart_config, ",", plic_hart_config_len);
 579         }
 580         strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, plic_hart_config_len);
 581         plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1);
 582     }
 583
 584     /* MMIO */
 585     s->plic = sifive_plic_create(memmap[VIRT_PLIC].base,
 586         plic_hart_config,
 587         VIRT_PLIC_NUM_SOURCES,
 588         VIRT_PLIC_NUM_PRIORITIES,
 589         VIRT_PLIC_PRIORITY_BASE,
 590         VIRT_PLIC_PENDING_BASE,
 591         VIRT_PLIC_ENABLE_BASE,
 592         VIRT_PLIC_ENABLE_STRIDE,
 593         VIRT_PLIC_CONTEXT_BASE,
 594         VIRT_PLIC_CONTEXT_STRIDE,
 595         memmap[VIRT_PLIC].size);
 596     sifive_clint_create(memmap[VIRT_CLINT].base,
 597         memmap[VIRT_CLINT].size, smp_cpus,
 598         SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, true);
 599     sifive_test_create(memmap[VIRT_TEST].base);
 600
 601     for (i = 0; i < VIRTIO_COUNT; i++) {
 602         sysbus_create_simple("virtio-mmio",
 603             memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
 604             qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i));
 605     }
 606
 607     gpex_pcie_init(system_memory,
 608                          memmap[VIRT_PCIE_ECAM].base,
 609                          memmap[VIRT_PCIE_ECAM].size,
 610                          memmap[VIRT_PCIE_MMIO].base,
 611                          memmap[VIRT_PCIE_MMIO].size,
 612                          memmap[VIRT_PCIE_PIO].base,
 613                          DEVICE(s->plic), true);
 614
 615     serial_mm_init(system_memory, memmap[VIRT_UART0].base,
 616         0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
 617         serial_hd(0), DEVICE_LITTLE_ENDIAN);
 618
 619     sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base,
 620         qdev_get_gpio_in(DEVICE(s->plic), RTC_IRQ));
 621
 622     virt_flash_create(s);
 623
 624     for (i = 0; i < ARRAY_SIZE(s->flash); i++) {
 625         /* Map legacy -drive if=pflash to machine properties */
 626         pflash_cfi01_legacy_drive(s->flash[i],
 627                                   drive_get(IF_PFLASH, 0, i));
 628     }
 629     virt_flash_map(s, system_memory);
 630
 631     g_free(plic_hart_config);
 632 }
 633
 634 static void virt_machine_instance_init(Object *obj)
 635 {
 636 }
 637
 638 static void virt_machine_class_init(ObjectClass *oc, void *data)
 639 {
 640     MachineClass *mc = MACHINE_CLASS(oc);
 641
 642     mc->desc = "RISC-V VirtIO board";
 643     mc->init = virt_machine_init;
 644     mc->max_cpus = 8;
 645     mc->default_cpu_type = VIRT_CPU;
 646     mc->pci_allow_0_address = true;
 647 }
 648
 649 static const TypeInfo virt_machine_typeinfo = {
 650     .name       = MACHINE_TYPE_NAME("virt"),
 651     .parent     = TYPE_MACHINE,
 652     .class_init = virt_machine_class_init,
 653     .instance_init = virt_machine_instance_init,
 654     .instance_size = sizeof(RISCVVirtState),
 655 };
 656
 657 static void virt_machine_init_register_types(void)
 658 {
 659     type_register_static(&virt_machine_typeinfo);
 660 }
 661
 662 type_init(virt_machine_init_register_types)