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[mirror_qemu.git] / hw / sparc / sun4m.c
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "qemu/osdep.h"
25 #include "qemu/units.h"
26 #include "qapi/error.h"
27 #include "qemu-common.h"
28 #include "cpu.h"
29 #include "hw/sysbus.h"
30 #include "qemu/error-report.h"
31 #include "qemu/timer.h"
32 #include "hw/sparc/sun4m_iommu.h"
33 #include "hw/timer/m48t59.h"
34 #include "hw/sparc/sparc32_dma.h"
35 #include "hw/block/fdc.h"
36 #include "sysemu/sysemu.h"
37 #include "net/net.h"
38 #include "hw/boards.h"
39 #include "hw/scsi/esp.h"
40 #include "hw/nvram/sun_nvram.h"
41 #include "hw/nvram/chrp_nvram.h"
42 #include "hw/nvram/fw_cfg.h"
43 #include "hw/char/escc.h"
44 #include "hw/empty_slot.h"
45 #include "hw/loader.h"
46 #include "elf.h"
47 #include "trace.h"
48
49 /*
50 * Sun4m architecture was used in the following machines:
51 *
52 * SPARCserver 6xxMP/xx
53 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
54 * SPARCclassic X (4/10)
55 * SPARCstation LX/ZX (4/30)
56 * SPARCstation Voyager
57 * SPARCstation 10/xx, SPARCserver 10/xx
58 * SPARCstation 5, SPARCserver 5
59 * SPARCstation 20/xx, SPARCserver 20
60 * SPARCstation 4
61 *
62 * See for example: http://www.sunhelp.org/faq/sunref1.html
63 */
64
65 #define KERNEL_LOAD_ADDR 0x00004000
66 #define CMDLINE_ADDR 0x007ff000
67 #define INITRD_LOAD_ADDR 0x00800000
68 #define PROM_SIZE_MAX (1 * MiB)
69 #define PROM_VADDR 0xffd00000
70 #define PROM_FILENAME "openbios-sparc32"
71 #define CFG_ADDR 0xd00000510ULL
72 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
73 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
74 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
75
76 #define MAX_CPUS 16
77 #define MAX_PILS 16
78 #define MAX_VSIMMS 4
79
80 #define ESCC_CLOCK 4915200
81
82 struct sun4m_hwdef {
83 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
84 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
85 hwaddr serial_base, fd_base;
86 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
87 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
88 hwaddr bpp_base, dbri_base, sx_base;
89 struct {
90 hwaddr reg_base, vram_base;
91 } vsimm[MAX_VSIMMS];
92 hwaddr ecc_base;
93 uint64_t max_mem;
94 uint32_t ecc_version;
95 uint32_t iommu_version;
96 uint16_t machine_id;
97 uint8_t nvram_machine_id;
98 };
99
100 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
101 Error **errp)
102 {
103 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
104 }
105
106 static void nvram_init(Nvram *nvram, uint8_t *macaddr,
107 const char *cmdline, const char *boot_devices,
108 ram_addr_t RAM_size, uint32_t kernel_size,
109 int width, int height, int depth,
110 int nvram_machine_id, const char *arch)
111 {
112 unsigned int i;
113 int sysp_end;
114 uint8_t image[0x1ff0];
115 NvramClass *k = NVRAM_GET_CLASS(nvram);
116
117 memset(image, '\0', sizeof(image));
118
119 /* OpenBIOS nvram variables partition */
120 sysp_end = chrp_nvram_create_system_partition(image, 0);
121
122 /* Free space partition */
123 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
124
125 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
126 nvram_machine_id);
127
128 for (i = 0; i < sizeof(image); i++) {
129 (k->write)(nvram, i, image[i]);
130 }
131 }
132
133 void cpu_check_irqs(CPUSPARCState *env)
134 {
135 CPUState *cs;
136
137 /* We should be holding the BQL before we mess with IRQs */
138 g_assert(qemu_mutex_iothread_locked());
139
140 if (env->pil_in && (env->interrupt_index == 0 ||
141 (env->interrupt_index & ~15) == TT_EXTINT)) {
142 unsigned int i;
143
144 for (i = 15; i > 0; i--) {
145 if (env->pil_in & (1 << i)) {
146 int old_interrupt = env->interrupt_index;
147
148 env->interrupt_index = TT_EXTINT | i;
149 if (old_interrupt != env->interrupt_index) {
150 cs = CPU(sparc_env_get_cpu(env));
151 trace_sun4m_cpu_interrupt(i);
152 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
153 }
154 break;
155 }
156 }
157 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
158 cs = CPU(sparc_env_get_cpu(env));
159 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
160 env->interrupt_index = 0;
161 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
162 }
163 }
164
165 static void cpu_kick_irq(SPARCCPU *cpu)
166 {
167 CPUSPARCState *env = &cpu->env;
168 CPUState *cs = CPU(cpu);
169
170 cs->halted = 0;
171 cpu_check_irqs(env);
172 qemu_cpu_kick(cs);
173 }
174
175 static void cpu_set_irq(void *opaque, int irq, int level)
176 {
177 SPARCCPU *cpu = opaque;
178 CPUSPARCState *env = &cpu->env;
179
180 if (level) {
181 trace_sun4m_cpu_set_irq_raise(irq);
182 env->pil_in |= 1 << irq;
183 cpu_kick_irq(cpu);
184 } else {
185 trace_sun4m_cpu_set_irq_lower(irq);
186 env->pil_in &= ~(1 << irq);
187 cpu_check_irqs(env);
188 }
189 }
190
191 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
192 {
193 }
194
195 static void main_cpu_reset(void *opaque)
196 {
197 SPARCCPU *cpu = opaque;
198 CPUState *cs = CPU(cpu);
199
200 cpu_reset(cs);
201 cs->halted = 0;
202 }
203
204 static void secondary_cpu_reset(void *opaque)
205 {
206 SPARCCPU *cpu = opaque;
207 CPUState *cs = CPU(cpu);
208
209 cpu_reset(cs);
210 cs->halted = 1;
211 }
212
213 static void cpu_halt_signal(void *opaque, int irq, int level)
214 {
215 if (level && current_cpu) {
216 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
217 }
218 }
219
220 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
221 {
222 return addr - 0xf0000000ULL;
223 }
224
225 static unsigned long sun4m_load_kernel(const char *kernel_filename,
226 const char *initrd_filename,
227 ram_addr_t RAM_size)
228 {
229 int linux_boot;
230 unsigned int i;
231 long initrd_size, kernel_size;
232 uint8_t *ptr;
233
234 linux_boot = (kernel_filename != NULL);
235
236 kernel_size = 0;
237 if (linux_boot) {
238 int bswap_needed;
239
240 #ifdef BSWAP_NEEDED
241 bswap_needed = 1;
242 #else
243 bswap_needed = 0;
244 #endif
245 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
246 NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
247 if (kernel_size < 0)
248 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
249 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
250 TARGET_PAGE_SIZE);
251 if (kernel_size < 0)
252 kernel_size = load_image_targphys(kernel_filename,
253 KERNEL_LOAD_ADDR,
254 RAM_size - KERNEL_LOAD_ADDR);
255 if (kernel_size < 0) {
256 error_report("could not load kernel '%s'", kernel_filename);
257 exit(1);
258 }
259
260 /* load initrd */
261 initrd_size = 0;
262 if (initrd_filename) {
263 initrd_size = load_image_targphys(initrd_filename,
264 INITRD_LOAD_ADDR,
265 RAM_size - INITRD_LOAD_ADDR);
266 if (initrd_size < 0) {
267 error_report("could not load initial ram disk '%s'",
268 initrd_filename);
269 exit(1);
270 }
271 }
272 if (initrd_size > 0) {
273 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
274 ptr = rom_ptr(KERNEL_LOAD_ADDR + i, 24);
275 if (ptr && ldl_p(ptr) == 0x48647253) { /* HdrS */
276 stl_p(ptr + 16, INITRD_LOAD_ADDR);
277 stl_p(ptr + 20, initrd_size);
278 break;
279 }
280 }
281 }
282 }
283 return kernel_size;
284 }
285
286 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
287 {
288 DeviceState *dev;
289 SysBusDevice *s;
290
291 dev = qdev_create(NULL, TYPE_SUN4M_IOMMU);
292 qdev_prop_set_uint32(dev, "version", version);
293 qdev_init_nofail(dev);
294 s = SYS_BUS_DEVICE(dev);
295 sysbus_connect_irq(s, 0, irq);
296 sysbus_mmio_map(s, 0, addr);
297
298 return s;
299 }
300
301 static void *sparc32_dma_init(hwaddr dma_base,
302 hwaddr esp_base, qemu_irq espdma_irq,
303 hwaddr le_base, qemu_irq ledma_irq)
304 {
305 DeviceState *dma;
306 ESPDMADeviceState *espdma;
307 LEDMADeviceState *ledma;
308 SysBusESPState *esp;
309 SysBusPCNetState *lance;
310
311 dma = qdev_create(NULL, TYPE_SPARC32_DMA);
312 qdev_init_nofail(dma);
313 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base);
314
315 espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component(
316 OBJECT(dma), "espdma"));
317 sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq);
318
319 esp = ESP_STATE(object_resolve_path_component(OBJECT(espdma), "esp"));
320 sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base);
321 scsi_bus_legacy_handle_cmdline(&esp->esp.bus);
322
323 ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component(
324 OBJECT(dma), "ledma"));
325 sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq);
326
327 lance = SYSBUS_PCNET(object_resolve_path_component(
328 OBJECT(ledma), "lance"));
329 sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base);
330
331 return dma;
332 }
333
334 static DeviceState *slavio_intctl_init(hwaddr addr,
335 hwaddr addrg,
336 qemu_irq **parent_irq)
337 {
338 DeviceState *dev;
339 SysBusDevice *s;
340 unsigned int i, j;
341
342 dev = qdev_create(NULL, "slavio_intctl");
343 qdev_init_nofail(dev);
344
345 s = SYS_BUS_DEVICE(dev);
346
347 for (i = 0; i < MAX_CPUS; i++) {
348 for (j = 0; j < MAX_PILS; j++) {
349 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
350 }
351 }
352 sysbus_mmio_map(s, 0, addrg);
353 for (i = 0; i < MAX_CPUS; i++) {
354 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
355 }
356
357 return dev;
358 }
359
360 #define SYS_TIMER_OFFSET 0x10000ULL
361 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
362
363 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
364 qemu_irq *cpu_irqs, unsigned int num_cpus)
365 {
366 DeviceState *dev;
367 SysBusDevice *s;
368 unsigned int i;
369
370 dev = qdev_create(NULL, "slavio_timer");
371 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
372 qdev_init_nofail(dev);
373 s = SYS_BUS_DEVICE(dev);
374 sysbus_connect_irq(s, 0, master_irq);
375 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
376
377 for (i = 0; i < MAX_CPUS; i++) {
378 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
379 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
380 }
381 }
382
383 static qemu_irq slavio_system_powerdown;
384
385 static void slavio_powerdown_req(Notifier *n, void *opaque)
386 {
387 qemu_irq_raise(slavio_system_powerdown);
388 }
389
390 static Notifier slavio_system_powerdown_notifier = {
391 .notify = slavio_powerdown_req
392 };
393
394 #define MISC_LEDS 0x01600000
395 #define MISC_CFG 0x01800000
396 #define MISC_DIAG 0x01a00000
397 #define MISC_MDM 0x01b00000
398 #define MISC_SYS 0x01f00000
399
400 static void slavio_misc_init(hwaddr base,
401 hwaddr aux1_base,
402 hwaddr aux2_base, qemu_irq irq,
403 qemu_irq fdc_tc)
404 {
405 DeviceState *dev;
406 SysBusDevice *s;
407
408 dev = qdev_create(NULL, "slavio_misc");
409 qdev_init_nofail(dev);
410 s = SYS_BUS_DEVICE(dev);
411 if (base) {
412 /* 8 bit registers */
413 /* Slavio control */
414 sysbus_mmio_map(s, 0, base + MISC_CFG);
415 /* Diagnostics */
416 sysbus_mmio_map(s, 1, base + MISC_DIAG);
417 /* Modem control */
418 sysbus_mmio_map(s, 2, base + MISC_MDM);
419 /* 16 bit registers */
420 /* ss600mp diag LEDs */
421 sysbus_mmio_map(s, 3, base + MISC_LEDS);
422 /* 32 bit registers */
423 /* System control */
424 sysbus_mmio_map(s, 4, base + MISC_SYS);
425 }
426 if (aux1_base) {
427 /* AUX 1 (Misc System Functions) */
428 sysbus_mmio_map(s, 5, aux1_base);
429 }
430 if (aux2_base) {
431 /* AUX 2 (Software Powerdown Control) */
432 sysbus_mmio_map(s, 6, aux2_base);
433 }
434 sysbus_connect_irq(s, 0, irq);
435 sysbus_connect_irq(s, 1, fdc_tc);
436 slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
437 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
438 }
439
440 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
441 {
442 DeviceState *dev;
443 SysBusDevice *s;
444
445 dev = qdev_create(NULL, "eccmemctl");
446 qdev_prop_set_uint32(dev, "version", version);
447 qdev_init_nofail(dev);
448 s = SYS_BUS_DEVICE(dev);
449 sysbus_connect_irq(s, 0, irq);
450 sysbus_mmio_map(s, 0, base);
451 if (version == 0) { // SS-600MP only
452 sysbus_mmio_map(s, 1, base + 0x1000);
453 }
454 }
455
456 static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
457 {
458 DeviceState *dev;
459 SysBusDevice *s;
460
461 dev = qdev_create(NULL, "apc");
462 qdev_init_nofail(dev);
463 s = SYS_BUS_DEVICE(dev);
464 /* Power management (APC) XXX: not a Slavio device */
465 sysbus_mmio_map(s, 0, power_base);
466 sysbus_connect_irq(s, 0, cpu_halt);
467 }
468
469 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
470 int height, int depth)
471 {
472 DeviceState *dev;
473 SysBusDevice *s;
474
475 dev = qdev_create(NULL, "SUNW,tcx");
476 qdev_prop_set_uint32(dev, "vram_size", vram_size);
477 qdev_prop_set_uint16(dev, "width", width);
478 qdev_prop_set_uint16(dev, "height", height);
479 qdev_prop_set_uint16(dev, "depth", depth);
480 qdev_init_nofail(dev);
481 s = SYS_BUS_DEVICE(dev);
482
483 /* 10/ROM : FCode ROM */
484 sysbus_mmio_map(s, 0, addr);
485 /* 2/STIP : Stipple */
486 sysbus_mmio_map(s, 1, addr + 0x04000000ULL);
487 /* 3/BLIT : Blitter */
488 sysbus_mmio_map(s, 2, addr + 0x06000000ULL);
489 /* 5/RSTIP : Raw Stipple */
490 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL);
491 /* 6/RBLIT : Raw Blitter */
492 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL);
493 /* 7/TEC : Transform Engine */
494 sysbus_mmio_map(s, 5, addr + 0x00700000ULL);
495 /* 8/CMAP : DAC */
496 sysbus_mmio_map(s, 6, addr + 0x00200000ULL);
497 /* 9/THC : */
498 if (depth == 8) {
499 sysbus_mmio_map(s, 7, addr + 0x00300000ULL);
500 } else {
501 sysbus_mmio_map(s, 7, addr + 0x00301000ULL);
502 }
503 /* 11/DHC : */
504 sysbus_mmio_map(s, 8, addr + 0x00240000ULL);
505 /* 12/ALT : */
506 sysbus_mmio_map(s, 9, addr + 0x00280000ULL);
507 /* 0/DFB8 : 8-bit plane */
508 sysbus_mmio_map(s, 10, addr + 0x00800000ULL);
509 /* 1/DFB24 : 24bit plane */
510 sysbus_mmio_map(s, 11, addr + 0x02000000ULL);
511 /* 4/RDFB32: Raw framebuffer. Control plane */
512 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL);
513 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
514 if (depth == 8) {
515 sysbus_mmio_map(s, 13, addr + 0x00301000ULL);
516 }
517
518 sysbus_connect_irq(s, 0, irq);
519 }
520
521 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
522 int height, int depth)
523 {
524 DeviceState *dev;
525 SysBusDevice *s;
526
527 dev = qdev_create(NULL, "cgthree");
528 qdev_prop_set_uint32(dev, "vram-size", vram_size);
529 qdev_prop_set_uint16(dev, "width", width);
530 qdev_prop_set_uint16(dev, "height", height);
531 qdev_prop_set_uint16(dev, "depth", depth);
532 qdev_init_nofail(dev);
533 s = SYS_BUS_DEVICE(dev);
534
535 /* FCode ROM */
536 sysbus_mmio_map(s, 0, addr);
537 /* DAC */
538 sysbus_mmio_map(s, 1, addr + 0x400000ULL);
539 /* 8-bit plane */
540 sysbus_mmio_map(s, 2, addr + 0x800000ULL);
541
542 sysbus_connect_irq(s, 0, irq);
543 }
544
545 /* NCR89C100/MACIO Internal ID register */
546
547 #define TYPE_MACIO_ID_REGISTER "macio_idreg"
548
549 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
550
551 static void idreg_init(hwaddr addr)
552 {
553 DeviceState *dev;
554 SysBusDevice *s;
555
556 dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER);
557 qdev_init_nofail(dev);
558 s = SYS_BUS_DEVICE(dev);
559
560 sysbus_mmio_map(s, 0, addr);
561 address_space_write_rom(&address_space_memory, addr,
562 MEMTXATTRS_UNSPECIFIED,
563 idreg_data, sizeof(idreg_data));
564 }
565
566 #define MACIO_ID_REGISTER(obj) \
567 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER)
568
569 typedef struct IDRegState {
570 SysBusDevice parent_obj;
571
572 MemoryRegion mem;
573 } IDRegState;
574
575 static void idreg_realize(DeviceState *ds, Error **errp)
576 {
577 IDRegState *s = MACIO_ID_REGISTER(ds);
578 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
579 Error *local_err = NULL;
580
581 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.idreg",
582 sizeof(idreg_data), &local_err);
583 if (local_err) {
584 error_propagate(errp, local_err);
585 return;
586 }
587
588 vmstate_register_ram_global(&s->mem);
589 memory_region_set_readonly(&s->mem, true);
590 sysbus_init_mmio(dev, &s->mem);
591 }
592
593 static void idreg_class_init(ObjectClass *oc, void *data)
594 {
595 DeviceClass *dc = DEVICE_CLASS(oc);
596
597 dc->realize = idreg_realize;
598 }
599
600 static const TypeInfo idreg_info = {
601 .name = TYPE_MACIO_ID_REGISTER,
602 .parent = TYPE_SYS_BUS_DEVICE,
603 .instance_size = sizeof(IDRegState),
604 .class_init = idreg_class_init,
605 };
606
607 #define TYPE_TCX_AFX "tcx_afx"
608 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX)
609
610 typedef struct AFXState {
611 SysBusDevice parent_obj;
612
613 MemoryRegion mem;
614 } AFXState;
615
616 /* SS-5 TCX AFX register */
617 static void afx_init(hwaddr addr)
618 {
619 DeviceState *dev;
620 SysBusDevice *s;
621
622 dev = qdev_create(NULL, TYPE_TCX_AFX);
623 qdev_init_nofail(dev);
624 s = SYS_BUS_DEVICE(dev);
625
626 sysbus_mmio_map(s, 0, addr);
627 }
628
629 static void afx_realize(DeviceState *ds, Error **errp)
630 {
631 AFXState *s = TCX_AFX(ds);
632 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
633 Error *local_err = NULL;
634
635 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.afx", 4,
636 &local_err);
637 if (local_err) {
638 error_propagate(errp, local_err);
639 return;
640 }
641
642 vmstate_register_ram_global(&s->mem);
643 sysbus_init_mmio(dev, &s->mem);
644 }
645
646 static void afx_class_init(ObjectClass *oc, void *data)
647 {
648 DeviceClass *dc = DEVICE_CLASS(oc);
649
650 dc->realize = afx_realize;
651 }
652
653 static const TypeInfo afx_info = {
654 .name = TYPE_TCX_AFX,
655 .parent = TYPE_SYS_BUS_DEVICE,
656 .instance_size = sizeof(AFXState),
657 .class_init = afx_class_init,
658 };
659
660 #define TYPE_OPENPROM "openprom"
661 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
662
663 typedef struct PROMState {
664 SysBusDevice parent_obj;
665
666 MemoryRegion prom;
667 } PROMState;
668
669 /* Boot PROM (OpenBIOS) */
670 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
671 {
672 hwaddr *base_addr = (hwaddr *)opaque;
673 return addr + *base_addr - PROM_VADDR;
674 }
675
676 static void prom_init(hwaddr addr, const char *bios_name)
677 {
678 DeviceState *dev;
679 SysBusDevice *s;
680 char *filename;
681 int ret;
682
683 dev = qdev_create(NULL, TYPE_OPENPROM);
684 qdev_init_nofail(dev);
685 s = SYS_BUS_DEVICE(dev);
686
687 sysbus_mmio_map(s, 0, addr);
688
689 /* load boot prom */
690 if (bios_name == NULL) {
691 bios_name = PROM_FILENAME;
692 }
693 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
694 if (filename) {
695 ret = load_elf(filename, translate_prom_address, &addr, NULL,
696 NULL, NULL, 1, EM_SPARC, 0, 0);
697 if (ret < 0 || ret > PROM_SIZE_MAX) {
698 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
699 }
700 g_free(filename);
701 } else {
702 ret = -1;
703 }
704 if (ret < 0 || ret > PROM_SIZE_MAX) {
705 error_report("could not load prom '%s'", bios_name);
706 exit(1);
707 }
708 }
709
710 static void prom_realize(DeviceState *ds, Error **errp)
711 {
712 PROMState *s = OPENPROM(ds);
713 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
714 Error *local_err = NULL;
715
716 memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4m.prom",
717 PROM_SIZE_MAX, &local_err);
718 if (local_err) {
719 error_propagate(errp, local_err);
720 return;
721 }
722
723 vmstate_register_ram_global(&s->prom);
724 memory_region_set_readonly(&s->prom, true);
725 sysbus_init_mmio(dev, &s->prom);
726 }
727
728 static Property prom_properties[] = {
729 {/* end of property list */},
730 };
731
732 static void prom_class_init(ObjectClass *klass, void *data)
733 {
734 DeviceClass *dc = DEVICE_CLASS(klass);
735
736 dc->props = prom_properties;
737 dc->realize = prom_realize;
738 }
739
740 static const TypeInfo prom_info = {
741 .name = TYPE_OPENPROM,
742 .parent = TYPE_SYS_BUS_DEVICE,
743 .instance_size = sizeof(PROMState),
744 .class_init = prom_class_init,
745 };
746
747 #define TYPE_SUN4M_MEMORY "memory"
748 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY)
749
750 typedef struct RamDevice {
751 SysBusDevice parent_obj;
752
753 MemoryRegion ram;
754 uint64_t size;
755 } RamDevice;
756
757 /* System RAM */
758 static void ram_realize(DeviceState *dev, Error **errp)
759 {
760 RamDevice *d = SUN4M_RAM(dev);
761 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
762
763 memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram",
764 d->size);
765 sysbus_init_mmio(sbd, &d->ram);
766 }
767
768 static void ram_init(hwaddr addr, ram_addr_t RAM_size,
769 uint64_t max_mem)
770 {
771 DeviceState *dev;
772 SysBusDevice *s;
773 RamDevice *d;
774
775 /* allocate RAM */
776 if ((uint64_t)RAM_size > max_mem) {
777 error_report("Too much memory for this machine: %" PRId64 ","
778 " maximum %" PRId64,
779 RAM_size / MiB, max_mem / MiB);
780 exit(1);
781 }
782 dev = qdev_create(NULL, "memory");
783 s = SYS_BUS_DEVICE(dev);
784
785 d = SUN4M_RAM(dev);
786 d->size = RAM_size;
787 qdev_init_nofail(dev);
788
789 sysbus_mmio_map(s, 0, addr);
790 }
791
792 static Property ram_properties[] = {
793 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
794 DEFINE_PROP_END_OF_LIST(),
795 };
796
797 static void ram_class_init(ObjectClass *klass, void *data)
798 {
799 DeviceClass *dc = DEVICE_CLASS(klass);
800
801 dc->realize = ram_realize;
802 dc->props = ram_properties;
803 }
804
805 static const TypeInfo ram_info = {
806 .name = TYPE_SUN4M_MEMORY,
807 .parent = TYPE_SYS_BUS_DEVICE,
808 .instance_size = sizeof(RamDevice),
809 .class_init = ram_class_init,
810 };
811
812 static void cpu_devinit(const char *cpu_type, unsigned int id,
813 uint64_t prom_addr, qemu_irq **cpu_irqs)
814 {
815 CPUState *cs;
816 SPARCCPU *cpu;
817 CPUSPARCState *env;
818
819 cpu = SPARC_CPU(cpu_create(cpu_type));
820 env = &cpu->env;
821
822 cpu_sparc_set_id(env, id);
823 if (id == 0) {
824 qemu_register_reset(main_cpu_reset, cpu);
825 } else {
826 qemu_register_reset(secondary_cpu_reset, cpu);
827 cs = CPU(cpu);
828 cs->halted = 1;
829 }
830 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
831 env->prom_addr = prom_addr;
832 }
833
834 static void dummy_fdc_tc(void *opaque, int irq, int level)
835 {
836 }
837
838 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
839 MachineState *machine)
840 {
841 DeviceState *slavio_intctl;
842 unsigned int i;
843 void *nvram;
844 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS];
845 qemu_irq fdc_tc;
846 unsigned long kernel_size;
847 DriveInfo *fd[MAX_FD];
848 FWCfgState *fw_cfg;
849 unsigned int num_vsimms;
850 DeviceState *dev;
851 SysBusDevice *s;
852
853 /* init CPUs */
854 for(i = 0; i < smp_cpus; i++) {
855 cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]);
856 }
857
858 for (i = smp_cpus; i < MAX_CPUS; i++)
859 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
860
861
862 /* set up devices */
863 ram_init(0, machine->ram_size, hwdef->max_mem);
864 /* models without ECC don't trap when missing ram is accessed */
865 if (!hwdef->ecc_base) {
866 empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size);
867 }
868
869 prom_init(hwdef->slavio_base, bios_name);
870
871 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
872 hwdef->intctl_base + 0x10000ULL,
873 cpu_irqs);
874
875 for (i = 0; i < 32; i++) {
876 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
877 }
878 for (i = 0; i < MAX_CPUS; i++) {
879 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
880 }
881
882 if (hwdef->idreg_base) {
883 idreg_init(hwdef->idreg_base);
884 }
885
886 if (hwdef->afx_base) {
887 afx_init(hwdef->afx_base);
888 }
889
890 iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]);
891
892 if (hwdef->iommu_pad_base) {
893 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
894 Software shouldn't use aliased addresses, neither should it crash
895 when does. Using empty_slot instead of aliasing can help with
896 debugging such accesses */
897 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
898 }
899
900 sparc32_dma_init(hwdef->dma_base,
901 hwdef->esp_base, slavio_irq[18],
902 hwdef->le_base, slavio_irq[16]);
903
904 if (graphic_depth != 8 && graphic_depth != 24) {
905 error_report("Unsupported depth: %d", graphic_depth);
906 exit (1);
907 }
908 num_vsimms = 0;
909 if (num_vsimms == 0) {
910 if (vga_interface_type == VGA_CG3) {
911 if (graphic_depth != 8) {
912 error_report("Unsupported depth: %d", graphic_depth);
913 exit(1);
914 }
915
916 if (!(graphic_width == 1024 && graphic_height == 768) &&
917 !(graphic_width == 1152 && graphic_height == 900)) {
918 error_report("Unsupported resolution: %d x %d", graphic_width,
919 graphic_height);
920 exit(1);
921 }
922
923 /* sbus irq 5 */
924 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
925 graphic_width, graphic_height, graphic_depth);
926 } else {
927 /* If no display specified, default to TCX */
928 if (graphic_depth != 8 && graphic_depth != 24) {
929 error_report("Unsupported depth: %d", graphic_depth);
930 exit(1);
931 }
932
933 if (!(graphic_width == 1024 && graphic_height == 768)) {
934 error_report("Unsupported resolution: %d x %d",
935 graphic_width, graphic_height);
936 exit(1);
937 }
938
939 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
940 graphic_width, graphic_height, graphic_depth);
941 }
942 }
943
944 for (i = num_vsimms; i < MAX_VSIMMS; i++) {
945 /* vsimm registers probed by OBP */
946 if (hwdef->vsimm[i].reg_base) {
947 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
948 }
949 }
950
951 if (hwdef->sx_base) {
952 empty_slot_init(hwdef->sx_base, 0x2000);
953 }
954
955 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8);
956
957 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
958
959 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
960 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
961 dev = qdev_create(NULL, TYPE_ESCC);
962 qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics);
963 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
964 qdev_prop_set_uint32(dev, "it_shift", 1);
965 qdev_prop_set_chr(dev, "chrB", NULL);
966 qdev_prop_set_chr(dev, "chrA", NULL);
967 qdev_prop_set_uint32(dev, "chnBtype", escc_mouse);
968 qdev_prop_set_uint32(dev, "chnAtype", escc_kbd);
969 qdev_init_nofail(dev);
970 s = SYS_BUS_DEVICE(dev);
971 sysbus_connect_irq(s, 0, slavio_irq[14]);
972 sysbus_connect_irq(s, 1, slavio_irq[14]);
973 sysbus_mmio_map(s, 0, hwdef->ms_kb_base);
974
975 dev = qdev_create(NULL, TYPE_ESCC);
976 qdev_prop_set_uint32(dev, "disabled", 0);
977 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
978 qdev_prop_set_uint32(dev, "it_shift", 1);
979 qdev_prop_set_chr(dev, "chrB", serial_hd(1));
980 qdev_prop_set_chr(dev, "chrA", serial_hd(0));
981 qdev_prop_set_uint32(dev, "chnBtype", escc_serial);
982 qdev_prop_set_uint32(dev, "chnAtype", escc_serial);
983 qdev_init_nofail(dev);
984
985 s = SYS_BUS_DEVICE(dev);
986 sysbus_connect_irq(s, 0, slavio_irq[15]);
987 sysbus_connect_irq(s, 1, slavio_irq[15]);
988 sysbus_mmio_map(s, 0, hwdef->serial_base);
989
990 if (hwdef->apc_base) {
991 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0));
992 }
993
994 if (hwdef->fd_base) {
995 /* there is zero or one floppy drive */
996 memset(fd, 0, sizeof(fd));
997 fd[0] = drive_get(IF_FLOPPY, 0, 0);
998 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
999 &fdc_tc);
1000 } else {
1001 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0);
1002 }
1003
1004 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
1005 slavio_irq[30], fdc_tc);
1006
1007 if (hwdef->cs_base) {
1008 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
1009 slavio_irq[5]);
1010 }
1011
1012 if (hwdef->dbri_base) {
1013 /* ISDN chip with attached CS4215 audio codec */
1014 /* prom space */
1015 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
1016 /* reg space */
1017 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
1018 }
1019
1020 if (hwdef->bpp_base) {
1021 /* parallel port */
1022 empty_slot_init(hwdef->bpp_base, 0x20);
1023 }
1024
1025 kernel_size = sun4m_load_kernel(machine->kernel_filename,
1026 machine->initrd_filename,
1027 machine->ram_size);
1028
1029 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline,
1030 machine->boot_order, machine->ram_size, kernel_size,
1031 graphic_width, graphic_height, graphic_depth,
1032 hwdef->nvram_machine_id, "Sun4m");
1033
1034 if (hwdef->ecc_base)
1035 ecc_init(hwdef->ecc_base, slavio_irq[28],
1036 hwdef->ecc_version);
1037
1038 dev = qdev_create(NULL, TYPE_FW_CFG_MEM);
1039 fw_cfg = FW_CFG(dev);
1040 qdev_prop_set_uint32(dev, "data_width", 1);
1041 qdev_prop_set_bit(dev, "dma_enabled", false);
1042 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
1043 OBJECT(fw_cfg), NULL);
1044 qdev_init_nofail(dev);
1045 s = SYS_BUS_DEVICE(dev);
1046 sysbus_mmio_map(s, 0, CFG_ADDR);
1047 sysbus_mmio_map(s, 1, CFG_ADDR + 2);
1048
1049 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
1050 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1051 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1052 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1053 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1054 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width);
1055 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height);
1056 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1057 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1058 if (machine->kernel_cmdline) {
1059 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1060 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
1061 machine->kernel_cmdline);
1062 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
1063 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1064 strlen(machine->kernel_cmdline) + 1);
1065 } else {
1066 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1067 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1068 }
1069 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1070 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1071 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
1072 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1073 }
1074
1075 enum {
1076 ss5_id = 32,
1077 vger_id,
1078 lx_id,
1079 ss4_id,
1080 scls_id,
1081 sbook_id,
1082 ss10_id = 64,
1083 ss20_id,
1084 ss600mp_id,
1085 };
1086
1087 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1088 /* SS-5 */
1089 {
1090 .iommu_base = 0x10000000,
1091 .iommu_pad_base = 0x10004000,
1092 .iommu_pad_len = 0x0fffb000,
1093 .tcx_base = 0x50000000,
1094 .cs_base = 0x6c000000,
1095 .slavio_base = 0x70000000,
1096 .ms_kb_base = 0x71000000,
1097 .serial_base = 0x71100000,
1098 .nvram_base = 0x71200000,
1099 .fd_base = 0x71400000,
1100 .counter_base = 0x71d00000,
1101 .intctl_base = 0x71e00000,
1102 .idreg_base = 0x78000000,
1103 .dma_base = 0x78400000,
1104 .esp_base = 0x78800000,
1105 .le_base = 0x78c00000,
1106 .apc_base = 0x6a000000,
1107 .afx_base = 0x6e000000,
1108 .aux1_base = 0x71900000,
1109 .aux2_base = 0x71910000,
1110 .nvram_machine_id = 0x80,
1111 .machine_id = ss5_id,
1112 .iommu_version = 0x05000000,
1113 .max_mem = 0x10000000,
1114 },
1115 /* SS-10 */
1116 {
1117 .iommu_base = 0xfe0000000ULL,
1118 .tcx_base = 0xe20000000ULL,
1119 .slavio_base = 0xff0000000ULL,
1120 .ms_kb_base = 0xff1000000ULL,
1121 .serial_base = 0xff1100000ULL,
1122 .nvram_base = 0xff1200000ULL,
1123 .fd_base = 0xff1700000ULL,
1124 .counter_base = 0xff1300000ULL,
1125 .intctl_base = 0xff1400000ULL,
1126 .idreg_base = 0xef0000000ULL,
1127 .dma_base = 0xef0400000ULL,
1128 .esp_base = 0xef0800000ULL,
1129 .le_base = 0xef0c00000ULL,
1130 .apc_base = 0xefa000000ULL, // XXX should not exist
1131 .aux1_base = 0xff1800000ULL,
1132 .aux2_base = 0xff1a01000ULL,
1133 .ecc_base = 0xf00000000ULL,
1134 .ecc_version = 0x10000000, // version 0, implementation 1
1135 .nvram_machine_id = 0x72,
1136 .machine_id = ss10_id,
1137 .iommu_version = 0x03000000,
1138 .max_mem = 0xf00000000ULL,
1139 },
1140 /* SS-600MP */
1141 {
1142 .iommu_base = 0xfe0000000ULL,
1143 .tcx_base = 0xe20000000ULL,
1144 .slavio_base = 0xff0000000ULL,
1145 .ms_kb_base = 0xff1000000ULL,
1146 .serial_base = 0xff1100000ULL,
1147 .nvram_base = 0xff1200000ULL,
1148 .counter_base = 0xff1300000ULL,
1149 .intctl_base = 0xff1400000ULL,
1150 .dma_base = 0xef0081000ULL,
1151 .esp_base = 0xef0080000ULL,
1152 .le_base = 0xef0060000ULL,
1153 .apc_base = 0xefa000000ULL, // XXX should not exist
1154 .aux1_base = 0xff1800000ULL,
1155 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1156 .ecc_base = 0xf00000000ULL,
1157 .ecc_version = 0x00000000, // version 0, implementation 0
1158 .nvram_machine_id = 0x71,
1159 .machine_id = ss600mp_id,
1160 .iommu_version = 0x01000000,
1161 .max_mem = 0xf00000000ULL,
1162 },
1163 /* SS-20 */
1164 {
1165 .iommu_base = 0xfe0000000ULL,
1166 .tcx_base = 0xe20000000ULL,
1167 .slavio_base = 0xff0000000ULL,
1168 .ms_kb_base = 0xff1000000ULL,
1169 .serial_base = 0xff1100000ULL,
1170 .nvram_base = 0xff1200000ULL,
1171 .fd_base = 0xff1700000ULL,
1172 .counter_base = 0xff1300000ULL,
1173 .intctl_base = 0xff1400000ULL,
1174 .idreg_base = 0xef0000000ULL,
1175 .dma_base = 0xef0400000ULL,
1176 .esp_base = 0xef0800000ULL,
1177 .le_base = 0xef0c00000ULL,
1178 .bpp_base = 0xef4800000ULL,
1179 .apc_base = 0xefa000000ULL, // XXX should not exist
1180 .aux1_base = 0xff1800000ULL,
1181 .aux2_base = 0xff1a01000ULL,
1182 .dbri_base = 0xee0000000ULL,
1183 .sx_base = 0xf80000000ULL,
1184 .vsimm = {
1185 {
1186 .reg_base = 0x9c000000ULL,
1187 .vram_base = 0xfc000000ULL
1188 }, {
1189 .reg_base = 0x90000000ULL,
1190 .vram_base = 0xf0000000ULL
1191 }, {
1192 .reg_base = 0x94000000ULL
1193 }, {
1194 .reg_base = 0x98000000ULL
1195 }
1196 },
1197 .ecc_base = 0xf00000000ULL,
1198 .ecc_version = 0x20000000, // version 0, implementation 2
1199 .nvram_machine_id = 0x72,
1200 .machine_id = ss20_id,
1201 .iommu_version = 0x13000000,
1202 .max_mem = 0xf00000000ULL,
1203 },
1204 /* Voyager */
1205 {
1206 .iommu_base = 0x10000000,
1207 .tcx_base = 0x50000000,
1208 .slavio_base = 0x70000000,
1209 .ms_kb_base = 0x71000000,
1210 .serial_base = 0x71100000,
1211 .nvram_base = 0x71200000,
1212 .fd_base = 0x71400000,
1213 .counter_base = 0x71d00000,
1214 .intctl_base = 0x71e00000,
1215 .idreg_base = 0x78000000,
1216 .dma_base = 0x78400000,
1217 .esp_base = 0x78800000,
1218 .le_base = 0x78c00000,
1219 .apc_base = 0x71300000, // pmc
1220 .aux1_base = 0x71900000,
1221 .aux2_base = 0x71910000,
1222 .nvram_machine_id = 0x80,
1223 .machine_id = vger_id,
1224 .iommu_version = 0x05000000,
1225 .max_mem = 0x10000000,
1226 },
1227 /* LX */
1228 {
1229 .iommu_base = 0x10000000,
1230 .iommu_pad_base = 0x10004000,
1231 .iommu_pad_len = 0x0fffb000,
1232 .tcx_base = 0x50000000,
1233 .slavio_base = 0x70000000,
1234 .ms_kb_base = 0x71000000,
1235 .serial_base = 0x71100000,
1236 .nvram_base = 0x71200000,
1237 .fd_base = 0x71400000,
1238 .counter_base = 0x71d00000,
1239 .intctl_base = 0x71e00000,
1240 .idreg_base = 0x78000000,
1241 .dma_base = 0x78400000,
1242 .esp_base = 0x78800000,
1243 .le_base = 0x78c00000,
1244 .aux1_base = 0x71900000,
1245 .aux2_base = 0x71910000,
1246 .nvram_machine_id = 0x80,
1247 .machine_id = lx_id,
1248 .iommu_version = 0x04000000,
1249 .max_mem = 0x10000000,
1250 },
1251 /* SS-4 */
1252 {
1253 .iommu_base = 0x10000000,
1254 .tcx_base = 0x50000000,
1255 .cs_base = 0x6c000000,
1256 .slavio_base = 0x70000000,
1257 .ms_kb_base = 0x71000000,
1258 .serial_base = 0x71100000,
1259 .nvram_base = 0x71200000,
1260 .fd_base = 0x71400000,
1261 .counter_base = 0x71d00000,
1262 .intctl_base = 0x71e00000,
1263 .idreg_base = 0x78000000,
1264 .dma_base = 0x78400000,
1265 .esp_base = 0x78800000,
1266 .le_base = 0x78c00000,
1267 .apc_base = 0x6a000000,
1268 .aux1_base = 0x71900000,
1269 .aux2_base = 0x71910000,
1270 .nvram_machine_id = 0x80,
1271 .machine_id = ss4_id,
1272 .iommu_version = 0x05000000,
1273 .max_mem = 0x10000000,
1274 },
1275 /* SPARCClassic */
1276 {
1277 .iommu_base = 0x10000000,
1278 .tcx_base = 0x50000000,
1279 .slavio_base = 0x70000000,
1280 .ms_kb_base = 0x71000000,
1281 .serial_base = 0x71100000,
1282 .nvram_base = 0x71200000,
1283 .fd_base = 0x71400000,
1284 .counter_base = 0x71d00000,
1285 .intctl_base = 0x71e00000,
1286 .idreg_base = 0x78000000,
1287 .dma_base = 0x78400000,
1288 .esp_base = 0x78800000,
1289 .le_base = 0x78c00000,
1290 .apc_base = 0x6a000000,
1291 .aux1_base = 0x71900000,
1292 .aux2_base = 0x71910000,
1293 .nvram_machine_id = 0x80,
1294 .machine_id = scls_id,
1295 .iommu_version = 0x05000000,
1296 .max_mem = 0x10000000,
1297 },
1298 /* SPARCbook */
1299 {
1300 .iommu_base = 0x10000000,
1301 .tcx_base = 0x50000000, // XXX
1302 .slavio_base = 0x70000000,
1303 .ms_kb_base = 0x71000000,
1304 .serial_base = 0x71100000,
1305 .nvram_base = 0x71200000,
1306 .fd_base = 0x71400000,
1307 .counter_base = 0x71d00000,
1308 .intctl_base = 0x71e00000,
1309 .idreg_base = 0x78000000,
1310 .dma_base = 0x78400000,
1311 .esp_base = 0x78800000,
1312 .le_base = 0x78c00000,
1313 .apc_base = 0x6a000000,
1314 .aux1_base = 0x71900000,
1315 .aux2_base = 0x71910000,
1316 .nvram_machine_id = 0x80,
1317 .machine_id = sbook_id,
1318 .iommu_version = 0x05000000,
1319 .max_mem = 0x10000000,
1320 },
1321 };
1322
1323 /* SPARCstation 5 hardware initialisation */
1324 static void ss5_init(MachineState *machine)
1325 {
1326 sun4m_hw_init(&sun4m_hwdefs[0], machine);
1327 }
1328
1329 /* SPARCstation 10 hardware initialisation */
1330 static void ss10_init(MachineState *machine)
1331 {
1332 sun4m_hw_init(&sun4m_hwdefs[1], machine);
1333 }
1334
1335 /* SPARCserver 600MP hardware initialisation */
1336 static void ss600mp_init(MachineState *machine)
1337 {
1338 sun4m_hw_init(&sun4m_hwdefs[2], machine);
1339 }
1340
1341 /* SPARCstation 20 hardware initialisation */
1342 static void ss20_init(MachineState *machine)
1343 {
1344 sun4m_hw_init(&sun4m_hwdefs[3], machine);
1345 }
1346
1347 /* SPARCstation Voyager hardware initialisation */
1348 static void vger_init(MachineState *machine)
1349 {
1350 sun4m_hw_init(&sun4m_hwdefs[4], machine);
1351 }
1352
1353 /* SPARCstation LX hardware initialisation */
1354 static void ss_lx_init(MachineState *machine)
1355 {
1356 sun4m_hw_init(&sun4m_hwdefs[5], machine);
1357 }
1358
1359 /* SPARCstation 4 hardware initialisation */
1360 static void ss4_init(MachineState *machine)
1361 {
1362 sun4m_hw_init(&sun4m_hwdefs[6], machine);
1363 }
1364
1365 /* SPARCClassic hardware initialisation */
1366 static void scls_init(MachineState *machine)
1367 {
1368 sun4m_hw_init(&sun4m_hwdefs[7], machine);
1369 }
1370
1371 /* SPARCbook hardware initialisation */
1372 static void sbook_init(MachineState *machine)
1373 {
1374 sun4m_hw_init(&sun4m_hwdefs[8], machine);
1375 }
1376
1377 static void ss5_class_init(ObjectClass *oc, void *data)
1378 {
1379 MachineClass *mc = MACHINE_CLASS(oc);
1380
1381 mc->desc = "Sun4m platform, SPARCstation 5";
1382 mc->init = ss5_init;
1383 mc->block_default_type = IF_SCSI;
1384 mc->is_default = 1;
1385 mc->default_boot_order = "c";
1386 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1387 }
1388
1389 static const TypeInfo ss5_type = {
1390 .name = MACHINE_TYPE_NAME("SS-5"),
1391 .parent = TYPE_MACHINE,
1392 .class_init = ss5_class_init,
1393 };
1394
1395 static void ss10_class_init(ObjectClass *oc, void *data)
1396 {
1397 MachineClass *mc = MACHINE_CLASS(oc);
1398
1399 mc->desc = "Sun4m platform, SPARCstation 10";
1400 mc->init = ss10_init;
1401 mc->block_default_type = IF_SCSI;
1402 mc->max_cpus = 4;
1403 mc->default_boot_order = "c";
1404 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1405 }
1406
1407 static const TypeInfo ss10_type = {
1408 .name = MACHINE_TYPE_NAME("SS-10"),
1409 .parent = TYPE_MACHINE,
1410 .class_init = ss10_class_init,
1411 };
1412
1413 static void ss600mp_class_init(ObjectClass *oc, void *data)
1414 {
1415 MachineClass *mc = MACHINE_CLASS(oc);
1416
1417 mc->desc = "Sun4m platform, SPARCserver 600MP";
1418 mc->init = ss600mp_init;
1419 mc->block_default_type = IF_SCSI;
1420 mc->max_cpus = 4;
1421 mc->default_boot_order = "c";
1422 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1423 }
1424
1425 static const TypeInfo ss600mp_type = {
1426 .name = MACHINE_TYPE_NAME("SS-600MP"),
1427 .parent = TYPE_MACHINE,
1428 .class_init = ss600mp_class_init,
1429 };
1430
1431 static void ss20_class_init(ObjectClass *oc, void *data)
1432 {
1433 MachineClass *mc = MACHINE_CLASS(oc);
1434
1435 mc->desc = "Sun4m platform, SPARCstation 20";
1436 mc->init = ss20_init;
1437 mc->block_default_type = IF_SCSI;
1438 mc->max_cpus = 4;
1439 mc->default_boot_order = "c";
1440 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1441 }
1442
1443 static const TypeInfo ss20_type = {
1444 .name = MACHINE_TYPE_NAME("SS-20"),
1445 .parent = TYPE_MACHINE,
1446 .class_init = ss20_class_init,
1447 };
1448
1449 static void voyager_class_init(ObjectClass *oc, void *data)
1450 {
1451 MachineClass *mc = MACHINE_CLASS(oc);
1452
1453 mc->desc = "Sun4m platform, SPARCstation Voyager";
1454 mc->init = vger_init;
1455 mc->block_default_type = IF_SCSI;
1456 mc->default_boot_order = "c";
1457 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1458 }
1459
1460 static const TypeInfo voyager_type = {
1461 .name = MACHINE_TYPE_NAME("Voyager"),
1462 .parent = TYPE_MACHINE,
1463 .class_init = voyager_class_init,
1464 };
1465
1466 static void ss_lx_class_init(ObjectClass *oc, void *data)
1467 {
1468 MachineClass *mc = MACHINE_CLASS(oc);
1469
1470 mc->desc = "Sun4m platform, SPARCstation LX";
1471 mc->init = ss_lx_init;
1472 mc->block_default_type = IF_SCSI;
1473 mc->default_boot_order = "c";
1474 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1475 }
1476
1477 static const TypeInfo ss_lx_type = {
1478 .name = MACHINE_TYPE_NAME("LX"),
1479 .parent = TYPE_MACHINE,
1480 .class_init = ss_lx_class_init,
1481 };
1482
1483 static void ss4_class_init(ObjectClass *oc, void *data)
1484 {
1485 MachineClass *mc = MACHINE_CLASS(oc);
1486
1487 mc->desc = "Sun4m platform, SPARCstation 4";
1488 mc->init = ss4_init;
1489 mc->block_default_type = IF_SCSI;
1490 mc->default_boot_order = "c";
1491 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1492 }
1493
1494 static const TypeInfo ss4_type = {
1495 .name = MACHINE_TYPE_NAME("SS-4"),
1496 .parent = TYPE_MACHINE,
1497 .class_init = ss4_class_init,
1498 };
1499
1500 static void scls_class_init(ObjectClass *oc, void *data)
1501 {
1502 MachineClass *mc = MACHINE_CLASS(oc);
1503
1504 mc->desc = "Sun4m platform, SPARCClassic";
1505 mc->init = scls_init;
1506 mc->block_default_type = IF_SCSI;
1507 mc->default_boot_order = "c";
1508 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1509 }
1510
1511 static const TypeInfo scls_type = {
1512 .name = MACHINE_TYPE_NAME("SPARCClassic"),
1513 .parent = TYPE_MACHINE,
1514 .class_init = scls_class_init,
1515 };
1516
1517 static void sbook_class_init(ObjectClass *oc, void *data)
1518 {
1519 MachineClass *mc = MACHINE_CLASS(oc);
1520
1521 mc->desc = "Sun4m platform, SPARCbook";
1522 mc->init = sbook_init;
1523 mc->block_default_type = IF_SCSI;
1524 mc->default_boot_order = "c";
1525 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1526 }
1527
1528 static const TypeInfo sbook_type = {
1529 .name = MACHINE_TYPE_NAME("SPARCbook"),
1530 .parent = TYPE_MACHINE,
1531 .class_init = sbook_class_init,
1532 };
1533
1534 static void sun4m_register_types(void)
1535 {
1536 type_register_static(&idreg_info);
1537 type_register_static(&afx_info);
1538 type_register_static(&prom_info);
1539 type_register_static(&ram_info);
1540
1541 type_register_static(&ss5_type);
1542 type_register_static(&ss10_type);
1543 type_register_static(&ss600mp_type);
1544 type_register_static(&ss20_type);
1545 type_register_static(&voyager_type);
1546 type_register_static(&ss_lx_type);
1547 type_register_static(&ss4_type);
1548 type_register_static(&scls_type);
1549 type_register_static(&sbook_type);
1550 }
1551
1552 type_init(sun4m_register_types)
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