2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 #include "qemu/osdep.h"
25 #include "qapi/error.h"
26 #include "qemu-common.h"
28 #include "hw/sysbus.h"
29 #include "qemu/error-report.h"
30 #include "qemu/timer.h"
31 #include "hw/sparc/sun4m_iommu.h"
32 #include "hw/timer/m48t59.h"
33 #include "hw/sparc/sparc32_dma.h"
34 #include "hw/block/fdc.h"
35 #include "sysemu/sysemu.h"
37 #include "hw/boards.h"
38 #include "hw/scsi/esp.h"
39 #include "hw/isa/isa.h"
40 #include "hw/nvram/sun_nvram.h"
41 #include "hw/nvram/chrp_nvram.h"
42 #include "hw/nvram/fw_cfg.h"
43 #include "hw/char/escc.h"
44 #include "hw/empty_slot.h"
45 #include "hw/loader.h"
47 #include "sysemu/block-backend.h"
49 #include "qemu/cutils.h"
52 * Sun4m architecture was used in the following machines:
54 * SPARCserver 6xxMP/xx
55 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
56 * SPARCclassic X (4/10)
57 * SPARCstation LX/ZX (4/30)
58 * SPARCstation Voyager
59 * SPARCstation 10/xx, SPARCserver 10/xx
60 * SPARCstation 5, SPARCserver 5
61 * SPARCstation 20/xx, SPARCserver 20
64 * See for example: http://www.sunhelp.org/faq/sunref1.html
67 #define KERNEL_LOAD_ADDR 0x00004000
68 #define CMDLINE_ADDR 0x007ff000
69 #define INITRD_LOAD_ADDR 0x00800000
70 #define PROM_SIZE_MAX (1024 * 1024)
71 #define PROM_VADDR 0xffd00000
72 #define PROM_FILENAME "openbios-sparc32"
73 #define CFG_ADDR 0xd00000510ULL
74 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
75 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
76 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
82 #define ESCC_CLOCK 4915200
85 hwaddr iommu_base
, iommu_pad_base
, iommu_pad_len
, slavio_base
;
86 hwaddr intctl_base
, counter_base
, nvram_base
, ms_kb_base
;
87 hwaddr serial_base
, fd_base
;
88 hwaddr afx_base
, idreg_base
, dma_base
, esp_base
, le_base
;
89 hwaddr tcx_base
, cs_base
, apc_base
, aux1_base
, aux2_base
;
90 hwaddr bpp_base
, dbri_base
, sx_base
;
92 hwaddr reg_base
, vram_base
;
97 uint32_t iommu_version
;
99 uint8_t nvram_machine_id
;
102 void DMA_init(ISABus
*bus
, int high_page_enable
)
106 static void fw_cfg_boot_set(void *opaque
, const char *boot_device
,
109 fw_cfg_modify_i16(opaque
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
112 static void nvram_init(Nvram
*nvram
, uint8_t *macaddr
,
113 const char *cmdline
, const char *boot_devices
,
114 ram_addr_t RAM_size
, uint32_t kernel_size
,
115 int width
, int height
, int depth
,
116 int nvram_machine_id
, const char *arch
)
120 uint8_t image
[0x1ff0];
121 NvramClass
*k
= NVRAM_GET_CLASS(nvram
);
123 memset(image
, '\0', sizeof(image
));
125 /* OpenBIOS nvram variables partition */
126 sysp_end
= chrp_nvram_create_system_partition(image
, 0);
128 /* Free space partition */
129 chrp_nvram_create_free_partition(&image
[sysp_end
], 0x1fd0 - sysp_end
);
131 Sun_init_header((struct Sun_nvram
*)&image
[0x1fd8], macaddr
,
134 for (i
= 0; i
< sizeof(image
); i
++) {
135 (k
->write
)(nvram
, i
, image
[i
]);
139 void cpu_check_irqs(CPUSPARCState
*env
)
143 /* We should be holding the BQL before we mess with IRQs */
144 g_assert(qemu_mutex_iothread_locked());
146 if (env
->pil_in
&& (env
->interrupt_index
== 0 ||
147 (env
->interrupt_index
& ~15) == TT_EXTINT
)) {
150 for (i
= 15; i
> 0; i
--) {
151 if (env
->pil_in
& (1 << i
)) {
152 int old_interrupt
= env
->interrupt_index
;
154 env
->interrupt_index
= TT_EXTINT
| i
;
155 if (old_interrupt
!= env
->interrupt_index
) {
156 cs
= CPU(sparc_env_get_cpu(env
));
157 trace_sun4m_cpu_interrupt(i
);
158 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
163 } else if (!env
->pil_in
&& (env
->interrupt_index
& ~15) == TT_EXTINT
) {
164 cs
= CPU(sparc_env_get_cpu(env
));
165 trace_sun4m_cpu_reset_interrupt(env
->interrupt_index
& 15);
166 env
->interrupt_index
= 0;
167 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
171 static void cpu_kick_irq(SPARCCPU
*cpu
)
173 CPUSPARCState
*env
= &cpu
->env
;
174 CPUState
*cs
= CPU(cpu
);
181 static void cpu_set_irq(void *opaque
, int irq
, int level
)
183 SPARCCPU
*cpu
= opaque
;
184 CPUSPARCState
*env
= &cpu
->env
;
187 trace_sun4m_cpu_set_irq_raise(irq
);
188 env
->pil_in
|= 1 << irq
;
191 trace_sun4m_cpu_set_irq_lower(irq
);
192 env
->pil_in
&= ~(1 << irq
);
197 static void dummy_cpu_set_irq(void *opaque
, int irq
, int level
)
201 static void main_cpu_reset(void *opaque
)
203 SPARCCPU
*cpu
= opaque
;
204 CPUState
*cs
= CPU(cpu
);
210 static void secondary_cpu_reset(void *opaque
)
212 SPARCCPU
*cpu
= opaque
;
213 CPUState
*cs
= CPU(cpu
);
219 static void cpu_halt_signal(void *opaque
, int irq
, int level
)
221 if (level
&& current_cpu
) {
222 cpu_interrupt(current_cpu
, CPU_INTERRUPT_HALT
);
226 static uint64_t translate_kernel_address(void *opaque
, uint64_t addr
)
228 return addr
- 0xf0000000ULL
;
231 static unsigned long sun4m_load_kernel(const char *kernel_filename
,
232 const char *initrd_filename
,
237 long initrd_size
, kernel_size
;
240 linux_boot
= (kernel_filename
!= NULL
);
251 kernel_size
= load_elf(kernel_filename
, translate_kernel_address
, NULL
,
252 NULL
, NULL
, NULL
, 1, EM_SPARC
, 0, 0);
254 kernel_size
= load_aout(kernel_filename
, KERNEL_LOAD_ADDR
,
255 RAM_size
- KERNEL_LOAD_ADDR
, bswap_needed
,
258 kernel_size
= load_image_targphys(kernel_filename
,
260 RAM_size
- KERNEL_LOAD_ADDR
);
261 if (kernel_size
< 0) {
262 error_report("could not load kernel '%s'", kernel_filename
);
268 if (initrd_filename
) {
269 initrd_size
= load_image_targphys(initrd_filename
,
271 RAM_size
- INITRD_LOAD_ADDR
);
272 if (initrd_size
< 0) {
273 error_report("could not load initial ram disk '%s'",
278 if (initrd_size
> 0) {
279 for (i
= 0; i
< 64 * TARGET_PAGE_SIZE
; i
+= TARGET_PAGE_SIZE
) {
280 ptr
= rom_ptr(KERNEL_LOAD_ADDR
+ i
);
281 if (ldl_p(ptr
) == 0x48647253) { // HdrS
282 stl_p(ptr
+ 16, INITRD_LOAD_ADDR
);
283 stl_p(ptr
+ 20, initrd_size
);
292 static void *iommu_init(hwaddr addr
, uint32_t version
, qemu_irq irq
)
297 dev
= qdev_create(NULL
, TYPE_SUN4M_IOMMU
);
298 qdev_prop_set_uint32(dev
, "version", version
);
299 qdev_init_nofail(dev
);
300 s
= SYS_BUS_DEVICE(dev
);
301 sysbus_connect_irq(s
, 0, irq
);
302 sysbus_mmio_map(s
, 0, addr
);
307 static void *sparc32_dma_init(hwaddr dma_base
,
308 hwaddr esp_base
, qemu_irq espdma_irq
,
309 hwaddr le_base
, qemu_irq ledma_irq
)
312 ESPDMADeviceState
*espdma
;
313 LEDMADeviceState
*ledma
;
315 SysBusPCNetState
*lance
;
317 dma
= qdev_create(NULL
, TYPE_SPARC32_DMA
);
318 qdev_init_nofail(dma
);
319 sysbus_mmio_map(SYS_BUS_DEVICE(dma
), 0, dma_base
);
321 espdma
= SPARC32_ESPDMA_DEVICE(object_resolve_path_component(
322 OBJECT(dma
), "espdma"));
323 sysbus_connect_irq(SYS_BUS_DEVICE(espdma
), 0, espdma_irq
);
325 esp
= ESP_STATE(object_resolve_path_component(OBJECT(espdma
), "esp"));
326 sysbus_mmio_map(SYS_BUS_DEVICE(esp
), 0, esp_base
);
328 ledma
= SPARC32_LEDMA_DEVICE(object_resolve_path_component(
329 OBJECT(dma
), "ledma"));
330 sysbus_connect_irq(SYS_BUS_DEVICE(ledma
), 0, ledma_irq
);
332 lance
= SYSBUS_PCNET(object_resolve_path_component(
333 OBJECT(ledma
), "lance"));
334 sysbus_mmio_map(SYS_BUS_DEVICE(lance
), 0, le_base
);
339 static DeviceState
*slavio_intctl_init(hwaddr addr
,
341 qemu_irq
**parent_irq
)
347 dev
= qdev_create(NULL
, "slavio_intctl");
348 qdev_init_nofail(dev
);
350 s
= SYS_BUS_DEVICE(dev
);
352 for (i
= 0; i
< MAX_CPUS
; i
++) {
353 for (j
= 0; j
< MAX_PILS
; j
++) {
354 sysbus_connect_irq(s
, i
* MAX_PILS
+ j
, parent_irq
[i
][j
]);
357 sysbus_mmio_map(s
, 0, addrg
);
358 for (i
= 0; i
< MAX_CPUS
; i
++) {
359 sysbus_mmio_map(s
, i
+ 1, addr
+ i
* TARGET_PAGE_SIZE
);
365 #define SYS_TIMER_OFFSET 0x10000ULL
366 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
368 static void slavio_timer_init_all(hwaddr addr
, qemu_irq master_irq
,
369 qemu_irq
*cpu_irqs
, unsigned int num_cpus
)
375 dev
= qdev_create(NULL
, "slavio_timer");
376 qdev_prop_set_uint32(dev
, "num_cpus", num_cpus
);
377 qdev_init_nofail(dev
);
378 s
= SYS_BUS_DEVICE(dev
);
379 sysbus_connect_irq(s
, 0, master_irq
);
380 sysbus_mmio_map(s
, 0, addr
+ SYS_TIMER_OFFSET
);
382 for (i
= 0; i
< MAX_CPUS
; i
++) {
383 sysbus_mmio_map(s
, i
+ 1, addr
+ (hwaddr
)CPU_TIMER_OFFSET(i
));
384 sysbus_connect_irq(s
, i
+ 1, cpu_irqs
[i
]);
388 static qemu_irq slavio_system_powerdown
;
390 static void slavio_powerdown_req(Notifier
*n
, void *opaque
)
392 qemu_irq_raise(slavio_system_powerdown
);
395 static Notifier slavio_system_powerdown_notifier
= {
396 .notify
= slavio_powerdown_req
399 #define MISC_LEDS 0x01600000
400 #define MISC_CFG 0x01800000
401 #define MISC_DIAG 0x01a00000
402 #define MISC_MDM 0x01b00000
403 #define MISC_SYS 0x01f00000
405 static void slavio_misc_init(hwaddr base
,
407 hwaddr aux2_base
, qemu_irq irq
,
413 dev
= qdev_create(NULL
, "slavio_misc");
414 qdev_init_nofail(dev
);
415 s
= SYS_BUS_DEVICE(dev
);
417 /* 8 bit registers */
419 sysbus_mmio_map(s
, 0, base
+ MISC_CFG
);
421 sysbus_mmio_map(s
, 1, base
+ MISC_DIAG
);
423 sysbus_mmio_map(s
, 2, base
+ MISC_MDM
);
424 /* 16 bit registers */
425 /* ss600mp diag LEDs */
426 sysbus_mmio_map(s
, 3, base
+ MISC_LEDS
);
427 /* 32 bit registers */
429 sysbus_mmio_map(s
, 4, base
+ MISC_SYS
);
432 /* AUX 1 (Misc System Functions) */
433 sysbus_mmio_map(s
, 5, aux1_base
);
436 /* AUX 2 (Software Powerdown Control) */
437 sysbus_mmio_map(s
, 6, aux2_base
);
439 sysbus_connect_irq(s
, 0, irq
);
440 sysbus_connect_irq(s
, 1, fdc_tc
);
441 slavio_system_powerdown
= qdev_get_gpio_in(dev
, 0);
442 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier
);
445 static void ecc_init(hwaddr base
, qemu_irq irq
, uint32_t version
)
450 dev
= qdev_create(NULL
, "eccmemctl");
451 qdev_prop_set_uint32(dev
, "version", version
);
452 qdev_init_nofail(dev
);
453 s
= SYS_BUS_DEVICE(dev
);
454 sysbus_connect_irq(s
, 0, irq
);
455 sysbus_mmio_map(s
, 0, base
);
456 if (version
== 0) { // SS-600MP only
457 sysbus_mmio_map(s
, 1, base
+ 0x1000);
461 static void apc_init(hwaddr power_base
, qemu_irq cpu_halt
)
466 dev
= qdev_create(NULL
, "apc");
467 qdev_init_nofail(dev
);
468 s
= SYS_BUS_DEVICE(dev
);
469 /* Power management (APC) XXX: not a Slavio device */
470 sysbus_mmio_map(s
, 0, power_base
);
471 sysbus_connect_irq(s
, 0, cpu_halt
);
474 static void tcx_init(hwaddr addr
, qemu_irq irq
, int vram_size
, int width
,
475 int height
, int depth
)
480 dev
= qdev_create(NULL
, "SUNW,tcx");
481 qdev_prop_set_uint32(dev
, "vram_size", vram_size
);
482 qdev_prop_set_uint16(dev
, "width", width
);
483 qdev_prop_set_uint16(dev
, "height", height
);
484 qdev_prop_set_uint16(dev
, "depth", depth
);
485 qdev_init_nofail(dev
);
486 s
= SYS_BUS_DEVICE(dev
);
488 /* 10/ROM : FCode ROM */
489 sysbus_mmio_map(s
, 0, addr
);
490 /* 2/STIP : Stipple */
491 sysbus_mmio_map(s
, 1, addr
+ 0x04000000ULL
);
492 /* 3/BLIT : Blitter */
493 sysbus_mmio_map(s
, 2, addr
+ 0x06000000ULL
);
494 /* 5/RSTIP : Raw Stipple */
495 sysbus_mmio_map(s
, 3, addr
+ 0x0c000000ULL
);
496 /* 6/RBLIT : Raw Blitter */
497 sysbus_mmio_map(s
, 4, addr
+ 0x0e000000ULL
);
498 /* 7/TEC : Transform Engine */
499 sysbus_mmio_map(s
, 5, addr
+ 0x00700000ULL
);
501 sysbus_mmio_map(s
, 6, addr
+ 0x00200000ULL
);
504 sysbus_mmio_map(s
, 7, addr
+ 0x00300000ULL
);
506 sysbus_mmio_map(s
, 7, addr
+ 0x00301000ULL
);
509 sysbus_mmio_map(s
, 8, addr
+ 0x00240000ULL
);
511 sysbus_mmio_map(s
, 9, addr
+ 0x00280000ULL
);
512 /* 0/DFB8 : 8-bit plane */
513 sysbus_mmio_map(s
, 10, addr
+ 0x00800000ULL
);
514 /* 1/DFB24 : 24bit plane */
515 sysbus_mmio_map(s
, 11, addr
+ 0x02000000ULL
);
516 /* 4/RDFB32: Raw framebuffer. Control plane */
517 sysbus_mmio_map(s
, 12, addr
+ 0x0a000000ULL
);
518 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
520 sysbus_mmio_map(s
, 13, addr
+ 0x00301000ULL
);
523 sysbus_connect_irq(s
, 0, irq
);
526 static void cg3_init(hwaddr addr
, qemu_irq irq
, int vram_size
, int width
,
527 int height
, int depth
)
532 dev
= qdev_create(NULL
, "cgthree");
533 qdev_prop_set_uint32(dev
, "vram-size", vram_size
);
534 qdev_prop_set_uint16(dev
, "width", width
);
535 qdev_prop_set_uint16(dev
, "height", height
);
536 qdev_prop_set_uint16(dev
, "depth", depth
);
537 qdev_init_nofail(dev
);
538 s
= SYS_BUS_DEVICE(dev
);
541 sysbus_mmio_map(s
, 0, addr
);
543 sysbus_mmio_map(s
, 1, addr
+ 0x400000ULL
);
545 sysbus_mmio_map(s
, 2, addr
+ 0x800000ULL
);
547 sysbus_connect_irq(s
, 0, irq
);
550 /* NCR89C100/MACIO Internal ID register */
552 #define TYPE_MACIO_ID_REGISTER "macio_idreg"
554 static const uint8_t idreg_data
[] = { 0xfe, 0x81, 0x01, 0x03 };
556 static void idreg_init(hwaddr addr
)
561 dev
= qdev_create(NULL
, TYPE_MACIO_ID_REGISTER
);
562 qdev_init_nofail(dev
);
563 s
= SYS_BUS_DEVICE(dev
);
565 sysbus_mmio_map(s
, 0, addr
);
566 cpu_physical_memory_write_rom(&address_space_memory
,
567 addr
, idreg_data
, sizeof(idreg_data
));
570 #define MACIO_ID_REGISTER(obj) \
571 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER)
573 typedef struct IDRegState
{
574 SysBusDevice parent_obj
;
579 static void idreg_init1(Object
*obj
)
581 IDRegState
*s
= MACIO_ID_REGISTER(obj
);
582 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
584 memory_region_init_ram_nomigrate(&s
->mem
, obj
,
585 "sun4m.idreg", sizeof(idreg_data
), &error_fatal
);
586 vmstate_register_ram_global(&s
->mem
);
587 memory_region_set_readonly(&s
->mem
, true);
588 sysbus_init_mmio(dev
, &s
->mem
);
591 static const TypeInfo idreg_info
= {
592 .name
= TYPE_MACIO_ID_REGISTER
,
593 .parent
= TYPE_SYS_BUS_DEVICE
,
594 .instance_size
= sizeof(IDRegState
),
595 .instance_init
= idreg_init1
,
598 #define TYPE_TCX_AFX "tcx_afx"
599 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX)
601 typedef struct AFXState
{
602 SysBusDevice parent_obj
;
607 /* SS-5 TCX AFX register */
608 static void afx_init(hwaddr addr
)
613 dev
= qdev_create(NULL
, TYPE_TCX_AFX
);
614 qdev_init_nofail(dev
);
615 s
= SYS_BUS_DEVICE(dev
);
617 sysbus_mmio_map(s
, 0, addr
);
620 static void afx_init1(Object
*obj
)
622 AFXState
*s
= TCX_AFX(obj
);
623 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
625 memory_region_init_ram_nomigrate(&s
->mem
, obj
, "sun4m.afx", 4, &error_fatal
);
626 vmstate_register_ram_global(&s
->mem
);
627 sysbus_init_mmio(dev
, &s
->mem
);
630 static const TypeInfo afx_info
= {
631 .name
= TYPE_TCX_AFX
,
632 .parent
= TYPE_SYS_BUS_DEVICE
,
633 .instance_size
= sizeof(AFXState
),
634 .instance_init
= afx_init1
,
637 #define TYPE_OPENPROM "openprom"
638 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
640 typedef struct PROMState
{
641 SysBusDevice parent_obj
;
646 /* Boot PROM (OpenBIOS) */
647 static uint64_t translate_prom_address(void *opaque
, uint64_t addr
)
649 hwaddr
*base_addr
= (hwaddr
*)opaque
;
650 return addr
+ *base_addr
- PROM_VADDR
;
653 static void prom_init(hwaddr addr
, const char *bios_name
)
660 dev
= qdev_create(NULL
, TYPE_OPENPROM
);
661 qdev_init_nofail(dev
);
662 s
= SYS_BUS_DEVICE(dev
);
664 sysbus_mmio_map(s
, 0, addr
);
667 if (bios_name
== NULL
) {
668 bios_name
= PROM_FILENAME
;
670 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
672 ret
= load_elf(filename
, translate_prom_address
, &addr
, NULL
,
673 NULL
, NULL
, 1, EM_SPARC
, 0, 0);
674 if (ret
< 0 || ret
> PROM_SIZE_MAX
) {
675 ret
= load_image_targphys(filename
, addr
, PROM_SIZE_MAX
);
681 if (ret
< 0 || ret
> PROM_SIZE_MAX
) {
682 error_report("could not load prom '%s'", bios_name
);
687 static void prom_init1(Object
*obj
)
689 PROMState
*s
= OPENPROM(obj
);
690 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
692 memory_region_init_ram_nomigrate(&s
->prom
, obj
, "sun4m.prom", PROM_SIZE_MAX
,
694 vmstate_register_ram_global(&s
->prom
);
695 memory_region_set_readonly(&s
->prom
, true);
696 sysbus_init_mmio(dev
, &s
->prom
);
699 static Property prom_properties
[] = {
700 {/* end of property list */},
703 static void prom_class_init(ObjectClass
*klass
, void *data
)
705 DeviceClass
*dc
= DEVICE_CLASS(klass
);
707 dc
->props
= prom_properties
;
710 static const TypeInfo prom_info
= {
711 .name
= TYPE_OPENPROM
,
712 .parent
= TYPE_SYS_BUS_DEVICE
,
713 .instance_size
= sizeof(PROMState
),
714 .class_init
= prom_class_init
,
715 .instance_init
= prom_init1
,
718 #define TYPE_SUN4M_MEMORY "memory"
719 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY)
721 typedef struct RamDevice
{
722 SysBusDevice parent_obj
;
729 static void ram_realize(DeviceState
*dev
, Error
**errp
)
731 RamDevice
*d
= SUN4M_RAM(dev
);
732 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
734 memory_region_allocate_system_memory(&d
->ram
, OBJECT(d
), "sun4m.ram",
736 sysbus_init_mmio(sbd
, &d
->ram
);
739 static void ram_init(hwaddr addr
, ram_addr_t RAM_size
,
747 if ((uint64_t)RAM_size
> max_mem
) {
748 error_report("Too much memory for this machine: %d, maximum %d",
749 (unsigned int)(RAM_size
/ (1024 * 1024)),
750 (unsigned int)(max_mem
/ (1024 * 1024)));
753 dev
= qdev_create(NULL
, "memory");
754 s
= SYS_BUS_DEVICE(dev
);
758 qdev_init_nofail(dev
);
760 sysbus_mmio_map(s
, 0, addr
);
763 static Property ram_properties
[] = {
764 DEFINE_PROP_UINT64("size", RamDevice
, size
, 0),
765 DEFINE_PROP_END_OF_LIST(),
768 static void ram_class_init(ObjectClass
*klass
, void *data
)
770 DeviceClass
*dc
= DEVICE_CLASS(klass
);
772 dc
->realize
= ram_realize
;
773 dc
->props
= ram_properties
;
776 static const TypeInfo ram_info
= {
777 .name
= TYPE_SUN4M_MEMORY
,
778 .parent
= TYPE_SYS_BUS_DEVICE
,
779 .instance_size
= sizeof(RamDevice
),
780 .class_init
= ram_class_init
,
783 static void cpu_devinit(const char *cpu_type
, unsigned int id
,
784 uint64_t prom_addr
, qemu_irq
**cpu_irqs
)
790 cpu
= SPARC_CPU(cpu_create(cpu_type
));
793 cpu_sparc_set_id(env
, id
);
795 qemu_register_reset(main_cpu_reset
, cpu
);
797 qemu_register_reset(secondary_cpu_reset
, cpu
);
801 *cpu_irqs
= qemu_allocate_irqs(cpu_set_irq
, cpu
, MAX_PILS
);
802 env
->prom_addr
= prom_addr
;
805 static void dummy_fdc_tc(void *opaque
, int irq
, int level
)
809 static void sun4m_hw_init(const struct sun4m_hwdef
*hwdef
,
810 MachineState
*machine
)
812 DeviceState
*slavio_intctl
;
815 qemu_irq
*cpu_irqs
[MAX_CPUS
], slavio_irq
[32], slavio_cpu_irq
[MAX_CPUS
];
817 unsigned long kernel_size
;
818 DriveInfo
*fd
[MAX_FD
];
820 unsigned int num_vsimms
;
823 for(i
= 0; i
< smp_cpus
; i
++) {
824 cpu_devinit(machine
->cpu_type
, i
, hwdef
->slavio_base
, &cpu_irqs
[i
]);
827 for (i
= smp_cpus
; i
< MAX_CPUS
; i
++)
828 cpu_irqs
[i
] = qemu_allocate_irqs(dummy_cpu_set_irq
, NULL
, MAX_PILS
);
832 ram_init(0, machine
->ram_size
, hwdef
->max_mem
);
833 /* models without ECC don't trap when missing ram is accessed */
834 if (!hwdef
->ecc_base
) {
835 empty_slot_init(machine
->ram_size
, hwdef
->max_mem
- machine
->ram_size
);
838 prom_init(hwdef
->slavio_base
, bios_name
);
840 slavio_intctl
= slavio_intctl_init(hwdef
->intctl_base
,
841 hwdef
->intctl_base
+ 0x10000ULL
,
844 for (i
= 0; i
< 32; i
++) {
845 slavio_irq
[i
] = qdev_get_gpio_in(slavio_intctl
, i
);
847 for (i
= 0; i
< MAX_CPUS
; i
++) {
848 slavio_cpu_irq
[i
] = qdev_get_gpio_in(slavio_intctl
, 32 + i
);
851 if (hwdef
->idreg_base
) {
852 idreg_init(hwdef
->idreg_base
);
855 if (hwdef
->afx_base
) {
856 afx_init(hwdef
->afx_base
);
859 iommu_init(hwdef
->iommu_base
, hwdef
->iommu_version
, slavio_irq
[30]);
861 if (hwdef
->iommu_pad_base
) {
862 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
863 Software shouldn't use aliased addresses, neither should it crash
864 when does. Using empty_slot instead of aliasing can help with
865 debugging such accesses */
866 empty_slot_init(hwdef
->iommu_pad_base
,hwdef
->iommu_pad_len
);
869 sparc32_dma_init(hwdef
->dma_base
,
870 hwdef
->esp_base
, slavio_irq
[18],
871 hwdef
->le_base
, slavio_irq
[16]);
873 if (graphic_depth
!= 8 && graphic_depth
!= 24) {
874 error_report("Unsupported depth: %d", graphic_depth
);
878 if (num_vsimms
== 0) {
879 if (vga_interface_type
== VGA_CG3
) {
880 if (graphic_depth
!= 8) {
881 error_report("Unsupported depth: %d", graphic_depth
);
885 if (!(graphic_width
== 1024 && graphic_height
== 768) &&
886 !(graphic_width
== 1152 && graphic_height
== 900)) {
887 error_report("Unsupported resolution: %d x %d", graphic_width
,
893 cg3_init(hwdef
->tcx_base
, slavio_irq
[11], 0x00100000,
894 graphic_width
, graphic_height
, graphic_depth
);
896 /* If no display specified, default to TCX */
897 if (graphic_depth
!= 8 && graphic_depth
!= 24) {
898 error_report("Unsupported depth: %d", graphic_depth
);
902 if (!(graphic_width
== 1024 && graphic_height
== 768)) {
903 error_report("Unsupported resolution: %d x %d",
904 graphic_width
, graphic_height
);
908 tcx_init(hwdef
->tcx_base
, slavio_irq
[11], 0x00100000,
909 graphic_width
, graphic_height
, graphic_depth
);
913 for (i
= num_vsimms
; i
< MAX_VSIMMS
; i
++) {
914 /* vsimm registers probed by OBP */
915 if (hwdef
->vsimm
[i
].reg_base
) {
916 empty_slot_init(hwdef
->vsimm
[i
].reg_base
, 0x2000);
920 if (hwdef
->sx_base
) {
921 empty_slot_init(hwdef
->sx_base
, 0x2000);
924 nvram
= m48t59_init(slavio_irq
[0], hwdef
->nvram_base
, 0, 0x2000, 1968, 8);
926 slavio_timer_init_all(hwdef
->counter_base
, slavio_irq
[19], slavio_cpu_irq
, smp_cpus
);
928 slavio_serial_ms_kbd_init(hwdef
->ms_kb_base
, slavio_irq
[14],
929 !machine
->enable_graphics
, ESCC_CLOCK
, 1);
930 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
931 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
932 escc_init(hwdef
->serial_base
, slavio_irq
[15], slavio_irq
[15],
933 serial_hds
[0], serial_hds
[1], ESCC_CLOCK
, 1);
935 if (hwdef
->apc_base
) {
936 apc_init(hwdef
->apc_base
, qemu_allocate_irq(cpu_halt_signal
, NULL
, 0));
939 if (hwdef
->fd_base
) {
940 /* there is zero or one floppy drive */
941 memset(fd
, 0, sizeof(fd
));
942 fd
[0] = drive_get(IF_FLOPPY
, 0, 0);
943 sun4m_fdctrl_init(slavio_irq
[22], hwdef
->fd_base
, fd
,
946 fdc_tc
= qemu_allocate_irq(dummy_fdc_tc
, NULL
, 0);
949 slavio_misc_init(hwdef
->slavio_base
, hwdef
->aux1_base
, hwdef
->aux2_base
,
950 slavio_irq
[30], fdc_tc
);
952 if (hwdef
->cs_base
) {
953 sysbus_create_simple("SUNW,CS4231", hwdef
->cs_base
,
957 if (hwdef
->dbri_base
) {
958 /* ISDN chip with attached CS4215 audio codec */
960 empty_slot_init(hwdef
->dbri_base
+0x1000, 0x30);
962 empty_slot_init(hwdef
->dbri_base
+0x10000, 0x100);
965 if (hwdef
->bpp_base
) {
967 empty_slot_init(hwdef
->bpp_base
, 0x20);
970 kernel_size
= sun4m_load_kernel(machine
->kernel_filename
,
971 machine
->initrd_filename
,
974 nvram_init(nvram
, (uint8_t *)&nd_table
[0].macaddr
, machine
->kernel_cmdline
,
975 machine
->boot_order
, machine
->ram_size
, kernel_size
,
976 graphic_width
, graphic_height
, graphic_depth
,
977 hwdef
->nvram_machine_id
, "Sun4m");
980 ecc_init(hwdef
->ecc_base
, slavio_irq
[28],
983 fw_cfg
= fw_cfg_init_mem(CFG_ADDR
, CFG_ADDR
+ 2);
984 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, (uint16_t)smp_cpus
);
985 fw_cfg_add_i16(fw_cfg
, FW_CFG_MAX_CPUS
, (uint16_t)max_cpus
);
986 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
987 fw_cfg_add_i16(fw_cfg
, FW_CFG_MACHINE_ID
, hwdef
->machine_id
);
988 fw_cfg_add_i16(fw_cfg
, FW_CFG_SUN4M_DEPTH
, graphic_depth
);
989 fw_cfg_add_i16(fw_cfg
, FW_CFG_SUN4M_WIDTH
, graphic_width
);
990 fw_cfg_add_i16(fw_cfg
, FW_CFG_SUN4M_HEIGHT
, graphic_height
);
991 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, KERNEL_LOAD_ADDR
);
992 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
993 if (machine
->kernel_cmdline
) {
994 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, CMDLINE_ADDR
);
995 pstrcpy_targphys("cmdline", CMDLINE_ADDR
, TARGET_PAGE_SIZE
,
996 machine
->kernel_cmdline
);
997 fw_cfg_add_string(fw_cfg
, FW_CFG_CMDLINE_DATA
, machine
->kernel_cmdline
);
998 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
,
999 strlen(machine
->kernel_cmdline
) + 1);
1001 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, 0);
1002 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
, 0);
1004 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, INITRD_LOAD_ADDR
);
1005 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, 0); // not used
1006 fw_cfg_add_i16(fw_cfg
, FW_CFG_BOOT_DEVICE
, machine
->boot_order
[0]);
1007 qemu_register_boot_set(fw_cfg_boot_set
, fw_cfg
);
1022 static const struct sun4m_hwdef sun4m_hwdefs
[] = {
1025 .iommu_base
= 0x10000000,
1026 .iommu_pad_base
= 0x10004000,
1027 .iommu_pad_len
= 0x0fffb000,
1028 .tcx_base
= 0x50000000,
1029 .cs_base
= 0x6c000000,
1030 .slavio_base
= 0x70000000,
1031 .ms_kb_base
= 0x71000000,
1032 .serial_base
= 0x71100000,
1033 .nvram_base
= 0x71200000,
1034 .fd_base
= 0x71400000,
1035 .counter_base
= 0x71d00000,
1036 .intctl_base
= 0x71e00000,
1037 .idreg_base
= 0x78000000,
1038 .dma_base
= 0x78400000,
1039 .esp_base
= 0x78800000,
1040 .le_base
= 0x78c00000,
1041 .apc_base
= 0x6a000000,
1042 .afx_base
= 0x6e000000,
1043 .aux1_base
= 0x71900000,
1044 .aux2_base
= 0x71910000,
1045 .nvram_machine_id
= 0x80,
1046 .machine_id
= ss5_id
,
1047 .iommu_version
= 0x05000000,
1048 .max_mem
= 0x10000000,
1052 .iommu_base
= 0xfe0000000ULL
,
1053 .tcx_base
= 0xe20000000ULL
,
1054 .slavio_base
= 0xff0000000ULL
,
1055 .ms_kb_base
= 0xff1000000ULL
,
1056 .serial_base
= 0xff1100000ULL
,
1057 .nvram_base
= 0xff1200000ULL
,
1058 .fd_base
= 0xff1700000ULL
,
1059 .counter_base
= 0xff1300000ULL
,
1060 .intctl_base
= 0xff1400000ULL
,
1061 .idreg_base
= 0xef0000000ULL
,
1062 .dma_base
= 0xef0400000ULL
,
1063 .esp_base
= 0xef0800000ULL
,
1064 .le_base
= 0xef0c00000ULL
,
1065 .apc_base
= 0xefa000000ULL
, // XXX should not exist
1066 .aux1_base
= 0xff1800000ULL
,
1067 .aux2_base
= 0xff1a01000ULL
,
1068 .ecc_base
= 0xf00000000ULL
,
1069 .ecc_version
= 0x10000000, // version 0, implementation 1
1070 .nvram_machine_id
= 0x72,
1071 .machine_id
= ss10_id
,
1072 .iommu_version
= 0x03000000,
1073 .max_mem
= 0xf00000000ULL
,
1077 .iommu_base
= 0xfe0000000ULL
,
1078 .tcx_base
= 0xe20000000ULL
,
1079 .slavio_base
= 0xff0000000ULL
,
1080 .ms_kb_base
= 0xff1000000ULL
,
1081 .serial_base
= 0xff1100000ULL
,
1082 .nvram_base
= 0xff1200000ULL
,
1083 .counter_base
= 0xff1300000ULL
,
1084 .intctl_base
= 0xff1400000ULL
,
1085 .dma_base
= 0xef0081000ULL
,
1086 .esp_base
= 0xef0080000ULL
,
1087 .le_base
= 0xef0060000ULL
,
1088 .apc_base
= 0xefa000000ULL
, // XXX should not exist
1089 .aux1_base
= 0xff1800000ULL
,
1090 .aux2_base
= 0xff1a01000ULL
, // XXX should not exist
1091 .ecc_base
= 0xf00000000ULL
,
1092 .ecc_version
= 0x00000000, // version 0, implementation 0
1093 .nvram_machine_id
= 0x71,
1094 .machine_id
= ss600mp_id
,
1095 .iommu_version
= 0x01000000,
1096 .max_mem
= 0xf00000000ULL
,
1100 .iommu_base
= 0xfe0000000ULL
,
1101 .tcx_base
= 0xe20000000ULL
,
1102 .slavio_base
= 0xff0000000ULL
,
1103 .ms_kb_base
= 0xff1000000ULL
,
1104 .serial_base
= 0xff1100000ULL
,
1105 .nvram_base
= 0xff1200000ULL
,
1106 .fd_base
= 0xff1700000ULL
,
1107 .counter_base
= 0xff1300000ULL
,
1108 .intctl_base
= 0xff1400000ULL
,
1109 .idreg_base
= 0xef0000000ULL
,
1110 .dma_base
= 0xef0400000ULL
,
1111 .esp_base
= 0xef0800000ULL
,
1112 .le_base
= 0xef0c00000ULL
,
1113 .bpp_base
= 0xef4800000ULL
,
1114 .apc_base
= 0xefa000000ULL
, // XXX should not exist
1115 .aux1_base
= 0xff1800000ULL
,
1116 .aux2_base
= 0xff1a01000ULL
,
1117 .dbri_base
= 0xee0000000ULL
,
1118 .sx_base
= 0xf80000000ULL
,
1121 .reg_base
= 0x9c000000ULL
,
1122 .vram_base
= 0xfc000000ULL
1124 .reg_base
= 0x90000000ULL
,
1125 .vram_base
= 0xf0000000ULL
1127 .reg_base
= 0x94000000ULL
1129 .reg_base
= 0x98000000ULL
1132 .ecc_base
= 0xf00000000ULL
,
1133 .ecc_version
= 0x20000000, // version 0, implementation 2
1134 .nvram_machine_id
= 0x72,
1135 .machine_id
= ss20_id
,
1136 .iommu_version
= 0x13000000,
1137 .max_mem
= 0xf00000000ULL
,
1141 .iommu_base
= 0x10000000,
1142 .tcx_base
= 0x50000000,
1143 .slavio_base
= 0x70000000,
1144 .ms_kb_base
= 0x71000000,
1145 .serial_base
= 0x71100000,
1146 .nvram_base
= 0x71200000,
1147 .fd_base
= 0x71400000,
1148 .counter_base
= 0x71d00000,
1149 .intctl_base
= 0x71e00000,
1150 .idreg_base
= 0x78000000,
1151 .dma_base
= 0x78400000,
1152 .esp_base
= 0x78800000,
1153 .le_base
= 0x78c00000,
1154 .apc_base
= 0x71300000, // pmc
1155 .aux1_base
= 0x71900000,
1156 .aux2_base
= 0x71910000,
1157 .nvram_machine_id
= 0x80,
1158 .machine_id
= vger_id
,
1159 .iommu_version
= 0x05000000,
1160 .max_mem
= 0x10000000,
1164 .iommu_base
= 0x10000000,
1165 .iommu_pad_base
= 0x10004000,
1166 .iommu_pad_len
= 0x0fffb000,
1167 .tcx_base
= 0x50000000,
1168 .slavio_base
= 0x70000000,
1169 .ms_kb_base
= 0x71000000,
1170 .serial_base
= 0x71100000,
1171 .nvram_base
= 0x71200000,
1172 .fd_base
= 0x71400000,
1173 .counter_base
= 0x71d00000,
1174 .intctl_base
= 0x71e00000,
1175 .idreg_base
= 0x78000000,
1176 .dma_base
= 0x78400000,
1177 .esp_base
= 0x78800000,
1178 .le_base
= 0x78c00000,
1179 .aux1_base
= 0x71900000,
1180 .aux2_base
= 0x71910000,
1181 .nvram_machine_id
= 0x80,
1182 .machine_id
= lx_id
,
1183 .iommu_version
= 0x04000000,
1184 .max_mem
= 0x10000000,
1188 .iommu_base
= 0x10000000,
1189 .tcx_base
= 0x50000000,
1190 .cs_base
= 0x6c000000,
1191 .slavio_base
= 0x70000000,
1192 .ms_kb_base
= 0x71000000,
1193 .serial_base
= 0x71100000,
1194 .nvram_base
= 0x71200000,
1195 .fd_base
= 0x71400000,
1196 .counter_base
= 0x71d00000,
1197 .intctl_base
= 0x71e00000,
1198 .idreg_base
= 0x78000000,
1199 .dma_base
= 0x78400000,
1200 .esp_base
= 0x78800000,
1201 .le_base
= 0x78c00000,
1202 .apc_base
= 0x6a000000,
1203 .aux1_base
= 0x71900000,
1204 .aux2_base
= 0x71910000,
1205 .nvram_machine_id
= 0x80,
1206 .machine_id
= ss4_id
,
1207 .iommu_version
= 0x05000000,
1208 .max_mem
= 0x10000000,
1212 .iommu_base
= 0x10000000,
1213 .tcx_base
= 0x50000000,
1214 .slavio_base
= 0x70000000,
1215 .ms_kb_base
= 0x71000000,
1216 .serial_base
= 0x71100000,
1217 .nvram_base
= 0x71200000,
1218 .fd_base
= 0x71400000,
1219 .counter_base
= 0x71d00000,
1220 .intctl_base
= 0x71e00000,
1221 .idreg_base
= 0x78000000,
1222 .dma_base
= 0x78400000,
1223 .esp_base
= 0x78800000,
1224 .le_base
= 0x78c00000,
1225 .apc_base
= 0x6a000000,
1226 .aux1_base
= 0x71900000,
1227 .aux2_base
= 0x71910000,
1228 .nvram_machine_id
= 0x80,
1229 .machine_id
= scls_id
,
1230 .iommu_version
= 0x05000000,
1231 .max_mem
= 0x10000000,
1235 .iommu_base
= 0x10000000,
1236 .tcx_base
= 0x50000000, // XXX
1237 .slavio_base
= 0x70000000,
1238 .ms_kb_base
= 0x71000000,
1239 .serial_base
= 0x71100000,
1240 .nvram_base
= 0x71200000,
1241 .fd_base
= 0x71400000,
1242 .counter_base
= 0x71d00000,
1243 .intctl_base
= 0x71e00000,
1244 .idreg_base
= 0x78000000,
1245 .dma_base
= 0x78400000,
1246 .esp_base
= 0x78800000,
1247 .le_base
= 0x78c00000,
1248 .apc_base
= 0x6a000000,
1249 .aux1_base
= 0x71900000,
1250 .aux2_base
= 0x71910000,
1251 .nvram_machine_id
= 0x80,
1252 .machine_id
= sbook_id
,
1253 .iommu_version
= 0x05000000,
1254 .max_mem
= 0x10000000,
1258 /* SPARCstation 5 hardware initialisation */
1259 static void ss5_init(MachineState
*machine
)
1261 sun4m_hw_init(&sun4m_hwdefs
[0], machine
);
1264 /* SPARCstation 10 hardware initialisation */
1265 static void ss10_init(MachineState
*machine
)
1267 sun4m_hw_init(&sun4m_hwdefs
[1], machine
);
1270 /* SPARCserver 600MP hardware initialisation */
1271 static void ss600mp_init(MachineState
*machine
)
1273 sun4m_hw_init(&sun4m_hwdefs
[2], machine
);
1276 /* SPARCstation 20 hardware initialisation */
1277 static void ss20_init(MachineState
*machine
)
1279 sun4m_hw_init(&sun4m_hwdefs
[3], machine
);
1282 /* SPARCstation Voyager hardware initialisation */
1283 static void vger_init(MachineState
*machine
)
1285 sun4m_hw_init(&sun4m_hwdefs
[4], machine
);
1288 /* SPARCstation LX hardware initialisation */
1289 static void ss_lx_init(MachineState
*machine
)
1291 sun4m_hw_init(&sun4m_hwdefs
[5], machine
);
1294 /* SPARCstation 4 hardware initialisation */
1295 static void ss4_init(MachineState
*machine
)
1297 sun4m_hw_init(&sun4m_hwdefs
[6], machine
);
1300 /* SPARCClassic hardware initialisation */
1301 static void scls_init(MachineState
*machine
)
1303 sun4m_hw_init(&sun4m_hwdefs
[7], machine
);
1306 /* SPARCbook hardware initialisation */
1307 static void sbook_init(MachineState
*machine
)
1309 sun4m_hw_init(&sun4m_hwdefs
[8], machine
);
1312 static void ss5_class_init(ObjectClass
*oc
, void *data
)
1314 MachineClass
*mc
= MACHINE_CLASS(oc
);
1316 mc
->desc
= "Sun4m platform, SPARCstation 5";
1317 mc
->init
= ss5_init
;
1318 mc
->block_default_type
= IF_SCSI
;
1320 mc
->default_boot_order
= "c";
1321 mc
->default_cpu_type
= SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1324 static const TypeInfo ss5_type
= {
1325 .name
= MACHINE_TYPE_NAME("SS-5"),
1326 .parent
= TYPE_MACHINE
,
1327 .class_init
= ss5_class_init
,
1330 static void ss10_class_init(ObjectClass
*oc
, void *data
)
1332 MachineClass
*mc
= MACHINE_CLASS(oc
);
1334 mc
->desc
= "Sun4m platform, SPARCstation 10";
1335 mc
->init
= ss10_init
;
1336 mc
->block_default_type
= IF_SCSI
;
1338 mc
->default_boot_order
= "c";
1339 mc
->default_cpu_type
= SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1342 static const TypeInfo ss10_type
= {
1343 .name
= MACHINE_TYPE_NAME("SS-10"),
1344 .parent
= TYPE_MACHINE
,
1345 .class_init
= ss10_class_init
,
1348 static void ss600mp_class_init(ObjectClass
*oc
, void *data
)
1350 MachineClass
*mc
= MACHINE_CLASS(oc
);
1352 mc
->desc
= "Sun4m platform, SPARCserver 600MP";
1353 mc
->init
= ss600mp_init
;
1354 mc
->block_default_type
= IF_SCSI
;
1356 mc
->default_boot_order
= "c";
1357 mc
->default_cpu_type
= SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1360 static const TypeInfo ss600mp_type
= {
1361 .name
= MACHINE_TYPE_NAME("SS-600MP"),
1362 .parent
= TYPE_MACHINE
,
1363 .class_init
= ss600mp_class_init
,
1366 static void ss20_class_init(ObjectClass
*oc
, void *data
)
1368 MachineClass
*mc
= MACHINE_CLASS(oc
);
1370 mc
->desc
= "Sun4m platform, SPARCstation 20";
1371 mc
->init
= ss20_init
;
1372 mc
->block_default_type
= IF_SCSI
;
1374 mc
->default_boot_order
= "c";
1375 mc
->default_cpu_type
= SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1378 static const TypeInfo ss20_type
= {
1379 .name
= MACHINE_TYPE_NAME("SS-20"),
1380 .parent
= TYPE_MACHINE
,
1381 .class_init
= ss20_class_init
,
1384 static void voyager_class_init(ObjectClass
*oc
, void *data
)
1386 MachineClass
*mc
= MACHINE_CLASS(oc
);
1388 mc
->desc
= "Sun4m platform, SPARCstation Voyager";
1389 mc
->init
= vger_init
;
1390 mc
->block_default_type
= IF_SCSI
;
1391 mc
->default_boot_order
= "c";
1392 mc
->default_cpu_type
= SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1395 static const TypeInfo voyager_type
= {
1396 .name
= MACHINE_TYPE_NAME("Voyager"),
1397 .parent
= TYPE_MACHINE
,
1398 .class_init
= voyager_class_init
,
1401 static void ss_lx_class_init(ObjectClass
*oc
, void *data
)
1403 MachineClass
*mc
= MACHINE_CLASS(oc
);
1405 mc
->desc
= "Sun4m platform, SPARCstation LX";
1406 mc
->init
= ss_lx_init
;
1407 mc
->block_default_type
= IF_SCSI
;
1408 mc
->default_boot_order
= "c";
1409 mc
->default_cpu_type
= SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1412 static const TypeInfo ss_lx_type
= {
1413 .name
= MACHINE_TYPE_NAME("LX"),
1414 .parent
= TYPE_MACHINE
,
1415 .class_init
= ss_lx_class_init
,
1418 static void ss4_class_init(ObjectClass
*oc
, void *data
)
1420 MachineClass
*mc
= MACHINE_CLASS(oc
);
1422 mc
->desc
= "Sun4m platform, SPARCstation 4";
1423 mc
->init
= ss4_init
;
1424 mc
->block_default_type
= IF_SCSI
;
1425 mc
->default_boot_order
= "c";
1426 mc
->default_cpu_type
= SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1429 static const TypeInfo ss4_type
= {
1430 .name
= MACHINE_TYPE_NAME("SS-4"),
1431 .parent
= TYPE_MACHINE
,
1432 .class_init
= ss4_class_init
,
1435 static void scls_class_init(ObjectClass
*oc
, void *data
)
1437 MachineClass
*mc
= MACHINE_CLASS(oc
);
1439 mc
->desc
= "Sun4m platform, SPARCClassic";
1440 mc
->init
= scls_init
;
1441 mc
->block_default_type
= IF_SCSI
;
1442 mc
->default_boot_order
= "c";
1443 mc
->default_cpu_type
= SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1446 static const TypeInfo scls_type
= {
1447 .name
= MACHINE_TYPE_NAME("SPARCClassic"),
1448 .parent
= TYPE_MACHINE
,
1449 .class_init
= scls_class_init
,
1452 static void sbook_class_init(ObjectClass
*oc
, void *data
)
1454 MachineClass
*mc
= MACHINE_CLASS(oc
);
1456 mc
->desc
= "Sun4m platform, SPARCbook";
1457 mc
->init
= sbook_init
;
1458 mc
->block_default_type
= IF_SCSI
;
1459 mc
->default_boot_order
= "c";
1460 mc
->default_cpu_type
= SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1463 static const TypeInfo sbook_type
= {
1464 .name
= MACHINE_TYPE_NAME("SPARCbook"),
1465 .parent
= TYPE_MACHINE
,
1466 .class_init
= sbook_class_init
,
1469 static void sun4m_register_types(void)
1471 type_register_static(&idreg_info
);
1472 type_register_static(&afx_info
);
1473 type_register_static(&prom_info
);
1474 type_register_static(&ram_info
);
1476 type_register_static(&ss5_type
);
1477 type_register_static(&ss10_type
);
1478 type_register_static(&ss600mp_type
);
1479 type_register_static(&ss20_type
);
1480 type_register_static(&voyager_type
);
1481 type_register_static(&ss_lx_type
);
1482 type_register_static(&ss4_type
);
1483 type_register_static(&scls_type
);
1484 type_register_static(&sbook_type
);
1487 type_init(sun4m_register_types
)