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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-misc-20181214' into staging
[mirror_qemu.git] / hw / sparc / sun4m.c
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "qemu/osdep.h"
25 #include "qemu/units.h"
26 #include "qapi/error.h"
27 #include "qemu-common.h"
28 #include "cpu.h"
29 #include "hw/sysbus.h"
30 #include "qemu/error-report.h"
31 #include "qemu/timer.h"
32 #include "hw/sparc/sun4m_iommu.h"
33 #include "hw/timer/m48t59.h"
34 #include "hw/sparc/sparc32_dma.h"
35 #include "hw/block/fdc.h"
36 #include "sysemu/sysemu.h"
37 #include "net/net.h"
38 #include "hw/boards.h"
39 #include "hw/scsi/esp.h"
40 #include "hw/isa/isa.h"
41 #include "hw/nvram/sun_nvram.h"
42 #include "hw/nvram/chrp_nvram.h"
43 #include "hw/nvram/fw_cfg.h"
44 #include "hw/char/escc.h"
45 #include "hw/empty_slot.h"
46 #include "hw/loader.h"
47 #include "elf.h"
48 #include "trace.h"
49
50 /*
51 * Sun4m architecture was used in the following machines:
52 *
53 * SPARCserver 6xxMP/xx
54 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
55 * SPARCclassic X (4/10)
56 * SPARCstation LX/ZX (4/30)
57 * SPARCstation Voyager
58 * SPARCstation 10/xx, SPARCserver 10/xx
59 * SPARCstation 5, SPARCserver 5
60 * SPARCstation 20/xx, SPARCserver 20
61 * SPARCstation 4
62 *
63 * See for example: http://www.sunhelp.org/faq/sunref1.html
64 */
65
66 #define KERNEL_LOAD_ADDR 0x00004000
67 #define CMDLINE_ADDR 0x007ff000
68 #define INITRD_LOAD_ADDR 0x00800000
69 #define PROM_SIZE_MAX (1 * MiB)
70 #define PROM_VADDR 0xffd00000
71 #define PROM_FILENAME "openbios-sparc32"
72 #define CFG_ADDR 0xd00000510ULL
73 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
74 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
75 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
76
77 #define MAX_CPUS 16
78 #define MAX_PILS 16
79 #define MAX_VSIMMS 4
80
81 #define ESCC_CLOCK 4915200
82
83 struct sun4m_hwdef {
84 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
85 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
86 hwaddr serial_base, fd_base;
87 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
88 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
89 hwaddr bpp_base, dbri_base, sx_base;
90 struct {
91 hwaddr reg_base, vram_base;
92 } vsimm[MAX_VSIMMS];
93 hwaddr ecc_base;
94 uint64_t max_mem;
95 uint32_t ecc_version;
96 uint32_t iommu_version;
97 uint16_t machine_id;
98 uint8_t nvram_machine_id;
99 };
100
101 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
102 Error **errp)
103 {
104 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
105 }
106
107 static void nvram_init(Nvram *nvram, uint8_t *macaddr,
108 const char *cmdline, const char *boot_devices,
109 ram_addr_t RAM_size, uint32_t kernel_size,
110 int width, int height, int depth,
111 int nvram_machine_id, const char *arch)
112 {
113 unsigned int i;
114 int sysp_end;
115 uint8_t image[0x1ff0];
116 NvramClass *k = NVRAM_GET_CLASS(nvram);
117
118 memset(image, '\0', sizeof(image));
119
120 /* OpenBIOS nvram variables partition */
121 sysp_end = chrp_nvram_create_system_partition(image, 0);
122
123 /* Free space partition */
124 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
125
126 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
127 nvram_machine_id);
128
129 for (i = 0; i < sizeof(image); i++) {
130 (k->write)(nvram, i, image[i]);
131 }
132 }
133
134 void cpu_check_irqs(CPUSPARCState *env)
135 {
136 CPUState *cs;
137
138 /* We should be holding the BQL before we mess with IRQs */
139 g_assert(qemu_mutex_iothread_locked());
140
141 if (env->pil_in && (env->interrupt_index == 0 ||
142 (env->interrupt_index & ~15) == TT_EXTINT)) {
143 unsigned int i;
144
145 for (i = 15; i > 0; i--) {
146 if (env->pil_in & (1 << i)) {
147 int old_interrupt = env->interrupt_index;
148
149 env->interrupt_index = TT_EXTINT | i;
150 if (old_interrupt != env->interrupt_index) {
151 cs = CPU(sparc_env_get_cpu(env));
152 trace_sun4m_cpu_interrupt(i);
153 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
154 }
155 break;
156 }
157 }
158 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
159 cs = CPU(sparc_env_get_cpu(env));
160 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
161 env->interrupt_index = 0;
162 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
163 }
164 }
165
166 static void cpu_kick_irq(SPARCCPU *cpu)
167 {
168 CPUSPARCState *env = &cpu->env;
169 CPUState *cs = CPU(cpu);
170
171 cs->halted = 0;
172 cpu_check_irqs(env);
173 qemu_cpu_kick(cs);
174 }
175
176 static void cpu_set_irq(void *opaque, int irq, int level)
177 {
178 SPARCCPU *cpu = opaque;
179 CPUSPARCState *env = &cpu->env;
180
181 if (level) {
182 trace_sun4m_cpu_set_irq_raise(irq);
183 env->pil_in |= 1 << irq;
184 cpu_kick_irq(cpu);
185 } else {
186 trace_sun4m_cpu_set_irq_lower(irq);
187 env->pil_in &= ~(1 << irq);
188 cpu_check_irqs(env);
189 }
190 }
191
192 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
193 {
194 }
195
196 static void main_cpu_reset(void *opaque)
197 {
198 SPARCCPU *cpu = opaque;
199 CPUState *cs = CPU(cpu);
200
201 cpu_reset(cs);
202 cs->halted = 0;
203 }
204
205 static void secondary_cpu_reset(void *opaque)
206 {
207 SPARCCPU *cpu = opaque;
208 CPUState *cs = CPU(cpu);
209
210 cpu_reset(cs);
211 cs->halted = 1;
212 }
213
214 static void cpu_halt_signal(void *opaque, int irq, int level)
215 {
216 if (level && current_cpu) {
217 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
218 }
219 }
220
221 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
222 {
223 return addr - 0xf0000000ULL;
224 }
225
226 static unsigned long sun4m_load_kernel(const char *kernel_filename,
227 const char *initrd_filename,
228 ram_addr_t RAM_size)
229 {
230 int linux_boot;
231 unsigned int i;
232 long initrd_size, kernel_size;
233 uint8_t *ptr;
234
235 linux_boot = (kernel_filename != NULL);
236
237 kernel_size = 0;
238 if (linux_boot) {
239 int bswap_needed;
240
241 #ifdef BSWAP_NEEDED
242 bswap_needed = 1;
243 #else
244 bswap_needed = 0;
245 #endif
246 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
247 NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
248 if (kernel_size < 0)
249 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
250 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
251 TARGET_PAGE_SIZE);
252 if (kernel_size < 0)
253 kernel_size = load_image_targphys(kernel_filename,
254 KERNEL_LOAD_ADDR,
255 RAM_size - KERNEL_LOAD_ADDR);
256 if (kernel_size < 0) {
257 error_report("could not load kernel '%s'", kernel_filename);
258 exit(1);
259 }
260
261 /* load initrd */
262 initrd_size = 0;
263 if (initrd_filename) {
264 initrd_size = load_image_targphys(initrd_filename,
265 INITRD_LOAD_ADDR,
266 RAM_size - INITRD_LOAD_ADDR);
267 if (initrd_size < 0) {
268 error_report("could not load initial ram disk '%s'",
269 initrd_filename);
270 exit(1);
271 }
272 }
273 if (initrd_size > 0) {
274 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
275 ptr = rom_ptr(KERNEL_LOAD_ADDR + i, 24);
276 if (ptr && ldl_p(ptr) == 0x48647253) { /* HdrS */
277 stl_p(ptr + 16, INITRD_LOAD_ADDR);
278 stl_p(ptr + 20, initrd_size);
279 break;
280 }
281 }
282 }
283 }
284 return kernel_size;
285 }
286
287 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
288 {
289 DeviceState *dev;
290 SysBusDevice *s;
291
292 dev = qdev_create(NULL, TYPE_SUN4M_IOMMU);
293 qdev_prop_set_uint32(dev, "version", version);
294 qdev_init_nofail(dev);
295 s = SYS_BUS_DEVICE(dev);
296 sysbus_connect_irq(s, 0, irq);
297 sysbus_mmio_map(s, 0, addr);
298
299 return s;
300 }
301
302 static void *sparc32_dma_init(hwaddr dma_base,
303 hwaddr esp_base, qemu_irq espdma_irq,
304 hwaddr le_base, qemu_irq ledma_irq)
305 {
306 DeviceState *dma;
307 ESPDMADeviceState *espdma;
308 LEDMADeviceState *ledma;
309 SysBusESPState *esp;
310 SysBusPCNetState *lance;
311
312 dma = qdev_create(NULL, TYPE_SPARC32_DMA);
313 qdev_init_nofail(dma);
314 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base);
315
316 espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component(
317 OBJECT(dma), "espdma"));
318 sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq);
319
320 esp = ESP_STATE(object_resolve_path_component(OBJECT(espdma), "esp"));
321 sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base);
322 scsi_bus_legacy_handle_cmdline(&esp->esp.bus);
323
324 ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component(
325 OBJECT(dma), "ledma"));
326 sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq);
327
328 lance = SYSBUS_PCNET(object_resolve_path_component(
329 OBJECT(ledma), "lance"));
330 sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base);
331
332 return dma;
333 }
334
335 static DeviceState *slavio_intctl_init(hwaddr addr,
336 hwaddr addrg,
337 qemu_irq **parent_irq)
338 {
339 DeviceState *dev;
340 SysBusDevice *s;
341 unsigned int i, j;
342
343 dev = qdev_create(NULL, "slavio_intctl");
344 qdev_init_nofail(dev);
345
346 s = SYS_BUS_DEVICE(dev);
347
348 for (i = 0; i < MAX_CPUS; i++) {
349 for (j = 0; j < MAX_PILS; j++) {
350 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
351 }
352 }
353 sysbus_mmio_map(s, 0, addrg);
354 for (i = 0; i < MAX_CPUS; i++) {
355 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
356 }
357
358 return dev;
359 }
360
361 #define SYS_TIMER_OFFSET 0x10000ULL
362 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
363
364 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
365 qemu_irq *cpu_irqs, unsigned int num_cpus)
366 {
367 DeviceState *dev;
368 SysBusDevice *s;
369 unsigned int i;
370
371 dev = qdev_create(NULL, "slavio_timer");
372 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
373 qdev_init_nofail(dev);
374 s = SYS_BUS_DEVICE(dev);
375 sysbus_connect_irq(s, 0, master_irq);
376 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
377
378 for (i = 0; i < MAX_CPUS; i++) {
379 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
380 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
381 }
382 }
383
384 static qemu_irq slavio_system_powerdown;
385
386 static void slavio_powerdown_req(Notifier *n, void *opaque)
387 {
388 qemu_irq_raise(slavio_system_powerdown);
389 }
390
391 static Notifier slavio_system_powerdown_notifier = {
392 .notify = slavio_powerdown_req
393 };
394
395 #define MISC_LEDS 0x01600000
396 #define MISC_CFG 0x01800000
397 #define MISC_DIAG 0x01a00000
398 #define MISC_MDM 0x01b00000
399 #define MISC_SYS 0x01f00000
400
401 static void slavio_misc_init(hwaddr base,
402 hwaddr aux1_base,
403 hwaddr aux2_base, qemu_irq irq,
404 qemu_irq fdc_tc)
405 {
406 DeviceState *dev;
407 SysBusDevice *s;
408
409 dev = qdev_create(NULL, "slavio_misc");
410 qdev_init_nofail(dev);
411 s = SYS_BUS_DEVICE(dev);
412 if (base) {
413 /* 8 bit registers */
414 /* Slavio control */
415 sysbus_mmio_map(s, 0, base + MISC_CFG);
416 /* Diagnostics */
417 sysbus_mmio_map(s, 1, base + MISC_DIAG);
418 /* Modem control */
419 sysbus_mmio_map(s, 2, base + MISC_MDM);
420 /* 16 bit registers */
421 /* ss600mp diag LEDs */
422 sysbus_mmio_map(s, 3, base + MISC_LEDS);
423 /* 32 bit registers */
424 /* System control */
425 sysbus_mmio_map(s, 4, base + MISC_SYS);
426 }
427 if (aux1_base) {
428 /* AUX 1 (Misc System Functions) */
429 sysbus_mmio_map(s, 5, aux1_base);
430 }
431 if (aux2_base) {
432 /* AUX 2 (Software Powerdown Control) */
433 sysbus_mmio_map(s, 6, aux2_base);
434 }
435 sysbus_connect_irq(s, 0, irq);
436 sysbus_connect_irq(s, 1, fdc_tc);
437 slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
438 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
439 }
440
441 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
442 {
443 DeviceState *dev;
444 SysBusDevice *s;
445
446 dev = qdev_create(NULL, "eccmemctl");
447 qdev_prop_set_uint32(dev, "version", version);
448 qdev_init_nofail(dev);
449 s = SYS_BUS_DEVICE(dev);
450 sysbus_connect_irq(s, 0, irq);
451 sysbus_mmio_map(s, 0, base);
452 if (version == 0) { // SS-600MP only
453 sysbus_mmio_map(s, 1, base + 0x1000);
454 }
455 }
456
457 static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
458 {
459 DeviceState *dev;
460 SysBusDevice *s;
461
462 dev = qdev_create(NULL, "apc");
463 qdev_init_nofail(dev);
464 s = SYS_BUS_DEVICE(dev);
465 /* Power management (APC) XXX: not a Slavio device */
466 sysbus_mmio_map(s, 0, power_base);
467 sysbus_connect_irq(s, 0, cpu_halt);
468 }
469
470 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
471 int height, int depth)
472 {
473 DeviceState *dev;
474 SysBusDevice *s;
475
476 dev = qdev_create(NULL, "SUNW,tcx");
477 qdev_prop_set_uint32(dev, "vram_size", vram_size);
478 qdev_prop_set_uint16(dev, "width", width);
479 qdev_prop_set_uint16(dev, "height", height);
480 qdev_prop_set_uint16(dev, "depth", depth);
481 qdev_init_nofail(dev);
482 s = SYS_BUS_DEVICE(dev);
483
484 /* 10/ROM : FCode ROM */
485 sysbus_mmio_map(s, 0, addr);
486 /* 2/STIP : Stipple */
487 sysbus_mmio_map(s, 1, addr + 0x04000000ULL);
488 /* 3/BLIT : Blitter */
489 sysbus_mmio_map(s, 2, addr + 0x06000000ULL);
490 /* 5/RSTIP : Raw Stipple */
491 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL);
492 /* 6/RBLIT : Raw Blitter */
493 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL);
494 /* 7/TEC : Transform Engine */
495 sysbus_mmio_map(s, 5, addr + 0x00700000ULL);
496 /* 8/CMAP : DAC */
497 sysbus_mmio_map(s, 6, addr + 0x00200000ULL);
498 /* 9/THC : */
499 if (depth == 8) {
500 sysbus_mmio_map(s, 7, addr + 0x00300000ULL);
501 } else {
502 sysbus_mmio_map(s, 7, addr + 0x00301000ULL);
503 }
504 /* 11/DHC : */
505 sysbus_mmio_map(s, 8, addr + 0x00240000ULL);
506 /* 12/ALT : */
507 sysbus_mmio_map(s, 9, addr + 0x00280000ULL);
508 /* 0/DFB8 : 8-bit plane */
509 sysbus_mmio_map(s, 10, addr + 0x00800000ULL);
510 /* 1/DFB24 : 24bit plane */
511 sysbus_mmio_map(s, 11, addr + 0x02000000ULL);
512 /* 4/RDFB32: Raw framebuffer. Control plane */
513 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL);
514 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
515 if (depth == 8) {
516 sysbus_mmio_map(s, 13, addr + 0x00301000ULL);
517 }
518
519 sysbus_connect_irq(s, 0, irq);
520 }
521
522 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
523 int height, int depth)
524 {
525 DeviceState *dev;
526 SysBusDevice *s;
527
528 dev = qdev_create(NULL, "cgthree");
529 qdev_prop_set_uint32(dev, "vram-size", vram_size);
530 qdev_prop_set_uint16(dev, "width", width);
531 qdev_prop_set_uint16(dev, "height", height);
532 qdev_prop_set_uint16(dev, "depth", depth);
533 qdev_init_nofail(dev);
534 s = SYS_BUS_DEVICE(dev);
535
536 /* FCode ROM */
537 sysbus_mmio_map(s, 0, addr);
538 /* DAC */
539 sysbus_mmio_map(s, 1, addr + 0x400000ULL);
540 /* 8-bit plane */
541 sysbus_mmio_map(s, 2, addr + 0x800000ULL);
542
543 sysbus_connect_irq(s, 0, irq);
544 }
545
546 /* NCR89C100/MACIO Internal ID register */
547
548 #define TYPE_MACIO_ID_REGISTER "macio_idreg"
549
550 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
551
552 static void idreg_init(hwaddr addr)
553 {
554 DeviceState *dev;
555 SysBusDevice *s;
556
557 dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER);
558 qdev_init_nofail(dev);
559 s = SYS_BUS_DEVICE(dev);
560
561 sysbus_mmio_map(s, 0, addr);
562 address_space_write_rom(&address_space_memory, addr,
563 MEMTXATTRS_UNSPECIFIED,
564 idreg_data, sizeof(idreg_data));
565 }
566
567 #define MACIO_ID_REGISTER(obj) \
568 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER)
569
570 typedef struct IDRegState {
571 SysBusDevice parent_obj;
572
573 MemoryRegion mem;
574 } IDRegState;
575
576 static void idreg_realize(DeviceState *ds, Error **errp)
577 {
578 IDRegState *s = MACIO_ID_REGISTER(ds);
579 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
580 Error *local_err = NULL;
581
582 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.idreg",
583 sizeof(idreg_data), &local_err);
584 if (local_err) {
585 error_propagate(errp, local_err);
586 return;
587 }
588
589 vmstate_register_ram_global(&s->mem);
590 memory_region_set_readonly(&s->mem, true);
591 sysbus_init_mmio(dev, &s->mem);
592 }
593
594 static void idreg_class_init(ObjectClass *oc, void *data)
595 {
596 DeviceClass *dc = DEVICE_CLASS(oc);
597
598 dc->realize = idreg_realize;
599 }
600
601 static const TypeInfo idreg_info = {
602 .name = TYPE_MACIO_ID_REGISTER,
603 .parent = TYPE_SYS_BUS_DEVICE,
604 .instance_size = sizeof(IDRegState),
605 .class_init = idreg_class_init,
606 };
607
608 #define TYPE_TCX_AFX "tcx_afx"
609 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX)
610
611 typedef struct AFXState {
612 SysBusDevice parent_obj;
613
614 MemoryRegion mem;
615 } AFXState;
616
617 /* SS-5 TCX AFX register */
618 static void afx_init(hwaddr addr)
619 {
620 DeviceState *dev;
621 SysBusDevice *s;
622
623 dev = qdev_create(NULL, TYPE_TCX_AFX);
624 qdev_init_nofail(dev);
625 s = SYS_BUS_DEVICE(dev);
626
627 sysbus_mmio_map(s, 0, addr);
628 }
629
630 static void afx_realize(DeviceState *ds, Error **errp)
631 {
632 AFXState *s = TCX_AFX(ds);
633 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
634 Error *local_err = NULL;
635
636 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.afx", 4,
637 &local_err);
638 if (local_err) {
639 error_propagate(errp, local_err);
640 return;
641 }
642
643 vmstate_register_ram_global(&s->mem);
644 sysbus_init_mmio(dev, &s->mem);
645 }
646
647 static void afx_class_init(ObjectClass *oc, void *data)
648 {
649 DeviceClass *dc = DEVICE_CLASS(oc);
650
651 dc->realize = afx_realize;
652 }
653
654 static const TypeInfo afx_info = {
655 .name = TYPE_TCX_AFX,
656 .parent = TYPE_SYS_BUS_DEVICE,
657 .instance_size = sizeof(AFXState),
658 .class_init = afx_class_init,
659 };
660
661 #define TYPE_OPENPROM "openprom"
662 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
663
664 typedef struct PROMState {
665 SysBusDevice parent_obj;
666
667 MemoryRegion prom;
668 } PROMState;
669
670 /* Boot PROM (OpenBIOS) */
671 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
672 {
673 hwaddr *base_addr = (hwaddr *)opaque;
674 return addr + *base_addr - PROM_VADDR;
675 }
676
677 static void prom_init(hwaddr addr, const char *bios_name)
678 {
679 DeviceState *dev;
680 SysBusDevice *s;
681 char *filename;
682 int ret;
683
684 dev = qdev_create(NULL, TYPE_OPENPROM);
685 qdev_init_nofail(dev);
686 s = SYS_BUS_DEVICE(dev);
687
688 sysbus_mmio_map(s, 0, addr);
689
690 /* load boot prom */
691 if (bios_name == NULL) {
692 bios_name = PROM_FILENAME;
693 }
694 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
695 if (filename) {
696 ret = load_elf(filename, translate_prom_address, &addr, NULL,
697 NULL, NULL, 1, EM_SPARC, 0, 0);
698 if (ret < 0 || ret > PROM_SIZE_MAX) {
699 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
700 }
701 g_free(filename);
702 } else {
703 ret = -1;
704 }
705 if (ret < 0 || ret > PROM_SIZE_MAX) {
706 error_report("could not load prom '%s'", bios_name);
707 exit(1);
708 }
709 }
710
711 static void prom_realize(DeviceState *ds, Error **errp)
712 {
713 PROMState *s = OPENPROM(ds);
714 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
715 Error *local_err = NULL;
716
717 memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4m.prom",
718 PROM_SIZE_MAX, &local_err);
719 if (local_err) {
720 error_propagate(errp, local_err);
721 return;
722 }
723
724 vmstate_register_ram_global(&s->prom);
725 memory_region_set_readonly(&s->prom, true);
726 sysbus_init_mmio(dev, &s->prom);
727 }
728
729 static Property prom_properties[] = {
730 {/* end of property list */},
731 };
732
733 static void prom_class_init(ObjectClass *klass, void *data)
734 {
735 DeviceClass *dc = DEVICE_CLASS(klass);
736
737 dc->props = prom_properties;
738 dc->realize = prom_realize;
739 }
740
741 static const TypeInfo prom_info = {
742 .name = TYPE_OPENPROM,
743 .parent = TYPE_SYS_BUS_DEVICE,
744 .instance_size = sizeof(PROMState),
745 .class_init = prom_class_init,
746 };
747
748 #define TYPE_SUN4M_MEMORY "memory"
749 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY)
750
751 typedef struct RamDevice {
752 SysBusDevice parent_obj;
753
754 MemoryRegion ram;
755 uint64_t size;
756 } RamDevice;
757
758 /* System RAM */
759 static void ram_realize(DeviceState *dev, Error **errp)
760 {
761 RamDevice *d = SUN4M_RAM(dev);
762 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
763
764 memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram",
765 d->size);
766 sysbus_init_mmio(sbd, &d->ram);
767 }
768
769 static void ram_init(hwaddr addr, ram_addr_t RAM_size,
770 uint64_t max_mem)
771 {
772 DeviceState *dev;
773 SysBusDevice *s;
774 RamDevice *d;
775
776 /* allocate RAM */
777 if ((uint64_t)RAM_size > max_mem) {
778 error_report("Too much memory for this machine: %" PRId64 ","
779 " maximum %" PRId64,
780 RAM_size / MiB, max_mem / MiB);
781 exit(1);
782 }
783 dev = qdev_create(NULL, "memory");
784 s = SYS_BUS_DEVICE(dev);
785
786 d = SUN4M_RAM(dev);
787 d->size = RAM_size;
788 qdev_init_nofail(dev);
789
790 sysbus_mmio_map(s, 0, addr);
791 }
792
793 static Property ram_properties[] = {
794 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
795 DEFINE_PROP_END_OF_LIST(),
796 };
797
798 static void ram_class_init(ObjectClass *klass, void *data)
799 {
800 DeviceClass *dc = DEVICE_CLASS(klass);
801
802 dc->realize = ram_realize;
803 dc->props = ram_properties;
804 }
805
806 static const TypeInfo ram_info = {
807 .name = TYPE_SUN4M_MEMORY,
808 .parent = TYPE_SYS_BUS_DEVICE,
809 .instance_size = sizeof(RamDevice),
810 .class_init = ram_class_init,
811 };
812
813 static void cpu_devinit(const char *cpu_type, unsigned int id,
814 uint64_t prom_addr, qemu_irq **cpu_irqs)
815 {
816 CPUState *cs;
817 SPARCCPU *cpu;
818 CPUSPARCState *env;
819
820 cpu = SPARC_CPU(cpu_create(cpu_type));
821 env = &cpu->env;
822
823 cpu_sparc_set_id(env, id);
824 if (id == 0) {
825 qemu_register_reset(main_cpu_reset, cpu);
826 } else {
827 qemu_register_reset(secondary_cpu_reset, cpu);
828 cs = CPU(cpu);
829 cs->halted = 1;
830 }
831 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
832 env->prom_addr = prom_addr;
833 }
834
835 static void dummy_fdc_tc(void *opaque, int irq, int level)
836 {
837 }
838
839 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
840 MachineState *machine)
841 {
842 DeviceState *slavio_intctl;
843 unsigned int i;
844 void *nvram;
845 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS];
846 qemu_irq fdc_tc;
847 unsigned long kernel_size;
848 DriveInfo *fd[MAX_FD];
849 FWCfgState *fw_cfg;
850 unsigned int num_vsimms;
851 DeviceState *dev;
852 SysBusDevice *s;
853
854 /* init CPUs */
855 for(i = 0; i < smp_cpus; i++) {
856 cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]);
857 }
858
859 for (i = smp_cpus; i < MAX_CPUS; i++)
860 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
861
862
863 /* set up devices */
864 ram_init(0, machine->ram_size, hwdef->max_mem);
865 /* models without ECC don't trap when missing ram is accessed */
866 if (!hwdef->ecc_base) {
867 empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size);
868 }
869
870 prom_init(hwdef->slavio_base, bios_name);
871
872 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
873 hwdef->intctl_base + 0x10000ULL,
874 cpu_irqs);
875
876 for (i = 0; i < 32; i++) {
877 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
878 }
879 for (i = 0; i < MAX_CPUS; i++) {
880 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
881 }
882
883 if (hwdef->idreg_base) {
884 idreg_init(hwdef->idreg_base);
885 }
886
887 if (hwdef->afx_base) {
888 afx_init(hwdef->afx_base);
889 }
890
891 iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]);
892
893 if (hwdef->iommu_pad_base) {
894 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
895 Software shouldn't use aliased addresses, neither should it crash
896 when does. Using empty_slot instead of aliasing can help with
897 debugging such accesses */
898 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
899 }
900
901 sparc32_dma_init(hwdef->dma_base,
902 hwdef->esp_base, slavio_irq[18],
903 hwdef->le_base, slavio_irq[16]);
904
905 if (graphic_depth != 8 && graphic_depth != 24) {
906 error_report("Unsupported depth: %d", graphic_depth);
907 exit (1);
908 }
909 num_vsimms = 0;
910 if (num_vsimms == 0) {
911 if (vga_interface_type == VGA_CG3) {
912 if (graphic_depth != 8) {
913 error_report("Unsupported depth: %d", graphic_depth);
914 exit(1);
915 }
916
917 if (!(graphic_width == 1024 && graphic_height == 768) &&
918 !(graphic_width == 1152 && graphic_height == 900)) {
919 error_report("Unsupported resolution: %d x %d", graphic_width,
920 graphic_height);
921 exit(1);
922 }
923
924 /* sbus irq 5 */
925 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
926 graphic_width, graphic_height, graphic_depth);
927 } else {
928 /* If no display specified, default to TCX */
929 if (graphic_depth != 8 && graphic_depth != 24) {
930 error_report("Unsupported depth: %d", graphic_depth);
931 exit(1);
932 }
933
934 if (!(graphic_width == 1024 && graphic_height == 768)) {
935 error_report("Unsupported resolution: %d x %d",
936 graphic_width, graphic_height);
937 exit(1);
938 }
939
940 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
941 graphic_width, graphic_height, graphic_depth);
942 }
943 }
944
945 for (i = num_vsimms; i < MAX_VSIMMS; i++) {
946 /* vsimm registers probed by OBP */
947 if (hwdef->vsimm[i].reg_base) {
948 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
949 }
950 }
951
952 if (hwdef->sx_base) {
953 empty_slot_init(hwdef->sx_base, 0x2000);
954 }
955
956 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8);
957
958 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
959
960 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
961 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
962 dev = qdev_create(NULL, TYPE_ESCC);
963 qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics);
964 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
965 qdev_prop_set_uint32(dev, "it_shift", 1);
966 qdev_prop_set_chr(dev, "chrB", NULL);
967 qdev_prop_set_chr(dev, "chrA", NULL);
968 qdev_prop_set_uint32(dev, "chnBtype", escc_mouse);
969 qdev_prop_set_uint32(dev, "chnAtype", escc_kbd);
970 qdev_init_nofail(dev);
971 s = SYS_BUS_DEVICE(dev);
972 sysbus_connect_irq(s, 0, slavio_irq[14]);
973 sysbus_connect_irq(s, 1, slavio_irq[14]);
974 sysbus_mmio_map(s, 0, hwdef->ms_kb_base);
975
976 dev = qdev_create(NULL, TYPE_ESCC);
977 qdev_prop_set_uint32(dev, "disabled", 0);
978 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
979 qdev_prop_set_uint32(dev, "it_shift", 1);
980 qdev_prop_set_chr(dev, "chrB", serial_hd(1));
981 qdev_prop_set_chr(dev, "chrA", serial_hd(0));
982 qdev_prop_set_uint32(dev, "chnBtype", escc_serial);
983 qdev_prop_set_uint32(dev, "chnAtype", escc_serial);
984 qdev_init_nofail(dev);
985
986 s = SYS_BUS_DEVICE(dev);
987 sysbus_connect_irq(s, 0, slavio_irq[15]);
988 sysbus_connect_irq(s, 1, slavio_irq[15]);
989 sysbus_mmio_map(s, 0, hwdef->serial_base);
990
991 if (hwdef->apc_base) {
992 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0));
993 }
994
995 if (hwdef->fd_base) {
996 /* there is zero or one floppy drive */
997 memset(fd, 0, sizeof(fd));
998 fd[0] = drive_get(IF_FLOPPY, 0, 0);
999 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
1000 &fdc_tc);
1001 } else {
1002 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0);
1003 }
1004
1005 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
1006 slavio_irq[30], fdc_tc);
1007
1008 if (hwdef->cs_base) {
1009 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
1010 slavio_irq[5]);
1011 }
1012
1013 if (hwdef->dbri_base) {
1014 /* ISDN chip with attached CS4215 audio codec */
1015 /* prom space */
1016 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
1017 /* reg space */
1018 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
1019 }
1020
1021 if (hwdef->bpp_base) {
1022 /* parallel port */
1023 empty_slot_init(hwdef->bpp_base, 0x20);
1024 }
1025
1026 kernel_size = sun4m_load_kernel(machine->kernel_filename,
1027 machine->initrd_filename,
1028 machine->ram_size);
1029
1030 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline,
1031 machine->boot_order, machine->ram_size, kernel_size,
1032 graphic_width, graphic_height, graphic_depth,
1033 hwdef->nvram_machine_id, "Sun4m");
1034
1035 if (hwdef->ecc_base)
1036 ecc_init(hwdef->ecc_base, slavio_irq[28],
1037 hwdef->ecc_version);
1038
1039 dev = qdev_create(NULL, TYPE_FW_CFG_MEM);
1040 fw_cfg = FW_CFG(dev);
1041 qdev_prop_set_uint32(dev, "data_width", 1);
1042 qdev_prop_set_bit(dev, "dma_enabled", false);
1043 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
1044 OBJECT(fw_cfg), NULL);
1045 qdev_init_nofail(dev);
1046 s = SYS_BUS_DEVICE(dev);
1047 sysbus_mmio_map(s, 0, CFG_ADDR);
1048 sysbus_mmio_map(s, 1, CFG_ADDR + 2);
1049
1050 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
1051 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1052 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1053 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1054 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1055 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width);
1056 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height);
1057 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1058 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1059 if (machine->kernel_cmdline) {
1060 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1061 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
1062 machine->kernel_cmdline);
1063 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
1064 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1065 strlen(machine->kernel_cmdline) + 1);
1066 } else {
1067 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1068 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1069 }
1070 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1071 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1072 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
1073 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1074 }
1075
1076 enum {
1077 ss5_id = 32,
1078 vger_id,
1079 lx_id,
1080 ss4_id,
1081 scls_id,
1082 sbook_id,
1083 ss10_id = 64,
1084 ss20_id,
1085 ss600mp_id,
1086 };
1087
1088 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1089 /* SS-5 */
1090 {
1091 .iommu_base = 0x10000000,
1092 .iommu_pad_base = 0x10004000,
1093 .iommu_pad_len = 0x0fffb000,
1094 .tcx_base = 0x50000000,
1095 .cs_base = 0x6c000000,
1096 .slavio_base = 0x70000000,
1097 .ms_kb_base = 0x71000000,
1098 .serial_base = 0x71100000,
1099 .nvram_base = 0x71200000,
1100 .fd_base = 0x71400000,
1101 .counter_base = 0x71d00000,
1102 .intctl_base = 0x71e00000,
1103 .idreg_base = 0x78000000,
1104 .dma_base = 0x78400000,
1105 .esp_base = 0x78800000,
1106 .le_base = 0x78c00000,
1107 .apc_base = 0x6a000000,
1108 .afx_base = 0x6e000000,
1109 .aux1_base = 0x71900000,
1110 .aux2_base = 0x71910000,
1111 .nvram_machine_id = 0x80,
1112 .machine_id = ss5_id,
1113 .iommu_version = 0x05000000,
1114 .max_mem = 0x10000000,
1115 },
1116 /* SS-10 */
1117 {
1118 .iommu_base = 0xfe0000000ULL,
1119 .tcx_base = 0xe20000000ULL,
1120 .slavio_base = 0xff0000000ULL,
1121 .ms_kb_base = 0xff1000000ULL,
1122 .serial_base = 0xff1100000ULL,
1123 .nvram_base = 0xff1200000ULL,
1124 .fd_base = 0xff1700000ULL,
1125 .counter_base = 0xff1300000ULL,
1126 .intctl_base = 0xff1400000ULL,
1127 .idreg_base = 0xef0000000ULL,
1128 .dma_base = 0xef0400000ULL,
1129 .esp_base = 0xef0800000ULL,
1130 .le_base = 0xef0c00000ULL,
1131 .apc_base = 0xefa000000ULL, // XXX should not exist
1132 .aux1_base = 0xff1800000ULL,
1133 .aux2_base = 0xff1a01000ULL,
1134 .ecc_base = 0xf00000000ULL,
1135 .ecc_version = 0x10000000, // version 0, implementation 1
1136 .nvram_machine_id = 0x72,
1137 .machine_id = ss10_id,
1138 .iommu_version = 0x03000000,
1139 .max_mem = 0xf00000000ULL,
1140 },
1141 /* SS-600MP */
1142 {
1143 .iommu_base = 0xfe0000000ULL,
1144 .tcx_base = 0xe20000000ULL,
1145 .slavio_base = 0xff0000000ULL,
1146 .ms_kb_base = 0xff1000000ULL,
1147 .serial_base = 0xff1100000ULL,
1148 .nvram_base = 0xff1200000ULL,
1149 .counter_base = 0xff1300000ULL,
1150 .intctl_base = 0xff1400000ULL,
1151 .dma_base = 0xef0081000ULL,
1152 .esp_base = 0xef0080000ULL,
1153 .le_base = 0xef0060000ULL,
1154 .apc_base = 0xefa000000ULL, // XXX should not exist
1155 .aux1_base = 0xff1800000ULL,
1156 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1157 .ecc_base = 0xf00000000ULL,
1158 .ecc_version = 0x00000000, // version 0, implementation 0
1159 .nvram_machine_id = 0x71,
1160 .machine_id = ss600mp_id,
1161 .iommu_version = 0x01000000,
1162 .max_mem = 0xf00000000ULL,
1163 },
1164 /* SS-20 */
1165 {
1166 .iommu_base = 0xfe0000000ULL,
1167 .tcx_base = 0xe20000000ULL,
1168 .slavio_base = 0xff0000000ULL,
1169 .ms_kb_base = 0xff1000000ULL,
1170 .serial_base = 0xff1100000ULL,
1171 .nvram_base = 0xff1200000ULL,
1172 .fd_base = 0xff1700000ULL,
1173 .counter_base = 0xff1300000ULL,
1174 .intctl_base = 0xff1400000ULL,
1175 .idreg_base = 0xef0000000ULL,
1176 .dma_base = 0xef0400000ULL,
1177 .esp_base = 0xef0800000ULL,
1178 .le_base = 0xef0c00000ULL,
1179 .bpp_base = 0xef4800000ULL,
1180 .apc_base = 0xefa000000ULL, // XXX should not exist
1181 .aux1_base = 0xff1800000ULL,
1182 .aux2_base = 0xff1a01000ULL,
1183 .dbri_base = 0xee0000000ULL,
1184 .sx_base = 0xf80000000ULL,
1185 .vsimm = {
1186 {
1187 .reg_base = 0x9c000000ULL,
1188 .vram_base = 0xfc000000ULL
1189 }, {
1190 .reg_base = 0x90000000ULL,
1191 .vram_base = 0xf0000000ULL
1192 }, {
1193 .reg_base = 0x94000000ULL
1194 }, {
1195 .reg_base = 0x98000000ULL
1196 }
1197 },
1198 .ecc_base = 0xf00000000ULL,
1199 .ecc_version = 0x20000000, // version 0, implementation 2
1200 .nvram_machine_id = 0x72,
1201 .machine_id = ss20_id,
1202 .iommu_version = 0x13000000,
1203 .max_mem = 0xf00000000ULL,
1204 },
1205 /* Voyager */
1206 {
1207 .iommu_base = 0x10000000,
1208 .tcx_base = 0x50000000,
1209 .slavio_base = 0x70000000,
1210 .ms_kb_base = 0x71000000,
1211 .serial_base = 0x71100000,
1212 .nvram_base = 0x71200000,
1213 .fd_base = 0x71400000,
1214 .counter_base = 0x71d00000,
1215 .intctl_base = 0x71e00000,
1216 .idreg_base = 0x78000000,
1217 .dma_base = 0x78400000,
1218 .esp_base = 0x78800000,
1219 .le_base = 0x78c00000,
1220 .apc_base = 0x71300000, // pmc
1221 .aux1_base = 0x71900000,
1222 .aux2_base = 0x71910000,
1223 .nvram_machine_id = 0x80,
1224 .machine_id = vger_id,
1225 .iommu_version = 0x05000000,
1226 .max_mem = 0x10000000,
1227 },
1228 /* LX */
1229 {
1230 .iommu_base = 0x10000000,
1231 .iommu_pad_base = 0x10004000,
1232 .iommu_pad_len = 0x0fffb000,
1233 .tcx_base = 0x50000000,
1234 .slavio_base = 0x70000000,
1235 .ms_kb_base = 0x71000000,
1236 .serial_base = 0x71100000,
1237 .nvram_base = 0x71200000,
1238 .fd_base = 0x71400000,
1239 .counter_base = 0x71d00000,
1240 .intctl_base = 0x71e00000,
1241 .idreg_base = 0x78000000,
1242 .dma_base = 0x78400000,
1243 .esp_base = 0x78800000,
1244 .le_base = 0x78c00000,
1245 .aux1_base = 0x71900000,
1246 .aux2_base = 0x71910000,
1247 .nvram_machine_id = 0x80,
1248 .machine_id = lx_id,
1249 .iommu_version = 0x04000000,
1250 .max_mem = 0x10000000,
1251 },
1252 /* SS-4 */
1253 {
1254 .iommu_base = 0x10000000,
1255 .tcx_base = 0x50000000,
1256 .cs_base = 0x6c000000,
1257 .slavio_base = 0x70000000,
1258 .ms_kb_base = 0x71000000,
1259 .serial_base = 0x71100000,
1260 .nvram_base = 0x71200000,
1261 .fd_base = 0x71400000,
1262 .counter_base = 0x71d00000,
1263 .intctl_base = 0x71e00000,
1264 .idreg_base = 0x78000000,
1265 .dma_base = 0x78400000,
1266 .esp_base = 0x78800000,
1267 .le_base = 0x78c00000,
1268 .apc_base = 0x6a000000,
1269 .aux1_base = 0x71900000,
1270 .aux2_base = 0x71910000,
1271 .nvram_machine_id = 0x80,
1272 .machine_id = ss4_id,
1273 .iommu_version = 0x05000000,
1274 .max_mem = 0x10000000,
1275 },
1276 /* SPARCClassic */
1277 {
1278 .iommu_base = 0x10000000,
1279 .tcx_base = 0x50000000,
1280 .slavio_base = 0x70000000,
1281 .ms_kb_base = 0x71000000,
1282 .serial_base = 0x71100000,
1283 .nvram_base = 0x71200000,
1284 .fd_base = 0x71400000,
1285 .counter_base = 0x71d00000,
1286 .intctl_base = 0x71e00000,
1287 .idreg_base = 0x78000000,
1288 .dma_base = 0x78400000,
1289 .esp_base = 0x78800000,
1290 .le_base = 0x78c00000,
1291 .apc_base = 0x6a000000,
1292 .aux1_base = 0x71900000,
1293 .aux2_base = 0x71910000,
1294 .nvram_machine_id = 0x80,
1295 .machine_id = scls_id,
1296 .iommu_version = 0x05000000,
1297 .max_mem = 0x10000000,
1298 },
1299 /* SPARCbook */
1300 {
1301 .iommu_base = 0x10000000,
1302 .tcx_base = 0x50000000, // XXX
1303 .slavio_base = 0x70000000,
1304 .ms_kb_base = 0x71000000,
1305 .serial_base = 0x71100000,
1306 .nvram_base = 0x71200000,
1307 .fd_base = 0x71400000,
1308 .counter_base = 0x71d00000,
1309 .intctl_base = 0x71e00000,
1310 .idreg_base = 0x78000000,
1311 .dma_base = 0x78400000,
1312 .esp_base = 0x78800000,
1313 .le_base = 0x78c00000,
1314 .apc_base = 0x6a000000,
1315 .aux1_base = 0x71900000,
1316 .aux2_base = 0x71910000,
1317 .nvram_machine_id = 0x80,
1318 .machine_id = sbook_id,
1319 .iommu_version = 0x05000000,
1320 .max_mem = 0x10000000,
1321 },
1322 };
1323
1324 /* SPARCstation 5 hardware initialisation */
1325 static void ss5_init(MachineState *machine)
1326 {
1327 sun4m_hw_init(&sun4m_hwdefs[0], machine);
1328 }
1329
1330 /* SPARCstation 10 hardware initialisation */
1331 static void ss10_init(MachineState *machine)
1332 {
1333 sun4m_hw_init(&sun4m_hwdefs[1], machine);
1334 }
1335
1336 /* SPARCserver 600MP hardware initialisation */
1337 static void ss600mp_init(MachineState *machine)
1338 {
1339 sun4m_hw_init(&sun4m_hwdefs[2], machine);
1340 }
1341
1342 /* SPARCstation 20 hardware initialisation */
1343 static void ss20_init(MachineState *machine)
1344 {
1345 sun4m_hw_init(&sun4m_hwdefs[3], machine);
1346 }
1347
1348 /* SPARCstation Voyager hardware initialisation */
1349 static void vger_init(MachineState *machine)
1350 {
1351 sun4m_hw_init(&sun4m_hwdefs[4], machine);
1352 }
1353
1354 /* SPARCstation LX hardware initialisation */
1355 static void ss_lx_init(MachineState *machine)
1356 {
1357 sun4m_hw_init(&sun4m_hwdefs[5], machine);
1358 }
1359
1360 /* SPARCstation 4 hardware initialisation */
1361 static void ss4_init(MachineState *machine)
1362 {
1363 sun4m_hw_init(&sun4m_hwdefs[6], machine);
1364 }
1365
1366 /* SPARCClassic hardware initialisation */
1367 static void scls_init(MachineState *machine)
1368 {
1369 sun4m_hw_init(&sun4m_hwdefs[7], machine);
1370 }
1371
1372 /* SPARCbook hardware initialisation */
1373 static void sbook_init(MachineState *machine)
1374 {
1375 sun4m_hw_init(&sun4m_hwdefs[8], machine);
1376 }
1377
1378 static void ss5_class_init(ObjectClass *oc, void *data)
1379 {
1380 MachineClass *mc = MACHINE_CLASS(oc);
1381
1382 mc->desc = "Sun4m platform, SPARCstation 5";
1383 mc->init = ss5_init;
1384 mc->block_default_type = IF_SCSI;
1385 mc->is_default = 1;
1386 mc->default_boot_order = "c";
1387 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1388 }
1389
1390 static const TypeInfo ss5_type = {
1391 .name = MACHINE_TYPE_NAME("SS-5"),
1392 .parent = TYPE_MACHINE,
1393 .class_init = ss5_class_init,
1394 };
1395
1396 static void ss10_class_init(ObjectClass *oc, void *data)
1397 {
1398 MachineClass *mc = MACHINE_CLASS(oc);
1399
1400 mc->desc = "Sun4m platform, SPARCstation 10";
1401 mc->init = ss10_init;
1402 mc->block_default_type = IF_SCSI;
1403 mc->max_cpus = 4;
1404 mc->default_boot_order = "c";
1405 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1406 }
1407
1408 static const TypeInfo ss10_type = {
1409 .name = MACHINE_TYPE_NAME("SS-10"),
1410 .parent = TYPE_MACHINE,
1411 .class_init = ss10_class_init,
1412 };
1413
1414 static void ss600mp_class_init(ObjectClass *oc, void *data)
1415 {
1416 MachineClass *mc = MACHINE_CLASS(oc);
1417
1418 mc->desc = "Sun4m platform, SPARCserver 600MP";
1419 mc->init = ss600mp_init;
1420 mc->block_default_type = IF_SCSI;
1421 mc->max_cpus = 4;
1422 mc->default_boot_order = "c";
1423 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1424 }
1425
1426 static const TypeInfo ss600mp_type = {
1427 .name = MACHINE_TYPE_NAME("SS-600MP"),
1428 .parent = TYPE_MACHINE,
1429 .class_init = ss600mp_class_init,
1430 };
1431
1432 static void ss20_class_init(ObjectClass *oc, void *data)
1433 {
1434 MachineClass *mc = MACHINE_CLASS(oc);
1435
1436 mc->desc = "Sun4m platform, SPARCstation 20";
1437 mc->init = ss20_init;
1438 mc->block_default_type = IF_SCSI;
1439 mc->max_cpus = 4;
1440 mc->default_boot_order = "c";
1441 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1442 }
1443
1444 static const TypeInfo ss20_type = {
1445 .name = MACHINE_TYPE_NAME("SS-20"),
1446 .parent = TYPE_MACHINE,
1447 .class_init = ss20_class_init,
1448 };
1449
1450 static void voyager_class_init(ObjectClass *oc, void *data)
1451 {
1452 MachineClass *mc = MACHINE_CLASS(oc);
1453
1454 mc->desc = "Sun4m platform, SPARCstation Voyager";
1455 mc->init = vger_init;
1456 mc->block_default_type = IF_SCSI;
1457 mc->default_boot_order = "c";
1458 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1459 }
1460
1461 static const TypeInfo voyager_type = {
1462 .name = MACHINE_TYPE_NAME("Voyager"),
1463 .parent = TYPE_MACHINE,
1464 .class_init = voyager_class_init,
1465 };
1466
1467 static void ss_lx_class_init(ObjectClass *oc, void *data)
1468 {
1469 MachineClass *mc = MACHINE_CLASS(oc);
1470
1471 mc->desc = "Sun4m platform, SPARCstation LX";
1472 mc->init = ss_lx_init;
1473 mc->block_default_type = IF_SCSI;
1474 mc->default_boot_order = "c";
1475 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1476 }
1477
1478 static const TypeInfo ss_lx_type = {
1479 .name = MACHINE_TYPE_NAME("LX"),
1480 .parent = TYPE_MACHINE,
1481 .class_init = ss_lx_class_init,
1482 };
1483
1484 static void ss4_class_init(ObjectClass *oc, void *data)
1485 {
1486 MachineClass *mc = MACHINE_CLASS(oc);
1487
1488 mc->desc = "Sun4m platform, SPARCstation 4";
1489 mc->init = ss4_init;
1490 mc->block_default_type = IF_SCSI;
1491 mc->default_boot_order = "c";
1492 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1493 }
1494
1495 static const TypeInfo ss4_type = {
1496 .name = MACHINE_TYPE_NAME("SS-4"),
1497 .parent = TYPE_MACHINE,
1498 .class_init = ss4_class_init,
1499 };
1500
1501 static void scls_class_init(ObjectClass *oc, void *data)
1502 {
1503 MachineClass *mc = MACHINE_CLASS(oc);
1504
1505 mc->desc = "Sun4m platform, SPARCClassic";
1506 mc->init = scls_init;
1507 mc->block_default_type = IF_SCSI;
1508 mc->default_boot_order = "c";
1509 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1510 }
1511
1512 static const TypeInfo scls_type = {
1513 .name = MACHINE_TYPE_NAME("SPARCClassic"),
1514 .parent = TYPE_MACHINE,
1515 .class_init = scls_class_init,
1516 };
1517
1518 static void sbook_class_init(ObjectClass *oc, void *data)
1519 {
1520 MachineClass *mc = MACHINE_CLASS(oc);
1521
1522 mc->desc = "Sun4m platform, SPARCbook";
1523 mc->init = sbook_init;
1524 mc->block_default_type = IF_SCSI;
1525 mc->default_boot_order = "c";
1526 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1527 }
1528
1529 static const TypeInfo sbook_type = {
1530 .name = MACHINE_TYPE_NAME("SPARCbook"),
1531 .parent = TYPE_MACHINE,
1532 .class_init = sbook_class_init,
1533 };
1534
1535 static void sun4m_register_types(void)
1536 {
1537 type_register_static(&idreg_info);
1538 type_register_static(&afx_info);
1539 type_register_static(&prom_info);
1540 type_register_static(&ram_info);
1541
1542 type_register_static(&ss5_type);
1543 type_register_static(&ss10_type);
1544 type_register_static(&ss600mp_type);
1545 type_register_static(&ss20_type);
1546 type_register_static(&voyager_type);
1547 type_register_static(&ss_lx_type);
1548 type_register_static(&ss4_type);
1549 type_register_static(&scls_type);
1550 type_register_static(&sbook_type);
1551 }
1552
1553 type_init(sun4m_register_types)
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