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Merge remote-tracking branch 'remotes/stsquad/tags/pull-shippable-disable-ppc-080318...
[mirror_qemu.git] / hw / sparc / sun4m.c
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "qemu/osdep.h"
25 #include "qapi/error.h"
26 #include "qemu-common.h"
27 #include "cpu.h"
28 #include "hw/sysbus.h"
29 #include "qemu/error-report.h"
30 #include "qemu/timer.h"
31 #include "hw/sparc/sun4m_iommu.h"
32 #include "hw/timer/m48t59.h"
33 #include "hw/sparc/sparc32_dma.h"
34 #include "hw/block/fdc.h"
35 #include "sysemu/sysemu.h"
36 #include "net/net.h"
37 #include "hw/boards.h"
38 #include "hw/scsi/esp.h"
39 #include "hw/isa/isa.h"
40 #include "hw/nvram/sun_nvram.h"
41 #include "hw/nvram/chrp_nvram.h"
42 #include "hw/nvram/fw_cfg.h"
43 #include "hw/char/escc.h"
44 #include "hw/empty_slot.h"
45 #include "hw/loader.h"
46 #include "elf.h"
47 #include "sysemu/block-backend.h"
48 #include "trace.h"
49 #include "qemu/cutils.h"
50
51 /*
52 * Sun4m architecture was used in the following machines:
53 *
54 * SPARCserver 6xxMP/xx
55 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
56 * SPARCclassic X (4/10)
57 * SPARCstation LX/ZX (4/30)
58 * SPARCstation Voyager
59 * SPARCstation 10/xx, SPARCserver 10/xx
60 * SPARCstation 5, SPARCserver 5
61 * SPARCstation 20/xx, SPARCserver 20
62 * SPARCstation 4
63 *
64 * See for example: http://www.sunhelp.org/faq/sunref1.html
65 */
66
67 #define KERNEL_LOAD_ADDR 0x00004000
68 #define CMDLINE_ADDR 0x007ff000
69 #define INITRD_LOAD_ADDR 0x00800000
70 #define PROM_SIZE_MAX (1024 * 1024)
71 #define PROM_VADDR 0xffd00000
72 #define PROM_FILENAME "openbios-sparc32"
73 #define CFG_ADDR 0xd00000510ULL
74 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
75 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
76 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
77
78 #define MAX_CPUS 16
79 #define MAX_PILS 16
80 #define MAX_VSIMMS 4
81
82 #define ESCC_CLOCK 4915200
83
84 struct sun4m_hwdef {
85 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
86 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
87 hwaddr serial_base, fd_base;
88 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
89 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
90 hwaddr bpp_base, dbri_base, sx_base;
91 struct {
92 hwaddr reg_base, vram_base;
93 } vsimm[MAX_VSIMMS];
94 hwaddr ecc_base;
95 uint64_t max_mem;
96 uint32_t ecc_version;
97 uint32_t iommu_version;
98 uint16_t machine_id;
99 uint8_t nvram_machine_id;
100 };
101
102 void DMA_init(ISABus *bus, int high_page_enable)
103 {
104 }
105
106 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
107 Error **errp)
108 {
109 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
110 }
111
112 static void nvram_init(Nvram *nvram, uint8_t *macaddr,
113 const char *cmdline, const char *boot_devices,
114 ram_addr_t RAM_size, uint32_t kernel_size,
115 int width, int height, int depth,
116 int nvram_machine_id, const char *arch)
117 {
118 unsigned int i;
119 int sysp_end;
120 uint8_t image[0x1ff0];
121 NvramClass *k = NVRAM_GET_CLASS(nvram);
122
123 memset(image, '\0', sizeof(image));
124
125 /* OpenBIOS nvram variables partition */
126 sysp_end = chrp_nvram_create_system_partition(image, 0);
127
128 /* Free space partition */
129 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
130
131 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
132 nvram_machine_id);
133
134 for (i = 0; i < sizeof(image); i++) {
135 (k->write)(nvram, i, image[i]);
136 }
137 }
138
139 void cpu_check_irqs(CPUSPARCState *env)
140 {
141 CPUState *cs;
142
143 /* We should be holding the BQL before we mess with IRQs */
144 g_assert(qemu_mutex_iothread_locked());
145
146 if (env->pil_in && (env->interrupt_index == 0 ||
147 (env->interrupt_index & ~15) == TT_EXTINT)) {
148 unsigned int i;
149
150 for (i = 15; i > 0; i--) {
151 if (env->pil_in & (1 << i)) {
152 int old_interrupt = env->interrupt_index;
153
154 env->interrupt_index = TT_EXTINT | i;
155 if (old_interrupt != env->interrupt_index) {
156 cs = CPU(sparc_env_get_cpu(env));
157 trace_sun4m_cpu_interrupt(i);
158 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
159 }
160 break;
161 }
162 }
163 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
164 cs = CPU(sparc_env_get_cpu(env));
165 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
166 env->interrupt_index = 0;
167 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
168 }
169 }
170
171 static void cpu_kick_irq(SPARCCPU *cpu)
172 {
173 CPUSPARCState *env = &cpu->env;
174 CPUState *cs = CPU(cpu);
175
176 cs->halted = 0;
177 cpu_check_irqs(env);
178 qemu_cpu_kick(cs);
179 }
180
181 static void cpu_set_irq(void *opaque, int irq, int level)
182 {
183 SPARCCPU *cpu = opaque;
184 CPUSPARCState *env = &cpu->env;
185
186 if (level) {
187 trace_sun4m_cpu_set_irq_raise(irq);
188 env->pil_in |= 1 << irq;
189 cpu_kick_irq(cpu);
190 } else {
191 trace_sun4m_cpu_set_irq_lower(irq);
192 env->pil_in &= ~(1 << irq);
193 cpu_check_irqs(env);
194 }
195 }
196
197 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
198 {
199 }
200
201 static void main_cpu_reset(void *opaque)
202 {
203 SPARCCPU *cpu = opaque;
204 CPUState *cs = CPU(cpu);
205
206 cpu_reset(cs);
207 cs->halted = 0;
208 }
209
210 static void secondary_cpu_reset(void *opaque)
211 {
212 SPARCCPU *cpu = opaque;
213 CPUState *cs = CPU(cpu);
214
215 cpu_reset(cs);
216 cs->halted = 1;
217 }
218
219 static void cpu_halt_signal(void *opaque, int irq, int level)
220 {
221 if (level && current_cpu) {
222 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
223 }
224 }
225
226 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
227 {
228 return addr - 0xf0000000ULL;
229 }
230
231 static unsigned long sun4m_load_kernel(const char *kernel_filename,
232 const char *initrd_filename,
233 ram_addr_t RAM_size)
234 {
235 int linux_boot;
236 unsigned int i;
237 long initrd_size, kernel_size;
238 uint8_t *ptr;
239
240 linux_boot = (kernel_filename != NULL);
241
242 kernel_size = 0;
243 if (linux_boot) {
244 int bswap_needed;
245
246 #ifdef BSWAP_NEEDED
247 bswap_needed = 1;
248 #else
249 bswap_needed = 0;
250 #endif
251 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
252 NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
253 if (kernel_size < 0)
254 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
255 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
256 TARGET_PAGE_SIZE);
257 if (kernel_size < 0)
258 kernel_size = load_image_targphys(kernel_filename,
259 KERNEL_LOAD_ADDR,
260 RAM_size - KERNEL_LOAD_ADDR);
261 if (kernel_size < 0) {
262 error_report("could not load kernel '%s'", kernel_filename);
263 exit(1);
264 }
265
266 /* load initrd */
267 initrd_size = 0;
268 if (initrd_filename) {
269 initrd_size = load_image_targphys(initrd_filename,
270 INITRD_LOAD_ADDR,
271 RAM_size - INITRD_LOAD_ADDR);
272 if (initrd_size < 0) {
273 error_report("could not load initial ram disk '%s'",
274 initrd_filename);
275 exit(1);
276 }
277 }
278 if (initrd_size > 0) {
279 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
280 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
281 if (ldl_p(ptr) == 0x48647253) { // HdrS
282 stl_p(ptr + 16, INITRD_LOAD_ADDR);
283 stl_p(ptr + 20, initrd_size);
284 break;
285 }
286 }
287 }
288 }
289 return kernel_size;
290 }
291
292 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
293 {
294 DeviceState *dev;
295 SysBusDevice *s;
296
297 dev = qdev_create(NULL, TYPE_SUN4M_IOMMU);
298 qdev_prop_set_uint32(dev, "version", version);
299 qdev_init_nofail(dev);
300 s = SYS_BUS_DEVICE(dev);
301 sysbus_connect_irq(s, 0, irq);
302 sysbus_mmio_map(s, 0, addr);
303
304 return s;
305 }
306
307 static void *sparc32_dma_init(hwaddr dma_base,
308 hwaddr esp_base, qemu_irq espdma_irq,
309 hwaddr le_base, qemu_irq ledma_irq)
310 {
311 DeviceState *dma;
312 ESPDMADeviceState *espdma;
313 LEDMADeviceState *ledma;
314 SysBusESPState *esp;
315 SysBusPCNetState *lance;
316
317 dma = qdev_create(NULL, TYPE_SPARC32_DMA);
318 qdev_init_nofail(dma);
319 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base);
320
321 espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component(
322 OBJECT(dma), "espdma"));
323 sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq);
324
325 esp = ESP_STATE(object_resolve_path_component(OBJECT(espdma), "esp"));
326 sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base);
327 scsi_bus_legacy_handle_cmdline(&esp->esp.bus);
328
329 ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component(
330 OBJECT(dma), "ledma"));
331 sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq);
332
333 lance = SYSBUS_PCNET(object_resolve_path_component(
334 OBJECT(ledma), "lance"));
335 sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base);
336
337 return dma;
338 }
339
340 static DeviceState *slavio_intctl_init(hwaddr addr,
341 hwaddr addrg,
342 qemu_irq **parent_irq)
343 {
344 DeviceState *dev;
345 SysBusDevice *s;
346 unsigned int i, j;
347
348 dev = qdev_create(NULL, "slavio_intctl");
349 qdev_init_nofail(dev);
350
351 s = SYS_BUS_DEVICE(dev);
352
353 for (i = 0; i < MAX_CPUS; i++) {
354 for (j = 0; j < MAX_PILS; j++) {
355 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
356 }
357 }
358 sysbus_mmio_map(s, 0, addrg);
359 for (i = 0; i < MAX_CPUS; i++) {
360 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
361 }
362
363 return dev;
364 }
365
366 #define SYS_TIMER_OFFSET 0x10000ULL
367 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
368
369 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
370 qemu_irq *cpu_irqs, unsigned int num_cpus)
371 {
372 DeviceState *dev;
373 SysBusDevice *s;
374 unsigned int i;
375
376 dev = qdev_create(NULL, "slavio_timer");
377 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
378 qdev_init_nofail(dev);
379 s = SYS_BUS_DEVICE(dev);
380 sysbus_connect_irq(s, 0, master_irq);
381 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
382
383 for (i = 0; i < MAX_CPUS; i++) {
384 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
385 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
386 }
387 }
388
389 static qemu_irq slavio_system_powerdown;
390
391 static void slavio_powerdown_req(Notifier *n, void *opaque)
392 {
393 qemu_irq_raise(slavio_system_powerdown);
394 }
395
396 static Notifier slavio_system_powerdown_notifier = {
397 .notify = slavio_powerdown_req
398 };
399
400 #define MISC_LEDS 0x01600000
401 #define MISC_CFG 0x01800000
402 #define MISC_DIAG 0x01a00000
403 #define MISC_MDM 0x01b00000
404 #define MISC_SYS 0x01f00000
405
406 static void slavio_misc_init(hwaddr base,
407 hwaddr aux1_base,
408 hwaddr aux2_base, qemu_irq irq,
409 qemu_irq fdc_tc)
410 {
411 DeviceState *dev;
412 SysBusDevice *s;
413
414 dev = qdev_create(NULL, "slavio_misc");
415 qdev_init_nofail(dev);
416 s = SYS_BUS_DEVICE(dev);
417 if (base) {
418 /* 8 bit registers */
419 /* Slavio control */
420 sysbus_mmio_map(s, 0, base + MISC_CFG);
421 /* Diagnostics */
422 sysbus_mmio_map(s, 1, base + MISC_DIAG);
423 /* Modem control */
424 sysbus_mmio_map(s, 2, base + MISC_MDM);
425 /* 16 bit registers */
426 /* ss600mp diag LEDs */
427 sysbus_mmio_map(s, 3, base + MISC_LEDS);
428 /* 32 bit registers */
429 /* System control */
430 sysbus_mmio_map(s, 4, base + MISC_SYS);
431 }
432 if (aux1_base) {
433 /* AUX 1 (Misc System Functions) */
434 sysbus_mmio_map(s, 5, aux1_base);
435 }
436 if (aux2_base) {
437 /* AUX 2 (Software Powerdown Control) */
438 sysbus_mmio_map(s, 6, aux2_base);
439 }
440 sysbus_connect_irq(s, 0, irq);
441 sysbus_connect_irq(s, 1, fdc_tc);
442 slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
443 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
444 }
445
446 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
447 {
448 DeviceState *dev;
449 SysBusDevice *s;
450
451 dev = qdev_create(NULL, "eccmemctl");
452 qdev_prop_set_uint32(dev, "version", version);
453 qdev_init_nofail(dev);
454 s = SYS_BUS_DEVICE(dev);
455 sysbus_connect_irq(s, 0, irq);
456 sysbus_mmio_map(s, 0, base);
457 if (version == 0) { // SS-600MP only
458 sysbus_mmio_map(s, 1, base + 0x1000);
459 }
460 }
461
462 static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
463 {
464 DeviceState *dev;
465 SysBusDevice *s;
466
467 dev = qdev_create(NULL, "apc");
468 qdev_init_nofail(dev);
469 s = SYS_BUS_DEVICE(dev);
470 /* Power management (APC) XXX: not a Slavio device */
471 sysbus_mmio_map(s, 0, power_base);
472 sysbus_connect_irq(s, 0, cpu_halt);
473 }
474
475 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
476 int height, int depth)
477 {
478 DeviceState *dev;
479 SysBusDevice *s;
480
481 dev = qdev_create(NULL, "SUNW,tcx");
482 qdev_prop_set_uint32(dev, "vram_size", vram_size);
483 qdev_prop_set_uint16(dev, "width", width);
484 qdev_prop_set_uint16(dev, "height", height);
485 qdev_prop_set_uint16(dev, "depth", depth);
486 qdev_init_nofail(dev);
487 s = SYS_BUS_DEVICE(dev);
488
489 /* 10/ROM : FCode ROM */
490 sysbus_mmio_map(s, 0, addr);
491 /* 2/STIP : Stipple */
492 sysbus_mmio_map(s, 1, addr + 0x04000000ULL);
493 /* 3/BLIT : Blitter */
494 sysbus_mmio_map(s, 2, addr + 0x06000000ULL);
495 /* 5/RSTIP : Raw Stipple */
496 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL);
497 /* 6/RBLIT : Raw Blitter */
498 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL);
499 /* 7/TEC : Transform Engine */
500 sysbus_mmio_map(s, 5, addr + 0x00700000ULL);
501 /* 8/CMAP : DAC */
502 sysbus_mmio_map(s, 6, addr + 0x00200000ULL);
503 /* 9/THC : */
504 if (depth == 8) {
505 sysbus_mmio_map(s, 7, addr + 0x00300000ULL);
506 } else {
507 sysbus_mmio_map(s, 7, addr + 0x00301000ULL);
508 }
509 /* 11/DHC : */
510 sysbus_mmio_map(s, 8, addr + 0x00240000ULL);
511 /* 12/ALT : */
512 sysbus_mmio_map(s, 9, addr + 0x00280000ULL);
513 /* 0/DFB8 : 8-bit plane */
514 sysbus_mmio_map(s, 10, addr + 0x00800000ULL);
515 /* 1/DFB24 : 24bit plane */
516 sysbus_mmio_map(s, 11, addr + 0x02000000ULL);
517 /* 4/RDFB32: Raw framebuffer. Control plane */
518 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL);
519 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
520 if (depth == 8) {
521 sysbus_mmio_map(s, 13, addr + 0x00301000ULL);
522 }
523
524 sysbus_connect_irq(s, 0, irq);
525 }
526
527 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
528 int height, int depth)
529 {
530 DeviceState *dev;
531 SysBusDevice *s;
532
533 dev = qdev_create(NULL, "cgthree");
534 qdev_prop_set_uint32(dev, "vram-size", vram_size);
535 qdev_prop_set_uint16(dev, "width", width);
536 qdev_prop_set_uint16(dev, "height", height);
537 qdev_prop_set_uint16(dev, "depth", depth);
538 qdev_init_nofail(dev);
539 s = SYS_BUS_DEVICE(dev);
540
541 /* FCode ROM */
542 sysbus_mmio_map(s, 0, addr);
543 /* DAC */
544 sysbus_mmio_map(s, 1, addr + 0x400000ULL);
545 /* 8-bit plane */
546 sysbus_mmio_map(s, 2, addr + 0x800000ULL);
547
548 sysbus_connect_irq(s, 0, irq);
549 }
550
551 /* NCR89C100/MACIO Internal ID register */
552
553 #define TYPE_MACIO_ID_REGISTER "macio_idreg"
554
555 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
556
557 static void idreg_init(hwaddr addr)
558 {
559 DeviceState *dev;
560 SysBusDevice *s;
561
562 dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER);
563 qdev_init_nofail(dev);
564 s = SYS_BUS_DEVICE(dev);
565
566 sysbus_mmio_map(s, 0, addr);
567 cpu_physical_memory_write_rom(&address_space_memory,
568 addr, idreg_data, sizeof(idreg_data));
569 }
570
571 #define MACIO_ID_REGISTER(obj) \
572 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER)
573
574 typedef struct IDRegState {
575 SysBusDevice parent_obj;
576
577 MemoryRegion mem;
578 } IDRegState;
579
580 static void idreg_init1(Object *obj)
581 {
582 IDRegState *s = MACIO_ID_REGISTER(obj);
583 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
584
585 memory_region_init_ram_nomigrate(&s->mem, obj,
586 "sun4m.idreg", sizeof(idreg_data), &error_fatal);
587 vmstate_register_ram_global(&s->mem);
588 memory_region_set_readonly(&s->mem, true);
589 sysbus_init_mmio(dev, &s->mem);
590 }
591
592 static const TypeInfo idreg_info = {
593 .name = TYPE_MACIO_ID_REGISTER,
594 .parent = TYPE_SYS_BUS_DEVICE,
595 .instance_size = sizeof(IDRegState),
596 .instance_init = idreg_init1,
597 };
598
599 #define TYPE_TCX_AFX "tcx_afx"
600 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX)
601
602 typedef struct AFXState {
603 SysBusDevice parent_obj;
604
605 MemoryRegion mem;
606 } AFXState;
607
608 /* SS-5 TCX AFX register */
609 static void afx_init(hwaddr addr)
610 {
611 DeviceState *dev;
612 SysBusDevice *s;
613
614 dev = qdev_create(NULL, TYPE_TCX_AFX);
615 qdev_init_nofail(dev);
616 s = SYS_BUS_DEVICE(dev);
617
618 sysbus_mmio_map(s, 0, addr);
619 }
620
621 static void afx_init1(Object *obj)
622 {
623 AFXState *s = TCX_AFX(obj);
624 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
625
626 memory_region_init_ram_nomigrate(&s->mem, obj, "sun4m.afx", 4, &error_fatal);
627 vmstate_register_ram_global(&s->mem);
628 sysbus_init_mmio(dev, &s->mem);
629 }
630
631 static const TypeInfo afx_info = {
632 .name = TYPE_TCX_AFX,
633 .parent = TYPE_SYS_BUS_DEVICE,
634 .instance_size = sizeof(AFXState),
635 .instance_init = afx_init1,
636 };
637
638 #define TYPE_OPENPROM "openprom"
639 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
640
641 typedef struct PROMState {
642 SysBusDevice parent_obj;
643
644 MemoryRegion prom;
645 } PROMState;
646
647 /* Boot PROM (OpenBIOS) */
648 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
649 {
650 hwaddr *base_addr = (hwaddr *)opaque;
651 return addr + *base_addr - PROM_VADDR;
652 }
653
654 static void prom_init(hwaddr addr, const char *bios_name)
655 {
656 DeviceState *dev;
657 SysBusDevice *s;
658 char *filename;
659 int ret;
660
661 dev = qdev_create(NULL, TYPE_OPENPROM);
662 qdev_init_nofail(dev);
663 s = SYS_BUS_DEVICE(dev);
664
665 sysbus_mmio_map(s, 0, addr);
666
667 /* load boot prom */
668 if (bios_name == NULL) {
669 bios_name = PROM_FILENAME;
670 }
671 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
672 if (filename) {
673 ret = load_elf(filename, translate_prom_address, &addr, NULL,
674 NULL, NULL, 1, EM_SPARC, 0, 0);
675 if (ret < 0 || ret > PROM_SIZE_MAX) {
676 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
677 }
678 g_free(filename);
679 } else {
680 ret = -1;
681 }
682 if (ret < 0 || ret > PROM_SIZE_MAX) {
683 error_report("could not load prom '%s'", bios_name);
684 exit(1);
685 }
686 }
687
688 static void prom_init1(Object *obj)
689 {
690 PROMState *s = OPENPROM(obj);
691 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
692
693 memory_region_init_ram_nomigrate(&s->prom, obj, "sun4m.prom", PROM_SIZE_MAX,
694 &error_fatal);
695 vmstate_register_ram_global(&s->prom);
696 memory_region_set_readonly(&s->prom, true);
697 sysbus_init_mmio(dev, &s->prom);
698 }
699
700 static Property prom_properties[] = {
701 {/* end of property list */},
702 };
703
704 static void prom_class_init(ObjectClass *klass, void *data)
705 {
706 DeviceClass *dc = DEVICE_CLASS(klass);
707
708 dc->props = prom_properties;
709 }
710
711 static const TypeInfo prom_info = {
712 .name = TYPE_OPENPROM,
713 .parent = TYPE_SYS_BUS_DEVICE,
714 .instance_size = sizeof(PROMState),
715 .class_init = prom_class_init,
716 .instance_init = prom_init1,
717 };
718
719 #define TYPE_SUN4M_MEMORY "memory"
720 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY)
721
722 typedef struct RamDevice {
723 SysBusDevice parent_obj;
724
725 MemoryRegion ram;
726 uint64_t size;
727 } RamDevice;
728
729 /* System RAM */
730 static void ram_realize(DeviceState *dev, Error **errp)
731 {
732 RamDevice *d = SUN4M_RAM(dev);
733 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
734
735 memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram",
736 d->size);
737 sysbus_init_mmio(sbd, &d->ram);
738 }
739
740 static void ram_init(hwaddr addr, ram_addr_t RAM_size,
741 uint64_t max_mem)
742 {
743 DeviceState *dev;
744 SysBusDevice *s;
745 RamDevice *d;
746
747 /* allocate RAM */
748 if ((uint64_t)RAM_size > max_mem) {
749 error_report("Too much memory for this machine: %d, maximum %d",
750 (unsigned int)(RAM_size / (1024 * 1024)),
751 (unsigned int)(max_mem / (1024 * 1024)));
752 exit(1);
753 }
754 dev = qdev_create(NULL, "memory");
755 s = SYS_BUS_DEVICE(dev);
756
757 d = SUN4M_RAM(dev);
758 d->size = RAM_size;
759 qdev_init_nofail(dev);
760
761 sysbus_mmio_map(s, 0, addr);
762 }
763
764 static Property ram_properties[] = {
765 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
766 DEFINE_PROP_END_OF_LIST(),
767 };
768
769 static void ram_class_init(ObjectClass *klass, void *data)
770 {
771 DeviceClass *dc = DEVICE_CLASS(klass);
772
773 dc->realize = ram_realize;
774 dc->props = ram_properties;
775 }
776
777 static const TypeInfo ram_info = {
778 .name = TYPE_SUN4M_MEMORY,
779 .parent = TYPE_SYS_BUS_DEVICE,
780 .instance_size = sizeof(RamDevice),
781 .class_init = ram_class_init,
782 };
783
784 static void cpu_devinit(const char *cpu_type, unsigned int id,
785 uint64_t prom_addr, qemu_irq **cpu_irqs)
786 {
787 CPUState *cs;
788 SPARCCPU *cpu;
789 CPUSPARCState *env;
790
791 cpu = SPARC_CPU(cpu_create(cpu_type));
792 env = &cpu->env;
793
794 cpu_sparc_set_id(env, id);
795 if (id == 0) {
796 qemu_register_reset(main_cpu_reset, cpu);
797 } else {
798 qemu_register_reset(secondary_cpu_reset, cpu);
799 cs = CPU(cpu);
800 cs->halted = 1;
801 }
802 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
803 env->prom_addr = prom_addr;
804 }
805
806 static void dummy_fdc_tc(void *opaque, int irq, int level)
807 {
808 }
809
810 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
811 MachineState *machine)
812 {
813 DeviceState *slavio_intctl;
814 unsigned int i;
815 void *nvram;
816 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS];
817 qemu_irq fdc_tc;
818 unsigned long kernel_size;
819 DriveInfo *fd[MAX_FD];
820 FWCfgState *fw_cfg;
821 unsigned int num_vsimms;
822 DeviceState *dev;
823 SysBusDevice *s;
824
825 /* init CPUs */
826 for(i = 0; i < smp_cpus; i++) {
827 cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]);
828 }
829
830 for (i = smp_cpus; i < MAX_CPUS; i++)
831 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
832
833
834 /* set up devices */
835 ram_init(0, machine->ram_size, hwdef->max_mem);
836 /* models without ECC don't trap when missing ram is accessed */
837 if (!hwdef->ecc_base) {
838 empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size);
839 }
840
841 prom_init(hwdef->slavio_base, bios_name);
842
843 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
844 hwdef->intctl_base + 0x10000ULL,
845 cpu_irqs);
846
847 for (i = 0; i < 32; i++) {
848 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
849 }
850 for (i = 0; i < MAX_CPUS; i++) {
851 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
852 }
853
854 if (hwdef->idreg_base) {
855 idreg_init(hwdef->idreg_base);
856 }
857
858 if (hwdef->afx_base) {
859 afx_init(hwdef->afx_base);
860 }
861
862 iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]);
863
864 if (hwdef->iommu_pad_base) {
865 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
866 Software shouldn't use aliased addresses, neither should it crash
867 when does. Using empty_slot instead of aliasing can help with
868 debugging such accesses */
869 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
870 }
871
872 sparc32_dma_init(hwdef->dma_base,
873 hwdef->esp_base, slavio_irq[18],
874 hwdef->le_base, slavio_irq[16]);
875
876 if (graphic_depth != 8 && graphic_depth != 24) {
877 error_report("Unsupported depth: %d", graphic_depth);
878 exit (1);
879 }
880 num_vsimms = 0;
881 if (num_vsimms == 0) {
882 if (vga_interface_type == VGA_CG3) {
883 if (graphic_depth != 8) {
884 error_report("Unsupported depth: %d", graphic_depth);
885 exit(1);
886 }
887
888 if (!(graphic_width == 1024 && graphic_height == 768) &&
889 !(graphic_width == 1152 && graphic_height == 900)) {
890 error_report("Unsupported resolution: %d x %d", graphic_width,
891 graphic_height);
892 exit(1);
893 }
894
895 /* sbus irq 5 */
896 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
897 graphic_width, graphic_height, graphic_depth);
898 } else {
899 /* If no display specified, default to TCX */
900 if (graphic_depth != 8 && graphic_depth != 24) {
901 error_report("Unsupported depth: %d", graphic_depth);
902 exit(1);
903 }
904
905 if (!(graphic_width == 1024 && graphic_height == 768)) {
906 error_report("Unsupported resolution: %d x %d",
907 graphic_width, graphic_height);
908 exit(1);
909 }
910
911 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
912 graphic_width, graphic_height, graphic_depth);
913 }
914 }
915
916 for (i = num_vsimms; i < MAX_VSIMMS; i++) {
917 /* vsimm registers probed by OBP */
918 if (hwdef->vsimm[i].reg_base) {
919 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
920 }
921 }
922
923 if (hwdef->sx_base) {
924 empty_slot_init(hwdef->sx_base, 0x2000);
925 }
926
927 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8);
928
929 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
930
931 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
932 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
933 dev = qdev_create(NULL, TYPE_ESCC);
934 qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics);
935 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
936 qdev_prop_set_uint32(dev, "it_shift", 1);
937 qdev_prop_set_chr(dev, "chrB", NULL);
938 qdev_prop_set_chr(dev, "chrA", NULL);
939 qdev_prop_set_uint32(dev, "chnBtype", escc_mouse);
940 qdev_prop_set_uint32(dev, "chnAtype", escc_kbd);
941 qdev_init_nofail(dev);
942 s = SYS_BUS_DEVICE(dev);
943 sysbus_connect_irq(s, 0, slavio_irq[14]);
944 sysbus_connect_irq(s, 1, slavio_irq[14]);
945 sysbus_mmio_map(s, 0, hwdef->ms_kb_base);
946
947 dev = qdev_create(NULL, TYPE_ESCC);
948 qdev_prop_set_uint32(dev, "disabled", 0);
949 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
950 qdev_prop_set_uint32(dev, "it_shift", 1);
951 qdev_prop_set_chr(dev, "chrB", serial_hds[1]);
952 qdev_prop_set_chr(dev, "chrA", serial_hds[0]);
953 qdev_prop_set_uint32(dev, "chnBtype", escc_serial);
954 qdev_prop_set_uint32(dev, "chnAtype", escc_serial);
955 qdev_init_nofail(dev);
956
957 s = SYS_BUS_DEVICE(dev);
958 sysbus_connect_irq(s, 0, slavio_irq[15]);
959 sysbus_connect_irq(s, 1, slavio_irq[15]);
960 sysbus_mmio_map(s, 0, hwdef->serial_base);
961
962 if (hwdef->apc_base) {
963 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0));
964 }
965
966 if (hwdef->fd_base) {
967 /* there is zero or one floppy drive */
968 memset(fd, 0, sizeof(fd));
969 fd[0] = drive_get(IF_FLOPPY, 0, 0);
970 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
971 &fdc_tc);
972 } else {
973 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0);
974 }
975
976 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
977 slavio_irq[30], fdc_tc);
978
979 if (hwdef->cs_base) {
980 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
981 slavio_irq[5]);
982 }
983
984 if (hwdef->dbri_base) {
985 /* ISDN chip with attached CS4215 audio codec */
986 /* prom space */
987 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
988 /* reg space */
989 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
990 }
991
992 if (hwdef->bpp_base) {
993 /* parallel port */
994 empty_slot_init(hwdef->bpp_base, 0x20);
995 }
996
997 kernel_size = sun4m_load_kernel(machine->kernel_filename,
998 machine->initrd_filename,
999 machine->ram_size);
1000
1001 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline,
1002 machine->boot_order, machine->ram_size, kernel_size,
1003 graphic_width, graphic_height, graphic_depth,
1004 hwdef->nvram_machine_id, "Sun4m");
1005
1006 if (hwdef->ecc_base)
1007 ecc_init(hwdef->ecc_base, slavio_irq[28],
1008 hwdef->ecc_version);
1009
1010 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
1011 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
1012 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1013 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1014 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1015 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1016 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width);
1017 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height);
1018 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1019 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1020 if (machine->kernel_cmdline) {
1021 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1022 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
1023 machine->kernel_cmdline);
1024 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
1025 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1026 strlen(machine->kernel_cmdline) + 1);
1027 } else {
1028 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1029 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1030 }
1031 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1032 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1033 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
1034 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1035 }
1036
1037 enum {
1038 ss5_id = 32,
1039 vger_id,
1040 lx_id,
1041 ss4_id,
1042 scls_id,
1043 sbook_id,
1044 ss10_id = 64,
1045 ss20_id,
1046 ss600mp_id,
1047 };
1048
1049 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1050 /* SS-5 */
1051 {
1052 .iommu_base = 0x10000000,
1053 .iommu_pad_base = 0x10004000,
1054 .iommu_pad_len = 0x0fffb000,
1055 .tcx_base = 0x50000000,
1056 .cs_base = 0x6c000000,
1057 .slavio_base = 0x70000000,
1058 .ms_kb_base = 0x71000000,
1059 .serial_base = 0x71100000,
1060 .nvram_base = 0x71200000,
1061 .fd_base = 0x71400000,
1062 .counter_base = 0x71d00000,
1063 .intctl_base = 0x71e00000,
1064 .idreg_base = 0x78000000,
1065 .dma_base = 0x78400000,
1066 .esp_base = 0x78800000,
1067 .le_base = 0x78c00000,
1068 .apc_base = 0x6a000000,
1069 .afx_base = 0x6e000000,
1070 .aux1_base = 0x71900000,
1071 .aux2_base = 0x71910000,
1072 .nvram_machine_id = 0x80,
1073 .machine_id = ss5_id,
1074 .iommu_version = 0x05000000,
1075 .max_mem = 0x10000000,
1076 },
1077 /* SS-10 */
1078 {
1079 .iommu_base = 0xfe0000000ULL,
1080 .tcx_base = 0xe20000000ULL,
1081 .slavio_base = 0xff0000000ULL,
1082 .ms_kb_base = 0xff1000000ULL,
1083 .serial_base = 0xff1100000ULL,
1084 .nvram_base = 0xff1200000ULL,
1085 .fd_base = 0xff1700000ULL,
1086 .counter_base = 0xff1300000ULL,
1087 .intctl_base = 0xff1400000ULL,
1088 .idreg_base = 0xef0000000ULL,
1089 .dma_base = 0xef0400000ULL,
1090 .esp_base = 0xef0800000ULL,
1091 .le_base = 0xef0c00000ULL,
1092 .apc_base = 0xefa000000ULL, // XXX should not exist
1093 .aux1_base = 0xff1800000ULL,
1094 .aux2_base = 0xff1a01000ULL,
1095 .ecc_base = 0xf00000000ULL,
1096 .ecc_version = 0x10000000, // version 0, implementation 1
1097 .nvram_machine_id = 0x72,
1098 .machine_id = ss10_id,
1099 .iommu_version = 0x03000000,
1100 .max_mem = 0xf00000000ULL,
1101 },
1102 /* SS-600MP */
1103 {
1104 .iommu_base = 0xfe0000000ULL,
1105 .tcx_base = 0xe20000000ULL,
1106 .slavio_base = 0xff0000000ULL,
1107 .ms_kb_base = 0xff1000000ULL,
1108 .serial_base = 0xff1100000ULL,
1109 .nvram_base = 0xff1200000ULL,
1110 .counter_base = 0xff1300000ULL,
1111 .intctl_base = 0xff1400000ULL,
1112 .dma_base = 0xef0081000ULL,
1113 .esp_base = 0xef0080000ULL,
1114 .le_base = 0xef0060000ULL,
1115 .apc_base = 0xefa000000ULL, // XXX should not exist
1116 .aux1_base = 0xff1800000ULL,
1117 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1118 .ecc_base = 0xf00000000ULL,
1119 .ecc_version = 0x00000000, // version 0, implementation 0
1120 .nvram_machine_id = 0x71,
1121 .machine_id = ss600mp_id,
1122 .iommu_version = 0x01000000,
1123 .max_mem = 0xf00000000ULL,
1124 },
1125 /* SS-20 */
1126 {
1127 .iommu_base = 0xfe0000000ULL,
1128 .tcx_base = 0xe20000000ULL,
1129 .slavio_base = 0xff0000000ULL,
1130 .ms_kb_base = 0xff1000000ULL,
1131 .serial_base = 0xff1100000ULL,
1132 .nvram_base = 0xff1200000ULL,
1133 .fd_base = 0xff1700000ULL,
1134 .counter_base = 0xff1300000ULL,
1135 .intctl_base = 0xff1400000ULL,
1136 .idreg_base = 0xef0000000ULL,
1137 .dma_base = 0xef0400000ULL,
1138 .esp_base = 0xef0800000ULL,
1139 .le_base = 0xef0c00000ULL,
1140 .bpp_base = 0xef4800000ULL,
1141 .apc_base = 0xefa000000ULL, // XXX should not exist
1142 .aux1_base = 0xff1800000ULL,
1143 .aux2_base = 0xff1a01000ULL,
1144 .dbri_base = 0xee0000000ULL,
1145 .sx_base = 0xf80000000ULL,
1146 .vsimm = {
1147 {
1148 .reg_base = 0x9c000000ULL,
1149 .vram_base = 0xfc000000ULL
1150 }, {
1151 .reg_base = 0x90000000ULL,
1152 .vram_base = 0xf0000000ULL
1153 }, {
1154 .reg_base = 0x94000000ULL
1155 }, {
1156 .reg_base = 0x98000000ULL
1157 }
1158 },
1159 .ecc_base = 0xf00000000ULL,
1160 .ecc_version = 0x20000000, // version 0, implementation 2
1161 .nvram_machine_id = 0x72,
1162 .machine_id = ss20_id,
1163 .iommu_version = 0x13000000,
1164 .max_mem = 0xf00000000ULL,
1165 },
1166 /* Voyager */
1167 {
1168 .iommu_base = 0x10000000,
1169 .tcx_base = 0x50000000,
1170 .slavio_base = 0x70000000,
1171 .ms_kb_base = 0x71000000,
1172 .serial_base = 0x71100000,
1173 .nvram_base = 0x71200000,
1174 .fd_base = 0x71400000,
1175 .counter_base = 0x71d00000,
1176 .intctl_base = 0x71e00000,
1177 .idreg_base = 0x78000000,
1178 .dma_base = 0x78400000,
1179 .esp_base = 0x78800000,
1180 .le_base = 0x78c00000,
1181 .apc_base = 0x71300000, // pmc
1182 .aux1_base = 0x71900000,
1183 .aux2_base = 0x71910000,
1184 .nvram_machine_id = 0x80,
1185 .machine_id = vger_id,
1186 .iommu_version = 0x05000000,
1187 .max_mem = 0x10000000,
1188 },
1189 /* LX */
1190 {
1191 .iommu_base = 0x10000000,
1192 .iommu_pad_base = 0x10004000,
1193 .iommu_pad_len = 0x0fffb000,
1194 .tcx_base = 0x50000000,
1195 .slavio_base = 0x70000000,
1196 .ms_kb_base = 0x71000000,
1197 .serial_base = 0x71100000,
1198 .nvram_base = 0x71200000,
1199 .fd_base = 0x71400000,
1200 .counter_base = 0x71d00000,
1201 .intctl_base = 0x71e00000,
1202 .idreg_base = 0x78000000,
1203 .dma_base = 0x78400000,
1204 .esp_base = 0x78800000,
1205 .le_base = 0x78c00000,
1206 .aux1_base = 0x71900000,
1207 .aux2_base = 0x71910000,
1208 .nvram_machine_id = 0x80,
1209 .machine_id = lx_id,
1210 .iommu_version = 0x04000000,
1211 .max_mem = 0x10000000,
1212 },
1213 /* SS-4 */
1214 {
1215 .iommu_base = 0x10000000,
1216 .tcx_base = 0x50000000,
1217 .cs_base = 0x6c000000,
1218 .slavio_base = 0x70000000,
1219 .ms_kb_base = 0x71000000,
1220 .serial_base = 0x71100000,
1221 .nvram_base = 0x71200000,
1222 .fd_base = 0x71400000,
1223 .counter_base = 0x71d00000,
1224 .intctl_base = 0x71e00000,
1225 .idreg_base = 0x78000000,
1226 .dma_base = 0x78400000,
1227 .esp_base = 0x78800000,
1228 .le_base = 0x78c00000,
1229 .apc_base = 0x6a000000,
1230 .aux1_base = 0x71900000,
1231 .aux2_base = 0x71910000,
1232 .nvram_machine_id = 0x80,
1233 .machine_id = ss4_id,
1234 .iommu_version = 0x05000000,
1235 .max_mem = 0x10000000,
1236 },
1237 /* SPARCClassic */
1238 {
1239 .iommu_base = 0x10000000,
1240 .tcx_base = 0x50000000,
1241 .slavio_base = 0x70000000,
1242 .ms_kb_base = 0x71000000,
1243 .serial_base = 0x71100000,
1244 .nvram_base = 0x71200000,
1245 .fd_base = 0x71400000,
1246 .counter_base = 0x71d00000,
1247 .intctl_base = 0x71e00000,
1248 .idreg_base = 0x78000000,
1249 .dma_base = 0x78400000,
1250 .esp_base = 0x78800000,
1251 .le_base = 0x78c00000,
1252 .apc_base = 0x6a000000,
1253 .aux1_base = 0x71900000,
1254 .aux2_base = 0x71910000,
1255 .nvram_machine_id = 0x80,
1256 .machine_id = scls_id,
1257 .iommu_version = 0x05000000,
1258 .max_mem = 0x10000000,
1259 },
1260 /* SPARCbook */
1261 {
1262 .iommu_base = 0x10000000,
1263 .tcx_base = 0x50000000, // XXX
1264 .slavio_base = 0x70000000,
1265 .ms_kb_base = 0x71000000,
1266 .serial_base = 0x71100000,
1267 .nvram_base = 0x71200000,
1268 .fd_base = 0x71400000,
1269 .counter_base = 0x71d00000,
1270 .intctl_base = 0x71e00000,
1271 .idreg_base = 0x78000000,
1272 .dma_base = 0x78400000,
1273 .esp_base = 0x78800000,
1274 .le_base = 0x78c00000,
1275 .apc_base = 0x6a000000,
1276 .aux1_base = 0x71900000,
1277 .aux2_base = 0x71910000,
1278 .nvram_machine_id = 0x80,
1279 .machine_id = sbook_id,
1280 .iommu_version = 0x05000000,
1281 .max_mem = 0x10000000,
1282 },
1283 };
1284
1285 /* SPARCstation 5 hardware initialisation */
1286 static void ss5_init(MachineState *machine)
1287 {
1288 sun4m_hw_init(&sun4m_hwdefs[0], machine);
1289 }
1290
1291 /* SPARCstation 10 hardware initialisation */
1292 static void ss10_init(MachineState *machine)
1293 {
1294 sun4m_hw_init(&sun4m_hwdefs[1], machine);
1295 }
1296
1297 /* SPARCserver 600MP hardware initialisation */
1298 static void ss600mp_init(MachineState *machine)
1299 {
1300 sun4m_hw_init(&sun4m_hwdefs[2], machine);
1301 }
1302
1303 /* SPARCstation 20 hardware initialisation */
1304 static void ss20_init(MachineState *machine)
1305 {
1306 sun4m_hw_init(&sun4m_hwdefs[3], machine);
1307 }
1308
1309 /* SPARCstation Voyager hardware initialisation */
1310 static void vger_init(MachineState *machine)
1311 {
1312 sun4m_hw_init(&sun4m_hwdefs[4], machine);
1313 }
1314
1315 /* SPARCstation LX hardware initialisation */
1316 static void ss_lx_init(MachineState *machine)
1317 {
1318 sun4m_hw_init(&sun4m_hwdefs[5], machine);
1319 }
1320
1321 /* SPARCstation 4 hardware initialisation */
1322 static void ss4_init(MachineState *machine)
1323 {
1324 sun4m_hw_init(&sun4m_hwdefs[6], machine);
1325 }
1326
1327 /* SPARCClassic hardware initialisation */
1328 static void scls_init(MachineState *machine)
1329 {
1330 sun4m_hw_init(&sun4m_hwdefs[7], machine);
1331 }
1332
1333 /* SPARCbook hardware initialisation */
1334 static void sbook_init(MachineState *machine)
1335 {
1336 sun4m_hw_init(&sun4m_hwdefs[8], machine);
1337 }
1338
1339 static void ss5_class_init(ObjectClass *oc, void *data)
1340 {
1341 MachineClass *mc = MACHINE_CLASS(oc);
1342
1343 mc->desc = "Sun4m platform, SPARCstation 5";
1344 mc->init = ss5_init;
1345 mc->block_default_type = IF_SCSI;
1346 mc->is_default = 1;
1347 mc->default_boot_order = "c";
1348 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1349 }
1350
1351 static const TypeInfo ss5_type = {
1352 .name = MACHINE_TYPE_NAME("SS-5"),
1353 .parent = TYPE_MACHINE,
1354 .class_init = ss5_class_init,
1355 };
1356
1357 static void ss10_class_init(ObjectClass *oc, void *data)
1358 {
1359 MachineClass *mc = MACHINE_CLASS(oc);
1360
1361 mc->desc = "Sun4m platform, SPARCstation 10";
1362 mc->init = ss10_init;
1363 mc->block_default_type = IF_SCSI;
1364 mc->max_cpus = 4;
1365 mc->default_boot_order = "c";
1366 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1367 }
1368
1369 static const TypeInfo ss10_type = {
1370 .name = MACHINE_TYPE_NAME("SS-10"),
1371 .parent = TYPE_MACHINE,
1372 .class_init = ss10_class_init,
1373 };
1374
1375 static void ss600mp_class_init(ObjectClass *oc, void *data)
1376 {
1377 MachineClass *mc = MACHINE_CLASS(oc);
1378
1379 mc->desc = "Sun4m platform, SPARCserver 600MP";
1380 mc->init = ss600mp_init;
1381 mc->block_default_type = IF_SCSI;
1382 mc->max_cpus = 4;
1383 mc->default_boot_order = "c";
1384 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1385 }
1386
1387 static const TypeInfo ss600mp_type = {
1388 .name = MACHINE_TYPE_NAME("SS-600MP"),
1389 .parent = TYPE_MACHINE,
1390 .class_init = ss600mp_class_init,
1391 };
1392
1393 static void ss20_class_init(ObjectClass *oc, void *data)
1394 {
1395 MachineClass *mc = MACHINE_CLASS(oc);
1396
1397 mc->desc = "Sun4m platform, SPARCstation 20";
1398 mc->init = ss20_init;
1399 mc->block_default_type = IF_SCSI;
1400 mc->max_cpus = 4;
1401 mc->default_boot_order = "c";
1402 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1403 }
1404
1405 static const TypeInfo ss20_type = {
1406 .name = MACHINE_TYPE_NAME("SS-20"),
1407 .parent = TYPE_MACHINE,
1408 .class_init = ss20_class_init,
1409 };
1410
1411 static void voyager_class_init(ObjectClass *oc, void *data)
1412 {
1413 MachineClass *mc = MACHINE_CLASS(oc);
1414
1415 mc->desc = "Sun4m platform, SPARCstation Voyager";
1416 mc->init = vger_init;
1417 mc->block_default_type = IF_SCSI;
1418 mc->default_boot_order = "c";
1419 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1420 }
1421
1422 static const TypeInfo voyager_type = {
1423 .name = MACHINE_TYPE_NAME("Voyager"),
1424 .parent = TYPE_MACHINE,
1425 .class_init = voyager_class_init,
1426 };
1427
1428 static void ss_lx_class_init(ObjectClass *oc, void *data)
1429 {
1430 MachineClass *mc = MACHINE_CLASS(oc);
1431
1432 mc->desc = "Sun4m platform, SPARCstation LX";
1433 mc->init = ss_lx_init;
1434 mc->block_default_type = IF_SCSI;
1435 mc->default_boot_order = "c";
1436 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1437 }
1438
1439 static const TypeInfo ss_lx_type = {
1440 .name = MACHINE_TYPE_NAME("LX"),
1441 .parent = TYPE_MACHINE,
1442 .class_init = ss_lx_class_init,
1443 };
1444
1445 static void ss4_class_init(ObjectClass *oc, void *data)
1446 {
1447 MachineClass *mc = MACHINE_CLASS(oc);
1448
1449 mc->desc = "Sun4m platform, SPARCstation 4";
1450 mc->init = ss4_init;
1451 mc->block_default_type = IF_SCSI;
1452 mc->default_boot_order = "c";
1453 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1454 }
1455
1456 static const TypeInfo ss4_type = {
1457 .name = MACHINE_TYPE_NAME("SS-4"),
1458 .parent = TYPE_MACHINE,
1459 .class_init = ss4_class_init,
1460 };
1461
1462 static void scls_class_init(ObjectClass *oc, void *data)
1463 {
1464 MachineClass *mc = MACHINE_CLASS(oc);
1465
1466 mc->desc = "Sun4m platform, SPARCClassic";
1467 mc->init = scls_init;
1468 mc->block_default_type = IF_SCSI;
1469 mc->default_boot_order = "c";
1470 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1471 }
1472
1473 static const TypeInfo scls_type = {
1474 .name = MACHINE_TYPE_NAME("SPARCClassic"),
1475 .parent = TYPE_MACHINE,
1476 .class_init = scls_class_init,
1477 };
1478
1479 static void sbook_class_init(ObjectClass *oc, void *data)
1480 {
1481 MachineClass *mc = MACHINE_CLASS(oc);
1482
1483 mc->desc = "Sun4m platform, SPARCbook";
1484 mc->init = sbook_init;
1485 mc->block_default_type = IF_SCSI;
1486 mc->default_boot_order = "c";
1487 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1488 }
1489
1490 static const TypeInfo sbook_type = {
1491 .name = MACHINE_TYPE_NAME("SPARCbook"),
1492 .parent = TYPE_MACHINE,
1493 .class_init = sbook_class_init,
1494 };
1495
1496 static void sun4m_register_types(void)
1497 {
1498 type_register_static(&idreg_info);
1499 type_register_static(&afx_info);
1500 type_register_static(&prom_info);
1501 type_register_static(&ram_info);
1502
1503 type_register_static(&ss5_type);
1504 type_register_static(&ss10_type);
1505 type_register_static(&ss600mp_type);
1506 type_register_static(&ss20_type);
1507 type_register_static(&voyager_type);
1508 type_register_static(&ss_lx_type);
1509 type_register_static(&ss4_type);
1510 type_register_static(&scls_type);
1511 type_register_static(&sbook_type);
1512 }
1513
1514 type_init(sun4m_register_types)
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