hw/sparc64/sun4u.c

   1 /*
   2  * QEMU Sun4u/Sun4v System Emulator
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "qemu/osdep.h"
  25 #include "qapi/error.h"
  26 #include "qemu-common.h"
  27 #include "cpu.h"
  28 #include "hw/hw.h"
  29 #include "hw/pci/pci.h"
  30 #include "hw/pci/pci_bridge.h"
  31 #include "hw/pci/pci_bus.h"
  32 #include "hw/pci/pci_host.h"
  33 #include "hw/pci-host/apb.h"
  34 #include "hw/i386/pc.h"
  35 #include "hw/char/serial.h"
  36 #include "hw/timer/m48t59.h"
  37 #include "hw/block/fdc.h"
  38 #include "net/net.h"
  39 #include "qemu/timer.h"
  40 #include "sysemu/sysemu.h"
  41 #include "hw/boards.h"
  42 #include "hw/nvram/sun_nvram.h"
  43 #include "hw/nvram/chrp_nvram.h"
  44 #include "hw/sparc/sparc64.h"
  45 #include "hw/nvram/fw_cfg.h"
  46 #include "hw/sysbus.h"
  47 #include "hw/ide.h"
  48 #include "hw/ide/pci.h"
  49 #include "hw/loader.h"
  50 #include "elf.h"
  51 #include "trace.h"
  52 #include "qemu/cutils.h"
  53
  54 #define KERNEL_LOAD_ADDR     0x00404000
  55 #define CMDLINE_ADDR         0x003ff000
  56 #define PROM_SIZE_MAX        (4 * 1024 * 1024)
  57 #define PROM_VADDR           0x000ffd00000ULL
  58 #define APB_SPECIAL_BASE     0x1fe00000000ULL
  59 #define APB_MEM_BASE         0x1ff00000000ULL
  60 #define APB_PCI_IO_BASE      (APB_SPECIAL_BASE + 0x02000000ULL)
  61 #define PROM_FILENAME        "openbios-sparc64"
  62 #define NVRAM_SIZE           0x2000
  63 #define MAX_IDE_BUS          2
  64 #define BIOS_CFG_IOPORT      0x510
  65 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
  66 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
  67 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
  68
  69 #define IVEC_MAX             0x40
  70
  71 struct hwdef {
  72     uint16_t machine_id;
  73     uint64_t prom_addr;
  74     uint64_t console_serial_base;
  75 };
  76
  77 typedef struct EbusState {
  78     /*< private >*/
  79     PCIDevice parent_obj;
  80
  81     ISABus *isa_bus;
  82     qemu_irq isa_bus_irqs[ISA_NUM_IRQS];
  83     uint64_t console_serial_base;
  84     MemoryRegion bar0;
  85     MemoryRegion bar1;
  86 } EbusState;
  87
  88 #define TYPE_EBUS "ebus"
  89 #define EBUS(obj) OBJECT_CHECK(EbusState, (obj), TYPE_EBUS)
  90
  91 void DMA_init(ISABus *bus, int high_page_enable)
  92 {
  93 }
  94
  95 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
  96                             Error **errp)
  97 {
  98     fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
  99 }
 100
 101 static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size,
 102                                   const char *arch, ram_addr_t RAM_size,
 103                                   const char *boot_devices,
 104                                   uint32_t kernel_image, uint32_t kernel_size,
 105                                   const char *cmdline,
 106                                   uint32_t initrd_image, uint32_t initrd_size,
 107                                   uint32_t NVRAM_image,
 108                                   int width, int height, int depth,
 109                                   const uint8_t *macaddr)
 110 {
 111     unsigned int i;
 112     int sysp_end;
 113     uint8_t image[0x1ff0];
 114     NvramClass *k = NVRAM_GET_CLASS(nvram);
 115
 116     memset(image, '\0', sizeof(image));
 117
 118     /* OpenBIOS nvram variables partition */
 119     sysp_end = chrp_nvram_create_system_partition(image, 0);
 120
 121     /* Free space partition */
 122     chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
 123
 124     Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
 125
 126     for (i = 0; i < sizeof(image); i++) {
 127         (k->write)(nvram, i, image[i]);
 128     }
 129
 130     return 0;
 131 }
 132
 133 static uint64_t sun4u_load_kernel(const char *kernel_filename,
 134                                   const char *initrd_filename,
 135                                   ram_addr_t RAM_size, uint64_t *initrd_size,
 136                                   uint64_t *initrd_addr, uint64_t *kernel_addr,
 137                                   uint64_t *kernel_entry)
 138 {
 139     int linux_boot;
 140     unsigned int i;
 141     long kernel_size;
 142     uint8_t *ptr;
 143     uint64_t kernel_top;
 144
 145     linux_boot = (kernel_filename != NULL);
 146
 147     kernel_size = 0;
 148     if (linux_boot) {
 149         int bswap_needed;
 150
 151 #ifdef BSWAP_NEEDED
 152         bswap_needed = 1;
 153 #else
 154         bswap_needed = 0;
 155 #endif
 156         kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry,
 157                                kernel_addr, &kernel_top, 1, EM_SPARCV9, 0, 0);
 158         if (kernel_size < 0) {
 159             *kernel_addr = KERNEL_LOAD_ADDR;
 160             *kernel_entry = KERNEL_LOAD_ADDR;
 161             kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
 162                                     RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
 163                                     TARGET_PAGE_SIZE);
 164         }
 165         if (kernel_size < 0) {
 166             kernel_size = load_image_targphys(kernel_filename,
 167                                               KERNEL_LOAD_ADDR,
 168                                               RAM_size - KERNEL_LOAD_ADDR);
 169         }
 170         if (kernel_size < 0) {
 171             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 172                     kernel_filename);
 173             exit(1);
 174         }
 175         /* load initrd above kernel */
 176         *initrd_size = 0;
 177         if (initrd_filename) {
 178             *initrd_addr = TARGET_PAGE_ALIGN(kernel_top);
 179
 180             *initrd_size = load_image_targphys(initrd_filename,
 181                                                *initrd_addr,
 182                                                RAM_size - *initrd_addr);
 183             if ((int)*initrd_size < 0) {
 184                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 185                         initrd_filename);
 186                 exit(1);
 187             }
 188         }
 189         if (*initrd_size > 0) {
 190             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 191                 ptr = rom_ptr(*kernel_addr + i);
 192                 if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */
 193                     stl_p(ptr + 24, *initrd_addr + *kernel_addr);
 194                     stl_p(ptr + 28, *initrd_size);
 195                     break;
 196                 }
 197             }
 198         }
 199     }
 200     return kernel_size;
 201 }
 202
 203 typedef struct ResetData {
 204     SPARCCPU *cpu;
 205     uint64_t prom_addr;
 206 } ResetData;
 207
 208 static void ebus_isa_irq_handler(void *opaque, int n, int level)
 209 {
 210     EbusState *s = EBUS(opaque);
 211     qemu_irq irq = s->isa_bus_irqs[n];
 212
 213     /* Pass ISA bus IRQs onto their gpio equivalent */
 214     trace_ebus_isa_irq_handler(n, level);
 215     if (irq) {
 216         qemu_set_irq(irq, level);
 217     }
 218 }
 219
 220 /* EBUS (Eight bit bus) bridge */
 221 static void ebus_realize(PCIDevice *pci_dev, Error **errp)
 222 {
 223     EbusState *s = EBUS(pci_dev);
 224     DeviceState *dev;
 225     qemu_irq *isa_irq;
 226     DriveInfo *fd[MAX_FD];
 227     int i;
 228
 229     s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(),
 230                              pci_address_space_io(pci_dev), errp);
 231     if (!s->isa_bus) {
 232         error_setg(errp, "unable to instantiate EBUS ISA bus");
 233         return;
 234     }
 235
 236     /* ISA bus */
 237     isa_irq = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS);
 238     isa_bus_irqs(s->isa_bus, isa_irq);
 239     qdev_init_gpio_out_named(DEVICE(s), s->isa_bus_irqs, "isa-irq",
 240                              ISA_NUM_IRQS);
 241
 242     /* Serial ports */
 243     i = 0;
 244     if (s->console_serial_base) {
 245         serial_mm_init(pci_address_space(pci_dev), s->console_serial_base,
 246                        0, NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN);
 247         i++;
 248     }
 249     serial_hds_isa_init(s->isa_bus, i, MAX_SERIAL_PORTS);
 250
 251     /* Parallel ports */
 252     parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS);
 253
 254     /* Keyboard */
 255     isa_create_simple(s->isa_bus, "i8042");
 256
 257     /* Floppy */
 258     for (i = 0; i < MAX_FD; i++) {
 259         fd[i] = drive_get(IF_FLOPPY, 0, i);
 260     }
 261     dev = DEVICE(isa_create(s->isa_bus, TYPE_ISA_FDC));
 262     if (fd[0]) {
 263         qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]),
 264                             &error_abort);
 265     }
 266     if (fd[1]) {
 267         qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]),
 268                             &error_abort);
 269     }
 270     qdev_prop_set_uint32(dev, "dma", -1);
 271     qdev_init_nofail(dev);
 272
 273     /* PCI */
 274     pci_dev->config[0x04] = 0x06; // command = bus master, pci mem
 275     pci_dev->config[0x05] = 0x00;
 276     pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 277     pci_dev->config[0x07] = 0x03; // status = medium devsel
 278     pci_dev->config[0x09] = 0x00; // programming i/f
 279     pci_dev->config[0x0D] = 0x0a; // latency_timer
 280
 281     memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(),
 282                              0, 0x1000000);
 283     pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
 284     memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(),
 285                              0, 0x4000);
 286     pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1);
 287 }
 288
 289 static Property ebus_properties[] = {
 290     DEFINE_PROP_UINT64("console-serial-base", EbusState,
 291                        console_serial_base, 0),
 292     DEFINE_PROP_END_OF_LIST(),
 293 };
 294
 295 static void ebus_class_init(ObjectClass *klass, void *data)
 296 {
 297     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 298     DeviceClass *dc = DEVICE_CLASS(klass);
 299
 300     k->realize = ebus_realize;
 301     k->vendor_id = PCI_VENDOR_ID_SUN;
 302     k->device_id = PCI_DEVICE_ID_SUN_EBUS;
 303     k->revision = 0x01;
 304     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 305     dc->props = ebus_properties;
 306 }
 307
 308 static const TypeInfo ebus_info = {
 309     .name          = TYPE_EBUS,
 310     .parent        = TYPE_PCI_DEVICE,
 311     .class_init    = ebus_class_init,
 312     .instance_size = sizeof(EbusState),
 313     .interfaces = (InterfaceInfo[]) {
 314         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 315         { },
 316     },
 317 };
 318
 319 #define TYPE_OPENPROM "openprom"
 320 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
 321
 322 typedef struct PROMState {
 323     SysBusDevice parent_obj;
 324
 325     MemoryRegion prom;
 326 } PROMState;
 327
 328 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
 329 {
 330     hwaddr *base_addr = (hwaddr *)opaque;
 331     return addr + *base_addr - PROM_VADDR;
 332 }
 333
 334 /* Boot PROM (OpenBIOS) */
 335 static void prom_init(hwaddr addr, const char *bios_name)
 336 {
 337     DeviceState *dev;
 338     SysBusDevice *s;
 339     char *filename;
 340     int ret;
 341
 342     dev = qdev_create(NULL, TYPE_OPENPROM);
 343     qdev_init_nofail(dev);
 344     s = SYS_BUS_DEVICE(dev);
 345
 346     sysbus_mmio_map(s, 0, addr);
 347
 348     /* load boot prom */
 349     if (bios_name == NULL) {
 350         bios_name = PROM_FILENAME;
 351     }
 352     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 353     if (filename) {
 354         ret = load_elf(filename, translate_prom_address, &addr,
 355                        NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0);
 356         if (ret < 0 || ret > PROM_SIZE_MAX) {
 357             ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
 358         }
 359         g_free(filename);
 360     } else {
 361         ret = -1;
 362     }
 363     if (ret < 0 || ret > PROM_SIZE_MAX) {
 364         fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
 365         exit(1);
 366     }
 367 }
 368
 369 static void prom_init1(Object *obj)
 370 {
 371     PROMState *s = OPENPROM(obj);
 372     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 373
 374     memory_region_init_ram_nomigrate(&s->prom, obj, "sun4u.prom", PROM_SIZE_MAX,
 375                            &error_fatal);
 376     vmstate_register_ram_global(&s->prom);
 377     memory_region_set_readonly(&s->prom, true);
 378     sysbus_init_mmio(dev, &s->prom);
 379 }
 380
 381 static Property prom_properties[] = {
 382     {/* end of property list */},
 383 };
 384
 385 static void prom_class_init(ObjectClass *klass, void *data)
 386 {
 387     DeviceClass *dc = DEVICE_CLASS(klass);
 388
 389     dc->props = prom_properties;
 390 }
 391
 392 static const TypeInfo prom_info = {
 393     .name          = TYPE_OPENPROM,
 394     .parent        = TYPE_SYS_BUS_DEVICE,
 395     .instance_size = sizeof(PROMState),
 396     .class_init    = prom_class_init,
 397     .instance_init = prom_init1,
 398 };
 399
 400
 401 #define TYPE_SUN4U_MEMORY "memory"
 402 #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY)
 403
 404 typedef struct RamDevice {
 405     SysBusDevice parent_obj;
 406
 407     MemoryRegion ram;
 408     uint64_t size;
 409 } RamDevice;
 410
 411 /* System RAM */
 412 static void ram_realize(DeviceState *dev, Error **errp)
 413 {
 414     RamDevice *d = SUN4U_RAM(dev);
 415     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 416
 417     memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size,
 418                            &error_fatal);
 419     vmstate_register_ram_global(&d->ram);
 420     sysbus_init_mmio(sbd, &d->ram);
 421 }
 422
 423 static void ram_init(hwaddr addr, ram_addr_t RAM_size)
 424 {
 425     DeviceState *dev;
 426     SysBusDevice *s;
 427     RamDevice *d;
 428
 429     /* allocate RAM */
 430     dev = qdev_create(NULL, TYPE_SUN4U_MEMORY);
 431     s = SYS_BUS_DEVICE(dev);
 432
 433     d = SUN4U_RAM(dev);
 434     d->size = RAM_size;
 435     qdev_init_nofail(dev);
 436
 437     sysbus_mmio_map(s, 0, addr);
 438 }
 439
 440 static Property ram_properties[] = {
 441     DEFINE_PROP_UINT64("size", RamDevice, size, 0),
 442     DEFINE_PROP_END_OF_LIST(),
 443 };
 444
 445 static void ram_class_init(ObjectClass *klass, void *data)
 446 {
 447     DeviceClass *dc = DEVICE_CLASS(klass);
 448
 449     dc->realize = ram_realize;
 450     dc->props = ram_properties;
 451 }
 452
 453 static const TypeInfo ram_info = {
 454     .name          = TYPE_SUN4U_MEMORY,
 455     .parent        = TYPE_SYS_BUS_DEVICE,
 456     .instance_size = sizeof(RamDevice),
 457     .class_init    = ram_class_init,
 458 };
 459
 460 static void sun4uv_init(MemoryRegion *address_space_mem,
 461                         MachineState *machine,
 462                         const struct hwdef *hwdef)
 463 {
 464     SPARCCPU *cpu;
 465     Nvram *nvram;
 466     unsigned int i;
 467     uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
 468     APBState *apb;
 469     PCIBus *pci_bus, *pci_busA, *pci_busB;
 470     PCIDevice *ebus, *pci_dev;
 471     SysBusDevice *s;
 472     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 473     DeviceState *iommu, *dev;
 474     FWCfgState *fw_cfg;
 475     NICInfo *nd;
 476     MACAddr macaddr;
 477     bool onboard_nic;
 478
 479     /* init CPUs */
 480     cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr);
 481
 482     /* IOMMU */
 483     iommu = qdev_create(NULL, TYPE_SUN4U_IOMMU);
 484     qdev_init_nofail(iommu);
 485
 486     /* set up devices */
 487     ram_init(0, machine->ram_size);
 488
 489     prom_init(hwdef->prom_addr, bios_name);
 490
 491     /* Init APB (PCI host bridge) */
 492     apb = APB_DEVICE(qdev_create(NULL, TYPE_APB));
 493     qdev_prop_set_uint64(DEVICE(apb), "special-base", APB_SPECIAL_BASE);
 494     qdev_prop_set_uint64(DEVICE(apb), "mem-base", APB_MEM_BASE);
 495     object_property_set_link(OBJECT(apb), OBJECT(iommu), "iommu", &error_abort);
 496     qdev_init_nofail(DEVICE(apb));
 497
 498     /* Wire up PCI interrupts to CPU */
 499     for (i = 0; i < IVEC_MAX; i++) {
 500         qdev_connect_gpio_out_named(DEVICE(apb), "ivec-irq", i,
 501             qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i));
 502     }
 503
 504     pci_bus = PCI_HOST_BRIDGE(apb)->bus;
 505     pci_busA = pci_bridge_get_sec_bus(apb->bridgeA);
 506     pci_busB = pci_bridge_get_sec_bus(apb->bridgeB);
 507
 508     /* Only in-built Simba PBMs can exist on the root bus, slot 0 on busA is
 509        reserved (leaving no slots free after on-board devices) however slots
 510        0-3 are free on busB */
 511     pci_bus->slot_reserved_mask = 0xfffffffc;
 512     pci_busA->slot_reserved_mask = 0xfffffff1;
 513     pci_busB->slot_reserved_mask = 0xfffffff0;
 514
 515     ebus = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 0), true, TYPE_EBUS);
 516     qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base",
 517                          hwdef->console_serial_base);
 518     qdev_init_nofail(DEVICE(ebus));
 519
 520     /* Wire up "well-known" ISA IRQs to APB legacy obio IRQs */
 521     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7,
 522         qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_LPT_IRQ));
 523     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6,
 524         qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_FDD_IRQ));
 525     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1,
 526         qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_KBD_IRQ));
 527     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12,
 528         qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_MSE_IRQ));
 529     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4,
 530         qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_SER_IRQ));
 531
 532     pci_dev = pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA");
 533
 534     memset(&macaddr, 0, sizeof(MACAddr));
 535     onboard_nic = false;
 536     for (i = 0; i < nb_nics; i++) {
 537         nd = &nd_table[i];
 538
 539         if (!nd->model || strcmp(nd->model, "sunhme") == 0) {
 540             if (!onboard_nic) {
 541                 pci_dev = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 1),
 542                                                    true, "sunhme");
 543                 memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr));
 544                 onboard_nic = true;
 545             } else {
 546                 pci_dev = pci_create(pci_busB, -1, "sunhme");
 547             }
 548         } else {
 549             pci_dev = pci_create(pci_busB, -1, nd->model);
 550         }
 551
 552         dev = &pci_dev->qdev;
 553         qdev_set_nic_properties(dev, nd);
 554         qdev_init_nofail(dev);
 555     }
 556
 557     /* If we don't have an onboard NIC, grab a default MAC address so that
 558      * we have a valid machine id */
 559     if (!onboard_nic) {
 560         qemu_macaddr_default_if_unset(&macaddr);
 561     }
 562
 563     ide_drive_get(hd, ARRAY_SIZE(hd));
 564
 565     pci_dev = pci_create(pci_busA, PCI_DEVFN(3, 0), "cmd646-ide");
 566     qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1);
 567     qdev_init_nofail(&pci_dev->qdev);
 568     pci_ide_create_devs(pci_dev, hd);
 569
 570     /* Map NVRAM into I/O (ebus) space */
 571     nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59);
 572     s = SYS_BUS_DEVICE(nvram);
 573     memory_region_add_subregion(pci_address_space_io(ebus), 0x2000,
 574                                 sysbus_mmio_get_region(s, 0));
 575
 576     initrd_size = 0;
 577     initrd_addr = 0;
 578     kernel_size = sun4u_load_kernel(machine->kernel_filename,
 579                                     machine->initrd_filename,
 580                                     ram_size, &initrd_size, &initrd_addr,
 581                                     &kernel_addr, &kernel_entry);
 582
 583     sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size,
 584                            machine->boot_order,
 585                            kernel_addr, kernel_size,
 586                            machine->kernel_cmdline,
 587                            initrd_addr, initrd_size,
 588                            /* XXX: need an option to load a NVRAM image */
 589                            0,
 590                            graphic_width, graphic_height, graphic_depth,
 591                            (uint8_t *)&macaddr);
 592
 593     dev = qdev_create(NULL, TYPE_FW_CFG_IO);
 594     qdev_prop_set_bit(dev, "dma_enabled", false);
 595     object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev), NULL);
 596     qdev_init_nofail(dev);
 597     memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT,
 598                                 &FW_CFG_IO(dev)->comb_iomem);
 599
 600     fw_cfg = FW_CFG(dev);
 601     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
 602     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
 603     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 604     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
 605     fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry);
 606     fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 607     if (machine->kernel_cmdline) {
 608         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
 609                        strlen(machine->kernel_cmdline) + 1);
 610         fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
 611     } else {
 612         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
 613     }
 614     fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 615     fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 616     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
 617
 618     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
 619     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
 620     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
 621
 622     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 623 }
 624
 625 enum {
 626     sun4u_id = 0,
 627     sun4v_id = 64,
 628 };
 629
 630 static const struct hwdef hwdefs[] = {
 631     /* Sun4u generic PC-like machine */
 632     {
 633         .machine_id = sun4u_id,
 634         .prom_addr = 0x1fff0000000ULL,
 635         .console_serial_base = 0,
 636     },
 637     /* Sun4v generic PC-like machine */
 638     {
 639         .machine_id = sun4v_id,
 640         .prom_addr = 0x1fff0000000ULL,
 641         .console_serial_base = 0,
 642     },
 643 };
 644
 645 /* Sun4u hardware initialisation */
 646 static void sun4u_init(MachineState *machine)
 647 {
 648     sun4uv_init(get_system_memory(), machine, &hwdefs[0]);
 649 }
 650
 651 /* Sun4v hardware initialisation */
 652 static void sun4v_init(MachineState *machine)
 653 {
 654     sun4uv_init(get_system_memory(), machine, &hwdefs[1]);
 655 }
 656
 657 static void sun4u_class_init(ObjectClass *oc, void *data)
 658 {
 659     MachineClass *mc = MACHINE_CLASS(oc);
 660
 661     mc->desc = "Sun4u platform";
 662     mc->init = sun4u_init;
 663     mc->block_default_type = IF_IDE;
 664     mc->max_cpus = 1; /* XXX for now */
 665     mc->is_default = 1;
 666     mc->default_boot_order = "c";
 667     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi");
 668 }
 669
 670 static const TypeInfo sun4u_type = {
 671     .name = MACHINE_TYPE_NAME("sun4u"),
 672     .parent = TYPE_MACHINE,
 673     .class_init = sun4u_class_init,
 674 };
 675
 676 static void sun4v_class_init(ObjectClass *oc, void *data)
 677 {
 678     MachineClass *mc = MACHINE_CLASS(oc);
 679
 680     mc->desc = "Sun4v platform";
 681     mc->init = sun4v_init;
 682     mc->block_default_type = IF_IDE;
 683     mc->max_cpus = 1; /* XXX for now */
 684     mc->default_boot_order = "c";
 685     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1");
 686 }
 687
 688 static const TypeInfo sun4v_type = {
 689     .name = MACHINE_TYPE_NAME("sun4v"),
 690     .parent = TYPE_MACHINE,
 691     .class_init = sun4v_class_init,
 692 };
 693
 694 static void sun4u_register_types(void)
 695 {
 696     type_register_static(&ebus_info);
 697     type_register_static(&prom_info);
 698     type_register_static(&ram_info);
 699
 700     type_register_static(&sun4u_type);
 701     type_register_static(&sun4v_type);
 702 }
 703
 704 type_init(sun4u_register_types)