hw/sparc64/sun4u.c

   1 /*
   2  * QEMU Sun4u/Sun4v System Emulator
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "qemu/osdep.h"
  25 #include "qapi/error.h"
  26 #include "qemu-common.h"
  27 #include "cpu.h"
  28 #include "hw/hw.h"
  29 #include "hw/pci/pci.h"
  30 #include "hw/pci/pci_bridge.h"
  31 #include "hw/pci/pci_bus.h"
  32 #include "hw/pci-host/apb.h"
  33 #include "hw/i386/pc.h"
  34 #include "hw/char/serial.h"
  35 #include "hw/timer/m48t59.h"
  36 #include "hw/block/fdc.h"
  37 #include "net/net.h"
  38 #include "qemu/timer.h"
  39 #include "sysemu/sysemu.h"
  40 #include "hw/boards.h"
  41 #include "hw/nvram/sun_nvram.h"
  42 #include "hw/nvram/chrp_nvram.h"
  43 #include "hw/sparc/sparc64.h"
  44 #include "hw/nvram/fw_cfg.h"
  45 #include "hw/sysbus.h"
  46 #include "hw/ide.h"
  47 #include "hw/ide/pci.h"
  48 #include "hw/loader.h"
  49 #include "elf.h"
  50 #include "trace.h"
  51 #include "qemu/cutils.h"
  52
  53 #define KERNEL_LOAD_ADDR     0x00404000
  54 #define CMDLINE_ADDR         0x003ff000
  55 #define PROM_SIZE_MAX        (4 * 1024 * 1024)
  56 #define PROM_VADDR           0x000ffd00000ULL
  57 #define APB_SPECIAL_BASE     0x1fe00000000ULL
  58 #define APB_MEM_BASE         0x1ff00000000ULL
  59 #define APB_PCI_IO_BASE      (APB_SPECIAL_BASE + 0x02000000ULL)
  60 #define PROM_FILENAME        "openbios-sparc64"
  61 #define NVRAM_SIZE           0x2000
  62 #define MAX_IDE_BUS          2
  63 #define BIOS_CFG_IOPORT      0x510
  64 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
  65 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
  66 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
  67
  68 #define IVEC_MAX             0x40
  69
  70 struct hwdef {
  71     uint16_t machine_id;
  72     uint64_t prom_addr;
  73     uint64_t console_serial_base;
  74 };
  75
  76 typedef struct EbusState {
  77     /*< private >*/
  78     PCIDevice parent_obj;
  79
  80     ISABus *isa_bus;
  81     qemu_irq isa_bus_irqs[ISA_NUM_IRQS];
  82     uint64_t console_serial_base;
  83     MemoryRegion bar0;
  84     MemoryRegion bar1;
  85 } EbusState;
  86
  87 #define TYPE_EBUS "ebus"
  88 #define EBUS(obj) OBJECT_CHECK(EbusState, (obj), TYPE_EBUS)
  89
  90 void DMA_init(ISABus *bus, int high_page_enable)
  91 {
  92 }
  93
  94 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
  95                             Error **errp)
  96 {
  97     fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
  98 }
  99
 100 static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size,
 101                                   const char *arch, ram_addr_t RAM_size,
 102                                   const char *boot_devices,
 103                                   uint32_t kernel_image, uint32_t kernel_size,
 104                                   const char *cmdline,
 105                                   uint32_t initrd_image, uint32_t initrd_size,
 106                                   uint32_t NVRAM_image,
 107                                   int width, int height, int depth,
 108                                   const uint8_t *macaddr)
 109 {
 110     unsigned int i;
 111     int sysp_end;
 112     uint8_t image[0x1ff0];
 113     NvramClass *k = NVRAM_GET_CLASS(nvram);
 114
 115     memset(image, '\0', sizeof(image));
 116
 117     /* OpenBIOS nvram variables partition */
 118     sysp_end = chrp_nvram_create_system_partition(image, 0);
 119
 120     /* Free space partition */
 121     chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
 122
 123     Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
 124
 125     for (i = 0; i < sizeof(image); i++) {
 126         (k->write)(nvram, i, image[i]);
 127     }
 128
 129     return 0;
 130 }
 131
 132 static uint64_t sun4u_load_kernel(const char *kernel_filename,
 133                                   const char *initrd_filename,
 134                                   ram_addr_t RAM_size, uint64_t *initrd_size,
 135                                   uint64_t *initrd_addr, uint64_t *kernel_addr,
 136                                   uint64_t *kernel_entry)
 137 {
 138     int linux_boot;
 139     unsigned int i;
 140     long kernel_size;
 141     uint8_t *ptr;
 142     uint64_t kernel_top;
 143
 144     linux_boot = (kernel_filename != NULL);
 145
 146     kernel_size = 0;
 147     if (linux_boot) {
 148         int bswap_needed;
 149
 150 #ifdef BSWAP_NEEDED
 151         bswap_needed = 1;
 152 #else
 153         bswap_needed = 0;
 154 #endif
 155         kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry,
 156                                kernel_addr, &kernel_top, 1, EM_SPARCV9, 0, 0);
 157         if (kernel_size < 0) {
 158             *kernel_addr = KERNEL_LOAD_ADDR;
 159             *kernel_entry = KERNEL_LOAD_ADDR;
 160             kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
 161                                     RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
 162                                     TARGET_PAGE_SIZE);
 163         }
 164         if (kernel_size < 0) {
 165             kernel_size = load_image_targphys(kernel_filename,
 166                                               KERNEL_LOAD_ADDR,
 167                                               RAM_size - KERNEL_LOAD_ADDR);
 168         }
 169         if (kernel_size < 0) {
 170             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 171                     kernel_filename);
 172             exit(1);
 173         }
 174         /* load initrd above kernel */
 175         *initrd_size = 0;
 176         if (initrd_filename) {
 177             *initrd_addr = TARGET_PAGE_ALIGN(kernel_top);
 178
 179             *initrd_size = load_image_targphys(initrd_filename,
 180                                                *initrd_addr,
 181                                                RAM_size - *initrd_addr);
 182             if ((int)*initrd_size < 0) {
 183                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 184                         initrd_filename);
 185                 exit(1);
 186             }
 187         }
 188         if (*initrd_size > 0) {
 189             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 190                 ptr = rom_ptr(*kernel_addr + i);
 191                 if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */
 192                     stl_p(ptr + 24, *initrd_addr + *kernel_addr);
 193                     stl_p(ptr + 28, *initrd_size);
 194                     break;
 195                 }
 196             }
 197         }
 198     }
 199     return kernel_size;
 200 }
 201
 202 typedef struct ResetData {
 203     SPARCCPU *cpu;
 204     uint64_t prom_addr;
 205 } ResetData;
 206
 207 static void ebus_isa_irq_handler(void *opaque, int n, int level)
 208 {
 209     EbusState *s = EBUS(opaque);
 210     qemu_irq irq = s->isa_bus_irqs[n];
 211
 212     /* Pass ISA bus IRQs onto their gpio equivalent */
 213     trace_ebus_isa_irq_handler(n, level);
 214     if (irq) {
 215         qemu_set_irq(irq, level);
 216     }
 217 }
 218
 219 /* EBUS (Eight bit bus) bridge */
 220 static void ebus_realize(PCIDevice *pci_dev, Error **errp)
 221 {
 222     EbusState *s = EBUS(pci_dev);
 223     DeviceState *dev;
 224     qemu_irq *isa_irq;
 225     DriveInfo *fd[MAX_FD];
 226     int i;
 227
 228     s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(),
 229                              pci_address_space_io(pci_dev), errp);
 230     if (!s->isa_bus) {
 231         error_setg(errp, "unable to instantiate EBUS ISA bus");
 232         return;
 233     }
 234
 235     /* ISA bus */
 236     isa_irq = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS);
 237     isa_bus_irqs(s->isa_bus, isa_irq);
 238     qdev_init_gpio_out_named(DEVICE(s), s->isa_bus_irqs, "isa-irq",
 239                              ISA_NUM_IRQS);
 240
 241     /* Serial ports */
 242     i = 0;
 243     if (s->console_serial_base) {
 244         serial_mm_init(pci_address_space(pci_dev), s->console_serial_base,
 245                        0, NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN);
 246         i++;
 247     }
 248     serial_hds_isa_init(s->isa_bus, i, MAX_SERIAL_PORTS);
 249
 250     /* Parallel ports */
 251     parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS);
 252
 253     /* Keyboard */
 254     isa_create_simple(s->isa_bus, "i8042");
 255
 256     /* Floppy */
 257     for (i = 0; i < MAX_FD; i++) {
 258         fd[i] = drive_get(IF_FLOPPY, 0, i);
 259     }
 260     dev = DEVICE(isa_create(s->isa_bus, TYPE_ISA_FDC));
 261     if (fd[0]) {
 262         qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]),
 263                             &error_abort);
 264     }
 265     if (fd[1]) {
 266         qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]),
 267                             &error_abort);
 268     }
 269     qdev_prop_set_uint32(dev, "dma", -1);
 270     qdev_init_nofail(dev);
 271
 272     /* PCI */
 273     pci_dev->config[0x04] = 0x06; // command = bus master, pci mem
 274     pci_dev->config[0x05] = 0x00;
 275     pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 276     pci_dev->config[0x07] = 0x03; // status = medium devsel
 277     pci_dev->config[0x09] = 0x00; // programming i/f
 278     pci_dev->config[0x0D] = 0x0a; // latency_timer
 279
 280     memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(),
 281                              0, 0x1000000);
 282     pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
 283     memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(),
 284                              0, 0x4000);
 285     pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1);
 286 }
 287
 288 static Property ebus_properties[] = {
 289     DEFINE_PROP_UINT64("console-serial-base", EbusState,
 290                        console_serial_base, 0),
 291     DEFINE_PROP_END_OF_LIST(),
 292 };
 293
 294 static void ebus_class_init(ObjectClass *klass, void *data)
 295 {
 296     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 297     DeviceClass *dc = DEVICE_CLASS(klass);
 298
 299     k->realize = ebus_realize;
 300     k->vendor_id = PCI_VENDOR_ID_SUN;
 301     k->device_id = PCI_DEVICE_ID_SUN_EBUS;
 302     k->revision = 0x01;
 303     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 304     dc->props = ebus_properties;
 305 }
 306
 307 static const TypeInfo ebus_info = {
 308     .name          = TYPE_EBUS,
 309     .parent        = TYPE_PCI_DEVICE,
 310     .class_init    = ebus_class_init,
 311     .instance_size = sizeof(EbusState),
 312     .interfaces = (InterfaceInfo[]) {
 313         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 314         { },
 315     },
 316 };
 317
 318 #define TYPE_OPENPROM "openprom"
 319 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
 320
 321 typedef struct PROMState {
 322     SysBusDevice parent_obj;
 323
 324     MemoryRegion prom;
 325 } PROMState;
 326
 327 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
 328 {
 329     hwaddr *base_addr = (hwaddr *)opaque;
 330     return addr + *base_addr - PROM_VADDR;
 331 }
 332
 333 /* Boot PROM (OpenBIOS) */
 334 static void prom_init(hwaddr addr, const char *bios_name)
 335 {
 336     DeviceState *dev;
 337     SysBusDevice *s;
 338     char *filename;
 339     int ret;
 340
 341     dev = qdev_create(NULL, TYPE_OPENPROM);
 342     qdev_init_nofail(dev);
 343     s = SYS_BUS_DEVICE(dev);
 344
 345     sysbus_mmio_map(s, 0, addr);
 346
 347     /* load boot prom */
 348     if (bios_name == NULL) {
 349         bios_name = PROM_FILENAME;
 350     }
 351     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 352     if (filename) {
 353         ret = load_elf(filename, translate_prom_address, &addr,
 354                        NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0);
 355         if (ret < 0 || ret > PROM_SIZE_MAX) {
 356             ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
 357         }
 358         g_free(filename);
 359     } else {
 360         ret = -1;
 361     }
 362     if (ret < 0 || ret > PROM_SIZE_MAX) {
 363         fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
 364         exit(1);
 365     }
 366 }
 367
 368 static void prom_init1(Object *obj)
 369 {
 370     PROMState *s = OPENPROM(obj);
 371     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 372
 373     memory_region_init_ram_nomigrate(&s->prom, obj, "sun4u.prom", PROM_SIZE_MAX,
 374                            &error_fatal);
 375     vmstate_register_ram_global(&s->prom);
 376     memory_region_set_readonly(&s->prom, true);
 377     sysbus_init_mmio(dev, &s->prom);
 378 }
 379
 380 static Property prom_properties[] = {
 381     {/* end of property list */},
 382 };
 383
 384 static void prom_class_init(ObjectClass *klass, void *data)
 385 {
 386     DeviceClass *dc = DEVICE_CLASS(klass);
 387
 388     dc->props = prom_properties;
 389 }
 390
 391 static const TypeInfo prom_info = {
 392     .name          = TYPE_OPENPROM,
 393     .parent        = TYPE_SYS_BUS_DEVICE,
 394     .instance_size = sizeof(PROMState),
 395     .class_init    = prom_class_init,
 396     .instance_init = prom_init1,
 397 };
 398
 399
 400 #define TYPE_SUN4U_MEMORY "memory"
 401 #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY)
 402
 403 typedef struct RamDevice {
 404     SysBusDevice parent_obj;
 405
 406     MemoryRegion ram;
 407     uint64_t size;
 408 } RamDevice;
 409
 410 /* System RAM */
 411 static void ram_realize(DeviceState *dev, Error **errp)
 412 {
 413     RamDevice *d = SUN4U_RAM(dev);
 414     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 415
 416     memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size,
 417                            &error_fatal);
 418     vmstate_register_ram_global(&d->ram);
 419     sysbus_init_mmio(sbd, &d->ram);
 420 }
 421
 422 static void ram_init(hwaddr addr, ram_addr_t RAM_size)
 423 {
 424     DeviceState *dev;
 425     SysBusDevice *s;
 426     RamDevice *d;
 427
 428     /* allocate RAM */
 429     dev = qdev_create(NULL, TYPE_SUN4U_MEMORY);
 430     s = SYS_BUS_DEVICE(dev);
 431
 432     d = SUN4U_RAM(dev);
 433     d->size = RAM_size;
 434     qdev_init_nofail(dev);
 435
 436     sysbus_mmio_map(s, 0, addr);
 437 }
 438
 439 static Property ram_properties[] = {
 440     DEFINE_PROP_UINT64("size", RamDevice, size, 0),
 441     DEFINE_PROP_END_OF_LIST(),
 442 };
 443
 444 static void ram_class_init(ObjectClass *klass, void *data)
 445 {
 446     DeviceClass *dc = DEVICE_CLASS(klass);
 447
 448     dc->realize = ram_realize;
 449     dc->props = ram_properties;
 450 }
 451
 452 static const TypeInfo ram_info = {
 453     .name          = TYPE_SUN4U_MEMORY,
 454     .parent        = TYPE_SYS_BUS_DEVICE,
 455     .instance_size = sizeof(RamDevice),
 456     .class_init    = ram_class_init,
 457 };
 458
 459 static void sun4uv_init(MemoryRegion *address_space_mem,
 460                         MachineState *machine,
 461                         const struct hwdef *hwdef)
 462 {
 463     SPARCCPU *cpu;
 464     Nvram *nvram;
 465     unsigned int i;
 466     uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
 467     APBState *apb;
 468     PCIBus *pci_bus, *pci_busA, *pci_busB;
 469     PCIDevice *ebus, *pci_dev;
 470     SysBusDevice *s;
 471     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 472     DeviceState *iommu, *dev;
 473     FWCfgState *fw_cfg;
 474     NICInfo *nd;
 475     MACAddr macaddr;
 476     bool onboard_nic;
 477
 478     /* init CPUs */
 479     cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr);
 480
 481     /* IOMMU */
 482     iommu = qdev_create(NULL, TYPE_SUN4U_IOMMU);
 483     qdev_init_nofail(iommu);
 484
 485     /* set up devices */
 486     ram_init(0, machine->ram_size);
 487
 488     prom_init(hwdef->prom_addr, bios_name);
 489
 490     /* Init APB (PCI host bridge) */
 491     apb = APB_DEVICE(qdev_create(NULL, TYPE_APB));
 492     qdev_prop_set_uint64(DEVICE(apb), "special-base", APB_SPECIAL_BASE);
 493     qdev_prop_set_uint64(DEVICE(apb), "mem-base", APB_MEM_BASE);
 494     object_property_set_link(OBJECT(apb), OBJECT(iommu), "iommu", &error_abort);
 495     qdev_init_nofail(DEVICE(apb));
 496
 497     /* Wire up PCI interrupts to CPU */
 498     for (i = 0; i < IVEC_MAX; i++) {
 499         qdev_connect_gpio_out_named(DEVICE(apb), "ivec-irq", i,
 500             qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i));
 501     }
 502
 503     pci_bus = PCI_HOST_BRIDGE(apb)->bus;
 504     pci_busA = pci_bridge_get_sec_bus(apb->bridgeA);
 505     pci_busB = pci_bridge_get_sec_bus(apb->bridgeB);
 506
 507     /* Only in-built Simba PBMs can exist on the root bus, slot 0 on busA is
 508        reserved (leaving no slots free after on-board devices) however slots
 509        0-3 are free on busB */
 510     pci_bus->slot_reserved_mask = 0xfffffffc;
 511     pci_busA->slot_reserved_mask = 0xfffffff1;
 512     pci_busB->slot_reserved_mask = 0xfffffff0;
 513
 514     ebus = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 0), true, TYPE_EBUS);
 515     qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base",
 516                          hwdef->console_serial_base);
 517     qdev_init_nofail(DEVICE(ebus));
 518
 519     /* Wire up "well-known" ISA IRQs to APB legacy obio IRQs */
 520     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7,
 521         qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_LPT_IRQ));
 522     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6,
 523         qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_FDD_IRQ));
 524     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1,
 525         qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_KBD_IRQ));
 526     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12,
 527         qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_MSE_IRQ));
 528     qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4,
 529         qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_SER_IRQ));
 530
 531     pci_dev = pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA");
 532
 533     memset(&macaddr, 0, sizeof(MACAddr));
 534     onboard_nic = false;
 535     for (i = 0; i < nb_nics; i++) {
 536         nd = &nd_table[i];
 537
 538         if (!nd->model || strcmp(nd->model, "sunhme") == 0) {
 539             if (!onboard_nic) {
 540                 pci_dev = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 1),
 541                                                    true, "sunhme");
 542                 memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr));
 543                 onboard_nic = true;
 544             } else {
 545                 pci_dev = pci_create(pci_busB, -1, "sunhme");
 546             }
 547         } else {
 548             pci_dev = pci_create(pci_busB, -1, nd->model);
 549         }
 550
 551         dev = &pci_dev->qdev;
 552         qdev_set_nic_properties(dev, nd);
 553         qdev_init_nofail(dev);
 554     }
 555
 556     /* If we don't have an onboard NIC, grab a default MAC address so that
 557      * we have a valid machine id */
 558     if (!onboard_nic) {
 559         qemu_macaddr_default_if_unset(&macaddr);
 560     }
 561
 562     ide_drive_get(hd, ARRAY_SIZE(hd));
 563
 564     pci_dev = pci_create(pci_busA, PCI_DEVFN(3, 0), "cmd646-ide");
 565     qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1);
 566     qdev_init_nofail(&pci_dev->qdev);
 567     pci_ide_create_devs(pci_dev, hd);
 568
 569     /* Map NVRAM into I/O (ebus) space */
 570     nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59);
 571     s = SYS_BUS_DEVICE(nvram);
 572     memory_region_add_subregion(pci_address_space_io(ebus), 0x2000,
 573                                 sysbus_mmio_get_region(s, 0));
 574
 575     initrd_size = 0;
 576     initrd_addr = 0;
 577     kernel_size = sun4u_load_kernel(machine->kernel_filename,
 578                                     machine->initrd_filename,
 579                                     ram_size, &initrd_size, &initrd_addr,
 580                                     &kernel_addr, &kernel_entry);
 581
 582     sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size,
 583                            machine->boot_order,
 584                            kernel_addr, kernel_size,
 585                            machine->kernel_cmdline,
 586                            initrd_addr, initrd_size,
 587                            /* XXX: need an option to load a NVRAM image */
 588                            0,
 589                            graphic_width, graphic_height, graphic_depth,
 590                            (uint8_t *)&macaddr);
 591
 592     dev = qdev_create(NULL, TYPE_FW_CFG_IO);
 593     qdev_prop_set_bit(dev, "dma_enabled", false);
 594     object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev), NULL);
 595     qdev_init_nofail(dev);
 596     memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT,
 597                                 &FW_CFG_IO(dev)->comb_iomem);
 598
 599     fw_cfg = FW_CFG(dev);
 600     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
 601     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
 602     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 603     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
 604     fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry);
 605     fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 606     if (machine->kernel_cmdline) {
 607         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
 608                        strlen(machine->kernel_cmdline) + 1);
 609         fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
 610     } else {
 611         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
 612     }
 613     fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 614     fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 615     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
 616
 617     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
 618     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
 619     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
 620
 621     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 622 }
 623
 624 enum {
 625     sun4u_id = 0,
 626     sun4v_id = 64,
 627 };
 628
 629 static const struct hwdef hwdefs[] = {
 630     /* Sun4u generic PC-like machine */
 631     {
 632         .machine_id = sun4u_id,
 633         .prom_addr = 0x1fff0000000ULL,
 634         .console_serial_base = 0,
 635     },
 636     /* Sun4v generic PC-like machine */
 637     {
 638         .machine_id = sun4v_id,
 639         .prom_addr = 0x1fff0000000ULL,
 640         .console_serial_base = 0,
 641     },
 642 };
 643
 644 /* Sun4u hardware initialisation */
 645 static void sun4u_init(MachineState *machine)
 646 {
 647     sun4uv_init(get_system_memory(), machine, &hwdefs[0]);
 648 }
 649
 650 /* Sun4v hardware initialisation */
 651 static void sun4v_init(MachineState *machine)
 652 {
 653     sun4uv_init(get_system_memory(), machine, &hwdefs[1]);
 654 }
 655
 656 static void sun4u_class_init(ObjectClass *oc, void *data)
 657 {
 658     MachineClass *mc = MACHINE_CLASS(oc);
 659
 660     mc->desc = "Sun4u platform";
 661     mc->init = sun4u_init;
 662     mc->block_default_type = IF_IDE;
 663     mc->max_cpus = 1; /* XXX for now */
 664     mc->is_default = 1;
 665     mc->default_boot_order = "c";
 666     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi");
 667 }
 668
 669 static const TypeInfo sun4u_type = {
 670     .name = MACHINE_TYPE_NAME("sun4u"),
 671     .parent = TYPE_MACHINE,
 672     .class_init = sun4u_class_init,
 673 };
 674
 675 static void sun4v_class_init(ObjectClass *oc, void *data)
 676 {
 677     MachineClass *mc = MACHINE_CLASS(oc);
 678
 679     mc->desc = "Sun4v platform";
 680     mc->init = sun4v_init;
 681     mc->block_default_type = IF_IDE;
 682     mc->max_cpus = 1; /* XXX for now */
 683     mc->default_boot_order = "c";
 684     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1");
 685 }
 686
 687 static const TypeInfo sun4v_type = {
 688     .name = MACHINE_TYPE_NAME("sun4v"),
 689     .parent = TYPE_MACHINE,
 690     .class_init = sun4v_class_init,
 691 };
 692
 693 static void sun4u_register_types(void)
 694 {
 695     type_register_static(&ebus_info);
 696     type_register_static(&prom_info);
 697     type_register_static(&ram_info);
 698
 699     type_register_static(&sun4u_type);
 700     type_register_static(&sun4v_type);
 701 }
 702
 703 type_init(sun4u_register_types)