2 * ASPEED AST2400 SMC Controller (SPI Flash Only)
4 * Copyright (C) 2016 IBM Corp.
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "hw/sysbus.h"
27 #include "migration/vmstate.h"
29 #include "qemu/module.h"
30 #include "qemu/error-report.h"
33 #include "hw/qdev-properties.h"
34 #include "hw/ssi/aspeed_smc.h"
36 /* CE Type Setting Register */
37 #define R_CONF (0x00 / 4)
38 #define CONF_LEGACY_DISABLE (1 << 31)
39 #define CONF_ENABLE_W4 20
40 #define CONF_ENABLE_W3 19
41 #define CONF_ENABLE_W2 18
42 #define CONF_ENABLE_W1 17
43 #define CONF_ENABLE_W0 16
44 #define CONF_FLASH_TYPE4 8
45 #define CONF_FLASH_TYPE3 6
46 #define CONF_FLASH_TYPE2 4
47 #define CONF_FLASH_TYPE1 2
48 #define CONF_FLASH_TYPE0 0
49 #define CONF_FLASH_TYPE_NOR 0x0
50 #define CONF_FLASH_TYPE_NAND 0x1
51 #define CONF_FLASH_TYPE_SPI 0x2
53 /* CE Control Register */
54 #define R_CE_CTRL (0x04 / 4)
55 #define CTRL_EXTENDED4 4 /* 32 bit addressing for SPI */
56 #define CTRL_EXTENDED3 3 /* 32 bit addressing for SPI */
57 #define CTRL_EXTENDED2 2 /* 32 bit addressing for SPI */
58 #define CTRL_EXTENDED1 1 /* 32 bit addressing for SPI */
59 #define CTRL_EXTENDED0 0 /* 32 bit addressing for SPI */
61 /* Interrupt Control and Status Register */
62 #define R_INTR_CTRL (0x08 / 4)
63 #define INTR_CTRL_DMA_STATUS (1 << 11)
64 #define INTR_CTRL_CMD_ABORT_STATUS (1 << 10)
65 #define INTR_CTRL_WRITE_PROTECT_STATUS (1 << 9)
66 #define INTR_CTRL_DMA_EN (1 << 3)
67 #define INTR_CTRL_CMD_ABORT_EN (1 << 2)
68 #define INTR_CTRL_WRITE_PROTECT_EN (1 << 1)
70 /* CEx Control Register */
71 #define R_CTRL0 (0x10 / 4)
72 #define CTRL_IO_DUAL_DATA (1 << 29)
73 #define CTRL_IO_DUAL_ADDR_DATA (1 << 28) /* Includes dummies */
74 #define CTRL_CMD_SHIFT 16
75 #define CTRL_CMD_MASK 0xff
76 #define CTRL_DUMMY_HIGH_SHIFT 14
77 #define CTRL_AST2400_SPI_4BYTE (1 << 13)
78 #define CTRL_DUMMY_LOW_SHIFT 6 /* 2 bits [7:6] */
79 #define CTRL_CE_STOP_ACTIVE (1 << 2)
80 #define CTRL_CMD_MODE_MASK 0x3
81 #define CTRL_READMODE 0x0
82 #define CTRL_FREADMODE 0x1
83 #define CTRL_WRITEMODE 0x2
84 #define CTRL_USERMODE 0x3
85 #define R_CTRL1 (0x14 / 4)
86 #define R_CTRL2 (0x18 / 4)
87 #define R_CTRL3 (0x1C / 4)
88 #define R_CTRL4 (0x20 / 4)
90 /* CEx Segment Address Register */
91 #define R_SEG_ADDR0 (0x30 / 4)
92 #define SEG_END_SHIFT 24 /* 8MB units */
93 #define SEG_END_MASK 0xff
94 #define SEG_START_SHIFT 16 /* address bit [A29-A23] */
95 #define SEG_START_MASK 0xff
96 #define R_SEG_ADDR1 (0x34 / 4)
97 #define R_SEG_ADDR2 (0x38 / 4)
98 #define R_SEG_ADDR3 (0x3C / 4)
99 #define R_SEG_ADDR4 (0x40 / 4)
101 /* Misc Control Register #1 */
102 #define R_MISC_CTRL1 (0x50 / 4)
104 /* SPI dummy cycle data */
105 #define R_DUMMY_DATA (0x54 / 4)
107 /* DMA Control/Status Register */
108 #define R_DMA_CTRL (0x80 / 4)
109 #define DMA_CTRL_DELAY_MASK 0xf
110 #define DMA_CTRL_DELAY_SHIFT 8
111 #define DMA_CTRL_FREQ_MASK 0xf
112 #define DMA_CTRL_FREQ_SHIFT 4
113 #define DMA_CTRL_MODE (1 << 3)
114 #define DMA_CTRL_CKSUM (1 << 2)
115 #define DMA_CTRL_DIR (1 << 1)
116 #define DMA_CTRL_EN (1 << 0)
118 /* DMA Flash Side Address */
119 #define R_DMA_FLASH_ADDR (0x84 / 4)
121 /* DMA DRAM Side Address */
122 #define R_DMA_DRAM_ADDR (0x88 / 4)
124 /* DMA Length Register */
125 #define R_DMA_LEN (0x8C / 4)
127 /* Checksum Calculation Result */
128 #define R_DMA_CHECKSUM (0x90 / 4)
130 /* Misc Control Register #2 */
131 #define R_TIMINGS (0x94 / 4)
133 /* SPI controller registers and bits */
134 #define R_SPI_CONF (0x00 / 4)
135 #define SPI_CONF_ENABLE_W0 0
136 #define R_SPI_CTRL0 (0x4 / 4)
137 #define R_SPI_MISC_CTRL (0x10 / 4)
138 #define R_SPI_TIMINGS (0x14 / 4)
140 #define ASPEED_SMC_R_SPI_MAX (0x20 / 4)
141 #define ASPEED_SMC_R_SMC_MAX (0x20 / 4)
143 #define ASPEED_SOC_SMC_FLASH_BASE 0x10000000
144 #define ASPEED_SOC_FMC_FLASH_BASE 0x20000000
145 #define ASPEED_SOC_SPI_FLASH_BASE 0x30000000
146 #define ASPEED_SOC_SPI2_FLASH_BASE 0x38000000
149 #define SPI_OP_READ 0x03 /* Read data bytes (low frequency) */
151 #define SNOOP_OFF 0xFF
152 #define SNOOP_START 0x0
155 * Default segments mapping addresses and size for each slave per
156 * controller. These can be changed when board is initialized with the
157 * Segment Address Registers.
159 static const AspeedSegments aspeed_segments_legacy
[] = {
160 { 0x10000000, 32 * 1024 * 1024 },
163 static const AspeedSegments aspeed_segments_fmc
[] = {
164 { 0x20000000, 64 * 1024 * 1024 }, /* start address is readonly */
165 { 0x24000000, 32 * 1024 * 1024 },
166 { 0x26000000, 32 * 1024 * 1024 },
167 { 0x28000000, 32 * 1024 * 1024 },
168 { 0x2A000000, 32 * 1024 * 1024 }
171 static const AspeedSegments aspeed_segments_spi
[] = {
172 { 0x30000000, 64 * 1024 * 1024 },
175 static const AspeedSegments aspeed_segments_ast2500_fmc
[] = {
176 { 0x20000000, 128 * 1024 * 1024 }, /* start address is readonly */
177 { 0x28000000, 32 * 1024 * 1024 },
178 { 0x2A000000, 32 * 1024 * 1024 },
181 static const AspeedSegments aspeed_segments_ast2500_spi1
[] = {
182 { 0x30000000, 32 * 1024 * 1024 }, /* start address is readonly */
183 { 0x32000000, 96 * 1024 * 1024 }, /* end address is readonly */
186 static const AspeedSegments aspeed_segments_ast2500_spi2
[] = {
187 { 0x38000000, 32 * 1024 * 1024 }, /* start address is readonly */
188 { 0x3A000000, 96 * 1024 * 1024 }, /* end address is readonly */
191 static const AspeedSMCController controllers
[] = {
193 .name
= "aspeed.smc.smc",
195 .r_ce_ctrl
= R_CE_CTRL
,
197 .r_timings
= R_TIMINGS
,
198 .conf_enable_w0
= CONF_ENABLE_W0
,
200 .segments
= aspeed_segments_legacy
,
201 .flash_window_base
= ASPEED_SOC_SMC_FLASH_BASE
,
202 .flash_window_size
= 0x6000000,
204 .nregs
= ASPEED_SMC_R_SMC_MAX
,
206 .name
= "aspeed.smc.fmc",
208 .r_ce_ctrl
= R_CE_CTRL
,
210 .r_timings
= R_TIMINGS
,
211 .conf_enable_w0
= CONF_ENABLE_W0
,
213 .segments
= aspeed_segments_fmc
,
214 .flash_window_base
= ASPEED_SOC_FMC_FLASH_BASE
,
215 .flash_window_size
= 0x10000000,
217 .nregs
= ASPEED_SMC_R_MAX
,
219 .name
= "aspeed.smc.spi",
220 .r_conf
= R_SPI_CONF
,
222 .r_ctrl0
= R_SPI_CTRL0
,
223 .r_timings
= R_SPI_TIMINGS
,
224 .conf_enable_w0
= SPI_CONF_ENABLE_W0
,
226 .segments
= aspeed_segments_spi
,
227 .flash_window_base
= ASPEED_SOC_SPI_FLASH_BASE
,
228 .flash_window_size
= 0x10000000,
230 .nregs
= ASPEED_SMC_R_SPI_MAX
,
232 .name
= "aspeed.smc.ast2500-fmc",
234 .r_ce_ctrl
= R_CE_CTRL
,
236 .r_timings
= R_TIMINGS
,
237 .conf_enable_w0
= CONF_ENABLE_W0
,
239 .segments
= aspeed_segments_ast2500_fmc
,
240 .flash_window_base
= ASPEED_SOC_FMC_FLASH_BASE
,
241 .flash_window_size
= 0x10000000,
243 .nregs
= ASPEED_SMC_R_MAX
,
245 .name
= "aspeed.smc.ast2500-spi1",
247 .r_ce_ctrl
= R_CE_CTRL
,
249 .r_timings
= R_TIMINGS
,
250 .conf_enable_w0
= CONF_ENABLE_W0
,
252 .segments
= aspeed_segments_ast2500_spi1
,
253 .flash_window_base
= ASPEED_SOC_SPI_FLASH_BASE
,
254 .flash_window_size
= 0x8000000,
256 .nregs
= ASPEED_SMC_R_MAX
,
258 .name
= "aspeed.smc.ast2500-spi2",
260 .r_ce_ctrl
= R_CE_CTRL
,
262 .r_timings
= R_TIMINGS
,
263 .conf_enable_w0
= CONF_ENABLE_W0
,
265 .segments
= aspeed_segments_ast2500_spi2
,
266 .flash_window_base
= ASPEED_SOC_SPI2_FLASH_BASE
,
267 .flash_window_size
= 0x8000000,
269 .nregs
= ASPEED_SMC_R_MAX
,
274 * The Segment Register uses a 8MB unit to encode the start address
275 * and the end address of the mapping window of a flash SPI slave :
277 * | byte 1 | byte 2 | byte 3 | byte 4 |
278 * +--------+--------+--------+--------+
279 * | end | start | 0 | 0 |
282 static inline uint32_t aspeed_smc_segment_to_reg(const AspeedSegments
*seg
)
285 reg
|= ((seg
->addr
>> 23) & SEG_START_MASK
) << SEG_START_SHIFT
;
286 reg
|= (((seg
->addr
+ seg
->size
) >> 23) & SEG_END_MASK
) << SEG_END_SHIFT
;
290 static inline void aspeed_smc_reg_to_segment(uint32_t reg
, AspeedSegments
*seg
)
292 seg
->addr
= ((reg
>> SEG_START_SHIFT
) & SEG_START_MASK
) << 23;
293 seg
->size
= (((reg
>> SEG_END_SHIFT
) & SEG_END_MASK
) << 23) - seg
->addr
;
296 static bool aspeed_smc_flash_overlap(const AspeedSMCState
*s
,
297 const AspeedSegments
*new,
303 for (i
= 0; i
< s
->ctrl
->max_slaves
; i
++) {
308 aspeed_smc_reg_to_segment(s
->regs
[R_SEG_ADDR0
+ i
], &seg
);
310 if (new->addr
+ new->size
> seg
.addr
&&
311 new->addr
< seg
.addr
+ seg
.size
) {
312 qemu_log_mask(LOG_GUEST_ERROR
, "%s: new segment CS%d [ 0x%"
313 HWADDR_PRIx
" - 0x%"HWADDR_PRIx
" ] overlaps with "
314 "CS%d [ 0x%"HWADDR_PRIx
" - 0x%"HWADDR_PRIx
" ]\n",
315 s
->ctrl
->name
, cs
, new->addr
, new->addr
+ new->size
,
316 i
, seg
.addr
, seg
.addr
+ seg
.size
);
323 static void aspeed_smc_flash_set_segment(AspeedSMCState
*s
, int cs
,
326 AspeedSMCFlash
*fl
= &s
->flashes
[cs
];
329 aspeed_smc_reg_to_segment(new, &seg
);
331 /* The start address of CS0 is read-only */
332 if (cs
== 0 && seg
.addr
!= s
->ctrl
->flash_window_base
) {
333 qemu_log_mask(LOG_GUEST_ERROR
,
334 "%s: Tried to change CS0 start address to 0x%"
335 HWADDR_PRIx
"\n", s
->ctrl
->name
, seg
.addr
);
336 seg
.addr
= s
->ctrl
->flash_window_base
;
337 new = aspeed_smc_segment_to_reg(&seg
);
341 * The end address of the AST2500 spi controllers is also
344 if ((s
->ctrl
->segments
== aspeed_segments_ast2500_spi1
||
345 s
->ctrl
->segments
== aspeed_segments_ast2500_spi2
) &&
346 cs
== s
->ctrl
->max_slaves
&&
347 seg
.addr
+ seg
.size
!= s
->ctrl
->segments
[cs
].addr
+
348 s
->ctrl
->segments
[cs
].size
) {
349 qemu_log_mask(LOG_GUEST_ERROR
,
350 "%s: Tried to change CS%d end address to 0x%"
351 HWADDR_PRIx
"\n", s
->ctrl
->name
, cs
, seg
.addr
+ seg
.size
);
352 seg
.size
= s
->ctrl
->segments
[cs
].addr
+ s
->ctrl
->segments
[cs
].size
-
354 new = aspeed_smc_segment_to_reg(&seg
);
357 /* Keep the segment in the overall flash window */
358 if (seg
.addr
+ seg
.size
<= s
->ctrl
->flash_window_base
||
359 seg
.addr
> s
->ctrl
->flash_window_base
+ s
->ctrl
->flash_window_size
) {
360 qemu_log_mask(LOG_GUEST_ERROR
, "%s: new segment for CS%d is invalid : "
361 "[ 0x%"HWADDR_PRIx
" - 0x%"HWADDR_PRIx
" ]\n",
362 s
->ctrl
->name
, cs
, seg
.addr
, seg
.addr
+ seg
.size
);
366 /* Check start address vs. alignment */
367 if (seg
.size
&& !QEMU_IS_ALIGNED(seg
.addr
, seg
.size
)) {
368 qemu_log_mask(LOG_GUEST_ERROR
, "%s: new segment for CS%d is not "
369 "aligned : [ 0x%"HWADDR_PRIx
" - 0x%"HWADDR_PRIx
" ]\n",
370 s
->ctrl
->name
, cs
, seg
.addr
, seg
.addr
+ seg
.size
);
373 /* And segments should not overlap (in the specs) */
374 aspeed_smc_flash_overlap(s
, &seg
, cs
);
376 /* All should be fine now to move the region */
377 memory_region_transaction_begin();
378 memory_region_set_size(&fl
->mmio
, seg
.size
);
379 memory_region_set_address(&fl
->mmio
, seg
.addr
- s
->ctrl
->flash_window_base
);
380 memory_region_set_enabled(&fl
->mmio
, true);
381 memory_region_transaction_commit();
383 s
->regs
[R_SEG_ADDR0
+ cs
] = new;
386 static uint64_t aspeed_smc_flash_default_read(void *opaque
, hwaddr addr
,
389 qemu_log_mask(LOG_GUEST_ERROR
, "%s: To 0x%" HWADDR_PRIx
" of size %u"
390 PRIx64
"\n", __func__
, addr
, size
);
394 static void aspeed_smc_flash_default_write(void *opaque
, hwaddr addr
,
395 uint64_t data
, unsigned size
)
397 qemu_log_mask(LOG_GUEST_ERROR
, "%s: To 0x%" HWADDR_PRIx
" of size %u: 0x%"
398 PRIx64
"\n", __func__
, addr
, size
, data
);
401 static const MemoryRegionOps aspeed_smc_flash_default_ops
= {
402 .read
= aspeed_smc_flash_default_read
,
403 .write
= aspeed_smc_flash_default_write
,
404 .endianness
= DEVICE_LITTLE_ENDIAN
,
406 .min_access_size
= 1,
407 .max_access_size
= 4,
411 static inline int aspeed_smc_flash_mode(const AspeedSMCFlash
*fl
)
413 const AspeedSMCState
*s
= fl
->controller
;
415 return s
->regs
[s
->r_ctrl0
+ fl
->id
] & CTRL_CMD_MODE_MASK
;
418 static inline bool aspeed_smc_is_writable(const AspeedSMCFlash
*fl
)
420 const AspeedSMCState
*s
= fl
->controller
;
422 return s
->regs
[s
->r_conf
] & (1 << (s
->conf_enable_w0
+ fl
->id
));
425 static inline int aspeed_smc_flash_cmd(const AspeedSMCFlash
*fl
)
427 const AspeedSMCState
*s
= fl
->controller
;
428 int cmd
= (s
->regs
[s
->r_ctrl0
+ fl
->id
] >> CTRL_CMD_SHIFT
) & CTRL_CMD_MASK
;
430 /* In read mode, the default SPI command is READ (0x3). In other
431 * modes, the command should necessarily be defined */
432 if (aspeed_smc_flash_mode(fl
) == CTRL_READMODE
) {
437 qemu_log_mask(LOG_GUEST_ERROR
, "%s: no command defined for mode %d\n",
438 __func__
, aspeed_smc_flash_mode(fl
));
444 static inline int aspeed_smc_flash_is_4byte(const AspeedSMCFlash
*fl
)
446 const AspeedSMCState
*s
= fl
->controller
;
448 if (s
->ctrl
->segments
== aspeed_segments_spi
) {
449 return s
->regs
[s
->r_ctrl0
] & CTRL_AST2400_SPI_4BYTE
;
451 return s
->regs
[s
->r_ce_ctrl
] & (1 << (CTRL_EXTENDED0
+ fl
->id
));
455 static inline bool aspeed_smc_is_ce_stop_active(const AspeedSMCFlash
*fl
)
457 const AspeedSMCState
*s
= fl
->controller
;
459 return s
->regs
[s
->r_ctrl0
+ fl
->id
] & CTRL_CE_STOP_ACTIVE
;
462 static void aspeed_smc_flash_select(AspeedSMCFlash
*fl
)
464 AspeedSMCState
*s
= fl
->controller
;
466 s
->regs
[s
->r_ctrl0
+ fl
->id
] &= ~CTRL_CE_STOP_ACTIVE
;
467 qemu_set_irq(s
->cs_lines
[fl
->id
], aspeed_smc_is_ce_stop_active(fl
));
470 static void aspeed_smc_flash_unselect(AspeedSMCFlash
*fl
)
472 AspeedSMCState
*s
= fl
->controller
;
474 s
->regs
[s
->r_ctrl0
+ fl
->id
] |= CTRL_CE_STOP_ACTIVE
;
475 qemu_set_irq(s
->cs_lines
[fl
->id
], aspeed_smc_is_ce_stop_active(fl
));
478 static uint32_t aspeed_smc_check_segment_addr(const AspeedSMCFlash
*fl
,
481 const AspeedSMCState
*s
= fl
->controller
;
484 aspeed_smc_reg_to_segment(s
->regs
[R_SEG_ADDR0
+ fl
->id
], &seg
);
485 if ((addr
% seg
.size
) != addr
) {
486 qemu_log_mask(LOG_GUEST_ERROR
,
487 "%s: invalid address 0x%08x for CS%d segment : "
488 "[ 0x%"HWADDR_PRIx
" - 0x%"HWADDR_PRIx
" ]\n",
489 s
->ctrl
->name
, addr
, fl
->id
, seg
.addr
,
490 seg
.addr
+ seg
.size
);
497 static int aspeed_smc_flash_dummies(const AspeedSMCFlash
*fl
)
499 const AspeedSMCState
*s
= fl
->controller
;
500 uint32_t r_ctrl0
= s
->regs
[s
->r_ctrl0
+ fl
->id
];
501 uint32_t dummy_high
= (r_ctrl0
>> CTRL_DUMMY_HIGH_SHIFT
) & 0x1;
502 uint32_t dummy_low
= (r_ctrl0
>> CTRL_DUMMY_LOW_SHIFT
) & 0x3;
503 uint32_t dummies
= ((dummy_high
<< 2) | dummy_low
) * 8;
505 if (r_ctrl0
& CTRL_IO_DUAL_ADDR_DATA
) {
512 static void aspeed_smc_flash_setup(AspeedSMCFlash
*fl
, uint32_t addr
)
514 const AspeedSMCState
*s
= fl
->controller
;
515 uint8_t cmd
= aspeed_smc_flash_cmd(fl
);
518 /* Flash access can not exceed CS segment */
519 addr
= aspeed_smc_check_segment_addr(fl
, addr
);
521 ssi_transfer(s
->spi
, cmd
);
523 if (aspeed_smc_flash_is_4byte(fl
)) {
524 ssi_transfer(s
->spi
, (addr
>> 24) & 0xff);
526 ssi_transfer(s
->spi
, (addr
>> 16) & 0xff);
527 ssi_transfer(s
->spi
, (addr
>> 8) & 0xff);
528 ssi_transfer(s
->spi
, (addr
& 0xff));
531 * Use fake transfers to model dummy bytes. The value should
532 * be configured to some non-zero value in fast read mode and
533 * zero in read mode. But, as the HW allows inconsistent
534 * settings, let's check for fast read mode.
536 if (aspeed_smc_flash_mode(fl
) == CTRL_FREADMODE
) {
537 for (i
= 0; i
< aspeed_smc_flash_dummies(fl
); i
++) {
538 ssi_transfer(fl
->controller
->spi
, s
->regs
[R_DUMMY_DATA
] & 0xff);
543 static uint64_t aspeed_smc_flash_read(void *opaque
, hwaddr addr
, unsigned size
)
545 AspeedSMCFlash
*fl
= opaque
;
546 AspeedSMCState
*s
= fl
->controller
;
550 switch (aspeed_smc_flash_mode(fl
)) {
552 for (i
= 0; i
< size
; i
++) {
553 ret
|= ssi_transfer(s
->spi
, 0x0) << (8 * i
);
558 aspeed_smc_flash_select(fl
);
559 aspeed_smc_flash_setup(fl
, addr
);
561 for (i
= 0; i
< size
; i
++) {
562 ret
|= ssi_transfer(s
->spi
, 0x0) << (8 * i
);
565 aspeed_smc_flash_unselect(fl
);
568 qemu_log_mask(LOG_GUEST_ERROR
, "%s: invalid flash mode %d\n",
569 __func__
, aspeed_smc_flash_mode(fl
));
576 * TODO (clg@kaod.org): stolen from xilinx_spips.c. Should move to a
577 * common include header.
580 READ
= 0x3, READ_4
= 0x13,
581 FAST_READ
= 0xb, FAST_READ_4
= 0x0c,
582 DOR
= 0x3b, DOR_4
= 0x3c,
583 QOR
= 0x6b, QOR_4
= 0x6c,
584 DIOR
= 0xbb, DIOR_4
= 0xbc,
585 QIOR
= 0xeb, QIOR_4
= 0xec,
587 PP
= 0x2, PP_4
= 0x12,
589 QPP
= 0x32, QPP_4
= 0x34,
592 static int aspeed_smc_num_dummies(uint8_t command
)
594 switch (command
) { /* check for dummies */
595 case READ
: /* no dummy bytes/cycles */
621 static bool aspeed_smc_do_snoop(AspeedSMCFlash
*fl
, uint64_t data
,
624 AspeedSMCState
*s
= fl
->controller
;
625 uint8_t addr_width
= aspeed_smc_flash_is_4byte(fl
) ? 4 : 3;
627 if (s
->snoop_index
== SNOOP_OFF
) {
628 return false; /* Do nothing */
630 } else if (s
->snoop_index
== SNOOP_START
) {
631 uint8_t cmd
= data
& 0xff;
632 int ndummies
= aspeed_smc_num_dummies(cmd
);
635 * No dummy cycles are expected with the current command. Turn
636 * off snooping and let the transfer proceed normally.
639 s
->snoop_index
= SNOOP_OFF
;
643 s
->snoop_dummies
= ndummies
* 8;
645 } else if (s
->snoop_index
>= addr_width
+ 1) {
647 /* The SPI transfer has reached the dummy cycles sequence */
648 for (; s
->snoop_dummies
; s
->snoop_dummies
--) {
649 ssi_transfer(s
->spi
, s
->regs
[R_DUMMY_DATA
] & 0xff);
652 /* If no more dummy cycles are expected, turn off snooping */
653 if (!s
->snoop_dummies
) {
654 s
->snoop_index
= SNOOP_OFF
;
656 s
->snoop_index
+= size
;
660 * Dummy cycles have been faked already. Ignore the current
666 s
->snoop_index
+= size
;
670 static void aspeed_smc_flash_write(void *opaque
, hwaddr addr
, uint64_t data
,
673 AspeedSMCFlash
*fl
= opaque
;
674 AspeedSMCState
*s
= fl
->controller
;
677 if (!aspeed_smc_is_writable(fl
)) {
678 qemu_log_mask(LOG_GUEST_ERROR
, "%s: flash is not writable at 0x%"
679 HWADDR_PRIx
"\n", __func__
, addr
);
683 switch (aspeed_smc_flash_mode(fl
)) {
685 if (aspeed_smc_do_snoop(fl
, data
, size
)) {
689 for (i
= 0; i
< size
; i
++) {
690 ssi_transfer(s
->spi
, (data
>> (8 * i
)) & 0xff);
694 aspeed_smc_flash_select(fl
);
695 aspeed_smc_flash_setup(fl
, addr
);
697 for (i
= 0; i
< size
; i
++) {
698 ssi_transfer(s
->spi
, (data
>> (8 * i
)) & 0xff);
701 aspeed_smc_flash_unselect(fl
);
704 qemu_log_mask(LOG_GUEST_ERROR
, "%s: invalid flash mode %d\n",
705 __func__
, aspeed_smc_flash_mode(fl
));
709 static const MemoryRegionOps aspeed_smc_flash_ops
= {
710 .read
= aspeed_smc_flash_read
,
711 .write
= aspeed_smc_flash_write
,
712 .endianness
= DEVICE_LITTLE_ENDIAN
,
714 .min_access_size
= 1,
715 .max_access_size
= 4,
719 static void aspeed_smc_flash_update_cs(AspeedSMCFlash
*fl
)
721 AspeedSMCState
*s
= fl
->controller
;
723 s
->snoop_index
= aspeed_smc_is_ce_stop_active(fl
) ? SNOOP_OFF
: SNOOP_START
;
725 qemu_set_irq(s
->cs_lines
[fl
->id
], aspeed_smc_is_ce_stop_active(fl
));
728 static void aspeed_smc_reset(DeviceState
*d
)
730 AspeedSMCState
*s
= ASPEED_SMC(d
);
733 memset(s
->regs
, 0, sizeof s
->regs
);
735 /* Pretend DMA is done (u-boot initialization) */
736 s
->regs
[R_INTR_CTRL
] = INTR_CTRL_DMA_STATUS
;
738 /* Unselect all slaves */
739 for (i
= 0; i
< s
->num_cs
; ++i
) {
740 s
->regs
[s
->r_ctrl0
+ i
] |= CTRL_CE_STOP_ACTIVE
;
741 qemu_set_irq(s
->cs_lines
[i
], true);
744 /* setup default segment register values for all */
745 for (i
= 0; i
< s
->ctrl
->max_slaves
; ++i
) {
746 s
->regs
[R_SEG_ADDR0
+ i
] =
747 aspeed_smc_segment_to_reg(&s
->ctrl
->segments
[i
]);
750 /* HW strapping flash type for FMC controllers */
751 if (s
->ctrl
->segments
== aspeed_segments_ast2500_fmc
) {
752 /* flash type is fixed to SPI for CE0 and CE1 */
753 s
->regs
[s
->r_conf
] |= (CONF_FLASH_TYPE_SPI
<< CONF_FLASH_TYPE0
);
754 s
->regs
[s
->r_conf
] |= (CONF_FLASH_TYPE_SPI
<< CONF_FLASH_TYPE1
);
757 /* HW strapping for AST2400 FMC controllers (SCU70). Let's use the
758 * configuration of the palmetto-bmc machine */
759 if (s
->ctrl
->segments
== aspeed_segments_fmc
) {
760 s
->regs
[s
->r_conf
] |= (CONF_FLASH_TYPE_SPI
<< CONF_FLASH_TYPE0
);
763 s
->snoop_index
= SNOOP_OFF
;
764 s
->snoop_dummies
= 0;
767 static uint64_t aspeed_smc_read(void *opaque
, hwaddr addr
, unsigned int size
)
769 AspeedSMCState
*s
= ASPEED_SMC(opaque
);
773 if (addr
== s
->r_conf
||
774 addr
== s
->r_timings
||
775 addr
== s
->r_ce_ctrl
||
776 addr
== R_INTR_CTRL
||
777 addr
== R_DUMMY_DATA
||
778 (addr
>= R_SEG_ADDR0
&& addr
< R_SEG_ADDR0
+ s
->ctrl
->max_slaves
) ||
779 (addr
>= s
->r_ctrl0
&& addr
< s
->r_ctrl0
+ s
->ctrl
->max_slaves
)) {
780 return s
->regs
[addr
];
782 qemu_log_mask(LOG_UNIMP
, "%s: not implemented: 0x%" HWADDR_PRIx
"\n",
788 static void aspeed_smc_write(void *opaque
, hwaddr addr
, uint64_t data
,
791 AspeedSMCState
*s
= ASPEED_SMC(opaque
);
792 uint32_t value
= data
;
796 if (addr
== s
->r_conf
||
797 addr
== s
->r_timings
||
798 addr
== s
->r_ce_ctrl
) {
799 s
->regs
[addr
] = value
;
800 } else if (addr
>= s
->r_ctrl0
&& addr
< s
->r_ctrl0
+ s
->num_cs
) {
801 int cs
= addr
- s
->r_ctrl0
;
802 s
->regs
[addr
] = value
;
803 aspeed_smc_flash_update_cs(&s
->flashes
[cs
]);
804 } else if (addr
>= R_SEG_ADDR0
&&
805 addr
< R_SEG_ADDR0
+ s
->ctrl
->max_slaves
) {
806 int cs
= addr
- R_SEG_ADDR0
;
808 if (value
!= s
->regs
[R_SEG_ADDR0
+ cs
]) {
809 aspeed_smc_flash_set_segment(s
, cs
, value
);
811 } else if (addr
== R_DUMMY_DATA
) {
812 s
->regs
[addr
] = value
& 0xff;
814 qemu_log_mask(LOG_UNIMP
, "%s: not implemented: 0x%" HWADDR_PRIx
"\n",
820 static const MemoryRegionOps aspeed_smc_ops
= {
821 .read
= aspeed_smc_read
,
822 .write
= aspeed_smc_write
,
823 .endianness
= DEVICE_LITTLE_ENDIAN
,
824 .valid
.unaligned
= true,
827 static void aspeed_smc_realize(DeviceState
*dev
, Error
**errp
)
829 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
830 AspeedSMCState
*s
= ASPEED_SMC(dev
);
831 AspeedSMCClass
*mc
= ASPEED_SMC_GET_CLASS(s
);
838 /* keep a copy under AspeedSMCState to speed up accesses */
839 s
->r_conf
= s
->ctrl
->r_conf
;
840 s
->r_ce_ctrl
= s
->ctrl
->r_ce_ctrl
;
841 s
->r_ctrl0
= s
->ctrl
->r_ctrl0
;
842 s
->r_timings
= s
->ctrl
->r_timings
;
843 s
->conf_enable_w0
= s
->ctrl
->conf_enable_w0
;
845 /* Enforce some real HW limits */
846 if (s
->num_cs
> s
->ctrl
->max_slaves
) {
847 qemu_log_mask(LOG_GUEST_ERROR
, "%s: num_cs cannot exceed: %d\n",
848 __func__
, s
->ctrl
->max_slaves
);
849 s
->num_cs
= s
->ctrl
->max_slaves
;
852 s
->spi
= ssi_create_bus(dev
, "spi");
854 /* Setup cs_lines for slaves */
855 sysbus_init_irq(sbd
, &s
->irq
);
856 s
->cs_lines
= g_new0(qemu_irq
, s
->num_cs
);
857 ssi_auto_connect_slaves(dev
, s
->cs_lines
, s
->spi
);
859 for (i
= 0; i
< s
->num_cs
; ++i
) {
860 sysbus_init_irq(sbd
, &s
->cs_lines
[i
]);
863 /* The memory region for the controller registers */
864 memory_region_init_io(&s
->mmio
, OBJECT(s
), &aspeed_smc_ops
, s
,
865 s
->ctrl
->name
, s
->ctrl
->nregs
* 4);
866 sysbus_init_mmio(sbd
, &s
->mmio
);
869 * The container memory region representing the address space
870 * window in which the flash modules are mapped. The size and
871 * address depends on the SoC model and controller type.
873 snprintf(name
, sizeof(name
), "%s.flash", s
->ctrl
->name
);
875 memory_region_init_io(&s
->mmio_flash
, OBJECT(s
),
876 &aspeed_smc_flash_default_ops
, s
, name
,
877 s
->ctrl
->flash_window_size
);
878 sysbus_init_mmio(sbd
, &s
->mmio_flash
);
880 s
->flashes
= g_new0(AspeedSMCFlash
, s
->ctrl
->max_slaves
);
883 * Let's create a sub memory region for each possible slave. All
884 * have a configurable memory segment in the overall flash mapping
885 * window of the controller but, there is not necessarily a flash
886 * module behind to handle the memory accesses. This depends on
887 * the board configuration.
889 for (i
= 0; i
< s
->ctrl
->max_slaves
; ++i
) {
890 AspeedSMCFlash
*fl
= &s
->flashes
[i
];
892 snprintf(name
, sizeof(name
), "%s.%d", s
->ctrl
->name
, i
);
896 fl
->size
= s
->ctrl
->segments
[i
].size
;
897 memory_region_init_io(&fl
->mmio
, OBJECT(s
), &aspeed_smc_flash_ops
,
899 memory_region_add_subregion(&s
->mmio_flash
, offset
, &fl
->mmio
);
904 static const VMStateDescription vmstate_aspeed_smc
= {
905 .name
= "aspeed.smc",
907 .minimum_version_id
= 2,
908 .fields
= (VMStateField
[]) {
909 VMSTATE_UINT32_ARRAY(regs
, AspeedSMCState
, ASPEED_SMC_R_MAX
),
910 VMSTATE_UINT8(snoop_index
, AspeedSMCState
),
911 VMSTATE_UINT8(snoop_dummies
, AspeedSMCState
),
912 VMSTATE_END_OF_LIST()
916 static Property aspeed_smc_properties
[] = {
917 DEFINE_PROP_UINT32("num-cs", AspeedSMCState
, num_cs
, 1),
918 DEFINE_PROP_UINT64("sdram-base", AspeedSMCState
, sdram_base
, 0),
919 DEFINE_PROP_END_OF_LIST(),
922 static void aspeed_smc_class_init(ObjectClass
*klass
, void *data
)
924 DeviceClass
*dc
= DEVICE_CLASS(klass
);
925 AspeedSMCClass
*mc
= ASPEED_SMC_CLASS(klass
);
927 dc
->realize
= aspeed_smc_realize
;
928 dc
->reset
= aspeed_smc_reset
;
929 dc
->props
= aspeed_smc_properties
;
930 dc
->vmsd
= &vmstate_aspeed_smc
;
934 static const TypeInfo aspeed_smc_info
= {
935 .name
= TYPE_ASPEED_SMC
,
936 .parent
= TYPE_SYS_BUS_DEVICE
,
937 .instance_size
= sizeof(AspeedSMCState
),
938 .class_size
= sizeof(AspeedSMCClass
),
942 static void aspeed_smc_register_types(void)
946 type_register_static(&aspeed_smc_info
);
947 for (i
= 0; i
< ARRAY_SIZE(controllers
); ++i
) {
949 .name
= controllers
[i
].name
,
950 .parent
= TYPE_ASPEED_SMC
,
951 .class_init
= aspeed_smc_class_init
,
952 .class_data
= (void *)&controllers
[i
],
958 type_init(aspeed_smc_register_types
)