hw/xtensa/xtfpga.c

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "qemu/units.h"
  30 #include "qapi/error.h"
  31 #include "cpu.h"
  32 #include "sysemu/sysemu.h"
  33 #include "hw/boards.h"
  34 #include "hw/loader.h"
  35 #include "elf.h"
  36 #include "exec/memory.h"
  37 #include "exec/address-spaces.h"
  38 #include "hw/char/serial.h"
  39 #include "net/net.h"
  40 #include "hw/sysbus.h"
  41 #include "hw/block/flash.h"
  42 #include "chardev/char.h"
  43 #include "sysemu/device_tree.h"
  44 #include "qemu/error-report.h"
  45 #include "qemu/option.h"
  46 #include "bootparam.h"
  47 #include "xtensa_memory.h"
  48 #include "hw/xtensa/mx_pic.h"
  49
  50 typedef struct XtfpgaFlashDesc {
  51     hwaddr base;
  52     size_t size;
  53     size_t boot_base;
  54     size_t sector_size;
  55 } XtfpgaFlashDesc;
  56
  57 typedef struct XtfpgaBoardDesc {
  58     const XtfpgaFlashDesc *flash;
  59     size_t sram_size;
  60     const hwaddr *io;
  61 } XtfpgaBoardDesc;
  62
  63 typedef struct XtfpgaFpgaState {
  64     MemoryRegion iomem;
  65     uint32_t freq;
  66     uint32_t leds;
  67     uint32_t switches;
  68 } XtfpgaFpgaState;
  69
  70 static void xtfpga_fpga_reset(void *opaque)
  71 {
  72     XtfpgaFpgaState *s = opaque;
  73
  74     s->leds = 0;
  75     s->switches = 0;
  76 }
  77
  78 static uint64_t xtfpga_fpga_read(void *opaque, hwaddr addr,
  79         unsigned size)
  80 {
  81     XtfpgaFpgaState *s = opaque;
  82
  83     switch (addr) {
  84     case 0x0: /*build date code*/
  85         return 0x09272011;
  86
  87     case 0x4: /*processor clock frequency, Hz*/
  88         return s->freq;
  89
  90     case 0x8: /*LEDs (off = 0, on = 1)*/
  91         return s->leds;
  92
  93     case 0xc: /*DIP switches (off = 0, on = 1)*/
  94         return s->switches;
  95     }
  96     return 0;
  97 }
  98
  99 static void xtfpga_fpga_write(void *opaque, hwaddr addr,
 100         uint64_t val, unsigned size)
 101 {
 102     XtfpgaFpgaState *s = opaque;
 103
 104     switch (addr) {
 105     case 0x8: /*LEDs (off = 0, on = 1)*/
 106         s->leds = val;
 107         break;
 108
 109     case 0x10: /*board reset*/
 110         if (val == 0xdead) {
 111             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 112         }
 113         break;
 114     }
 115 }
 116
 117 static const MemoryRegionOps xtfpga_fpga_ops = {
 118     .read = xtfpga_fpga_read,
 119     .write = xtfpga_fpga_write,
 120     .endianness = DEVICE_NATIVE_ENDIAN,
 121 };
 122
 123 static XtfpgaFpgaState *xtfpga_fpga_init(MemoryRegion *address_space,
 124                                          hwaddr base, uint32_t freq)
 125 {
 126     XtfpgaFpgaState *s = g_malloc(sizeof(XtfpgaFpgaState));
 127
 128     memory_region_init_io(&s->iomem, NULL, &xtfpga_fpga_ops, s,
 129                           "xtfpga.fpga", 0x10000);
 130     memory_region_add_subregion(address_space, base, &s->iomem);
 131     s->freq = freq;
 132     xtfpga_fpga_reset(s);
 133     qemu_register_reset(xtfpga_fpga_reset, s);
 134     return s;
 135 }
 136
 137 static void xtfpga_net_init(MemoryRegion *address_space,
 138         hwaddr base,
 139         hwaddr descriptors,
 140         hwaddr buffers,
 141         qemu_irq irq, NICInfo *nd)
 142 {
 143     DeviceState *dev;
 144     SysBusDevice *s;
 145     MemoryRegion *ram;
 146
 147     dev = qdev_create(NULL, "open_eth");
 148     qdev_set_nic_properties(dev, nd);
 149     qdev_init_nofail(dev);
 150
 151     s = SYS_BUS_DEVICE(dev);
 152     sysbus_connect_irq(s, 0, irq);
 153     memory_region_add_subregion(address_space, base,
 154             sysbus_mmio_get_region(s, 0));
 155     memory_region_add_subregion(address_space, descriptors,
 156             sysbus_mmio_get_region(s, 1));
 157
 158     ram = g_malloc(sizeof(*ram));
 159     memory_region_init_ram_nomigrate(ram, OBJECT(s), "open_eth.ram", 16 * KiB,
 160                            &error_fatal);
 161     vmstate_register_ram_global(ram);
 162     memory_region_add_subregion(address_space, buffers, ram);
 163 }
 164
 165 static PFlashCFI01 *xtfpga_flash_init(MemoryRegion *address_space,
 166                                       const XtfpgaBoardDesc *board,
 167                                       DriveInfo *dinfo, int be)
 168 {
 169     SysBusDevice *s;
 170     DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01);
 171
 172     qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
 173                         &error_abort);
 174     qdev_prop_set_uint32(dev, "num-blocks",
 175                          board->flash->size / board->flash->sector_size);
 176     qdev_prop_set_uint64(dev, "sector-length", board->flash->sector_size);
 177     qdev_prop_set_uint8(dev, "width", 2);
 178     qdev_prop_set_bit(dev, "big-endian", be);
 179     qdev_prop_set_string(dev, "name", "xtfpga.io.flash");
 180     qdev_init_nofail(dev);
 181     s = SYS_BUS_DEVICE(dev);
 182     memory_region_add_subregion(address_space, board->flash->base,
 183                                 sysbus_mmio_get_region(s, 0));
 184     return PFLASH_CFI01(dev);
 185 }
 186
 187 static uint64_t translate_phys_addr(void *opaque, uint64_t addr)
 188 {
 189     XtensaCPU *cpu = opaque;
 190
 191     return cpu_get_phys_page_debug(CPU(cpu), addr);
 192 }
 193
 194 static void xtfpga_reset(void *opaque)
 195 {
 196     XtensaCPU *cpu = opaque;
 197
 198     cpu_reset(CPU(cpu));
 199 }
 200
 201 static uint64_t xtfpga_io_read(void *opaque, hwaddr addr,
 202         unsigned size)
 203 {
 204     return 0;
 205 }
 206
 207 static void xtfpga_io_write(void *opaque, hwaddr addr,
 208         uint64_t val, unsigned size)
 209 {
 210 }
 211
 212 static const MemoryRegionOps xtfpga_io_ops = {
 213     .read = xtfpga_io_read,
 214     .write = xtfpga_io_write,
 215     .endianness = DEVICE_NATIVE_ENDIAN,
 216 };
 217
 218 static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine)
 219 {
 220 #ifdef TARGET_WORDS_BIGENDIAN
 221     int be = 1;
 222 #else
 223     int be = 0;
 224 #endif
 225     MemoryRegion *system_memory = get_system_memory();
 226     XtensaCPU *cpu = NULL;
 227     CPUXtensaState *env = NULL;
 228     MemoryRegion *system_io;
 229     XtensaMxPic *mx_pic = NULL;
 230     qemu_irq *extints;
 231     DriveInfo *dinfo;
 232     PFlashCFI01 *flash = NULL;
 233     QemuOpts *machine_opts = qemu_get_machine_opts();
 234     const char *kernel_filename = qemu_opt_get(machine_opts, "kernel");
 235     const char *kernel_cmdline = qemu_opt_get(machine_opts, "append");
 236     const char *dtb_filename = qemu_opt_get(machine_opts, "dtb");
 237     const char *initrd_filename = qemu_opt_get(machine_opts, "initrd");
 238     const unsigned system_io_size = 224 * MiB;
 239     uint32_t freq = 10000000;
 240     int n;
 241
 242     if (smp_cpus > 1) {
 243         mx_pic = xtensa_mx_pic_init(31);
 244         qemu_register_reset(xtensa_mx_pic_reset, mx_pic);
 245     }
 246     for (n = 0; n < smp_cpus; n++) {
 247         CPUXtensaState *cenv = NULL;
 248
 249         cpu = XTENSA_CPU(cpu_create(machine->cpu_type));
 250         cenv = &cpu->env;
 251         if (!env) {
 252             env = cenv;
 253             freq = env->config->clock_freq_khz * 1000;
 254         }
 255
 256         if (mx_pic) {
 257             MemoryRegion *mx_eri;
 258
 259             mx_eri = xtensa_mx_pic_register_cpu(mx_pic,
 260                                                 xtensa_get_extints(cenv),
 261                                                 xtensa_get_runstall(cenv));
 262             memory_region_add_subregion(xtensa_get_er_region(cenv),
 263                                         0, mx_eri);
 264         }
 265         cenv->sregs[PRID] = n;
 266         xtensa_select_static_vectors(cenv, n != 0);
 267         qemu_register_reset(xtfpga_reset, cpu);
 268         /* Need MMU initialized prior to ELF loading,
 269          * so that ELF gets loaded into virtual addresses
 270          */
 271         cpu_reset(CPU(cpu));
 272     }
 273     if (smp_cpus > 1) {
 274         extints = xtensa_mx_pic_get_extints(mx_pic);
 275     } else {
 276         extints = xtensa_get_extints(env);
 277     }
 278
 279     if (env) {
 280         XtensaMemory sysram = env->config->sysram;
 281
 282         sysram.location[0].size = machine->ram_size;
 283         xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom",
 284                                      system_memory);
 285         xtensa_create_memory_regions(&env->config->instram, "xtensa.instram",
 286                                      system_memory);
 287         xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom",
 288                                      system_memory);
 289         xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram",
 290                                      system_memory);
 291         xtensa_create_memory_regions(&sysram, "xtensa.sysram",
 292                                      system_memory);
 293     }
 294
 295     system_io = g_malloc(sizeof(*system_io));
 296     memory_region_init_io(system_io, NULL, &xtfpga_io_ops, NULL, "xtfpga.io",
 297                           system_io_size);
 298     memory_region_add_subregion(system_memory, board->io[0], system_io);
 299     if (board->io[1]) {
 300         MemoryRegion *io = g_malloc(sizeof(*io));
 301
 302         memory_region_init_alias(io, NULL, "xtfpga.io.cached",
 303                                  system_io, 0, system_io_size);
 304         memory_region_add_subregion(system_memory, board->io[1], io);
 305     }
 306     xtfpga_fpga_init(system_io, 0x0d020000, freq);
 307     if (nd_table[0].used) {
 308         xtfpga_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000,
 309                         extints[1], nd_table);
 310     }
 311
 312     serial_mm_init(system_io, 0x0d050020, 2, extints[0],
 313                    115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
 314
 315     dinfo = drive_get(IF_PFLASH, 0, 0);
 316     if (dinfo) {
 317         flash = xtfpga_flash_init(system_io, board, dinfo, be);
 318     }
 319
 320     /* Use presence of kernel file name as 'boot from SRAM' switch. */
 321     if (kernel_filename) {
 322         uint32_t entry_point = env->pc;
 323         size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */
 324         uint32_t tagptr = env->config->sysrom.location[0].addr +
 325             board->sram_size;
 326         uint32_t cur_tagptr;
 327         BpMemInfo memory_location = {
 328             .type = tswap32(MEMORY_TYPE_CONVENTIONAL),
 329             .start = tswap32(env->config->sysram.location[0].addr),
 330             .end = tswap32(env->config->sysram.location[0].addr +
 331                            machine->ram_size),
 332         };
 333         uint32_t lowmem_end = machine->ram_size < 0x08000000 ?
 334             machine->ram_size : 0x08000000;
 335         uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096);
 336
 337         lowmem_end += env->config->sysram.location[0].addr;
 338         cur_lowmem += env->config->sysram.location[0].addr;
 339
 340         xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom",
 341                                      system_memory);
 342
 343         if (kernel_cmdline) {
 344             bp_size += get_tag_size(strlen(kernel_cmdline) + 1);
 345         }
 346         if (dtb_filename) {
 347             bp_size += get_tag_size(sizeof(uint32_t));
 348         }
 349         if (initrd_filename) {
 350             bp_size += get_tag_size(sizeof(BpMemInfo));
 351         }
 352
 353         /* Put kernel bootparameters to the end of that SRAM */
 354         tagptr = (tagptr - bp_size) & ~0xff;
 355         cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL);
 356         cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY,
 357                              sizeof(memory_location), &memory_location);
 358
 359         if (kernel_cmdline) {
 360             cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE,
 361                                  strlen(kernel_cmdline) + 1, kernel_cmdline);
 362         }
 363 #ifdef CONFIG_FDT
 364         if (dtb_filename) {
 365             int fdt_size;
 366             void *fdt = load_device_tree(dtb_filename, &fdt_size);
 367             uint32_t dtb_addr = tswap32(cur_lowmem);
 368
 369             if (!fdt) {
 370                 error_report("could not load DTB '%s'", dtb_filename);
 371                 exit(EXIT_FAILURE);
 372             }
 373
 374             cpu_physical_memory_write(cur_lowmem, fdt, fdt_size);
 375             cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT,
 376                                  sizeof(dtb_addr), &dtb_addr);
 377             cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4 * KiB);
 378         }
 379 #else
 380         if (dtb_filename) {
 381             error_report("could not load DTB '%s': "
 382                          "FDT support is not configured in QEMU",
 383                          dtb_filename);
 384             exit(EXIT_FAILURE);
 385         }
 386 #endif
 387         if (initrd_filename) {
 388             BpMemInfo initrd_location = { 0 };
 389             int initrd_size = load_ramdisk(initrd_filename, cur_lowmem,
 390                                            lowmem_end - cur_lowmem);
 391
 392             if (initrd_size < 0) {
 393                 initrd_size = load_image_targphys(initrd_filename,
 394                                                   cur_lowmem,
 395                                                   lowmem_end - cur_lowmem);
 396             }
 397             if (initrd_size < 0) {
 398                 error_report("could not load initrd '%s'", initrd_filename);
 399                 exit(EXIT_FAILURE);
 400             }
 401             initrd_location.start = tswap32(cur_lowmem);
 402             initrd_location.end = tswap32(cur_lowmem + initrd_size);
 403             cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD,
 404                                  sizeof(initrd_location), &initrd_location);
 405             cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4 * KiB);
 406         }
 407         cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL);
 408         env->regs[2] = tagptr;
 409
 410         uint64_t elf_entry;
 411         uint64_t elf_lowaddr;
 412         int success = load_elf(kernel_filename, NULL, translate_phys_addr, cpu,
 413                 &elf_entry, &elf_lowaddr, NULL, be, EM_XTENSA, 0, 0);
 414         if (success > 0) {
 415             entry_point = elf_entry;
 416         } else {
 417             hwaddr ep;
 418             int is_linux;
 419             success = load_uimage(kernel_filename, &ep, NULL, &is_linux,
 420                                   translate_phys_addr, cpu);
 421             if (success > 0 && is_linux) {
 422                 entry_point = ep;
 423             } else {
 424                 error_report("could not load kernel '%s'",
 425                              kernel_filename);
 426                 exit(EXIT_FAILURE);
 427             }
 428         }
 429         if (entry_point != env->pc) {
 430             uint8_t boot[] = {
 431 #ifdef TARGET_WORDS_BIGENDIAN
 432                 0x60, 0x00, 0x08,       /* j    1f */
 433                 0x00,                   /* .literal_position */
 434                 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
 435                 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */
 436                                         /* 1: */
 437                 0x10, 0xff, 0xfe,       /* l32r a0, entry_pc */
 438                 0x12, 0xff, 0xfe,       /* l32r a2, entry_a2 */
 439                 0x0a, 0x00, 0x00,       /* jx   a0 */
 440 #else
 441                 0x06, 0x02, 0x00,       /* j    1f */
 442                 0x00,                   /* .literal_position */
 443                 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
 444                 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */
 445                                         /* 1: */
 446                 0x01, 0xfe, 0xff,       /* l32r a0, entry_pc */
 447                 0x21, 0xfe, 0xff,       /* l32r a2, entry_a2 */
 448                 0xa0, 0x00, 0x00,       /* jx   a0 */
 449 #endif
 450             };
 451             uint32_t entry_pc = tswap32(entry_point);
 452             uint32_t entry_a2 = tswap32(tagptr);
 453
 454             memcpy(boot + 4, &entry_pc, sizeof(entry_pc));
 455             memcpy(boot + 8, &entry_a2, sizeof(entry_a2));
 456             cpu_physical_memory_write(env->pc, boot, sizeof(boot));
 457         }
 458     } else {
 459         if (flash) {
 460             MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash);
 461             MemoryRegion *flash_io = g_malloc(sizeof(*flash_io));
 462             uint32_t size = env->config->sysrom.location[0].size;
 463
 464             if (board->flash->size - board->flash->boot_base < size) {
 465                 size = board->flash->size - board->flash->boot_base;
 466             }
 467
 468             memory_region_init_alias(flash_io, NULL, "xtfpga.flash",
 469                                      flash_mr, board->flash->boot_base, size);
 470             memory_region_add_subregion(system_memory,
 471                                         env->config->sysrom.location[0].addr,
 472                                         flash_io);
 473         } else {
 474             xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom",
 475                                          system_memory);
 476         }
 477     }
 478 }
 479
 480 #define XTFPGA_MMU_RESERVED_MEMORY_SIZE (128 * MiB)
 481
 482 static const hwaddr xtfpga_mmu_io[2] = {
 483     0xf0000000,
 484 };
 485
 486 static const hwaddr xtfpga_nommu_io[2] = {
 487     0x90000000,
 488     0x70000000,
 489 };
 490
 491 static const XtfpgaFlashDesc lx60_flash = {
 492     .base = 0x08000000,
 493     .size = 0x00400000,
 494     .sector_size = 0x10000,
 495 };
 496
 497 static void xtfpga_lx60_init(MachineState *machine)
 498 {
 499     static const XtfpgaBoardDesc lx60_board = {
 500         .flash = &lx60_flash,
 501         .sram_size = 0x20000,
 502         .io = xtfpga_mmu_io,
 503     };
 504     xtfpga_init(&lx60_board, machine);
 505 }
 506
 507 static void xtfpga_lx60_nommu_init(MachineState *machine)
 508 {
 509     static const XtfpgaBoardDesc lx60_board = {
 510         .flash = &lx60_flash,
 511         .sram_size = 0x20000,
 512         .io = xtfpga_nommu_io,
 513     };
 514     xtfpga_init(&lx60_board, machine);
 515 }
 516
 517 static const XtfpgaFlashDesc lx200_flash = {
 518     .base = 0x08000000,
 519     .size = 0x01000000,
 520     .sector_size = 0x20000,
 521 };
 522
 523 static void xtfpga_lx200_init(MachineState *machine)
 524 {
 525     static const XtfpgaBoardDesc lx200_board = {
 526         .flash = &lx200_flash,
 527         .sram_size = 0x2000000,
 528         .io = xtfpga_mmu_io,
 529     };
 530     xtfpga_init(&lx200_board, machine);
 531 }
 532
 533 static void xtfpga_lx200_nommu_init(MachineState *machine)
 534 {
 535     static const XtfpgaBoardDesc lx200_board = {
 536         .flash = &lx200_flash,
 537         .sram_size = 0x2000000,
 538         .io = xtfpga_nommu_io,
 539     };
 540     xtfpga_init(&lx200_board, machine);
 541 }
 542
 543 static const XtfpgaFlashDesc ml605_flash = {
 544     .base = 0x08000000,
 545     .size = 0x01000000,
 546     .sector_size = 0x20000,
 547 };
 548
 549 static void xtfpga_ml605_init(MachineState *machine)
 550 {
 551     static const XtfpgaBoardDesc ml605_board = {
 552         .flash = &ml605_flash,
 553         .sram_size = 0x2000000,
 554         .io = xtfpga_mmu_io,
 555     };
 556     xtfpga_init(&ml605_board, machine);
 557 }
 558
 559 static void xtfpga_ml605_nommu_init(MachineState *machine)
 560 {
 561     static const XtfpgaBoardDesc ml605_board = {
 562         .flash = &ml605_flash,
 563         .sram_size = 0x2000000,
 564         .io = xtfpga_nommu_io,
 565     };
 566     xtfpga_init(&ml605_board, machine);
 567 }
 568
 569 static const XtfpgaFlashDesc kc705_flash = {
 570     .base = 0x00000000,
 571     .size = 0x08000000,
 572     .boot_base = 0x06000000,
 573     .sector_size = 0x20000,
 574 };
 575
 576 static void xtfpga_kc705_init(MachineState *machine)
 577 {
 578     static const XtfpgaBoardDesc kc705_board = {
 579         .flash = &kc705_flash,
 580         .sram_size = 0x2000000,
 581         .io = xtfpga_mmu_io,
 582     };
 583     xtfpga_init(&kc705_board, machine);
 584 }
 585
 586 static void xtfpga_kc705_nommu_init(MachineState *machine)
 587 {
 588     static const XtfpgaBoardDesc kc705_board = {
 589         .flash = &kc705_flash,
 590         .sram_size = 0x2000000,
 591         .io = xtfpga_nommu_io,
 592     };
 593     xtfpga_init(&kc705_board, machine);
 594 }
 595
 596 static void xtfpga_lx60_class_init(ObjectClass *oc, void *data)
 597 {
 598     MachineClass *mc = MACHINE_CLASS(oc);
 599
 600     mc->desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
 601     mc->init = xtfpga_lx60_init;
 602     mc->max_cpus = 32;
 603     mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
 604     mc->default_ram_size = 64 * MiB;
 605 }
 606
 607 static const TypeInfo xtfpga_lx60_type = {
 608     .name = MACHINE_TYPE_NAME("lx60"),
 609     .parent = TYPE_MACHINE,
 610     .class_init = xtfpga_lx60_class_init,
 611 };
 612
 613 static void xtfpga_lx60_nommu_class_init(ObjectClass *oc, void *data)
 614 {
 615     MachineClass *mc = MACHINE_CLASS(oc);
 616
 617     mc->desc = "lx60 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
 618     mc->init = xtfpga_lx60_nommu_init;
 619     mc->max_cpus = 32;
 620     mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
 621     mc->default_ram_size = 64 * MiB;
 622 }
 623
 624 static const TypeInfo xtfpga_lx60_nommu_type = {
 625     .name = MACHINE_TYPE_NAME("lx60-nommu"),
 626     .parent = TYPE_MACHINE,
 627     .class_init = xtfpga_lx60_nommu_class_init,
 628 };
 629
 630 static void xtfpga_lx200_class_init(ObjectClass *oc, void *data)
 631 {
 632     MachineClass *mc = MACHINE_CLASS(oc);
 633
 634     mc->desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
 635     mc->init = xtfpga_lx200_init;
 636     mc->max_cpus = 32;
 637     mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
 638     mc->default_ram_size = 96 * MiB;
 639 }
 640
 641 static const TypeInfo xtfpga_lx200_type = {
 642     .name = MACHINE_TYPE_NAME("lx200"),
 643     .parent = TYPE_MACHINE,
 644     .class_init = xtfpga_lx200_class_init,
 645 };
 646
 647 static void xtfpga_lx200_nommu_class_init(ObjectClass *oc, void *data)
 648 {
 649     MachineClass *mc = MACHINE_CLASS(oc);
 650
 651     mc->desc = "lx200 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
 652     mc->init = xtfpga_lx200_nommu_init;
 653     mc->max_cpus = 32;
 654     mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
 655     mc->default_ram_size = 96 * MiB;
 656 }
 657
 658 static const TypeInfo xtfpga_lx200_nommu_type = {
 659     .name = MACHINE_TYPE_NAME("lx200-nommu"),
 660     .parent = TYPE_MACHINE,
 661     .class_init = xtfpga_lx200_nommu_class_init,
 662 };
 663
 664 static void xtfpga_ml605_class_init(ObjectClass *oc, void *data)
 665 {
 666     MachineClass *mc = MACHINE_CLASS(oc);
 667
 668     mc->desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
 669     mc->init = xtfpga_ml605_init;
 670     mc->max_cpus = 32;
 671     mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
 672     mc->default_ram_size = 512 * MiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE;
 673 }
 674
 675 static const TypeInfo xtfpga_ml605_type = {
 676     .name = MACHINE_TYPE_NAME("ml605"),
 677     .parent = TYPE_MACHINE,
 678     .class_init = xtfpga_ml605_class_init,
 679 };
 680
 681 static void xtfpga_ml605_nommu_class_init(ObjectClass *oc, void *data)
 682 {
 683     MachineClass *mc = MACHINE_CLASS(oc);
 684
 685     mc->desc = "ml605 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
 686     mc->init = xtfpga_ml605_nommu_init;
 687     mc->max_cpus = 32;
 688     mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
 689     mc->default_ram_size = 256 * MiB;
 690 }
 691
 692 static const TypeInfo xtfpga_ml605_nommu_type = {
 693     .name = MACHINE_TYPE_NAME("ml605-nommu"),
 694     .parent = TYPE_MACHINE,
 695     .class_init = xtfpga_ml605_nommu_class_init,
 696 };
 697
 698 static void xtfpga_kc705_class_init(ObjectClass *oc, void *data)
 699 {
 700     MachineClass *mc = MACHINE_CLASS(oc);
 701
 702     mc->desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
 703     mc->init = xtfpga_kc705_init;
 704     mc->max_cpus = 32;
 705     mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
 706     mc->default_ram_size = 1 * GiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE;
 707 }
 708
 709 static const TypeInfo xtfpga_kc705_type = {
 710     .name = MACHINE_TYPE_NAME("kc705"),
 711     .parent = TYPE_MACHINE,
 712     .class_init = xtfpga_kc705_class_init,
 713 };
 714
 715 static void xtfpga_kc705_nommu_class_init(ObjectClass *oc, void *data)
 716 {
 717     MachineClass *mc = MACHINE_CLASS(oc);
 718
 719     mc->desc = "kc705 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
 720     mc->init = xtfpga_kc705_nommu_init;
 721     mc->max_cpus = 32;
 722     mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
 723     mc->default_ram_size = 256 * MiB;
 724 }
 725
 726 static const TypeInfo xtfpga_kc705_nommu_type = {
 727     .name = MACHINE_TYPE_NAME("kc705-nommu"),
 728     .parent = TYPE_MACHINE,
 729     .class_init = xtfpga_kc705_nommu_class_init,
 730 };
 731
 732 static void xtfpga_machines_init(void)
 733 {
 734     type_register_static(&xtfpga_lx60_type);
 735     type_register_static(&xtfpga_lx200_type);
 736     type_register_static(&xtfpga_ml605_type);
 737     type_register_static(&xtfpga_kc705_type);
 738     type_register_static(&xtfpga_lx60_nommu_type);
 739     type_register_static(&xtfpga_lx200_nommu_type);
 740     type_register_static(&xtfpga_ml605_nommu_type);
 741     type_register_static(&xtfpga_kc705_nommu_type);
 742 }
 743
 744 type_init(xtfpga_machines_init)