hw/xtensa/xtfpga.c

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "qemu/units.h"
  30 #include "qapi/error.h"
  31 #include "cpu.h"
  32 #include "sysemu/sysemu.h"
  33 #include "hw/boards.h"
  34 #include "hw/loader.h"
  35 #include "elf.h"
  36 #include "exec/memory.h"
  37 #include "exec/address-spaces.h"
  38 #include "hw/char/serial.h"
  39 #include "net/net.h"
  40 #include "hw/sysbus.h"
  41 #include "hw/block/flash.h"
  42 #include "chardev/char.h"
  43 #include "sysemu/device_tree.h"
  44 #include "qemu/error-report.h"
  45 #include "qemu/option.h"
  46 #include "bootparam.h"
  47 #include "xtensa_memory.h"
  48 #include "hw/xtensa/mx_pic.h"
  49
  50 typedef struct XtfpgaFlashDesc {
  51     hwaddr base;
  52     size_t size;
  53     size_t boot_base;
  54     size_t sector_size;
  55 } XtfpgaFlashDesc;
  56
  57 typedef struct XtfpgaBoardDesc {
  58     const XtfpgaFlashDesc *flash;
  59     size_t sram_size;
  60     const hwaddr *io;
  61 } XtfpgaBoardDesc;
  62
  63 typedef struct XtfpgaFpgaState {
  64     MemoryRegion iomem;
  65     uint32_t freq;
  66     uint32_t leds;
  67     uint32_t switches;
  68 } XtfpgaFpgaState;
  69
  70 static void xtfpga_fpga_reset(void *opaque)
  71 {
  72     XtfpgaFpgaState *s = opaque;
  73
  74     s->leds = 0;
  75     s->switches = 0;
  76 }
  77
  78 static uint64_t xtfpga_fpga_read(void *opaque, hwaddr addr,
  79         unsigned size)
  80 {
  81     XtfpgaFpgaState *s = opaque;
  82
  83     switch (addr) {
  84     case 0x0: /*build date code*/
  85         return 0x09272011;
  86
  87     case 0x4: /*processor clock frequency, Hz*/
  88         return s->freq;
  89
  90     case 0x8: /*LEDs (off = 0, on = 1)*/
  91         return s->leds;
  92
  93     case 0xc: /*DIP switches (off = 0, on = 1)*/
  94         return s->switches;
  95     }
  96     return 0;
  97 }
  98
  99 static void xtfpga_fpga_write(void *opaque, hwaddr addr,
 100         uint64_t val, unsigned size)
 101 {
 102     XtfpgaFpgaState *s = opaque;
 103
 104     switch (addr) {
 105     case 0x8: /*LEDs (off = 0, on = 1)*/
 106         s->leds = val;
 107         break;
 108
 109     case 0x10: /*board reset*/
 110         if (val == 0xdead) {
 111             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 112         }
 113         break;
 114     }
 115 }
 116
 117 static const MemoryRegionOps xtfpga_fpga_ops = {
 118     .read = xtfpga_fpga_read,
 119     .write = xtfpga_fpga_write,
 120     .endianness = DEVICE_NATIVE_ENDIAN,
 121 };
 122
 123 static XtfpgaFpgaState *xtfpga_fpga_init(MemoryRegion *address_space,
 124                                          hwaddr base, uint32_t freq)
 125 {
 126     XtfpgaFpgaState *s = g_malloc(sizeof(XtfpgaFpgaState));
 127
 128     memory_region_init_io(&s->iomem, NULL, &xtfpga_fpga_ops, s,
 129                           "xtfpga.fpga", 0x10000);
 130     memory_region_add_subregion(address_space, base, &s->iomem);
 131     s->freq = freq;
 132     xtfpga_fpga_reset(s);
 133     qemu_register_reset(xtfpga_fpga_reset, s);
 134     return s;
 135 }
 136
 137 static void xtfpga_net_init(MemoryRegion *address_space,
 138         hwaddr base,
 139         hwaddr descriptors,
 140         hwaddr buffers,
 141         qemu_irq irq, NICInfo *nd)
 142 {
 143     DeviceState *dev;
 144     SysBusDevice *s;
 145     MemoryRegion *ram;
 146
 147     dev = qdev_create(NULL, "open_eth");
 148     qdev_set_nic_properties(dev, nd);
 149     qdev_init_nofail(dev);
 150
 151     s = SYS_BUS_DEVICE(dev);
 152     sysbus_connect_irq(s, 0, irq);
 153     memory_region_add_subregion(address_space, base,
 154             sysbus_mmio_get_region(s, 0));
 155     memory_region_add_subregion(address_space, descriptors,
 156             sysbus_mmio_get_region(s, 1));
 157
 158     ram = g_malloc(sizeof(*ram));
 159     memory_region_init_ram_nomigrate(ram, OBJECT(s), "open_eth.ram", 16 * KiB,
 160                            &error_fatal);
 161     vmstate_register_ram_global(ram);
 162     memory_region_add_subregion(address_space, buffers, ram);
 163 }
 164
 165 static PFlashCFI01 *xtfpga_flash_init(MemoryRegion *address_space,
 166                                       const XtfpgaBoardDesc *board,
 167                                       DriveInfo *dinfo, int be)
 168 {
 169     SysBusDevice *s;
 170     DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01);
 171
 172     qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
 173                         &error_abort);
 174     qdev_prop_set_uint32(dev, "num-blocks",
 175                          board->flash->size / board->flash->sector_size);
 176     qdev_prop_set_uint64(dev, "sector-length", board->flash->sector_size);
 177     qdev_prop_set_uint8(dev, "width", 2);
 178     qdev_prop_set_bit(dev, "big-endian", be);
 179     qdev_prop_set_string(dev, "name", "xtfpga.io.flash");
 180     qdev_init_nofail(dev);
 181     s = SYS_BUS_DEVICE(dev);
 182     memory_region_add_subregion(address_space, board->flash->base,
 183                                 sysbus_mmio_get_region(s, 0));
 184     return PFLASH_CFI01(dev);
 185 }
 186
 187 static uint64_t translate_phys_addr(void *opaque, uint64_t addr)
 188 {
 189     XtensaCPU *cpu = opaque;
 190
 191     return cpu_get_phys_page_debug(CPU(cpu), addr);
 192 }
 193
 194 static void xtfpga_reset(void *opaque)
 195 {
 196     XtensaCPU *cpu = opaque;
 197
 198     cpu_reset(CPU(cpu));
 199 }
 200
 201 static uint64_t xtfpga_io_read(void *opaque, hwaddr addr,
 202         unsigned size)
 203 {
 204     return 0;
 205 }
 206
 207 static void xtfpga_io_write(void *opaque, hwaddr addr,
 208         uint64_t val, unsigned size)
 209 {
 210 }
 211
 212 static const MemoryRegionOps xtfpga_io_ops = {
 213     .read = xtfpga_io_read,
 214     .write = xtfpga_io_write,
 215     .endianness = DEVICE_NATIVE_ENDIAN,
 216 };
 217
 218 static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine)
 219 {
 220 #ifdef TARGET_WORDS_BIGENDIAN
 221     int be = 1;
 222 #else
 223     int be = 0;
 224 #endif
 225     MemoryRegion *system_memory = get_system_memory();
 226     XtensaCPU *cpu = NULL;
 227     CPUXtensaState *env = NULL;
 228     MemoryRegion *system_io;
 229     XtensaMxPic *mx_pic = NULL;
 230     qemu_irq *extints;
 231     DriveInfo *dinfo;
 232     PFlashCFI01 *flash = NULL;
 233     QemuOpts *machine_opts = qemu_get_machine_opts();
 234     const char *kernel_filename = qemu_opt_get(machine_opts, "kernel");
 235     const char *kernel_cmdline = qemu_opt_get(machine_opts, "append");
 236     const char *dtb_filename = qemu_opt_get(machine_opts, "dtb");
 237     const char *initrd_filename = qemu_opt_get(machine_opts, "initrd");
 238     const unsigned system_io_size = 224 * MiB;
 239     uint32_t freq = 10000000;
 240     int n;
 241     unsigned int smp_cpus = machine->smp.cpus;
 242
 243     if (smp_cpus > 1) {
 244         mx_pic = xtensa_mx_pic_init(31);
 245         qemu_register_reset(xtensa_mx_pic_reset, mx_pic);
 246     }
 247     for (n = 0; n < smp_cpus; n++) {
 248         CPUXtensaState *cenv = NULL;
 249
 250         cpu = XTENSA_CPU(cpu_create(machine->cpu_type));
 251         cenv = &cpu->env;
 252         if (!env) {
 253             env = cenv;
 254             freq = env->config->clock_freq_khz * 1000;
 255         }
 256
 257         if (mx_pic) {
 258             MemoryRegion *mx_eri;
 259
 260             mx_eri = xtensa_mx_pic_register_cpu(mx_pic,
 261                                                 xtensa_get_extints(cenv),
 262                                                 xtensa_get_runstall(cenv));
 263             memory_region_add_subregion(xtensa_get_er_region(cenv),
 264                                         0, mx_eri);
 265         }
 266         cenv->sregs[PRID] = n;
 267         xtensa_select_static_vectors(cenv, n != 0);
 268         qemu_register_reset(xtfpga_reset, cpu);
 269         /* Need MMU initialized prior to ELF loading,
 270          * so that ELF gets loaded into virtual addresses
 271          */
 272         cpu_reset(CPU(cpu));
 273     }
 274     if (smp_cpus > 1) {
 275         extints = xtensa_mx_pic_get_extints(mx_pic);
 276     } else {
 277         extints = xtensa_get_extints(env);
 278     }
 279
 280     if (env) {
 281         XtensaMemory sysram = env->config->sysram;
 282
 283         sysram.location[0].size = machine->ram_size;
 284         xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom",
 285                                      system_memory);
 286         xtensa_create_memory_regions(&env->config->instram, "xtensa.instram",
 287                                      system_memory);
 288         xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom",
 289                                      system_memory);
 290         xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram",
 291                                      system_memory);
 292         xtensa_create_memory_regions(&sysram, "xtensa.sysram",
 293                                      system_memory);
 294     }
 295
 296     system_io = g_malloc(sizeof(*system_io));
 297     memory_region_init_io(system_io, NULL, &xtfpga_io_ops, NULL, "xtfpga.io",
 298                           system_io_size);
 299     memory_region_add_subregion(system_memory, board->io[0], system_io);
 300     if (board->io[1]) {
 301         MemoryRegion *io = g_malloc(sizeof(*io));
 302
 303         memory_region_init_alias(io, NULL, "xtfpga.io.cached",
 304                                  system_io, 0, system_io_size);
 305         memory_region_add_subregion(system_memory, board->io[1], io);
 306     }
 307     xtfpga_fpga_init(system_io, 0x0d020000, freq);
 308     if (nd_table[0].used) {
 309         xtfpga_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000,
 310                         extints[1], nd_table);
 311     }
 312
 313     serial_mm_init(system_io, 0x0d050020, 2, extints[0],
 314                    115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
 315
 316     dinfo = drive_get(IF_PFLASH, 0, 0);
 317     if (dinfo) {
 318         flash = xtfpga_flash_init(system_io, board, dinfo, be);
 319     }
 320
 321     /* Use presence of kernel file name as 'boot from SRAM' switch. */
 322     if (kernel_filename) {
 323         uint32_t entry_point = env->pc;
 324         size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */
 325         uint32_t tagptr = env->config->sysrom.location[0].addr +
 326             board->sram_size;
 327         uint32_t cur_tagptr;
 328         BpMemInfo memory_location = {
 329             .type = tswap32(MEMORY_TYPE_CONVENTIONAL),
 330             .start = tswap32(env->config->sysram.location[0].addr),
 331             .end = tswap32(env->config->sysram.location[0].addr +
 332                            machine->ram_size),
 333         };
 334         uint32_t lowmem_end = machine->ram_size < 0x08000000 ?
 335             machine->ram_size : 0x08000000;
 336         uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096);
 337
 338         lowmem_end += env->config->sysram.location[0].addr;
 339         cur_lowmem += env->config->sysram.location[0].addr;
 340
 341         xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom",
 342                                      system_memory);
 343
 344         if (kernel_cmdline) {
 345             bp_size += get_tag_size(strlen(kernel_cmdline) + 1);
 346         }
 347         if (dtb_filename) {
 348             bp_size += get_tag_size(sizeof(uint32_t));
 349         }
 350         if (initrd_filename) {
 351             bp_size += get_tag_size(sizeof(BpMemInfo));
 352         }
 353
 354         /* Put kernel bootparameters to the end of that SRAM */
 355         tagptr = (tagptr - bp_size) & ~0xff;
 356         cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL);
 357         cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY,
 358                              sizeof(memory_location), &memory_location);
 359
 360         if (kernel_cmdline) {
 361             cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE,
 362                                  strlen(kernel_cmdline) + 1, kernel_cmdline);
 363         }
 364 #ifdef CONFIG_FDT
 365         if (dtb_filename) {
 366             int fdt_size;
 367             void *fdt = load_device_tree(dtb_filename, &fdt_size);
 368             uint32_t dtb_addr = tswap32(cur_lowmem);
 369
 370             if (!fdt) {
 371                 error_report("could not load DTB '%s'", dtb_filename);
 372                 exit(EXIT_FAILURE);
 373             }
 374
 375             cpu_physical_memory_write(cur_lowmem, fdt, fdt_size);
 376             cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT,
 377                                  sizeof(dtb_addr), &dtb_addr);
 378             cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4 * KiB);
 379         }
 380 #else
 381         if (dtb_filename) {
 382             error_report("could not load DTB '%s': "
 383                          "FDT support is not configured in QEMU",
 384                          dtb_filename);
 385             exit(EXIT_FAILURE);
 386         }
 387 #endif
 388         if (initrd_filename) {
 389             BpMemInfo initrd_location = { 0 };
 390             int initrd_size = load_ramdisk(initrd_filename, cur_lowmem,
 391                                            lowmem_end - cur_lowmem);
 392
 393             if (initrd_size < 0) {
 394                 initrd_size = load_image_targphys(initrd_filename,
 395                                                   cur_lowmem,
 396                                                   lowmem_end - cur_lowmem);
 397             }
 398             if (initrd_size < 0) {
 399                 error_report("could not load initrd '%s'", initrd_filename);
 400                 exit(EXIT_FAILURE);
 401             }
 402             initrd_location.start = tswap32(cur_lowmem);
 403             initrd_location.end = tswap32(cur_lowmem + initrd_size);
 404             cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD,
 405                                  sizeof(initrd_location), &initrd_location);
 406             cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4 * KiB);
 407         }
 408         cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL);
 409         env->regs[2] = tagptr;
 410
 411         uint64_t elf_entry;
 412         uint64_t elf_lowaddr;
 413         int success = load_elf(kernel_filename, NULL, translate_phys_addr, cpu,
 414                 &elf_entry, &elf_lowaddr, NULL, be, EM_XTENSA, 0, 0);
 415         if (success > 0) {
 416             entry_point = elf_entry;
 417         } else {
 418             hwaddr ep;
 419             int is_linux;
 420             success = load_uimage(kernel_filename, &ep, NULL, &is_linux,
 421                                   translate_phys_addr, cpu);
 422             if (success > 0 && is_linux) {
 423                 entry_point = ep;
 424             } else {
 425                 error_report("could not load kernel '%s'",
 426                              kernel_filename);
 427                 exit(EXIT_FAILURE);
 428             }
 429         }
 430         if (entry_point != env->pc) {
 431             uint8_t boot[] = {
 432 #ifdef TARGET_WORDS_BIGENDIAN
 433                 0x60, 0x00, 0x08,       /* j    1f */
 434                 0x00,                   /* .literal_position */
 435                 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
 436                 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */
 437                                         /* 1: */
 438                 0x10, 0xff, 0xfe,       /* l32r a0, entry_pc */
 439                 0x12, 0xff, 0xfe,       /* l32r a2, entry_a2 */
 440                 0x0a, 0x00, 0x00,       /* jx   a0 */
 441 #else
 442                 0x06, 0x02, 0x00,       /* j    1f */
 443                 0x00,                   /* .literal_position */
 444                 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
 445                 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */
 446                                         /* 1: */
 447                 0x01, 0xfe, 0xff,       /* l32r a0, entry_pc */
 448                 0x21, 0xfe, 0xff,       /* l32r a2, entry_a2 */
 449                 0xa0, 0x00, 0x00,       /* jx   a0 */
 450 #endif
 451             };
 452             uint32_t entry_pc = tswap32(entry_point);
 453             uint32_t entry_a2 = tswap32(tagptr);
 454
 455             memcpy(boot + 4, &entry_pc, sizeof(entry_pc));
 456             memcpy(boot + 8, &entry_a2, sizeof(entry_a2));
 457             cpu_physical_memory_write(env->pc, boot, sizeof(boot));
 458         }
 459     } else {
 460         if (flash) {
 461             MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash);
 462             MemoryRegion *flash_io = g_malloc(sizeof(*flash_io));
 463             uint32_t size = env->config->sysrom.location[0].size;
 464
 465             if (board->flash->size - board->flash->boot_base < size) {
 466                 size = board->flash->size - board->flash->boot_base;
 467             }
 468
 469             memory_region_init_alias(flash_io, NULL, "xtfpga.flash",
 470                                      flash_mr, board->flash->boot_base, size);
 471             memory_region_add_subregion(system_memory,
 472                                         env->config->sysrom.location[0].addr,
 473                                         flash_io);
 474         } else {
 475             xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom",
 476                                          system_memory);
 477         }
 478     }
 479 }
 480
 481 #define XTFPGA_MMU_RESERVED_MEMORY_SIZE (128 * MiB)
 482
 483 static const hwaddr xtfpga_mmu_io[2] = {
 484     0xf0000000,
 485 };
 486
 487 static const hwaddr xtfpga_nommu_io[2] = {
 488     0x90000000,
 489     0x70000000,
 490 };
 491
 492 static const XtfpgaFlashDesc lx60_flash = {
 493     .base = 0x08000000,
 494     .size = 0x00400000,
 495     .sector_size = 0x10000,
 496 };
 497
 498 static void xtfpga_lx60_init(MachineState *machine)
 499 {
 500     static const XtfpgaBoardDesc lx60_board = {
 501         .flash = &lx60_flash,
 502         .sram_size = 0x20000,
 503         .io = xtfpga_mmu_io,
 504     };
 505     xtfpga_init(&lx60_board, machine);
 506 }
 507
 508 static void xtfpga_lx60_nommu_init(MachineState *machine)
 509 {
 510     static const XtfpgaBoardDesc lx60_board = {
 511         .flash = &lx60_flash,
 512         .sram_size = 0x20000,
 513         .io = xtfpga_nommu_io,
 514     };
 515     xtfpga_init(&lx60_board, machine);
 516 }
 517
 518 static const XtfpgaFlashDesc lx200_flash = {
 519     .base = 0x08000000,
 520     .size = 0x01000000,
 521     .sector_size = 0x20000,
 522 };
 523
 524 static void xtfpga_lx200_init(MachineState *machine)
 525 {
 526     static const XtfpgaBoardDesc lx200_board = {
 527         .flash = &lx200_flash,
 528         .sram_size = 0x2000000,
 529         .io = xtfpga_mmu_io,
 530     };
 531     xtfpga_init(&lx200_board, machine);
 532 }
 533
 534 static void xtfpga_lx200_nommu_init(MachineState *machine)
 535 {
 536     static const XtfpgaBoardDesc lx200_board = {
 537         .flash = &lx200_flash,
 538         .sram_size = 0x2000000,
 539         .io = xtfpga_nommu_io,
 540     };
 541     xtfpga_init(&lx200_board, machine);
 542 }
 543
 544 static const XtfpgaFlashDesc ml605_flash = {
 545     .base = 0x08000000,
 546     .size = 0x01000000,
 547     .sector_size = 0x20000,
 548 };
 549
 550 static void xtfpga_ml605_init(MachineState *machine)
 551 {
 552     static const XtfpgaBoardDesc ml605_board = {
 553         .flash = &ml605_flash,
 554         .sram_size = 0x2000000,
 555         .io = xtfpga_mmu_io,
 556     };
 557     xtfpga_init(&ml605_board, machine);
 558 }
 559
 560 static void xtfpga_ml605_nommu_init(MachineState *machine)
 561 {
 562     static const XtfpgaBoardDesc ml605_board = {
 563         .flash = &ml605_flash,
 564         .sram_size = 0x2000000,
 565         .io = xtfpga_nommu_io,
 566     };
 567     xtfpga_init(&ml605_board, machine);
 568 }
 569
 570 static const XtfpgaFlashDesc kc705_flash = {
 571     .base = 0x00000000,
 572     .size = 0x08000000,
 573     .boot_base = 0x06000000,
 574     .sector_size = 0x20000,
 575 };
 576
 577 static void xtfpga_kc705_init(MachineState *machine)
 578 {
 579     static const XtfpgaBoardDesc kc705_board = {
 580         .flash = &kc705_flash,
 581         .sram_size = 0x2000000,
 582         .io = xtfpga_mmu_io,
 583     };
 584     xtfpga_init(&kc705_board, machine);
 585 }
 586
 587 static void xtfpga_kc705_nommu_init(MachineState *machine)
 588 {
 589     static const XtfpgaBoardDesc kc705_board = {
 590         .flash = &kc705_flash,
 591         .sram_size = 0x2000000,
 592         .io = xtfpga_nommu_io,
 593     };
 594     xtfpga_init(&kc705_board, machine);
 595 }
 596
 597 static void xtfpga_lx60_class_init(ObjectClass *oc, void *data)
 598 {
 599     MachineClass *mc = MACHINE_CLASS(oc);
 600
 601     mc->desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
 602     mc->init = xtfpga_lx60_init;
 603     mc->max_cpus = 32;
 604     mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
 605     mc->default_ram_size = 64 * MiB;
 606 }
 607
 608 static const TypeInfo xtfpga_lx60_type = {
 609     .name = MACHINE_TYPE_NAME("lx60"),
 610     .parent = TYPE_MACHINE,
 611     .class_init = xtfpga_lx60_class_init,
 612 };
 613
 614 static void xtfpga_lx60_nommu_class_init(ObjectClass *oc, void *data)
 615 {
 616     MachineClass *mc = MACHINE_CLASS(oc);
 617
 618     mc->desc = "lx60 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
 619     mc->init = xtfpga_lx60_nommu_init;
 620     mc->max_cpus = 32;
 621     mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
 622     mc->default_ram_size = 64 * MiB;
 623 }
 624
 625 static const TypeInfo xtfpga_lx60_nommu_type = {
 626     .name = MACHINE_TYPE_NAME("lx60-nommu"),
 627     .parent = TYPE_MACHINE,
 628     .class_init = xtfpga_lx60_nommu_class_init,
 629 };
 630
 631 static void xtfpga_lx200_class_init(ObjectClass *oc, void *data)
 632 {
 633     MachineClass *mc = MACHINE_CLASS(oc);
 634
 635     mc->desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
 636     mc->init = xtfpga_lx200_init;
 637     mc->max_cpus = 32;
 638     mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
 639     mc->default_ram_size = 96 * MiB;
 640 }
 641
 642 static const TypeInfo xtfpga_lx200_type = {
 643     .name = MACHINE_TYPE_NAME("lx200"),
 644     .parent = TYPE_MACHINE,
 645     .class_init = xtfpga_lx200_class_init,
 646 };
 647
 648 static void xtfpga_lx200_nommu_class_init(ObjectClass *oc, void *data)
 649 {
 650     MachineClass *mc = MACHINE_CLASS(oc);
 651
 652     mc->desc = "lx200 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
 653     mc->init = xtfpga_lx200_nommu_init;
 654     mc->max_cpus = 32;
 655     mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
 656     mc->default_ram_size = 96 * MiB;
 657 }
 658
 659 static const TypeInfo xtfpga_lx200_nommu_type = {
 660     .name = MACHINE_TYPE_NAME("lx200-nommu"),
 661     .parent = TYPE_MACHINE,
 662     .class_init = xtfpga_lx200_nommu_class_init,
 663 };
 664
 665 static void xtfpga_ml605_class_init(ObjectClass *oc, void *data)
 666 {
 667     MachineClass *mc = MACHINE_CLASS(oc);
 668
 669     mc->desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
 670     mc->init = xtfpga_ml605_init;
 671     mc->max_cpus = 32;
 672     mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
 673     mc->default_ram_size = 512 * MiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE;
 674 }
 675
 676 static const TypeInfo xtfpga_ml605_type = {
 677     .name = MACHINE_TYPE_NAME("ml605"),
 678     .parent = TYPE_MACHINE,
 679     .class_init = xtfpga_ml605_class_init,
 680 };
 681
 682 static void xtfpga_ml605_nommu_class_init(ObjectClass *oc, void *data)
 683 {
 684     MachineClass *mc = MACHINE_CLASS(oc);
 685
 686     mc->desc = "ml605 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
 687     mc->init = xtfpga_ml605_nommu_init;
 688     mc->max_cpus = 32;
 689     mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
 690     mc->default_ram_size = 256 * MiB;
 691 }
 692
 693 static const TypeInfo xtfpga_ml605_nommu_type = {
 694     .name = MACHINE_TYPE_NAME("ml605-nommu"),
 695     .parent = TYPE_MACHINE,
 696     .class_init = xtfpga_ml605_nommu_class_init,
 697 };
 698
 699 static void xtfpga_kc705_class_init(ObjectClass *oc, void *data)
 700 {
 701     MachineClass *mc = MACHINE_CLASS(oc);
 702
 703     mc->desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
 704     mc->init = xtfpga_kc705_init;
 705     mc->max_cpus = 32;
 706     mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
 707     mc->default_ram_size = 1 * GiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE;
 708 }
 709
 710 static const TypeInfo xtfpga_kc705_type = {
 711     .name = MACHINE_TYPE_NAME("kc705"),
 712     .parent = TYPE_MACHINE,
 713     .class_init = xtfpga_kc705_class_init,
 714 };
 715
 716 static void xtfpga_kc705_nommu_class_init(ObjectClass *oc, void *data)
 717 {
 718     MachineClass *mc = MACHINE_CLASS(oc);
 719
 720     mc->desc = "kc705 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")";
 721     mc->init = xtfpga_kc705_nommu_init;
 722     mc->max_cpus = 32;
 723     mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE;
 724     mc->default_ram_size = 256 * MiB;
 725 }
 726
 727 static const TypeInfo xtfpga_kc705_nommu_type = {
 728     .name = MACHINE_TYPE_NAME("kc705-nommu"),
 729     .parent = TYPE_MACHINE,
 730     .class_init = xtfpga_kc705_nommu_class_init,
 731 };
 732
 733 static void xtfpga_machines_init(void)
 734 {
 735     type_register_static(&xtfpga_lx60_type);
 736     type_register_static(&xtfpga_lx200_type);
 737     type_register_static(&xtfpga_ml605_type);
 738     type_register_static(&xtfpga_kc705_type);
 739     type_register_static(&xtfpga_lx60_nommu_type);
 740     type_register_static(&xtfpga_lx200_nommu_type);
 741     type_register_static(&xtfpga_ml605_nommu_type);
 742     type_register_static(&xtfpga_kc705_nommu_type);
 743 }
 744
 745 type_init(xtfpga_machines_init)