hw/xtensa/xtfpga.c

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "qapi/error.h"
  30 #include "qemu-common.h"
  31 #include "cpu.h"
  32 #include "sysemu/sysemu.h"
  33 #include "hw/boards.h"
  34 #include "hw/loader.h"
  35 #include "elf.h"
  36 #include "exec/memory.h"
  37 #include "exec/address-spaces.h"
  38 #include "hw/char/serial.h"
  39 #include "net/net.h"
  40 #include "hw/sysbus.h"
  41 #include "hw/block/flash.h"
  42 #include "sysemu/block-backend.h"
  43 #include "chardev/char.h"
  44 #include "sysemu/device_tree.h"
  45 #include "qemu/error-report.h"
  46 #include "bootparam.h"
  47 #include "xtensa_memory.h"
  48
  49 typedef struct XtfpgaFlashDesc {
  50     hwaddr base;
  51     size_t size;
  52     size_t boot_base;
  53     size_t sector_size;
  54 } XtfpgaFlashDesc;
  55
  56 typedef struct XtfpgaBoardDesc {
  57     const XtfpgaFlashDesc *flash;
  58     size_t sram_size;
  59 } XtfpgaBoardDesc;
  60
  61 typedef struct XtfpgaFpgaState {
  62     MemoryRegion iomem;
  63     uint32_t leds;
  64     uint32_t switches;
  65 } XtfpgaFpgaState;
  66
  67 static void xtfpga_fpga_reset(void *opaque)
  68 {
  69     XtfpgaFpgaState *s = opaque;
  70
  71     s->leds = 0;
  72     s->switches = 0;
  73 }
  74
  75 static uint64_t xtfpga_fpga_read(void *opaque, hwaddr addr,
  76         unsigned size)
  77 {
  78     XtfpgaFpgaState *s = opaque;
  79
  80     switch (addr) {
  81     case 0x0: /*build date code*/
  82         return 0x09272011;
  83
  84     case 0x4: /*processor clock frequency, Hz*/
  85         return 10000000;
  86
  87     case 0x8: /*LEDs (off = 0, on = 1)*/
  88         return s->leds;
  89
  90     case 0xc: /*DIP switches (off = 0, on = 1)*/
  91         return s->switches;
  92     }
  93     return 0;
  94 }
  95
  96 static void xtfpga_fpga_write(void *opaque, hwaddr addr,
  97         uint64_t val, unsigned size)
  98 {
  99     XtfpgaFpgaState *s = opaque;
 100
 101     switch (addr) {
 102     case 0x8: /*LEDs (off = 0, on = 1)*/
 103         s->leds = val;
 104         break;
 105
 106     case 0x10: /*board reset*/
 107         if (val == 0xdead) {
 108             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 109         }
 110         break;
 111     }
 112 }
 113
 114 static const MemoryRegionOps xtfpga_fpga_ops = {
 115     .read = xtfpga_fpga_read,
 116     .write = xtfpga_fpga_write,
 117     .endianness = DEVICE_NATIVE_ENDIAN,
 118 };
 119
 120 static XtfpgaFpgaState *xtfpga_fpga_init(MemoryRegion *address_space,
 121         hwaddr base)
 122 {
 123     XtfpgaFpgaState *s = g_malloc(sizeof(XtfpgaFpgaState));
 124
 125     memory_region_init_io(&s->iomem, NULL, &xtfpga_fpga_ops, s,
 126             "xtfpga.fpga", 0x10000);
 127     memory_region_add_subregion(address_space, base, &s->iomem);
 128     xtfpga_fpga_reset(s);
 129     qemu_register_reset(xtfpga_fpga_reset, s);
 130     return s;
 131 }
 132
 133 static void xtfpga_net_init(MemoryRegion *address_space,
 134         hwaddr base,
 135         hwaddr descriptors,
 136         hwaddr buffers,
 137         qemu_irq irq, NICInfo *nd)
 138 {
 139     DeviceState *dev;
 140     SysBusDevice *s;
 141     MemoryRegion *ram;
 142
 143     dev = qdev_create(NULL, "open_eth");
 144     qdev_set_nic_properties(dev, nd);
 145     qdev_init_nofail(dev);
 146
 147     s = SYS_BUS_DEVICE(dev);
 148     sysbus_connect_irq(s, 0, irq);
 149     memory_region_add_subregion(address_space, base,
 150             sysbus_mmio_get_region(s, 0));
 151     memory_region_add_subregion(address_space, descriptors,
 152             sysbus_mmio_get_region(s, 1));
 153
 154     ram = g_malloc(sizeof(*ram));
 155     memory_region_init_ram_nomigrate(ram, OBJECT(s), "open_eth.ram", 16384,
 156                            &error_fatal);
 157     vmstate_register_ram_global(ram);
 158     memory_region_add_subregion(address_space, buffers, ram);
 159 }
 160
 161 static pflash_t *xtfpga_flash_init(MemoryRegion *address_space,
 162                                    const XtfpgaBoardDesc *board,
 163                                    DriveInfo *dinfo, int be)
 164 {
 165     SysBusDevice *s;
 166     DeviceState *dev = qdev_create(NULL, "cfi.pflash01");
 167
 168     qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
 169                         &error_abort);
 170     qdev_prop_set_uint32(dev, "num-blocks",
 171                          board->flash->size / board->flash->sector_size);
 172     qdev_prop_set_uint64(dev, "sector-length", board->flash->sector_size);
 173     qdev_prop_set_uint8(dev, "width", 2);
 174     qdev_prop_set_bit(dev, "big-endian", be);
 175     qdev_prop_set_string(dev, "name", "xtfpga.io.flash");
 176     qdev_init_nofail(dev);
 177     s = SYS_BUS_DEVICE(dev);
 178     memory_region_add_subregion(address_space, board->flash->base,
 179                                 sysbus_mmio_get_region(s, 0));
 180     return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01");
 181 }
 182
 183 static uint64_t translate_phys_addr(void *opaque, uint64_t addr)
 184 {
 185     XtensaCPU *cpu = opaque;
 186
 187     return cpu_get_phys_page_debug(CPU(cpu), addr);
 188 }
 189
 190 static void xtfpga_reset(void *opaque)
 191 {
 192     XtensaCPU *cpu = opaque;
 193
 194     cpu_reset(CPU(cpu));
 195 }
 196
 197 static uint64_t xtfpga_io_read(void *opaque, hwaddr addr,
 198         unsigned size)
 199 {
 200     return 0;
 201 }
 202
 203 static void xtfpga_io_write(void *opaque, hwaddr addr,
 204         uint64_t val, unsigned size)
 205 {
 206 }
 207
 208 static const MemoryRegionOps xtfpga_io_ops = {
 209     .read = xtfpga_io_read,
 210     .write = xtfpga_io_write,
 211     .endianness = DEVICE_NATIVE_ENDIAN,
 212 };
 213
 214 static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine)
 215 {
 216 #ifdef TARGET_WORDS_BIGENDIAN
 217     int be = 1;
 218 #else
 219     int be = 0;
 220 #endif
 221     MemoryRegion *system_memory = get_system_memory();
 222     XtensaCPU *cpu = NULL;
 223     CPUXtensaState *env = NULL;
 224     MemoryRegion *system_io;
 225     DriveInfo *dinfo;
 226     pflash_t *flash = NULL;
 227     QemuOpts *machine_opts = qemu_get_machine_opts();
 228     const char *kernel_filename = qemu_opt_get(machine_opts, "kernel");
 229     const char *kernel_cmdline = qemu_opt_get(machine_opts, "append");
 230     const char *dtb_filename = qemu_opt_get(machine_opts, "dtb");
 231     const char *initrd_filename = qemu_opt_get(machine_opts, "initrd");
 232     int n;
 233
 234     for (n = 0; n < smp_cpus; n++) {
 235         cpu = XTENSA_CPU(cpu_create(machine->cpu_type));
 236         env = &cpu->env;
 237
 238         env->sregs[PRID] = n;
 239         qemu_register_reset(xtfpga_reset, cpu);
 240         /* Need MMU initialized prior to ELF loading,
 241          * so that ELF gets loaded into virtual addresses
 242          */
 243         cpu_reset(CPU(cpu));
 244     }
 245
 246     if (env) {
 247         XtensaMemory sysram = env->config->sysram;
 248
 249         sysram.location[0].size = machine->ram_size;
 250         xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom",
 251                                      system_memory);
 252         xtensa_create_memory_regions(&env->config->instram, "xtensa.instram",
 253                                      system_memory);
 254         xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom",
 255                                      system_memory);
 256         xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram",
 257                                      system_memory);
 258         xtensa_create_memory_regions(&sysram, "xtensa.sysram",
 259                                      system_memory);
 260     }
 261
 262     system_io = g_malloc(sizeof(*system_io));
 263     memory_region_init_io(system_io, NULL, &xtfpga_io_ops, NULL, "xtfpga.io",
 264                           224 * 1024 * 1024);
 265     memory_region_add_subregion(system_memory, 0xf0000000, system_io);
 266     xtfpga_fpga_init(system_io, 0x0d020000);
 267     if (nd_table[0].used) {
 268         xtfpga_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000,
 269                 xtensa_get_extint(env, 1), nd_table);
 270     }
 271
 272     if (!serial_hds[0]) {
 273         serial_hds[0] = qemu_chr_new("serial0", "null");
 274     }
 275
 276     serial_mm_init(system_io, 0x0d050020, 2, xtensa_get_extint(env, 0),
 277             115200, serial_hds[0], DEVICE_NATIVE_ENDIAN);
 278
 279     dinfo = drive_get(IF_PFLASH, 0, 0);
 280     if (dinfo) {
 281         flash = xtfpga_flash_init(system_io, board, dinfo, be);
 282     }
 283
 284     /* Use presence of kernel file name as 'boot from SRAM' switch. */
 285     if (kernel_filename) {
 286         uint32_t entry_point = env->pc;
 287         size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */
 288         uint32_t tagptr = env->config->sysrom.location[0].addr +
 289             board->sram_size;
 290         uint32_t cur_tagptr;
 291         BpMemInfo memory_location = {
 292             .type = tswap32(MEMORY_TYPE_CONVENTIONAL),
 293             .start = tswap32(env->config->sysram.location[0].addr),
 294             .end = tswap32(env->config->sysram.location[0].addr +
 295                            machine->ram_size),
 296         };
 297         uint32_t lowmem_end = machine->ram_size < 0x08000000 ?
 298             machine->ram_size : 0x08000000;
 299         uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096);
 300
 301         lowmem_end += env->config->sysram.location[0].addr;
 302         cur_lowmem += env->config->sysram.location[0].addr;
 303
 304         xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom",
 305                                      system_memory);
 306
 307         if (kernel_cmdline) {
 308             bp_size += get_tag_size(strlen(kernel_cmdline) + 1);
 309         }
 310         if (dtb_filename) {
 311             bp_size += get_tag_size(sizeof(uint32_t));
 312         }
 313         if (initrd_filename) {
 314             bp_size += get_tag_size(sizeof(BpMemInfo));
 315         }
 316
 317         /* Put kernel bootparameters to the end of that SRAM */
 318         tagptr = (tagptr - bp_size) & ~0xff;
 319         cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL);
 320         cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY,
 321                              sizeof(memory_location), &memory_location);
 322
 323         if (kernel_cmdline) {
 324             cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE,
 325                                  strlen(kernel_cmdline) + 1, kernel_cmdline);
 326         }
 327 #ifdef CONFIG_FDT
 328         if (dtb_filename) {
 329             int fdt_size;
 330             void *fdt = load_device_tree(dtb_filename, &fdt_size);
 331             uint32_t dtb_addr = tswap32(cur_lowmem);
 332
 333             if (!fdt) {
 334                 error_report("could not load DTB '%s'", dtb_filename);
 335                 exit(EXIT_FAILURE);
 336             }
 337
 338             cpu_physical_memory_write(cur_lowmem, fdt, fdt_size);
 339             cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT,
 340                                  sizeof(dtb_addr), &dtb_addr);
 341             cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4096);
 342         }
 343 #else
 344         if (dtb_filename) {
 345             error_report("could not load DTB '%s': "
 346                          "FDT support is not configured in QEMU",
 347                          dtb_filename);
 348             exit(EXIT_FAILURE);
 349         }
 350 #endif
 351         if (initrd_filename) {
 352             BpMemInfo initrd_location = { 0 };
 353             int initrd_size = load_ramdisk(initrd_filename, cur_lowmem,
 354                                            lowmem_end - cur_lowmem);
 355
 356             if (initrd_size < 0) {
 357                 initrd_size = load_image_targphys(initrd_filename,
 358                                                   cur_lowmem,
 359                                                   lowmem_end - cur_lowmem);
 360             }
 361             if (initrd_size < 0) {
 362                 error_report("could not load initrd '%s'", initrd_filename);
 363                 exit(EXIT_FAILURE);
 364             }
 365             initrd_location.start = tswap32(cur_lowmem);
 366             initrd_location.end = tswap32(cur_lowmem + initrd_size);
 367             cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD,
 368                                  sizeof(initrd_location), &initrd_location);
 369             cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4096);
 370         }
 371         cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL);
 372         env->regs[2] = tagptr;
 373
 374         uint64_t elf_entry;
 375         uint64_t elf_lowaddr;
 376         int success = load_elf(kernel_filename, translate_phys_addr, cpu,
 377                 &elf_entry, &elf_lowaddr, NULL, be, EM_XTENSA, 0, 0);
 378         if (success > 0) {
 379             entry_point = elf_entry;
 380         } else {
 381             hwaddr ep;
 382             int is_linux;
 383             success = load_uimage(kernel_filename, &ep, NULL, &is_linux,
 384                                   translate_phys_addr, cpu);
 385             if (success > 0 && is_linux) {
 386                 entry_point = ep;
 387             } else {
 388                 error_report("could not load kernel '%s'",
 389                              kernel_filename);
 390                 exit(EXIT_FAILURE);
 391             }
 392         }
 393         if (entry_point != env->pc) {
 394             uint8_t boot[] = {
 395 #ifdef TARGET_WORDS_BIGENDIAN
 396                 0x60, 0x00, 0x08,       /* j    1f */
 397                 0x00,                   /* .literal_position */
 398                 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
 399                 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */
 400                                         /* 1: */
 401                 0x10, 0xff, 0xfe,       /* l32r a0, entry_pc */
 402                 0x12, 0xff, 0xfe,       /* l32r a2, entry_a2 */
 403                 0x0a, 0x00, 0x00,       /* jx   a0 */
 404 #else
 405                 0x06, 0x02, 0x00,       /* j    1f */
 406                 0x00,                   /* .literal_position */
 407                 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
 408                 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */
 409                                         /* 1: */
 410                 0x01, 0xfe, 0xff,       /* l32r a0, entry_pc */
 411                 0x21, 0xfe, 0xff,       /* l32r a2, entry_a2 */
 412                 0xa0, 0x00, 0x00,       /* jx   a0 */
 413 #endif
 414             };
 415             uint32_t entry_pc = tswap32(entry_point);
 416             uint32_t entry_a2 = tswap32(tagptr);
 417
 418             memcpy(boot + 4, &entry_pc, sizeof(entry_pc));
 419             memcpy(boot + 8, &entry_a2, sizeof(entry_a2));
 420             cpu_physical_memory_write(env->pc, boot, sizeof(boot));
 421         }
 422     } else {
 423         if (flash) {
 424             MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash);
 425             MemoryRegion *flash_io = g_malloc(sizeof(*flash_io));
 426             uint32_t size = env->config->sysrom.location[0].size;
 427
 428             if (board->flash->size - board->flash->boot_base < size) {
 429                 size = board->flash->size - board->flash->boot_base;
 430             }
 431
 432             memory_region_init_alias(flash_io, NULL, "xtfpga.flash",
 433                                      flash_mr, board->flash->boot_base, size);
 434             memory_region_add_subregion(system_memory,
 435                                         env->config->sysrom.location[0].addr,
 436                                         flash_io);
 437         } else {
 438             xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom",
 439                                          system_memory);
 440         }
 441     }
 442 }
 443
 444 static const XtfpgaFlashDesc lx60_flash = {
 445     .base = 0x08000000,
 446     .size = 0x00400000,
 447     .sector_size = 0x10000,
 448 };
 449
 450 static void xtfpga_lx60_init(MachineState *machine)
 451 {
 452     static const XtfpgaBoardDesc lx60_board = {
 453         .flash = &lx60_flash,
 454         .sram_size = 0x20000,
 455     };
 456     xtfpga_init(&lx60_board, machine);
 457 }
 458
 459 static const XtfpgaFlashDesc lx200_flash = {
 460     .base = 0x08000000,
 461     .size = 0x01000000,
 462     .sector_size = 0x20000,
 463 };
 464
 465 static void xtfpga_lx200_init(MachineState *machine)
 466 {
 467     static const XtfpgaBoardDesc lx200_board = {
 468         .flash = &lx200_flash,
 469         .sram_size = 0x2000000,
 470     };
 471     xtfpga_init(&lx200_board, machine);
 472 }
 473
 474 static const XtfpgaFlashDesc ml605_flash = {
 475     .base = 0x08000000,
 476     .size = 0x01000000,
 477     .sector_size = 0x20000,
 478 };
 479
 480 static void xtfpga_ml605_init(MachineState *machine)
 481 {
 482     static const XtfpgaBoardDesc ml605_board = {
 483         .flash = &ml605_flash,
 484         .sram_size = 0x2000000,
 485     };
 486     xtfpga_init(&ml605_board, machine);
 487 }
 488
 489 static const XtfpgaFlashDesc kc705_flash = {
 490     .base = 0x00000000,
 491     .size = 0x08000000,
 492     .boot_base = 0x06000000,
 493     .sector_size = 0x20000,
 494 };
 495
 496 static void xtfpga_kc705_init(MachineState *machine)
 497 {
 498     static const XtfpgaBoardDesc kc705_board = {
 499         .flash = &kc705_flash,
 500         .sram_size = 0x2000000,
 501     };
 502     xtfpga_init(&kc705_board, machine);
 503 }
 504
 505 static void xtfpga_lx60_class_init(ObjectClass *oc, void *data)
 506 {
 507     MachineClass *mc = MACHINE_CLASS(oc);
 508
 509     mc->desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
 510     mc->init = xtfpga_lx60_init;
 511     mc->max_cpus = 4;
 512     mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
 513 }
 514
 515 static const TypeInfo xtfpga_lx60_type = {
 516     .name = MACHINE_TYPE_NAME("lx60"),
 517     .parent = TYPE_MACHINE,
 518     .class_init = xtfpga_lx60_class_init,
 519 };
 520
 521 static void xtfpga_lx200_class_init(ObjectClass *oc, void *data)
 522 {
 523     MachineClass *mc = MACHINE_CLASS(oc);
 524
 525     mc->desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
 526     mc->init = xtfpga_lx200_init;
 527     mc->max_cpus = 4;
 528     mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
 529 }
 530
 531 static const TypeInfo xtfpga_lx200_type = {
 532     .name = MACHINE_TYPE_NAME("lx200"),
 533     .parent = TYPE_MACHINE,
 534     .class_init = xtfpga_lx200_class_init,
 535 };
 536
 537 static void xtfpga_ml605_class_init(ObjectClass *oc, void *data)
 538 {
 539     MachineClass *mc = MACHINE_CLASS(oc);
 540
 541     mc->desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
 542     mc->init = xtfpga_ml605_init;
 543     mc->max_cpus = 4;
 544     mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
 545 }
 546
 547 static const TypeInfo xtfpga_ml605_type = {
 548     .name = MACHINE_TYPE_NAME("ml605"),
 549     .parent = TYPE_MACHINE,
 550     .class_init = xtfpga_ml605_class_init,
 551 };
 552
 553 static void xtfpga_kc705_class_init(ObjectClass *oc, void *data)
 554 {
 555     MachineClass *mc = MACHINE_CLASS(oc);
 556
 557     mc->desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
 558     mc->init = xtfpga_kc705_init;
 559     mc->max_cpus = 4;
 560     mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
 561 }
 562
 563 static const TypeInfo xtfpga_kc705_type = {
 564     .name = MACHINE_TYPE_NAME("kc705"),
 565     .parent = TYPE_MACHINE,
 566     .class_init = xtfpga_kc705_class_init,
 567 };
 568
 569 static void xtfpga_machines_init(void)
 570 {
 571     type_register_static(&xtfpga_lx60_type);
 572     type_register_static(&xtfpga_lx200_type);
 573     type_register_static(&xtfpga_ml605_type);
 574     type_register_static(&xtfpga_kc705_type);
 575 }
 576
 577 type_init(xtfpga_machines_init)