include/hw/arm/aspeed_soc.h

   1 /*
   2  * ASPEED SoC family
   3  *
   4  * Andrew Jeffery <andrew@aj.id.au>
   5  *
   6  * Copyright 2016 IBM Corp.
   7  *
   8  * This code is licensed under the GPL version 2 or later.  See
   9  * the COPYING file in the top-level directory.
  10  */
  11
  12 #ifndef ASPEED_SOC_H
  13 #define ASPEED_SOC_H
  14
  15 #include "hw/cpu/a15mpcore.h"
  16 #include "hw/arm/armv7m.h"
  17 #include "hw/intc/aspeed_vic.h"
  18 #include "hw/misc/aspeed_scu.h"
  19 #include "hw/adc/aspeed_adc.h"
  20 #include "hw/misc/aspeed_sdmc.h"
  21 #include "hw/misc/aspeed_xdma.h"
  22 #include "hw/timer/aspeed_timer.h"
  23 #include "hw/rtc/aspeed_rtc.h"
  24 #include "hw/i2c/aspeed_i2c.h"
  25 #include "hw/misc/aspeed_i3c.h"
  26 #include "hw/ssi/aspeed_smc.h"
  27 #include "hw/misc/aspeed_hace.h"
  28 #include "hw/misc/aspeed_sbc.h"
  29 #include "hw/watchdog/wdt_aspeed.h"
  30 #include "hw/net/ftgmac100.h"
  31 #include "target/arm/cpu.h"
  32 #include "hw/gpio/aspeed_gpio.h"
  33 #include "hw/sd/aspeed_sdhci.h"
  34 #include "hw/usb/hcd-ehci.h"
  35 #include "qom/object.h"
  36 #include "hw/misc/aspeed_lpc.h"
  37 #include "hw/misc/unimp.h"
  38 #include "hw/misc/aspeed_peci.h"
  39 #include "hw/char/serial.h"
  40
  41 #define ASPEED_SPIS_NUM  2
  42 #define ASPEED_EHCIS_NUM 2
  43 #define ASPEED_WDTS_NUM  4
  44 #define ASPEED_CPUS_NUM  2
  45 #define ASPEED_MACS_NUM  4
  46 #define ASPEED_UARTS_NUM 13
  47 #define ASPEED_JTAG_NUM  2
  48
  49 struct AspeedSoCState {
  50     DeviceState parent;
  51
  52     MemoryRegion *memory;
  53     MemoryRegion *dram_mr;
  54     MemoryRegion dram_container;
  55     MemoryRegion sram;
  56     MemoryRegion spi_boot_container;
  57     MemoryRegion spi_boot;
  58     AspeedRtcState rtc;
  59     AspeedTimerCtrlState timerctrl;
  60     AspeedI2CState i2c;
  61     AspeedI3CState i3c;
  62     AspeedSCUState scu;
  63     AspeedHACEState hace;
  64     AspeedXDMAState xdma;
  65     AspeedADCState adc;
  66     AspeedSMCState fmc;
  67     AspeedSMCState spi[ASPEED_SPIS_NUM];
  68     EHCISysBusState ehci[ASPEED_EHCIS_NUM];
  69     AspeedSBCState sbc;
  70     MemoryRegion secsram;
  71     UnimplementedDeviceState sbc_unimplemented;
  72     AspeedSDMCState sdmc;
  73     AspeedWDTState wdt[ASPEED_WDTS_NUM];
  74     FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
  75     AspeedMiiState mii[ASPEED_MACS_NUM];
  76     AspeedGPIOState gpio;
  77     AspeedGPIOState gpio_1_8v;
  78     AspeedSDHCIState sdhci;
  79     AspeedSDHCIState emmc;
  80     AspeedLPCState lpc;
  81     AspeedPECIState peci;
  82     SerialMM uart[ASPEED_UARTS_NUM];
  83     Clock *sysclk;
  84     UnimplementedDeviceState iomem;
  85     UnimplementedDeviceState video;
  86     UnimplementedDeviceState emmc_boot_controller;
  87     UnimplementedDeviceState dpmcu;
  88     UnimplementedDeviceState pwm;
  89     UnimplementedDeviceState espi;
  90     UnimplementedDeviceState udc;
  91     UnimplementedDeviceState sgpiom;
  92     UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
  93 };
  94
  95 #define TYPE_ASPEED_SOC "aspeed-soc"
  96 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
  97
  98 struct Aspeed2400SoCState {
  99     AspeedSoCState parent;
 100
 101     ARMCPU cpu[ASPEED_CPUS_NUM];
 102     AspeedVICState vic;
 103 };
 104
 105 #define TYPE_ASPEED2400_SOC "aspeed2400-soc"
 106 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC)
 107
 108 struct Aspeed2600SoCState {
 109     AspeedSoCState parent;
 110
 111     A15MPPrivState a7mpcore;
 112     ARMCPU cpu[ASPEED_CPUS_NUM]; /* XXX belong to a7mpcore */
 113 };
 114
 115 #define TYPE_ASPEED2600_SOC "aspeed2600-soc"
 116 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)
 117
 118 struct Aspeed10x0SoCState {
 119     AspeedSoCState parent;
 120
 121     ARMv7MState armv7m;
 122 };
 123
 124 #define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
 125 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC)
 126
 127 struct AspeedSoCClass {
 128     DeviceClass parent_class;
 129
 130     const char *name;
 131     /** valid_cpu_types: NULL terminated array of a single CPU type. */
 132     const char * const *valid_cpu_types;
 133     uint32_t silicon_rev;
 134     uint64_t sram_size;
 135     uint64_t secsram_size;
 136     int spis_num;
 137     int ehcis_num;
 138     int wdts_num;
 139     int macs_num;
 140     int uarts_num;
 141     const int *irqmap;
 142     const hwaddr *memmap;
 143     uint32_t num_cpus;
 144     qemu_irq (*get_irq)(AspeedSoCState *s, int dev);
 145 };
 146
 147 const char *aspeed_soc_cpu_type(AspeedSoCClass *sc);
 148
 149 enum {
 150     ASPEED_DEV_SPI_BOOT,
 151     ASPEED_DEV_IOMEM,
 152     ASPEED_DEV_UART1,
 153     ASPEED_DEV_UART2,
 154     ASPEED_DEV_UART3,
 155     ASPEED_DEV_UART4,
 156     ASPEED_DEV_UART5,
 157     ASPEED_DEV_UART6,
 158     ASPEED_DEV_UART7,
 159     ASPEED_DEV_UART8,
 160     ASPEED_DEV_UART9,
 161     ASPEED_DEV_UART10,
 162     ASPEED_DEV_UART11,
 163     ASPEED_DEV_UART12,
 164     ASPEED_DEV_UART13,
 165     ASPEED_DEV_VUART,
 166     ASPEED_DEV_FMC,
 167     ASPEED_DEV_SPI1,
 168     ASPEED_DEV_SPI2,
 169     ASPEED_DEV_EHCI1,
 170     ASPEED_DEV_EHCI2,
 171     ASPEED_DEV_VIC,
 172     ASPEED_DEV_SDMC,
 173     ASPEED_DEV_SCU,
 174     ASPEED_DEV_ADC,
 175     ASPEED_DEV_SBC,
 176     ASPEED_DEV_SECSRAM,
 177     ASPEED_DEV_EMMC_BC,
 178     ASPEED_DEV_VIDEO,
 179     ASPEED_DEV_SRAM,
 180     ASPEED_DEV_SDHCI,
 181     ASPEED_DEV_GPIO,
 182     ASPEED_DEV_GPIO_1_8V,
 183     ASPEED_DEV_RTC,
 184     ASPEED_DEV_TIMER1,
 185     ASPEED_DEV_TIMER2,
 186     ASPEED_DEV_TIMER3,
 187     ASPEED_DEV_TIMER4,
 188     ASPEED_DEV_TIMER5,
 189     ASPEED_DEV_TIMER6,
 190     ASPEED_DEV_TIMER7,
 191     ASPEED_DEV_TIMER8,
 192     ASPEED_DEV_WDT,
 193     ASPEED_DEV_PWM,
 194     ASPEED_DEV_LPC,
 195     ASPEED_DEV_IBT,
 196     ASPEED_DEV_I2C,
 197     ASPEED_DEV_PECI,
 198     ASPEED_DEV_ETH1,
 199     ASPEED_DEV_ETH2,
 200     ASPEED_DEV_ETH3,
 201     ASPEED_DEV_ETH4,
 202     ASPEED_DEV_MII1,
 203     ASPEED_DEV_MII2,
 204     ASPEED_DEV_MII3,
 205     ASPEED_DEV_MII4,
 206     ASPEED_DEV_SDRAM,
 207     ASPEED_DEV_XDMA,
 208     ASPEED_DEV_EMMC,
 209     ASPEED_DEV_KCS,
 210     ASPEED_DEV_HACE,
 211     ASPEED_DEV_DPMCU,
 212     ASPEED_DEV_DP,
 213     ASPEED_DEV_I3C,
 214     ASPEED_DEV_ESPI,
 215     ASPEED_DEV_UDC,
 216     ASPEED_DEV_SGPIOM,
 217     ASPEED_DEV_JTAG0,
 218     ASPEED_DEV_JTAG1,
 219 };
 220
 221 #define ASPEED_SOC_SPI_BOOT_ADDR 0x0
 222
 223 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev);
 224 bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp);
 225 void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr);
 226 bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp);
 227 void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr);
 228 void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
 229                                    const char *name, hwaddr addr,
 230                                    uint64_t size);
 231 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
 232                                unsigned int count, int unit0);
 233
 234 #endif /* ASPEED_SOC_H */