include/hw/i386/intel_iommu.h

   1 /*
   2  * QEMU emulation of an Intel IOMMU (VT-d)
   3  *   (DMA Remapping device)
   4  *
   5  * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
   6  * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17
  18  * You should have received a copy of the GNU General Public License along
  19  * with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #ifndef INTEL_IOMMU_H
  23 #define INTEL_IOMMU_H
  24 #include "hw/qdev.h"
  25 #include "sysemu/dma.h"
  26 #include "hw/i386/x86-iommu.h"
  27 #include "hw/i386/ioapic.h"
  28 #include "hw/pci/msi.h"
  29 #include "hw/sysbus.h"
  30 #include "qemu/iova-tree.h"
  31
  32 #define TYPE_INTEL_IOMMU_DEVICE "intel-iommu"
  33 #define INTEL_IOMMU_DEVICE(obj) \
  34      OBJECT_CHECK(IntelIOMMUState, (obj), TYPE_INTEL_IOMMU_DEVICE)
  35
  36 #define TYPE_INTEL_IOMMU_MEMORY_REGION "intel-iommu-iommu-memory-region"
  37
  38 /* DMAR Hardware Unit Definition address (IOMMU unit) */
  39 #define Q35_HOST_BRIDGE_IOMMU_ADDR  0xfed90000ULL
  40
  41 #define VTD_PCI_BUS_MAX             256
  42 #define VTD_PCI_SLOT_MAX            32
  43 #define VTD_PCI_FUNC_MAX            8
  44 #define VTD_PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  45 #define VTD_PCI_FUNC(devfn)         ((devfn) & 0x07)
  46 #define VTD_SID_TO_BUS(sid)         (((sid) >> 8) & 0xff)
  47 #define VTD_SID_TO_DEVFN(sid)       ((sid) & 0xff)
  48
  49 #define DMAR_REG_SIZE               0x230
  50 #define VTD_HOST_AW_39BIT           39
  51 #define VTD_HOST_AW_48BIT           48
  52 #define VTD_HOST_ADDRESS_WIDTH      VTD_HOST_AW_39BIT
  53 #define VTD_HAW_MASK(aw)            ((1ULL << (aw)) - 1)
  54
  55 #define DMAR_REPORT_F_INTR          (1)
  56
  57 #define  VTD_MSI_ADDR_HI_MASK        (0xffffffff00000000ULL)
  58 #define  VTD_MSI_ADDR_HI_SHIFT       (32)
  59 #define  VTD_MSI_ADDR_LO_MASK        (0x00000000ffffffffULL)
  60
  61 typedef struct VTDContextEntry VTDContextEntry;
  62 typedef struct VTDContextCacheEntry VTDContextCacheEntry;
  63 typedef struct IntelIOMMUState IntelIOMMUState;
  64 typedef struct VTDAddressSpace VTDAddressSpace;
  65 typedef struct VTDIOTLBEntry VTDIOTLBEntry;
  66 typedef struct VTDBus VTDBus;
  67 typedef union VTD_IR_TableEntry VTD_IR_TableEntry;
  68 typedef union VTD_IR_MSIAddress VTD_IR_MSIAddress;
  69 typedef struct VTDPASIDDirEntry VTDPASIDDirEntry;
  70 typedef struct VTDPASIDEntry VTDPASIDEntry;
  71
  72 /* Context-Entry */
  73 struct VTDContextEntry {
  74     union {
  75         struct {
  76             uint64_t lo;
  77             uint64_t hi;
  78         };
  79         struct {
  80             uint64_t val[4];
  81         };
  82     };
  83 };
  84
  85 struct VTDContextCacheEntry {
  86     /* The cache entry is obsolete if
  87      * context_cache_gen!=IntelIOMMUState.context_cache_gen
  88      */
  89     uint32_t context_cache_gen;
  90     struct VTDContextEntry context_entry;
  91 };
  92
  93 /* PASID Directory Entry */
  94 struct VTDPASIDDirEntry {
  95     uint64_t val;
  96 };
  97
  98 /* PASID Table Entry */
  99 struct VTDPASIDEntry {
 100     uint64_t val[8];
 101 };
 102
 103 struct VTDAddressSpace {
 104     PCIBus *bus;
 105     uint8_t devfn;
 106     AddressSpace as;
 107     IOMMUMemoryRegion iommu;
 108     MemoryRegion root;
 109     MemoryRegion sys_alias;
 110     MemoryRegion iommu_ir;      /* Interrupt region: 0xfeeXXXXX */
 111     IntelIOMMUState *iommu_state;
 112     VTDContextCacheEntry context_cache_entry;
 113     QLIST_ENTRY(VTDAddressSpace) next;
 114     /* Superset of notifier flags that this address space has */
 115     IOMMUNotifierFlag notifier_flags;
 116     IOVATree *iova_tree;          /* Traces mapped IOVA ranges */
 117 };
 118
 119 struct VTDBus {
 120     PCIBus* bus;                /* A reference to the bus to provide translation for */
 121     VTDAddressSpace *dev_as[0]; /* A table of VTDAddressSpace objects indexed by devfn */
 122 };
 123
 124 struct VTDIOTLBEntry {
 125     uint64_t gfn;
 126     uint16_t domain_id;
 127     uint64_t slpte;
 128     uint64_t mask;
 129     uint8_t access_flags;
 130 };
 131
 132 /* VT-d Source-ID Qualifier types */
 133 enum {
 134     VTD_SQ_FULL = 0x00,     /* Full SID verification */
 135     VTD_SQ_IGN_3 = 0x01,    /* Ignore bit 3 */
 136     VTD_SQ_IGN_2_3 = 0x02,  /* Ignore bits 2 & 3 */
 137     VTD_SQ_IGN_1_3 = 0x03,  /* Ignore bits 1-3 */
 138     VTD_SQ_MAX,
 139 };
 140
 141 /* VT-d Source Validation Types */
 142 enum {
 143     VTD_SVT_NONE = 0x00,    /* No validation */
 144     VTD_SVT_ALL = 0x01,     /* Do full validation */
 145     VTD_SVT_BUS = 0x02,     /* Validate bus range */
 146     VTD_SVT_MAX,
 147 };
 148
 149 /* Interrupt Remapping Table Entry Definition */
 150 union VTD_IR_TableEntry {
 151     struct {
 152 #ifdef HOST_WORDS_BIGENDIAN
 153         uint32_t __reserved_1:8;     /* Reserved 1 */
 154         uint32_t vector:8;           /* Interrupt Vector */
 155         uint32_t irte_mode:1;        /* IRTE Mode */
 156         uint32_t __reserved_0:3;     /* Reserved 0 */
 157         uint32_t __avail:4;          /* Available spaces for software */
 158         uint32_t delivery_mode:3;    /* Delivery Mode */
 159         uint32_t trigger_mode:1;     /* Trigger Mode */
 160         uint32_t redir_hint:1;       /* Redirection Hint */
 161         uint32_t dest_mode:1;        /* Destination Mode */
 162         uint32_t fault_disable:1;    /* Fault Processing Disable */
 163         uint32_t present:1;          /* Whether entry present/available */
 164 #else
 165         uint32_t present:1;          /* Whether entry present/available */
 166         uint32_t fault_disable:1;    /* Fault Processing Disable */
 167         uint32_t dest_mode:1;        /* Destination Mode */
 168         uint32_t redir_hint:1;       /* Redirection Hint */
 169         uint32_t trigger_mode:1;     /* Trigger Mode */
 170         uint32_t delivery_mode:3;    /* Delivery Mode */
 171         uint32_t __avail:4;          /* Available spaces for software */
 172         uint32_t __reserved_0:3;     /* Reserved 0 */
 173         uint32_t irte_mode:1;        /* IRTE Mode */
 174         uint32_t vector:8;           /* Interrupt Vector */
 175         uint32_t __reserved_1:8;     /* Reserved 1 */
 176 #endif
 177         uint32_t dest_id;            /* Destination ID */
 178         uint16_t source_id;          /* Source-ID */
 179 #ifdef HOST_WORDS_BIGENDIAN
 180         uint64_t __reserved_2:44;    /* Reserved 2 */
 181         uint64_t sid_vtype:2;        /* Source-ID Validation Type */
 182         uint64_t sid_q:2;            /* Source-ID Qualifier */
 183 #else
 184         uint64_t sid_q:2;            /* Source-ID Qualifier */
 185         uint64_t sid_vtype:2;        /* Source-ID Validation Type */
 186         uint64_t __reserved_2:44;    /* Reserved 2 */
 187 #endif
 188     } QEMU_PACKED irte;
 189     uint64_t data[2];
 190 };
 191
 192 #define VTD_IR_INT_FORMAT_COMPAT     (0) /* Compatible Interrupt */
 193 #define VTD_IR_INT_FORMAT_REMAP      (1) /* Remappable Interrupt */
 194
 195 /* Programming format for MSI/MSI-X addresses */
 196 union VTD_IR_MSIAddress {
 197     struct {
 198 #ifdef HOST_WORDS_BIGENDIAN
 199         uint32_t __head:12;          /* Should always be: 0x0fee */
 200         uint32_t index_l:15;         /* Interrupt index bit 14-0 */
 201         uint32_t int_mode:1;         /* Interrupt format */
 202         uint32_t sub_valid:1;        /* SHV: Sub-Handle Valid bit */
 203         uint32_t index_h:1;          /* Interrupt index bit 15 */
 204         uint32_t __not_care:2;
 205 #else
 206         uint32_t __not_care:2;
 207         uint32_t index_h:1;          /* Interrupt index bit 15 */
 208         uint32_t sub_valid:1;        /* SHV: Sub-Handle Valid bit */
 209         uint32_t int_mode:1;         /* Interrupt format */
 210         uint32_t index_l:15;         /* Interrupt index bit 14-0 */
 211         uint32_t __head:12;          /* Should always be: 0x0fee */
 212 #endif
 213     } QEMU_PACKED addr;
 214     uint32_t data;
 215 };
 216
 217 /* When IR is enabled, all MSI/MSI-X data bits should be zero */
 218 #define VTD_IR_MSI_DATA          (0)
 219
 220 /* The iommu (DMAR) device state struct */
 221 struct IntelIOMMUState {
 222     X86IOMMUState x86_iommu;
 223     MemoryRegion csrmem;
 224     uint8_t csr[DMAR_REG_SIZE];     /* register values */
 225     uint8_t wmask[DMAR_REG_SIZE];   /* R/W bytes */
 226     uint8_t w1cmask[DMAR_REG_SIZE]; /* RW1C(Write 1 to Clear) bytes */
 227     uint8_t womask[DMAR_REG_SIZE];  /* WO (write only - read returns 0) */
 228     uint32_t version;
 229
 230     bool caching_mode;          /* RO - is cap CM enabled? */
 231
 232     dma_addr_t root;                /* Current root table pointer */
 233     bool root_extended;             /* Type of root table (extended or not) */
 234     bool root_scalable;             /* Type of root table (scalable or not) */
 235     bool dmar_enabled;              /* Set if DMA remapping is enabled */
 236
 237     uint16_t iq_head;               /* Current invalidation queue head */
 238     uint16_t iq_tail;               /* Current invalidation queue tail */
 239     dma_addr_t iq;                  /* Current invalidation queue pointer */
 240     uint16_t iq_size;               /* IQ Size in number of entries */
 241     bool qi_enabled;                /* Set if the QI is enabled */
 242     uint8_t iq_last_desc_type;      /* The type of last completed descriptor */
 243
 244     /* The index of the Fault Recording Register to be used next.
 245      * Wraps around from N-1 to 0, where N is the number of FRCD_REG.
 246      */
 247     uint16_t next_frcd_reg;
 248
 249     uint64_t cap;                   /* The value of capability reg */
 250     uint64_t ecap;                  /* The value of extended capability reg */
 251
 252     uint32_t context_cache_gen;     /* Should be in [1,MAX] */
 253     GHashTable *iotlb;              /* IOTLB */
 254
 255     GHashTable *vtd_as_by_busptr;   /* VTDBus objects indexed by PCIBus* reference */
 256     VTDBus *vtd_as_by_bus_num[VTD_PCI_BUS_MAX]; /* VTDBus objects indexed by bus number */
 257     /* list of registered notifiers */
 258     QLIST_HEAD(, VTDAddressSpace) vtd_as_with_notifiers;
 259
 260     /* interrupt remapping */
 261     bool intr_enabled;              /* Whether guest enabled IR */
 262     dma_addr_t intr_root;           /* Interrupt remapping table pointer */
 263     uint32_t intr_size;             /* Number of IR table entries */
 264     bool intr_eime;                 /* Extended interrupt mode enabled */
 265     OnOffAuto intr_eim;             /* Toggle for EIM cabability */
 266     bool buggy_eim;                 /* Force buggy EIM unless eim=off */
 267     uint8_t aw_bits;                /* Host/IOVA address width (in bits) */
 268     bool dma_drain;                 /* Whether DMA r/w draining enabled */
 269
 270     /*
 271      * Protects IOMMU states in general.  Currently it protects the
 272      * per-IOMMU IOTLB cache, and context entry cache in VTDAddressSpace.
 273      */
 274     QemuMutex iommu_lock;
 275 };
 276
 277 /* Find the VTD Address space associated with the given bus pointer,
 278  * create a new one if none exists
 279  */
 280 VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn);
 281
 282 #endif