include/hw/i386/intel_iommu.h

   1 /*
   2  * QEMU emulation of an Intel IOMMU (VT-d)
   3  *   (DMA Remapping device)
   4  *
   5  * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
   6  * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17
  18  * You should have received a copy of the GNU General Public License along
  19  * with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #ifndef INTEL_IOMMU_H
  23 #define INTEL_IOMMU_H
  24 #include "hw/qdev.h"
  25 #include "sysemu/dma.h"
  26 #include "hw/i386/x86-iommu.h"
  27 #include "hw/i386/ioapic.h"
  28 #include "hw/pci/msi.h"
  29 #include "hw/sysbus.h"
  30 #include "qemu/iova-tree.h"
  31
  32 #define TYPE_INTEL_IOMMU_DEVICE "intel-iommu"
  33 #define INTEL_IOMMU_DEVICE(obj) \
  34      OBJECT_CHECK(IntelIOMMUState, (obj), TYPE_INTEL_IOMMU_DEVICE)
  35
  36 #define TYPE_INTEL_IOMMU_MEMORY_REGION "intel-iommu-iommu-memory-region"
  37
  38 /* DMAR Hardware Unit Definition address (IOMMU unit) */
  39 #define Q35_HOST_BRIDGE_IOMMU_ADDR  0xfed90000ULL
  40
  41 #define VTD_PCI_BUS_MAX             256
  42 #define VTD_PCI_SLOT_MAX            32
  43 #define VTD_PCI_FUNC_MAX            8
  44 #define VTD_PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  45 #define VTD_PCI_FUNC(devfn)         ((devfn) & 0x07)
  46 #define VTD_SID_TO_BUS(sid)         (((sid) >> 8) & 0xff)
  47 #define VTD_SID_TO_DEVFN(sid)       ((sid) & 0xff)
  48
  49 #define DMAR_REG_SIZE               0x230
  50 #define VTD_HOST_AW_39BIT           39
  51 #define VTD_HOST_AW_48BIT           48
  52 #define VTD_HOST_ADDRESS_WIDTH      VTD_HOST_AW_39BIT
  53 #define VTD_HAW_MASK(aw)            ((1ULL << (aw)) - 1)
  54
  55 #define DMAR_REPORT_F_INTR          (1)
  56
  57 #define  VTD_MSI_ADDR_HI_MASK        (0xffffffff00000000ULL)
  58 #define  VTD_MSI_ADDR_HI_SHIFT       (32)
  59 #define  VTD_MSI_ADDR_LO_MASK        (0x00000000ffffffffULL)
  60
  61 typedef struct VTDContextEntry VTDContextEntry;
  62 typedef struct VTDContextCacheEntry VTDContextCacheEntry;
  63 typedef struct IntelIOMMUState IntelIOMMUState;
  64 typedef struct VTDAddressSpace VTDAddressSpace;
  65 typedef struct VTDIOTLBEntry VTDIOTLBEntry;
  66 typedef struct VTDBus VTDBus;
  67 typedef union VTD_IR_TableEntry VTD_IR_TableEntry;
  68 typedef union VTD_IR_MSIAddress VTD_IR_MSIAddress;
  69 typedef struct VTDIrq VTDIrq;
  70 typedef struct VTD_MSIMessage VTD_MSIMessage;
  71
  72 /* Context-Entry */
  73 struct VTDContextEntry {
  74     uint64_t lo;
  75     uint64_t hi;
  76 };
  77
  78 struct VTDContextCacheEntry {
  79     /* The cache entry is obsolete if
  80      * context_cache_gen!=IntelIOMMUState.context_cache_gen
  81      */
  82     uint32_t context_cache_gen;
  83     struct VTDContextEntry context_entry;
  84 };
  85
  86 struct VTDAddressSpace {
  87     PCIBus *bus;
  88     uint8_t devfn;
  89     AddressSpace as;
  90     IOMMUMemoryRegion iommu;
  91     MemoryRegion root;
  92     MemoryRegion sys_alias;
  93     MemoryRegion iommu_ir;      /* Interrupt region: 0xfeeXXXXX */
  94     IntelIOMMUState *iommu_state;
  95     VTDContextCacheEntry context_cache_entry;
  96     QLIST_ENTRY(VTDAddressSpace) next;
  97     /* Superset of notifier flags that this address space has */
  98     IOMMUNotifierFlag notifier_flags;
  99     IOVATree *iova_tree;          /* Traces mapped IOVA ranges */
 100 };
 101
 102 struct VTDBus {
 103     PCIBus* bus;                /* A reference to the bus to provide translation for */
 104     VTDAddressSpace *dev_as[0]; /* A table of VTDAddressSpace objects indexed by devfn */
 105 };
 106
 107 struct VTDIOTLBEntry {
 108     uint64_t gfn;
 109     uint16_t domain_id;
 110     uint64_t slpte;
 111     uint64_t mask;
 112     uint8_t access_flags;
 113 };
 114
 115 /* VT-d Source-ID Qualifier types */
 116 enum {
 117     VTD_SQ_FULL = 0x00,     /* Full SID verification */
 118     VTD_SQ_IGN_3 = 0x01,    /* Ignore bit 3 */
 119     VTD_SQ_IGN_2_3 = 0x02,  /* Ignore bits 2 & 3 */
 120     VTD_SQ_IGN_1_3 = 0x03,  /* Ignore bits 1-3 */
 121     VTD_SQ_MAX,
 122 };
 123
 124 /* VT-d Source Validation Types */
 125 enum {
 126     VTD_SVT_NONE = 0x00,    /* No validation */
 127     VTD_SVT_ALL = 0x01,     /* Do full validation */
 128     VTD_SVT_BUS = 0x02,     /* Validate bus range */
 129     VTD_SVT_MAX,
 130 };
 131
 132 /* Interrupt Remapping Table Entry Definition */
 133 union VTD_IR_TableEntry {
 134     struct {
 135 #ifdef HOST_WORDS_BIGENDIAN
 136         uint32_t __reserved_1:8;     /* Reserved 1 */
 137         uint32_t vector:8;           /* Interrupt Vector */
 138         uint32_t irte_mode:1;        /* IRTE Mode */
 139         uint32_t __reserved_0:3;     /* Reserved 0 */
 140         uint32_t __avail:4;          /* Available spaces for software */
 141         uint32_t delivery_mode:3;    /* Delivery Mode */
 142         uint32_t trigger_mode:1;     /* Trigger Mode */
 143         uint32_t redir_hint:1;       /* Redirection Hint */
 144         uint32_t dest_mode:1;        /* Destination Mode */
 145         uint32_t fault_disable:1;    /* Fault Processing Disable */
 146         uint32_t present:1;          /* Whether entry present/available */
 147 #else
 148         uint32_t present:1;          /* Whether entry present/available */
 149         uint32_t fault_disable:1;    /* Fault Processing Disable */
 150         uint32_t dest_mode:1;        /* Destination Mode */
 151         uint32_t redir_hint:1;       /* Redirection Hint */
 152         uint32_t trigger_mode:1;     /* Trigger Mode */
 153         uint32_t delivery_mode:3;    /* Delivery Mode */
 154         uint32_t __avail:4;          /* Available spaces for software */
 155         uint32_t __reserved_0:3;     /* Reserved 0 */
 156         uint32_t irte_mode:1;        /* IRTE Mode */
 157         uint32_t vector:8;           /* Interrupt Vector */
 158         uint32_t __reserved_1:8;     /* Reserved 1 */
 159 #endif
 160         uint32_t dest_id;            /* Destination ID */
 161         uint16_t source_id;          /* Source-ID */
 162 #ifdef HOST_WORDS_BIGENDIAN
 163         uint64_t __reserved_2:44;    /* Reserved 2 */
 164         uint64_t sid_vtype:2;        /* Source-ID Validation Type */
 165         uint64_t sid_q:2;            /* Source-ID Qualifier */
 166 #else
 167         uint64_t sid_q:2;            /* Source-ID Qualifier */
 168         uint64_t sid_vtype:2;        /* Source-ID Validation Type */
 169         uint64_t __reserved_2:44;    /* Reserved 2 */
 170 #endif
 171     } QEMU_PACKED irte;
 172     uint64_t data[2];
 173 };
 174
 175 #define VTD_IR_INT_FORMAT_COMPAT     (0) /* Compatible Interrupt */
 176 #define VTD_IR_INT_FORMAT_REMAP      (1) /* Remappable Interrupt */
 177
 178 /* Programming format for MSI/MSI-X addresses */
 179 union VTD_IR_MSIAddress {
 180     struct {
 181 #ifdef HOST_WORDS_BIGENDIAN
 182         uint32_t __head:12;          /* Should always be: 0x0fee */
 183         uint32_t index_l:15;         /* Interrupt index bit 14-0 */
 184         uint32_t int_mode:1;         /* Interrupt format */
 185         uint32_t sub_valid:1;        /* SHV: Sub-Handle Valid bit */
 186         uint32_t index_h:1;          /* Interrupt index bit 15 */
 187         uint32_t __not_care:2;
 188 #else
 189         uint32_t __not_care:2;
 190         uint32_t index_h:1;          /* Interrupt index bit 15 */
 191         uint32_t sub_valid:1;        /* SHV: Sub-Handle Valid bit */
 192         uint32_t int_mode:1;         /* Interrupt format */
 193         uint32_t index_l:15;         /* Interrupt index bit 14-0 */
 194         uint32_t __head:12;          /* Should always be: 0x0fee */
 195 #endif
 196     } QEMU_PACKED addr;
 197     uint32_t data;
 198 };
 199
 200 /* Generic IRQ entry information */
 201 struct VTDIrq {
 202     /* Used by both IOAPIC/MSI interrupt remapping */
 203     uint8_t trigger_mode;
 204     uint8_t vector;
 205     uint8_t delivery_mode;
 206     uint32_t dest;
 207     uint8_t dest_mode;
 208
 209     /* only used by MSI interrupt remapping */
 210     uint8_t redir_hint;
 211     uint8_t msi_addr_last_bits;
 212 };
 213
 214 struct VTD_MSIMessage {
 215     union {
 216         struct {
 217 #ifdef HOST_WORDS_BIGENDIAN
 218             uint32_t __addr_head:12; /* 0xfee */
 219             uint32_t dest:8;
 220             uint32_t __reserved:8;
 221             uint32_t redir_hint:1;
 222             uint32_t dest_mode:1;
 223             uint32_t __not_used:2;
 224 #else
 225             uint32_t __not_used:2;
 226             uint32_t dest_mode:1;
 227             uint32_t redir_hint:1;
 228             uint32_t __reserved:8;
 229             uint32_t dest:8;
 230             uint32_t __addr_head:12; /* 0xfee */
 231 #endif
 232             uint32_t __addr_hi;
 233         } QEMU_PACKED;
 234         uint64_t msi_addr;
 235     };
 236     union {
 237         struct {
 238 #ifdef HOST_WORDS_BIGENDIAN
 239             uint16_t trigger_mode:1;
 240             uint16_t level:1;
 241             uint16_t __resved:3;
 242             uint16_t delivery_mode:3;
 243             uint16_t vector:8;
 244 #else
 245             uint16_t vector:8;
 246             uint16_t delivery_mode:3;
 247             uint16_t __resved:3;
 248             uint16_t level:1;
 249             uint16_t trigger_mode:1;
 250 #endif
 251             uint16_t __resved1;
 252         } QEMU_PACKED;
 253         uint32_t msi_data;
 254     };
 255 };
 256
 257 /* When IR is enabled, all MSI/MSI-X data bits should be zero */
 258 #define VTD_IR_MSI_DATA          (0)
 259
 260 /* The iommu (DMAR) device state struct */
 261 struct IntelIOMMUState {
 262     X86IOMMUState x86_iommu;
 263     MemoryRegion csrmem;
 264     uint8_t csr[DMAR_REG_SIZE];     /* register values */
 265     uint8_t wmask[DMAR_REG_SIZE];   /* R/W bytes */
 266     uint8_t w1cmask[DMAR_REG_SIZE]; /* RW1C(Write 1 to Clear) bytes */
 267     uint8_t womask[DMAR_REG_SIZE];  /* WO (write only - read returns 0) */
 268     uint32_t version;
 269
 270     bool caching_mode;          /* RO - is cap CM enabled? */
 271
 272     dma_addr_t root;                /* Current root table pointer */
 273     bool root_extended;             /* Type of root table (extended or not) */
 274     bool dmar_enabled;              /* Set if DMA remapping is enabled */
 275
 276     uint16_t iq_head;               /* Current invalidation queue head */
 277     uint16_t iq_tail;               /* Current invalidation queue tail */
 278     dma_addr_t iq;                  /* Current invalidation queue pointer */
 279     uint16_t iq_size;               /* IQ Size in number of entries */
 280     bool qi_enabled;                /* Set if the QI is enabled */
 281     uint8_t iq_last_desc_type;      /* The type of last completed descriptor */
 282
 283     /* The index of the Fault Recording Register to be used next.
 284      * Wraps around from N-1 to 0, where N is the number of FRCD_REG.
 285      */
 286     uint16_t next_frcd_reg;
 287
 288     uint64_t cap;                   /* The value of capability reg */
 289     uint64_t ecap;                  /* The value of extended capability reg */
 290
 291     uint32_t context_cache_gen;     /* Should be in [1,MAX] */
 292     GHashTable *iotlb;              /* IOTLB */
 293
 294     GHashTable *vtd_as_by_busptr;   /* VTDBus objects indexed by PCIBus* reference */
 295     VTDBus *vtd_as_by_bus_num[VTD_PCI_BUS_MAX]; /* VTDBus objects indexed by bus number */
 296     /* list of registered notifiers */
 297     QLIST_HEAD(, VTDAddressSpace) vtd_as_with_notifiers;
 298
 299     /* interrupt remapping */
 300     bool intr_enabled;              /* Whether guest enabled IR */
 301     dma_addr_t intr_root;           /* Interrupt remapping table pointer */
 302     uint32_t intr_size;             /* Number of IR table entries */
 303     bool intr_eime;                 /* Extended interrupt mode enabled */
 304     OnOffAuto intr_eim;             /* Toggle for EIM cabability */
 305     bool buggy_eim;                 /* Force buggy EIM unless eim=off */
 306     uint8_t aw_bits;                /* Host/IOVA address width (in bits) */
 307
 308     /*
 309      * Protects IOMMU states in general.  Currently it protects the
 310      * per-IOMMU IOTLB cache, and context entry cache in VTDAddressSpace.
 311      */
 312     QemuMutex iommu_lock;
 313 };
 314
 315 /* Find the VTD Address space associated with the given bus pointer,
 316  * create a new one if none exists
 317  */
 318 VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn);
 319
 320 #endif