include/hw/i386/intel_iommu.h

   1 /*
   2  * QEMU emulation of an Intel IOMMU (VT-d)
   3  *   (DMA Remapping device)
   4  *
   5  * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
   6  * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17
  18  * You should have received a copy of the GNU General Public License along
  19  * with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #ifndef INTEL_IOMMU_H
  23 #define INTEL_IOMMU_H
  24 #include "hw/qdev.h"
  25 #include "sysemu/dma.h"
  26 #include "hw/i386/x86-iommu.h"
  27 #include "hw/i386/ioapic.h"
  28 #include "hw/pci/msi.h"
  29 #include "hw/sysbus.h"
  30
  31 #define TYPE_INTEL_IOMMU_DEVICE "intel-iommu"
  32 #define INTEL_IOMMU_DEVICE(obj) \
  33      OBJECT_CHECK(IntelIOMMUState, (obj), TYPE_INTEL_IOMMU_DEVICE)
  34
  35 /* DMAR Hardware Unit Definition address (IOMMU unit) */
  36 #define Q35_HOST_BRIDGE_IOMMU_ADDR  0xfed90000ULL
  37
  38 #define VTD_PCI_BUS_MAX             256
  39 #define VTD_PCI_SLOT_MAX            32
  40 #define VTD_PCI_FUNC_MAX            8
  41 #define VTD_PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  42 #define VTD_PCI_FUNC(devfn)         ((devfn) & 0x07)
  43 #define VTD_SID_TO_BUS(sid)         (((sid) >> 8) & 0xff)
  44 #define VTD_SID_TO_DEVFN(sid)       ((sid) & 0xff)
  45
  46 #define DMAR_REG_SIZE               0x230
  47 #define VTD_HOST_ADDRESS_WIDTH      39
  48 #define VTD_HAW_MASK                ((1ULL << VTD_HOST_ADDRESS_WIDTH) - 1)
  49
  50 #define DMAR_REPORT_F_INTR          (1)
  51
  52 #define  VTD_MSI_ADDR_HI_MASK        (0xffffffff00000000ULL)
  53 #define  VTD_MSI_ADDR_HI_SHIFT       (32)
  54 #define  VTD_MSI_ADDR_LO_MASK        (0x00000000ffffffffULL)
  55
  56 typedef struct VTDContextEntry VTDContextEntry;
  57 typedef struct VTDContextCacheEntry VTDContextCacheEntry;
  58 typedef struct IntelIOMMUState IntelIOMMUState;
  59 typedef struct VTDAddressSpace VTDAddressSpace;
  60 typedef struct VTDIOTLBEntry VTDIOTLBEntry;
  61 typedef struct VTDBus VTDBus;
  62 typedef union VTD_IRTE VTD_IRTE;
  63 typedef union VTD_IR_MSIAddress VTD_IR_MSIAddress;
  64 typedef struct VTDIrq VTDIrq;
  65 typedef struct VTD_MSIMessage VTD_MSIMessage;
  66
  67 /* Context-Entry */
  68 struct VTDContextEntry {
  69     uint64_t lo;
  70     uint64_t hi;
  71 };
  72
  73 struct VTDContextCacheEntry {
  74     /* The cache entry is obsolete if
  75      * context_cache_gen!=IntelIOMMUState.context_cache_gen
  76      */
  77     uint32_t context_cache_gen;
  78     struct VTDContextEntry context_entry;
  79 };
  80
  81 struct VTDAddressSpace {
  82     PCIBus *bus;
  83     uint8_t devfn;
  84     AddressSpace as;
  85     MemoryRegion iommu;
  86     MemoryRegion iommu_ir;      /* Interrupt region: 0xfeeXXXXX */
  87     IntelIOMMUState *iommu_state;
  88     VTDContextCacheEntry context_cache_entry;
  89 };
  90
  91 struct VTDBus {
  92     PCIBus* bus;                /* A reference to the bus to provide translation for */
  93     VTDAddressSpace *dev_as[0]; /* A table of VTDAddressSpace objects indexed by devfn */
  94 };
  95
  96 struct VTDIOTLBEntry {
  97     uint64_t gfn;
  98     uint16_t domain_id;
  99     uint64_t slpte;
 100     uint64_t mask;
 101     bool read_flags;
 102     bool write_flags;
 103 };
 104
 105 /* Interrupt Remapping Table Entry Definition */
 106 union VTD_IRTE {
 107     struct {
 108 #ifdef HOST_WORDS_BIGENDIAN
 109         uint32_t dest_id:32;         /* Destination ID */
 110         uint32_t __reserved_1:8;     /* Reserved 1 */
 111         uint32_t vector:8;           /* Interrupt Vector */
 112         uint32_t irte_mode:1;        /* IRTE Mode */
 113         uint32_t __reserved_0:3;     /* Reserved 0 */
 114         uint32_t __avail:4;          /* Available spaces for software */
 115         uint32_t delivery_mode:3;    /* Delivery Mode */
 116         uint32_t trigger_mode:1;     /* Trigger Mode */
 117         uint32_t redir_hint:1;       /* Redirection Hint */
 118         uint32_t dest_mode:1;        /* Destination Mode */
 119         uint32_t fault_disable:1;    /* Fault Processing Disable */
 120         uint32_t present:1;          /* Whether entry present/available */
 121 #else
 122         uint32_t present:1;          /* Whether entry present/available */
 123         uint32_t fault_disable:1;    /* Fault Processing Disable */
 124         uint32_t dest_mode:1;        /* Destination Mode */
 125         uint32_t redir_hint:1;       /* Redirection Hint */
 126         uint32_t trigger_mode:1;     /* Trigger Mode */
 127         uint32_t delivery_mode:3;    /* Delivery Mode */
 128         uint32_t __avail:4;          /* Available spaces for software */
 129         uint32_t __reserved_0:3;     /* Reserved 0 */
 130         uint32_t irte_mode:1;        /* IRTE Mode */
 131         uint32_t vector:8;           /* Interrupt Vector */
 132         uint32_t __reserved_1:8;     /* Reserved 1 */
 133         uint32_t dest_id:32;         /* Destination ID */
 134 #endif
 135         uint16_t source_id:16;       /* Source-ID */
 136 #ifdef HOST_WORDS_BIGENDIAN
 137         uint64_t __reserved_2:44;    /* Reserved 2 */
 138         uint64_t sid_vtype:2;        /* Source-ID Validation Type */
 139         uint64_t sid_q:2;            /* Source-ID Qualifier */
 140 #else
 141         uint64_t sid_q:2;            /* Source-ID Qualifier */
 142         uint64_t sid_vtype:2;        /* Source-ID Validation Type */
 143         uint64_t __reserved_2:44;    /* Reserved 2 */
 144 #endif
 145     } QEMU_PACKED;
 146     uint64_t data[2];
 147 };
 148
 149 #define VTD_IR_INT_FORMAT_COMPAT     (0) /* Compatible Interrupt */
 150 #define VTD_IR_INT_FORMAT_REMAP      (1) /* Remappable Interrupt */
 151
 152 /* Programming format for MSI/MSI-X addresses */
 153 union VTD_IR_MSIAddress {
 154     struct {
 155 #ifdef HOST_WORDS_BIGENDIAN
 156         uint32_t __head:12;          /* Should always be: 0x0fee */
 157         uint32_t index_l:15;         /* Interrupt index bit 14-0 */
 158         uint32_t int_mode:1;         /* Interrupt format */
 159         uint32_t sub_valid:1;        /* SHV: Sub-Handle Valid bit */
 160         uint32_t index_h:1;          /* Interrupt index bit 15 */
 161         uint32_t __not_care:2;
 162 #else
 163         uint32_t __not_care:2;
 164         uint32_t index_h:1;          /* Interrupt index bit 15 */
 165         uint32_t sub_valid:1;        /* SHV: Sub-Handle Valid bit */
 166         uint32_t int_mode:1;         /* Interrupt format */
 167         uint32_t index_l:15;         /* Interrupt index bit 14-0 */
 168         uint32_t __head:12;          /* Should always be: 0x0fee */
 169 #endif
 170     } QEMU_PACKED;
 171     uint32_t data;
 172 };
 173
 174 /* Generic IRQ entry information */
 175 struct VTDIrq {
 176     /* Used by both IOAPIC/MSI interrupt remapping */
 177     uint8_t trigger_mode;
 178     uint8_t vector;
 179     uint8_t delivery_mode;
 180     uint32_t dest;
 181     uint8_t dest_mode;
 182
 183     /* only used by MSI interrupt remapping */
 184     uint8_t redir_hint;
 185     uint8_t msi_addr_last_bits;
 186 };
 187
 188 struct VTD_MSIMessage {
 189     union {
 190         struct {
 191 #ifdef HOST_WORDS_BIGENDIAN
 192             uint32_t __addr_head:12; /* 0xfee */
 193             uint32_t dest:8;
 194             uint32_t __reserved:8;
 195             uint32_t redir_hint:1;
 196             uint32_t dest_mode:1;
 197             uint32_t __not_used:2;
 198 #else
 199             uint32_t __not_used:2;
 200             uint32_t dest_mode:1;
 201             uint32_t redir_hint:1;
 202             uint32_t __reserved:8;
 203             uint32_t dest:8;
 204             uint32_t __addr_head:12; /* 0xfee */
 205 #endif
 206             uint32_t __addr_hi:32;
 207         } QEMU_PACKED;
 208         uint64_t msi_addr;
 209     };
 210     union {
 211         struct {
 212 #ifdef HOST_WORDS_BIGENDIAN
 213             uint16_t trigger_mode:1;
 214             uint16_t level:1;
 215             uint16_t __resved:3;
 216             uint16_t delivery_mode:3;
 217             uint16_t vector:8;
 218 #else
 219             uint16_t vector:8;
 220             uint16_t delivery_mode:3;
 221             uint16_t __resved:3;
 222             uint16_t level:1;
 223             uint16_t trigger_mode:1;
 224 #endif
 225             uint16_t __resved1:16;
 226         } QEMU_PACKED;
 227         uint32_t msi_data;
 228     };
 229 };
 230
 231 /* When IR is enabled, all MSI/MSI-X data bits should be zero */
 232 #define VTD_IR_MSI_DATA          (0)
 233
 234 /* The iommu (DMAR) device state struct */
 235 struct IntelIOMMUState {
 236     X86IOMMUState x86_iommu;
 237     MemoryRegion csrmem;
 238     uint8_t csr[DMAR_REG_SIZE];     /* register values */
 239     uint8_t wmask[DMAR_REG_SIZE];   /* R/W bytes */
 240     uint8_t w1cmask[DMAR_REG_SIZE]; /* RW1C(Write 1 to Clear) bytes */
 241     uint8_t womask[DMAR_REG_SIZE];  /* WO (write only - read returns 0) */
 242     uint32_t version;
 243
 244     dma_addr_t root;                /* Current root table pointer */
 245     bool root_extended;             /* Type of root table (extended or not) */
 246     bool dmar_enabled;              /* Set if DMA remapping is enabled */
 247
 248     uint16_t iq_head;               /* Current invalidation queue head */
 249     uint16_t iq_tail;               /* Current invalidation queue tail */
 250     dma_addr_t iq;                  /* Current invalidation queue pointer */
 251     uint16_t iq_size;               /* IQ Size in number of entries */
 252     bool qi_enabled;                /* Set if the QI is enabled */
 253     uint8_t iq_last_desc_type;      /* The type of last completed descriptor */
 254
 255     /* The index of the Fault Recording Register to be used next.
 256      * Wraps around from N-1 to 0, where N is the number of FRCD_REG.
 257      */
 258     uint16_t next_frcd_reg;
 259
 260     uint64_t cap;                   /* The value of capability reg */
 261     uint64_t ecap;                  /* The value of extended capability reg */
 262
 263     uint32_t context_cache_gen;     /* Should be in [1,MAX] */
 264     GHashTable *iotlb;              /* IOTLB */
 265
 266     MemoryRegionIOMMUOps iommu_ops;
 267     GHashTable *vtd_as_by_busptr;   /* VTDBus objects indexed by PCIBus* reference */
 268     VTDBus *vtd_as_by_bus_num[VTD_PCI_BUS_MAX]; /* VTDBus objects indexed by bus number */
 269
 270     /* interrupt remapping */
 271     bool intr_enabled;              /* Whether guest enabled IR */
 272     dma_addr_t intr_root;           /* Interrupt remapping table pointer */
 273     uint32_t intr_size;             /* Number of IR table entries */
 274 };
 275
 276 /* Find the VTD Address space associated with the given bus pointer,
 277  * create a new one if none exists
 278  */
 279 VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn);
 280
 281 #endif