include/hw/i386/pc.h

   1 #ifndef HW_PC_H
   2 #define HW_PC_H
   3
   4 #include "exec/memory.h"
   5 #include "hw/boards.h"
   6 #include "hw/isa/isa.h"
   7 #include "hw/block/fdc.h"
   8 #include "hw/block/flash.h"
   9 #include "net/net.h"
  10 #include "hw/i386/ioapic.h"
  11
  12 #include "qemu/range.h"
  13 #include "qemu/bitmap.h"
  14 #include "qemu/module.h"
  15 #include "sysemu/sysemu.h"
  16 #include "hw/pci/pci.h"
  17 #include "hw/mem/pc-dimm.h"
  18 #include "hw/mem/nvdimm.h"
  19 #include "hw/acpi/acpi_dev_interface.h"
  20
  21 #define HPET_INTCAP "hpet-intcap"
  22
  23 /**
  24  * PCMachineState:
  25  * @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling
  26  * @boot_cpus: number of present VCPUs
  27  */
  28 struct PCMachineState {
  29     /*< private >*/
  30     MachineState parent_obj;
  31
  32     /* <public> */
  33
  34     /* State for other subsystems/APIs: */
  35     Notifier machine_done;
  36
  37     /* Pointers to devices and objects: */
  38     HotplugHandler *acpi_dev;
  39     ISADevice *rtc;
  40     PCIBus *bus;
  41     FWCfgState *fw_cfg;
  42     qemu_irq *gsi;
  43     PFlashCFI01 *flash[2];
  44
  45     /* Configuration options: */
  46     uint64_t max_ram_below_4g;
  47     OnOffAuto vmport;
  48     OnOffAuto smm;
  49
  50     bool acpi_build_enabled;
  51     bool smbus_enabled;
  52     bool sata_enabled;
  53     bool pit_enabled;
  54
  55     /* RAM information (sizes, addresses, configuration): */
  56     ram_addr_t below_4g_mem_size, above_4g_mem_size;
  57
  58     /* CPU and apic information: */
  59     bool apic_xrupt_override;
  60     unsigned apic_id_limit;
  61     uint16_t boot_cpus;
  62
  63     /* NUMA information: */
  64     uint64_t numa_nodes;
  65     uint64_t *node_mem;
  66
  67     /* Address space used by IOAPIC device. All IOAPIC interrupts
  68      * will be translated to MSI messages in the address space. */
  69     AddressSpace *ioapic_as;
  70 };
  71
  72 #define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device"
  73 #define PC_MACHINE_DEVMEM_REGION_SIZE "device-memory-region-size"
  74 #define PC_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g"
  75 #define PC_MACHINE_VMPORT           "vmport"
  76 #define PC_MACHINE_SMM              "smm"
  77 #define PC_MACHINE_SMBUS            "smbus"
  78 #define PC_MACHINE_SATA             "sata"
  79 #define PC_MACHINE_PIT              "pit"
  80
  81 /**
  82  * PCMachineClass:
  83  *
  84  * Compat fields:
  85  *
  86  * @enforce_aligned_dimm: check that DIMM's address/size is aligned by
  87  *                        backend's alignment value if provided
  88  * @acpi_data_size: Size of the chunk of memory at the top of RAM
  89  *                  for the BIOS ACPI tables and other BIOS
  90  *                  datastructures.
  91  * @gigabyte_align: Make sure that guest addresses aligned at
  92  *                  1Gbyte boundaries get mapped to host
  93  *                  addresses aligned at 1Gbyte boundaries. This
  94  *                  way we can use 1GByte pages in the host.
  95  *
  96  */
  97 typedef struct PCMachineClass {
  98     /*< private >*/
  99     MachineClass parent_class;
 100
 101     /*< public >*/
 102
 103     /* Device configuration: */
 104     bool pci_enabled;
 105     bool kvmclock_enabled;
 106     const char *default_nic_model;
 107
 108     /* Compat options: */
 109
 110     /* ACPI compat: */
 111     bool has_acpi_build;
 112     bool rsdp_in_ram;
 113     int legacy_acpi_table_size;
 114     unsigned acpi_data_size;
 115
 116     /* SMBIOS compat: */
 117     bool smbios_defaults;
 118     bool smbios_legacy_mode;
 119     bool smbios_uuid_encoded;
 120
 121     /* RAM / address space compat: */
 122     bool gigabyte_align;
 123     bool has_reserved_memory;
 124     bool enforce_aligned_dimm;
 125     bool broken_reserved_end;
 126
 127     /* TSC rate migration: */
 128     bool save_tsc_khz;
 129     /* generate legacy CPU hotplug AML */
 130     bool legacy_cpu_hotplug;
 131
 132     /* use DMA capable linuxboot option rom */
 133     bool linuxboot_dma_enabled;
 134
 135     /* use PVH to load kernels that support this feature */
 136     bool pvh_enabled;
 137
 138     /* Enables contiguous-apic-ID mode */
 139     bool compat_apic_id_mode;
 140 } PCMachineClass;
 141
 142 #define TYPE_PC_MACHINE "generic-pc-machine"
 143 #define PC_MACHINE(obj) \
 144     OBJECT_CHECK(PCMachineState, (obj), TYPE_PC_MACHINE)
 145 #define PC_MACHINE_GET_CLASS(obj) \
 146     OBJECT_GET_CLASS(PCMachineClass, (obj), TYPE_PC_MACHINE)
 147 #define PC_MACHINE_CLASS(klass) \
 148     OBJECT_CLASS_CHECK(PCMachineClass, (klass), TYPE_PC_MACHINE)
 149
 150 /* i8259.c */
 151
 152 extern DeviceState *isa_pic;
 153 qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
 154 qemu_irq *kvm_i8259_init(ISABus *bus);
 155 int pic_read_irq(DeviceState *d);
 156 int pic_get_output(DeviceState *d);
 157
 158 /* ioapic.c */
 159
 160 /* Global System Interrupts */
 161
 162 #define GSI_NUM_PINS IOAPIC_NUM_PINS
 163
 164 typedef struct GSIState {
 165     qemu_irq i8259_irq[ISA_NUM_IRQS];
 166     qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
 167 } GSIState;
 168
 169 void gsi_handler(void *opaque, int n, int level);
 170
 171 /* vmport.c */
 172 #define TYPE_VMPORT "vmport"
 173 typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address);
 174
 175 static inline void vmport_init(ISABus *bus)
 176 {
 177     isa_create_simple(bus, TYPE_VMPORT);
 178 }
 179
 180 void vmport_register(unsigned char command, VMPortReadFunc *func, void *opaque);
 181 void vmmouse_get_data(uint32_t *data);
 182 void vmmouse_set_data(const uint32_t *data);
 183
 184 /* pc.c */
 185 extern int fd_bootchk;
 186
 187 bool pc_machine_is_smm_enabled(PCMachineState *pcms);
 188 void pc_register_ferr_irq(qemu_irq irq);
 189 void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
 190
 191 void pc_cpus_init(PCMachineState *pcms);
 192 void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp);
 193
 194 void pc_guest_info_init(PCMachineState *pcms);
 195
 196 #define PCI_HOST_PROP_PCI_HOLE_START   "pci-hole-start"
 197 #define PCI_HOST_PROP_PCI_HOLE_END     "pci-hole-end"
 198 #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start"
 199 #define PCI_HOST_PROP_PCI_HOLE64_END   "pci-hole64-end"
 200 #define PCI_HOST_PROP_PCI_HOLE64_SIZE  "pci-hole64-size"
 201 #define PCI_HOST_BELOW_4G_MEM_SIZE     "below-4g-mem-size"
 202 #define PCI_HOST_ABOVE_4G_MEM_SIZE     "above-4g-mem-size"
 203
 204
 205 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
 206                             MemoryRegion *pci_address_space);
 207
 208 void xen_load_linux(PCMachineState *pcms);
 209 void pc_memory_init(PCMachineState *pcms,
 210                     MemoryRegion *system_memory,
 211                     MemoryRegion *rom_memory,
 212                     MemoryRegion **ram_memory);
 213 uint64_t pc_pci_hole64_start(void);
 214 qemu_irq pc_allocate_cpu_irq(void);
 215 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
 216 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
 217                           ISADevice **rtc_state,
 218                           bool create_fdctrl,
 219                           bool no_vmport,
 220                           bool has_pit,
 221                           uint32_t hpet_irqs);
 222 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd);
 223 void pc_cmos_init(PCMachineState *pcms,
 224                   BusState *ide0, BusState *ide1,
 225                   ISADevice *s);
 226 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus);
 227 void pc_pci_device_init(PCIBus *pci_bus);
 228
 229 typedef void (*cpu_set_smm_t)(int smm, void *arg);
 230
 231 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
 232
 233 ISADevice *pc_find_fdc0(void);
 234 int cmos_get_fd_drive_type(FloppyDriveType fd0);
 235
 236 #define FW_CFG_IO_BASE     0x510
 237
 238 #define PORT92_A20_LINE "a20"
 239
 240 /* acpi_piix.c */
 241
 242 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 243                       qemu_irq sci_irq, qemu_irq smi_irq,
 244                       int smm_enabled, DeviceState **piix4_pm);
 245
 246 /* hpet.c */
 247 extern int no_hpet;
 248
 249 /* piix_pci.c */
 250 struct PCII440FXState;
 251 typedef struct PCII440FXState PCII440FXState;
 252
 253 #define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
 254 #define TYPE_I440FX_PCI_DEVICE "i440FX"
 255
 256 #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
 257
 258 /*
 259  * Reset Control Register: PCI-accessible ISA-Compatible Register at address
 260  * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
 261  */
 262 #define RCR_IOPORT 0xcf9
 263
 264 PCIBus *i440fx_init(const char *host_type, const char *pci_type,
 265                     PCII440FXState **pi440fx_state, int *piix_devfn,
 266                     ISABus **isa_bus, qemu_irq *pic,
 267                     MemoryRegion *address_space_mem,
 268                     MemoryRegion *address_space_io,
 269                     ram_addr_t ram_size,
 270                     ram_addr_t below_4g_mem_size,
 271                     ram_addr_t above_4g_mem_size,
 272                     MemoryRegion *pci_memory,
 273                     MemoryRegion *ram_memory);
 274
 275 PCIBus *find_i440fx(void);
 276 /* piix4.c */
 277 extern PCIDevice *piix4_dev;
 278 int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
 279
 280 /* pc_sysfw.c */
 281 void pc_system_flash_create(PCMachineState *pcms);
 282 void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory);
 283
 284 /* acpi-build.c */
 285 void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
 286                        const CPUArchIdList *apic_ids, GArray *entry);
 287
 288 /* e820 types */
 289 #define E820_RAM        1
 290 #define E820_RESERVED   2
 291 #define E820_ACPI       3
 292 #define E820_NVS        4
 293 #define E820_UNUSABLE   5
 294
 295 int e820_add_entry(uint64_t, uint64_t, uint32_t);
 296 int e820_get_num_entries(void);
 297 bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
 298
 299 extern GlobalProperty pc_compat_4_0[];
 300 extern const size_t pc_compat_4_0_len;
 301
 302 extern GlobalProperty pc_compat_3_1[];
 303 extern const size_t pc_compat_3_1_len;
 304
 305 extern GlobalProperty pc_compat_3_0[];
 306 extern const size_t pc_compat_3_0_len;
 307
 308 extern GlobalProperty pc_compat_2_12[];
 309 extern const size_t pc_compat_2_12_len;
 310
 311 extern GlobalProperty pc_compat_2_11[];
 312 extern const size_t pc_compat_2_11_len;
 313
 314 extern GlobalProperty pc_compat_2_10[];
 315 extern const size_t pc_compat_2_10_len;
 316
 317 extern GlobalProperty pc_compat_2_9[];
 318 extern const size_t pc_compat_2_9_len;
 319
 320 extern GlobalProperty pc_compat_2_8[];
 321 extern const size_t pc_compat_2_8_len;
 322
 323 extern GlobalProperty pc_compat_2_7[];
 324 extern const size_t pc_compat_2_7_len;
 325
 326 extern GlobalProperty pc_compat_2_6[];
 327 extern const size_t pc_compat_2_6_len;
 328
 329 extern GlobalProperty pc_compat_2_5[];
 330 extern const size_t pc_compat_2_5_len;
 331
 332 extern GlobalProperty pc_compat_2_4[];
 333 extern const size_t pc_compat_2_4_len;
 334
 335 extern GlobalProperty pc_compat_2_3[];
 336 extern const size_t pc_compat_2_3_len;
 337
 338 extern GlobalProperty pc_compat_2_2[];
 339 extern const size_t pc_compat_2_2_len;
 340
 341 extern GlobalProperty pc_compat_2_1[];
 342 extern const size_t pc_compat_2_1_len;
 343
 344 extern GlobalProperty pc_compat_2_0[];
 345 extern const size_t pc_compat_2_0_len;
 346
 347 extern GlobalProperty pc_compat_1_7[];
 348 extern const size_t pc_compat_1_7_len;
 349
 350 extern GlobalProperty pc_compat_1_6[];
 351 extern const size_t pc_compat_1_6_len;
 352
 353 extern GlobalProperty pc_compat_1_5[];
 354 extern const size_t pc_compat_1_5_len;
 355
 356 extern GlobalProperty pc_compat_1_4[];
 357 extern const size_t pc_compat_1_4_len;
 358
 359 /* Helper for setting model-id for CPU models that changed model-id
 360  * depending on QEMU versions up to QEMU 2.4.
 361  */
 362 #define PC_CPU_MODEL_IDS(v) \
 363     { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
 364     { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
 365     { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },
 366
 367 #define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \
 368     static void pc_machine_##suffix##_class_init(ObjectClass *oc, void *data) \
 369     { \
 370         MachineClass *mc = MACHINE_CLASS(oc); \
 371         optsfn(mc); \
 372         mc->init = initfn; \
 373     } \
 374     static const TypeInfo pc_machine_type_##suffix = { \
 375         .name       = namestr TYPE_MACHINE_SUFFIX, \
 376         .parent     = TYPE_PC_MACHINE, \
 377         .class_init = pc_machine_##suffix##_class_init, \
 378     }; \
 379     static void pc_machine_init_##suffix(void) \
 380     { \
 381         type_register(&pc_machine_type_##suffix); \
 382     } \
 383     type_init(pc_machine_init_##suffix)
 384
 385 extern void igd_passthrough_isa_bridge_create(PCIBus *bus, uint16_t gpu_dev_id);
 386 #endif