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Introduce and use cache-utils.[ch]
[mirror_qemu.git] / linux-user / main.c
1 /*
2 * qemu user main
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20 #include <stdlib.h>
21 #include <stdio.h>
22 #include <stdarg.h>
23 #include <string.h>
24 #include <errno.h>
25 #include <unistd.h>
26 #include <sys/mman.h>
27
28 #include "qemu.h"
29 #include "qemu-common.h"
30 #include "cache-utils.h"
31 /* For tb_lock */
32 #include "exec-all.h"
33
34 #define DEBUG_LOGFILE "/tmp/qemu.log"
35
36 static const char *interp_prefix = CONFIG_QEMU_PREFIX;
37 const char *qemu_uname_release = CONFIG_UNAME_RELEASE;
38
39 #if defined(__i386__) && !defined(CONFIG_STATIC)
40 /* Force usage of an ELF interpreter even if it is an ELF shared
41 object ! */
42 const char interp[] __attribute__((section(".interp"))) = "/lib/ld-linux.so.2";
43 #endif
44
45 /* for recent libc, we add these dummy symbols which are not declared
46 when generating a linked object (bug in ld ?) */
47 #if (__GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 3)) && !defined(CONFIG_STATIC)
48 asm(".globl __preinit_array_start\n"
49 ".globl __preinit_array_end\n"
50 ".globl __init_array_start\n"
51 ".globl __init_array_end\n"
52 ".globl __fini_array_start\n"
53 ".globl __fini_array_end\n"
54 ".section \".rodata\"\n"
55 "__preinit_array_start:\n"
56 "__preinit_array_end:\n"
57 "__init_array_start:\n"
58 "__init_array_end:\n"
59 "__fini_array_start:\n"
60 "__fini_array_end:\n"
61 ".long 0\n"
62 ".previous\n");
63 #endif
64
65 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
66 we allocate a bigger stack. Need a better solution, for example
67 by remapping the process stack directly at the right place */
68 unsigned long x86_stack_size = 512 * 1024;
69
70 void gemu_log(const char *fmt, ...)
71 {
72 va_list ap;
73
74 va_start(ap, fmt);
75 vfprintf(stderr, fmt, ap);
76 va_end(ap);
77 }
78
79 void cpu_outb(CPUState *env, int addr, int val)
80 {
81 fprintf(stderr, "outb: port=0x%04x, data=%02x\n", addr, val);
82 }
83
84 void cpu_outw(CPUState *env, int addr, int val)
85 {
86 fprintf(stderr, "outw: port=0x%04x, data=%04x\n", addr, val);
87 }
88
89 void cpu_outl(CPUState *env, int addr, int val)
90 {
91 fprintf(stderr, "outl: port=0x%04x, data=%08x\n", addr, val);
92 }
93
94 int cpu_inb(CPUState *env, int addr)
95 {
96 fprintf(stderr, "inb: port=0x%04x\n", addr);
97 return 0;
98 }
99
100 int cpu_inw(CPUState *env, int addr)
101 {
102 fprintf(stderr, "inw: port=0x%04x\n", addr);
103 return 0;
104 }
105
106 int cpu_inl(CPUState *env, int addr)
107 {
108 fprintf(stderr, "inl: port=0x%04x\n", addr);
109 return 0;
110 }
111
112 #if defined(TARGET_I386)
113 int cpu_get_pic_interrupt(CPUState *env)
114 {
115 return -1;
116 }
117 #endif
118
119 /* timers for rdtsc */
120
121 #if 0
122
123 static uint64_t emu_time;
124
125 int64_t cpu_get_real_ticks(void)
126 {
127 return emu_time++;
128 }
129
130 #endif
131
132 #if defined(USE_NPTL)
133 /***********************************************************/
134 /* Helper routines for implementing atomic operations. */
135
136 /* To implement exclusive operations we force all cpus to syncronise.
137 We don't require a full sync, only that no cpus are executing guest code.
138 The alternative is to map target atomic ops onto host equivalents,
139 which requires quite a lot of per host/target work. */
140 static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
141 static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
142 static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
143 static int pending_cpus;
144
145 /* Make sure everything is in a consistent state for calling fork(). */
146 void fork_start(void)
147 {
148 mmap_fork_start();
149 pthread_mutex_lock(&tb_lock);
150 pthread_mutex_lock(&exclusive_lock);
151 }
152
153 void fork_end(int child)
154 {
155 if (child) {
156 /* Child processes created by fork() only have a single thread.
157 Discard information about the parent threads. */
158 first_cpu = thread_env;
159 thread_env->next_cpu = NULL;
160 pending_cpus = 0;
161 pthread_mutex_init(&exclusive_lock, NULL);
162 pthread_cond_init(&exclusive_cond, NULL);
163 pthread_cond_init(&exclusive_resume, NULL);
164 pthread_mutex_init(&tb_lock, NULL);
165 } else {
166 pthread_mutex_unlock(&exclusive_lock);
167 pthread_mutex_unlock(&tb_lock);
168 }
169 mmap_fork_end(child);
170 }
171
172 /* Wait for pending exclusive operations to complete. The exclusive lock
173 must be held. */
174 static inline void exclusive_idle(void)
175 {
176 while (pending_cpus) {
177 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
178 }
179 }
180
181 /* Start an exclusive operation.
182 Must only be called from outside cpu_arm_exec. */
183 static inline void start_exclusive(void)
184 {
185 CPUState *other;
186 pthread_mutex_lock(&exclusive_lock);
187 exclusive_idle();
188
189 pending_cpus = 1;
190 /* Make all other cpus stop executing. */
191 for (other = first_cpu; other; other = other->next_cpu) {
192 if (other->running) {
193 pending_cpus++;
194 cpu_interrupt(other, CPU_INTERRUPT_EXIT);
195 }
196 }
197 if (pending_cpus > 1) {
198 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
199 }
200 }
201
202 /* Finish an exclusive operation. */
203 static inline void end_exclusive(void)
204 {
205 pending_cpus = 0;
206 pthread_cond_broadcast(&exclusive_resume);
207 pthread_mutex_unlock(&exclusive_lock);
208 }
209
210 /* Wait for exclusive ops to finish, and begin cpu execution. */
211 static inline void cpu_exec_start(CPUState *env)
212 {
213 pthread_mutex_lock(&exclusive_lock);
214 exclusive_idle();
215 env->running = 1;
216 pthread_mutex_unlock(&exclusive_lock);
217 }
218
219 /* Mark cpu as not executing, and release pending exclusive ops. */
220 static inline void cpu_exec_end(CPUState *env)
221 {
222 pthread_mutex_lock(&exclusive_lock);
223 env->running = 0;
224 if (pending_cpus > 1) {
225 pending_cpus--;
226 if (pending_cpus == 1) {
227 pthread_cond_signal(&exclusive_cond);
228 }
229 }
230 exclusive_idle();
231 pthread_mutex_unlock(&exclusive_lock);
232 }
233 #else /* if !USE_NPTL */
234 /* These are no-ops because we are not threadsafe. */
235 static inline void cpu_exec_start(CPUState *env)
236 {
237 }
238
239 static inline void cpu_exec_end(CPUState *env)
240 {
241 }
242
243 static inline void start_exclusive(void)
244 {
245 }
246
247 static inline void end_exclusive(void)
248 {
249 }
250
251 void fork_start(void)
252 {
253 }
254
255 void fork_end(int child)
256 {
257 }
258 #endif
259
260
261 #ifdef TARGET_I386
262 /***********************************************************/
263 /* CPUX86 core interface */
264
265 void cpu_smm_update(CPUState *env)
266 {
267 }
268
269 uint64_t cpu_get_tsc(CPUX86State *env)
270 {
271 return cpu_get_real_ticks();
272 }
273
274 static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
275 int flags)
276 {
277 unsigned int e1, e2;
278 uint32_t *p;
279 e1 = (addr << 16) | (limit & 0xffff);
280 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
281 e2 |= flags;
282 p = ptr;
283 p[0] = tswap32(e1);
284 p[1] = tswap32(e2);
285 }
286
287 static uint64_t *idt_table;
288 #ifdef TARGET_X86_64
289 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
290 uint64_t addr, unsigned int sel)
291 {
292 uint32_t *p, e1, e2;
293 e1 = (addr & 0xffff) | (sel << 16);
294 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
295 p = ptr;
296 p[0] = tswap32(e1);
297 p[1] = tswap32(e2);
298 p[2] = tswap32(addr >> 32);
299 p[3] = 0;
300 }
301 /* only dpl matters as we do only user space emulation */
302 static void set_idt(int n, unsigned int dpl)
303 {
304 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
305 }
306 #else
307 static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
308 uint32_t addr, unsigned int sel)
309 {
310 uint32_t *p, e1, e2;
311 e1 = (addr & 0xffff) | (sel << 16);
312 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
313 p = ptr;
314 p[0] = tswap32(e1);
315 p[1] = tswap32(e2);
316 }
317
318 /* only dpl matters as we do only user space emulation */
319 static void set_idt(int n, unsigned int dpl)
320 {
321 set_gate(idt_table + n, 0, dpl, 0, 0);
322 }
323 #endif
324
325 void cpu_loop(CPUX86State *env)
326 {
327 int trapnr;
328 abi_ulong pc;
329 target_siginfo_t info;
330
331 for(;;) {
332 trapnr = cpu_x86_exec(env);
333 switch(trapnr) {
334 case 0x80:
335 /* linux syscall from int $0x80 */
336 env->regs[R_EAX] = do_syscall(env,
337 env->regs[R_EAX],
338 env->regs[R_EBX],
339 env->regs[R_ECX],
340 env->regs[R_EDX],
341 env->regs[R_ESI],
342 env->regs[R_EDI],
343 env->regs[R_EBP]);
344 break;
345 #ifndef TARGET_ABI32
346 case EXCP_SYSCALL:
347 /* linux syscall from syscall intruction */
348 env->regs[R_EAX] = do_syscall(env,
349 env->regs[R_EAX],
350 env->regs[R_EDI],
351 env->regs[R_ESI],
352 env->regs[R_EDX],
353 env->regs[10],
354 env->regs[8],
355 env->regs[9]);
356 env->eip = env->exception_next_eip;
357 break;
358 #endif
359 case EXCP0B_NOSEG:
360 case EXCP0C_STACK:
361 info.si_signo = SIGBUS;
362 info.si_errno = 0;
363 info.si_code = TARGET_SI_KERNEL;
364 info._sifields._sigfault._addr = 0;
365 queue_signal(env, info.si_signo, &info);
366 break;
367 case EXCP0D_GPF:
368 /* XXX: potential problem if ABI32 */
369 #ifndef TARGET_X86_64
370 if (env->eflags & VM_MASK) {
371 handle_vm86_fault(env);
372 } else
373 #endif
374 {
375 info.si_signo = SIGSEGV;
376 info.si_errno = 0;
377 info.si_code = TARGET_SI_KERNEL;
378 info._sifields._sigfault._addr = 0;
379 queue_signal(env, info.si_signo, &info);
380 }
381 break;
382 case EXCP0E_PAGE:
383 info.si_signo = SIGSEGV;
384 info.si_errno = 0;
385 if (!(env->error_code & 1))
386 info.si_code = TARGET_SEGV_MAPERR;
387 else
388 info.si_code = TARGET_SEGV_ACCERR;
389 info._sifields._sigfault._addr = env->cr[2];
390 queue_signal(env, info.si_signo, &info);
391 break;
392 case EXCP00_DIVZ:
393 #ifndef TARGET_X86_64
394 if (env->eflags & VM_MASK) {
395 handle_vm86_trap(env, trapnr);
396 } else
397 #endif
398 {
399 /* division by zero */
400 info.si_signo = SIGFPE;
401 info.si_errno = 0;
402 info.si_code = TARGET_FPE_INTDIV;
403 info._sifields._sigfault._addr = env->eip;
404 queue_signal(env, info.si_signo, &info);
405 }
406 break;
407 case EXCP01_DB:
408 case EXCP03_INT3:
409 #ifndef TARGET_X86_64
410 if (env->eflags & VM_MASK) {
411 handle_vm86_trap(env, trapnr);
412 } else
413 #endif
414 {
415 info.si_signo = SIGTRAP;
416 info.si_errno = 0;
417 if (trapnr == EXCP01_DB) {
418 info.si_code = TARGET_TRAP_BRKPT;
419 info._sifields._sigfault._addr = env->eip;
420 } else {
421 info.si_code = TARGET_SI_KERNEL;
422 info._sifields._sigfault._addr = 0;
423 }
424 queue_signal(env, info.si_signo, &info);
425 }
426 break;
427 case EXCP04_INTO:
428 case EXCP05_BOUND:
429 #ifndef TARGET_X86_64
430 if (env->eflags & VM_MASK) {
431 handle_vm86_trap(env, trapnr);
432 } else
433 #endif
434 {
435 info.si_signo = SIGSEGV;
436 info.si_errno = 0;
437 info.si_code = TARGET_SI_KERNEL;
438 info._sifields._sigfault._addr = 0;
439 queue_signal(env, info.si_signo, &info);
440 }
441 break;
442 case EXCP06_ILLOP:
443 info.si_signo = SIGILL;
444 info.si_errno = 0;
445 info.si_code = TARGET_ILL_ILLOPN;
446 info._sifields._sigfault._addr = env->eip;
447 queue_signal(env, info.si_signo, &info);
448 break;
449 case EXCP_INTERRUPT:
450 /* just indicate that signals should be handled asap */
451 break;
452 case EXCP_DEBUG:
453 {
454 int sig;
455
456 sig = gdb_handlesig (env, TARGET_SIGTRAP);
457 if (sig)
458 {
459 info.si_signo = sig;
460 info.si_errno = 0;
461 info.si_code = TARGET_TRAP_BRKPT;
462 queue_signal(env, info.si_signo, &info);
463 }
464 }
465 break;
466 default:
467 pc = env->segs[R_CS].base + env->eip;
468 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
469 (long)pc, trapnr);
470 abort();
471 }
472 process_pending_signals(env);
473 }
474 }
475 #endif
476
477 #ifdef TARGET_ARM
478
479 static void arm_cache_flush(abi_ulong start, abi_ulong last)
480 {
481 abi_ulong addr, last1;
482
483 if (last < start)
484 return;
485 addr = start;
486 for(;;) {
487 last1 = ((addr + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK) - 1;
488 if (last1 > last)
489 last1 = last;
490 tb_invalidate_page_range(addr, last1 + 1);
491 if (last1 == last)
492 break;
493 addr = last1 + 1;
494 }
495 }
496
497 /* Handle a jump to the kernel code page. */
498 static int
499 do_kernel_trap(CPUARMState *env)
500 {
501 uint32_t addr;
502 uint32_t cpsr;
503 uint32_t val;
504
505 switch (env->regs[15]) {
506 case 0xffff0fa0: /* __kernel_memory_barrier */
507 /* ??? No-op. Will need to do better for SMP. */
508 break;
509 case 0xffff0fc0: /* __kernel_cmpxchg */
510 /* XXX: This only works between threads, not between processes.
511 It's probably possible to implement this with native host
512 operations. However things like ldrex/strex are much harder so
513 there's not much point trying. */
514 start_exclusive();
515 cpsr = cpsr_read(env);
516 addr = env->regs[2];
517 /* FIXME: This should SEGV if the access fails. */
518 if (get_user_u32(val, addr))
519 val = ~env->regs[0];
520 if (val == env->regs[0]) {
521 val = env->regs[1];
522 /* FIXME: Check for segfaults. */
523 put_user_u32(val, addr);
524 env->regs[0] = 0;
525 cpsr |= CPSR_C;
526 } else {
527 env->regs[0] = -1;
528 cpsr &= ~CPSR_C;
529 }
530 cpsr_write(env, cpsr, CPSR_C);
531 end_exclusive();
532 break;
533 case 0xffff0fe0: /* __kernel_get_tls */
534 env->regs[0] = env->cp15.c13_tls2;
535 break;
536 default:
537 return 1;
538 }
539 /* Jump back to the caller. */
540 addr = env->regs[14];
541 if (addr & 1) {
542 env->thumb = 1;
543 addr &= ~1;
544 }
545 env->regs[15] = addr;
546
547 return 0;
548 }
549
550 void cpu_loop(CPUARMState *env)
551 {
552 int trapnr;
553 unsigned int n, insn;
554 target_siginfo_t info;
555 uint32_t addr;
556
557 for(;;) {
558 cpu_exec_start(env);
559 trapnr = cpu_arm_exec(env);
560 cpu_exec_end(env);
561 switch(trapnr) {
562 case EXCP_UDEF:
563 {
564 TaskState *ts = env->opaque;
565 uint32_t opcode;
566 int rc;
567
568 /* we handle the FPU emulation here, as Linux */
569 /* we get the opcode */
570 /* FIXME - what to do if get_user() fails? */
571 get_user_u32(opcode, env->regs[15]);
572
573 rc = EmulateAll(opcode, &ts->fpa, env);
574 if (rc == 0) { /* illegal instruction */
575 info.si_signo = SIGILL;
576 info.si_errno = 0;
577 info.si_code = TARGET_ILL_ILLOPN;
578 info._sifields._sigfault._addr = env->regs[15];
579 queue_signal(env, info.si_signo, &info);
580 } else if (rc < 0) { /* FP exception */
581 int arm_fpe=0;
582
583 /* translate softfloat flags to FPSR flags */
584 if (-rc & float_flag_invalid)
585 arm_fpe |= BIT_IOC;
586 if (-rc & float_flag_divbyzero)
587 arm_fpe |= BIT_DZC;
588 if (-rc & float_flag_overflow)
589 arm_fpe |= BIT_OFC;
590 if (-rc & float_flag_underflow)
591 arm_fpe |= BIT_UFC;
592 if (-rc & float_flag_inexact)
593 arm_fpe |= BIT_IXC;
594
595 FPSR fpsr = ts->fpa.fpsr;
596 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
597
598 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
599 info.si_signo = SIGFPE;
600 info.si_errno = 0;
601
602 /* ordered by priority, least first */
603 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
604 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
605 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
606 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
607 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
608
609 info._sifields._sigfault._addr = env->regs[15];
610 queue_signal(env, info.si_signo, &info);
611 } else {
612 env->regs[15] += 4;
613 }
614
615 /* accumulate unenabled exceptions */
616 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
617 fpsr |= BIT_IXC;
618 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
619 fpsr |= BIT_UFC;
620 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
621 fpsr |= BIT_OFC;
622 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
623 fpsr |= BIT_DZC;
624 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
625 fpsr |= BIT_IOC;
626 ts->fpa.fpsr=fpsr;
627 } else { /* everything OK */
628 /* increment PC */
629 env->regs[15] += 4;
630 }
631 }
632 break;
633 case EXCP_SWI:
634 case EXCP_BKPT:
635 {
636 env->eabi = 1;
637 /* system call */
638 if (trapnr == EXCP_BKPT) {
639 if (env->thumb) {
640 /* FIXME - what to do if get_user() fails? */
641 get_user_u16(insn, env->regs[15]);
642 n = insn & 0xff;
643 env->regs[15] += 2;
644 } else {
645 /* FIXME - what to do if get_user() fails? */
646 get_user_u32(insn, env->regs[15]);
647 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
648 env->regs[15] += 4;
649 }
650 } else {
651 if (env->thumb) {
652 /* FIXME - what to do if get_user() fails? */
653 get_user_u16(insn, env->regs[15] - 2);
654 n = insn & 0xff;
655 } else {
656 /* FIXME - what to do if get_user() fails? */
657 get_user_u32(insn, env->regs[15] - 4);
658 n = insn & 0xffffff;
659 }
660 }
661
662 if (n == ARM_NR_cacheflush) {
663 arm_cache_flush(env->regs[0], env->regs[1]);
664 } else if (n == ARM_NR_semihosting
665 || n == ARM_NR_thumb_semihosting) {
666 env->regs[0] = do_arm_semihosting (env);
667 } else if (n == 0 || n >= ARM_SYSCALL_BASE
668 || (env->thumb && n == ARM_THUMB_SYSCALL)) {
669 /* linux syscall */
670 if (env->thumb || n == 0) {
671 n = env->regs[7];
672 } else {
673 n -= ARM_SYSCALL_BASE;
674 env->eabi = 0;
675 }
676 if ( n > ARM_NR_BASE) {
677 switch (n) {
678 case ARM_NR_cacheflush:
679 arm_cache_flush(env->regs[0], env->regs[1]);
680 break;
681 case ARM_NR_set_tls:
682 cpu_set_tls(env, env->regs[0]);
683 env->regs[0] = 0;
684 break;
685 default:
686 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
687 n);
688 env->regs[0] = -TARGET_ENOSYS;
689 break;
690 }
691 } else {
692 env->regs[0] = do_syscall(env,
693 n,
694 env->regs[0],
695 env->regs[1],
696 env->regs[2],
697 env->regs[3],
698 env->regs[4],
699 env->regs[5]);
700 }
701 } else {
702 goto error;
703 }
704 }
705 break;
706 case EXCP_INTERRUPT:
707 /* just indicate that signals should be handled asap */
708 break;
709 case EXCP_PREFETCH_ABORT:
710 addr = env->cp15.c6_insn;
711 goto do_segv;
712 case EXCP_DATA_ABORT:
713 addr = env->cp15.c6_data;
714 goto do_segv;
715 do_segv:
716 {
717 info.si_signo = SIGSEGV;
718 info.si_errno = 0;
719 /* XXX: check env->error_code */
720 info.si_code = TARGET_SEGV_MAPERR;
721 info._sifields._sigfault._addr = addr;
722 queue_signal(env, info.si_signo, &info);
723 }
724 break;
725 case EXCP_DEBUG:
726 {
727 int sig;
728
729 sig = gdb_handlesig (env, TARGET_SIGTRAP);
730 if (sig)
731 {
732 info.si_signo = sig;
733 info.si_errno = 0;
734 info.si_code = TARGET_TRAP_BRKPT;
735 queue_signal(env, info.si_signo, &info);
736 }
737 }
738 break;
739 case EXCP_KERNEL_TRAP:
740 if (do_kernel_trap(env))
741 goto error;
742 break;
743 default:
744 error:
745 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
746 trapnr);
747 cpu_dump_state(env, stderr, fprintf, 0);
748 abort();
749 }
750 process_pending_signals(env);
751 }
752 }
753
754 #endif
755
756 #ifdef TARGET_SPARC
757 #define SPARC64_STACK_BIAS 2047
758
759 //#define DEBUG_WIN
760
761 /* WARNING: dealing with register windows _is_ complicated. More info
762 can be found at http://www.sics.se/~psm/sparcstack.html */
763 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
764 {
765 index = (index + cwp * 16) % (16 * env->nwindows);
766 /* wrap handling : if cwp is on the last window, then we use the
767 registers 'after' the end */
768 if (index < 8 && env->cwp == env->nwindows - 1)
769 index += 16 * env->nwindows;
770 return index;
771 }
772
773 /* save the register window 'cwp1' */
774 static inline void save_window_offset(CPUSPARCState *env, int cwp1)
775 {
776 unsigned int i;
777 abi_ulong sp_ptr;
778
779 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
780 #ifdef TARGET_SPARC64
781 if (sp_ptr & 3)
782 sp_ptr += SPARC64_STACK_BIAS;
783 #endif
784 #if defined(DEBUG_WIN)
785 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
786 sp_ptr, cwp1);
787 #endif
788 for(i = 0; i < 16; i++) {
789 /* FIXME - what to do if put_user() fails? */
790 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
791 sp_ptr += sizeof(abi_ulong);
792 }
793 }
794
795 static void save_window(CPUSPARCState *env)
796 {
797 #ifndef TARGET_SPARC64
798 unsigned int new_wim;
799 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
800 ((1LL << env->nwindows) - 1);
801 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
802 env->wim = new_wim;
803 #else
804 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
805 env->cansave++;
806 env->canrestore--;
807 #endif
808 }
809
810 static void restore_window(CPUSPARCState *env)
811 {
812 #ifndef TARGET_SPARC64
813 unsigned int new_wim;
814 #endif
815 unsigned int i, cwp1;
816 abi_ulong sp_ptr;
817
818 #ifndef TARGET_SPARC64
819 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
820 ((1LL << env->nwindows) - 1);
821 #endif
822
823 /* restore the invalid window */
824 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
825 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
826 #ifdef TARGET_SPARC64
827 if (sp_ptr & 3)
828 sp_ptr += SPARC64_STACK_BIAS;
829 #endif
830 #if defined(DEBUG_WIN)
831 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
832 sp_ptr, cwp1);
833 #endif
834 for(i = 0; i < 16; i++) {
835 /* FIXME - what to do if get_user() fails? */
836 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
837 sp_ptr += sizeof(abi_ulong);
838 }
839 #ifdef TARGET_SPARC64
840 env->canrestore++;
841 if (env->cleanwin < env->nwindows - 1)
842 env->cleanwin++;
843 env->cansave--;
844 #else
845 env->wim = new_wim;
846 #endif
847 }
848
849 static void flush_windows(CPUSPARCState *env)
850 {
851 int offset, cwp1;
852
853 offset = 1;
854 for(;;) {
855 /* if restore would invoke restore_window(), then we can stop */
856 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
857 #ifndef TARGET_SPARC64
858 if (env->wim & (1 << cwp1))
859 break;
860 #else
861 if (env->canrestore == 0)
862 break;
863 env->cansave++;
864 env->canrestore--;
865 #endif
866 save_window_offset(env, cwp1);
867 offset++;
868 }
869 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
870 #ifndef TARGET_SPARC64
871 /* set wim so that restore will reload the registers */
872 env->wim = 1 << cwp1;
873 #endif
874 #if defined(DEBUG_WIN)
875 printf("flush_windows: nb=%d\n", offset - 1);
876 #endif
877 }
878
879 void cpu_loop (CPUSPARCState *env)
880 {
881 int trapnr, ret;
882 target_siginfo_t info;
883
884 while (1) {
885 trapnr = cpu_sparc_exec (env);
886
887 switch (trapnr) {
888 #ifndef TARGET_SPARC64
889 case 0x88:
890 case 0x90:
891 #else
892 case 0x110:
893 case 0x16d:
894 #endif
895 ret = do_syscall (env, env->gregs[1],
896 env->regwptr[0], env->regwptr[1],
897 env->regwptr[2], env->regwptr[3],
898 env->regwptr[4], env->regwptr[5]);
899 if ((unsigned int)ret >= (unsigned int)(-515)) {
900 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
901 env->xcc |= PSR_CARRY;
902 #else
903 env->psr |= PSR_CARRY;
904 #endif
905 ret = -ret;
906 } else {
907 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
908 env->xcc &= ~PSR_CARRY;
909 #else
910 env->psr &= ~PSR_CARRY;
911 #endif
912 }
913 env->regwptr[0] = ret;
914 /* next instruction */
915 env->pc = env->npc;
916 env->npc = env->npc + 4;
917 break;
918 case 0x83: /* flush windows */
919 #ifdef TARGET_ABI32
920 case 0x103:
921 #endif
922 flush_windows(env);
923 /* next instruction */
924 env->pc = env->npc;
925 env->npc = env->npc + 4;
926 break;
927 #ifndef TARGET_SPARC64
928 case TT_WIN_OVF: /* window overflow */
929 save_window(env);
930 break;
931 case TT_WIN_UNF: /* window underflow */
932 restore_window(env);
933 break;
934 case TT_TFAULT:
935 case TT_DFAULT:
936 {
937 info.si_signo = SIGSEGV;
938 info.si_errno = 0;
939 /* XXX: check env->error_code */
940 info.si_code = TARGET_SEGV_MAPERR;
941 info._sifields._sigfault._addr = env->mmuregs[4];
942 queue_signal(env, info.si_signo, &info);
943 }
944 break;
945 #else
946 case TT_SPILL: /* window overflow */
947 save_window(env);
948 break;
949 case TT_FILL: /* window underflow */
950 restore_window(env);
951 break;
952 case TT_TFAULT:
953 case TT_DFAULT:
954 {
955 info.si_signo = SIGSEGV;
956 info.si_errno = 0;
957 /* XXX: check env->error_code */
958 info.si_code = TARGET_SEGV_MAPERR;
959 if (trapnr == TT_DFAULT)
960 info._sifields._sigfault._addr = env->dmmuregs[4];
961 else
962 info._sifields._sigfault._addr = env->tsptr->tpc;
963 queue_signal(env, info.si_signo, &info);
964 }
965 break;
966 #ifndef TARGET_ABI32
967 case 0x16e:
968 flush_windows(env);
969 sparc64_get_context(env);
970 break;
971 case 0x16f:
972 flush_windows(env);
973 sparc64_set_context(env);
974 break;
975 #endif
976 #endif
977 case EXCP_INTERRUPT:
978 /* just indicate that signals should be handled asap */
979 break;
980 case EXCP_DEBUG:
981 {
982 int sig;
983
984 sig = gdb_handlesig (env, TARGET_SIGTRAP);
985 if (sig)
986 {
987 info.si_signo = sig;
988 info.si_errno = 0;
989 info.si_code = TARGET_TRAP_BRKPT;
990 queue_signal(env, info.si_signo, &info);
991 }
992 }
993 break;
994 default:
995 printf ("Unhandled trap: 0x%x\n", trapnr);
996 cpu_dump_state(env, stderr, fprintf, 0);
997 exit (1);
998 }
999 process_pending_signals (env);
1000 }
1001 }
1002
1003 #endif
1004
1005 #ifdef TARGET_PPC
1006 static inline uint64_t cpu_ppc_get_tb (CPUState *env)
1007 {
1008 /* TO FIX */
1009 return 0;
1010 }
1011
1012 uint32_t cpu_ppc_load_tbl (CPUState *env)
1013 {
1014 return cpu_ppc_get_tb(env) & 0xFFFFFFFF;
1015 }
1016
1017 uint32_t cpu_ppc_load_tbu (CPUState *env)
1018 {
1019 return cpu_ppc_get_tb(env) >> 32;
1020 }
1021
1022 uint32_t cpu_ppc_load_atbl (CPUState *env)
1023 {
1024 return cpu_ppc_get_tb(env) & 0xFFFFFFFF;
1025 }
1026
1027 uint32_t cpu_ppc_load_atbu (CPUState *env)
1028 {
1029 return cpu_ppc_get_tb(env) >> 32;
1030 }
1031
1032 uint32_t cpu_ppc601_load_rtcu (CPUState *env)
1033 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
1034
1035 uint32_t cpu_ppc601_load_rtcl (CPUState *env)
1036 {
1037 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
1038 }
1039
1040 /* XXX: to be fixed */
1041 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp)
1042 {
1043 return -1;
1044 }
1045
1046 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val)
1047 {
1048 return -1;
1049 }
1050
1051 #define EXCP_DUMP(env, fmt, args...) \
1052 do { \
1053 fprintf(stderr, fmt , ##args); \
1054 cpu_dump_state(env, stderr, fprintf, 0); \
1055 if (loglevel != 0) { \
1056 fprintf(logfile, fmt , ##args); \
1057 cpu_dump_state(env, logfile, fprintf, 0); \
1058 } \
1059 } while (0)
1060
1061 void cpu_loop(CPUPPCState *env)
1062 {
1063 target_siginfo_t info;
1064 int trapnr;
1065 uint32_t ret;
1066
1067 for(;;) {
1068 trapnr = cpu_ppc_exec(env);
1069 switch(trapnr) {
1070 case POWERPC_EXCP_NONE:
1071 /* Just go on */
1072 break;
1073 case POWERPC_EXCP_CRITICAL: /* Critical input */
1074 cpu_abort(env, "Critical interrupt while in user mode. "
1075 "Aborting\n");
1076 break;
1077 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1078 cpu_abort(env, "Machine check exception while in user mode. "
1079 "Aborting\n");
1080 break;
1081 case POWERPC_EXCP_DSI: /* Data storage exception */
1082 EXCP_DUMP(env, "Invalid data memory access: 0x" ADDRX "\n",
1083 env->spr[SPR_DAR]);
1084 /* XXX: check this. Seems bugged */
1085 switch (env->error_code & 0xFF000000) {
1086 case 0x40000000:
1087 info.si_signo = TARGET_SIGSEGV;
1088 info.si_errno = 0;
1089 info.si_code = TARGET_SEGV_MAPERR;
1090 break;
1091 case 0x04000000:
1092 info.si_signo = TARGET_SIGILL;
1093 info.si_errno = 0;
1094 info.si_code = TARGET_ILL_ILLADR;
1095 break;
1096 case 0x08000000:
1097 info.si_signo = TARGET_SIGSEGV;
1098 info.si_errno = 0;
1099 info.si_code = TARGET_SEGV_ACCERR;
1100 break;
1101 default:
1102 /* Let's send a regular segfault... */
1103 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1104 env->error_code);
1105 info.si_signo = TARGET_SIGSEGV;
1106 info.si_errno = 0;
1107 info.si_code = TARGET_SEGV_MAPERR;
1108 break;
1109 }
1110 info._sifields._sigfault._addr = env->nip;
1111 queue_signal(env, info.si_signo, &info);
1112 break;
1113 case POWERPC_EXCP_ISI: /* Instruction storage exception */
1114 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" ADDRX "\n",
1115 env->spr[SPR_SRR0]);
1116 /* XXX: check this */
1117 switch (env->error_code & 0xFF000000) {
1118 case 0x40000000:
1119 info.si_signo = TARGET_SIGSEGV;
1120 info.si_errno = 0;
1121 info.si_code = TARGET_SEGV_MAPERR;
1122 break;
1123 case 0x10000000:
1124 case 0x08000000:
1125 info.si_signo = TARGET_SIGSEGV;
1126 info.si_errno = 0;
1127 info.si_code = TARGET_SEGV_ACCERR;
1128 break;
1129 default:
1130 /* Let's send a regular segfault... */
1131 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1132 env->error_code);
1133 info.si_signo = TARGET_SIGSEGV;
1134 info.si_errno = 0;
1135 info.si_code = TARGET_SEGV_MAPERR;
1136 break;
1137 }
1138 info._sifields._sigfault._addr = env->nip - 4;
1139 queue_signal(env, info.si_signo, &info);
1140 break;
1141 case POWERPC_EXCP_EXTERNAL: /* External input */
1142 cpu_abort(env, "External interrupt while in user mode. "
1143 "Aborting\n");
1144 break;
1145 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1146 EXCP_DUMP(env, "Unaligned memory access\n");
1147 /* XXX: check this */
1148 info.si_signo = TARGET_SIGBUS;
1149 info.si_errno = 0;
1150 info.si_code = TARGET_BUS_ADRALN;
1151 info._sifields._sigfault._addr = env->nip - 4;
1152 queue_signal(env, info.si_signo, &info);
1153 break;
1154 case POWERPC_EXCP_PROGRAM: /* Program exception */
1155 /* XXX: check this */
1156 switch (env->error_code & ~0xF) {
1157 case POWERPC_EXCP_FP:
1158 EXCP_DUMP(env, "Floating point program exception\n");
1159 info.si_signo = TARGET_SIGFPE;
1160 info.si_errno = 0;
1161 switch (env->error_code & 0xF) {
1162 case POWERPC_EXCP_FP_OX:
1163 info.si_code = TARGET_FPE_FLTOVF;
1164 break;
1165 case POWERPC_EXCP_FP_UX:
1166 info.si_code = TARGET_FPE_FLTUND;
1167 break;
1168 case POWERPC_EXCP_FP_ZX:
1169 case POWERPC_EXCP_FP_VXZDZ:
1170 info.si_code = TARGET_FPE_FLTDIV;
1171 break;
1172 case POWERPC_EXCP_FP_XX:
1173 info.si_code = TARGET_FPE_FLTRES;
1174 break;
1175 case POWERPC_EXCP_FP_VXSOFT:
1176 info.si_code = TARGET_FPE_FLTINV;
1177 break;
1178 case POWERPC_EXCP_FP_VXSNAN:
1179 case POWERPC_EXCP_FP_VXISI:
1180 case POWERPC_EXCP_FP_VXIDI:
1181 case POWERPC_EXCP_FP_VXIMZ:
1182 case POWERPC_EXCP_FP_VXVC:
1183 case POWERPC_EXCP_FP_VXSQRT:
1184 case POWERPC_EXCP_FP_VXCVI:
1185 info.si_code = TARGET_FPE_FLTSUB;
1186 break;
1187 default:
1188 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1189 env->error_code);
1190 break;
1191 }
1192 break;
1193 case POWERPC_EXCP_INVAL:
1194 EXCP_DUMP(env, "Invalid instruction\n");
1195 info.si_signo = TARGET_SIGILL;
1196 info.si_errno = 0;
1197 switch (env->error_code & 0xF) {
1198 case POWERPC_EXCP_INVAL_INVAL:
1199 info.si_code = TARGET_ILL_ILLOPC;
1200 break;
1201 case POWERPC_EXCP_INVAL_LSWX:
1202 info.si_code = TARGET_ILL_ILLOPN;
1203 break;
1204 case POWERPC_EXCP_INVAL_SPR:
1205 info.si_code = TARGET_ILL_PRVREG;
1206 break;
1207 case POWERPC_EXCP_INVAL_FP:
1208 info.si_code = TARGET_ILL_COPROC;
1209 break;
1210 default:
1211 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1212 env->error_code & 0xF);
1213 info.si_code = TARGET_ILL_ILLADR;
1214 break;
1215 }
1216 break;
1217 case POWERPC_EXCP_PRIV:
1218 EXCP_DUMP(env, "Privilege violation\n");
1219 info.si_signo = TARGET_SIGILL;
1220 info.si_errno = 0;
1221 switch (env->error_code & 0xF) {
1222 case POWERPC_EXCP_PRIV_OPC:
1223 info.si_code = TARGET_ILL_PRVOPC;
1224 break;
1225 case POWERPC_EXCP_PRIV_REG:
1226 info.si_code = TARGET_ILL_PRVREG;
1227 break;
1228 default:
1229 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1230 env->error_code & 0xF);
1231 info.si_code = TARGET_ILL_PRVOPC;
1232 break;
1233 }
1234 break;
1235 case POWERPC_EXCP_TRAP:
1236 cpu_abort(env, "Tried to call a TRAP\n");
1237 break;
1238 default:
1239 /* Should not happen ! */
1240 cpu_abort(env, "Unknown program exception (%02x)\n",
1241 env->error_code);
1242 break;
1243 }
1244 info._sifields._sigfault._addr = env->nip - 4;
1245 queue_signal(env, info.si_signo, &info);
1246 break;
1247 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1248 EXCP_DUMP(env, "No floating point allowed\n");
1249 info.si_signo = TARGET_SIGILL;
1250 info.si_errno = 0;
1251 info.si_code = TARGET_ILL_COPROC;
1252 info._sifields._sigfault._addr = env->nip - 4;
1253 queue_signal(env, info.si_signo, &info);
1254 break;
1255 case POWERPC_EXCP_SYSCALL: /* System call exception */
1256 cpu_abort(env, "Syscall exception while in user mode. "
1257 "Aborting\n");
1258 break;
1259 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1260 EXCP_DUMP(env, "No APU instruction allowed\n");
1261 info.si_signo = TARGET_SIGILL;
1262 info.si_errno = 0;
1263 info.si_code = TARGET_ILL_COPROC;
1264 info._sifields._sigfault._addr = env->nip - 4;
1265 queue_signal(env, info.si_signo, &info);
1266 break;
1267 case POWERPC_EXCP_DECR: /* Decrementer exception */
1268 cpu_abort(env, "Decrementer interrupt while in user mode. "
1269 "Aborting\n");
1270 break;
1271 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1272 cpu_abort(env, "Fix interval timer interrupt while in user mode. "
1273 "Aborting\n");
1274 break;
1275 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1276 cpu_abort(env, "Watchdog timer interrupt while in user mode. "
1277 "Aborting\n");
1278 break;
1279 case POWERPC_EXCP_DTLB: /* Data TLB error */
1280 cpu_abort(env, "Data TLB exception while in user mode. "
1281 "Aborting\n");
1282 break;
1283 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1284 cpu_abort(env, "Instruction TLB exception while in user mode. "
1285 "Aborting\n");
1286 break;
1287 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1288 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1289 info.si_signo = TARGET_SIGILL;
1290 info.si_errno = 0;
1291 info.si_code = TARGET_ILL_COPROC;
1292 info._sifields._sigfault._addr = env->nip - 4;
1293 queue_signal(env, info.si_signo, &info);
1294 break;
1295 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1296 cpu_abort(env, "Embedded floating-point data IRQ not handled\n");
1297 break;
1298 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1299 cpu_abort(env, "Embedded floating-point round IRQ not handled\n");
1300 break;
1301 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1302 cpu_abort(env, "Performance monitor exception not handled\n");
1303 break;
1304 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1305 cpu_abort(env, "Doorbell interrupt while in user mode. "
1306 "Aborting\n");
1307 break;
1308 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1309 cpu_abort(env, "Doorbell critical interrupt while in user mode. "
1310 "Aborting\n");
1311 break;
1312 case POWERPC_EXCP_RESET: /* System reset exception */
1313 cpu_abort(env, "Reset interrupt while in user mode. "
1314 "Aborting\n");
1315 break;
1316 case POWERPC_EXCP_DSEG: /* Data segment exception */
1317 cpu_abort(env, "Data segment exception while in user mode. "
1318 "Aborting\n");
1319 break;
1320 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1321 cpu_abort(env, "Instruction segment exception "
1322 "while in user mode. Aborting\n");
1323 break;
1324 /* PowerPC 64 with hypervisor mode support */
1325 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1326 cpu_abort(env, "Hypervisor decrementer interrupt "
1327 "while in user mode. Aborting\n");
1328 break;
1329 case POWERPC_EXCP_TRACE: /* Trace exception */
1330 /* Nothing to do:
1331 * we use this exception to emulate step-by-step execution mode.
1332 */
1333 break;
1334 /* PowerPC 64 with hypervisor mode support */
1335 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1336 cpu_abort(env, "Hypervisor data storage exception "
1337 "while in user mode. Aborting\n");
1338 break;
1339 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1340 cpu_abort(env, "Hypervisor instruction storage exception "
1341 "while in user mode. Aborting\n");
1342 break;
1343 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1344 cpu_abort(env, "Hypervisor data segment exception "
1345 "while in user mode. Aborting\n");
1346 break;
1347 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1348 cpu_abort(env, "Hypervisor instruction segment exception "
1349 "while in user mode. Aborting\n");
1350 break;
1351 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1352 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1353 info.si_signo = TARGET_SIGILL;
1354 info.si_errno = 0;
1355 info.si_code = TARGET_ILL_COPROC;
1356 info._sifields._sigfault._addr = env->nip - 4;
1357 queue_signal(env, info.si_signo, &info);
1358 break;
1359 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
1360 cpu_abort(env, "Programable interval timer interrupt "
1361 "while in user mode. Aborting\n");
1362 break;
1363 case POWERPC_EXCP_IO: /* IO error exception */
1364 cpu_abort(env, "IO error exception while in user mode. "
1365 "Aborting\n");
1366 break;
1367 case POWERPC_EXCP_RUNM: /* Run mode exception */
1368 cpu_abort(env, "Run mode exception while in user mode. "
1369 "Aborting\n");
1370 break;
1371 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1372 cpu_abort(env, "Emulation trap exception not handled\n");
1373 break;
1374 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1375 cpu_abort(env, "Instruction fetch TLB exception "
1376 "while in user-mode. Aborting");
1377 break;
1378 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1379 cpu_abort(env, "Data load TLB exception while in user-mode. "
1380 "Aborting");
1381 break;
1382 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1383 cpu_abort(env, "Data store TLB exception while in user-mode. "
1384 "Aborting");
1385 break;
1386 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1387 cpu_abort(env, "Floating-point assist exception not handled\n");
1388 break;
1389 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1390 cpu_abort(env, "Instruction address breakpoint exception "
1391 "not handled\n");
1392 break;
1393 case POWERPC_EXCP_SMI: /* System management interrupt */
1394 cpu_abort(env, "System management interrupt while in user mode. "
1395 "Aborting\n");
1396 break;
1397 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1398 cpu_abort(env, "Thermal interrupt interrupt while in user mode. "
1399 "Aborting\n");
1400 break;
1401 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1402 cpu_abort(env, "Performance monitor exception not handled\n");
1403 break;
1404 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1405 cpu_abort(env, "Vector assist exception not handled\n");
1406 break;
1407 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1408 cpu_abort(env, "Soft patch exception not handled\n");
1409 break;
1410 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1411 cpu_abort(env, "Maintenance exception while in user mode. "
1412 "Aborting\n");
1413 break;
1414 case POWERPC_EXCP_STOP: /* stop translation */
1415 /* We did invalidate the instruction cache. Go on */
1416 break;
1417 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1418 /* We just stopped because of a branch. Go on */
1419 break;
1420 case POWERPC_EXCP_SYSCALL_USER:
1421 /* system call in user-mode emulation */
1422 /* WARNING:
1423 * PPC ABI uses overflow flag in cr0 to signal an error
1424 * in syscalls.
1425 */
1426 #if 0
1427 printf("syscall %d 0x%08x 0x%08x 0x%08x 0x%08x\n", env->gpr[0],
1428 env->gpr[3], env->gpr[4], env->gpr[5], env->gpr[6]);
1429 #endif
1430 env->crf[0] &= ~0x1;
1431 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1432 env->gpr[5], env->gpr[6], env->gpr[7],
1433 env->gpr[8]);
1434 if (ret > (uint32_t)(-515)) {
1435 env->crf[0] |= 0x1;
1436 ret = -ret;
1437 }
1438 env->gpr[3] = ret;
1439 #if 0
1440 printf("syscall returned 0x%08x (%d)\n", ret, ret);
1441 #endif
1442 break;
1443 case EXCP_DEBUG:
1444 {
1445 int sig;
1446
1447 sig = gdb_handlesig(env, TARGET_SIGTRAP);
1448 if (sig) {
1449 info.si_signo = sig;
1450 info.si_errno = 0;
1451 info.si_code = TARGET_TRAP_BRKPT;
1452 queue_signal(env, info.si_signo, &info);
1453 }
1454 }
1455 break;
1456 case EXCP_INTERRUPT:
1457 /* just indicate that signals should be handled asap */
1458 break;
1459 default:
1460 cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr);
1461 break;
1462 }
1463 process_pending_signals(env);
1464 }
1465 }
1466 #endif
1467
1468 #ifdef TARGET_MIPS
1469
1470 #define MIPS_SYS(name, args) args,
1471
1472 static const uint8_t mips_syscall_args[] = {
1473 MIPS_SYS(sys_syscall , 0) /* 4000 */
1474 MIPS_SYS(sys_exit , 1)
1475 MIPS_SYS(sys_fork , 0)
1476 MIPS_SYS(sys_read , 3)
1477 MIPS_SYS(sys_write , 3)
1478 MIPS_SYS(sys_open , 3) /* 4005 */
1479 MIPS_SYS(sys_close , 1)
1480 MIPS_SYS(sys_waitpid , 3)
1481 MIPS_SYS(sys_creat , 2)
1482 MIPS_SYS(sys_link , 2)
1483 MIPS_SYS(sys_unlink , 1) /* 4010 */
1484 MIPS_SYS(sys_execve , 0)
1485 MIPS_SYS(sys_chdir , 1)
1486 MIPS_SYS(sys_time , 1)
1487 MIPS_SYS(sys_mknod , 3)
1488 MIPS_SYS(sys_chmod , 2) /* 4015 */
1489 MIPS_SYS(sys_lchown , 3)
1490 MIPS_SYS(sys_ni_syscall , 0)
1491 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
1492 MIPS_SYS(sys_lseek , 3)
1493 MIPS_SYS(sys_getpid , 0) /* 4020 */
1494 MIPS_SYS(sys_mount , 5)
1495 MIPS_SYS(sys_oldumount , 1)
1496 MIPS_SYS(sys_setuid , 1)
1497 MIPS_SYS(sys_getuid , 0)
1498 MIPS_SYS(sys_stime , 1) /* 4025 */
1499 MIPS_SYS(sys_ptrace , 4)
1500 MIPS_SYS(sys_alarm , 1)
1501 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
1502 MIPS_SYS(sys_pause , 0)
1503 MIPS_SYS(sys_utime , 2) /* 4030 */
1504 MIPS_SYS(sys_ni_syscall , 0)
1505 MIPS_SYS(sys_ni_syscall , 0)
1506 MIPS_SYS(sys_access , 2)
1507 MIPS_SYS(sys_nice , 1)
1508 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
1509 MIPS_SYS(sys_sync , 0)
1510 MIPS_SYS(sys_kill , 2)
1511 MIPS_SYS(sys_rename , 2)
1512 MIPS_SYS(sys_mkdir , 2)
1513 MIPS_SYS(sys_rmdir , 1) /* 4040 */
1514 MIPS_SYS(sys_dup , 1)
1515 MIPS_SYS(sys_pipe , 0)
1516 MIPS_SYS(sys_times , 1)
1517 MIPS_SYS(sys_ni_syscall , 0)
1518 MIPS_SYS(sys_brk , 1) /* 4045 */
1519 MIPS_SYS(sys_setgid , 1)
1520 MIPS_SYS(sys_getgid , 0)
1521 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
1522 MIPS_SYS(sys_geteuid , 0)
1523 MIPS_SYS(sys_getegid , 0) /* 4050 */
1524 MIPS_SYS(sys_acct , 0)
1525 MIPS_SYS(sys_umount , 2)
1526 MIPS_SYS(sys_ni_syscall , 0)
1527 MIPS_SYS(sys_ioctl , 3)
1528 MIPS_SYS(sys_fcntl , 3) /* 4055 */
1529 MIPS_SYS(sys_ni_syscall , 2)
1530 MIPS_SYS(sys_setpgid , 2)
1531 MIPS_SYS(sys_ni_syscall , 0)
1532 MIPS_SYS(sys_olduname , 1)
1533 MIPS_SYS(sys_umask , 1) /* 4060 */
1534 MIPS_SYS(sys_chroot , 1)
1535 MIPS_SYS(sys_ustat , 2)
1536 MIPS_SYS(sys_dup2 , 2)
1537 MIPS_SYS(sys_getppid , 0)
1538 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
1539 MIPS_SYS(sys_setsid , 0)
1540 MIPS_SYS(sys_sigaction , 3)
1541 MIPS_SYS(sys_sgetmask , 0)
1542 MIPS_SYS(sys_ssetmask , 1)
1543 MIPS_SYS(sys_setreuid , 2) /* 4070 */
1544 MIPS_SYS(sys_setregid , 2)
1545 MIPS_SYS(sys_sigsuspend , 0)
1546 MIPS_SYS(sys_sigpending , 1)
1547 MIPS_SYS(sys_sethostname , 2)
1548 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
1549 MIPS_SYS(sys_getrlimit , 2)
1550 MIPS_SYS(sys_getrusage , 2)
1551 MIPS_SYS(sys_gettimeofday, 2)
1552 MIPS_SYS(sys_settimeofday, 2)
1553 MIPS_SYS(sys_getgroups , 2) /* 4080 */
1554 MIPS_SYS(sys_setgroups , 2)
1555 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
1556 MIPS_SYS(sys_symlink , 2)
1557 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
1558 MIPS_SYS(sys_readlink , 3) /* 4085 */
1559 MIPS_SYS(sys_uselib , 1)
1560 MIPS_SYS(sys_swapon , 2)
1561 MIPS_SYS(sys_reboot , 3)
1562 MIPS_SYS(old_readdir , 3)
1563 MIPS_SYS(old_mmap , 6) /* 4090 */
1564 MIPS_SYS(sys_munmap , 2)
1565 MIPS_SYS(sys_truncate , 2)
1566 MIPS_SYS(sys_ftruncate , 2)
1567 MIPS_SYS(sys_fchmod , 2)
1568 MIPS_SYS(sys_fchown , 3) /* 4095 */
1569 MIPS_SYS(sys_getpriority , 2)
1570 MIPS_SYS(sys_setpriority , 3)
1571 MIPS_SYS(sys_ni_syscall , 0)
1572 MIPS_SYS(sys_statfs , 2)
1573 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
1574 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
1575 MIPS_SYS(sys_socketcall , 2)
1576 MIPS_SYS(sys_syslog , 3)
1577 MIPS_SYS(sys_setitimer , 3)
1578 MIPS_SYS(sys_getitimer , 2) /* 4105 */
1579 MIPS_SYS(sys_newstat , 2)
1580 MIPS_SYS(sys_newlstat , 2)
1581 MIPS_SYS(sys_newfstat , 2)
1582 MIPS_SYS(sys_uname , 1)
1583 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
1584 MIPS_SYS(sys_vhangup , 0)
1585 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
1586 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
1587 MIPS_SYS(sys_wait4 , 4)
1588 MIPS_SYS(sys_swapoff , 1) /* 4115 */
1589 MIPS_SYS(sys_sysinfo , 1)
1590 MIPS_SYS(sys_ipc , 6)
1591 MIPS_SYS(sys_fsync , 1)
1592 MIPS_SYS(sys_sigreturn , 0)
1593 MIPS_SYS(sys_clone , 0) /* 4120 */
1594 MIPS_SYS(sys_setdomainname, 2)
1595 MIPS_SYS(sys_newuname , 1)
1596 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
1597 MIPS_SYS(sys_adjtimex , 1)
1598 MIPS_SYS(sys_mprotect , 3) /* 4125 */
1599 MIPS_SYS(sys_sigprocmask , 3)
1600 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
1601 MIPS_SYS(sys_init_module , 5)
1602 MIPS_SYS(sys_delete_module, 1)
1603 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
1604 MIPS_SYS(sys_quotactl , 0)
1605 MIPS_SYS(sys_getpgid , 1)
1606 MIPS_SYS(sys_fchdir , 1)
1607 MIPS_SYS(sys_bdflush , 2)
1608 MIPS_SYS(sys_sysfs , 3) /* 4135 */
1609 MIPS_SYS(sys_personality , 1)
1610 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
1611 MIPS_SYS(sys_setfsuid , 1)
1612 MIPS_SYS(sys_setfsgid , 1)
1613 MIPS_SYS(sys_llseek , 5) /* 4140 */
1614 MIPS_SYS(sys_getdents , 3)
1615 MIPS_SYS(sys_select , 5)
1616 MIPS_SYS(sys_flock , 2)
1617 MIPS_SYS(sys_msync , 3)
1618 MIPS_SYS(sys_readv , 3) /* 4145 */
1619 MIPS_SYS(sys_writev , 3)
1620 MIPS_SYS(sys_cacheflush , 3)
1621 MIPS_SYS(sys_cachectl , 3)
1622 MIPS_SYS(sys_sysmips , 4)
1623 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
1624 MIPS_SYS(sys_getsid , 1)
1625 MIPS_SYS(sys_fdatasync , 0)
1626 MIPS_SYS(sys_sysctl , 1)
1627 MIPS_SYS(sys_mlock , 2)
1628 MIPS_SYS(sys_munlock , 2) /* 4155 */
1629 MIPS_SYS(sys_mlockall , 1)
1630 MIPS_SYS(sys_munlockall , 0)
1631 MIPS_SYS(sys_sched_setparam, 2)
1632 MIPS_SYS(sys_sched_getparam, 2)
1633 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
1634 MIPS_SYS(sys_sched_getscheduler, 1)
1635 MIPS_SYS(sys_sched_yield , 0)
1636 MIPS_SYS(sys_sched_get_priority_max, 1)
1637 MIPS_SYS(sys_sched_get_priority_min, 1)
1638 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
1639 MIPS_SYS(sys_nanosleep, 2)
1640 MIPS_SYS(sys_mremap , 4)
1641 MIPS_SYS(sys_accept , 3)
1642 MIPS_SYS(sys_bind , 3)
1643 MIPS_SYS(sys_connect , 3) /* 4170 */
1644 MIPS_SYS(sys_getpeername , 3)
1645 MIPS_SYS(sys_getsockname , 3)
1646 MIPS_SYS(sys_getsockopt , 5)
1647 MIPS_SYS(sys_listen , 2)
1648 MIPS_SYS(sys_recv , 4) /* 4175 */
1649 MIPS_SYS(sys_recvfrom , 6)
1650 MIPS_SYS(sys_recvmsg , 3)
1651 MIPS_SYS(sys_send , 4)
1652 MIPS_SYS(sys_sendmsg , 3)
1653 MIPS_SYS(sys_sendto , 6) /* 4180 */
1654 MIPS_SYS(sys_setsockopt , 5)
1655 MIPS_SYS(sys_shutdown , 2)
1656 MIPS_SYS(sys_socket , 3)
1657 MIPS_SYS(sys_socketpair , 4)
1658 MIPS_SYS(sys_setresuid , 3) /* 4185 */
1659 MIPS_SYS(sys_getresuid , 3)
1660 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
1661 MIPS_SYS(sys_poll , 3)
1662 MIPS_SYS(sys_nfsservctl , 3)
1663 MIPS_SYS(sys_setresgid , 3) /* 4190 */
1664 MIPS_SYS(sys_getresgid , 3)
1665 MIPS_SYS(sys_prctl , 5)
1666 MIPS_SYS(sys_rt_sigreturn, 0)
1667 MIPS_SYS(sys_rt_sigaction, 4)
1668 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
1669 MIPS_SYS(sys_rt_sigpending, 2)
1670 MIPS_SYS(sys_rt_sigtimedwait, 4)
1671 MIPS_SYS(sys_rt_sigqueueinfo, 3)
1672 MIPS_SYS(sys_rt_sigsuspend, 0)
1673 MIPS_SYS(sys_pread64 , 6) /* 4200 */
1674 MIPS_SYS(sys_pwrite64 , 6)
1675 MIPS_SYS(sys_chown , 3)
1676 MIPS_SYS(sys_getcwd , 2)
1677 MIPS_SYS(sys_capget , 2)
1678 MIPS_SYS(sys_capset , 2) /* 4205 */
1679 MIPS_SYS(sys_sigaltstack , 0)
1680 MIPS_SYS(sys_sendfile , 4)
1681 MIPS_SYS(sys_ni_syscall , 0)
1682 MIPS_SYS(sys_ni_syscall , 0)
1683 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
1684 MIPS_SYS(sys_truncate64 , 4)
1685 MIPS_SYS(sys_ftruncate64 , 4)
1686 MIPS_SYS(sys_stat64 , 2)
1687 MIPS_SYS(sys_lstat64 , 2)
1688 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
1689 MIPS_SYS(sys_pivot_root , 2)
1690 MIPS_SYS(sys_mincore , 3)
1691 MIPS_SYS(sys_madvise , 3)
1692 MIPS_SYS(sys_getdents64 , 3)
1693 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
1694 MIPS_SYS(sys_ni_syscall , 0)
1695 MIPS_SYS(sys_gettid , 0)
1696 MIPS_SYS(sys_readahead , 5)
1697 MIPS_SYS(sys_setxattr , 5)
1698 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
1699 MIPS_SYS(sys_fsetxattr , 5)
1700 MIPS_SYS(sys_getxattr , 4)
1701 MIPS_SYS(sys_lgetxattr , 4)
1702 MIPS_SYS(sys_fgetxattr , 4)
1703 MIPS_SYS(sys_listxattr , 3) /* 4230 */
1704 MIPS_SYS(sys_llistxattr , 3)
1705 MIPS_SYS(sys_flistxattr , 3)
1706 MIPS_SYS(sys_removexattr , 2)
1707 MIPS_SYS(sys_lremovexattr, 2)
1708 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
1709 MIPS_SYS(sys_tkill , 2)
1710 MIPS_SYS(sys_sendfile64 , 5)
1711 MIPS_SYS(sys_futex , 2)
1712 MIPS_SYS(sys_sched_setaffinity, 3)
1713 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
1714 MIPS_SYS(sys_io_setup , 2)
1715 MIPS_SYS(sys_io_destroy , 1)
1716 MIPS_SYS(sys_io_getevents, 5)
1717 MIPS_SYS(sys_io_submit , 3)
1718 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
1719 MIPS_SYS(sys_exit_group , 1)
1720 MIPS_SYS(sys_lookup_dcookie, 3)
1721 MIPS_SYS(sys_epoll_create, 1)
1722 MIPS_SYS(sys_epoll_ctl , 4)
1723 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
1724 MIPS_SYS(sys_remap_file_pages, 5)
1725 MIPS_SYS(sys_set_tid_address, 1)
1726 MIPS_SYS(sys_restart_syscall, 0)
1727 MIPS_SYS(sys_fadvise64_64, 7)
1728 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
1729 MIPS_SYS(sys_fstatfs64 , 2)
1730 MIPS_SYS(sys_timer_create, 3)
1731 MIPS_SYS(sys_timer_settime, 4)
1732 MIPS_SYS(sys_timer_gettime, 2)
1733 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
1734 MIPS_SYS(sys_timer_delete, 1)
1735 MIPS_SYS(sys_clock_settime, 2)
1736 MIPS_SYS(sys_clock_gettime, 2)
1737 MIPS_SYS(sys_clock_getres, 2)
1738 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
1739 MIPS_SYS(sys_tgkill , 3)
1740 MIPS_SYS(sys_utimes , 2)
1741 MIPS_SYS(sys_mbind , 4)
1742 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
1743 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
1744 MIPS_SYS(sys_mq_open , 4)
1745 MIPS_SYS(sys_mq_unlink , 1)
1746 MIPS_SYS(sys_mq_timedsend, 5)
1747 MIPS_SYS(sys_mq_timedreceive, 5)
1748 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
1749 MIPS_SYS(sys_mq_getsetattr, 3)
1750 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
1751 MIPS_SYS(sys_waitid , 4)
1752 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
1753 MIPS_SYS(sys_add_key , 5)
1754 MIPS_SYS(sys_request_key, 4)
1755 MIPS_SYS(sys_keyctl , 5)
1756 MIPS_SYS(sys_set_thread_area, 1)
1757 MIPS_SYS(sys_inotify_init, 0)
1758 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
1759 MIPS_SYS(sys_inotify_rm_watch, 2)
1760 MIPS_SYS(sys_migrate_pages, 4)
1761 MIPS_SYS(sys_openat, 4)
1762 MIPS_SYS(sys_mkdirat, 3)
1763 MIPS_SYS(sys_mknodat, 4) /* 4290 */
1764 MIPS_SYS(sys_fchownat, 5)
1765 MIPS_SYS(sys_futimesat, 3)
1766 MIPS_SYS(sys_fstatat64, 4)
1767 MIPS_SYS(sys_unlinkat, 3)
1768 MIPS_SYS(sys_renameat, 4) /* 4295 */
1769 MIPS_SYS(sys_linkat, 5)
1770 MIPS_SYS(sys_symlinkat, 3)
1771 MIPS_SYS(sys_readlinkat, 4)
1772 MIPS_SYS(sys_fchmodat, 3)
1773 MIPS_SYS(sys_faccessat, 3) /* 4300 */
1774 MIPS_SYS(sys_pselect6, 6)
1775 MIPS_SYS(sys_ppoll, 5)
1776 MIPS_SYS(sys_unshare, 1)
1777 MIPS_SYS(sys_splice, 4)
1778 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
1779 MIPS_SYS(sys_tee, 4)
1780 MIPS_SYS(sys_vmsplice, 4)
1781 MIPS_SYS(sys_move_pages, 6)
1782 MIPS_SYS(sys_set_robust_list, 2)
1783 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
1784 MIPS_SYS(sys_kexec_load, 4)
1785 MIPS_SYS(sys_getcpu, 3)
1786 MIPS_SYS(sys_epoll_pwait, 6)
1787 MIPS_SYS(sys_ioprio_set, 3)
1788 MIPS_SYS(sys_ioprio_get, 2)
1789 };
1790
1791 #undef MIPS_SYS
1792
1793 void cpu_loop(CPUMIPSState *env)
1794 {
1795 target_siginfo_t info;
1796 int trapnr, ret;
1797 unsigned int syscall_num;
1798
1799 for(;;) {
1800 trapnr = cpu_mips_exec(env);
1801 switch(trapnr) {
1802 case EXCP_SYSCALL:
1803 syscall_num = env->active_tc.gpr[2] - 4000;
1804 env->active_tc.PC += 4;
1805 if (syscall_num >= sizeof(mips_syscall_args)) {
1806 ret = -ENOSYS;
1807 } else {
1808 int nb_args;
1809 abi_ulong sp_reg;
1810 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
1811
1812 nb_args = mips_syscall_args[syscall_num];
1813 sp_reg = env->active_tc.gpr[29];
1814 switch (nb_args) {
1815 /* these arguments are taken from the stack */
1816 /* FIXME - what to do if get_user() fails? */
1817 case 8: get_user_ual(arg8, sp_reg + 28);
1818 case 7: get_user_ual(arg7, sp_reg + 24);
1819 case 6: get_user_ual(arg6, sp_reg + 20);
1820 case 5: get_user_ual(arg5, sp_reg + 16);
1821 default:
1822 break;
1823 }
1824 ret = do_syscall(env, env->active_tc.gpr[2],
1825 env->active_tc.gpr[4],
1826 env->active_tc.gpr[5],
1827 env->active_tc.gpr[6],
1828 env->active_tc.gpr[7],
1829 arg5, arg6/*, arg7, arg8*/);
1830 }
1831 if ((unsigned int)ret >= (unsigned int)(-1133)) {
1832 env->active_tc.gpr[7] = 1; /* error flag */
1833 ret = -ret;
1834 } else {
1835 env->active_tc.gpr[7] = 0; /* error flag */
1836 }
1837 env->active_tc.gpr[2] = ret;
1838 break;
1839 case EXCP_TLBL:
1840 case EXCP_TLBS:
1841 case EXCP_CpU:
1842 case EXCP_RI:
1843 info.si_signo = TARGET_SIGILL;
1844 info.si_errno = 0;
1845 info.si_code = 0;
1846 queue_signal(env, info.si_signo, &info);
1847 break;
1848 case EXCP_INTERRUPT:
1849 /* just indicate that signals should be handled asap */
1850 break;
1851 case EXCP_DEBUG:
1852 {
1853 int sig;
1854
1855 sig = gdb_handlesig (env, TARGET_SIGTRAP);
1856 if (sig)
1857 {
1858 info.si_signo = sig;
1859 info.si_errno = 0;
1860 info.si_code = TARGET_TRAP_BRKPT;
1861 queue_signal(env, info.si_signo, &info);
1862 }
1863 }
1864 break;
1865 default:
1866 // error:
1867 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
1868 trapnr);
1869 cpu_dump_state(env, stderr, fprintf, 0);
1870 abort();
1871 }
1872 process_pending_signals(env);
1873 }
1874 }
1875 #endif
1876
1877 #ifdef TARGET_SH4
1878 void cpu_loop (CPUState *env)
1879 {
1880 int trapnr, ret;
1881 target_siginfo_t info;
1882
1883 while (1) {
1884 trapnr = cpu_sh4_exec (env);
1885
1886 switch (trapnr) {
1887 case 0x160:
1888 env->pc += 2;
1889 ret = do_syscall(env,
1890 env->gregs[3],
1891 env->gregs[4],
1892 env->gregs[5],
1893 env->gregs[6],
1894 env->gregs[7],
1895 env->gregs[0],
1896 env->gregs[1]);
1897 env->gregs[0] = ret;
1898 break;
1899 case EXCP_INTERRUPT:
1900 /* just indicate that signals should be handled asap */
1901 break;
1902 case EXCP_DEBUG:
1903 {
1904 int sig;
1905
1906 sig = gdb_handlesig (env, TARGET_SIGTRAP);
1907 if (sig)
1908 {
1909 info.si_signo = sig;
1910 info.si_errno = 0;
1911 info.si_code = TARGET_TRAP_BRKPT;
1912 queue_signal(env, info.si_signo, &info);
1913 }
1914 }
1915 break;
1916 case 0xa0:
1917 case 0xc0:
1918 info.si_signo = SIGSEGV;
1919 info.si_errno = 0;
1920 info.si_code = TARGET_SEGV_MAPERR;
1921 info._sifields._sigfault._addr = env->tea;
1922 queue_signal(env, info.si_signo, &info);
1923 break;
1924
1925 default:
1926 printf ("Unhandled trap: 0x%x\n", trapnr);
1927 cpu_dump_state(env, stderr, fprintf, 0);
1928 exit (1);
1929 }
1930 process_pending_signals (env);
1931 }
1932 }
1933 #endif
1934
1935 #ifdef TARGET_CRIS
1936 void cpu_loop (CPUState *env)
1937 {
1938 int trapnr, ret;
1939 target_siginfo_t info;
1940
1941 while (1) {
1942 trapnr = cpu_cris_exec (env);
1943 switch (trapnr) {
1944 case 0xaa:
1945 {
1946 info.si_signo = SIGSEGV;
1947 info.si_errno = 0;
1948 /* XXX: check env->error_code */
1949 info.si_code = TARGET_SEGV_MAPERR;
1950 info._sifields._sigfault._addr = env->pregs[PR_EDA];
1951 queue_signal(env, info.si_signo, &info);
1952 }
1953 break;
1954 case EXCP_INTERRUPT:
1955 /* just indicate that signals should be handled asap */
1956 break;
1957 case EXCP_BREAK:
1958 ret = do_syscall(env,
1959 env->regs[9],
1960 env->regs[10],
1961 env->regs[11],
1962 env->regs[12],
1963 env->regs[13],
1964 env->pregs[7],
1965 env->pregs[11]);
1966 env->regs[10] = ret;
1967 break;
1968 case EXCP_DEBUG:
1969 {
1970 int sig;
1971
1972 sig = gdb_handlesig (env, TARGET_SIGTRAP);
1973 if (sig)
1974 {
1975 info.si_signo = sig;
1976 info.si_errno = 0;
1977 info.si_code = TARGET_TRAP_BRKPT;
1978 queue_signal(env, info.si_signo, &info);
1979 }
1980 }
1981 break;
1982 default:
1983 printf ("Unhandled trap: 0x%x\n", trapnr);
1984 cpu_dump_state(env, stderr, fprintf, 0);
1985 exit (1);
1986 }
1987 process_pending_signals (env);
1988 }
1989 }
1990 #endif
1991
1992 #ifdef TARGET_M68K
1993
1994 void cpu_loop(CPUM68KState *env)
1995 {
1996 int trapnr;
1997 unsigned int n;
1998 target_siginfo_t info;
1999 TaskState *ts = env->opaque;
2000
2001 for(;;) {
2002 trapnr = cpu_m68k_exec(env);
2003 switch(trapnr) {
2004 case EXCP_ILLEGAL:
2005 {
2006 if (ts->sim_syscalls) {
2007 uint16_t nr;
2008 nr = lduw(env->pc + 2);
2009 env->pc += 4;
2010 do_m68k_simcall(env, nr);
2011 } else {
2012 goto do_sigill;
2013 }
2014 }
2015 break;
2016 case EXCP_HALT_INSN:
2017 /* Semihosing syscall. */
2018 env->pc += 4;
2019 do_m68k_semihosting(env, env->dregs[0]);
2020 break;
2021 case EXCP_LINEA:
2022 case EXCP_LINEF:
2023 case EXCP_UNSUPPORTED:
2024 do_sigill:
2025 info.si_signo = SIGILL;
2026 info.si_errno = 0;
2027 info.si_code = TARGET_ILL_ILLOPN;
2028 info._sifields._sigfault._addr = env->pc;
2029 queue_signal(env, info.si_signo, &info);
2030 break;
2031 case EXCP_TRAP0:
2032 {
2033 ts->sim_syscalls = 0;
2034 n = env->dregs[0];
2035 env->pc += 2;
2036 env->dregs[0] = do_syscall(env,
2037 n,
2038 env->dregs[1],
2039 env->dregs[2],
2040 env->dregs[3],
2041 env->dregs[4],
2042 env->dregs[5],
2043 env->aregs[0]);
2044 }
2045 break;
2046 case EXCP_INTERRUPT:
2047 /* just indicate that signals should be handled asap */
2048 break;
2049 case EXCP_ACCESS:
2050 {
2051 info.si_signo = SIGSEGV;
2052 info.si_errno = 0;
2053 /* XXX: check env->error_code */
2054 info.si_code = TARGET_SEGV_MAPERR;
2055 info._sifields._sigfault._addr = env->mmu.ar;
2056 queue_signal(env, info.si_signo, &info);
2057 }
2058 break;
2059 case EXCP_DEBUG:
2060 {
2061 int sig;
2062
2063 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2064 if (sig)
2065 {
2066 info.si_signo = sig;
2067 info.si_errno = 0;
2068 info.si_code = TARGET_TRAP_BRKPT;
2069 queue_signal(env, info.si_signo, &info);
2070 }
2071 }
2072 break;
2073 default:
2074 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
2075 trapnr);
2076 cpu_dump_state(env, stderr, fprintf, 0);
2077 abort();
2078 }
2079 process_pending_signals(env);
2080 }
2081 }
2082 #endif /* TARGET_M68K */
2083
2084 #ifdef TARGET_ALPHA
2085 void cpu_loop (CPUState *env)
2086 {
2087 int trapnr;
2088 target_siginfo_t info;
2089
2090 while (1) {
2091 trapnr = cpu_alpha_exec (env);
2092
2093 switch (trapnr) {
2094 case EXCP_RESET:
2095 fprintf(stderr, "Reset requested. Exit\n");
2096 exit(1);
2097 break;
2098 case EXCP_MCHK:
2099 fprintf(stderr, "Machine check exception. Exit\n");
2100 exit(1);
2101 break;
2102 case EXCP_ARITH:
2103 fprintf(stderr, "Arithmetic trap.\n");
2104 exit(1);
2105 break;
2106 case EXCP_HW_INTERRUPT:
2107 fprintf(stderr, "External interrupt. Exit\n");
2108 exit(1);
2109 break;
2110 case EXCP_DFAULT:
2111 fprintf(stderr, "MMU data fault\n");
2112 exit(1);
2113 break;
2114 case EXCP_DTB_MISS_PAL:
2115 fprintf(stderr, "MMU data TLB miss in PALcode\n");
2116 exit(1);
2117 break;
2118 case EXCP_ITB_MISS:
2119 fprintf(stderr, "MMU instruction TLB miss\n");
2120 exit(1);
2121 break;
2122 case EXCP_ITB_ACV:
2123 fprintf(stderr, "MMU instruction access violation\n");
2124 exit(1);
2125 break;
2126 case EXCP_DTB_MISS_NATIVE:
2127 fprintf(stderr, "MMU data TLB miss\n");
2128 exit(1);
2129 break;
2130 case EXCP_UNALIGN:
2131 fprintf(stderr, "Unaligned access\n");
2132 exit(1);
2133 break;
2134 case EXCP_OPCDEC:
2135 fprintf(stderr, "Invalid instruction\n");
2136 exit(1);
2137 break;
2138 case EXCP_FEN:
2139 fprintf(stderr, "Floating-point not allowed\n");
2140 exit(1);
2141 break;
2142 case EXCP_CALL_PAL ... (EXCP_CALL_PALP - 1):
2143 call_pal(env, (trapnr >> 6) | 0x80);
2144 break;
2145 case EXCP_CALL_PALP ... (EXCP_CALL_PALE - 1):
2146 fprintf(stderr, "Privileged call to PALcode\n");
2147 exit(1);
2148 break;
2149 case EXCP_DEBUG:
2150 {
2151 int sig;
2152
2153 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2154 if (sig)
2155 {
2156 info.si_signo = sig;
2157 info.si_errno = 0;
2158 info.si_code = TARGET_TRAP_BRKPT;
2159 queue_signal(env, info.si_signo, &info);
2160 }
2161 }
2162 break;
2163 default:
2164 printf ("Unhandled trap: 0x%x\n", trapnr);
2165 cpu_dump_state(env, stderr, fprintf, 0);
2166 exit (1);
2167 }
2168 process_pending_signals (env);
2169 }
2170 }
2171 #endif /* TARGET_ALPHA */
2172
2173 static void usage(void)
2174 {
2175 printf("qemu-" TARGET_ARCH " version " QEMU_VERSION ", Copyright (c) 2003-2008 Fabrice Bellard\n"
2176 "usage: qemu-" TARGET_ARCH " [options] program [arguments...]\n"
2177 "Linux CPU emulator (compiled for %s emulation)\n"
2178 "\n"
2179 "Standard options:\n"
2180 "-h print this help\n"
2181 "-g port wait gdb connection to port\n"
2182 "-L path set the elf interpreter prefix (default=%s)\n"
2183 "-s size set the stack size in bytes (default=%ld)\n"
2184 "-cpu model select CPU (-cpu ? for list)\n"
2185 "-drop-ld-preload drop LD_PRELOAD for target process\n"
2186 "\n"
2187 "Debug options:\n"
2188 "-d options activate log (logfile=%s)\n"
2189 "-p pagesize set the host page size to 'pagesize'\n"
2190 "-strace log system calls\n"
2191 "\n"
2192 "Environment variables:\n"
2193 "QEMU_STRACE Print system calls and arguments similar to the\n"
2194 " 'strace' program. Enable by setting to any value.\n"
2195 ,
2196 TARGET_ARCH,
2197 interp_prefix,
2198 x86_stack_size,
2199 DEBUG_LOGFILE);
2200 _exit(1);
2201 }
2202
2203 THREAD CPUState *thread_env;
2204
2205 /* Assumes contents are already zeroed. */
2206 void init_task_state(TaskState *ts)
2207 {
2208 int i;
2209
2210 ts->used = 1;
2211 ts->first_free = ts->sigqueue_table;
2212 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
2213 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
2214 }
2215 ts->sigqueue_table[i].next = NULL;
2216 }
2217
2218 int main(int argc, char **argv, char **envp)
2219 {
2220 const char *filename;
2221 const char *cpu_model;
2222 struct target_pt_regs regs1, *regs = &regs1;
2223 struct image_info info1, *info = &info1;
2224 TaskState ts1, *ts = &ts1;
2225 CPUState *env;
2226 int optind;
2227 const char *r;
2228 int gdbstub_port = 0;
2229 int drop_ld_preload = 0, environ_count = 0;
2230 char **target_environ, **wrk, **dst;
2231
2232 if (argc <= 1)
2233 usage();
2234
2235 qemu_cache_utils_init(envp);
2236
2237 /* init debug */
2238 cpu_set_log_filename(DEBUG_LOGFILE);
2239
2240 cpu_model = NULL;
2241 optind = 1;
2242 for(;;) {
2243 if (optind >= argc)
2244 break;
2245 r = argv[optind];
2246 if (r[0] != '-')
2247 break;
2248 optind++;
2249 r++;
2250 if (!strcmp(r, "-")) {
2251 break;
2252 } else if (!strcmp(r, "d")) {
2253 int mask;
2254 const CPULogItem *item;
2255
2256 if (optind >= argc)
2257 break;
2258
2259 r = argv[optind++];
2260 mask = cpu_str_to_log_mask(r);
2261 if (!mask) {
2262 printf("Log items (comma separated):\n");
2263 for(item = cpu_log_items; item->mask != 0; item++) {
2264 printf("%-10s %s\n", item->name, item->help);
2265 }
2266 exit(1);
2267 }
2268 cpu_set_log(mask);
2269 } else if (!strcmp(r, "s")) {
2270 r = argv[optind++];
2271 x86_stack_size = strtol(r, (char **)&r, 0);
2272 if (x86_stack_size <= 0)
2273 usage();
2274 if (*r == 'M')
2275 x86_stack_size *= 1024 * 1024;
2276 else if (*r == 'k' || *r == 'K')
2277 x86_stack_size *= 1024;
2278 } else if (!strcmp(r, "L")) {
2279 interp_prefix = argv[optind++];
2280 } else if (!strcmp(r, "p")) {
2281 qemu_host_page_size = atoi(argv[optind++]);
2282 if (qemu_host_page_size == 0 ||
2283 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
2284 fprintf(stderr, "page size must be a power of two\n");
2285 exit(1);
2286 }
2287 } else if (!strcmp(r, "g")) {
2288 gdbstub_port = atoi(argv[optind++]);
2289 } else if (!strcmp(r, "r")) {
2290 qemu_uname_release = argv[optind++];
2291 } else if (!strcmp(r, "cpu")) {
2292 cpu_model = argv[optind++];
2293 if (strcmp(cpu_model, "?") == 0) {
2294 /* XXX: implement xxx_cpu_list for targets that still miss it */
2295 #if defined(cpu_list)
2296 cpu_list(stdout, &fprintf);
2297 #endif
2298 _exit(1);
2299 }
2300 } else if (!strcmp(r, "drop-ld-preload")) {
2301 drop_ld_preload = 1;
2302 } else if (!strcmp(r, "strace")) {
2303 do_strace = 1;
2304 } else
2305 {
2306 usage();
2307 }
2308 }
2309 if (optind >= argc)
2310 usage();
2311 filename = argv[optind];
2312
2313 /* Zero out regs */
2314 memset(regs, 0, sizeof(struct target_pt_regs));
2315
2316 /* Zero out image_info */
2317 memset(info, 0, sizeof(struct image_info));
2318
2319 /* Scan interp_prefix dir for replacement files. */
2320 init_paths(interp_prefix);
2321
2322 if (cpu_model == NULL) {
2323 #if defined(TARGET_I386)
2324 #ifdef TARGET_X86_64
2325 cpu_model = "qemu64";
2326 #else
2327 cpu_model = "qemu32";
2328 #endif
2329 #elif defined(TARGET_ARM)
2330 cpu_model = "arm926";
2331 #elif defined(TARGET_M68K)
2332 cpu_model = "any";
2333 #elif defined(TARGET_SPARC)
2334 #ifdef TARGET_SPARC64
2335 cpu_model = "TI UltraSparc II";
2336 #else
2337 cpu_model = "Fujitsu MB86904";
2338 #endif
2339 #elif defined(TARGET_MIPS)
2340 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
2341 cpu_model = "20Kc";
2342 #else
2343 cpu_model = "24Kf";
2344 #endif
2345 #elif defined(TARGET_PPC)
2346 #ifdef TARGET_PPC64
2347 cpu_model = "970";
2348 #else
2349 cpu_model = "750";
2350 #endif
2351 #else
2352 cpu_model = "any";
2353 #endif
2354 }
2355 cpu_exec_init_all(0);
2356 /* NOTE: we need to init the CPU at this stage to get
2357 qemu_host_page_size */
2358 env = cpu_init(cpu_model);
2359 if (!env) {
2360 fprintf(stderr, "Unable to find CPU definition\n");
2361 exit(1);
2362 }
2363 thread_env = env;
2364
2365 if (getenv("QEMU_STRACE")) {
2366 do_strace = 1;
2367 }
2368
2369 wrk = environ;
2370 while (*(wrk++))
2371 environ_count++;
2372
2373 target_environ = malloc((environ_count + 1) * sizeof(char *));
2374 if (!target_environ)
2375 abort();
2376 for (wrk = environ, dst = target_environ; *wrk; wrk++) {
2377 if (drop_ld_preload && !strncmp(*wrk, "LD_PRELOAD=", 11))
2378 continue;
2379 *(dst++) = strdup(*wrk);
2380 }
2381 *dst = NULL; /* NULL terminate target_environ */
2382
2383 if (loader_exec(filename, argv+optind, target_environ, regs, info) != 0) {
2384 printf("Error loading %s\n", filename);
2385 _exit(1);
2386 }
2387
2388 for (wrk = target_environ; *wrk; wrk++) {
2389 free(*wrk);
2390 }
2391
2392 free(target_environ);
2393
2394 if (loglevel) {
2395 page_dump(logfile);
2396
2397 fprintf(logfile, "start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
2398 fprintf(logfile, "end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
2399 fprintf(logfile, "start_code 0x" TARGET_ABI_FMT_lx "\n",
2400 info->start_code);
2401 fprintf(logfile, "start_data 0x" TARGET_ABI_FMT_lx "\n",
2402 info->start_data);
2403 fprintf(logfile, "end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
2404 fprintf(logfile, "start_stack 0x" TARGET_ABI_FMT_lx "\n",
2405 info->start_stack);
2406 fprintf(logfile, "brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
2407 fprintf(logfile, "entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
2408 }
2409
2410 target_set_brk(info->brk);
2411 syscall_init();
2412 signal_init();
2413
2414 /* build Task State */
2415 memset(ts, 0, sizeof(TaskState));
2416 init_task_state(ts);
2417 ts->info = info;
2418 env->opaque = ts;
2419 env->user_mode_only = 1;
2420
2421 #if defined(TARGET_I386)
2422 cpu_x86_set_cpl(env, 3);
2423
2424 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
2425 env->hflags |= HF_PE_MASK;
2426 if (env->cpuid_features & CPUID_SSE) {
2427 env->cr[4] |= CR4_OSFXSR_MASK;
2428 env->hflags |= HF_OSFXSR_MASK;
2429 }
2430 #ifndef TARGET_ABI32
2431 /* enable 64 bit mode if possible */
2432 if (!(env->cpuid_ext2_features & CPUID_EXT2_LM)) {
2433 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
2434 exit(1);
2435 }
2436 env->cr[4] |= CR4_PAE_MASK;
2437 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
2438 env->hflags |= HF_LMA_MASK;
2439 #endif
2440
2441 /* flags setup : we activate the IRQs by default as in user mode */
2442 env->eflags |= IF_MASK;
2443
2444 /* linux register setup */
2445 #ifndef TARGET_ABI32
2446 env->regs[R_EAX] = regs->rax;
2447 env->regs[R_EBX] = regs->rbx;
2448 env->regs[R_ECX] = regs->rcx;
2449 env->regs[R_EDX] = regs->rdx;
2450 env->regs[R_ESI] = regs->rsi;
2451 env->regs[R_EDI] = regs->rdi;
2452 env->regs[R_EBP] = regs->rbp;
2453 env->regs[R_ESP] = regs->rsp;
2454 env->eip = regs->rip;
2455 #else
2456 env->regs[R_EAX] = regs->eax;
2457 env->regs[R_EBX] = regs->ebx;
2458 env->regs[R_ECX] = regs->ecx;
2459 env->regs[R_EDX] = regs->edx;
2460 env->regs[R_ESI] = regs->esi;
2461 env->regs[R_EDI] = regs->edi;
2462 env->regs[R_EBP] = regs->ebp;
2463 env->regs[R_ESP] = regs->esp;
2464 env->eip = regs->eip;
2465 #endif
2466
2467 /* linux interrupt setup */
2468 #ifndef TARGET_ABI32
2469 env->idt.limit = 511;
2470 #else
2471 env->idt.limit = 255;
2472 #endif
2473 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
2474 PROT_READ|PROT_WRITE,
2475 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
2476 idt_table = g2h(env->idt.base);
2477 set_idt(0, 0);
2478 set_idt(1, 0);
2479 set_idt(2, 0);
2480 set_idt(3, 3);
2481 set_idt(4, 3);
2482 set_idt(5, 0);
2483 set_idt(6, 0);
2484 set_idt(7, 0);
2485 set_idt(8, 0);
2486 set_idt(9, 0);
2487 set_idt(10, 0);
2488 set_idt(11, 0);
2489 set_idt(12, 0);
2490 set_idt(13, 0);
2491 set_idt(14, 0);
2492 set_idt(15, 0);
2493 set_idt(16, 0);
2494 set_idt(17, 0);
2495 set_idt(18, 0);
2496 set_idt(19, 0);
2497 set_idt(0x80, 3);
2498
2499 /* linux segment setup */
2500 {
2501 uint64_t *gdt_table;
2502 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
2503 PROT_READ|PROT_WRITE,
2504 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
2505 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
2506 gdt_table = g2h(env->gdt.base);
2507 #ifdef TARGET_ABI32
2508 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
2509 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
2510 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
2511 #else
2512 /* 64 bit code segment */
2513 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
2514 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
2515 DESC_L_MASK |
2516 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
2517 #endif
2518 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
2519 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
2520 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
2521 }
2522 cpu_x86_load_seg(env, R_CS, __USER_CS);
2523 cpu_x86_load_seg(env, R_SS, __USER_DS);
2524 #ifdef TARGET_ABI32
2525 cpu_x86_load_seg(env, R_DS, __USER_DS);
2526 cpu_x86_load_seg(env, R_ES, __USER_DS);
2527 cpu_x86_load_seg(env, R_FS, __USER_DS);
2528 cpu_x86_load_seg(env, R_GS, __USER_DS);
2529 /* This hack makes Wine work... */
2530 env->segs[R_FS].selector = 0;
2531 #else
2532 cpu_x86_load_seg(env, R_DS, 0);
2533 cpu_x86_load_seg(env, R_ES, 0);
2534 cpu_x86_load_seg(env, R_FS, 0);
2535 cpu_x86_load_seg(env, R_GS, 0);
2536 #endif
2537 #elif defined(TARGET_ARM)
2538 {
2539 int i;
2540 cpsr_write(env, regs->uregs[16], 0xffffffff);
2541 for(i = 0; i < 16; i++) {
2542 env->regs[i] = regs->uregs[i];
2543 }
2544 }
2545 #elif defined(TARGET_SPARC)
2546 {
2547 int i;
2548 env->pc = regs->pc;
2549 env->npc = regs->npc;
2550 env->y = regs->y;
2551 for(i = 0; i < 8; i++)
2552 env->gregs[i] = regs->u_regs[i];
2553 for(i = 0; i < 8; i++)
2554 env->regwptr[i] = regs->u_regs[i + 8];
2555 }
2556 #elif defined(TARGET_PPC)
2557 {
2558 int i;
2559
2560 #if defined(TARGET_PPC64)
2561 #if defined(TARGET_ABI32)
2562 env->msr &= ~((target_ulong)1 << MSR_SF);
2563 #else
2564 env->msr |= (target_ulong)1 << MSR_SF;
2565 #endif
2566 #endif
2567 env->nip = regs->nip;
2568 for(i = 0; i < 32; i++) {
2569 env->gpr[i] = regs->gpr[i];
2570 }
2571 }
2572 #elif defined(TARGET_M68K)
2573 {
2574 env->pc = regs->pc;
2575 env->dregs[0] = regs->d0;
2576 env->dregs[1] = regs->d1;
2577 env->dregs[2] = regs->d2;
2578 env->dregs[3] = regs->d3;
2579 env->dregs[4] = regs->d4;
2580 env->dregs[5] = regs->d5;
2581 env->dregs[6] = regs->d6;
2582 env->dregs[7] = regs->d7;
2583 env->aregs[0] = regs->a0;
2584 env->aregs[1] = regs->a1;
2585 env->aregs[2] = regs->a2;
2586 env->aregs[3] = regs->a3;
2587 env->aregs[4] = regs->a4;
2588 env->aregs[5] = regs->a5;
2589 env->aregs[6] = regs->a6;
2590 env->aregs[7] = regs->usp;
2591 env->sr = regs->sr;
2592 ts->sim_syscalls = 1;
2593 }
2594 #elif defined(TARGET_MIPS)
2595 {
2596 int i;
2597
2598 for(i = 0; i < 32; i++) {
2599 env->active_tc.gpr[i] = regs->regs[i];
2600 }
2601 env->active_tc.PC = regs->cp0_epc;
2602 }
2603 #elif defined(TARGET_SH4)
2604 {
2605 int i;
2606
2607 for(i = 0; i < 16; i++) {
2608 env->gregs[i] = regs->regs[i];
2609 }
2610 env->pc = regs->pc;
2611 }
2612 #elif defined(TARGET_ALPHA)
2613 {
2614 int i;
2615
2616 for(i = 0; i < 28; i++) {
2617 env->ir[i] = ((abi_ulong *)regs)[i];
2618 }
2619 env->ipr[IPR_USP] = regs->usp;
2620 env->ir[30] = regs->usp;
2621 env->pc = regs->pc;
2622 env->unique = regs->unique;
2623 }
2624 #elif defined(TARGET_CRIS)
2625 {
2626 env->regs[0] = regs->r0;
2627 env->regs[1] = regs->r1;
2628 env->regs[2] = regs->r2;
2629 env->regs[3] = regs->r3;
2630 env->regs[4] = regs->r4;
2631 env->regs[5] = regs->r5;
2632 env->regs[6] = regs->r6;
2633 env->regs[7] = regs->r7;
2634 env->regs[8] = regs->r8;
2635 env->regs[9] = regs->r9;
2636 env->regs[10] = regs->r10;
2637 env->regs[11] = regs->r11;
2638 env->regs[12] = regs->r12;
2639 env->regs[13] = regs->r13;
2640 env->regs[14] = info->start_stack;
2641 env->regs[15] = regs->acr;
2642 env->pc = regs->erp;
2643 }
2644 #else
2645 #error unsupported target CPU
2646 #endif
2647
2648 #if defined(TARGET_ARM) || defined(TARGET_M68K)
2649 ts->stack_base = info->start_stack;
2650 ts->heap_base = info->brk;
2651 /* This will be filled in on the first SYS_HEAPINFO call. */
2652 ts->heap_limit = 0;
2653 #endif
2654
2655 if (gdbstub_port) {
2656 gdbserver_start (gdbstub_port);
2657 gdb_handlesig(env, 0);
2658 }
2659 cpu_loop(env);
2660 /* never exits */
2661 return 0;
2662 }
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