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1 /*
2 * qemu user cpu loop
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "qemu/error-report.h"
23 #include "qemu.h"
24 #include "user-internals.h"
25 #include "cpu_loop-common.h"
26 #include "signal-common.h"
27 #include "elf.h"
28 #include "semihosting/common-semi.h"
29
30 void cpu_loop(CPURISCVState *env)
31 {
32 CPUState *cs = env_cpu(env);
33 int trapnr;
34 target_ulong ret;
35
36 for (;;) {
37 cpu_exec_start(cs);
38 trapnr = cpu_exec(cs);
39 cpu_exec_end(cs);
40 process_queued_cpu_work(cs);
41
42 switch (trapnr) {
43 case EXCP_INTERRUPT:
44 /* just indicate that signals should be handled asap */
45 break;
46 case EXCP_ATOMIC:
47 cpu_exec_step_atomic(cs);
48 break;
49 case RISCV_EXCP_U_ECALL:
50 env->pc += 4;
51 if (env->gpr[xA7] == TARGET_NR_arch_specific_syscall + 15) {
52 /* riscv_flush_icache_syscall is a no-op in QEMU as
53 self-modifying code is automatically detected */
54 ret = 0;
55 } else {
56 ret = do_syscall(env,
57 env->gpr[(env->elf_flags & EF_RISCV_RVE)
58 ? xT0 : xA7],
59 env->gpr[xA0],
60 env->gpr[xA1],
61 env->gpr[xA2],
62 env->gpr[xA3],
63 env->gpr[xA4],
64 env->gpr[xA5],
65 0, 0);
66 }
67 if (ret == -QEMU_ERESTARTSYS) {
68 env->pc -= 4;
69 } else if (ret != -QEMU_ESIGRETURN) {
70 env->gpr[xA0] = ret;
71 }
72 if (cs->singlestep_enabled) {
73 goto gdbstep;
74 }
75 break;
76 case RISCV_EXCP_ILLEGAL_INST:
77 force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC, env->pc);
78 break;
79 case RISCV_EXCP_BREAKPOINT:
80 case EXCP_DEBUG:
81 gdbstep:
82 force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc);
83 break;
84 case RISCV_EXCP_SEMIHOST:
85 env->gpr[xA0] = do_common_semihosting(cs);
86 env->pc += 4;
87 break;
88 default:
89 EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
90 trapnr);
91 exit(EXIT_FAILURE);
92 }
93
94 process_pending_signals(env);
95 }
96 }
97
98 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
99 {
100 CPUState *cpu = env_cpu(env);
101 TaskState *ts = cpu->opaque;
102 struct image_info *info = ts->info;
103
104 env->pc = regs->sepc;
105 env->gpr[xSP] = regs->sp;
106 env->elf_flags = info->elf_flags;
107
108 if ((env->misa_ext & RVE) && !(env->elf_flags & EF_RISCV_RVE)) {
109 error_report("Incompatible ELF: RVE cpu requires RVE ABI binary");
110 exit(EXIT_FAILURE);
111 }
112
113 ts->stack_base = info->start_stack;
114 ts->heap_base = info->brk;
115 /* This will be filled in on the first SYS_HEAPINFO call. */
116 ts->heap_limit = 0;
117 }