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exec: Adjust notdirty tracing
[mirror_qemu.git] / memory.c
1 /*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
14 */
15
16 #include "qemu/osdep.h"
17 #include "qapi/error.h"
18 #include "cpu.h"
19 #include "exec/memory.h"
20 #include "exec/address-spaces.h"
21 #include "qapi/visitor.h"
22 #include "qemu/bitops.h"
23 #include "qemu/error-report.h"
24 #include "qemu/main-loop.h"
25 #include "qemu/qemu-print.h"
26 #include "qom/object.h"
27 #include "trace-root.h"
28
29 #include "exec/memory-internal.h"
30 #include "exec/ram_addr.h"
31 #include "sysemu/kvm.h"
32 #include "sysemu/runstate.h"
33 #include "sysemu/tcg.h"
34 #include "sysemu/accel.h"
35 #include "hw/boards.h"
36 #include "migration/vmstate.h"
37
38 //#define DEBUG_UNASSIGNED
39
40 static unsigned memory_region_transaction_depth;
41 static bool memory_region_update_pending;
42 static bool ioeventfd_update_pending;
43 bool global_dirty_log;
44
45 static QTAILQ_HEAD(, MemoryListener) memory_listeners
46 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
47
48 static QTAILQ_HEAD(, AddressSpace) address_spaces
49 = QTAILQ_HEAD_INITIALIZER(address_spaces);
50
51 static GHashTable *flat_views;
52
53 typedef struct AddrRange AddrRange;
54
55 /*
56 * Note that signed integers are needed for negative offsetting in aliases
57 * (large MemoryRegion::alias_offset).
58 */
59 struct AddrRange {
60 Int128 start;
61 Int128 size;
62 };
63
64 static AddrRange addrrange_make(Int128 start, Int128 size)
65 {
66 return (AddrRange) { start, size };
67 }
68
69 static bool addrrange_equal(AddrRange r1, AddrRange r2)
70 {
71 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
72 }
73
74 static Int128 addrrange_end(AddrRange r)
75 {
76 return int128_add(r.start, r.size);
77 }
78
79 static AddrRange addrrange_shift(AddrRange range, Int128 delta)
80 {
81 int128_addto(&range.start, delta);
82 return range;
83 }
84
85 static bool addrrange_contains(AddrRange range, Int128 addr)
86 {
87 return int128_ge(addr, range.start)
88 && int128_lt(addr, addrrange_end(range));
89 }
90
91 static bool addrrange_intersects(AddrRange r1, AddrRange r2)
92 {
93 return addrrange_contains(r1, r2.start)
94 || addrrange_contains(r2, r1.start);
95 }
96
97 static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
98 {
99 Int128 start = int128_max(r1.start, r2.start);
100 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
101 return addrrange_make(start, int128_sub(end, start));
102 }
103
104 enum ListenerDirection { Forward, Reverse };
105
106 #define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
107 do { \
108 MemoryListener *_listener; \
109 \
110 switch (_direction) { \
111 case Forward: \
112 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
113 if (_listener->_callback) { \
114 _listener->_callback(_listener, ##_args); \
115 } \
116 } \
117 break; \
118 case Reverse: \
119 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, link) { \
120 if (_listener->_callback) { \
121 _listener->_callback(_listener, ##_args); \
122 } \
123 } \
124 break; \
125 default: \
126 abort(); \
127 } \
128 } while (0)
129
130 #define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
131 do { \
132 MemoryListener *_listener; \
133 \
134 switch (_direction) { \
135 case Forward: \
136 QTAILQ_FOREACH(_listener, &(_as)->listeners, link_as) { \
137 if (_listener->_callback) { \
138 _listener->_callback(_listener, _section, ##_args); \
139 } \
140 } \
141 break; \
142 case Reverse: \
143 QTAILQ_FOREACH_REVERSE(_listener, &(_as)->listeners, link_as) { \
144 if (_listener->_callback) { \
145 _listener->_callback(_listener, _section, ##_args); \
146 } \
147 } \
148 break; \
149 default: \
150 abort(); \
151 } \
152 } while (0)
153
154 /* No need to ref/unref .mr, the FlatRange keeps it alive. */
155 #define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
156 do { \
157 MemoryRegionSection mrs = section_from_flat_range(fr, \
158 address_space_to_flatview(as)); \
159 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
160 } while(0)
161
162 struct CoalescedMemoryRange {
163 AddrRange addr;
164 QTAILQ_ENTRY(CoalescedMemoryRange) link;
165 };
166
167 struct MemoryRegionIoeventfd {
168 AddrRange addr;
169 bool match_data;
170 uint64_t data;
171 EventNotifier *e;
172 };
173
174 static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd *a,
175 MemoryRegionIoeventfd *b)
176 {
177 if (int128_lt(a->addr.start, b->addr.start)) {
178 return true;
179 } else if (int128_gt(a->addr.start, b->addr.start)) {
180 return false;
181 } else if (int128_lt(a->addr.size, b->addr.size)) {
182 return true;
183 } else if (int128_gt(a->addr.size, b->addr.size)) {
184 return false;
185 } else if (a->match_data < b->match_data) {
186 return true;
187 } else if (a->match_data > b->match_data) {
188 return false;
189 } else if (a->match_data) {
190 if (a->data < b->data) {
191 return true;
192 } else if (a->data > b->data) {
193 return false;
194 }
195 }
196 if (a->e < b->e) {
197 return true;
198 } else if (a->e > b->e) {
199 return false;
200 }
201 return false;
202 }
203
204 static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd *a,
205 MemoryRegionIoeventfd *b)
206 {
207 return !memory_region_ioeventfd_before(a, b)
208 && !memory_region_ioeventfd_before(b, a);
209 }
210
211 /* Range of memory in the global map. Addresses are absolute. */
212 struct FlatRange {
213 MemoryRegion *mr;
214 hwaddr offset_in_region;
215 AddrRange addr;
216 uint8_t dirty_log_mask;
217 bool romd_mode;
218 bool readonly;
219 bool nonvolatile;
220 };
221
222 #define FOR_EACH_FLAT_RANGE(var, view) \
223 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
224
225 static inline MemoryRegionSection
226 section_from_flat_range(FlatRange *fr, FlatView *fv)
227 {
228 return (MemoryRegionSection) {
229 .mr = fr->mr,
230 .fv = fv,
231 .offset_within_region = fr->offset_in_region,
232 .size = fr->addr.size,
233 .offset_within_address_space = int128_get64(fr->addr.start),
234 .readonly = fr->readonly,
235 .nonvolatile = fr->nonvolatile,
236 };
237 }
238
239 static bool flatrange_equal(FlatRange *a, FlatRange *b)
240 {
241 return a->mr == b->mr
242 && addrrange_equal(a->addr, b->addr)
243 && a->offset_in_region == b->offset_in_region
244 && a->romd_mode == b->romd_mode
245 && a->readonly == b->readonly
246 && a->nonvolatile == b->nonvolatile;
247 }
248
249 static FlatView *flatview_new(MemoryRegion *mr_root)
250 {
251 FlatView *view;
252
253 view = g_new0(FlatView, 1);
254 view->ref = 1;
255 view->root = mr_root;
256 memory_region_ref(mr_root);
257 trace_flatview_new(view, mr_root);
258
259 return view;
260 }
261
262 /* Insert a range into a given position. Caller is responsible for maintaining
263 * sorting order.
264 */
265 static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
266 {
267 if (view->nr == view->nr_allocated) {
268 view->nr_allocated = MAX(2 * view->nr, 10);
269 view->ranges = g_realloc(view->ranges,
270 view->nr_allocated * sizeof(*view->ranges));
271 }
272 memmove(view->ranges + pos + 1, view->ranges + pos,
273 (view->nr - pos) * sizeof(FlatRange));
274 view->ranges[pos] = *range;
275 memory_region_ref(range->mr);
276 ++view->nr;
277 }
278
279 static void flatview_destroy(FlatView *view)
280 {
281 int i;
282
283 trace_flatview_destroy(view, view->root);
284 if (view->dispatch) {
285 address_space_dispatch_free(view->dispatch);
286 }
287 for (i = 0; i < view->nr; i++) {
288 memory_region_unref(view->ranges[i].mr);
289 }
290 g_free(view->ranges);
291 memory_region_unref(view->root);
292 g_free(view);
293 }
294
295 static bool flatview_ref(FlatView *view)
296 {
297 return atomic_fetch_inc_nonzero(&view->ref) > 0;
298 }
299
300 void flatview_unref(FlatView *view)
301 {
302 if (atomic_fetch_dec(&view->ref) == 1) {
303 trace_flatview_destroy_rcu(view, view->root);
304 assert(view->root);
305 call_rcu(view, flatview_destroy, rcu);
306 }
307 }
308
309 static bool can_merge(FlatRange *r1, FlatRange *r2)
310 {
311 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
312 && r1->mr == r2->mr
313 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
314 r1->addr.size),
315 int128_make64(r2->offset_in_region))
316 && r1->dirty_log_mask == r2->dirty_log_mask
317 && r1->romd_mode == r2->romd_mode
318 && r1->readonly == r2->readonly
319 && r1->nonvolatile == r2->nonvolatile;
320 }
321
322 /* Attempt to simplify a view by merging adjacent ranges */
323 static void flatview_simplify(FlatView *view)
324 {
325 unsigned i, j, k;
326
327 i = 0;
328 while (i < view->nr) {
329 j = i + 1;
330 while (j < view->nr
331 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
332 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
333 ++j;
334 }
335 ++i;
336 for (k = i; k < j; k++) {
337 memory_region_unref(view->ranges[k].mr);
338 }
339 memmove(&view->ranges[i], &view->ranges[j],
340 (view->nr - j) * sizeof(view->ranges[j]));
341 view->nr -= j - i;
342 }
343 }
344
345 static bool memory_region_big_endian(MemoryRegion *mr)
346 {
347 #ifdef TARGET_WORDS_BIGENDIAN
348 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
349 #else
350 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
351 #endif
352 }
353
354 static void adjust_endianness(MemoryRegion *mr, uint64_t *data, MemOp op)
355 {
356 if ((op & MO_BSWAP) != devend_memop(mr->ops->endianness)) {
357 switch (op & MO_SIZE) {
358 case MO_8:
359 break;
360 case MO_16:
361 *data = bswap16(*data);
362 break;
363 case MO_32:
364 *data = bswap32(*data);
365 break;
366 case MO_64:
367 *data = bswap64(*data);
368 break;
369 default:
370 g_assert_not_reached();
371 }
372 }
373 }
374
375 static inline void memory_region_shift_read_access(uint64_t *value,
376 signed shift,
377 uint64_t mask,
378 uint64_t tmp)
379 {
380 if (shift >= 0) {
381 *value |= (tmp & mask) << shift;
382 } else {
383 *value |= (tmp & mask) >> -shift;
384 }
385 }
386
387 static inline uint64_t memory_region_shift_write_access(uint64_t *value,
388 signed shift,
389 uint64_t mask)
390 {
391 uint64_t tmp;
392
393 if (shift >= 0) {
394 tmp = (*value >> shift) & mask;
395 } else {
396 tmp = (*value << -shift) & mask;
397 }
398
399 return tmp;
400 }
401
402 static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
403 {
404 MemoryRegion *root;
405 hwaddr abs_addr = offset;
406
407 abs_addr += mr->addr;
408 for (root = mr; root->container; ) {
409 root = root->container;
410 abs_addr += root->addr;
411 }
412
413 return abs_addr;
414 }
415
416 static int get_cpu_index(void)
417 {
418 if (current_cpu) {
419 return current_cpu->cpu_index;
420 }
421 return -1;
422 }
423
424 static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
425 hwaddr addr,
426 uint64_t *value,
427 unsigned size,
428 signed shift,
429 uint64_t mask,
430 MemTxAttrs attrs)
431 {
432 uint64_t tmp;
433
434 tmp = mr->ops->read(mr->opaque, addr, size);
435 if (mr->subpage) {
436 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
437 } else if (mr == &io_mem_notdirty) {
438 /* Accesses to code which has previously been translated into a TB show
439 * up in the MMIO path, as accesses to the io_mem_notdirty
440 * MemoryRegion. */
441 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
442 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
443 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
444 }
445 memory_region_shift_read_access(value, shift, mask, tmp);
446 return MEMTX_OK;
447 }
448
449 static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
450 hwaddr addr,
451 uint64_t *value,
452 unsigned size,
453 signed shift,
454 uint64_t mask,
455 MemTxAttrs attrs)
456 {
457 uint64_t tmp = 0;
458 MemTxResult r;
459
460 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
461 if (mr->subpage) {
462 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
463 } else if (mr == &io_mem_notdirty) {
464 /* Accesses to code which has previously been translated into a TB show
465 * up in the MMIO path, as accesses to the io_mem_notdirty
466 * MemoryRegion. */
467 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
468 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
469 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
470 }
471 memory_region_shift_read_access(value, shift, mask, tmp);
472 return r;
473 }
474
475 static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
476 hwaddr addr,
477 uint64_t *value,
478 unsigned size,
479 signed shift,
480 uint64_t mask,
481 MemTxAttrs attrs)
482 {
483 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
484
485 if (mr->subpage) {
486 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
487 } else if (mr == &io_mem_notdirty) {
488 /* Accesses to code which has previously been translated into a TB show
489 * up in the MMIO path, as accesses to the io_mem_notdirty
490 * MemoryRegion. */
491 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
492 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
493 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
494 }
495 mr->ops->write(mr->opaque, addr, tmp, size);
496 return MEMTX_OK;
497 }
498
499 static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
500 hwaddr addr,
501 uint64_t *value,
502 unsigned size,
503 signed shift,
504 uint64_t mask,
505 MemTxAttrs attrs)
506 {
507 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
508
509 if (mr->subpage) {
510 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
511 } else if (mr == &io_mem_notdirty) {
512 /* Accesses to code which has previously been translated into a TB show
513 * up in the MMIO path, as accesses to the io_mem_notdirty
514 * MemoryRegion. */
515 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
516 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
517 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
518 }
519 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
520 }
521
522 static MemTxResult access_with_adjusted_size(hwaddr addr,
523 uint64_t *value,
524 unsigned size,
525 unsigned access_size_min,
526 unsigned access_size_max,
527 MemTxResult (*access_fn)
528 (MemoryRegion *mr,
529 hwaddr addr,
530 uint64_t *value,
531 unsigned size,
532 signed shift,
533 uint64_t mask,
534 MemTxAttrs attrs),
535 MemoryRegion *mr,
536 MemTxAttrs attrs)
537 {
538 uint64_t access_mask;
539 unsigned access_size;
540 unsigned i;
541 MemTxResult r = MEMTX_OK;
542
543 if (!access_size_min) {
544 access_size_min = 1;
545 }
546 if (!access_size_max) {
547 access_size_max = 4;
548 }
549
550 /* FIXME: support unaligned access? */
551 access_size = MAX(MIN(size, access_size_max), access_size_min);
552 access_mask = MAKE_64BIT_MASK(0, access_size * 8);
553 if (memory_region_big_endian(mr)) {
554 for (i = 0; i < size; i += access_size) {
555 r |= access_fn(mr, addr + i, value, access_size,
556 (size - access_size - i) * 8, access_mask, attrs);
557 }
558 } else {
559 for (i = 0; i < size; i += access_size) {
560 r |= access_fn(mr, addr + i, value, access_size, i * 8,
561 access_mask, attrs);
562 }
563 }
564 return r;
565 }
566
567 static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
568 {
569 AddressSpace *as;
570
571 while (mr->container) {
572 mr = mr->container;
573 }
574 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
575 if (mr == as->root) {
576 return as;
577 }
578 }
579 return NULL;
580 }
581
582 /* Render a memory region into the global view. Ranges in @view obscure
583 * ranges in @mr.
584 */
585 static void render_memory_region(FlatView *view,
586 MemoryRegion *mr,
587 Int128 base,
588 AddrRange clip,
589 bool readonly,
590 bool nonvolatile)
591 {
592 MemoryRegion *subregion;
593 unsigned i;
594 hwaddr offset_in_region;
595 Int128 remain;
596 Int128 now;
597 FlatRange fr;
598 AddrRange tmp;
599
600 if (!mr->enabled) {
601 return;
602 }
603
604 int128_addto(&base, int128_make64(mr->addr));
605 readonly |= mr->readonly;
606 nonvolatile |= mr->nonvolatile;
607
608 tmp = addrrange_make(base, mr->size);
609
610 if (!addrrange_intersects(tmp, clip)) {
611 return;
612 }
613
614 clip = addrrange_intersection(tmp, clip);
615
616 if (mr->alias) {
617 int128_subfrom(&base, int128_make64(mr->alias->addr));
618 int128_subfrom(&base, int128_make64(mr->alias_offset));
619 render_memory_region(view, mr->alias, base, clip,
620 readonly, nonvolatile);
621 return;
622 }
623
624 /* Render subregions in priority order. */
625 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
626 render_memory_region(view, subregion, base, clip,
627 readonly, nonvolatile);
628 }
629
630 if (!mr->terminates) {
631 return;
632 }
633
634 offset_in_region = int128_get64(int128_sub(clip.start, base));
635 base = clip.start;
636 remain = clip.size;
637
638 fr.mr = mr;
639 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
640 fr.romd_mode = mr->romd_mode;
641 fr.readonly = readonly;
642 fr.nonvolatile = nonvolatile;
643
644 /* Render the region itself into any gaps left by the current view. */
645 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
646 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
647 continue;
648 }
649 if (int128_lt(base, view->ranges[i].addr.start)) {
650 now = int128_min(remain,
651 int128_sub(view->ranges[i].addr.start, base));
652 fr.offset_in_region = offset_in_region;
653 fr.addr = addrrange_make(base, now);
654 flatview_insert(view, i, &fr);
655 ++i;
656 int128_addto(&base, now);
657 offset_in_region += int128_get64(now);
658 int128_subfrom(&remain, now);
659 }
660 now = int128_sub(int128_min(int128_add(base, remain),
661 addrrange_end(view->ranges[i].addr)),
662 base);
663 int128_addto(&base, now);
664 offset_in_region += int128_get64(now);
665 int128_subfrom(&remain, now);
666 }
667 if (int128_nz(remain)) {
668 fr.offset_in_region = offset_in_region;
669 fr.addr = addrrange_make(base, remain);
670 flatview_insert(view, i, &fr);
671 }
672 }
673
674 static MemoryRegion *memory_region_get_flatview_root(MemoryRegion *mr)
675 {
676 while (mr->enabled) {
677 if (mr->alias) {
678 if (!mr->alias_offset && int128_ge(mr->size, mr->alias->size)) {
679 /* The alias is included in its entirety. Use it as
680 * the "real" root, so that we can share more FlatViews.
681 */
682 mr = mr->alias;
683 continue;
684 }
685 } else if (!mr->terminates) {
686 unsigned int found = 0;
687 MemoryRegion *child, *next = NULL;
688 QTAILQ_FOREACH(child, &mr->subregions, subregions_link) {
689 if (child->enabled) {
690 if (++found > 1) {
691 next = NULL;
692 break;
693 }
694 if (!child->addr && int128_ge(mr->size, child->size)) {
695 /* A child is included in its entirety. If it's the only
696 * enabled one, use it in the hope of finding an alias down the
697 * way. This will also let us share FlatViews.
698 */
699 next = child;
700 }
701 }
702 }
703 if (found == 0) {
704 return NULL;
705 }
706 if (next) {
707 mr = next;
708 continue;
709 }
710 }
711
712 return mr;
713 }
714
715 return NULL;
716 }
717
718 /* Render a memory topology into a list of disjoint absolute ranges. */
719 static FlatView *generate_memory_topology(MemoryRegion *mr)
720 {
721 int i;
722 FlatView *view;
723
724 view = flatview_new(mr);
725
726 if (mr) {
727 render_memory_region(view, mr, int128_zero(),
728 addrrange_make(int128_zero(), int128_2_64()),
729 false, false);
730 }
731 flatview_simplify(view);
732
733 view->dispatch = address_space_dispatch_new(view);
734 for (i = 0; i < view->nr; i++) {
735 MemoryRegionSection mrs =
736 section_from_flat_range(&view->ranges[i], view);
737 flatview_add_to_dispatch(view, &mrs);
738 }
739 address_space_dispatch_compact(view->dispatch);
740 g_hash_table_replace(flat_views, mr, view);
741
742 return view;
743 }
744
745 static void address_space_add_del_ioeventfds(AddressSpace *as,
746 MemoryRegionIoeventfd *fds_new,
747 unsigned fds_new_nb,
748 MemoryRegionIoeventfd *fds_old,
749 unsigned fds_old_nb)
750 {
751 unsigned iold, inew;
752 MemoryRegionIoeventfd *fd;
753 MemoryRegionSection section;
754
755 /* Generate a symmetric difference of the old and new fd sets, adding
756 * and deleting as necessary.
757 */
758
759 iold = inew = 0;
760 while (iold < fds_old_nb || inew < fds_new_nb) {
761 if (iold < fds_old_nb
762 && (inew == fds_new_nb
763 || memory_region_ioeventfd_before(&fds_old[iold],
764 &fds_new[inew]))) {
765 fd = &fds_old[iold];
766 section = (MemoryRegionSection) {
767 .fv = address_space_to_flatview(as),
768 .offset_within_address_space = int128_get64(fd->addr.start),
769 .size = fd->addr.size,
770 };
771 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
772 fd->match_data, fd->data, fd->e);
773 ++iold;
774 } else if (inew < fds_new_nb
775 && (iold == fds_old_nb
776 || memory_region_ioeventfd_before(&fds_new[inew],
777 &fds_old[iold]))) {
778 fd = &fds_new[inew];
779 section = (MemoryRegionSection) {
780 .fv = address_space_to_flatview(as),
781 .offset_within_address_space = int128_get64(fd->addr.start),
782 .size = fd->addr.size,
783 };
784 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
785 fd->match_data, fd->data, fd->e);
786 ++inew;
787 } else {
788 ++iold;
789 ++inew;
790 }
791 }
792 }
793
794 FlatView *address_space_get_flatview(AddressSpace *as)
795 {
796 FlatView *view;
797
798 rcu_read_lock();
799 do {
800 view = address_space_to_flatview(as);
801 /* If somebody has replaced as->current_map concurrently,
802 * flatview_ref returns false.
803 */
804 } while (!flatview_ref(view));
805 rcu_read_unlock();
806 return view;
807 }
808
809 static void address_space_update_ioeventfds(AddressSpace *as)
810 {
811 FlatView *view;
812 FlatRange *fr;
813 unsigned ioeventfd_nb = 0;
814 MemoryRegionIoeventfd *ioeventfds = NULL;
815 AddrRange tmp;
816 unsigned i;
817
818 view = address_space_get_flatview(as);
819 FOR_EACH_FLAT_RANGE(fr, view) {
820 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
821 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
822 int128_sub(fr->addr.start,
823 int128_make64(fr->offset_in_region)));
824 if (addrrange_intersects(fr->addr, tmp)) {
825 ++ioeventfd_nb;
826 ioeventfds = g_realloc(ioeventfds,
827 ioeventfd_nb * sizeof(*ioeventfds));
828 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
829 ioeventfds[ioeventfd_nb-1].addr = tmp;
830 }
831 }
832 }
833
834 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
835 as->ioeventfds, as->ioeventfd_nb);
836
837 g_free(as->ioeventfds);
838 as->ioeventfds = ioeventfds;
839 as->ioeventfd_nb = ioeventfd_nb;
840 flatview_unref(view);
841 }
842
843 /*
844 * Notify the memory listeners about the coalesced IO change events of
845 * range `cmr'. Only the part that has intersection of the specified
846 * FlatRange will be sent.
847 */
848 static void flat_range_coalesced_io_notify(FlatRange *fr, AddressSpace *as,
849 CoalescedMemoryRange *cmr, bool add)
850 {
851 AddrRange tmp;
852
853 tmp = addrrange_shift(cmr->addr,
854 int128_sub(fr->addr.start,
855 int128_make64(fr->offset_in_region)));
856 if (!addrrange_intersects(tmp, fr->addr)) {
857 return;
858 }
859 tmp = addrrange_intersection(tmp, fr->addr);
860
861 if (add) {
862 MEMORY_LISTENER_UPDATE_REGION(fr, as, Forward, coalesced_io_add,
863 int128_get64(tmp.start),
864 int128_get64(tmp.size));
865 } else {
866 MEMORY_LISTENER_UPDATE_REGION(fr, as, Reverse, coalesced_io_del,
867 int128_get64(tmp.start),
868 int128_get64(tmp.size));
869 }
870 }
871
872 static void flat_range_coalesced_io_del(FlatRange *fr, AddressSpace *as)
873 {
874 CoalescedMemoryRange *cmr;
875
876 QTAILQ_FOREACH(cmr, &fr->mr->coalesced, link) {
877 flat_range_coalesced_io_notify(fr, as, cmr, false);
878 }
879 }
880
881 static void flat_range_coalesced_io_add(FlatRange *fr, AddressSpace *as)
882 {
883 MemoryRegion *mr = fr->mr;
884 CoalescedMemoryRange *cmr;
885
886 if (QTAILQ_EMPTY(&mr->coalesced)) {
887 return;
888 }
889
890 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
891 flat_range_coalesced_io_notify(fr, as, cmr, true);
892 }
893 }
894
895 static void address_space_update_topology_pass(AddressSpace *as,
896 const FlatView *old_view,
897 const FlatView *new_view,
898 bool adding)
899 {
900 unsigned iold, inew;
901 FlatRange *frold, *frnew;
902
903 /* Generate a symmetric difference of the old and new memory maps.
904 * Kill ranges in the old map, and instantiate ranges in the new map.
905 */
906 iold = inew = 0;
907 while (iold < old_view->nr || inew < new_view->nr) {
908 if (iold < old_view->nr) {
909 frold = &old_view->ranges[iold];
910 } else {
911 frold = NULL;
912 }
913 if (inew < new_view->nr) {
914 frnew = &new_view->ranges[inew];
915 } else {
916 frnew = NULL;
917 }
918
919 if (frold
920 && (!frnew
921 || int128_lt(frold->addr.start, frnew->addr.start)
922 || (int128_eq(frold->addr.start, frnew->addr.start)
923 && !flatrange_equal(frold, frnew)))) {
924 /* In old but not in new, or in both but attributes changed. */
925
926 if (!adding) {
927 flat_range_coalesced_io_del(frold, as);
928 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
929 }
930
931 ++iold;
932 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
933 /* In both and unchanged (except logging may have changed) */
934
935 if (adding) {
936 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
937 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
938 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
939 frold->dirty_log_mask,
940 frnew->dirty_log_mask);
941 }
942 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
943 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
944 frold->dirty_log_mask,
945 frnew->dirty_log_mask);
946 }
947 }
948
949 ++iold;
950 ++inew;
951 } else {
952 /* In new */
953
954 if (adding) {
955 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
956 flat_range_coalesced_io_add(frnew, as);
957 }
958
959 ++inew;
960 }
961 }
962 }
963
964 static void flatviews_init(void)
965 {
966 static FlatView *empty_view;
967
968 if (flat_views) {
969 return;
970 }
971
972 flat_views = g_hash_table_new_full(g_direct_hash, g_direct_equal, NULL,
973 (GDestroyNotify) flatview_unref);
974 if (!empty_view) {
975 empty_view = generate_memory_topology(NULL);
976 /* We keep it alive forever in the global variable. */
977 flatview_ref(empty_view);
978 } else {
979 g_hash_table_replace(flat_views, NULL, empty_view);
980 flatview_ref(empty_view);
981 }
982 }
983
984 static void flatviews_reset(void)
985 {
986 AddressSpace *as;
987
988 if (flat_views) {
989 g_hash_table_unref(flat_views);
990 flat_views = NULL;
991 }
992 flatviews_init();
993
994 /* Render unique FVs */
995 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
996 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
997
998 if (g_hash_table_lookup(flat_views, physmr)) {
999 continue;
1000 }
1001
1002 generate_memory_topology(physmr);
1003 }
1004 }
1005
1006 static void address_space_set_flatview(AddressSpace *as)
1007 {
1008 FlatView *old_view = address_space_to_flatview(as);
1009 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1010 FlatView *new_view = g_hash_table_lookup(flat_views, physmr);
1011
1012 assert(new_view);
1013
1014 if (old_view == new_view) {
1015 return;
1016 }
1017
1018 if (old_view) {
1019 flatview_ref(old_view);
1020 }
1021
1022 flatview_ref(new_view);
1023
1024 if (!QTAILQ_EMPTY(&as->listeners)) {
1025 FlatView tmpview = { .nr = 0 }, *old_view2 = old_view;
1026
1027 if (!old_view2) {
1028 old_view2 = &tmpview;
1029 }
1030 address_space_update_topology_pass(as, old_view2, new_view, false);
1031 address_space_update_topology_pass(as, old_view2, new_view, true);
1032 }
1033
1034 /* Writes are protected by the BQL. */
1035 atomic_rcu_set(&as->current_map, new_view);
1036 if (old_view) {
1037 flatview_unref(old_view);
1038 }
1039
1040 /* Note that all the old MemoryRegions are still alive up to this
1041 * point. This relieves most MemoryListeners from the need to
1042 * ref/unref the MemoryRegions they get---unless they use them
1043 * outside the iothread mutex, in which case precise reference
1044 * counting is necessary.
1045 */
1046 if (old_view) {
1047 flatview_unref(old_view);
1048 }
1049 }
1050
1051 static void address_space_update_topology(AddressSpace *as)
1052 {
1053 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1054
1055 flatviews_init();
1056 if (!g_hash_table_lookup(flat_views, physmr)) {
1057 generate_memory_topology(physmr);
1058 }
1059 address_space_set_flatview(as);
1060 }
1061
1062 void memory_region_transaction_begin(void)
1063 {
1064 qemu_flush_coalesced_mmio_buffer();
1065 ++memory_region_transaction_depth;
1066 }
1067
1068 void memory_region_transaction_commit(void)
1069 {
1070 AddressSpace *as;
1071
1072 assert(memory_region_transaction_depth);
1073 assert(qemu_mutex_iothread_locked());
1074
1075 --memory_region_transaction_depth;
1076 if (!memory_region_transaction_depth) {
1077 if (memory_region_update_pending) {
1078 flatviews_reset();
1079
1080 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
1081
1082 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1083 address_space_set_flatview(as);
1084 address_space_update_ioeventfds(as);
1085 }
1086 memory_region_update_pending = false;
1087 ioeventfd_update_pending = false;
1088 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
1089 } else if (ioeventfd_update_pending) {
1090 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1091 address_space_update_ioeventfds(as);
1092 }
1093 ioeventfd_update_pending = false;
1094 }
1095 }
1096 }
1097
1098 static void memory_region_destructor_none(MemoryRegion *mr)
1099 {
1100 }
1101
1102 static void memory_region_destructor_ram(MemoryRegion *mr)
1103 {
1104 qemu_ram_free(mr->ram_block);
1105 }
1106
1107 static bool memory_region_need_escape(char c)
1108 {
1109 return c == '/' || c == '[' || c == '\\' || c == ']';
1110 }
1111
1112 static char *memory_region_escape_name(const char *name)
1113 {
1114 const char *p;
1115 char *escaped, *q;
1116 uint8_t c;
1117 size_t bytes = 0;
1118
1119 for (p = name; *p; p++) {
1120 bytes += memory_region_need_escape(*p) ? 4 : 1;
1121 }
1122 if (bytes == p - name) {
1123 return g_memdup(name, bytes + 1);
1124 }
1125
1126 escaped = g_malloc(bytes + 1);
1127 for (p = name, q = escaped; *p; p++) {
1128 c = *p;
1129 if (unlikely(memory_region_need_escape(c))) {
1130 *q++ = '\\';
1131 *q++ = 'x';
1132 *q++ = "0123456789abcdef"[c >> 4];
1133 c = "0123456789abcdef"[c & 15];
1134 }
1135 *q++ = c;
1136 }
1137 *q = 0;
1138 return escaped;
1139 }
1140
1141 static void memory_region_do_init(MemoryRegion *mr,
1142 Object *owner,
1143 const char *name,
1144 uint64_t size)
1145 {
1146 mr->size = int128_make64(size);
1147 if (size == UINT64_MAX) {
1148 mr->size = int128_2_64();
1149 }
1150 mr->name = g_strdup(name);
1151 mr->owner = owner;
1152 mr->ram_block = NULL;
1153
1154 if (name) {
1155 char *escaped_name = memory_region_escape_name(name);
1156 char *name_array = g_strdup_printf("%s[*]", escaped_name);
1157
1158 if (!owner) {
1159 owner = container_get(qdev_get_machine(), "/unattached");
1160 }
1161
1162 object_property_add_child(owner, name_array, OBJECT(mr), &error_abort);
1163 object_unref(OBJECT(mr));
1164 g_free(name_array);
1165 g_free(escaped_name);
1166 }
1167 }
1168
1169 void memory_region_init(MemoryRegion *mr,
1170 Object *owner,
1171 const char *name,
1172 uint64_t size)
1173 {
1174 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
1175 memory_region_do_init(mr, owner, name, size);
1176 }
1177
1178 static void memory_region_get_addr(Object *obj, Visitor *v, const char *name,
1179 void *opaque, Error **errp)
1180 {
1181 MemoryRegion *mr = MEMORY_REGION(obj);
1182 uint64_t value = mr->addr;
1183
1184 visit_type_uint64(v, name, &value, errp);
1185 }
1186
1187 static void memory_region_get_container(Object *obj, Visitor *v,
1188 const char *name, void *opaque,
1189 Error **errp)
1190 {
1191 MemoryRegion *mr = MEMORY_REGION(obj);
1192 gchar *path = (gchar *)"";
1193
1194 if (mr->container) {
1195 path = object_get_canonical_path(OBJECT(mr->container));
1196 }
1197 visit_type_str(v, name, &path, errp);
1198 if (mr->container) {
1199 g_free(path);
1200 }
1201 }
1202
1203 static Object *memory_region_resolve_container(Object *obj, void *opaque,
1204 const char *part)
1205 {
1206 MemoryRegion *mr = MEMORY_REGION(obj);
1207
1208 return OBJECT(mr->container);
1209 }
1210
1211 static void memory_region_get_priority(Object *obj, Visitor *v,
1212 const char *name, void *opaque,
1213 Error **errp)
1214 {
1215 MemoryRegion *mr = MEMORY_REGION(obj);
1216 int32_t value = mr->priority;
1217
1218 visit_type_int32(v, name, &value, errp);
1219 }
1220
1221 static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1222 void *opaque, Error **errp)
1223 {
1224 MemoryRegion *mr = MEMORY_REGION(obj);
1225 uint64_t value = memory_region_size(mr);
1226
1227 visit_type_uint64(v, name, &value, errp);
1228 }
1229
1230 static void memory_region_initfn(Object *obj)
1231 {
1232 MemoryRegion *mr = MEMORY_REGION(obj);
1233 ObjectProperty *op;
1234
1235 mr->ops = &unassigned_mem_ops;
1236 mr->enabled = true;
1237 mr->romd_mode = true;
1238 mr->global_locking = true;
1239 mr->destructor = memory_region_destructor_none;
1240 QTAILQ_INIT(&mr->subregions);
1241 QTAILQ_INIT(&mr->coalesced);
1242
1243 op = object_property_add(OBJECT(mr), "container",
1244 "link<" TYPE_MEMORY_REGION ">",
1245 memory_region_get_container,
1246 NULL, /* memory_region_set_container */
1247 NULL, NULL, &error_abort);
1248 op->resolve = memory_region_resolve_container;
1249
1250 object_property_add(OBJECT(mr), "addr", "uint64",
1251 memory_region_get_addr,
1252 NULL, /* memory_region_set_addr */
1253 NULL, NULL, &error_abort);
1254 object_property_add(OBJECT(mr), "priority", "uint32",
1255 memory_region_get_priority,
1256 NULL, /* memory_region_set_priority */
1257 NULL, NULL, &error_abort);
1258 object_property_add(OBJECT(mr), "size", "uint64",
1259 memory_region_get_size,
1260 NULL, /* memory_region_set_size, */
1261 NULL, NULL, &error_abort);
1262 }
1263
1264 static void iommu_memory_region_initfn(Object *obj)
1265 {
1266 MemoryRegion *mr = MEMORY_REGION(obj);
1267
1268 mr->is_iommu = true;
1269 }
1270
1271 static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1272 unsigned size)
1273 {
1274 #ifdef DEBUG_UNASSIGNED
1275 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
1276 #endif
1277 if (current_cpu != NULL) {
1278 bool is_exec = current_cpu->mem_io_access_type == MMU_INST_FETCH;
1279 cpu_unassigned_access(current_cpu, addr, false, is_exec, 0, size);
1280 }
1281 return 0;
1282 }
1283
1284 static void unassigned_mem_write(void *opaque, hwaddr addr,
1285 uint64_t val, unsigned size)
1286 {
1287 #ifdef DEBUG_UNASSIGNED
1288 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
1289 #endif
1290 if (current_cpu != NULL) {
1291 cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
1292 }
1293 }
1294
1295 static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
1296 unsigned size, bool is_write,
1297 MemTxAttrs attrs)
1298 {
1299 return false;
1300 }
1301
1302 const MemoryRegionOps unassigned_mem_ops = {
1303 .valid.accepts = unassigned_mem_accepts,
1304 .endianness = DEVICE_NATIVE_ENDIAN,
1305 };
1306
1307 static uint64_t memory_region_ram_device_read(void *opaque,
1308 hwaddr addr, unsigned size)
1309 {
1310 MemoryRegion *mr = opaque;
1311 uint64_t data = (uint64_t)~0;
1312
1313 switch (size) {
1314 case 1:
1315 data = *(uint8_t *)(mr->ram_block->host + addr);
1316 break;
1317 case 2:
1318 data = *(uint16_t *)(mr->ram_block->host + addr);
1319 break;
1320 case 4:
1321 data = *(uint32_t *)(mr->ram_block->host + addr);
1322 break;
1323 case 8:
1324 data = *(uint64_t *)(mr->ram_block->host + addr);
1325 break;
1326 }
1327
1328 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1329
1330 return data;
1331 }
1332
1333 static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1334 uint64_t data, unsigned size)
1335 {
1336 MemoryRegion *mr = opaque;
1337
1338 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1339
1340 switch (size) {
1341 case 1:
1342 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1343 break;
1344 case 2:
1345 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1346 break;
1347 case 4:
1348 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1349 break;
1350 case 8:
1351 *(uint64_t *)(mr->ram_block->host + addr) = data;
1352 break;
1353 }
1354 }
1355
1356 static const MemoryRegionOps ram_device_mem_ops = {
1357 .read = memory_region_ram_device_read,
1358 .write = memory_region_ram_device_write,
1359 .endianness = DEVICE_HOST_ENDIAN,
1360 .valid = {
1361 .min_access_size = 1,
1362 .max_access_size = 8,
1363 .unaligned = true,
1364 },
1365 .impl = {
1366 .min_access_size = 1,
1367 .max_access_size = 8,
1368 .unaligned = true,
1369 },
1370 };
1371
1372 bool memory_region_access_valid(MemoryRegion *mr,
1373 hwaddr addr,
1374 unsigned size,
1375 bool is_write,
1376 MemTxAttrs attrs)
1377 {
1378 int access_size_min, access_size_max;
1379 int access_size, i;
1380
1381 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
1382 return false;
1383 }
1384
1385 if (!mr->ops->valid.accepts) {
1386 return true;
1387 }
1388
1389 access_size_min = mr->ops->valid.min_access_size;
1390 if (!mr->ops->valid.min_access_size) {
1391 access_size_min = 1;
1392 }
1393
1394 access_size_max = mr->ops->valid.max_access_size;
1395 if (!mr->ops->valid.max_access_size) {
1396 access_size_max = 4;
1397 }
1398
1399 access_size = MAX(MIN(size, access_size_max), access_size_min);
1400 for (i = 0; i < size; i += access_size) {
1401 if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
1402 is_write, attrs)) {
1403 return false;
1404 }
1405 }
1406
1407 return true;
1408 }
1409
1410 static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1411 hwaddr addr,
1412 uint64_t *pval,
1413 unsigned size,
1414 MemTxAttrs attrs)
1415 {
1416 *pval = 0;
1417
1418 if (mr->ops->read) {
1419 return access_with_adjusted_size(addr, pval, size,
1420 mr->ops->impl.min_access_size,
1421 mr->ops->impl.max_access_size,
1422 memory_region_read_accessor,
1423 mr, attrs);
1424 } else {
1425 return access_with_adjusted_size(addr, pval, size,
1426 mr->ops->impl.min_access_size,
1427 mr->ops->impl.max_access_size,
1428 memory_region_read_with_attrs_accessor,
1429 mr, attrs);
1430 }
1431 }
1432
1433 MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1434 hwaddr addr,
1435 uint64_t *pval,
1436 MemOp op,
1437 MemTxAttrs attrs)
1438 {
1439 unsigned size = memop_size(op);
1440 MemTxResult r;
1441
1442 if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
1443 *pval = unassigned_mem_read(mr, addr, size);
1444 return MEMTX_DECODE_ERROR;
1445 }
1446
1447 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
1448 adjust_endianness(mr, pval, op);
1449 return r;
1450 }
1451
1452 /* Return true if an eventfd was signalled */
1453 static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1454 hwaddr addr,
1455 uint64_t data,
1456 unsigned size,
1457 MemTxAttrs attrs)
1458 {
1459 MemoryRegionIoeventfd ioeventfd = {
1460 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1461 .data = data,
1462 };
1463 unsigned i;
1464
1465 for (i = 0; i < mr->ioeventfd_nb; i++) {
1466 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1467 ioeventfd.e = mr->ioeventfds[i].e;
1468
1469 if (memory_region_ioeventfd_equal(&ioeventfd, &mr->ioeventfds[i])) {
1470 event_notifier_set(ioeventfd.e);
1471 return true;
1472 }
1473 }
1474
1475 return false;
1476 }
1477
1478 MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1479 hwaddr addr,
1480 uint64_t data,
1481 MemOp op,
1482 MemTxAttrs attrs)
1483 {
1484 unsigned size = memop_size(op);
1485
1486 if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
1487 unassigned_mem_write(mr, addr, data, size);
1488 return MEMTX_DECODE_ERROR;
1489 }
1490
1491 adjust_endianness(mr, &data, op);
1492
1493 if ((!kvm_eventfds_enabled()) &&
1494 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1495 return MEMTX_OK;
1496 }
1497
1498 if (mr->ops->write) {
1499 return access_with_adjusted_size(addr, &data, size,
1500 mr->ops->impl.min_access_size,
1501 mr->ops->impl.max_access_size,
1502 memory_region_write_accessor, mr,
1503 attrs);
1504 } else {
1505 return
1506 access_with_adjusted_size(addr, &data, size,
1507 mr->ops->impl.min_access_size,
1508 mr->ops->impl.max_access_size,
1509 memory_region_write_with_attrs_accessor,
1510 mr, attrs);
1511 }
1512 }
1513
1514 void memory_region_init_io(MemoryRegion *mr,
1515 Object *owner,
1516 const MemoryRegionOps *ops,
1517 void *opaque,
1518 const char *name,
1519 uint64_t size)
1520 {
1521 memory_region_init(mr, owner, name, size);
1522 mr->ops = ops ? ops : &unassigned_mem_ops;
1523 mr->opaque = opaque;
1524 mr->terminates = true;
1525 }
1526
1527 void memory_region_init_ram_nomigrate(MemoryRegion *mr,
1528 Object *owner,
1529 const char *name,
1530 uint64_t size,
1531 Error **errp)
1532 {
1533 memory_region_init_ram_shared_nomigrate(mr, owner, name, size, false, errp);
1534 }
1535
1536 void memory_region_init_ram_shared_nomigrate(MemoryRegion *mr,
1537 Object *owner,
1538 const char *name,
1539 uint64_t size,
1540 bool share,
1541 Error **errp)
1542 {
1543 Error *err = NULL;
1544 memory_region_init(mr, owner, name, size);
1545 mr->ram = true;
1546 mr->terminates = true;
1547 mr->destructor = memory_region_destructor_ram;
1548 mr->ram_block = qemu_ram_alloc(size, share, mr, &err);
1549 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1550 if (err) {
1551 mr->size = int128_zero();
1552 object_unparent(OBJECT(mr));
1553 error_propagate(errp, err);
1554 }
1555 }
1556
1557 void memory_region_init_resizeable_ram(MemoryRegion *mr,
1558 Object *owner,
1559 const char *name,
1560 uint64_t size,
1561 uint64_t max_size,
1562 void (*resized)(const char*,
1563 uint64_t length,
1564 void *host),
1565 Error **errp)
1566 {
1567 Error *err = NULL;
1568 memory_region_init(mr, owner, name, size);
1569 mr->ram = true;
1570 mr->terminates = true;
1571 mr->destructor = memory_region_destructor_ram;
1572 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1573 mr, &err);
1574 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1575 if (err) {
1576 mr->size = int128_zero();
1577 object_unparent(OBJECT(mr));
1578 error_propagate(errp, err);
1579 }
1580 }
1581
1582 #ifdef CONFIG_POSIX
1583 void memory_region_init_ram_from_file(MemoryRegion *mr,
1584 struct Object *owner,
1585 const char *name,
1586 uint64_t size,
1587 uint64_t align,
1588 uint32_t ram_flags,
1589 const char *path,
1590 Error **errp)
1591 {
1592 Error *err = NULL;
1593 memory_region_init(mr, owner, name, size);
1594 mr->ram = true;
1595 mr->terminates = true;
1596 mr->destructor = memory_region_destructor_ram;
1597 mr->align = align;
1598 mr->ram_block = qemu_ram_alloc_from_file(size, mr, ram_flags, path, &err);
1599 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1600 if (err) {
1601 mr->size = int128_zero();
1602 object_unparent(OBJECT(mr));
1603 error_propagate(errp, err);
1604 }
1605 }
1606
1607 void memory_region_init_ram_from_fd(MemoryRegion *mr,
1608 struct Object *owner,
1609 const char *name,
1610 uint64_t size,
1611 bool share,
1612 int fd,
1613 Error **errp)
1614 {
1615 Error *err = NULL;
1616 memory_region_init(mr, owner, name, size);
1617 mr->ram = true;
1618 mr->terminates = true;
1619 mr->destructor = memory_region_destructor_ram;
1620 mr->ram_block = qemu_ram_alloc_from_fd(size, mr,
1621 share ? RAM_SHARED : 0,
1622 fd, &err);
1623 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1624 if (err) {
1625 mr->size = int128_zero();
1626 object_unparent(OBJECT(mr));
1627 error_propagate(errp, err);
1628 }
1629 }
1630 #endif
1631
1632 void memory_region_init_ram_ptr(MemoryRegion *mr,
1633 Object *owner,
1634 const char *name,
1635 uint64_t size,
1636 void *ptr)
1637 {
1638 memory_region_init(mr, owner, name, size);
1639 mr->ram = true;
1640 mr->terminates = true;
1641 mr->destructor = memory_region_destructor_ram;
1642 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1643
1644 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1645 assert(ptr != NULL);
1646 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
1647 }
1648
1649 void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1650 Object *owner,
1651 const char *name,
1652 uint64_t size,
1653 void *ptr)
1654 {
1655 memory_region_init(mr, owner, name, size);
1656 mr->ram = true;
1657 mr->terminates = true;
1658 mr->ram_device = true;
1659 mr->ops = &ram_device_mem_ops;
1660 mr->opaque = mr;
1661 mr->destructor = memory_region_destructor_ram;
1662 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1663 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1664 assert(ptr != NULL);
1665 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
1666 }
1667
1668 void memory_region_init_alias(MemoryRegion *mr,
1669 Object *owner,
1670 const char *name,
1671 MemoryRegion *orig,
1672 hwaddr offset,
1673 uint64_t size)
1674 {
1675 memory_region_init(mr, owner, name, size);
1676 mr->alias = orig;
1677 mr->alias_offset = offset;
1678 }
1679
1680 void memory_region_init_rom_nomigrate(MemoryRegion *mr,
1681 struct Object *owner,
1682 const char *name,
1683 uint64_t size,
1684 Error **errp)
1685 {
1686 Error *err = NULL;
1687 memory_region_init(mr, owner, name, size);
1688 mr->ram = true;
1689 mr->readonly = true;
1690 mr->terminates = true;
1691 mr->destructor = memory_region_destructor_ram;
1692 mr->ram_block = qemu_ram_alloc(size, false, mr, &err);
1693 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1694 if (err) {
1695 mr->size = int128_zero();
1696 object_unparent(OBJECT(mr));
1697 error_propagate(errp, err);
1698 }
1699 }
1700
1701 void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
1702 Object *owner,
1703 const MemoryRegionOps *ops,
1704 void *opaque,
1705 const char *name,
1706 uint64_t size,
1707 Error **errp)
1708 {
1709 Error *err = NULL;
1710 assert(ops);
1711 memory_region_init(mr, owner, name, size);
1712 mr->ops = ops;
1713 mr->opaque = opaque;
1714 mr->terminates = true;
1715 mr->rom_device = true;
1716 mr->destructor = memory_region_destructor_ram;
1717 mr->ram_block = qemu_ram_alloc(size, false, mr, &err);
1718 if (err) {
1719 mr->size = int128_zero();
1720 object_unparent(OBJECT(mr));
1721 error_propagate(errp, err);
1722 }
1723 }
1724
1725 void memory_region_init_iommu(void *_iommu_mr,
1726 size_t instance_size,
1727 const char *mrtypename,
1728 Object *owner,
1729 const char *name,
1730 uint64_t size)
1731 {
1732 struct IOMMUMemoryRegion *iommu_mr;
1733 struct MemoryRegion *mr;
1734
1735 object_initialize(_iommu_mr, instance_size, mrtypename);
1736 mr = MEMORY_REGION(_iommu_mr);
1737 memory_region_do_init(mr, owner, name, size);
1738 iommu_mr = IOMMU_MEMORY_REGION(mr);
1739 mr->terminates = true; /* then re-forwards */
1740 QLIST_INIT(&iommu_mr->iommu_notify);
1741 iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
1742 }
1743
1744 static void memory_region_finalize(Object *obj)
1745 {
1746 MemoryRegion *mr = MEMORY_REGION(obj);
1747
1748 assert(!mr->container);
1749
1750 /* We know the region is not visible in any address space (it
1751 * does not have a container and cannot be a root either because
1752 * it has no references, so we can blindly clear mr->enabled.
1753 * memory_region_set_enabled instead could trigger a transaction
1754 * and cause an infinite loop.
1755 */
1756 mr->enabled = false;
1757 memory_region_transaction_begin();
1758 while (!QTAILQ_EMPTY(&mr->subregions)) {
1759 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1760 memory_region_del_subregion(mr, subregion);
1761 }
1762 memory_region_transaction_commit();
1763
1764 mr->destructor(mr);
1765 memory_region_clear_coalescing(mr);
1766 g_free((char *)mr->name);
1767 g_free(mr->ioeventfds);
1768 }
1769
1770 Object *memory_region_owner(MemoryRegion *mr)
1771 {
1772 Object *obj = OBJECT(mr);
1773 return obj->parent;
1774 }
1775
1776 void memory_region_ref(MemoryRegion *mr)
1777 {
1778 /* MMIO callbacks most likely will access data that belongs
1779 * to the owner, hence the need to ref/unref the owner whenever
1780 * the memory region is in use.
1781 *
1782 * The memory region is a child of its owner. As long as the
1783 * owner doesn't call unparent itself on the memory region,
1784 * ref-ing the owner will also keep the memory region alive.
1785 * Memory regions without an owner are supposed to never go away;
1786 * we do not ref/unref them because it slows down DMA sensibly.
1787 */
1788 if (mr && mr->owner) {
1789 object_ref(mr->owner);
1790 }
1791 }
1792
1793 void memory_region_unref(MemoryRegion *mr)
1794 {
1795 if (mr && mr->owner) {
1796 object_unref(mr->owner);
1797 }
1798 }
1799
1800 uint64_t memory_region_size(MemoryRegion *mr)
1801 {
1802 if (int128_eq(mr->size, int128_2_64())) {
1803 return UINT64_MAX;
1804 }
1805 return int128_get64(mr->size);
1806 }
1807
1808 const char *memory_region_name(const MemoryRegion *mr)
1809 {
1810 if (!mr->name) {
1811 ((MemoryRegion *)mr)->name =
1812 object_get_canonical_path_component(OBJECT(mr));
1813 }
1814 return mr->name;
1815 }
1816
1817 bool memory_region_is_ram_device(MemoryRegion *mr)
1818 {
1819 return mr->ram_device;
1820 }
1821
1822 uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
1823 {
1824 uint8_t mask = mr->dirty_log_mask;
1825 if (global_dirty_log && mr->ram_block) {
1826 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1827 }
1828 return mask;
1829 }
1830
1831 bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1832 {
1833 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1834 }
1835
1836 static void memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr)
1837 {
1838 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1839 IOMMUNotifier *iommu_notifier;
1840 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1841
1842 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
1843 flags |= iommu_notifier->notifier_flags;
1844 }
1845
1846 if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) {
1847 imrc->notify_flag_changed(iommu_mr,
1848 iommu_mr->iommu_notify_flags,
1849 flags);
1850 }
1851
1852 iommu_mr->iommu_notify_flags = flags;
1853 }
1854
1855 void memory_region_register_iommu_notifier(MemoryRegion *mr,
1856 IOMMUNotifier *n)
1857 {
1858 IOMMUMemoryRegion *iommu_mr;
1859
1860 if (mr->alias) {
1861 memory_region_register_iommu_notifier(mr->alias, n);
1862 return;
1863 }
1864
1865 /* We need to register for at least one bitfield */
1866 iommu_mr = IOMMU_MEMORY_REGION(mr);
1867 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
1868 assert(n->start <= n->end);
1869 assert(n->iommu_idx >= 0 &&
1870 n->iommu_idx < memory_region_iommu_num_indexes(iommu_mr));
1871
1872 QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node);
1873 memory_region_update_iommu_notify_flags(iommu_mr);
1874 }
1875
1876 uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr)
1877 {
1878 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1879
1880 if (imrc->get_min_page_size) {
1881 return imrc->get_min_page_size(iommu_mr);
1882 }
1883 return TARGET_PAGE_SIZE;
1884 }
1885
1886 void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
1887 {
1888 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
1889 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1890 hwaddr addr, granularity;
1891 IOMMUTLBEntry iotlb;
1892
1893 /* If the IOMMU has its own replay callback, override */
1894 if (imrc->replay) {
1895 imrc->replay(iommu_mr, n);
1896 return;
1897 }
1898
1899 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
1900
1901 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
1902 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, n->iommu_idx);
1903 if (iotlb.perm != IOMMU_NONE) {
1904 n->notify(n, &iotlb);
1905 }
1906
1907 /* if (2^64 - MR size) < granularity, it's possible to get an
1908 * infinite loop here. This should catch such a wraparound */
1909 if ((addr + granularity) < addr) {
1910 break;
1911 }
1912 }
1913 }
1914
1915 void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1916 IOMMUNotifier *n)
1917 {
1918 IOMMUMemoryRegion *iommu_mr;
1919
1920 if (mr->alias) {
1921 memory_region_unregister_iommu_notifier(mr->alias, n);
1922 return;
1923 }
1924 QLIST_REMOVE(n, node);
1925 iommu_mr = IOMMU_MEMORY_REGION(mr);
1926 memory_region_update_iommu_notify_flags(iommu_mr);
1927 }
1928
1929 void memory_region_notify_one(IOMMUNotifier *notifier,
1930 IOMMUTLBEntry *entry)
1931 {
1932 IOMMUNotifierFlag request_flags;
1933 hwaddr entry_end = entry->iova + entry->addr_mask;
1934
1935 /*
1936 * Skip the notification if the notification does not overlap
1937 * with registered range.
1938 */
1939 if (notifier->start > entry_end || notifier->end < entry->iova) {
1940 return;
1941 }
1942
1943 assert(entry->iova >= notifier->start && entry_end <= notifier->end);
1944
1945 if (entry->perm & IOMMU_RW) {
1946 request_flags = IOMMU_NOTIFIER_MAP;
1947 } else {
1948 request_flags = IOMMU_NOTIFIER_UNMAP;
1949 }
1950
1951 if (notifier->notifier_flags & request_flags) {
1952 notifier->notify(notifier, entry);
1953 }
1954 }
1955
1956 void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
1957 int iommu_idx,
1958 IOMMUTLBEntry entry)
1959 {
1960 IOMMUNotifier *iommu_notifier;
1961
1962 assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr)));
1963
1964 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
1965 if (iommu_notifier->iommu_idx == iommu_idx) {
1966 memory_region_notify_one(iommu_notifier, &entry);
1967 }
1968 }
1969 }
1970
1971 int memory_region_iommu_get_attr(IOMMUMemoryRegion *iommu_mr,
1972 enum IOMMUMemoryRegionAttr attr,
1973 void *data)
1974 {
1975 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1976
1977 if (!imrc->get_attr) {
1978 return -EINVAL;
1979 }
1980
1981 return imrc->get_attr(iommu_mr, attr, data);
1982 }
1983
1984 int memory_region_iommu_attrs_to_index(IOMMUMemoryRegion *iommu_mr,
1985 MemTxAttrs attrs)
1986 {
1987 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1988
1989 if (!imrc->attrs_to_index) {
1990 return 0;
1991 }
1992
1993 return imrc->attrs_to_index(iommu_mr, attrs);
1994 }
1995
1996 int memory_region_iommu_num_indexes(IOMMUMemoryRegion *iommu_mr)
1997 {
1998 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1999
2000 if (!imrc->num_indexes) {
2001 return 1;
2002 }
2003
2004 return imrc->num_indexes(iommu_mr);
2005 }
2006
2007 void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
2008 {
2009 uint8_t mask = 1 << client;
2010 uint8_t old_logging;
2011
2012 assert(client == DIRTY_MEMORY_VGA);
2013 old_logging = mr->vga_logging_count;
2014 mr->vga_logging_count += log ? 1 : -1;
2015 if (!!old_logging == !!mr->vga_logging_count) {
2016 return;
2017 }
2018
2019 memory_region_transaction_begin();
2020 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
2021 memory_region_update_pending |= mr->enabled;
2022 memory_region_transaction_commit();
2023 }
2024
2025 void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
2026 hwaddr size)
2027 {
2028 assert(mr->ram_block);
2029 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
2030 size,
2031 memory_region_get_dirty_log_mask(mr));
2032 }
2033
2034 static void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
2035 {
2036 MemoryListener *listener;
2037 AddressSpace *as;
2038 FlatView *view;
2039 FlatRange *fr;
2040
2041 /* If the same address space has multiple log_sync listeners, we
2042 * visit that address space's FlatView multiple times. But because
2043 * log_sync listeners are rare, it's still cheaper than walking each
2044 * address space once.
2045 */
2046 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2047 if (!listener->log_sync) {
2048 continue;
2049 }
2050 as = listener->address_space;
2051 view = address_space_get_flatview(as);
2052 FOR_EACH_FLAT_RANGE(fr, view) {
2053 if (fr->dirty_log_mask && (!mr || fr->mr == mr)) {
2054 MemoryRegionSection mrs = section_from_flat_range(fr, view);
2055 listener->log_sync(listener, &mrs);
2056 }
2057 }
2058 flatview_unref(view);
2059 }
2060 }
2061
2062 void memory_region_clear_dirty_bitmap(MemoryRegion *mr, hwaddr start,
2063 hwaddr len)
2064 {
2065 MemoryRegionSection mrs;
2066 MemoryListener *listener;
2067 AddressSpace *as;
2068 FlatView *view;
2069 FlatRange *fr;
2070 hwaddr sec_start, sec_end, sec_size;
2071
2072 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2073 if (!listener->log_clear) {
2074 continue;
2075 }
2076 as = listener->address_space;
2077 view = address_space_get_flatview(as);
2078 FOR_EACH_FLAT_RANGE(fr, view) {
2079 if (!fr->dirty_log_mask || fr->mr != mr) {
2080 /*
2081 * Clear dirty bitmap operation only applies to those
2082 * regions whose dirty logging is at least enabled
2083 */
2084 continue;
2085 }
2086
2087 mrs = section_from_flat_range(fr, view);
2088
2089 sec_start = MAX(mrs.offset_within_region, start);
2090 sec_end = mrs.offset_within_region + int128_get64(mrs.size);
2091 sec_end = MIN(sec_end, start + len);
2092
2093 if (sec_start >= sec_end) {
2094 /*
2095 * If this memory region section has no intersection
2096 * with the requested range, skip.
2097 */
2098 continue;
2099 }
2100
2101 /* Valid case; shrink the section if needed */
2102 mrs.offset_within_address_space +=
2103 sec_start - mrs.offset_within_region;
2104 mrs.offset_within_region = sec_start;
2105 sec_size = sec_end - sec_start;
2106 mrs.size = int128_make64(sec_size);
2107 listener->log_clear(listener, &mrs);
2108 }
2109 flatview_unref(view);
2110 }
2111 }
2112
2113 DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
2114 hwaddr addr,
2115 hwaddr size,
2116 unsigned client)
2117 {
2118 DirtyBitmapSnapshot *snapshot;
2119 assert(mr->ram_block);
2120 memory_region_sync_dirty_bitmap(mr);
2121 snapshot = cpu_physical_memory_snapshot_and_clear_dirty(mr, addr, size, client);
2122 memory_global_after_dirty_log_sync();
2123 return snapshot;
2124 }
2125
2126 bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
2127 hwaddr addr, hwaddr size)
2128 {
2129 assert(mr->ram_block);
2130 return cpu_physical_memory_snapshot_get_dirty(snap,
2131 memory_region_get_ram_addr(mr) + addr, size);
2132 }
2133
2134 void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
2135 {
2136 if (mr->readonly != readonly) {
2137 memory_region_transaction_begin();
2138 mr->readonly = readonly;
2139 memory_region_update_pending |= mr->enabled;
2140 memory_region_transaction_commit();
2141 }
2142 }
2143
2144 void memory_region_set_nonvolatile(MemoryRegion *mr, bool nonvolatile)
2145 {
2146 if (mr->nonvolatile != nonvolatile) {
2147 memory_region_transaction_begin();
2148 mr->nonvolatile = nonvolatile;
2149 memory_region_update_pending |= mr->enabled;
2150 memory_region_transaction_commit();
2151 }
2152 }
2153
2154 void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
2155 {
2156 if (mr->romd_mode != romd_mode) {
2157 memory_region_transaction_begin();
2158 mr->romd_mode = romd_mode;
2159 memory_region_update_pending |= mr->enabled;
2160 memory_region_transaction_commit();
2161 }
2162 }
2163
2164 void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
2165 hwaddr size, unsigned client)
2166 {
2167 assert(mr->ram_block);
2168 cpu_physical_memory_test_and_clear_dirty(
2169 memory_region_get_ram_addr(mr) + addr, size, client);
2170 }
2171
2172 int memory_region_get_fd(MemoryRegion *mr)
2173 {
2174 int fd;
2175
2176 rcu_read_lock();
2177 while (mr->alias) {
2178 mr = mr->alias;
2179 }
2180 fd = mr->ram_block->fd;
2181 rcu_read_unlock();
2182
2183 return fd;
2184 }
2185
2186 void *memory_region_get_ram_ptr(MemoryRegion *mr)
2187 {
2188 void *ptr;
2189 uint64_t offset = 0;
2190
2191 rcu_read_lock();
2192 while (mr->alias) {
2193 offset += mr->alias_offset;
2194 mr = mr->alias;
2195 }
2196 assert(mr->ram_block);
2197 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
2198 rcu_read_unlock();
2199
2200 return ptr;
2201 }
2202
2203 MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
2204 {
2205 RAMBlock *block;
2206
2207 block = qemu_ram_block_from_host(ptr, false, offset);
2208 if (!block) {
2209 return NULL;
2210 }
2211
2212 return block->mr;
2213 }
2214
2215 ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
2216 {
2217 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
2218 }
2219
2220 void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
2221 {
2222 assert(mr->ram_block);
2223
2224 qemu_ram_resize(mr->ram_block, newsize, errp);
2225 }
2226
2227 /*
2228 * Call proper memory listeners about the change on the newly
2229 * added/removed CoalescedMemoryRange.
2230 */
2231 static void memory_region_update_coalesced_range(MemoryRegion *mr,
2232 CoalescedMemoryRange *cmr,
2233 bool add)
2234 {
2235 AddressSpace *as;
2236 FlatView *view;
2237 FlatRange *fr;
2238
2239 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2240 view = address_space_get_flatview(as);
2241 FOR_EACH_FLAT_RANGE(fr, view) {
2242 if (fr->mr == mr) {
2243 flat_range_coalesced_io_notify(fr, as, cmr, add);
2244 }
2245 }
2246 flatview_unref(view);
2247 }
2248 }
2249
2250 void memory_region_set_coalescing(MemoryRegion *mr)
2251 {
2252 memory_region_clear_coalescing(mr);
2253 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
2254 }
2255
2256 void memory_region_add_coalescing(MemoryRegion *mr,
2257 hwaddr offset,
2258 uint64_t size)
2259 {
2260 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
2261
2262 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
2263 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
2264 memory_region_update_coalesced_range(mr, cmr, true);
2265 memory_region_set_flush_coalesced(mr);
2266 }
2267
2268 void memory_region_clear_coalescing(MemoryRegion *mr)
2269 {
2270 CoalescedMemoryRange *cmr;
2271
2272 if (QTAILQ_EMPTY(&mr->coalesced)) {
2273 return;
2274 }
2275
2276 qemu_flush_coalesced_mmio_buffer();
2277 mr->flush_coalesced_mmio = false;
2278
2279 while (!QTAILQ_EMPTY(&mr->coalesced)) {
2280 cmr = QTAILQ_FIRST(&mr->coalesced);
2281 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
2282 memory_region_update_coalesced_range(mr, cmr, false);
2283 g_free(cmr);
2284 }
2285 }
2286
2287 void memory_region_set_flush_coalesced(MemoryRegion *mr)
2288 {
2289 mr->flush_coalesced_mmio = true;
2290 }
2291
2292 void memory_region_clear_flush_coalesced(MemoryRegion *mr)
2293 {
2294 qemu_flush_coalesced_mmio_buffer();
2295 if (QTAILQ_EMPTY(&mr->coalesced)) {
2296 mr->flush_coalesced_mmio = false;
2297 }
2298 }
2299
2300 void memory_region_clear_global_locking(MemoryRegion *mr)
2301 {
2302 mr->global_locking = false;
2303 }
2304
2305 static bool userspace_eventfd_warning;
2306
2307 void memory_region_add_eventfd(MemoryRegion *mr,
2308 hwaddr addr,
2309 unsigned size,
2310 bool match_data,
2311 uint64_t data,
2312 EventNotifier *e)
2313 {
2314 MemoryRegionIoeventfd mrfd = {
2315 .addr.start = int128_make64(addr),
2316 .addr.size = int128_make64(size),
2317 .match_data = match_data,
2318 .data = data,
2319 .e = e,
2320 };
2321 unsigned i;
2322
2323 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2324 userspace_eventfd_warning))) {
2325 userspace_eventfd_warning = true;
2326 error_report("Using eventfd without MMIO binding in KVM. "
2327 "Suboptimal performance expected");
2328 }
2329
2330 if (size) {
2331 adjust_endianness(mr, &mrfd.data, size_memop(size) | MO_TE);
2332 }
2333 memory_region_transaction_begin();
2334 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2335 if (memory_region_ioeventfd_before(&mrfd, &mr->ioeventfds[i])) {
2336 break;
2337 }
2338 }
2339 ++mr->ioeventfd_nb;
2340 mr->ioeventfds = g_realloc(mr->ioeventfds,
2341 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2342 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2343 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2344 mr->ioeventfds[i] = mrfd;
2345 ioeventfd_update_pending |= mr->enabled;
2346 memory_region_transaction_commit();
2347 }
2348
2349 void memory_region_del_eventfd(MemoryRegion *mr,
2350 hwaddr addr,
2351 unsigned size,
2352 bool match_data,
2353 uint64_t data,
2354 EventNotifier *e)
2355 {
2356 MemoryRegionIoeventfd mrfd = {
2357 .addr.start = int128_make64(addr),
2358 .addr.size = int128_make64(size),
2359 .match_data = match_data,
2360 .data = data,
2361 .e = e,
2362 };
2363 unsigned i;
2364
2365 if (size) {
2366 adjust_endianness(mr, &mrfd.data, size_memop(size) | MO_TE);
2367 }
2368 memory_region_transaction_begin();
2369 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2370 if (memory_region_ioeventfd_equal(&mrfd, &mr->ioeventfds[i])) {
2371 break;
2372 }
2373 }
2374 assert(i != mr->ioeventfd_nb);
2375 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2376 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2377 --mr->ioeventfd_nb;
2378 mr->ioeventfds = g_realloc(mr->ioeventfds,
2379 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
2380 ioeventfd_update_pending |= mr->enabled;
2381 memory_region_transaction_commit();
2382 }
2383
2384 static void memory_region_update_container_subregions(MemoryRegion *subregion)
2385 {
2386 MemoryRegion *mr = subregion->container;
2387 MemoryRegion *other;
2388
2389 memory_region_transaction_begin();
2390
2391 memory_region_ref(subregion);
2392 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2393 if (subregion->priority >= other->priority) {
2394 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2395 goto done;
2396 }
2397 }
2398 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2399 done:
2400 memory_region_update_pending |= mr->enabled && subregion->enabled;
2401 memory_region_transaction_commit();
2402 }
2403
2404 static void memory_region_add_subregion_common(MemoryRegion *mr,
2405 hwaddr offset,
2406 MemoryRegion *subregion)
2407 {
2408 assert(!subregion->container);
2409 subregion->container = mr;
2410 subregion->addr = offset;
2411 memory_region_update_container_subregions(subregion);
2412 }
2413
2414 void memory_region_add_subregion(MemoryRegion *mr,
2415 hwaddr offset,
2416 MemoryRegion *subregion)
2417 {
2418 subregion->priority = 0;
2419 memory_region_add_subregion_common(mr, offset, subregion);
2420 }
2421
2422 void memory_region_add_subregion_overlap(MemoryRegion *mr,
2423 hwaddr offset,
2424 MemoryRegion *subregion,
2425 int priority)
2426 {
2427 subregion->priority = priority;
2428 memory_region_add_subregion_common(mr, offset, subregion);
2429 }
2430
2431 void memory_region_del_subregion(MemoryRegion *mr,
2432 MemoryRegion *subregion)
2433 {
2434 memory_region_transaction_begin();
2435 assert(subregion->container == mr);
2436 subregion->container = NULL;
2437 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
2438 memory_region_unref(subregion);
2439 memory_region_update_pending |= mr->enabled && subregion->enabled;
2440 memory_region_transaction_commit();
2441 }
2442
2443 void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2444 {
2445 if (enabled == mr->enabled) {
2446 return;
2447 }
2448 memory_region_transaction_begin();
2449 mr->enabled = enabled;
2450 memory_region_update_pending = true;
2451 memory_region_transaction_commit();
2452 }
2453
2454 void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2455 {
2456 Int128 s = int128_make64(size);
2457
2458 if (size == UINT64_MAX) {
2459 s = int128_2_64();
2460 }
2461 if (int128_eq(s, mr->size)) {
2462 return;
2463 }
2464 memory_region_transaction_begin();
2465 mr->size = s;
2466 memory_region_update_pending = true;
2467 memory_region_transaction_commit();
2468 }
2469
2470 static void memory_region_readd_subregion(MemoryRegion *mr)
2471 {
2472 MemoryRegion *container = mr->container;
2473
2474 if (container) {
2475 memory_region_transaction_begin();
2476 memory_region_ref(mr);
2477 memory_region_del_subregion(container, mr);
2478 mr->container = container;
2479 memory_region_update_container_subregions(mr);
2480 memory_region_unref(mr);
2481 memory_region_transaction_commit();
2482 }
2483 }
2484
2485 void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2486 {
2487 if (addr != mr->addr) {
2488 mr->addr = addr;
2489 memory_region_readd_subregion(mr);
2490 }
2491 }
2492
2493 void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
2494 {
2495 assert(mr->alias);
2496
2497 if (offset == mr->alias_offset) {
2498 return;
2499 }
2500
2501 memory_region_transaction_begin();
2502 mr->alias_offset = offset;
2503 memory_region_update_pending |= mr->enabled;
2504 memory_region_transaction_commit();
2505 }
2506
2507 uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2508 {
2509 return mr->align;
2510 }
2511
2512 static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2513 {
2514 const AddrRange *addr = addr_;
2515 const FlatRange *fr = fr_;
2516
2517 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2518 return -1;
2519 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2520 return 1;
2521 }
2522 return 0;
2523 }
2524
2525 static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
2526 {
2527 return bsearch(&addr, view->ranges, view->nr,
2528 sizeof(FlatRange), cmp_flatrange_addr);
2529 }
2530
2531 bool memory_region_is_mapped(MemoryRegion *mr)
2532 {
2533 return mr->container ? true : false;
2534 }
2535
2536 /* Same as memory_region_find, but it does not add a reference to the
2537 * returned region. It must be called from an RCU critical section.
2538 */
2539 static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2540 hwaddr addr, uint64_t size)
2541 {
2542 MemoryRegionSection ret = { .mr = NULL };
2543 MemoryRegion *root;
2544 AddressSpace *as;
2545 AddrRange range;
2546 FlatView *view;
2547 FlatRange *fr;
2548
2549 addr += mr->addr;
2550 for (root = mr; root->container; ) {
2551 root = root->container;
2552 addr += root->addr;
2553 }
2554
2555 as = memory_region_to_address_space(root);
2556 if (!as) {
2557 return ret;
2558 }
2559 range = addrrange_make(int128_make64(addr), int128_make64(size));
2560
2561 view = address_space_to_flatview(as);
2562 fr = flatview_lookup(view, range);
2563 if (!fr) {
2564 return ret;
2565 }
2566
2567 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
2568 --fr;
2569 }
2570
2571 ret.mr = fr->mr;
2572 ret.fv = view;
2573 range = addrrange_intersection(range, fr->addr);
2574 ret.offset_within_region = fr->offset_in_region;
2575 ret.offset_within_region += int128_get64(int128_sub(range.start,
2576 fr->addr.start));
2577 ret.size = range.size;
2578 ret.offset_within_address_space = int128_get64(range.start);
2579 ret.readonly = fr->readonly;
2580 ret.nonvolatile = fr->nonvolatile;
2581 return ret;
2582 }
2583
2584 MemoryRegionSection memory_region_find(MemoryRegion *mr,
2585 hwaddr addr, uint64_t size)
2586 {
2587 MemoryRegionSection ret;
2588 rcu_read_lock();
2589 ret = memory_region_find_rcu(mr, addr, size);
2590 if (ret.mr) {
2591 memory_region_ref(ret.mr);
2592 }
2593 rcu_read_unlock();
2594 return ret;
2595 }
2596
2597 bool memory_region_present(MemoryRegion *container, hwaddr addr)
2598 {
2599 MemoryRegion *mr;
2600
2601 rcu_read_lock();
2602 mr = memory_region_find_rcu(container, addr, 1).mr;
2603 rcu_read_unlock();
2604 return mr && mr != container;
2605 }
2606
2607 void memory_global_dirty_log_sync(void)
2608 {
2609 memory_region_sync_dirty_bitmap(NULL);
2610 }
2611
2612 void memory_global_after_dirty_log_sync(void)
2613 {
2614 MEMORY_LISTENER_CALL_GLOBAL(log_global_after_sync, Forward);
2615 }
2616
2617 static VMChangeStateEntry *vmstate_change;
2618
2619 void memory_global_dirty_log_start(void)
2620 {
2621 if (vmstate_change) {
2622 qemu_del_vm_change_state_handler(vmstate_change);
2623 vmstate_change = NULL;
2624 }
2625
2626 global_dirty_log = true;
2627
2628 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
2629
2630 /* Refresh DIRTY_MEMORY_MIGRATION bit. */
2631 memory_region_transaction_begin();
2632 memory_region_update_pending = true;
2633 memory_region_transaction_commit();
2634 }
2635
2636 static void memory_global_dirty_log_do_stop(void)
2637 {
2638 global_dirty_log = false;
2639
2640 /* Refresh DIRTY_MEMORY_MIGRATION bit. */
2641 memory_region_transaction_begin();
2642 memory_region_update_pending = true;
2643 memory_region_transaction_commit();
2644
2645 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
2646 }
2647
2648 static void memory_vm_change_state_handler(void *opaque, int running,
2649 RunState state)
2650 {
2651 if (running) {
2652 memory_global_dirty_log_do_stop();
2653
2654 if (vmstate_change) {
2655 qemu_del_vm_change_state_handler(vmstate_change);
2656 vmstate_change = NULL;
2657 }
2658 }
2659 }
2660
2661 void memory_global_dirty_log_stop(void)
2662 {
2663 if (!runstate_is_running()) {
2664 if (vmstate_change) {
2665 return;
2666 }
2667 vmstate_change = qemu_add_vm_change_state_handler(
2668 memory_vm_change_state_handler, NULL);
2669 return;
2670 }
2671
2672 memory_global_dirty_log_do_stop();
2673 }
2674
2675 static void listener_add_address_space(MemoryListener *listener,
2676 AddressSpace *as)
2677 {
2678 FlatView *view;
2679 FlatRange *fr;
2680
2681 if (listener->begin) {
2682 listener->begin(listener);
2683 }
2684 if (global_dirty_log) {
2685 if (listener->log_global_start) {
2686 listener->log_global_start(listener);
2687 }
2688 }
2689
2690 view = address_space_get_flatview(as);
2691 FOR_EACH_FLAT_RANGE(fr, view) {
2692 MemoryRegionSection section = section_from_flat_range(fr, view);
2693
2694 if (listener->region_add) {
2695 listener->region_add(listener, &section);
2696 }
2697 if (fr->dirty_log_mask && listener->log_start) {
2698 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2699 }
2700 }
2701 if (listener->commit) {
2702 listener->commit(listener);
2703 }
2704 flatview_unref(view);
2705 }
2706
2707 static void listener_del_address_space(MemoryListener *listener,
2708 AddressSpace *as)
2709 {
2710 FlatView *view;
2711 FlatRange *fr;
2712
2713 if (listener->begin) {
2714 listener->begin(listener);
2715 }
2716 view = address_space_get_flatview(as);
2717 FOR_EACH_FLAT_RANGE(fr, view) {
2718 MemoryRegionSection section = section_from_flat_range(fr, view);
2719
2720 if (fr->dirty_log_mask && listener->log_stop) {
2721 listener->log_stop(listener, &section, fr->dirty_log_mask, 0);
2722 }
2723 if (listener->region_del) {
2724 listener->region_del(listener, &section);
2725 }
2726 }
2727 if (listener->commit) {
2728 listener->commit(listener);
2729 }
2730 flatview_unref(view);
2731 }
2732
2733 void memory_listener_register(MemoryListener *listener, AddressSpace *as)
2734 {
2735 MemoryListener *other = NULL;
2736
2737 listener->address_space = as;
2738 if (QTAILQ_EMPTY(&memory_listeners)
2739 || listener->priority >= QTAILQ_LAST(&memory_listeners)->priority) {
2740 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2741 } else {
2742 QTAILQ_FOREACH(other, &memory_listeners, link) {
2743 if (listener->priority < other->priority) {
2744 break;
2745 }
2746 }
2747 QTAILQ_INSERT_BEFORE(other, listener, link);
2748 }
2749
2750 if (QTAILQ_EMPTY(&as->listeners)
2751 || listener->priority >= QTAILQ_LAST(&as->listeners)->priority) {
2752 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2753 } else {
2754 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2755 if (listener->priority < other->priority) {
2756 break;
2757 }
2758 }
2759 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2760 }
2761
2762 listener_add_address_space(listener, as);
2763 }
2764
2765 void memory_listener_unregister(MemoryListener *listener)
2766 {
2767 if (!listener->address_space) {
2768 return;
2769 }
2770
2771 listener_del_address_space(listener, listener->address_space);
2772 QTAILQ_REMOVE(&memory_listeners, listener, link);
2773 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
2774 listener->address_space = NULL;
2775 }
2776
2777 void address_space_remove_listeners(AddressSpace *as)
2778 {
2779 while (!QTAILQ_EMPTY(&as->listeners)) {
2780 memory_listener_unregister(QTAILQ_FIRST(&as->listeners));
2781 }
2782 }
2783
2784 void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
2785 {
2786 memory_region_ref(root);
2787 as->root = root;
2788 as->current_map = NULL;
2789 as->ioeventfd_nb = 0;
2790 as->ioeventfds = NULL;
2791 QTAILQ_INIT(&as->listeners);
2792 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
2793 as->name = g_strdup(name ? name : "anonymous");
2794 address_space_update_topology(as);
2795 address_space_update_ioeventfds(as);
2796 }
2797
2798 static void do_address_space_destroy(AddressSpace *as)
2799 {
2800 assert(QTAILQ_EMPTY(&as->listeners));
2801
2802 flatview_unref(as->current_map);
2803 g_free(as->name);
2804 g_free(as->ioeventfds);
2805 memory_region_unref(as->root);
2806 }
2807
2808 void address_space_destroy(AddressSpace *as)
2809 {
2810 MemoryRegion *root = as->root;
2811
2812 /* Flush out anything from MemoryListeners listening in on this */
2813 memory_region_transaction_begin();
2814 as->root = NULL;
2815 memory_region_transaction_commit();
2816 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
2817
2818 /* At this point, as->dispatch and as->current_map are dummy
2819 * entries that the guest should never use. Wait for the old
2820 * values to expire before freeing the data.
2821 */
2822 as->root = root;
2823 call_rcu(as, do_address_space_destroy, rcu);
2824 }
2825
2826 static const char *memory_region_type(MemoryRegion *mr)
2827 {
2828 if (memory_region_is_ram_device(mr)) {
2829 return "ramd";
2830 } else if (memory_region_is_romd(mr)) {
2831 return "romd";
2832 } else if (memory_region_is_rom(mr)) {
2833 return "rom";
2834 } else if (memory_region_is_ram(mr)) {
2835 return "ram";
2836 } else {
2837 return "i/o";
2838 }
2839 }
2840
2841 typedef struct MemoryRegionList MemoryRegionList;
2842
2843 struct MemoryRegionList {
2844 const MemoryRegion *mr;
2845 QTAILQ_ENTRY(MemoryRegionList) mrqueue;
2846 };
2847
2848 typedef QTAILQ_HEAD(, MemoryRegionList) MemoryRegionListHead;
2849
2850 #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
2851 int128_sub((size), int128_one())) : 0)
2852 #define MTREE_INDENT " "
2853
2854 static void mtree_expand_owner(const char *label, Object *obj)
2855 {
2856 DeviceState *dev = (DeviceState *) object_dynamic_cast(obj, TYPE_DEVICE);
2857
2858 qemu_printf(" %s:{%s", label, dev ? "dev" : "obj");
2859 if (dev && dev->id) {
2860 qemu_printf(" id=%s", dev->id);
2861 } else {
2862 gchar *canonical_path = object_get_canonical_path(obj);
2863 if (canonical_path) {
2864 qemu_printf(" path=%s", canonical_path);
2865 g_free(canonical_path);
2866 } else {
2867 qemu_printf(" type=%s", object_get_typename(obj));
2868 }
2869 }
2870 qemu_printf("}");
2871 }
2872
2873 static void mtree_print_mr_owner(const MemoryRegion *mr)
2874 {
2875 Object *owner = mr->owner;
2876 Object *parent = memory_region_owner((MemoryRegion *)mr);
2877
2878 if (!owner && !parent) {
2879 qemu_printf(" orphan");
2880 return;
2881 }
2882 if (owner) {
2883 mtree_expand_owner("owner", owner);
2884 }
2885 if (parent && parent != owner) {
2886 mtree_expand_owner("parent", parent);
2887 }
2888 }
2889
2890 static void mtree_print_mr(const MemoryRegion *mr, unsigned int level,
2891 hwaddr base,
2892 MemoryRegionListHead *alias_print_queue,
2893 bool owner)
2894 {
2895 MemoryRegionList *new_ml, *ml, *next_ml;
2896 MemoryRegionListHead submr_print_queue;
2897 const MemoryRegion *submr;
2898 unsigned int i;
2899 hwaddr cur_start, cur_end;
2900
2901 if (!mr) {
2902 return;
2903 }
2904
2905 for (i = 0; i < level; i++) {
2906 qemu_printf(MTREE_INDENT);
2907 }
2908
2909 cur_start = base + mr->addr;
2910 cur_end = cur_start + MR_SIZE(mr->size);
2911
2912 /*
2913 * Try to detect overflow of memory region. This should never
2914 * happen normally. When it happens, we dump something to warn the
2915 * user who is observing this.
2916 */
2917 if (cur_start < base || cur_end < cur_start) {
2918 qemu_printf("[DETECTED OVERFLOW!] ");
2919 }
2920
2921 if (mr->alias) {
2922 MemoryRegionList *ml;
2923 bool found = false;
2924
2925 /* check if the alias is already in the queue */
2926 QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) {
2927 if (ml->mr == mr->alias) {
2928 found = true;
2929 }
2930 }
2931
2932 if (!found) {
2933 ml = g_new(MemoryRegionList, 1);
2934 ml->mr = mr->alias;
2935 QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue);
2936 }
2937 qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx
2938 " (prio %d, %s%s): alias %s @%s " TARGET_FMT_plx
2939 "-" TARGET_FMT_plx "%s",
2940 cur_start, cur_end,
2941 mr->priority,
2942 mr->nonvolatile ? "nv-" : "",
2943 memory_region_type((MemoryRegion *)mr),
2944 memory_region_name(mr),
2945 memory_region_name(mr->alias),
2946 mr->alias_offset,
2947 mr->alias_offset + MR_SIZE(mr->size),
2948 mr->enabled ? "" : " [disabled]");
2949 if (owner) {
2950 mtree_print_mr_owner(mr);
2951 }
2952 } else {
2953 qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx
2954 " (prio %d, %s%s): %s%s",
2955 cur_start, cur_end,
2956 mr->priority,
2957 mr->nonvolatile ? "nv-" : "",
2958 memory_region_type((MemoryRegion *)mr),
2959 memory_region_name(mr),
2960 mr->enabled ? "" : " [disabled]");
2961 if (owner) {
2962 mtree_print_mr_owner(mr);
2963 }
2964 }
2965 qemu_printf("\n");
2966
2967 QTAILQ_INIT(&submr_print_queue);
2968
2969 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
2970 new_ml = g_new(MemoryRegionList, 1);
2971 new_ml->mr = submr;
2972 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
2973 if (new_ml->mr->addr < ml->mr->addr ||
2974 (new_ml->mr->addr == ml->mr->addr &&
2975 new_ml->mr->priority > ml->mr->priority)) {
2976 QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue);
2977 new_ml = NULL;
2978 break;
2979 }
2980 }
2981 if (new_ml) {
2982 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue);
2983 }
2984 }
2985
2986 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
2987 mtree_print_mr(ml->mr, level + 1, cur_start,
2988 alias_print_queue, owner);
2989 }
2990
2991 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) {
2992 g_free(ml);
2993 }
2994 }
2995
2996 struct FlatViewInfo {
2997 int counter;
2998 bool dispatch_tree;
2999 bool owner;
3000 AccelClass *ac;
3001 const char *ac_name;
3002 };
3003
3004 static void mtree_print_flatview(gpointer key, gpointer value,
3005 gpointer user_data)
3006 {
3007 FlatView *view = key;
3008 GArray *fv_address_spaces = value;
3009 struct FlatViewInfo *fvi = user_data;
3010 FlatRange *range = &view->ranges[0];
3011 MemoryRegion *mr;
3012 int n = view->nr;
3013 int i;
3014 AddressSpace *as;
3015
3016 qemu_printf("FlatView #%d\n", fvi->counter);
3017 ++fvi->counter;
3018
3019 for (i = 0; i < fv_address_spaces->len; ++i) {
3020 as = g_array_index(fv_address_spaces, AddressSpace*, i);
3021 qemu_printf(" AS \"%s\", root: %s",
3022 as->name, memory_region_name(as->root));
3023 if (as->root->alias) {
3024 qemu_printf(", alias %s", memory_region_name(as->root->alias));
3025 }
3026 qemu_printf("\n");
3027 }
3028
3029 qemu_printf(" Root memory region: %s\n",
3030 view->root ? memory_region_name(view->root) : "(none)");
3031
3032 if (n <= 0) {
3033 qemu_printf(MTREE_INDENT "No rendered FlatView\n\n");
3034 return;
3035 }
3036
3037 while (n--) {
3038 mr = range->mr;
3039 if (range->offset_in_region) {
3040 qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx
3041 " (prio %d, %s%s): %s @" TARGET_FMT_plx,
3042 int128_get64(range->addr.start),
3043 int128_get64(range->addr.start)
3044 + MR_SIZE(range->addr.size),
3045 mr->priority,
3046 range->nonvolatile ? "nv-" : "",
3047 range->readonly ? "rom" : memory_region_type(mr),
3048 memory_region_name(mr),
3049 range->offset_in_region);
3050 } else {
3051 qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx
3052 " (prio %d, %s%s): %s",
3053 int128_get64(range->addr.start),
3054 int128_get64(range->addr.start)
3055 + MR_SIZE(range->addr.size),
3056 mr->priority,
3057 range->nonvolatile ? "nv-" : "",
3058 range->readonly ? "rom" : memory_region_type(mr),
3059 memory_region_name(mr));
3060 }
3061 if (fvi->owner) {
3062 mtree_print_mr_owner(mr);
3063 }
3064
3065 if (fvi->ac) {
3066 for (i = 0; i < fv_address_spaces->len; ++i) {
3067 as = g_array_index(fv_address_spaces, AddressSpace*, i);
3068 if (fvi->ac->has_memory(current_machine, as,
3069 int128_get64(range->addr.start),
3070 MR_SIZE(range->addr.size) + 1)) {
3071 qemu_printf(" %s", fvi->ac_name);
3072 }
3073 }
3074 }
3075 qemu_printf("\n");
3076 range++;
3077 }
3078
3079 #if !defined(CONFIG_USER_ONLY)
3080 if (fvi->dispatch_tree && view->root) {
3081 mtree_print_dispatch(view->dispatch, view->root);
3082 }
3083 #endif
3084
3085 qemu_printf("\n");
3086 }
3087
3088 static gboolean mtree_info_flatview_free(gpointer key, gpointer value,
3089 gpointer user_data)
3090 {
3091 FlatView *view = key;
3092 GArray *fv_address_spaces = value;
3093
3094 g_array_unref(fv_address_spaces);
3095 flatview_unref(view);
3096
3097 return true;
3098 }
3099
3100 void mtree_info(bool flatview, bool dispatch_tree, bool owner)
3101 {
3102 MemoryRegionListHead ml_head;
3103 MemoryRegionList *ml, *ml2;
3104 AddressSpace *as;
3105
3106 if (flatview) {
3107 FlatView *view;
3108 struct FlatViewInfo fvi = {
3109 .counter = 0,
3110 .dispatch_tree = dispatch_tree,
3111 .owner = owner,
3112 };
3113 GArray *fv_address_spaces;
3114 GHashTable *views = g_hash_table_new(g_direct_hash, g_direct_equal);
3115 AccelClass *ac = ACCEL_GET_CLASS(current_machine->accelerator);
3116
3117 if (ac->has_memory) {
3118 fvi.ac = ac;
3119 fvi.ac_name = current_machine->accel ? current_machine->accel :
3120 object_class_get_name(OBJECT_CLASS(ac));
3121 }
3122
3123 /* Gather all FVs in one table */
3124 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
3125 view = address_space_get_flatview(as);
3126
3127 fv_address_spaces = g_hash_table_lookup(views, view);
3128 if (!fv_address_spaces) {
3129 fv_address_spaces = g_array_new(false, false, sizeof(as));
3130 g_hash_table_insert(views, view, fv_address_spaces);
3131 }
3132
3133 g_array_append_val(fv_address_spaces, as);
3134 }
3135
3136 /* Print */
3137 g_hash_table_foreach(views, mtree_print_flatview, &fvi);
3138
3139 /* Free */
3140 g_hash_table_foreach_remove(views, mtree_info_flatview_free, 0);
3141 g_hash_table_unref(views);
3142
3143 return;
3144 }
3145
3146 QTAILQ_INIT(&ml_head);
3147
3148 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
3149 qemu_printf("address-space: %s\n", as->name);
3150 mtree_print_mr(as->root, 1, 0, &ml_head, owner);
3151 qemu_printf("\n");
3152 }
3153
3154 /* print aliased regions */
3155 QTAILQ_FOREACH(ml, &ml_head, mrqueue) {
3156 qemu_printf("memory-region: %s\n", memory_region_name(ml->mr));
3157 mtree_print_mr(ml->mr, 1, 0, &ml_head, owner);
3158 qemu_printf("\n");
3159 }
3160
3161 QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) {
3162 g_free(ml);
3163 }
3164 }
3165
3166 void memory_region_init_ram(MemoryRegion *mr,
3167 struct Object *owner,
3168 const char *name,
3169 uint64_t size,
3170 Error **errp)
3171 {
3172 DeviceState *owner_dev;
3173 Error *err = NULL;
3174
3175 memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
3176 if (err) {
3177 error_propagate(errp, err);
3178 return;
3179 }
3180 /* This will assert if owner is neither NULL nor a DeviceState.
3181 * We only want the owner here for the purposes of defining a
3182 * unique name for migration. TODO: Ideally we should implement
3183 * a naming scheme for Objects which are not DeviceStates, in
3184 * which case we can relax this restriction.
3185 */
3186 owner_dev = DEVICE(owner);
3187 vmstate_register_ram(mr, owner_dev);
3188 }
3189
3190 void memory_region_init_rom(MemoryRegion *mr,
3191 struct Object *owner,
3192 const char *name,
3193 uint64_t size,
3194 Error **errp)
3195 {
3196 DeviceState *owner_dev;
3197 Error *err = NULL;
3198
3199 memory_region_init_rom_nomigrate(mr, owner, name, size, &err);
3200 if (err) {
3201 error_propagate(errp, err);
3202 return;
3203 }
3204 /* This will assert if owner is neither NULL nor a DeviceState.
3205 * We only want the owner here for the purposes of defining a
3206 * unique name for migration. TODO: Ideally we should implement
3207 * a naming scheme for Objects which are not DeviceStates, in
3208 * which case we can relax this restriction.
3209 */
3210 owner_dev = DEVICE(owner);
3211 vmstate_register_ram(mr, owner_dev);
3212 }
3213
3214 void memory_region_init_rom_device(MemoryRegion *mr,
3215 struct Object *owner,
3216 const MemoryRegionOps *ops,
3217 void *opaque,
3218 const char *name,
3219 uint64_t size,
3220 Error **errp)
3221 {
3222 DeviceState *owner_dev;
3223 Error *err = NULL;
3224
3225 memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque,
3226 name, size, &err);
3227 if (err) {
3228 error_propagate(errp, err);
3229 return;
3230 }
3231 /* This will assert if owner is neither NULL nor a DeviceState.
3232 * We only want the owner here for the purposes of defining a
3233 * unique name for migration. TODO: Ideally we should implement
3234 * a naming scheme for Objects which are not DeviceStates, in
3235 * which case we can relax this restriction.
3236 */
3237 owner_dev = DEVICE(owner);
3238 vmstate_register_ram(mr, owner_dev);
3239 }
3240
3241 static const TypeInfo memory_region_info = {
3242 .parent = TYPE_OBJECT,
3243 .name = TYPE_MEMORY_REGION,
3244 .class_size = sizeof(MemoryRegionClass),
3245 .instance_size = sizeof(MemoryRegion),
3246 .instance_init = memory_region_initfn,
3247 .instance_finalize = memory_region_finalize,
3248 };
3249
3250 static const TypeInfo iommu_memory_region_info = {
3251 .parent = TYPE_MEMORY_REGION,
3252 .name = TYPE_IOMMU_MEMORY_REGION,
3253 .class_size = sizeof(IOMMUMemoryRegionClass),
3254 .instance_size = sizeof(IOMMUMemoryRegion),
3255 .instance_init = iommu_memory_region_initfn,
3256 .abstract = true,
3257 };
3258
3259 static void memory_register_types(void)
3260 {
3261 type_register_static(&memory_region_info);
3262 type_register_static(&iommu_memory_region_info);
3263 }
3264
3265 type_init(memory_register_types)
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