target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "qemu-common.h"
  23 #if !defined(CONFIG_USER_ONLY)
  24 #include "hw/loader.h"
  25 #endif
  26 #include "sysemu/sysemu.h"
  27
  28 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  29 {
  30     ARMCPU *cpu = ARM_CPU(cs);
  31
  32     cpu->env.regs[15] = value;
  33 }
  34
  35 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  36 {
  37     /* Reset a single ARMCPRegInfo register */
  38     ARMCPRegInfo *ri = value;
  39     ARMCPU *cpu = opaque;
  40
  41     if (ri->type & ARM_CP_SPECIAL) {
  42         return;
  43     }
  44
  45     if (ri->resetfn) {
  46         ri->resetfn(&cpu->env, ri);
  47         return;
  48     }
  49
  50     /* A zero offset is never possible as it would be regs[0]
  51      * so we use it to indicate that reset is being handled elsewhere.
  52      * This is basically only used for fields in non-core coprocessors
  53      * (like the pxa2xx ones).
  54      */
  55     if (!ri->fieldoffset) {
  56         return;
  57     }
  58
  59     if (ri->type & ARM_CP_64BIT) {
  60         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  61     } else {
  62         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  63     }
  64 }
  65
  66 /* CPUClass::reset() */
  67 static void arm_cpu_reset(CPUState *s)
  68 {
  69     ARMCPU *cpu = ARM_CPU(s);
  70     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
  71     CPUARMState *env = &cpu->env;
  72
  73     acc->parent_reset(s);
  74
  75     memset(env, 0, offsetof(CPUARMState, breakpoints));
  76     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
  77     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
  78     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
  79     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
  80
  81     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  82         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
  83     }
  84
  85 #if defined(CONFIG_USER_ONLY)
  86     env->uncached_cpsr = ARM_CPU_MODE_USR;
  87     /* For user mode we must enable access to coprocessors */
  88     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
  89     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  90         env->cp15.c15_cpar = 3;
  91     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
  92         env->cp15.c15_cpar = 1;
  93     }
  94 #else
  95     /* SVC mode with interrupts disabled.  */
  96     env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
  97     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
  98        clear at reset.  Initial SP and PC are loaded from ROM.  */
  99     if (IS_M(env)) {
 100         uint32_t pc;
 101         uint8_t *rom;
 102         env->uncached_cpsr &= ~CPSR_I;
 103         rom = rom_ptr(0);
 104         if (rom) {
 105             /* We should really use ldl_phys here, in case the guest
 106                modified flash and reset itself.  However images
 107                loaded via -kernel have not been copied yet, so load the
 108                values directly from there.  */
 109             env->regs[13] = ldl_p(rom);
 110             pc = ldl_p(rom + 4);
 111             env->thumb = pc & 1;
 112             env->regs[15] = pc & ~1;
 113         }
 114     }
 115     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 116 #endif
 117     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 118     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 119     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 120     set_float_detect_tininess(float_tininess_before_rounding,
 121                               &env->vfp.fp_status);
 122     set_float_detect_tininess(float_tininess_before_rounding,
 123                               &env->vfp.standard_fp_status);
 124     tlb_flush(env, 1);
 125     /* Reset is a state change for some CPUARMState fields which we
 126      * bake assumptions about into translated code, so we need to
 127      * tb_flush().
 128      */
 129     tb_flush(env);
 130 }
 131
 132 static inline void set_feature(CPUARMState *env, int feature)
 133 {
 134     env->features |= 1ULL << feature;
 135 }
 136
 137 static void arm_cpu_initfn(Object *obj)
 138 {
 139     CPUState *cs = CPU(obj);
 140     ARMCPU *cpu = ARM_CPU(obj);
 141     static bool inited;
 142
 143     cs->env_ptr = &cpu->env;
 144     cpu_exec_init(&cpu->env);
 145     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 146                                          g_free, g_free);
 147
 148     if (tcg_enabled() && !inited) {
 149         inited = true;
 150         arm_translate_init();
 151     }
 152 }
 153
 154 static void arm_cpu_finalizefn(Object *obj)
 155 {
 156     ARMCPU *cpu = ARM_CPU(obj);
 157     g_hash_table_destroy(cpu->cp_regs);
 158 }
 159
 160 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 161 {
 162     ARMCPU *cpu = ARM_CPU(dev);
 163     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 164     CPUARMState *env = &cpu->env;
 165
 166     /* Some features automatically imply others: */
 167     if (arm_feature(env, ARM_FEATURE_V8)) {
 168         set_feature(env, ARM_FEATURE_V7);
 169         set_feature(env, ARM_FEATURE_ARM_DIV);
 170         set_feature(env, ARM_FEATURE_LPAE);
 171     }
 172     if (arm_feature(env, ARM_FEATURE_V7)) {
 173         set_feature(env, ARM_FEATURE_VAPA);
 174         set_feature(env, ARM_FEATURE_THUMB2);
 175         set_feature(env, ARM_FEATURE_MPIDR);
 176         if (!arm_feature(env, ARM_FEATURE_M)) {
 177             set_feature(env, ARM_FEATURE_V6K);
 178         } else {
 179             set_feature(env, ARM_FEATURE_V6);
 180         }
 181     }
 182     if (arm_feature(env, ARM_FEATURE_V6K)) {
 183         set_feature(env, ARM_FEATURE_V6);
 184         set_feature(env, ARM_FEATURE_MVFR);
 185     }
 186     if (arm_feature(env, ARM_FEATURE_V6)) {
 187         set_feature(env, ARM_FEATURE_V5);
 188         if (!arm_feature(env, ARM_FEATURE_M)) {
 189             set_feature(env, ARM_FEATURE_AUXCR);
 190         }
 191     }
 192     if (arm_feature(env, ARM_FEATURE_V5)) {
 193         set_feature(env, ARM_FEATURE_V4T);
 194     }
 195     if (arm_feature(env, ARM_FEATURE_M)) {
 196         set_feature(env, ARM_FEATURE_THUMB_DIV);
 197     }
 198     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 199         set_feature(env, ARM_FEATURE_THUMB_DIV);
 200     }
 201     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 202         set_feature(env, ARM_FEATURE_VFP3);
 203     }
 204     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 205         set_feature(env, ARM_FEATURE_VFP);
 206     }
 207     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 208         set_feature(env, ARM_FEATURE_V7MP);
 209         set_feature(env, ARM_FEATURE_PXN);
 210     }
 211
 212     register_cp_regs_for_features(cpu);
 213     arm_cpu_register_gdb_regs_for_features(cpu);
 214
 215     init_cpreg_list(cpu);
 216
 217     cpu_reset(CPU(cpu));
 218
 219     acc->parent_realize(dev, errp);
 220 }
 221
 222 /* CPU models */
 223
 224 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 225 {
 226     ObjectClass *oc;
 227     char *typename;
 228
 229     if (!cpu_model) {
 230         return NULL;
 231     }
 232
 233     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model);
 234     oc = object_class_by_name(typename);
 235     g_free(typename);
 236     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 237         object_class_is_abstract(oc)) {
 238         return NULL;
 239     }
 240     return oc;
 241 }
 242
 243 static void arm926_initfn(Object *obj)
 244 {
 245     ARMCPU *cpu = ARM_CPU(obj);
 246     set_feature(&cpu->env, ARM_FEATURE_V5);
 247     set_feature(&cpu->env, ARM_FEATURE_VFP);
 248     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 249     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 250     cpu->midr = 0x41069265;
 251     cpu->reset_fpsid = 0x41011090;
 252     cpu->ctr = 0x1dd20d2;
 253     cpu->reset_sctlr = 0x00090078;
 254 }
 255
 256 static void arm946_initfn(Object *obj)
 257 {
 258     ARMCPU *cpu = ARM_CPU(obj);
 259     set_feature(&cpu->env, ARM_FEATURE_V5);
 260     set_feature(&cpu->env, ARM_FEATURE_MPU);
 261     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 262     cpu->midr = 0x41059461;
 263     cpu->ctr = 0x0f004006;
 264     cpu->reset_sctlr = 0x00000078;
 265 }
 266
 267 static void arm1026_initfn(Object *obj)
 268 {
 269     ARMCPU *cpu = ARM_CPU(obj);
 270     set_feature(&cpu->env, ARM_FEATURE_V5);
 271     set_feature(&cpu->env, ARM_FEATURE_VFP);
 272     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 273     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 274     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 275     cpu->midr = 0x4106a262;
 276     cpu->reset_fpsid = 0x410110a0;
 277     cpu->ctr = 0x1dd20d2;
 278     cpu->reset_sctlr = 0x00090078;
 279     cpu->reset_auxcr = 1;
 280     {
 281         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 282         ARMCPRegInfo ifar = {
 283             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 284             .access = PL1_RW,
 285             .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
 286             .resetvalue = 0
 287         };
 288         define_one_arm_cp_reg(cpu, &ifar);
 289     }
 290 }
 291
 292 static void arm1136_r2_initfn(Object *obj)
 293 {
 294     ARMCPU *cpu = ARM_CPU(obj);
 295     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 296      * older core than plain "arm1136". In particular this does not
 297      * have the v6K features.
 298      * These ID register values are correct for 1136 but may be wrong
 299      * for 1136_r2 (in particular r0p2 does not actually implement most
 300      * of the ID registers).
 301      */
 302     set_feature(&cpu->env, ARM_FEATURE_V6);
 303     set_feature(&cpu->env, ARM_FEATURE_VFP);
 304     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 305     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 306     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 307     cpu->midr = 0x4107b362;
 308     cpu->reset_fpsid = 0x410120b4;
 309     cpu->mvfr0 = 0x11111111;
 310     cpu->mvfr1 = 0x00000000;
 311     cpu->ctr = 0x1dd20d2;
 312     cpu->reset_sctlr = 0x00050078;
 313     cpu->id_pfr0 = 0x111;
 314     cpu->id_pfr1 = 0x1;
 315     cpu->id_dfr0 = 0x2;
 316     cpu->id_afr0 = 0x3;
 317     cpu->id_mmfr0 = 0x01130003;
 318     cpu->id_mmfr1 = 0x10030302;
 319     cpu->id_mmfr2 = 0x01222110;
 320     cpu->id_isar0 = 0x00140011;
 321     cpu->id_isar1 = 0x12002111;
 322     cpu->id_isar2 = 0x11231111;
 323     cpu->id_isar3 = 0x01102131;
 324     cpu->id_isar4 = 0x141;
 325     cpu->reset_auxcr = 7;
 326 }
 327
 328 static void arm1136_initfn(Object *obj)
 329 {
 330     ARMCPU *cpu = ARM_CPU(obj);
 331     set_feature(&cpu->env, ARM_FEATURE_V6K);
 332     set_feature(&cpu->env, ARM_FEATURE_V6);
 333     set_feature(&cpu->env, ARM_FEATURE_VFP);
 334     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 335     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 336     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 337     cpu->midr = 0x4117b363;
 338     cpu->reset_fpsid = 0x410120b4;
 339     cpu->mvfr0 = 0x11111111;
 340     cpu->mvfr1 = 0x00000000;
 341     cpu->ctr = 0x1dd20d2;
 342     cpu->reset_sctlr = 0x00050078;
 343     cpu->id_pfr0 = 0x111;
 344     cpu->id_pfr1 = 0x1;
 345     cpu->id_dfr0 = 0x2;
 346     cpu->id_afr0 = 0x3;
 347     cpu->id_mmfr0 = 0x01130003;
 348     cpu->id_mmfr1 = 0x10030302;
 349     cpu->id_mmfr2 = 0x01222110;
 350     cpu->id_isar0 = 0x00140011;
 351     cpu->id_isar1 = 0x12002111;
 352     cpu->id_isar2 = 0x11231111;
 353     cpu->id_isar3 = 0x01102131;
 354     cpu->id_isar4 = 0x141;
 355     cpu->reset_auxcr = 7;
 356 }
 357
 358 static void arm1176_initfn(Object *obj)
 359 {
 360     ARMCPU *cpu = ARM_CPU(obj);
 361     set_feature(&cpu->env, ARM_FEATURE_V6K);
 362     set_feature(&cpu->env, ARM_FEATURE_VFP);
 363     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 364     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 365     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 366     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 367     cpu->midr = 0x410fb767;
 368     cpu->reset_fpsid = 0x410120b5;
 369     cpu->mvfr0 = 0x11111111;
 370     cpu->mvfr1 = 0x00000000;
 371     cpu->ctr = 0x1dd20d2;
 372     cpu->reset_sctlr = 0x00050078;
 373     cpu->id_pfr0 = 0x111;
 374     cpu->id_pfr1 = 0x11;
 375     cpu->id_dfr0 = 0x33;
 376     cpu->id_afr0 = 0;
 377     cpu->id_mmfr0 = 0x01130003;
 378     cpu->id_mmfr1 = 0x10030302;
 379     cpu->id_mmfr2 = 0x01222100;
 380     cpu->id_isar0 = 0x0140011;
 381     cpu->id_isar1 = 0x12002111;
 382     cpu->id_isar2 = 0x11231121;
 383     cpu->id_isar3 = 0x01102131;
 384     cpu->id_isar4 = 0x01141;
 385     cpu->reset_auxcr = 7;
 386 }
 387
 388 static void arm11mpcore_initfn(Object *obj)
 389 {
 390     ARMCPU *cpu = ARM_CPU(obj);
 391     set_feature(&cpu->env, ARM_FEATURE_V6K);
 392     set_feature(&cpu->env, ARM_FEATURE_VFP);
 393     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 394     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 395     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 396     cpu->midr = 0x410fb022;
 397     cpu->reset_fpsid = 0x410120b4;
 398     cpu->mvfr0 = 0x11111111;
 399     cpu->mvfr1 = 0x00000000;
 400     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 401     cpu->id_pfr0 = 0x111;
 402     cpu->id_pfr1 = 0x1;
 403     cpu->id_dfr0 = 0;
 404     cpu->id_afr0 = 0x2;
 405     cpu->id_mmfr0 = 0x01100103;
 406     cpu->id_mmfr1 = 0x10020302;
 407     cpu->id_mmfr2 = 0x01222000;
 408     cpu->id_isar0 = 0x00100011;
 409     cpu->id_isar1 = 0x12002111;
 410     cpu->id_isar2 = 0x11221011;
 411     cpu->id_isar3 = 0x01102131;
 412     cpu->id_isar4 = 0x141;
 413     cpu->reset_auxcr = 1;
 414 }
 415
 416 static void cortex_m3_initfn(Object *obj)
 417 {
 418     ARMCPU *cpu = ARM_CPU(obj);
 419     set_feature(&cpu->env, ARM_FEATURE_V7);
 420     set_feature(&cpu->env, ARM_FEATURE_M);
 421     cpu->midr = 0x410fc231;
 422 }
 423
 424 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 425 {
 426 #ifndef CONFIG_USER_ONLY
 427     CPUClass *cc = CPU_CLASS(oc);
 428
 429     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
 430 #endif
 431 }
 432
 433 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 434     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 435       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 436     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 437       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 438     REGINFO_SENTINEL
 439 };
 440
 441 static void cortex_a8_initfn(Object *obj)
 442 {
 443     ARMCPU *cpu = ARM_CPU(obj);
 444     set_feature(&cpu->env, ARM_FEATURE_V7);
 445     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 446     set_feature(&cpu->env, ARM_FEATURE_NEON);
 447     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 448     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 449     cpu->midr = 0x410fc080;
 450     cpu->reset_fpsid = 0x410330c0;
 451     cpu->mvfr0 = 0x11110222;
 452     cpu->mvfr1 = 0x00011100;
 453     cpu->ctr = 0x82048004;
 454     cpu->reset_sctlr = 0x00c50078;
 455     cpu->id_pfr0 = 0x1031;
 456     cpu->id_pfr1 = 0x11;
 457     cpu->id_dfr0 = 0x400;
 458     cpu->id_afr0 = 0;
 459     cpu->id_mmfr0 = 0x31100003;
 460     cpu->id_mmfr1 = 0x20000000;
 461     cpu->id_mmfr2 = 0x01202000;
 462     cpu->id_mmfr3 = 0x11;
 463     cpu->id_isar0 = 0x00101111;
 464     cpu->id_isar1 = 0x12112111;
 465     cpu->id_isar2 = 0x21232031;
 466     cpu->id_isar3 = 0x11112131;
 467     cpu->id_isar4 = 0x00111142;
 468     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 469     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 470     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 471     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 472     cpu->reset_auxcr = 2;
 473     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
 474 }
 475
 476 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
 477     /* power_control should be set to maximum latency. Again,
 478      * default to 0 and set by private hook
 479      */
 480     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
 481       .access = PL1_RW, .resetvalue = 0,
 482       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
 483     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
 484       .access = PL1_RW, .resetvalue = 0,
 485       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
 486     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
 487       .access = PL1_RW, .resetvalue = 0,
 488       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
 489     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
 490       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 491     /* TLB lockdown control */
 492     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
 493       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 494     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
 495       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 496     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
 497       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 498     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
 499       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 500     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
 501       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 502     REGINFO_SENTINEL
 503 };
 504
 505 static void cortex_a9_initfn(Object *obj)
 506 {
 507     ARMCPU *cpu = ARM_CPU(obj);
 508     set_feature(&cpu->env, ARM_FEATURE_V7);
 509     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 510     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 511     set_feature(&cpu->env, ARM_FEATURE_NEON);
 512     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 513     /* Note that A9 supports the MP extensions even for
 514      * A9UP and single-core A9MP (which are both different
 515      * and valid configurations; we don't model A9UP).
 516      */
 517     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 518     cpu->midr = 0x410fc090;
 519     cpu->reset_fpsid = 0x41033090;
 520     cpu->mvfr0 = 0x11110222;
 521     cpu->mvfr1 = 0x01111111;
 522     cpu->ctr = 0x80038003;
 523     cpu->reset_sctlr = 0x00c50078;
 524     cpu->id_pfr0 = 0x1031;
 525     cpu->id_pfr1 = 0x11;
 526     cpu->id_dfr0 = 0x000;
 527     cpu->id_afr0 = 0;
 528     cpu->id_mmfr0 = 0x00100103;
 529     cpu->id_mmfr1 = 0x20000000;
 530     cpu->id_mmfr2 = 0x01230000;
 531     cpu->id_mmfr3 = 0x00002111;
 532     cpu->id_isar0 = 0x00101111;
 533     cpu->id_isar1 = 0x13112111;
 534     cpu->id_isar2 = 0x21232041;
 535     cpu->id_isar3 = 0x11112131;
 536     cpu->id_isar4 = 0x00111142;
 537     cpu->clidr = (1 << 27) | (1 << 24) | 3;
 538     cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
 539     cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
 540     {
 541         ARMCPRegInfo cbar = {
 542             .name = "CBAR", .cp = 15, .crn = 15,  .crm = 0, .opc1 = 4,
 543             .opc2 = 0, .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
 544             .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address)
 545         };
 546         define_one_arm_cp_reg(cpu, &cbar);
 547         define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 548     }
 549 }
 550
 551 #ifndef CONFIG_USER_ONLY
 552 static int a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri,
 553                            uint64_t *value)
 554 {
 555     /* Linux wants the number of processors from here.
 556      * Might as well set the interrupt-controller bit too.
 557      */
 558     *value = ((smp_cpus - 1) << 24) | (1 << 23);
 559     return 0;
 560 }
 561 #endif
 562
 563 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
 564 #ifndef CONFIG_USER_ONLY
 565     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 566       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
 567       .writefn = arm_cp_write_ignore, },
 568 #endif
 569     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
 570       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 571     REGINFO_SENTINEL
 572 };
 573
 574 static void cortex_a15_initfn(Object *obj)
 575 {
 576     ARMCPU *cpu = ARM_CPU(obj);
 577     set_feature(&cpu->env, ARM_FEATURE_V7);
 578     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 579     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 580     set_feature(&cpu->env, ARM_FEATURE_NEON);
 581     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 582     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 583     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 584     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 585     set_feature(&cpu->env, ARM_FEATURE_LPAE);
 586     cpu->midr = 0x412fc0f1;
 587     cpu->reset_fpsid = 0x410430f0;
 588     cpu->mvfr0 = 0x10110222;
 589     cpu->mvfr1 = 0x11111111;
 590     cpu->ctr = 0x8444c004;
 591     cpu->reset_sctlr = 0x00c50078;
 592     cpu->id_pfr0 = 0x00001131;
 593     cpu->id_pfr1 = 0x00011011;
 594     cpu->id_dfr0 = 0x02010555;
 595     cpu->id_afr0 = 0x00000000;
 596     cpu->id_mmfr0 = 0x10201105;
 597     cpu->id_mmfr1 = 0x20000000;
 598     cpu->id_mmfr2 = 0x01240000;
 599     cpu->id_mmfr3 = 0x02102211;
 600     cpu->id_isar0 = 0x02101110;
 601     cpu->id_isar1 = 0x13112111;
 602     cpu->id_isar2 = 0x21232041;
 603     cpu->id_isar3 = 0x11112131;
 604     cpu->id_isar4 = 0x10011142;
 605     cpu->clidr = 0x0a200023;
 606     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 607     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 608     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 609     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
 610 }
 611
 612 static void ti925t_initfn(Object *obj)
 613 {
 614     ARMCPU *cpu = ARM_CPU(obj);
 615     set_feature(&cpu->env, ARM_FEATURE_V4T);
 616     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
 617     cpu->midr = ARM_CPUID_TI925T;
 618     cpu->ctr = 0x5109149;
 619     cpu->reset_sctlr = 0x00000070;
 620 }
 621
 622 static void sa1100_initfn(Object *obj)
 623 {
 624     ARMCPU *cpu = ARM_CPU(obj);
 625     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 626     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 627     cpu->midr = 0x4401A11B;
 628     cpu->reset_sctlr = 0x00000070;
 629 }
 630
 631 static void sa1110_initfn(Object *obj)
 632 {
 633     ARMCPU *cpu = ARM_CPU(obj);
 634     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 635     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 636     cpu->midr = 0x6901B119;
 637     cpu->reset_sctlr = 0x00000070;
 638 }
 639
 640 static void pxa250_initfn(Object *obj)
 641 {
 642     ARMCPU *cpu = ARM_CPU(obj);
 643     set_feature(&cpu->env, ARM_FEATURE_V5);
 644     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 645     cpu->midr = 0x69052100;
 646     cpu->ctr = 0xd172172;
 647     cpu->reset_sctlr = 0x00000078;
 648 }
 649
 650 static void pxa255_initfn(Object *obj)
 651 {
 652     ARMCPU *cpu = ARM_CPU(obj);
 653     set_feature(&cpu->env, ARM_FEATURE_V5);
 654     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 655     cpu->midr = 0x69052d00;
 656     cpu->ctr = 0xd172172;
 657     cpu->reset_sctlr = 0x00000078;
 658 }
 659
 660 static void pxa260_initfn(Object *obj)
 661 {
 662     ARMCPU *cpu = ARM_CPU(obj);
 663     set_feature(&cpu->env, ARM_FEATURE_V5);
 664     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 665     cpu->midr = 0x69052903;
 666     cpu->ctr = 0xd172172;
 667     cpu->reset_sctlr = 0x00000078;
 668 }
 669
 670 static void pxa261_initfn(Object *obj)
 671 {
 672     ARMCPU *cpu = ARM_CPU(obj);
 673     set_feature(&cpu->env, ARM_FEATURE_V5);
 674     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 675     cpu->midr = 0x69052d05;
 676     cpu->ctr = 0xd172172;
 677     cpu->reset_sctlr = 0x00000078;
 678 }
 679
 680 static void pxa262_initfn(Object *obj)
 681 {
 682     ARMCPU *cpu = ARM_CPU(obj);
 683     set_feature(&cpu->env, ARM_FEATURE_V5);
 684     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 685     cpu->midr = 0x69052d06;
 686     cpu->ctr = 0xd172172;
 687     cpu->reset_sctlr = 0x00000078;
 688 }
 689
 690 static void pxa270a0_initfn(Object *obj)
 691 {
 692     ARMCPU *cpu = ARM_CPU(obj);
 693     set_feature(&cpu->env, ARM_FEATURE_V5);
 694     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 695     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 696     cpu->midr = 0x69054110;
 697     cpu->ctr = 0xd172172;
 698     cpu->reset_sctlr = 0x00000078;
 699 }
 700
 701 static void pxa270a1_initfn(Object *obj)
 702 {
 703     ARMCPU *cpu = ARM_CPU(obj);
 704     set_feature(&cpu->env, ARM_FEATURE_V5);
 705     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 706     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 707     cpu->midr = 0x69054111;
 708     cpu->ctr = 0xd172172;
 709     cpu->reset_sctlr = 0x00000078;
 710 }
 711
 712 static void pxa270b0_initfn(Object *obj)
 713 {
 714     ARMCPU *cpu = ARM_CPU(obj);
 715     set_feature(&cpu->env, ARM_FEATURE_V5);
 716     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 717     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 718     cpu->midr = 0x69054112;
 719     cpu->ctr = 0xd172172;
 720     cpu->reset_sctlr = 0x00000078;
 721 }
 722
 723 static void pxa270b1_initfn(Object *obj)
 724 {
 725     ARMCPU *cpu = ARM_CPU(obj);
 726     set_feature(&cpu->env, ARM_FEATURE_V5);
 727     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 728     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 729     cpu->midr = 0x69054113;
 730     cpu->ctr = 0xd172172;
 731     cpu->reset_sctlr = 0x00000078;
 732 }
 733
 734 static void pxa270c0_initfn(Object *obj)
 735 {
 736     ARMCPU *cpu = ARM_CPU(obj);
 737     set_feature(&cpu->env, ARM_FEATURE_V5);
 738     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 739     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 740     cpu->midr = 0x69054114;
 741     cpu->ctr = 0xd172172;
 742     cpu->reset_sctlr = 0x00000078;
 743 }
 744
 745 static void pxa270c5_initfn(Object *obj)
 746 {
 747     ARMCPU *cpu = ARM_CPU(obj);
 748     set_feature(&cpu->env, ARM_FEATURE_V5);
 749     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 750     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 751     cpu->midr = 0x69054117;
 752     cpu->ctr = 0xd172172;
 753     cpu->reset_sctlr = 0x00000078;
 754 }
 755
 756 static void arm_any_initfn(Object *obj)
 757 {
 758     ARMCPU *cpu = ARM_CPU(obj);
 759     set_feature(&cpu->env, ARM_FEATURE_V8);
 760     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 761     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 762     set_feature(&cpu->env, ARM_FEATURE_NEON);
 763     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 764     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 765     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 766     cpu->midr = 0xffffffff;
 767 }
 768
 769 typedef struct ARMCPUInfo {
 770     const char *name;
 771     void (*initfn)(Object *obj);
 772     void (*class_init)(ObjectClass *oc, void *data);
 773 } ARMCPUInfo;
 774
 775 static const ARMCPUInfo arm_cpus[] = {
 776     { .name = "arm926",      .initfn = arm926_initfn },
 777     { .name = "arm946",      .initfn = arm946_initfn },
 778     { .name = "arm1026",     .initfn = arm1026_initfn },
 779     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
 780      * older core than plain "arm1136". In particular this does not
 781      * have the v6K features.
 782      */
 783     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
 784     { .name = "arm1136",     .initfn = arm1136_initfn },
 785     { .name = "arm1176",     .initfn = arm1176_initfn },
 786     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
 787     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
 788                              .class_init = arm_v7m_class_init },
 789     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
 790     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
 791     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
 792     { .name = "ti925t",      .initfn = ti925t_initfn },
 793     { .name = "sa1100",      .initfn = sa1100_initfn },
 794     { .name = "sa1110",      .initfn = sa1110_initfn },
 795     { .name = "pxa250",      .initfn = pxa250_initfn },
 796     { .name = "pxa255",      .initfn = pxa255_initfn },
 797     { .name = "pxa260",      .initfn = pxa260_initfn },
 798     { .name = "pxa261",      .initfn = pxa261_initfn },
 799     { .name = "pxa262",      .initfn = pxa262_initfn },
 800     /* "pxa270" is an alias for "pxa270-a0" */
 801     { .name = "pxa270",      .initfn = pxa270a0_initfn },
 802     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
 803     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
 804     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
 805     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
 806     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
 807     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
 808     { .name = "any",         .initfn = arm_any_initfn },
 809 };
 810
 811 static void arm_cpu_class_init(ObjectClass *oc, void *data)
 812 {
 813     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
 814     CPUClass *cc = CPU_CLASS(acc);
 815     DeviceClass *dc = DEVICE_CLASS(oc);
 816
 817     acc->parent_realize = dc->realize;
 818     dc->realize = arm_cpu_realizefn;
 819
 820     acc->parent_reset = cc->reset;
 821     cc->reset = arm_cpu_reset;
 822
 823     cc->class_by_name = arm_cpu_class_by_name;
 824     cc->do_interrupt = arm_cpu_do_interrupt;
 825     cc->dump_state = arm_cpu_dump_state;
 826     cc->set_pc = arm_cpu_set_pc;
 827 #ifndef CONFIG_USER_ONLY
 828     cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
 829     cc->vmsd = &vmstate_arm_cpu;
 830 #endif
 831 }
 832
 833 static void cpu_register(const ARMCPUInfo *info)
 834 {
 835     TypeInfo type_info = {
 836         .parent = TYPE_ARM_CPU,
 837         .instance_size = sizeof(ARMCPU),
 838         .instance_init = info->initfn,
 839         .class_size = sizeof(ARMCPUClass),
 840         .class_init = info->class_init,
 841     };
 842
 843     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
 844     type_register(&type_info);
 845     g_free((void *)type_info.name);
 846 }
 847
 848 static const TypeInfo arm_cpu_type_info = {
 849     .name = TYPE_ARM_CPU,
 850     .parent = TYPE_CPU,
 851     .instance_size = sizeof(ARMCPU),
 852     .instance_init = arm_cpu_initfn,
 853     .instance_finalize = arm_cpu_finalizefn,
 854     .abstract = true,
 855     .class_size = sizeof(ARMCPUClass),
 856     .class_init = arm_cpu_class_init,
 857 };
 858
 859 static void arm_cpu_register_types(void)
 860 {
 861     int i;
 862
 863     type_register_static(&arm_cpu_type_info);
 864     for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) {
 865         cpu_register(&arm_cpus[i]);
 866     }
 867 }
 868
 869 type_init(arm_cpu_register_types)