target-mips/helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdarg.h>
  20 #include <stdlib.h>
  21 #include <stdio.h>
  22 #include <string.h>
  23 #include <inttypes.h>
  24 #include <signal.h>
  25
  26 #include "cpu.h"
  27 #include "sysemu/kvm.h"
  28 #include "exec/cpu_ldst.h"
  29
  30 enum {
  31     TLBRET_XI = -6,
  32     TLBRET_RI = -5,
  33     TLBRET_DIRTY = -4,
  34     TLBRET_INVALID = -3,
  35     TLBRET_NOMATCH = -2,
  36     TLBRET_BADADDR = -1,
  37     TLBRET_MATCH = 0
  38 };
  39
  40 #if !defined(CONFIG_USER_ONLY)
  41
  42 /* no MMU emulation */
  43 int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
  44                         target_ulong address, int rw, int access_type)
  45 {
  46     *physical = address;
  47     *prot = PAGE_READ | PAGE_WRITE;
  48     return TLBRET_MATCH;
  49 }
  50
  51 /* fixed mapping MMU emulation */
  52 int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
  53                            target_ulong address, int rw, int access_type)
  54 {
  55     if (address <= (int32_t)0x7FFFFFFFUL) {
  56         if (!(env->CP0_Status & (1 << CP0St_ERL)))
  57             *physical = address + 0x40000000UL;
  58         else
  59             *physical = address;
  60     } else if (address <= (int32_t)0xBFFFFFFFUL)
  61         *physical = address & 0x1FFFFFFF;
  62     else
  63         *physical = address;
  64
  65     *prot = PAGE_READ | PAGE_WRITE;
  66     return TLBRET_MATCH;
  67 }
  68
  69 /* MIPS32/MIPS64 R4000-style MMU emulation */
  70 int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
  71                      target_ulong address, int rw, int access_type)
  72 {
  73     uint8_t ASID = env->CP0_EntryHi & 0xFF;
  74     int i;
  75
  76     for (i = 0; i < env->tlb->tlb_in_use; i++) {
  77         r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
  78         /* 1k pages are not supported. */
  79         target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
  80         target_ulong tag = address & ~mask;
  81         target_ulong VPN = tlb->VPN & ~mask;
  82 #if defined(TARGET_MIPS64)
  83         tag &= env->SEGMask;
  84 #endif
  85
  86         /* Check ASID, virtual page number & size */
  87         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
  88             /* TLB match */
  89             int n = !!(address & mask & ~(mask >> 1));
  90             /* Check access rights */
  91             if (!(n ? tlb->V1 : tlb->V0)) {
  92                 return TLBRET_INVALID;
  93             }
  94             if (rw == MMU_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) {
  95                 return TLBRET_XI;
  96             }
  97             if (rw == MMU_DATA_LOAD && (n ? tlb->RI1 : tlb->RI0)) {
  98                 return TLBRET_RI;
  99             }
 100             if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {
 101                 *physical = tlb->PFN[n] | (address & (mask >> 1));
 102                 *prot = PAGE_READ;
 103                 if (n ? tlb->D1 : tlb->D0)
 104                     *prot |= PAGE_WRITE;
 105                 return TLBRET_MATCH;
 106             }
 107             return TLBRET_DIRTY;
 108         }
 109     }
 110     return TLBRET_NOMATCH;
 111 }
 112
 113 static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
 114                                 int *prot, target_ulong real_address,
 115                                 int rw, int access_type)
 116 {
 117     /* User mode can only access useg/xuseg */
 118     int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
 119     int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM;
 120     int kernel_mode = !user_mode && !supervisor_mode;
 121 #if defined(TARGET_MIPS64)
 122     int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 123     int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 124     int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 125 #endif
 126     int ret = TLBRET_MATCH;
 127     /* effective address (modified for KVM T&E kernel segments) */
 128     target_ulong address = real_address;
 129
 130 #define USEG_LIMIT      0x7FFFFFFFUL
 131 #define KSEG0_BASE      0x80000000UL
 132 #define KSEG1_BASE      0xA0000000UL
 133 #define KSEG2_BASE      0xC0000000UL
 134 #define KSEG3_BASE      0xE0000000UL
 135
 136 #define KVM_KSEG0_BASE  0x40000000UL
 137 #define KVM_KSEG2_BASE  0x60000000UL
 138
 139     if (kvm_enabled()) {
 140         /* KVM T&E adds guest kernel segments in useg */
 141         if (real_address >= KVM_KSEG0_BASE) {
 142             if (real_address < KVM_KSEG2_BASE) {
 143                 /* kseg0 */
 144                 address += KSEG0_BASE - KVM_KSEG0_BASE;
 145             } else if (real_address <= USEG_LIMIT) {
 146                 /* kseg2/3 */
 147                 address += KSEG2_BASE - KVM_KSEG2_BASE;
 148             }
 149         }
 150     }
 151
 152     if (address <= USEG_LIMIT) {
 153         /* useg */
 154         if (env->CP0_Status & (1 << CP0St_ERL)) {
 155             *physical = address & 0xFFFFFFFF;
 156             *prot = PAGE_READ | PAGE_WRITE;
 157         } else {
 158             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 159         }
 160 #if defined(TARGET_MIPS64)
 161     } else if (address < 0x4000000000000000ULL) {
 162         /* xuseg */
 163         if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
 164             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 165         } else {
 166             ret = TLBRET_BADADDR;
 167         }
 168     } else if (address < 0x8000000000000000ULL) {
 169         /* xsseg */
 170         if ((supervisor_mode || kernel_mode) &&
 171             SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
 172             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 173         } else {
 174             ret = TLBRET_BADADDR;
 175         }
 176     } else if (address < 0xC000000000000000ULL) {
 177         /* xkphys */
 178         if (kernel_mode && KX &&
 179             (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
 180             *physical = address & env->PAMask;
 181             *prot = PAGE_READ | PAGE_WRITE;
 182         } else {
 183             ret = TLBRET_BADADDR;
 184         }
 185     } else if (address < 0xFFFFFFFF80000000ULL) {
 186         /* xkseg */
 187         if (kernel_mode && KX &&
 188             address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
 189             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 190         } else {
 191             ret = TLBRET_BADADDR;
 192         }
 193 #endif
 194     } else if (address < (int32_t)KSEG1_BASE) {
 195         /* kseg0 */
 196         if (kernel_mode) {
 197             *physical = address - (int32_t)KSEG0_BASE;
 198             *prot = PAGE_READ | PAGE_WRITE;
 199         } else {
 200             ret = TLBRET_BADADDR;
 201         }
 202     } else if (address < (int32_t)KSEG2_BASE) {
 203         /* kseg1 */
 204         if (kernel_mode) {
 205             *physical = address - (int32_t)KSEG1_BASE;
 206             *prot = PAGE_READ | PAGE_WRITE;
 207         } else {
 208             ret = TLBRET_BADADDR;
 209         }
 210     } else if (address < (int32_t)KSEG3_BASE) {
 211         /* sseg (kseg2) */
 212         if (supervisor_mode || kernel_mode) {
 213             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 214         } else {
 215             ret = TLBRET_BADADDR;
 216         }
 217     } else {
 218         /* kseg3 */
 219         /* XXX: debug segment is not emulated */
 220         if (kernel_mode) {
 221             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 222         } else {
 223             ret = TLBRET_BADADDR;
 224         }
 225     }
 226     return ret;
 227 }
 228 #endif
 229
 230 static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
 231                                 int rw, int tlb_error)
 232 {
 233     CPUState *cs = CPU(mips_env_get_cpu(env));
 234     int exception = 0, error_code = 0;
 235
 236     if (rw == MMU_INST_FETCH) {
 237         error_code |= EXCP_INST_NOTAVAIL;
 238     }
 239
 240     switch (tlb_error) {
 241     default:
 242     case TLBRET_BADADDR:
 243         /* Reference to kernel address from user mode or supervisor mode */
 244         /* Reference to supervisor address from user mode */
 245         if (rw == MMU_DATA_STORE) {
 246             exception = EXCP_AdES;
 247         } else {
 248             exception = EXCP_AdEL;
 249         }
 250         break;
 251     case TLBRET_NOMATCH:
 252         /* No TLB match for a mapped address */
 253         if (rw == MMU_DATA_STORE) {
 254             exception = EXCP_TLBS;
 255         } else {
 256             exception = EXCP_TLBL;
 257         }
 258         error_code |= EXCP_TLB_NOMATCH;
 259         break;
 260     case TLBRET_INVALID:
 261         /* TLB match with no valid bit */
 262         if (rw == MMU_DATA_STORE) {
 263             exception = EXCP_TLBS;
 264         } else {
 265             exception = EXCP_TLBL;
 266         }
 267         break;
 268     case TLBRET_DIRTY:
 269         /* TLB match but 'D' bit is cleared */
 270         exception = EXCP_LTLBL;
 271         break;
 272     case TLBRET_XI:
 273         /* Execute-Inhibit Exception */
 274         if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
 275             exception = EXCP_TLBXI;
 276         } else {
 277             exception = EXCP_TLBL;
 278         }
 279         break;
 280     case TLBRET_RI:
 281         /* Read-Inhibit Exception */
 282         if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
 283             exception = EXCP_TLBRI;
 284         } else {
 285             exception = EXCP_TLBL;
 286         }
 287         break;
 288     }
 289     /* Raise exception */
 290     env->CP0_BadVAddr = address;
 291     env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
 292                        ((address >> 9) & 0x007ffff0);
 293     env->CP0_EntryHi =
 294         (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
 295 #if defined(TARGET_MIPS64)
 296     env->CP0_EntryHi &= env->SEGMask;
 297     env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
 298                         ((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) |
 299                         ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9);
 300 #endif
 301     cs->exception_index = exception;
 302     env->error_code = error_code;
 303 }
 304
 305 #if !defined(CONFIG_USER_ONLY)
 306 hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 307 {
 308     MIPSCPU *cpu = MIPS_CPU(cs);
 309     hwaddr phys_addr;
 310     int prot;
 311
 312     if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0,
 313                              ACCESS_INT) != 0) {
 314         return -1;
 315     }
 316     return phys_addr;
 317 }
 318 #endif
 319
 320 int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
 321                               int mmu_idx)
 322 {
 323     MIPSCPU *cpu = MIPS_CPU(cs);
 324     CPUMIPSState *env = &cpu->env;
 325 #if !defined(CONFIG_USER_ONLY)
 326     hwaddr physical;
 327     int prot;
 328     int access_type;
 329 #endif
 330     int ret = 0;
 331
 332 #if 0
 333     log_cpu_state(cs, 0);
 334 #endif
 335     qemu_log_mask(CPU_LOG_MMU,
 336               "%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
 337               __func__, env->active_tc.PC, address, rw, mmu_idx);
 338
 339     /* data access */
 340 #if !defined(CONFIG_USER_ONLY)
 341     /* XXX: put correct access by using cpu_restore_state()
 342        correctly */
 343     access_type = ACCESS_INT;
 344     ret = get_physical_address(env, &physical, &prot,
 345                                address, rw, access_type);
 346     qemu_log_mask(CPU_LOG_MMU,
 347              "%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx
 348              " prot %d\n",
 349              __func__, address, ret, physical, prot);
 350     if (ret == TLBRET_MATCH) {
 351         tlb_set_page(cs, address & TARGET_PAGE_MASK,
 352                      physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
 353                      mmu_idx, TARGET_PAGE_SIZE);
 354         ret = 0;
 355     } else if (ret < 0)
 356 #endif
 357     {
 358         raise_mmu_exception(env, address, rw, ret);
 359         ret = 1;
 360     }
 361
 362     return ret;
 363 }
 364
 365 #if !defined(CONFIG_USER_ONLY)
 366 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw)
 367 {
 368     hwaddr physical;
 369     int prot;
 370     int access_type;
 371     int ret = 0;
 372
 373     /* data access */
 374     access_type = ACCESS_INT;
 375     ret = get_physical_address(env, &physical, &prot,
 376                                address, rw, access_type);
 377     if (ret != TLBRET_MATCH) {
 378         raise_mmu_exception(env, address, rw, ret);
 379         return -1LL;
 380     } else {
 381         return physical;
 382     }
 383 }
 384
 385 static const char * const excp_names[EXCP_LAST + 1] = {
 386     [EXCP_RESET] = "reset",
 387     [EXCP_SRESET] = "soft reset",
 388     [EXCP_DSS] = "debug single step",
 389     [EXCP_DINT] = "debug interrupt",
 390     [EXCP_NMI] = "non-maskable interrupt",
 391     [EXCP_MCHECK] = "machine check",
 392     [EXCP_EXT_INTERRUPT] = "interrupt",
 393     [EXCP_DFWATCH] = "deferred watchpoint",
 394     [EXCP_DIB] = "debug instruction breakpoint",
 395     [EXCP_IWATCH] = "instruction fetch watchpoint",
 396     [EXCP_AdEL] = "address error load",
 397     [EXCP_AdES] = "address error store",
 398     [EXCP_TLBF] = "TLB refill",
 399     [EXCP_IBE] = "instruction bus error",
 400     [EXCP_DBp] = "debug breakpoint",
 401     [EXCP_SYSCALL] = "syscall",
 402     [EXCP_BREAK] = "break",
 403     [EXCP_CpU] = "coprocessor unusable",
 404     [EXCP_RI] = "reserved instruction",
 405     [EXCP_OVERFLOW] = "arithmetic overflow",
 406     [EXCP_TRAP] = "trap",
 407     [EXCP_FPE] = "floating point",
 408     [EXCP_DDBS] = "debug data break store",
 409     [EXCP_DWATCH] = "data watchpoint",
 410     [EXCP_LTLBL] = "TLB modify",
 411     [EXCP_TLBL] = "TLB load",
 412     [EXCP_TLBS] = "TLB store",
 413     [EXCP_DBE] = "data bus error",
 414     [EXCP_DDBL] = "debug data break load",
 415     [EXCP_THREAD] = "thread",
 416     [EXCP_MDMX] = "MDMX",
 417     [EXCP_C2E] = "precise coprocessor 2",
 418     [EXCP_CACHE] = "cache error",
 419     [EXCP_TLBXI] = "TLB execute-inhibit",
 420     [EXCP_TLBRI] = "TLB read-inhibit",
 421     [EXCP_MSADIS] = "MSA disabled",
 422     [EXCP_MSAFPE] = "MSA floating point",
 423 };
 424 #endif
 425
 426 target_ulong exception_resume_pc (CPUMIPSState *env)
 427 {
 428     target_ulong bad_pc;
 429     target_ulong isa_mode;
 430
 431     isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
 432     bad_pc = env->active_tc.PC | isa_mode;
 433     if (env->hflags & MIPS_HFLAG_BMASK) {
 434         /* If the exception was raised from a delay slot, come back to
 435            the jump.  */
 436         bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
 437     }
 438
 439     return bad_pc;
 440 }
 441
 442 #if !defined(CONFIG_USER_ONLY)
 443 static void set_hflags_for_handler (CPUMIPSState *env)
 444 {
 445     /* Exception handlers are entered in 32-bit mode.  */
 446     env->hflags &= ~(MIPS_HFLAG_M16);
 447     /* ...except that microMIPS lets you choose.  */
 448     if (env->insn_flags & ASE_MICROMIPS) {
 449         env->hflags |= (!!(env->CP0_Config3
 450                            & (1 << CP0C3_ISA_ON_EXC))
 451                         << MIPS_HFLAG_M16_SHIFT);
 452     }
 453 }
 454
 455 static inline void set_badinstr_registers(CPUMIPSState *env)
 456 {
 457     if (env->hflags & MIPS_HFLAG_M16) {
 458         /* TODO: add BadInstr support for microMIPS */
 459         return;
 460     }
 461     if (env->CP0_Config3 & (1 << CP0C3_BI)) {
 462         env->CP0_BadInstr = cpu_ldl_code(env, env->active_tc.PC);
 463     }
 464     if ((env->CP0_Config3 & (1 << CP0C3_BP)) &&
 465         (env->hflags & MIPS_HFLAG_BMASK)) {
 466         env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4);
 467     }
 468 }
 469 #endif
 470
 471 void mips_cpu_do_interrupt(CPUState *cs)
 472 {
 473 #if !defined(CONFIG_USER_ONLY)
 474     MIPSCPU *cpu = MIPS_CPU(cs);
 475     CPUMIPSState *env = &cpu->env;
 476     bool update_badinstr = 0;
 477     target_ulong offset;
 478     int cause = -1;
 479     const char *name;
 480
 481     if (qemu_loglevel_mask(CPU_LOG_INT)
 482         && cs->exception_index != EXCP_EXT_INTERRUPT) {
 483         if (cs->exception_index < 0 || cs->exception_index > EXCP_LAST) {
 484             name = "unknown";
 485         } else {
 486             name = excp_names[cs->exception_index];
 487         }
 488
 489         qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx
 490                  " %s exception\n",
 491                  __func__, env->active_tc.PC, env->CP0_EPC, name);
 492     }
 493     if (cs->exception_index == EXCP_EXT_INTERRUPT &&
 494         (env->hflags & MIPS_HFLAG_DM)) {
 495         cs->exception_index = EXCP_DINT;
 496     }
 497     offset = 0x180;
 498     switch (cs->exception_index) {
 499     case EXCP_DSS:
 500         env->CP0_Debug |= 1 << CP0DB_DSS;
 501         /* Debug single step cannot be raised inside a delay slot and
 502            resume will always occur on the next instruction
 503            (but we assume the pc has always been updated during
 504            code translation). */
 505         env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16);
 506         goto enter_debug_mode;
 507     case EXCP_DINT:
 508         env->CP0_Debug |= 1 << CP0DB_DINT;
 509         goto set_DEPC;
 510     case EXCP_DIB:
 511         env->CP0_Debug |= 1 << CP0DB_DIB;
 512         goto set_DEPC;
 513     case EXCP_DBp:
 514         env->CP0_Debug |= 1 << CP0DB_DBp;
 515         goto set_DEPC;
 516     case EXCP_DDBS:
 517         env->CP0_Debug |= 1 << CP0DB_DDBS;
 518         goto set_DEPC;
 519     case EXCP_DDBL:
 520         env->CP0_Debug |= 1 << CP0DB_DDBL;
 521     set_DEPC:
 522         env->CP0_DEPC = exception_resume_pc(env);
 523         env->hflags &= ~MIPS_HFLAG_BMASK;
 524  enter_debug_mode:
 525         if (env->insn_flags & ISA_MIPS3) {
 526             env->hflags |= MIPS_HFLAG_64;
 527         }
 528         env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_CP0;
 529         env->hflags &= ~(MIPS_HFLAG_KSU);
 530         /* EJTAG probe trap enable is not implemented... */
 531         if (!(env->CP0_Status & (1 << CP0St_EXL)))
 532             env->CP0_Cause &= ~(1U << CP0Ca_BD);
 533         env->active_tc.PC = (int32_t)0xBFC00480;
 534         set_hflags_for_handler(env);
 535         break;
 536     case EXCP_RESET:
 537         cpu_reset(CPU(cpu));
 538         break;
 539     case EXCP_SRESET:
 540         env->CP0_Status |= (1 << CP0St_SR);
 541         memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
 542         goto set_error_EPC;
 543     case EXCP_NMI:
 544         env->CP0_Status |= (1 << CP0St_NMI);
 545  set_error_EPC:
 546         env->CP0_ErrorEPC = exception_resume_pc(env);
 547         env->hflags &= ~MIPS_HFLAG_BMASK;
 548         env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
 549         if (env->insn_flags & ISA_MIPS3) {
 550             env->hflags |= MIPS_HFLAG_64;
 551         }
 552         env->hflags |= MIPS_HFLAG_CP0;
 553         env->hflags &= ~(MIPS_HFLAG_KSU);
 554         if (!(env->CP0_Status & (1 << CP0St_EXL)))
 555             env->CP0_Cause &= ~(1U << CP0Ca_BD);
 556         env->active_tc.PC = (int32_t)0xBFC00000;
 557         set_hflags_for_handler(env);
 558         break;
 559     case EXCP_EXT_INTERRUPT:
 560         cause = 0;
 561         if (env->CP0_Cause & (1 << CP0Ca_IV)) {
 562             uint32_t spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & 0x1f;
 563
 564             if ((env->CP0_Status & (1 << CP0St_BEV)) || spacing == 0) {
 565                 offset = 0x200;
 566             } else {
 567                 uint32_t vector = 0;
 568                 uint32_t pending = (env->CP0_Cause & CP0Ca_IP_mask) >> CP0Ca_IP;
 569
 570                 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
 571                     /* For VEIC mode, the external interrupt controller feeds
 572                      * the vector through the CP0Cause IP lines.  */
 573                     vector = pending;
 574                 } else {
 575                     /* Vectored Interrupts
 576                      * Mask with Status.IM7-IM0 to get enabled interrupts. */
 577                     pending &= (env->CP0_Status >> CP0St_IM) & 0xff;
 578                     /* Find the highest-priority interrupt. */
 579                     while (pending >>= 1) {
 580                         vector++;
 581                     }
 582                 }
 583                 offset = 0x200 + (vector * (spacing << 5));
 584             }
 585         }
 586         goto set_EPC;
 587     case EXCP_LTLBL:
 588         cause = 1;
 589         update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
 590         goto set_EPC;
 591     case EXCP_TLBL:
 592         cause = 2;
 593         update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
 594         if ((env->error_code & EXCP_TLB_NOMATCH) &&
 595             !(env->CP0_Status & (1 << CP0St_EXL))) {
 596 #if defined(TARGET_MIPS64)
 597             int R = env->CP0_BadVAddr >> 62;
 598             int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 599             int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 600             int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 601
 602             if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
 603                 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
 604                 offset = 0x080;
 605             else
 606 #endif
 607                 offset = 0x000;
 608         }
 609         goto set_EPC;
 610     case EXCP_TLBS:
 611         cause = 3;
 612         update_badinstr = 1;
 613         if ((env->error_code & EXCP_TLB_NOMATCH) &&
 614             !(env->CP0_Status & (1 << CP0St_EXL))) {
 615 #if defined(TARGET_MIPS64)
 616             int R = env->CP0_BadVAddr >> 62;
 617             int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 618             int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 619             int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 620
 621             if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
 622                 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
 623                 offset = 0x080;
 624             else
 625 #endif
 626                 offset = 0x000;
 627         }
 628         goto set_EPC;
 629     case EXCP_AdEL:
 630         cause = 4;
 631         update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
 632         goto set_EPC;
 633     case EXCP_AdES:
 634         cause = 5;
 635         update_badinstr = 1;
 636         goto set_EPC;
 637     case EXCP_IBE:
 638         cause = 6;
 639         goto set_EPC;
 640     case EXCP_DBE:
 641         cause = 7;
 642         goto set_EPC;
 643     case EXCP_SYSCALL:
 644         cause = 8;
 645         update_badinstr = 1;
 646         goto set_EPC;
 647     case EXCP_BREAK:
 648         cause = 9;
 649         update_badinstr = 1;
 650         goto set_EPC;
 651     case EXCP_RI:
 652         cause = 10;
 653         update_badinstr = 1;
 654         goto set_EPC;
 655     case EXCP_CpU:
 656         cause = 11;
 657         update_badinstr = 1;
 658         env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
 659                          (env->error_code << CP0Ca_CE);
 660         goto set_EPC;
 661     case EXCP_OVERFLOW:
 662         cause = 12;
 663         update_badinstr = 1;
 664         goto set_EPC;
 665     case EXCP_TRAP:
 666         cause = 13;
 667         update_badinstr = 1;
 668         goto set_EPC;
 669     case EXCP_MSAFPE:
 670         cause = 14;
 671         update_badinstr = 1;
 672         goto set_EPC;
 673     case EXCP_FPE:
 674         cause = 15;
 675         update_badinstr = 1;
 676         goto set_EPC;
 677     case EXCP_C2E:
 678         cause = 18;
 679         goto set_EPC;
 680     case EXCP_TLBRI:
 681         cause = 19;
 682         update_badinstr = 1;
 683         goto set_EPC;
 684     case EXCP_TLBXI:
 685         cause = 20;
 686         goto set_EPC;
 687     case EXCP_MSADIS:
 688         cause = 21;
 689         update_badinstr = 1;
 690         goto set_EPC;
 691     case EXCP_MDMX:
 692         cause = 22;
 693         goto set_EPC;
 694     case EXCP_DWATCH:
 695         cause = 23;
 696         /* XXX: TODO: manage defered watch exceptions */
 697         goto set_EPC;
 698     case EXCP_MCHECK:
 699         cause = 24;
 700         goto set_EPC;
 701     case EXCP_THREAD:
 702         cause = 25;
 703         goto set_EPC;
 704     case EXCP_DSPDIS:
 705         cause = 26;
 706         goto set_EPC;
 707     case EXCP_CACHE:
 708         cause = 30;
 709         if (env->CP0_Status & (1 << CP0St_BEV)) {
 710             offset = 0x100;
 711         } else {
 712             offset = 0x20000100;
 713         }
 714  set_EPC:
 715         if (!(env->CP0_Status & (1 << CP0St_EXL))) {
 716             env->CP0_EPC = exception_resume_pc(env);
 717             if (update_badinstr) {
 718                 set_badinstr_registers(env);
 719             }
 720             if (env->hflags & MIPS_HFLAG_BMASK) {
 721                 env->CP0_Cause |= (1U << CP0Ca_BD);
 722             } else {
 723                 env->CP0_Cause &= ~(1U << CP0Ca_BD);
 724             }
 725             env->CP0_Status |= (1 << CP0St_EXL);
 726             if (env->insn_flags & ISA_MIPS3) {
 727                 env->hflags |= MIPS_HFLAG_64;
 728             }
 729             env->hflags |= MIPS_HFLAG_CP0;
 730             env->hflags &= ~(MIPS_HFLAG_KSU);
 731         }
 732         env->hflags &= ~MIPS_HFLAG_BMASK;
 733         if (env->CP0_Status & (1 << CP0St_BEV)) {
 734             env->active_tc.PC = (int32_t)0xBFC00200;
 735         } else {
 736             env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
 737         }
 738         env->active_tc.PC += offset;
 739         set_hflags_for_handler(env);
 740         env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
 741         break;
 742     default:
 743         abort();
 744     }
 745     if (qemu_loglevel_mask(CPU_LOG_INT)
 746         && cs->exception_index != EXCP_EXT_INTERRUPT) {
 747         qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
 748                  "    S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
 749                  __func__, env->active_tc.PC, env->CP0_EPC, cause,
 750                  env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
 751                  env->CP0_DEPC);
 752     }
 753 #endif
 754     cs->exception_index = EXCP_NONE;
 755 }
 756
 757 bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 758 {
 759     if (interrupt_request & CPU_INTERRUPT_HARD) {
 760         MIPSCPU *cpu = MIPS_CPU(cs);
 761         CPUMIPSState *env = &cpu->env;
 762
 763         if (cpu_mips_hw_interrupts_pending(env)) {
 764             /* Raise it */
 765             cs->exception_index = EXCP_EXT_INTERRUPT;
 766             env->error_code = 0;
 767             mips_cpu_do_interrupt(cs);
 768             return true;
 769         }
 770     }
 771     return false;
 772 }
 773
 774 #if !defined(CONFIG_USER_ONLY)
 775 void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
 776 {
 777     MIPSCPU *cpu = mips_env_get_cpu(env);
 778     CPUState *cs;
 779     r4k_tlb_t *tlb;
 780     target_ulong addr;
 781     target_ulong end;
 782     uint8_t ASID = env->CP0_EntryHi & 0xFF;
 783     target_ulong mask;
 784
 785     tlb = &env->tlb->mmu.r4k.tlb[idx];
 786     /* The qemu TLB is flushed when the ASID changes, so no need to
 787        flush these entries again.  */
 788     if (tlb->G == 0 && tlb->ASID != ASID) {
 789         return;
 790     }
 791
 792     if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
 793         /* For tlbwr, we can shadow the discarded entry into
 794            a new (fake) TLB entry, as long as the guest can not
 795            tell that it's there.  */
 796         env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
 797         env->tlb->tlb_in_use++;
 798         return;
 799     }
 800
 801     /* 1k pages are not supported. */
 802     mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
 803     if (tlb->V0) {
 804         cs = CPU(cpu);
 805         addr = tlb->VPN & ~mask;
 806 #if defined(TARGET_MIPS64)
 807         if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
 808             addr |= 0x3FFFFF0000000000ULL;
 809         }
 810 #endif
 811         end = addr | (mask >> 1);
 812         while (addr < end) {
 813             tlb_flush_page(cs, addr);
 814             addr += TARGET_PAGE_SIZE;
 815         }
 816     }
 817     if (tlb->V1) {
 818         cs = CPU(cpu);
 819         addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
 820 #if defined(TARGET_MIPS64)
 821         if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
 822             addr |= 0x3FFFFF0000000000ULL;
 823         }
 824 #endif
 825         end = addr | mask;
 826         while (addr - 1 < end) {
 827             tlb_flush_page(cs, addr);
 828             addr += TARGET_PAGE_SIZE;
 829         }
 830     }
 831 }
 832 #endif