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[mirror_qemu.git] / target-s390x / cpu.h
1 /*
2 * S/390 virtual CPU header
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * Contributions after 2012-10-29 are licensed under the terms of the
17 * GNU GPL, version 2 or (at your option) any later version.
18 *
19 * You should have received a copy of the GNU (Lesser) General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 */
22 #ifndef CPU_S390X_H
23 #define CPU_S390X_H
24
25 #include "qemu-common.h"
26 #include "cpu-qom.h"
27
28 #define TARGET_LONG_BITS 64
29
30 #define ELF_MACHINE_UNAME "S390X"
31
32 #define CPUArchState struct CPUS390XState
33
34 #include "exec/cpu-defs.h"
35 #define TARGET_PAGE_BITS 12
36
37 #define TARGET_PHYS_ADDR_SPACE_BITS 64
38 #define TARGET_VIRT_ADDR_SPACE_BITS 64
39
40 #include "exec/cpu-all.h"
41
42 #include "fpu/softfloat.h"
43
44 #define NB_MMU_MODES 3
45 #define TARGET_INSN_START_EXTRA_WORDS 1
46
47 #define MMU_MODE0_SUFFIX _primary
48 #define MMU_MODE1_SUFFIX _secondary
49 #define MMU_MODE2_SUFFIX _home
50
51 #define MMU_USER_IDX 0
52
53 #define MAX_EXT_QUEUE 16
54 #define MAX_IO_QUEUE 16
55 #define MAX_MCHK_QUEUE 16
56
57 #define PSW_MCHK_MASK 0x0004000000000000
58 #define PSW_IO_MASK 0x0200000000000000
59
60 typedef struct PSW {
61 uint64_t mask;
62 uint64_t addr;
63 } PSW;
64
65 typedef struct ExtQueue {
66 uint32_t code;
67 uint32_t param;
68 uint32_t param64;
69 } ExtQueue;
70
71 typedef struct IOIntQueue {
72 uint16_t id;
73 uint16_t nr;
74 uint32_t parm;
75 uint32_t word;
76 } IOIntQueue;
77
78 typedef struct MchkQueue {
79 uint16_t type;
80 } MchkQueue;
81
82 typedef struct CPUS390XState {
83 uint64_t regs[16]; /* GP registers */
84 /*
85 * The floating point registers are part of the vector registers.
86 * vregs[0][0] -> vregs[15][0] are 16 floating point registers
87 */
88 CPU_DoubleU vregs[32][2]; /* vector registers */
89 uint32_t aregs[16]; /* access registers */
90
91 uint32_t fpc; /* floating-point control register */
92 uint32_t cc_op;
93
94 float_status fpu_status; /* passed to softfloat lib */
95
96 /* The low part of a 128-bit return, or remainder of a divide. */
97 uint64_t retxl;
98
99 PSW psw;
100
101 uint64_t cc_src;
102 uint64_t cc_dst;
103 uint64_t cc_vr;
104
105 uint64_t __excp_addr;
106 uint64_t psa;
107
108 uint32_t int_pgm_code;
109 uint32_t int_pgm_ilen;
110
111 uint32_t int_svc_code;
112 uint32_t int_svc_ilen;
113
114 uint64_t per_address;
115 uint16_t per_perc_atmid;
116
117 uint64_t cregs[16]; /* control registers */
118
119 ExtQueue ext_queue[MAX_EXT_QUEUE];
120 IOIntQueue io_queue[MAX_IO_QUEUE][8];
121 MchkQueue mchk_queue[MAX_MCHK_QUEUE];
122
123 int pending_int;
124 int ext_index;
125 int io_index[8];
126 int mchk_index;
127
128 uint64_t ckc;
129 uint64_t cputm;
130 uint32_t todpr;
131
132 uint64_t pfault_token;
133 uint64_t pfault_compare;
134 uint64_t pfault_select;
135
136 uint64_t gbea;
137 uint64_t pp;
138
139 uint8_t riccb[64];
140
141 CPU_COMMON
142
143 /* reset does memset(0) up to here */
144
145 uint32_t cpu_num;
146 uint32_t machine_type;
147
148 uint64_t tod_offset;
149 uint64_t tod_basetime;
150 QEMUTimer *tod_timer;
151
152 QEMUTimer *cpu_timer;
153
154 /*
155 * The cpu state represents the logical state of a cpu. In contrast to other
156 * architectures, there is a difference between a halt and a stop on s390.
157 * If all cpus are either stopped (including check stop) or in the disabled
158 * wait state, the vm can be shut down.
159 */
160 #define CPU_STATE_UNINITIALIZED 0x00
161 #define CPU_STATE_STOPPED 0x01
162 #define CPU_STATE_CHECK_STOP 0x02
163 #define CPU_STATE_OPERATING 0x03
164 #define CPU_STATE_LOAD 0x04
165 uint8_t cpu_state;
166
167 /* currently processed sigp order */
168 uint8_t sigp_order;
169
170 } CPUS390XState;
171
172 static inline CPU_DoubleU *get_freg(CPUS390XState *cs, int nr)
173 {
174 return &cs->vregs[nr][0];
175 }
176
177 /**
178 * S390CPU:
179 * @env: #CPUS390XState.
180 *
181 * An S/390 CPU.
182 */
183 struct S390CPU {
184 /*< private >*/
185 CPUState parent_obj;
186 /*< public >*/
187
188 CPUS390XState env;
189 int64_t id;
190 /* needed for live migration */
191 void *irqstate;
192 uint32_t irqstate_saved_size;
193 };
194
195 static inline S390CPU *s390_env_get_cpu(CPUS390XState *env)
196 {
197 return container_of(env, S390CPU, env);
198 }
199
200 #define ENV_GET_CPU(e) CPU(s390_env_get_cpu(e))
201
202 #define ENV_OFFSET offsetof(S390CPU, env)
203
204 #ifndef CONFIG_USER_ONLY
205 extern const struct VMStateDescription vmstate_s390_cpu;
206 #endif
207
208 void s390_cpu_do_interrupt(CPUState *cpu);
209 bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req);
210 void s390_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
211 int flags);
212 int s390_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
213 int cpuid, void *opaque);
214
215 hwaddr s390_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
216 hwaddr s390_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);
217 int s390_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
218 int s390_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
219 void s390_cpu_gdb_init(CPUState *cs);
220 void s390x_cpu_debug_excp_handler(CPUState *cs);
221
222 #include "sysemu/kvm.h"
223
224 /* distinguish between 24 bit and 31 bit addressing */
225 #define HIGH_ORDER_BIT 0x80000000
226
227 /* Interrupt Codes */
228 /* Program Interrupts */
229 #define PGM_OPERATION 0x0001
230 #define PGM_PRIVILEGED 0x0002
231 #define PGM_EXECUTE 0x0003
232 #define PGM_PROTECTION 0x0004
233 #define PGM_ADDRESSING 0x0005
234 #define PGM_SPECIFICATION 0x0006
235 #define PGM_DATA 0x0007
236 #define PGM_FIXPT_OVERFLOW 0x0008
237 #define PGM_FIXPT_DIVIDE 0x0009
238 #define PGM_DEC_OVERFLOW 0x000a
239 #define PGM_DEC_DIVIDE 0x000b
240 #define PGM_HFP_EXP_OVERFLOW 0x000c
241 #define PGM_HFP_EXP_UNDERFLOW 0x000d
242 #define PGM_HFP_SIGNIFICANCE 0x000e
243 #define PGM_HFP_DIVIDE 0x000f
244 #define PGM_SEGMENT_TRANS 0x0010
245 #define PGM_PAGE_TRANS 0x0011
246 #define PGM_TRANS_SPEC 0x0012
247 #define PGM_SPECIAL_OP 0x0013
248 #define PGM_OPERAND 0x0015
249 #define PGM_TRACE_TABLE 0x0016
250 #define PGM_SPACE_SWITCH 0x001c
251 #define PGM_HFP_SQRT 0x001d
252 #define PGM_PC_TRANS_SPEC 0x001f
253 #define PGM_AFX_TRANS 0x0020
254 #define PGM_ASX_TRANS 0x0021
255 #define PGM_LX_TRANS 0x0022
256 #define PGM_EX_TRANS 0x0023
257 #define PGM_PRIM_AUTH 0x0024
258 #define PGM_SEC_AUTH 0x0025
259 #define PGM_ALET_SPEC 0x0028
260 #define PGM_ALEN_SPEC 0x0029
261 #define PGM_ALE_SEQ 0x002a
262 #define PGM_ASTE_VALID 0x002b
263 #define PGM_ASTE_SEQ 0x002c
264 #define PGM_EXT_AUTH 0x002d
265 #define PGM_STACK_FULL 0x0030
266 #define PGM_STACK_EMPTY 0x0031
267 #define PGM_STACK_SPEC 0x0032
268 #define PGM_STACK_TYPE 0x0033
269 #define PGM_STACK_OP 0x0034
270 #define PGM_ASCE_TYPE 0x0038
271 #define PGM_REG_FIRST_TRANS 0x0039
272 #define PGM_REG_SEC_TRANS 0x003a
273 #define PGM_REG_THIRD_TRANS 0x003b
274 #define PGM_MONITOR 0x0040
275 #define PGM_PER 0x0080
276 #define PGM_CRYPTO 0x0119
277
278 /* External Interrupts */
279 #define EXT_INTERRUPT_KEY 0x0040
280 #define EXT_CLOCK_COMP 0x1004
281 #define EXT_CPU_TIMER 0x1005
282 #define EXT_MALFUNCTION 0x1200
283 #define EXT_EMERGENCY 0x1201
284 #define EXT_EXTERNAL_CALL 0x1202
285 #define EXT_ETR 0x1406
286 #define EXT_SERVICE 0x2401
287 #define EXT_VIRTIO 0x2603
288
289 /* PSW defines */
290 #undef PSW_MASK_PER
291 #undef PSW_MASK_DAT
292 #undef PSW_MASK_IO
293 #undef PSW_MASK_EXT
294 #undef PSW_MASK_KEY
295 #undef PSW_SHIFT_KEY
296 #undef PSW_MASK_MCHECK
297 #undef PSW_MASK_WAIT
298 #undef PSW_MASK_PSTATE
299 #undef PSW_MASK_ASC
300 #undef PSW_MASK_CC
301 #undef PSW_MASK_PM
302 #undef PSW_MASK_64
303 #undef PSW_MASK_32
304 #undef PSW_MASK_ESA_ADDR
305
306 #define PSW_MASK_PER 0x4000000000000000ULL
307 #define PSW_MASK_DAT 0x0400000000000000ULL
308 #define PSW_MASK_IO 0x0200000000000000ULL
309 #define PSW_MASK_EXT 0x0100000000000000ULL
310 #define PSW_MASK_KEY 0x00F0000000000000ULL
311 #define PSW_SHIFT_KEY 56
312 #define PSW_MASK_MCHECK 0x0004000000000000ULL
313 #define PSW_MASK_WAIT 0x0002000000000000ULL
314 #define PSW_MASK_PSTATE 0x0001000000000000ULL
315 #define PSW_MASK_ASC 0x0000C00000000000ULL
316 #define PSW_MASK_CC 0x0000300000000000ULL
317 #define PSW_MASK_PM 0x00000F0000000000ULL
318 #define PSW_MASK_64 0x0000000100000000ULL
319 #define PSW_MASK_32 0x0000000080000000ULL
320 #define PSW_MASK_ESA_ADDR 0x000000007fffffffULL
321
322 #undef PSW_ASC_PRIMARY
323 #undef PSW_ASC_ACCREG
324 #undef PSW_ASC_SECONDARY
325 #undef PSW_ASC_HOME
326
327 #define PSW_ASC_PRIMARY 0x0000000000000000ULL
328 #define PSW_ASC_ACCREG 0x0000400000000000ULL
329 #define PSW_ASC_SECONDARY 0x0000800000000000ULL
330 #define PSW_ASC_HOME 0x0000C00000000000ULL
331
332 /* tb flags */
333
334 #define FLAG_MASK_PER (PSW_MASK_PER >> 32)
335 #define FLAG_MASK_DAT (PSW_MASK_DAT >> 32)
336 #define FLAG_MASK_IO (PSW_MASK_IO >> 32)
337 #define FLAG_MASK_EXT (PSW_MASK_EXT >> 32)
338 #define FLAG_MASK_KEY (PSW_MASK_KEY >> 32)
339 #define FLAG_MASK_MCHECK (PSW_MASK_MCHECK >> 32)
340 #define FLAG_MASK_WAIT (PSW_MASK_WAIT >> 32)
341 #define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> 32)
342 #define FLAG_MASK_ASC (PSW_MASK_ASC >> 32)
343 #define FLAG_MASK_CC (PSW_MASK_CC >> 32)
344 #define FLAG_MASK_PM (PSW_MASK_PM >> 32)
345 #define FLAG_MASK_64 (PSW_MASK_64 >> 32)
346 #define FLAG_MASK_32 0x00001000
347
348 /* Control register 0 bits */
349 #define CR0_LOWPROT 0x0000000010000000ULL
350 #define CR0_EDAT 0x0000000000800000ULL
351
352 /* MMU */
353 #define MMU_PRIMARY_IDX 0
354 #define MMU_SECONDARY_IDX 1
355 #define MMU_HOME_IDX 2
356
357 static inline int cpu_mmu_index (CPUS390XState *env, bool ifetch)
358 {
359 switch (env->psw.mask & PSW_MASK_ASC) {
360 case PSW_ASC_PRIMARY:
361 return MMU_PRIMARY_IDX;
362 case PSW_ASC_SECONDARY:
363 return MMU_SECONDARY_IDX;
364 case PSW_ASC_HOME:
365 return MMU_HOME_IDX;
366 case PSW_ASC_ACCREG:
367 /* Fallthrough: access register mode is not yet supported */
368 default:
369 abort();
370 }
371 }
372
373 static inline uint64_t cpu_mmu_idx_to_asc(int mmu_idx)
374 {
375 switch (mmu_idx) {
376 case MMU_PRIMARY_IDX:
377 return PSW_ASC_PRIMARY;
378 case MMU_SECONDARY_IDX:
379 return PSW_ASC_SECONDARY;
380 case MMU_HOME_IDX:
381 return PSW_ASC_HOME;
382 default:
383 abort();
384 }
385 }
386
387 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
388 target_ulong *cs_base, uint32_t *flags)
389 {
390 *pc = env->psw.addr;
391 *cs_base = 0;
392 *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
393 ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
394 }
395
396 /* While the PoO talks about ILC (a number between 1-3) what is actually
397 stored in LowCore is shifted left one bit (an even between 2-6). As
398 this is the actual length of the insn and therefore more useful, that
399 is what we want to pass around and manipulate. To make sure that we
400 have applied this distinction universally, rename the "ILC" to "ILEN". */
401 static inline int get_ilen(uint8_t opc)
402 {
403 switch (opc >> 6) {
404 case 0:
405 return 2;
406 case 1:
407 case 2:
408 return 4;
409 default:
410 return 6;
411 }
412 }
413
414 /* PER bits from control register 9 */
415 #define PER_CR9_EVENT_BRANCH 0x80000000
416 #define PER_CR9_EVENT_IFETCH 0x40000000
417 #define PER_CR9_EVENT_STORE 0x20000000
418 #define PER_CR9_EVENT_STORE_REAL 0x08000000
419 #define PER_CR9_EVENT_NULLIFICATION 0x01000000
420 #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000
421 #define PER_CR9_CONTROL_ALTERATION 0x00200000
422
423 /* PER bits from the PER CODE/ATMID/AI in lowcore */
424 #define PER_CODE_EVENT_BRANCH 0x8000
425 #define PER_CODE_EVENT_IFETCH 0x4000
426 #define PER_CODE_EVENT_STORE 0x2000
427 #define PER_CODE_EVENT_STORE_REAL 0x0800
428 #define PER_CODE_EVENT_NULLIFICATION 0x0100
429
430 /* Compute the ATMID field that is stored in the per_perc_atmid lowcore
431 entry when a PER exception is triggered. */
432 static inline uint8_t get_per_atmid(CPUS390XState *env)
433 {
434 return ((env->psw.mask & PSW_MASK_64) ? (1 << 7) : 0) |
435 ( (1 << 6) ) |
436 ((env->psw.mask & PSW_MASK_32) ? (1 << 5) : 0) |
437 ((env->psw.mask & PSW_MASK_DAT)? (1 << 4) : 0) |
438 ((env->psw.mask & PSW_ASC_SECONDARY)? (1 << 3) : 0) |
439 ((env->psw.mask & PSW_ASC_ACCREG)? (1 << 2) : 0);
440 }
441
442 /* Check if an address is within the PER starting address and the PER
443 ending address. The address range might loop. */
444 static inline bool get_per_in_range(CPUS390XState *env, uint64_t addr)
445 {
446 if (env->cregs[10] <= env->cregs[11]) {
447 return env->cregs[10] <= addr && addr <= env->cregs[11];
448 } else {
449 return env->cregs[10] <= addr || addr <= env->cregs[11];
450 }
451 }
452
453 #ifndef CONFIG_USER_ONLY
454 /* In several cases of runtime exceptions, we havn't recorded the true
455 instruction length. Use these codes when raising exceptions in order
456 to re-compute the length by examining the insn in memory. */
457 #define ILEN_LATER 0x20
458 #define ILEN_LATER_INC 0x21
459 void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen);
460 #endif
461
462 S390CPU *cpu_s390x_init(const char *cpu_model);
463 S390CPU *s390x_new_cpu(const char *cpu_model, int64_t id, Error **errp);
464 S390CPU *cpu_s390x_create(const char *cpu_model, Error **errp);
465 void s390x_translate_init(void);
466
467 /* you can call this signal handler from your SIGBUS and SIGSEGV
468 signal handlers to inform the virtual CPU of exceptions. non zero
469 is returned if the signal was handled by the virtual CPU. */
470 int cpu_s390x_signal_handler(int host_signum, void *pinfo,
471 void *puc);
472 int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
473 int mmu_idx);
474
475
476 #ifndef CONFIG_USER_ONLY
477 void do_restart_interrupt(CPUS390XState *env);
478
479 static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb,
480 uint8_t *ar)
481 {
482 hwaddr addr = 0;
483 uint8_t reg;
484
485 reg = ipb >> 28;
486 if (reg > 0) {
487 addr = env->regs[reg];
488 }
489 addr += (ipb >> 16) & 0xfff;
490 if (ar) {
491 *ar = reg;
492 }
493
494 return addr;
495 }
496
497 /* Base/displacement are at the same locations. */
498 #define decode_basedisp_rs decode_basedisp_s
499
500 /* helper functions for run_on_cpu() */
501 static inline void s390_do_cpu_reset(void *arg)
502 {
503 CPUState *cs = arg;
504 S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
505
506 scc->cpu_reset(cs);
507 }
508 static inline void s390_do_cpu_full_reset(void *arg)
509 {
510 CPUState *cs = arg;
511
512 cpu_reset(cs);
513 }
514
515 void s390x_tod_timer(void *opaque);
516 void s390x_cpu_timer(void *opaque);
517
518 int s390_virtio_hypercall(CPUS390XState *env);
519
520 #ifdef CONFIG_KVM
521 void kvm_s390_service_interrupt(uint32_t parm);
522 void kvm_s390_vcpu_interrupt(S390CPU *cpu, struct kvm_s390_irq *irq);
523 void kvm_s390_floating_interrupt(struct kvm_s390_irq *irq);
524 int kvm_s390_inject_flic(struct kvm_s390_irq *irq);
525 void kvm_s390_access_exception(S390CPU *cpu, uint16_t code, uint64_t te_code);
526 int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar, void *hostbuf,
527 int len, bool is_write);
528 int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_clock);
529 int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_clock);
530 #else
531 static inline void kvm_s390_service_interrupt(uint32_t parm)
532 {
533 }
534 static inline int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
535 {
536 return -ENOSYS;
537 }
538 static inline int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
539 {
540 return -ENOSYS;
541 }
542 static inline int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar,
543 void *hostbuf, int len, bool is_write)
544 {
545 return -ENOSYS;
546 }
547 static inline void kvm_s390_access_exception(S390CPU *cpu, uint16_t code,
548 uint64_t te_code)
549 {
550 }
551 #endif
552
553 static inline int s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
554 {
555 if (kvm_enabled()) {
556 return kvm_s390_get_clock(tod_high, tod_low);
557 }
558 /* Fixme TCG */
559 *tod_high = 0;
560 *tod_low = 0;
561 return 0;
562 }
563
564 static inline int s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
565 {
566 if (kvm_enabled()) {
567 return kvm_s390_set_clock(tod_high, tod_low);
568 }
569 /* Fixme TCG */
570 return 0;
571 }
572
573 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
574 unsigned int s390_cpu_halt(S390CPU *cpu);
575 void s390_cpu_unhalt(S390CPU *cpu);
576 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
577 static inline uint8_t s390_cpu_get_state(S390CPU *cpu)
578 {
579 return cpu->env.cpu_state;
580 }
581
582 void gtod_save(QEMUFile *f, void *opaque);
583 int gtod_load(QEMUFile *f, void *opaque, int version_id);
584
585 void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
586 uint64_t param64);
587
588 /* ioinst.c */
589 void ioinst_handle_xsch(S390CPU *cpu, uint64_t reg1);
590 void ioinst_handle_csch(S390CPU *cpu, uint64_t reg1);
591 void ioinst_handle_hsch(S390CPU *cpu, uint64_t reg1);
592 void ioinst_handle_msch(S390CPU *cpu, uint64_t reg1, uint32_t ipb);
593 void ioinst_handle_ssch(S390CPU *cpu, uint64_t reg1, uint32_t ipb);
594 void ioinst_handle_stcrw(S390CPU *cpu, uint32_t ipb);
595 void ioinst_handle_stsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb);
596 int ioinst_handle_tsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb);
597 void ioinst_handle_chsc(S390CPU *cpu, uint32_t ipb);
598 int ioinst_handle_tpi(S390CPU *cpu, uint32_t ipb);
599 void ioinst_handle_schm(S390CPU *cpu, uint64_t reg1, uint64_t reg2,
600 uint32_t ipb);
601 void ioinst_handle_rsch(S390CPU *cpu, uint64_t reg1);
602 void ioinst_handle_rchp(S390CPU *cpu, uint64_t reg1);
603 void ioinst_handle_sal(S390CPU *cpu, uint64_t reg1);
604
605 /* service interrupts are floating therefore we must not pass an cpustate */
606 void s390_sclp_extint(uint32_t parm);
607
608 #else
609 static inline unsigned int s390_cpu_halt(S390CPU *cpu)
610 {
611 return 0;
612 }
613
614 static inline void s390_cpu_unhalt(S390CPU *cpu)
615 {
616 }
617
618 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
619 {
620 return 0;
621 }
622 #endif
623 void cpu_lock(void);
624 void cpu_unlock(void);
625
626 extern void subsystem_reset(void);
627
628 #define cpu_init(model) CPU(cpu_s390x_init(model))
629 #define cpu_signal_handler cpu_s390x_signal_handler
630
631 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
632 #define cpu_list s390_cpu_list
633
634 #define EXCP_EXT 1 /* external interrupt */
635 #define EXCP_SVC 2 /* supervisor call (syscall) */
636 #define EXCP_PGM 3 /* program interruption */
637 #define EXCP_IO 7 /* I/O interrupt */
638 #define EXCP_MCHK 8 /* machine check */
639
640 #define INTERRUPT_EXT (1 << 0)
641 #define INTERRUPT_TOD (1 << 1)
642 #define INTERRUPT_CPUTIMER (1 << 2)
643 #define INTERRUPT_IO (1 << 3)
644 #define INTERRUPT_MCHK (1 << 4)
645
646 /* Program Status Word. */
647 #define S390_PSWM_REGNUM 0
648 #define S390_PSWA_REGNUM 1
649 /* General Purpose Registers. */
650 #define S390_R0_REGNUM 2
651 #define S390_R1_REGNUM 3
652 #define S390_R2_REGNUM 4
653 #define S390_R3_REGNUM 5
654 #define S390_R4_REGNUM 6
655 #define S390_R5_REGNUM 7
656 #define S390_R6_REGNUM 8
657 #define S390_R7_REGNUM 9
658 #define S390_R8_REGNUM 10
659 #define S390_R9_REGNUM 11
660 #define S390_R10_REGNUM 12
661 #define S390_R11_REGNUM 13
662 #define S390_R12_REGNUM 14
663 #define S390_R13_REGNUM 15
664 #define S390_R14_REGNUM 16
665 #define S390_R15_REGNUM 17
666 /* Total Core Registers. */
667 #define S390_NUM_CORE_REGS 18
668
669 /* CC optimization */
670
671 enum cc_op {
672 CC_OP_CONST0 = 0, /* CC is 0 */
673 CC_OP_CONST1, /* CC is 1 */
674 CC_OP_CONST2, /* CC is 2 */
675 CC_OP_CONST3, /* CC is 3 */
676
677 CC_OP_DYNAMIC, /* CC calculation defined by env->cc_op */
678 CC_OP_STATIC, /* CC value is env->cc_op */
679
680 CC_OP_NZ, /* env->cc_dst != 0 */
681 CC_OP_LTGT_32, /* signed less/greater than (32bit) */
682 CC_OP_LTGT_64, /* signed less/greater than (64bit) */
683 CC_OP_LTUGTU_32, /* unsigned less/greater than (32bit) */
684 CC_OP_LTUGTU_64, /* unsigned less/greater than (64bit) */
685 CC_OP_LTGT0_32, /* signed less/greater than 0 (32bit) */
686 CC_OP_LTGT0_64, /* signed less/greater than 0 (64bit) */
687
688 CC_OP_ADD_64, /* overflow on add (64bit) */
689 CC_OP_ADDU_64, /* overflow on unsigned add (64bit) */
690 CC_OP_ADDC_64, /* overflow on unsigned add-carry (64bit) */
691 CC_OP_SUB_64, /* overflow on subtraction (64bit) */
692 CC_OP_SUBU_64, /* overflow on unsigned subtraction (64bit) */
693 CC_OP_SUBB_64, /* overflow on unsigned sub-borrow (64bit) */
694 CC_OP_ABS_64, /* sign eval on abs (64bit) */
695 CC_OP_NABS_64, /* sign eval on nabs (64bit) */
696
697 CC_OP_ADD_32, /* overflow on add (32bit) */
698 CC_OP_ADDU_32, /* overflow on unsigned add (32bit) */
699 CC_OP_ADDC_32, /* overflow on unsigned add-carry (32bit) */
700 CC_OP_SUB_32, /* overflow on subtraction (32bit) */
701 CC_OP_SUBU_32, /* overflow on unsigned subtraction (32bit) */
702 CC_OP_SUBB_32, /* overflow on unsigned sub-borrow (32bit) */
703 CC_OP_ABS_32, /* sign eval on abs (64bit) */
704 CC_OP_NABS_32, /* sign eval on nabs (64bit) */
705
706 CC_OP_COMP_32, /* complement */
707 CC_OP_COMP_64, /* complement */
708
709 CC_OP_TM_32, /* test under mask (32bit) */
710 CC_OP_TM_64, /* test under mask (64bit) */
711
712 CC_OP_NZ_F32, /* FP dst != 0 (32bit) */
713 CC_OP_NZ_F64, /* FP dst != 0 (64bit) */
714 CC_OP_NZ_F128, /* FP dst != 0 (128bit) */
715
716 CC_OP_ICM, /* insert characters under mask */
717 CC_OP_SLA_32, /* Calculate shift left signed (32bit) */
718 CC_OP_SLA_64, /* Calculate shift left signed (64bit) */
719 CC_OP_FLOGR, /* find leftmost one */
720 CC_OP_MAX
721 };
722
723 static const char *cc_names[] = {
724 [CC_OP_CONST0] = "CC_OP_CONST0",
725 [CC_OP_CONST1] = "CC_OP_CONST1",
726 [CC_OP_CONST2] = "CC_OP_CONST2",
727 [CC_OP_CONST3] = "CC_OP_CONST3",
728 [CC_OP_DYNAMIC] = "CC_OP_DYNAMIC",
729 [CC_OP_STATIC] = "CC_OP_STATIC",
730 [CC_OP_NZ] = "CC_OP_NZ",
731 [CC_OP_LTGT_32] = "CC_OP_LTGT_32",
732 [CC_OP_LTGT_64] = "CC_OP_LTGT_64",
733 [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
734 [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
735 [CC_OP_LTGT0_32] = "CC_OP_LTGT0_32",
736 [CC_OP_LTGT0_64] = "CC_OP_LTGT0_64",
737 [CC_OP_ADD_64] = "CC_OP_ADD_64",
738 [CC_OP_ADDU_64] = "CC_OP_ADDU_64",
739 [CC_OP_ADDC_64] = "CC_OP_ADDC_64",
740 [CC_OP_SUB_64] = "CC_OP_SUB_64",
741 [CC_OP_SUBU_64] = "CC_OP_SUBU_64",
742 [CC_OP_SUBB_64] = "CC_OP_SUBB_64",
743 [CC_OP_ABS_64] = "CC_OP_ABS_64",
744 [CC_OP_NABS_64] = "CC_OP_NABS_64",
745 [CC_OP_ADD_32] = "CC_OP_ADD_32",
746 [CC_OP_ADDU_32] = "CC_OP_ADDU_32",
747 [CC_OP_ADDC_32] = "CC_OP_ADDC_32",
748 [CC_OP_SUB_32] = "CC_OP_SUB_32",
749 [CC_OP_SUBU_32] = "CC_OP_SUBU_32",
750 [CC_OP_SUBB_32] = "CC_OP_SUBB_32",
751 [CC_OP_ABS_32] = "CC_OP_ABS_32",
752 [CC_OP_NABS_32] = "CC_OP_NABS_32",
753 [CC_OP_COMP_32] = "CC_OP_COMP_32",
754 [CC_OP_COMP_64] = "CC_OP_COMP_64",
755 [CC_OP_TM_32] = "CC_OP_TM_32",
756 [CC_OP_TM_64] = "CC_OP_TM_64",
757 [CC_OP_NZ_F32] = "CC_OP_NZ_F32",
758 [CC_OP_NZ_F64] = "CC_OP_NZ_F64",
759 [CC_OP_NZ_F128] = "CC_OP_NZ_F128",
760 [CC_OP_ICM] = "CC_OP_ICM",
761 [CC_OP_SLA_32] = "CC_OP_SLA_32",
762 [CC_OP_SLA_64] = "CC_OP_SLA_64",
763 [CC_OP_FLOGR] = "CC_OP_FLOGR",
764 };
765
766 static inline const char *cc_name(int cc_op)
767 {
768 return cc_names[cc_op];
769 }
770
771 static inline void setcc(S390CPU *cpu, uint64_t cc)
772 {
773 CPUS390XState *env = &cpu->env;
774
775 env->psw.mask &= ~(3ull << 44);
776 env->psw.mask |= (cc & 3) << 44;
777 env->cc_op = cc;
778 }
779
780 typedef struct LowCore
781 {
782 /* prefix area: defined by architecture */
783 uint32_t ccw1[2]; /* 0x000 */
784 uint32_t ccw2[4]; /* 0x008 */
785 uint8_t pad1[0x80-0x18]; /* 0x018 */
786 uint32_t ext_params; /* 0x080 */
787 uint16_t cpu_addr; /* 0x084 */
788 uint16_t ext_int_code; /* 0x086 */
789 uint16_t svc_ilen; /* 0x088 */
790 uint16_t svc_code; /* 0x08a */
791 uint16_t pgm_ilen; /* 0x08c */
792 uint16_t pgm_code; /* 0x08e */
793 uint32_t data_exc_code; /* 0x090 */
794 uint16_t mon_class_num; /* 0x094 */
795 uint16_t per_perc_atmid; /* 0x096 */
796 uint64_t per_address; /* 0x098 */
797 uint8_t exc_access_id; /* 0x0a0 */
798 uint8_t per_access_id; /* 0x0a1 */
799 uint8_t op_access_id; /* 0x0a2 */
800 uint8_t ar_access_id; /* 0x0a3 */
801 uint8_t pad2[0xA8-0xA4]; /* 0x0a4 */
802 uint64_t trans_exc_code; /* 0x0a8 */
803 uint64_t monitor_code; /* 0x0b0 */
804 uint16_t subchannel_id; /* 0x0b8 */
805 uint16_t subchannel_nr; /* 0x0ba */
806 uint32_t io_int_parm; /* 0x0bc */
807 uint32_t io_int_word; /* 0x0c0 */
808 uint8_t pad3[0xc8-0xc4]; /* 0x0c4 */
809 uint32_t stfl_fac_list; /* 0x0c8 */
810 uint8_t pad4[0xe8-0xcc]; /* 0x0cc */
811 uint32_t mcck_interruption_code[2]; /* 0x0e8 */
812 uint8_t pad5[0xf4-0xf0]; /* 0x0f0 */
813 uint32_t external_damage_code; /* 0x0f4 */
814 uint64_t failing_storage_address; /* 0x0f8 */
815 uint8_t pad6[0x110-0x100]; /* 0x100 */
816 uint64_t per_breaking_event_addr; /* 0x110 */
817 uint8_t pad7[0x120-0x118]; /* 0x118 */
818 PSW restart_old_psw; /* 0x120 */
819 PSW external_old_psw; /* 0x130 */
820 PSW svc_old_psw; /* 0x140 */
821 PSW program_old_psw; /* 0x150 */
822 PSW mcck_old_psw; /* 0x160 */
823 PSW io_old_psw; /* 0x170 */
824 uint8_t pad8[0x1a0-0x180]; /* 0x180 */
825 PSW restart_new_psw; /* 0x1a0 */
826 PSW external_new_psw; /* 0x1b0 */
827 PSW svc_new_psw; /* 0x1c0 */
828 PSW program_new_psw; /* 0x1d0 */
829 PSW mcck_new_psw; /* 0x1e0 */
830 PSW io_new_psw; /* 0x1f0 */
831 PSW return_psw; /* 0x200 */
832 uint8_t irb[64]; /* 0x210 */
833 uint64_t sync_enter_timer; /* 0x250 */
834 uint64_t async_enter_timer; /* 0x258 */
835 uint64_t exit_timer; /* 0x260 */
836 uint64_t last_update_timer; /* 0x268 */
837 uint64_t user_timer; /* 0x270 */
838 uint64_t system_timer; /* 0x278 */
839 uint64_t last_update_clock; /* 0x280 */
840 uint64_t steal_clock; /* 0x288 */
841 PSW return_mcck_psw; /* 0x290 */
842 uint8_t pad9[0xc00-0x2a0]; /* 0x2a0 */
843 /* System info area */
844 uint64_t save_area[16]; /* 0xc00 */
845 uint8_t pad10[0xd40-0xc80]; /* 0xc80 */
846 uint64_t kernel_stack; /* 0xd40 */
847 uint64_t thread_info; /* 0xd48 */
848 uint64_t async_stack; /* 0xd50 */
849 uint64_t kernel_asce; /* 0xd58 */
850 uint64_t user_asce; /* 0xd60 */
851 uint64_t panic_stack; /* 0xd68 */
852 uint64_t user_exec_asce; /* 0xd70 */
853 uint8_t pad11[0xdc0-0xd78]; /* 0xd78 */
854
855 /* SMP info area: defined by DJB */
856 uint64_t clock_comparator; /* 0xdc0 */
857 uint64_t ext_call_fast; /* 0xdc8 */
858 uint64_t percpu_offset; /* 0xdd0 */
859 uint64_t current_task; /* 0xdd8 */
860 uint32_t softirq_pending; /* 0xde0 */
861 uint32_t pad_0x0de4; /* 0xde4 */
862 uint64_t int_clock; /* 0xde8 */
863 uint8_t pad12[0xe00-0xdf0]; /* 0xdf0 */
864
865 /* 0xe00 is used as indicator for dump tools */
866 /* whether the kernel died with panic() or not */
867 uint32_t panic_magic; /* 0xe00 */
868
869 uint8_t pad13[0x11b8-0xe04]; /* 0xe04 */
870
871 /* 64 bit extparam used for pfault, diag 250 etc */
872 uint64_t ext_params2; /* 0x11B8 */
873
874 uint8_t pad14[0x1200-0x11C0]; /* 0x11C0 */
875
876 /* System info area */
877
878 uint64_t floating_pt_save_area[16]; /* 0x1200 */
879 uint64_t gpregs_save_area[16]; /* 0x1280 */
880 uint32_t st_status_fixed_logout[4]; /* 0x1300 */
881 uint8_t pad15[0x1318-0x1310]; /* 0x1310 */
882 uint32_t prefixreg_save_area; /* 0x1318 */
883 uint32_t fpt_creg_save_area; /* 0x131c */
884 uint8_t pad16[0x1324-0x1320]; /* 0x1320 */
885 uint32_t tod_progreg_save_area; /* 0x1324 */
886 uint32_t cpu_timer_save_area[2]; /* 0x1328 */
887 uint32_t clock_comp_save_area[2]; /* 0x1330 */
888 uint8_t pad17[0x1340-0x1338]; /* 0x1338 */
889 uint32_t access_regs_save_area[16]; /* 0x1340 */
890 uint64_t cregs_save_area[16]; /* 0x1380 */
891
892 /* align to the top of the prefix area */
893
894 uint8_t pad18[0x2000-0x1400]; /* 0x1400 */
895 } QEMU_PACKED LowCore;
896
897 /* STSI */
898 #define STSI_LEVEL_MASK 0x00000000f0000000ULL
899 #define STSI_LEVEL_CURRENT 0x0000000000000000ULL
900 #define STSI_LEVEL_1 0x0000000010000000ULL
901 #define STSI_LEVEL_2 0x0000000020000000ULL
902 #define STSI_LEVEL_3 0x0000000030000000ULL
903 #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
904 #define STSI_R0_SEL1_MASK 0x00000000000000ffULL
905 #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
906 #define STSI_R1_SEL2_MASK 0x000000000000ffffULL
907
908 /* Basic Machine Configuration */
909 struct sysib_111 {
910 uint32_t res1[8];
911 uint8_t manuf[16];
912 uint8_t type[4];
913 uint8_t res2[12];
914 uint8_t model[16];
915 uint8_t sequence[16];
916 uint8_t plant[4];
917 uint8_t res3[156];
918 };
919
920 /* Basic Machine CPU */
921 struct sysib_121 {
922 uint32_t res1[80];
923 uint8_t sequence[16];
924 uint8_t plant[4];
925 uint8_t res2[2];
926 uint16_t cpu_addr;
927 uint8_t res3[152];
928 };
929
930 /* Basic Machine CPUs */
931 struct sysib_122 {
932 uint8_t res1[32];
933 uint32_t capability;
934 uint16_t total_cpus;
935 uint16_t active_cpus;
936 uint16_t standby_cpus;
937 uint16_t reserved_cpus;
938 uint16_t adjustments[2026];
939 };
940
941 /* LPAR CPU */
942 struct sysib_221 {
943 uint32_t res1[80];
944 uint8_t sequence[16];
945 uint8_t plant[4];
946 uint16_t cpu_id;
947 uint16_t cpu_addr;
948 uint8_t res3[152];
949 };
950
951 /* LPAR CPUs */
952 struct sysib_222 {
953 uint32_t res1[32];
954 uint16_t lpar_num;
955 uint8_t res2;
956 uint8_t lcpuc;
957 uint16_t total_cpus;
958 uint16_t conf_cpus;
959 uint16_t standby_cpus;
960 uint16_t reserved_cpus;
961 uint8_t name[8];
962 uint32_t caf;
963 uint8_t res3[16];
964 uint16_t dedicated_cpus;
965 uint16_t shared_cpus;
966 uint8_t res4[180];
967 };
968
969 /* VM CPUs */
970 struct sysib_322 {
971 uint8_t res1[31];
972 uint8_t count;
973 struct {
974 uint8_t res2[4];
975 uint16_t total_cpus;
976 uint16_t conf_cpus;
977 uint16_t standby_cpus;
978 uint16_t reserved_cpus;
979 uint8_t name[8];
980 uint32_t caf;
981 uint8_t cpi[16];
982 uint8_t res5[3];
983 uint8_t ext_name_encoding;
984 uint32_t res3;
985 uint8_t uuid[16];
986 } vm[8];
987 uint8_t res4[1504];
988 uint8_t ext_names[8][256];
989 };
990
991 /* MMU defines */
992 #define _ASCE_ORIGIN ~0xfffULL /* segment table origin */
993 #define _ASCE_SUBSPACE 0x200 /* subspace group control */
994 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
995 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
996 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
997 #define _ASCE_REAL_SPACE 0x20 /* real space control */
998 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
999 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */
1000 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */
1001 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */
1002 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
1003 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */
1004
1005 #define _REGION_ENTRY_ORIGIN ~0xfffULL /* region/segment table origin */
1006 #define _REGION_ENTRY_RO 0x200 /* region/segment protection bit */
1007 #define _REGION_ENTRY_TF 0xc0 /* region/segment table offset */
1008 #define _REGION_ENTRY_INV 0x20 /* invalid region table entry */
1009 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
1010 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
1011 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
1012 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
1013 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */
1014
1015 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL /* segment table origin */
1016 #define _SEGMENT_ENTRY_FC 0x400 /* format control */
1017 #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
1018 #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
1019
1020 #define _PAGE_RO 0x200 /* HW read-only bit */
1021 #define _PAGE_INVALID 0x400 /* HW invalid bit */
1022 #define _PAGE_RES0 0x800 /* bit must be zero */
1023
1024 #define SK_C (0x1 << 1)
1025 #define SK_R (0x1 << 2)
1026 #define SK_F (0x1 << 3)
1027 #define SK_ACC_MASK (0xf << 4)
1028
1029 /* SIGP order codes */
1030 #define SIGP_SENSE 0x01
1031 #define SIGP_EXTERNAL_CALL 0x02
1032 #define SIGP_EMERGENCY 0x03
1033 #define SIGP_START 0x04
1034 #define SIGP_STOP 0x05
1035 #define SIGP_RESTART 0x06
1036 #define SIGP_STOP_STORE_STATUS 0x09
1037 #define SIGP_INITIAL_CPU_RESET 0x0b
1038 #define SIGP_CPU_RESET 0x0c
1039 #define SIGP_SET_PREFIX 0x0d
1040 #define SIGP_STORE_STATUS_ADDR 0x0e
1041 #define SIGP_SET_ARCH 0x12
1042 #define SIGP_STORE_ADTL_STATUS 0x17
1043
1044 /* SIGP condition codes */
1045 #define SIGP_CC_ORDER_CODE_ACCEPTED 0
1046 #define SIGP_CC_STATUS_STORED 1
1047 #define SIGP_CC_BUSY 2
1048 #define SIGP_CC_NOT_OPERATIONAL 3
1049
1050 /* SIGP status bits */
1051 #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
1052 #define SIGP_STAT_INCORRECT_STATE 0x00000200UL
1053 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
1054 #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
1055 #define SIGP_STAT_STOPPED 0x00000040UL
1056 #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
1057 #define SIGP_STAT_CHECK_STOP 0x00000010UL
1058 #define SIGP_STAT_INOPERATIVE 0x00000004UL
1059 #define SIGP_STAT_INVALID_ORDER 0x00000002UL
1060 #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
1061
1062 /* SIGP SET ARCHITECTURE modes */
1063 #define SIGP_MODE_ESA_S390 0
1064 #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
1065 #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
1066
1067 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
1068 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
1069 target_ulong *raddr, int *flags, bool exc);
1070 int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
1071 uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
1072 uint64_t vr);
1073 void s390_cpu_recompute_watchpoints(CPUState *cs);
1074
1075 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
1076 int len, bool is_write);
1077
1078 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \
1079 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
1080 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \
1081 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
1082 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \
1083 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
1084
1085 /* The value of the TOD clock for 1.1.1970. */
1086 #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
1087
1088 /* Converts ns to s390's clock format */
1089 static inline uint64_t time2tod(uint64_t ns) {
1090 return (ns << 9) / 125;
1091 }
1092
1093 /* Converts s390's clock format to ns */
1094 static inline uint64_t tod2time(uint64_t t) {
1095 return (t * 125) >> 9;
1096 }
1097
1098 /* from s390-virtio-ccw */
1099 #define MEM_SECTION_SIZE 0x10000000UL
1100 #define MAX_AVAIL_SLOTS 32
1101
1102 /* fpu_helper.c */
1103 uint32_t set_cc_nz_f32(float32 v);
1104 uint32_t set_cc_nz_f64(float64 v);
1105 uint32_t set_cc_nz_f128(float128 v);
1106
1107 /* misc_helper.c */
1108 #ifndef CONFIG_USER_ONLY
1109 int handle_diag_288(CPUS390XState *env, uint64_t r1, uint64_t r3);
1110 void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3);
1111 #endif
1112 void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
1113 void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
1114 uintptr_t retaddr);
1115
1116 #ifdef CONFIG_KVM
1117 void kvm_s390_io_interrupt(uint16_t subchannel_id,
1118 uint16_t subchannel_nr, uint32_t io_int_parm,
1119 uint32_t io_int_word);
1120 void kvm_s390_crw_mchk(void);
1121 void kvm_s390_enable_css_support(S390CPU *cpu);
1122 int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
1123 int vq, bool assign);
1124 int kvm_s390_cpu_restart(S390CPU *cpu);
1125 int kvm_s390_get_memslot_count(KVMState *s);
1126 void kvm_s390_cmma_reset(void);
1127 int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state);
1128 void kvm_s390_reset_vcpu(S390CPU *cpu);
1129 int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit, uint64_t *hw_limit);
1130 void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu);
1131 int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu);
1132 int kvm_s390_get_ri(void);
1133 void kvm_s390_crypto_reset(void);
1134 #else
1135 static inline void kvm_s390_io_interrupt(uint16_t subchannel_id,
1136 uint16_t subchannel_nr,
1137 uint32_t io_int_parm,
1138 uint32_t io_int_word)
1139 {
1140 }
1141 static inline void kvm_s390_crw_mchk(void)
1142 {
1143 }
1144 static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1145 {
1146 }
1147 static inline int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier,
1148 uint32_t sch, int vq,
1149 bool assign)
1150 {
1151 return -ENOSYS;
1152 }
1153 static inline int kvm_s390_cpu_restart(S390CPU *cpu)
1154 {
1155 return -ENOSYS;
1156 }
1157 static inline void kvm_s390_cmma_reset(void)
1158 {
1159 }
1160 static inline int kvm_s390_get_memslot_count(KVMState *s)
1161 {
1162 return MAX_AVAIL_SLOTS;
1163 }
1164 static inline int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state)
1165 {
1166 return -ENOSYS;
1167 }
1168 static inline void kvm_s390_reset_vcpu(S390CPU *cpu)
1169 {
1170 }
1171 static inline int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit,
1172 uint64_t *hw_limit)
1173 {
1174 return 0;
1175 }
1176 static inline void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu)
1177 {
1178 }
1179 static inline int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu)
1180 {
1181 return 0;
1182 }
1183 static inline int kvm_s390_get_ri(void)
1184 {
1185 return 0;
1186 }
1187 static inline void kvm_s390_crypto_reset(void)
1188 {
1189 }
1190 #endif
1191
1192 static inline int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit)
1193 {
1194 if (kvm_enabled()) {
1195 return kvm_s390_set_mem_limit(kvm_state, new_limit, hw_limit);
1196 }
1197 return 0;
1198 }
1199
1200 static inline void s390_cmma_reset(void)
1201 {
1202 if (kvm_enabled()) {
1203 kvm_s390_cmma_reset();
1204 }
1205 }
1206
1207 static inline int s390_cpu_restart(S390CPU *cpu)
1208 {
1209 if (kvm_enabled()) {
1210 return kvm_s390_cpu_restart(cpu);
1211 }
1212 return -ENOSYS;
1213 }
1214
1215 static inline int s390_get_memslot_count(KVMState *s)
1216 {
1217 if (kvm_enabled()) {
1218 return kvm_s390_get_memslot_count(s);
1219 } else {
1220 return MAX_AVAIL_SLOTS;
1221 }
1222 }
1223
1224 void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
1225 uint32_t io_int_parm, uint32_t io_int_word);
1226 void s390_crw_mchk(void);
1227
1228 static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
1229 uint32_t sch_id, int vq,
1230 bool assign)
1231 {
1232 return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
1233 }
1234
1235 static inline void s390_crypto_reset(void)
1236 {
1237 if (kvm_enabled()) {
1238 kvm_s390_crypto_reset();
1239 }
1240 }
1241
1242 /* machine check interruption code */
1243
1244 /* subclasses */
1245 #define MCIC_SC_SD 0x8000000000000000ULL
1246 #define MCIC_SC_PD 0x4000000000000000ULL
1247 #define MCIC_SC_SR 0x2000000000000000ULL
1248 #define MCIC_SC_CD 0x0800000000000000ULL
1249 #define MCIC_SC_ED 0x0400000000000000ULL
1250 #define MCIC_SC_DG 0x0100000000000000ULL
1251 #define MCIC_SC_W 0x0080000000000000ULL
1252 #define MCIC_SC_CP 0x0040000000000000ULL
1253 #define MCIC_SC_SP 0x0020000000000000ULL
1254 #define MCIC_SC_CK 0x0010000000000000ULL
1255
1256 /* subclass modifiers */
1257 #define MCIC_SCM_B 0x0002000000000000ULL
1258 #define MCIC_SCM_DA 0x0000000020000000ULL
1259 #define MCIC_SCM_AP 0x0000000000080000ULL
1260
1261 /* storage errors */
1262 #define MCIC_SE_SE 0x0000800000000000ULL
1263 #define MCIC_SE_SC 0x0000400000000000ULL
1264 #define MCIC_SE_KE 0x0000200000000000ULL
1265 #define MCIC_SE_DS 0x0000100000000000ULL
1266 #define MCIC_SE_IE 0x0000000080000000ULL
1267
1268 /* validity bits */
1269 #define MCIC_VB_WP 0x0000080000000000ULL
1270 #define MCIC_VB_MS 0x0000040000000000ULL
1271 #define MCIC_VB_PM 0x0000020000000000ULL
1272 #define MCIC_VB_IA 0x0000010000000000ULL
1273 #define MCIC_VB_FA 0x0000008000000000ULL
1274 #define MCIC_VB_VR 0x0000004000000000ULL
1275 #define MCIC_VB_EC 0x0000002000000000ULL
1276 #define MCIC_VB_FP 0x0000001000000000ULL
1277 #define MCIC_VB_GR 0x0000000800000000ULL
1278 #define MCIC_VB_CR 0x0000000400000000ULL
1279 #define MCIC_VB_ST 0x0000000100000000ULL
1280 #define MCIC_VB_AR 0x0000000040000000ULL
1281 #define MCIC_VB_PR 0x0000000000200000ULL
1282 #define MCIC_VB_FC 0x0000000000100000ULL
1283 #define MCIC_VB_CT 0x0000000000020000ULL
1284 #define MCIC_VB_CC 0x0000000000010000ULL
1285
1286 #endif
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