4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu/osdep.h"
22 #include "qemu/qemu-print.h"
23 #include "qemu-common.h"
24 #include "target/arm/idau.h"
25 #include "qemu/module.h"
26 #include "qapi/error.h"
27 #include "qapi/visitor.h"
29 #include "internals.h"
30 #include "exec/exec-all.h"
31 #include "hw/qdev-properties.h"
32 #if !defined(CONFIG_USER_ONLY)
33 #include "hw/loader.h"
34 #include "hw/boards.h"
36 #include "sysemu/sysemu.h"
37 #include "sysemu/tcg.h"
38 #include "sysemu/hw_accel.h"
40 #include "disas/capstone.h"
41 #include "fpu/softfloat.h"
43 static void arm_cpu_set_pc(CPUState
*cs
, vaddr value
)
45 ARMCPU
*cpu
= ARM_CPU(cs
);
46 CPUARMState
*env
= &cpu
->env
;
52 env
->regs
[15] = value
& ~1;
53 env
->thumb
= value
& 1;
57 static void arm_cpu_synchronize_from_tb(CPUState
*cs
, TranslationBlock
*tb
)
59 ARMCPU
*cpu
= ARM_CPU(cs
);
60 CPUARMState
*env
= &cpu
->env
;
63 * It's OK to look at env for the current mode here, because it's
64 * never possible for an AArch64 TB to chain to an AArch32 TB.
69 env
->regs
[15] = tb
->pc
;
73 static bool arm_cpu_has_work(CPUState
*cs
)
75 ARMCPU
*cpu
= ARM_CPU(cs
);
77 return (cpu
->power_state
!= PSCI_OFF
)
78 && cs
->interrupt_request
&
79 (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
80 | CPU_INTERRUPT_VFIQ
| CPU_INTERRUPT_VIRQ
81 | CPU_INTERRUPT_EXITTB
);
84 void arm_register_pre_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
87 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
90 entry
->opaque
= opaque
;
92 QLIST_INSERT_HEAD(&cpu
->pre_el_change_hooks
, entry
, node
);
95 void arm_register_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
98 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
101 entry
->opaque
= opaque
;
103 QLIST_INSERT_HEAD(&cpu
->el_change_hooks
, entry
, node
);
106 static void cp_reg_reset(gpointer key
, gpointer value
, gpointer opaque
)
108 /* Reset a single ARMCPRegInfo register */
109 ARMCPRegInfo
*ri
= value
;
110 ARMCPU
*cpu
= opaque
;
112 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
)) {
117 ri
->resetfn(&cpu
->env
, ri
);
121 /* A zero offset is never possible as it would be regs[0]
122 * so we use it to indicate that reset is being handled elsewhere.
123 * This is basically only used for fields in non-core coprocessors
124 * (like the pxa2xx ones).
126 if (!ri
->fieldoffset
) {
130 if (cpreg_field_is_64bit(ri
)) {
131 CPREG_FIELD64(&cpu
->env
, ri
) = ri
->resetvalue
;
133 CPREG_FIELD32(&cpu
->env
, ri
) = ri
->resetvalue
;
137 static void cp_reg_check_reset(gpointer key
, gpointer value
, gpointer opaque
)
139 /* Purely an assertion check: we've already done reset once,
140 * so now check that running the reset for the cpreg doesn't
141 * change its value. This traps bugs where two different cpregs
142 * both try to reset the same state field but to different values.
144 ARMCPRegInfo
*ri
= value
;
145 ARMCPU
*cpu
= opaque
;
146 uint64_t oldvalue
, newvalue
;
148 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
| ARM_CP_NO_RAW
)) {
152 oldvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
153 cp_reg_reset(key
, value
, opaque
);
154 newvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
155 assert(oldvalue
== newvalue
);
158 /* CPUClass::reset() */
159 static void arm_cpu_reset(CPUState
*s
)
161 ARMCPU
*cpu
= ARM_CPU(s
);
162 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(cpu
);
163 CPUARMState
*env
= &cpu
->env
;
165 acc
->parent_reset(s
);
167 memset(env
, 0, offsetof(CPUARMState
, end_reset_fields
));
169 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_reset
, cpu
);
170 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_check_reset
, cpu
);
172 env
->vfp
.xregs
[ARM_VFP_FPSID
] = cpu
->reset_fpsid
;
173 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = cpu
->isar
.mvfr0
;
174 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = cpu
->isar
.mvfr1
;
175 env
->vfp
.xregs
[ARM_VFP_MVFR2
] = cpu
->isar
.mvfr2
;
177 cpu
->power_state
= cpu
->start_powered_off
? PSCI_OFF
: PSCI_ON
;
178 s
->halted
= cpu
->start_powered_off
;
180 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
181 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
184 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
185 /* 64 bit CPUs always start in 64 bit mode */
187 #if defined(CONFIG_USER_ONLY)
188 env
->pstate
= PSTATE_MODE_EL0t
;
189 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
190 env
->cp15
.sctlr_el
[1] |= SCTLR_UCT
| SCTLR_UCI
| SCTLR_DZE
;
191 /* Enable all PAC keys. */
192 env
->cp15
.sctlr_el
[1] |= (SCTLR_EnIA
| SCTLR_EnIB
|
193 SCTLR_EnDA
| SCTLR_EnDB
);
194 /* Enable all PAC instructions */
195 env
->cp15
.hcr_el2
|= HCR_API
;
196 env
->cp15
.scr_el3
|= SCR_API
;
197 /* and to the FP/Neon instructions */
198 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 2, 3);
199 /* and to the SVE instructions */
200 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 16, 2, 3);
201 env
->cp15
.cptr_el
[3] |= CPTR_EZ
;
202 /* with maximum vector length */
203 env
->vfp
.zcr_el
[1] = cpu_isar_feature(aa64_sve
, cpu
) ?
204 cpu
->sve_max_vq
- 1 : 0;
205 env
->vfp
.zcr_el
[2] = env
->vfp
.zcr_el
[1];
206 env
->vfp
.zcr_el
[3] = env
->vfp
.zcr_el
[1];
208 * Enable TBI0 and TBI1. While the real kernel only enables TBI0,
209 * turning on both here will produce smaller code and otherwise
210 * make no difference to the user-level emulation.
212 env
->cp15
.tcr_el
[1].raw_tcr
= (3ULL << 37);
214 /* Reset into the highest available EL */
215 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
216 env
->pstate
= PSTATE_MODE_EL3h
;
217 } else if (arm_feature(env
, ARM_FEATURE_EL2
)) {
218 env
->pstate
= PSTATE_MODE_EL2h
;
220 env
->pstate
= PSTATE_MODE_EL1h
;
222 env
->pc
= cpu
->rvbar
;
225 #if defined(CONFIG_USER_ONLY)
226 /* Userspace expects access to cp10 and cp11 for FP/Neon */
227 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 4, 0xf);
231 #if defined(CONFIG_USER_ONLY)
232 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
233 /* For user mode we must enable access to coprocessors */
234 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
235 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
236 env
->cp15
.c15_cpar
= 3;
237 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
238 env
->cp15
.c15_cpar
= 1;
243 * If the highest available EL is EL2, AArch32 will start in Hyp
244 * mode; otherwise it starts in SVC. Note that if we start in
245 * AArch64 then these values in the uncached_cpsr will be ignored.
247 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
248 !arm_feature(env
, ARM_FEATURE_EL3
)) {
249 env
->uncached_cpsr
= ARM_CPU_MODE_HYP
;
251 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
;
253 env
->daif
= PSTATE_D
| PSTATE_A
| PSTATE_I
| PSTATE_F
;
255 if (arm_feature(env
, ARM_FEATURE_M
)) {
256 uint32_t initial_msp
; /* Loaded from 0x0 */
257 uint32_t initial_pc
; /* Loaded from 0x4 */
261 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
262 env
->v7m
.secure
= true;
264 /* This bit resets to 0 if security is supported, but 1 if
265 * it is not. The bit is not present in v7M, but we set it
266 * here so we can avoid having to make checks on it conditional
267 * on ARM_FEATURE_V8 (we don't let the guest see the bit).
269 env
->v7m
.aircr
= R_V7M_AIRCR_BFHFNMINS_MASK
;
271 * Set NSACR to indicate "NS access permitted to everything";
272 * this avoids having to have all the tests of it being
273 * conditional on ARM_FEATURE_M_SECURITY. Note also that from
274 * v8.1M the guest-visible value of NSACR in a CPU without the
275 * Security Extension is 0xcff.
277 env
->v7m
.nsacr
= 0xcff;
280 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
281 * that it resets to 1, so QEMU always does that rather than making
282 * it dependent on CPU model. In v8M it is RES1.
284 env
->v7m
.ccr
[M_REG_NS
] = R_V7M_CCR_STKALIGN_MASK
;
285 env
->v7m
.ccr
[M_REG_S
] = R_V7M_CCR_STKALIGN_MASK
;
286 if (arm_feature(env
, ARM_FEATURE_V8
)) {
287 /* in v8M the NONBASETHRDENA bit [0] is RES1 */
288 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
289 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
291 if (!arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
292 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
293 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
296 if (arm_feature(env
, ARM_FEATURE_VFP
)) {
297 env
->v7m
.fpccr
[M_REG_NS
] = R_V7M_FPCCR_ASPEN_MASK
;
298 env
->v7m
.fpccr
[M_REG_S
] = R_V7M_FPCCR_ASPEN_MASK
|
299 R_V7M_FPCCR_LSPEN_MASK
| R_V7M_FPCCR_S_MASK
;
301 /* Unlike A/R profile, M profile defines the reset LR value */
302 env
->regs
[14] = 0xffffffff;
304 env
->v7m
.vecbase
[M_REG_S
] = cpu
->init_svtor
& 0xffffff80;
306 /* Load the initial SP and PC from offset 0 and 4 in the vector table */
307 vecbase
= env
->v7m
.vecbase
[env
->v7m
.secure
];
308 rom
= rom_ptr(vecbase
, 8);
310 /* Address zero is covered by ROM which hasn't yet been
311 * copied into physical memory.
313 initial_msp
= ldl_p(rom
);
314 initial_pc
= ldl_p(rom
+ 4);
316 /* Address zero not covered by a ROM blob, or the ROM blob
317 * is in non-modifiable memory and this is a second reset after
318 * it got copied into memory. In the latter case, rom_ptr
319 * will return a NULL pointer and we should use ldl_phys instead.
321 initial_msp
= ldl_phys(s
->as
, vecbase
);
322 initial_pc
= ldl_phys(s
->as
, vecbase
+ 4);
325 env
->regs
[13] = initial_msp
& 0xFFFFFFFC;
326 env
->regs
[15] = initial_pc
& ~1;
327 env
->thumb
= initial_pc
& 1;
330 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
331 * executing as AArch32 then check if highvecs are enabled and
332 * adjust the PC accordingly.
334 if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
335 env
->regs
[15] = 0xFFFF0000;
338 /* M profile requires that reset clears the exclusive monitor;
339 * A profile does not, but clearing it makes more sense than having it
340 * set with an exclusive access on address zero.
342 arm_clear_exclusive(env
);
344 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
347 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
348 if (cpu
->pmsav7_dregion
> 0) {
349 if (arm_feature(env
, ARM_FEATURE_V8
)) {
350 memset(env
->pmsav8
.rbar
[M_REG_NS
], 0,
351 sizeof(*env
->pmsav8
.rbar
[M_REG_NS
])
352 * cpu
->pmsav7_dregion
);
353 memset(env
->pmsav8
.rlar
[M_REG_NS
], 0,
354 sizeof(*env
->pmsav8
.rlar
[M_REG_NS
])
355 * cpu
->pmsav7_dregion
);
356 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
357 memset(env
->pmsav8
.rbar
[M_REG_S
], 0,
358 sizeof(*env
->pmsav8
.rbar
[M_REG_S
])
359 * cpu
->pmsav7_dregion
);
360 memset(env
->pmsav8
.rlar
[M_REG_S
], 0,
361 sizeof(*env
->pmsav8
.rlar
[M_REG_S
])
362 * cpu
->pmsav7_dregion
);
364 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
365 memset(env
->pmsav7
.drbar
, 0,
366 sizeof(*env
->pmsav7
.drbar
) * cpu
->pmsav7_dregion
);
367 memset(env
->pmsav7
.drsr
, 0,
368 sizeof(*env
->pmsav7
.drsr
) * cpu
->pmsav7_dregion
);
369 memset(env
->pmsav7
.dracr
, 0,
370 sizeof(*env
->pmsav7
.dracr
) * cpu
->pmsav7_dregion
);
373 env
->pmsav7
.rnr
[M_REG_NS
] = 0;
374 env
->pmsav7
.rnr
[M_REG_S
] = 0;
375 env
->pmsav8
.mair0
[M_REG_NS
] = 0;
376 env
->pmsav8
.mair0
[M_REG_S
] = 0;
377 env
->pmsav8
.mair1
[M_REG_NS
] = 0;
378 env
->pmsav8
.mair1
[M_REG_S
] = 0;
381 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
382 if (cpu
->sau_sregion
> 0) {
383 memset(env
->sau
.rbar
, 0, sizeof(*env
->sau
.rbar
) * cpu
->sau_sregion
);
384 memset(env
->sau
.rlar
, 0, sizeof(*env
->sau
.rlar
) * cpu
->sau_sregion
);
387 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
388 * the Cortex-M33 does.
393 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
394 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
395 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
396 set_float_detect_tininess(float_tininess_before_rounding
,
397 &env
->vfp
.fp_status
);
398 set_float_detect_tininess(float_tininess_before_rounding
,
399 &env
->vfp
.standard_fp_status
);
400 set_float_detect_tininess(float_tininess_before_rounding
,
401 &env
->vfp
.fp_status_f16
);
402 #ifndef CONFIG_USER_ONLY
404 kvm_arm_reset_vcpu(cpu
);
408 hw_breakpoint_update_all(cpu
);
409 hw_watchpoint_update_all(cpu
);
410 arm_rebuild_hflags(env
);
413 bool arm_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
415 CPUClass
*cc
= CPU_GET_CLASS(cs
);
416 CPUARMState
*env
= cs
->env_ptr
;
417 uint32_t cur_el
= arm_current_el(env
);
418 bool secure
= arm_is_secure(env
);
423 if (interrupt_request
& CPU_INTERRUPT_FIQ
) {
425 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
426 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
427 cs
->exception_index
= excp_idx
;
428 env
->exception
.target_el
= target_el
;
429 cc
->do_interrupt(cs
);
433 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
435 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
436 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
437 cs
->exception_index
= excp_idx
;
438 env
->exception
.target_el
= target_el
;
439 cc
->do_interrupt(cs
);
443 if (interrupt_request
& CPU_INTERRUPT_VIRQ
) {
444 excp_idx
= EXCP_VIRQ
;
446 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
447 cs
->exception_index
= excp_idx
;
448 env
->exception
.target_el
= target_el
;
449 cc
->do_interrupt(cs
);
453 if (interrupt_request
& CPU_INTERRUPT_VFIQ
) {
454 excp_idx
= EXCP_VFIQ
;
456 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
457 cs
->exception_index
= excp_idx
;
458 env
->exception
.target_el
= target_el
;
459 cc
->do_interrupt(cs
);
467 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
468 static bool arm_v7m_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
470 CPUClass
*cc
= CPU_GET_CLASS(cs
);
471 ARMCPU
*cpu
= ARM_CPU(cs
);
472 CPUARMState
*env
= &cpu
->env
;
475 /* ARMv7-M interrupt masking works differently than -A or -R.
476 * There is no FIQ/IRQ distinction. Instead of I and F bits
477 * masking FIQ and IRQ interrupts, an exception is taken only
478 * if it is higher priority than the current execution priority
479 * (which depends on state like BASEPRI, FAULTMASK and the
480 * currently active exception).
482 if (interrupt_request
& CPU_INTERRUPT_HARD
483 && (armv7m_nvic_can_take_pending_exception(env
->nvic
))) {
484 cs
->exception_index
= EXCP_IRQ
;
485 cc
->do_interrupt(cs
);
492 void arm_cpu_update_virq(ARMCPU
*cpu
)
495 * Update the interrupt level for VIRQ, which is the logical OR of
496 * the HCR_EL2.VI bit and the input line level from the GIC.
498 CPUARMState
*env
= &cpu
->env
;
499 CPUState
*cs
= CPU(cpu
);
501 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VI
) ||
502 (env
->irq_line_state
& CPU_INTERRUPT_VIRQ
);
504 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) != 0)) {
506 cpu_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
508 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
513 void arm_cpu_update_vfiq(ARMCPU
*cpu
)
516 * Update the interrupt level for VFIQ, which is the logical OR of
517 * the HCR_EL2.VF bit and the input line level from the GIC.
519 CPUARMState
*env
= &cpu
->env
;
520 CPUState
*cs
= CPU(cpu
);
522 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VF
) ||
523 (env
->irq_line_state
& CPU_INTERRUPT_VFIQ
);
525 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) != 0)) {
527 cpu_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
529 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
534 #ifndef CONFIG_USER_ONLY
535 static void arm_cpu_set_irq(void *opaque
, int irq
, int level
)
537 ARMCPU
*cpu
= opaque
;
538 CPUARMState
*env
= &cpu
->env
;
539 CPUState
*cs
= CPU(cpu
);
540 static const int mask
[] = {
541 [ARM_CPU_IRQ
] = CPU_INTERRUPT_HARD
,
542 [ARM_CPU_FIQ
] = CPU_INTERRUPT_FIQ
,
543 [ARM_CPU_VIRQ
] = CPU_INTERRUPT_VIRQ
,
544 [ARM_CPU_VFIQ
] = CPU_INTERRUPT_VFIQ
548 env
->irq_line_state
|= mask
[irq
];
550 env
->irq_line_state
&= ~mask
[irq
];
555 assert(arm_feature(env
, ARM_FEATURE_EL2
));
556 arm_cpu_update_virq(cpu
);
559 assert(arm_feature(env
, ARM_FEATURE_EL2
));
560 arm_cpu_update_vfiq(cpu
);
565 cpu_interrupt(cs
, mask
[irq
]);
567 cpu_reset_interrupt(cs
, mask
[irq
]);
571 g_assert_not_reached();
575 static void arm_cpu_kvm_set_irq(void *opaque
, int irq
, int level
)
578 ARMCPU
*cpu
= opaque
;
579 CPUARMState
*env
= &cpu
->env
;
580 CPUState
*cs
= CPU(cpu
);
581 uint32_t linestate_bit
;
586 irq_id
= KVM_ARM_IRQ_CPU_IRQ
;
587 linestate_bit
= CPU_INTERRUPT_HARD
;
590 irq_id
= KVM_ARM_IRQ_CPU_FIQ
;
591 linestate_bit
= CPU_INTERRUPT_FIQ
;
594 g_assert_not_reached();
598 env
->irq_line_state
|= linestate_bit
;
600 env
->irq_line_state
&= ~linestate_bit
;
602 kvm_arm_set_irq(cs
->cpu_index
, KVM_ARM_IRQ_TYPE_CPU
, irq_id
, !!level
);
606 static bool arm_cpu_virtio_is_big_endian(CPUState
*cs
)
608 ARMCPU
*cpu
= ARM_CPU(cs
);
609 CPUARMState
*env
= &cpu
->env
;
611 cpu_synchronize_state(cs
);
612 return arm_cpu_data_is_big_endian(env
);
617 static inline void set_feature(CPUARMState
*env
, int feature
)
619 env
->features
|= 1ULL << feature
;
622 static inline void unset_feature(CPUARMState
*env
, int feature
)
624 env
->features
&= ~(1ULL << feature
);
628 print_insn_thumb1(bfd_vma pc
, disassemble_info
*info
)
630 return print_insn_arm(pc
| 1, info
);
633 static void arm_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
635 ARMCPU
*ac
= ARM_CPU(cpu
);
636 CPUARMState
*env
= &ac
->env
;
640 /* We might not be compiled with the A64 disassembler
641 * because it needs a C++ compiler. Leave print_insn
642 * unset in this case to use the caller default behaviour.
644 #if defined(CONFIG_ARM_A64_DIS)
645 info
->print_insn
= print_insn_arm_a64
;
647 info
->cap_arch
= CS_ARCH_ARM64
;
648 info
->cap_insn_unit
= 4;
649 info
->cap_insn_split
= 4;
653 info
->print_insn
= print_insn_thumb1
;
654 info
->cap_insn_unit
= 2;
655 info
->cap_insn_split
= 4;
656 cap_mode
= CS_MODE_THUMB
;
658 info
->print_insn
= print_insn_arm
;
659 info
->cap_insn_unit
= 4;
660 info
->cap_insn_split
= 4;
661 cap_mode
= CS_MODE_ARM
;
663 if (arm_feature(env
, ARM_FEATURE_V8
)) {
664 cap_mode
|= CS_MODE_V8
;
666 if (arm_feature(env
, ARM_FEATURE_M
)) {
667 cap_mode
|= CS_MODE_MCLASS
;
669 info
->cap_arch
= CS_ARCH_ARM
;
670 info
->cap_mode
= cap_mode
;
673 sctlr_b
= arm_sctlr_b(env
);
674 if (bswap_code(sctlr_b
)) {
675 #ifdef TARGET_WORDS_BIGENDIAN
676 info
->endian
= BFD_ENDIAN_LITTLE
;
678 info
->endian
= BFD_ENDIAN_BIG
;
681 info
->flags
&= ~INSN_ARM_BE32
;
682 #ifndef CONFIG_USER_ONLY
684 info
->flags
|= INSN_ARM_BE32
;
689 #ifdef TARGET_AARCH64
691 static void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
693 ARMCPU
*cpu
= ARM_CPU(cs
);
694 CPUARMState
*env
= &cpu
->env
;
695 uint32_t psr
= pstate_read(env
);
697 int el
= arm_current_el(env
);
698 const char *ns_status
;
700 qemu_fprintf(f
, " PC=%016" PRIx64
" ", env
->pc
);
701 for (i
= 0; i
< 32; i
++) {
703 qemu_fprintf(f
, " SP=%016" PRIx64
"\n", env
->xregs
[i
]);
705 qemu_fprintf(f
, "X%02d=%016" PRIx64
"%s", i
, env
->xregs
[i
],
706 (i
+ 2) % 3 ? " " : "\n");
710 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
711 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
715 qemu_fprintf(f
, "PSTATE=%08x %c%c%c%c %sEL%d%c",
717 psr
& PSTATE_N
? 'N' : '-',
718 psr
& PSTATE_Z
? 'Z' : '-',
719 psr
& PSTATE_C
? 'C' : '-',
720 psr
& PSTATE_V
? 'V' : '-',
723 psr
& PSTATE_SP
? 'h' : 't');
725 if (cpu_isar_feature(aa64_bti
, cpu
)) {
726 qemu_fprintf(f
, " BTYPE=%d", (psr
& PSTATE_BTYPE
) >> 10);
728 if (!(flags
& CPU_DUMP_FPU
)) {
729 qemu_fprintf(f
, "\n");
732 if (fp_exception_el(env
, el
) != 0) {
733 qemu_fprintf(f
, " FPU disabled\n");
736 qemu_fprintf(f
, " FPCR=%08x FPSR=%08x\n",
737 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
739 if (cpu_isar_feature(aa64_sve
, cpu
) && sve_exception_el(env
, el
) == 0) {
740 int j
, zcr_len
= sve_zcr_len_for_el(env
, el
);
742 for (i
= 0; i
<= FFR_PRED_NUM
; i
++) {
744 if (i
== FFR_PRED_NUM
) {
745 qemu_fprintf(f
, "FFR=");
746 /* It's last, so end the line. */
749 qemu_fprintf(f
, "P%02d=", i
);
762 /* More than one quadword per predicate. */
767 for (j
= zcr_len
/ 4; j
>= 0; j
--) {
769 if (j
* 4 + 4 <= zcr_len
+ 1) {
772 digits
= (zcr_len
% 4 + 1) * 4;
774 qemu_fprintf(f
, "%0*" PRIx64
"%s", digits
,
775 env
->vfp
.pregs
[i
].p
[j
],
776 j
? ":" : eol
? "\n" : " ");
780 for (i
= 0; i
< 32; i
++) {
782 qemu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
"%s",
783 i
, env
->vfp
.zregs
[i
].d
[1],
784 env
->vfp
.zregs
[i
].d
[0], i
& 1 ? "\n" : " ");
785 } else if (zcr_len
== 1) {
786 qemu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
787 ":%016" PRIx64
":%016" PRIx64
"\n",
788 i
, env
->vfp
.zregs
[i
].d
[3], env
->vfp
.zregs
[i
].d
[2],
789 env
->vfp
.zregs
[i
].d
[1], env
->vfp
.zregs
[i
].d
[0]);
791 for (j
= zcr_len
; j
>= 0; j
--) {
792 bool odd
= (zcr_len
- j
) % 2 != 0;
794 qemu_fprintf(f
, "Z%02d[%x-%x]=", i
, j
, j
- 1);
797 qemu_fprintf(f
, " [%x-%x]=", j
, j
- 1);
799 qemu_fprintf(f
, " [%x]=", j
);
802 qemu_fprintf(f
, "%016" PRIx64
":%016" PRIx64
"%s",
803 env
->vfp
.zregs
[i
].d
[j
* 2 + 1],
804 env
->vfp
.zregs
[i
].d
[j
* 2],
805 odd
|| j
== 0 ? "\n" : ":");
810 for (i
= 0; i
< 32; i
++) {
811 uint64_t *q
= aa64_vfp_qreg(env
, i
);
812 qemu_fprintf(f
, "Q%02d=%016" PRIx64
":%016" PRIx64
"%s",
813 i
, q
[1], q
[0], (i
& 1 ? "\n" : " "));
820 static inline void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
822 g_assert_not_reached();
827 static void arm_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
829 ARMCPU
*cpu
= ARM_CPU(cs
);
830 CPUARMState
*env
= &cpu
->env
;
834 aarch64_cpu_dump_state(cs
, f
, flags
);
838 for (i
= 0; i
< 16; i
++) {
839 qemu_fprintf(f
, "R%02d=%08x", i
, env
->regs
[i
]);
841 qemu_fprintf(f
, "\n");
843 qemu_fprintf(f
, " ");
847 if (arm_feature(env
, ARM_FEATURE_M
)) {
848 uint32_t xpsr
= xpsr_read(env
);
850 const char *ns_status
= "";
852 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
853 ns_status
= env
->v7m
.secure
? "S " : "NS ";
856 if (xpsr
& XPSR_EXCP
) {
859 if (env
->v7m
.control
[env
->v7m
.secure
] & R_V7M_CONTROL_NPRIV_MASK
) {
860 mode
= "unpriv-thread";
862 mode
= "priv-thread";
866 qemu_fprintf(f
, "XPSR=%08x %c%c%c%c %c %s%s\n",
868 xpsr
& XPSR_N
? 'N' : '-',
869 xpsr
& XPSR_Z
? 'Z' : '-',
870 xpsr
& XPSR_C
? 'C' : '-',
871 xpsr
& XPSR_V
? 'V' : '-',
872 xpsr
& XPSR_T
? 'T' : 'A',
876 uint32_t psr
= cpsr_read(env
);
877 const char *ns_status
= "";
879 if (arm_feature(env
, ARM_FEATURE_EL3
) &&
880 (psr
& CPSR_M
) != ARM_CPU_MODE_MON
) {
881 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
884 qemu_fprintf(f
, "PSR=%08x %c%c%c%c %c %s%s%d\n",
886 psr
& CPSR_N
? 'N' : '-',
887 psr
& CPSR_Z
? 'Z' : '-',
888 psr
& CPSR_C
? 'C' : '-',
889 psr
& CPSR_V
? 'V' : '-',
890 psr
& CPSR_T
? 'T' : 'A',
892 aarch32_mode_name(psr
), (psr
& 0x10) ? 32 : 26);
895 if (flags
& CPU_DUMP_FPU
) {
897 if (arm_feature(env
, ARM_FEATURE_VFP
)) {
900 if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
903 for (i
= 0; i
< numvfpregs
; i
++) {
904 uint64_t v
= *aa32_vfp_dreg(env
, i
);
905 qemu_fprintf(f
, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64
"\n",
907 i
* 2 + 1, (uint32_t)(v
>> 32),
910 qemu_fprintf(f
, "FPSCR: %08x\n", vfp_get_fpscr(env
));
914 uint64_t arm_cpu_mp_affinity(int idx
, uint8_t clustersz
)
916 uint32_t Aff1
= idx
/ clustersz
;
917 uint32_t Aff0
= idx
% clustersz
;
918 return (Aff1
<< ARM_AFF1_SHIFT
) | Aff0
;
921 static void cpreg_hashtable_data_destroy(gpointer data
)
924 * Destroy function for cpu->cp_regs hashtable data entries.
925 * We must free the name string because it was g_strdup()ed in
926 * add_cpreg_to_hashtable(). It's OK to cast away the 'const'
927 * from r->name because we know we definitely allocated it.
929 ARMCPRegInfo
*r
= data
;
931 g_free((void *)r
->name
);
935 static void arm_cpu_initfn(Object
*obj
)
937 ARMCPU
*cpu
= ARM_CPU(obj
);
939 cpu_set_cpustate_pointers(cpu
);
940 cpu
->cp_regs
= g_hash_table_new_full(g_int_hash
, g_int_equal
,
941 g_free
, cpreg_hashtable_data_destroy
);
943 QLIST_INIT(&cpu
->pre_el_change_hooks
);
944 QLIST_INIT(&cpu
->el_change_hooks
);
946 #ifndef CONFIG_USER_ONLY
947 /* Our inbound IRQ and FIQ lines */
949 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
950 * the same interface as non-KVM CPUs.
952 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_kvm_set_irq
, 4);
954 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_set_irq
, 4);
957 qdev_init_gpio_out(DEVICE(cpu
), cpu
->gt_timer_outputs
,
958 ARRAY_SIZE(cpu
->gt_timer_outputs
));
960 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->gicv3_maintenance_interrupt
,
961 "gicv3-maintenance-interrupt", 1);
962 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->pmu_interrupt
,
966 /* DTB consumers generally don't in fact care what the 'compatible'
967 * string is, so always provide some string and trust that a hypothetical
968 * picky DTB consumer will also provide a helpful error message.
970 cpu
->dtb_compatible
= "qemu,unknown";
971 cpu
->psci_version
= 1; /* By default assume PSCI v0.1 */
972 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_NONE
;
975 cpu
->psci_version
= 2; /* TCG implements PSCI 0.2 */
979 static Property arm_cpu_gt_cntfrq_property
=
980 DEFINE_PROP_UINT64("cntfrq", ARMCPU
, gt_cntfrq_hz
,
981 NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
);
983 static Property arm_cpu_reset_cbar_property
=
984 DEFINE_PROP_UINT64("reset-cbar", ARMCPU
, reset_cbar
, 0);
986 static Property arm_cpu_reset_hivecs_property
=
987 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU
, reset_hivecs
, false);
989 static Property arm_cpu_rvbar_property
=
990 DEFINE_PROP_UINT64("rvbar", ARMCPU
, rvbar
, 0);
992 static Property arm_cpu_has_el2_property
=
993 DEFINE_PROP_BOOL("has_el2", ARMCPU
, has_el2
, true);
995 static Property arm_cpu_has_el3_property
=
996 DEFINE_PROP_BOOL("has_el3", ARMCPU
, has_el3
, true);
998 static Property arm_cpu_cfgend_property
=
999 DEFINE_PROP_BOOL("cfgend", ARMCPU
, cfgend
, false);
1001 static Property arm_cpu_has_vfp_property
=
1002 DEFINE_PROP_BOOL("vfp", ARMCPU
, has_vfp
, true);
1004 static Property arm_cpu_has_neon_property
=
1005 DEFINE_PROP_BOOL("neon", ARMCPU
, has_neon
, true);
1007 static Property arm_cpu_has_dsp_property
=
1008 DEFINE_PROP_BOOL("dsp", ARMCPU
, has_dsp
, true);
1010 static Property arm_cpu_has_mpu_property
=
1011 DEFINE_PROP_BOOL("has-mpu", ARMCPU
, has_mpu
, true);
1013 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
1014 * because the CPU initfn will have already set cpu->pmsav7_dregion to
1015 * the right value for that particular CPU type, and we don't want
1016 * to override that with an incorrect constant value.
1018 static Property arm_cpu_pmsav7_dregion_property
=
1019 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU
,
1021 qdev_prop_uint32
, uint32_t);
1023 static bool arm_get_pmu(Object
*obj
, Error
**errp
)
1025 ARMCPU
*cpu
= ARM_CPU(obj
);
1027 return cpu
->has_pmu
;
1030 static void arm_set_pmu(Object
*obj
, bool value
, Error
**errp
)
1032 ARMCPU
*cpu
= ARM_CPU(obj
);
1035 if (kvm_enabled() && !kvm_arm_pmu_supported(CPU(cpu
))) {
1036 error_setg(errp
, "'pmu' feature not supported by KVM on this host");
1039 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
1041 unset_feature(&cpu
->env
, ARM_FEATURE_PMU
);
1043 cpu
->has_pmu
= value
;
1046 static void arm_get_init_svtor(Object
*obj
, Visitor
*v
, const char *name
,
1047 void *opaque
, Error
**errp
)
1049 ARMCPU
*cpu
= ARM_CPU(obj
);
1051 visit_type_uint32(v
, name
, &cpu
->init_svtor
, errp
);
1054 static void arm_set_init_svtor(Object
*obj
, Visitor
*v
, const char *name
,
1055 void *opaque
, Error
**errp
)
1057 ARMCPU
*cpu
= ARM_CPU(obj
);
1059 visit_type_uint32(v
, name
, &cpu
->init_svtor
, errp
);
1062 unsigned int gt_cntfrq_period_ns(ARMCPU
*cpu
)
1065 * The exact approach to calculating guest ticks is:
1067 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz,
1068 * NANOSECONDS_PER_SECOND);
1070 * We don't do that. Rather we intentionally use integer division
1071 * truncation below and in the caller for the conversion of host monotonic
1072 * time to guest ticks to provide the exact inverse for the semantics of
1073 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so
1074 * it loses precision when representing frequencies where
1075 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to
1076 * provide an exact inverse leads to scheduling timers with negative
1077 * periods, which in turn leads to sticky behaviour in the guest.
1079 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor
1080 * cannot become zero.
1082 return NANOSECONDS_PER_SECOND
> cpu
->gt_cntfrq_hz
?
1083 NANOSECONDS_PER_SECOND
/ cpu
->gt_cntfrq_hz
: 1;
1086 void arm_cpu_post_init(Object
*obj
)
1088 ARMCPU
*cpu
= ARM_CPU(obj
);
1090 /* M profile implies PMSA. We have to do this here rather than
1091 * in realize with the other feature-implication checks because
1092 * we look at the PMSA bit to see if we should add some properties.
1094 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1095 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
1097 /* Similarly for the VFP feature bits */
1098 if (arm_feature(&cpu
->env
, ARM_FEATURE_VFP4
)) {
1099 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
1101 if (arm_feature(&cpu
->env
, ARM_FEATURE_VFP3
)) {
1102 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1105 if (arm_feature(&cpu
->env
, ARM_FEATURE_CBAR
) ||
1106 arm_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
)) {
1107 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_cbar_property
);
1110 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1111 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_hivecs_property
);
1114 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1115 qdev_property_add_static(DEVICE(obj
), &arm_cpu_rvbar_property
);
1118 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
1119 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
1120 * prevent "has_el3" from existing on CPUs which cannot support EL3.
1122 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el3_property
);
1124 #ifndef CONFIG_USER_ONLY
1125 object_property_add_link(obj
, "secure-memory",
1127 (Object
**)&cpu
->secure_memory
,
1128 qdev_prop_allow_set_link_before_realize
,
1129 OBJ_PROP_LINK_STRONG
,
1134 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
)) {
1135 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el2_property
);
1138 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMU
)) {
1139 cpu
->has_pmu
= true;
1140 object_property_add_bool(obj
, "pmu", arm_get_pmu
, arm_set_pmu
,
1145 * Allow user to turn off VFP and Neon support, but only for TCG --
1146 * KVM does not currently allow us to lie to the guest about its
1147 * ID/feature registers, so the guest always sees what the host has.
1149 if (arm_feature(&cpu
->env
, ARM_FEATURE_VFP
)) {
1150 cpu
->has_vfp
= true;
1151 if (!kvm_enabled()) {
1152 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_vfp_property
);
1156 if (arm_feature(&cpu
->env
, ARM_FEATURE_NEON
)) {
1157 cpu
->has_neon
= true;
1158 if (!kvm_enabled()) {
1159 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_neon_property
);
1163 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
) &&
1164 arm_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
)) {
1165 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_dsp_property
);
1168 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMSA
)) {
1169 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_mpu_property
);
1170 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1171 qdev_property_add_static(DEVICE(obj
),
1172 &arm_cpu_pmsav7_dregion_property
);
1176 if (arm_feature(&cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
1177 object_property_add_link(obj
, "idau", TYPE_IDAU_INTERFACE
, &cpu
->idau
,
1178 qdev_prop_allow_set_link_before_realize
,
1179 OBJ_PROP_LINK_STRONG
,
1182 * M profile: initial value of the Secure VTOR. We can't just use
1183 * a simple DEFINE_PROP_UINT32 for this because we want to permit
1184 * the property to be set after realize.
1186 object_property_add(obj
, "init-svtor", "uint32",
1187 arm_get_init_svtor
, arm_set_init_svtor
,
1188 NULL
, NULL
, &error_abort
);
1191 qdev_property_add_static(DEVICE(obj
), &arm_cpu_cfgend_property
);
1193 if (arm_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
)) {
1194 qdev_property_add_static(DEVICE(cpu
), &arm_cpu_gt_cntfrq_property
);
1198 static void arm_cpu_finalizefn(Object
*obj
)
1200 ARMCPU
*cpu
= ARM_CPU(obj
);
1201 ARMELChangeHook
*hook
, *next
;
1203 g_hash_table_destroy(cpu
->cp_regs
);
1205 QLIST_FOREACH_SAFE(hook
, &cpu
->pre_el_change_hooks
, node
, next
) {
1206 QLIST_REMOVE(hook
, node
);
1209 QLIST_FOREACH_SAFE(hook
, &cpu
->el_change_hooks
, node
, next
) {
1210 QLIST_REMOVE(hook
, node
);
1213 #ifndef CONFIG_USER_ONLY
1214 if (cpu
->pmu_timer
) {
1215 timer_del(cpu
->pmu_timer
);
1216 timer_deinit(cpu
->pmu_timer
);
1217 timer_free(cpu
->pmu_timer
);
1222 void arm_cpu_finalize_features(ARMCPU
*cpu
, Error
**errp
)
1224 Error
*local_err
= NULL
;
1226 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1227 arm_cpu_sve_finalize(cpu
, &local_err
);
1228 if (local_err
!= NULL
) {
1229 error_propagate(errp
, local_err
);
1235 static void arm_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
1237 CPUState
*cs
= CPU(dev
);
1238 ARMCPU
*cpu
= ARM_CPU(dev
);
1239 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(dev
);
1240 CPUARMState
*env
= &cpu
->env
;
1242 Error
*local_err
= NULL
;
1243 bool no_aa32
= false;
1245 /* If we needed to query the host kernel for the CPU features
1246 * then it's possible that might have failed in the initfn, but
1247 * this is the first point where we can report it.
1249 if (cpu
->host_cpu_probe_failed
) {
1250 if (!kvm_enabled()) {
1251 error_setg(errp
, "The 'host' CPU type can only be used with KVM");
1253 error_setg(errp
, "Failed to retrieve host CPU features");
1258 #ifndef CONFIG_USER_ONLY
1259 /* The NVIC and M-profile CPU are two halves of a single piece of
1260 * hardware; trying to use one without the other is a command line
1261 * error and will result in segfaults if not caught here.
1263 if (arm_feature(env
, ARM_FEATURE_M
)) {
1265 error_setg(errp
, "This board cannot be used with Cortex-M CPUs");
1270 error_setg(errp
, "This board can only be used with Cortex-M CPUs");
1279 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
1280 if (!cpu
->gt_cntfrq_hz
) {
1281 error_setg(errp
, "Invalid CNTFRQ: %"PRId64
"Hz",
1285 scale
= gt_cntfrq_period_ns(cpu
);
1287 scale
= GTIMER_SCALE
;
1290 cpu
->gt_timer
[GTIMER_PHYS
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1291 arm_gt_ptimer_cb
, cpu
);
1292 cpu
->gt_timer
[GTIMER_VIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1293 arm_gt_vtimer_cb
, cpu
);
1294 cpu
->gt_timer
[GTIMER_HYP
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1295 arm_gt_htimer_cb
, cpu
);
1296 cpu
->gt_timer
[GTIMER_SEC
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1297 arm_gt_stimer_cb
, cpu
);
1301 cpu_exec_realizefn(cs
, &local_err
);
1302 if (local_err
!= NULL
) {
1303 error_propagate(errp
, local_err
);
1307 arm_cpu_finalize_features(cpu
, &local_err
);
1308 if (local_err
!= NULL
) {
1309 error_propagate(errp
, local_err
);
1313 if (arm_feature(env
, ARM_FEATURE_AARCH64
) &&
1314 cpu
->has_vfp
!= cpu
->has_neon
) {
1316 * This is an architectural requirement for AArch64; AArch32 is
1317 * more flexible and permits VFP-no-Neon and Neon-no-VFP.
1320 "AArch64 CPUs must have both VFP and Neon or neither");
1324 if (!cpu
->has_vfp
) {
1328 unset_feature(env
, ARM_FEATURE_VFP
);
1329 unset_feature(env
, ARM_FEATURE_VFP3
);
1330 unset_feature(env
, ARM_FEATURE_VFP4
);
1332 t
= cpu
->isar
.id_aa64isar1
;
1333 t
= FIELD_DP64(t
, ID_AA64ISAR1
, JSCVT
, 0);
1334 cpu
->isar
.id_aa64isar1
= t
;
1336 t
= cpu
->isar
.id_aa64pfr0
;
1337 t
= FIELD_DP64(t
, ID_AA64PFR0
, FP
, 0xf);
1338 cpu
->isar
.id_aa64pfr0
= t
;
1340 u
= cpu
->isar
.id_isar6
;
1341 u
= FIELD_DP32(u
, ID_ISAR6
, JSCVT
, 0);
1342 cpu
->isar
.id_isar6
= u
;
1344 u
= cpu
->isar
.mvfr0
;
1345 u
= FIELD_DP32(u
, MVFR0
, FPSP
, 0);
1346 u
= FIELD_DP32(u
, MVFR0
, FPDP
, 0);
1347 u
= FIELD_DP32(u
, MVFR0
, FPTRAP
, 0);
1348 u
= FIELD_DP32(u
, MVFR0
, FPDIVIDE
, 0);
1349 u
= FIELD_DP32(u
, MVFR0
, FPSQRT
, 0);
1350 u
= FIELD_DP32(u
, MVFR0
, FPSHVEC
, 0);
1351 u
= FIELD_DP32(u
, MVFR0
, FPROUND
, 0);
1352 cpu
->isar
.mvfr0
= u
;
1354 u
= cpu
->isar
.mvfr1
;
1355 u
= FIELD_DP32(u
, MVFR1
, FPFTZ
, 0);
1356 u
= FIELD_DP32(u
, MVFR1
, FPDNAN
, 0);
1357 u
= FIELD_DP32(u
, MVFR1
, FPHP
, 0);
1358 cpu
->isar
.mvfr1
= u
;
1360 u
= cpu
->isar
.mvfr2
;
1361 u
= FIELD_DP32(u
, MVFR2
, FPMISC
, 0);
1362 cpu
->isar
.mvfr2
= u
;
1365 if (!cpu
->has_neon
) {
1369 unset_feature(env
, ARM_FEATURE_NEON
);
1371 t
= cpu
->isar
.id_aa64isar0
;
1372 t
= FIELD_DP64(t
, ID_AA64ISAR0
, DP
, 0);
1373 cpu
->isar
.id_aa64isar0
= t
;
1375 t
= cpu
->isar
.id_aa64isar1
;
1376 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FCMA
, 0);
1377 cpu
->isar
.id_aa64isar1
= t
;
1379 t
= cpu
->isar
.id_aa64pfr0
;
1380 t
= FIELD_DP64(t
, ID_AA64PFR0
, ADVSIMD
, 0xf);
1381 cpu
->isar
.id_aa64pfr0
= t
;
1383 u
= cpu
->isar
.id_isar5
;
1384 u
= FIELD_DP32(u
, ID_ISAR5
, RDM
, 0);
1385 u
= FIELD_DP32(u
, ID_ISAR5
, VCMA
, 0);
1386 cpu
->isar
.id_isar5
= u
;
1388 u
= cpu
->isar
.id_isar6
;
1389 u
= FIELD_DP32(u
, ID_ISAR6
, DP
, 0);
1390 u
= FIELD_DP32(u
, ID_ISAR6
, FHM
, 0);
1391 cpu
->isar
.id_isar6
= u
;
1393 u
= cpu
->isar
.mvfr1
;
1394 u
= FIELD_DP32(u
, MVFR1
, SIMDLS
, 0);
1395 u
= FIELD_DP32(u
, MVFR1
, SIMDINT
, 0);
1396 u
= FIELD_DP32(u
, MVFR1
, SIMDSP
, 0);
1397 u
= FIELD_DP32(u
, MVFR1
, SIMDHP
, 0);
1398 u
= FIELD_DP32(u
, MVFR1
, SIMDFMAC
, 0);
1399 cpu
->isar
.mvfr1
= u
;
1401 u
= cpu
->isar
.mvfr2
;
1402 u
= FIELD_DP32(u
, MVFR2
, SIMDMISC
, 0);
1403 cpu
->isar
.mvfr2
= u
;
1406 if (!cpu
->has_neon
&& !cpu
->has_vfp
) {
1410 t
= cpu
->isar
.id_aa64isar0
;
1411 t
= FIELD_DP64(t
, ID_AA64ISAR0
, FHM
, 0);
1412 cpu
->isar
.id_aa64isar0
= t
;
1414 t
= cpu
->isar
.id_aa64isar1
;
1415 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FRINTTS
, 0);
1416 cpu
->isar
.id_aa64isar1
= t
;
1418 u
= cpu
->isar
.mvfr0
;
1419 u
= FIELD_DP32(u
, MVFR0
, SIMDREG
, 0);
1420 cpu
->isar
.mvfr0
= u
;
1423 if (arm_feature(env
, ARM_FEATURE_M
) && !cpu
->has_dsp
) {
1426 unset_feature(env
, ARM_FEATURE_THUMB_DSP
);
1428 u
= cpu
->isar
.id_isar1
;
1429 u
= FIELD_DP32(u
, ID_ISAR1
, EXTEND
, 1);
1430 cpu
->isar
.id_isar1
= u
;
1432 u
= cpu
->isar
.id_isar2
;
1433 u
= FIELD_DP32(u
, ID_ISAR2
, MULTU
, 1);
1434 u
= FIELD_DP32(u
, ID_ISAR2
, MULTS
, 1);
1435 cpu
->isar
.id_isar2
= u
;
1437 u
= cpu
->isar
.id_isar3
;
1438 u
= FIELD_DP32(u
, ID_ISAR3
, SIMD
, 1);
1439 u
= FIELD_DP32(u
, ID_ISAR3
, SATURATE
, 0);
1440 cpu
->isar
.id_isar3
= u
;
1443 /* Some features automatically imply others: */
1444 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1445 if (arm_feature(env
, ARM_FEATURE_M
)) {
1446 set_feature(env
, ARM_FEATURE_V7
);
1448 set_feature(env
, ARM_FEATURE_V7VE
);
1453 * There exist AArch64 cpus without AArch32 support. When KVM
1454 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
1455 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
1456 * As a general principle, we also do not make ID register
1457 * consistency checks anywhere unless using TCG, because only
1458 * for TCG would a consistency-check failure be a QEMU bug.
1460 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1461 no_aa32
= !cpu_isar_feature(aa64_aa32
, cpu
);
1464 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
1465 /* v7 Virtualization Extensions. In real hardware this implies
1466 * EL2 and also the presence of the Security Extensions.
1467 * For QEMU, for backwards-compatibility we implement some
1468 * CPUs or CPU configs which have no actual EL2 or EL3 but do
1469 * include the various other features that V7VE implies.
1470 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
1471 * Security Extensions is ARM_FEATURE_EL3.
1473 assert(!tcg_enabled() || no_aa32
|| cpu_isar_feature(arm_div
, cpu
));
1474 set_feature(env
, ARM_FEATURE_LPAE
);
1475 set_feature(env
, ARM_FEATURE_V7
);
1477 if (arm_feature(env
, ARM_FEATURE_V7
)) {
1478 set_feature(env
, ARM_FEATURE_VAPA
);
1479 set_feature(env
, ARM_FEATURE_THUMB2
);
1480 set_feature(env
, ARM_FEATURE_MPIDR
);
1481 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1482 set_feature(env
, ARM_FEATURE_V6K
);
1484 set_feature(env
, ARM_FEATURE_V6
);
1487 /* Always define VBAR for V7 CPUs even if it doesn't exist in
1488 * non-EL3 configs. This is needed by some legacy boards.
1490 set_feature(env
, ARM_FEATURE_VBAR
);
1492 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
1493 set_feature(env
, ARM_FEATURE_V6
);
1494 set_feature(env
, ARM_FEATURE_MVFR
);
1496 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1497 set_feature(env
, ARM_FEATURE_V5
);
1498 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1499 assert(!tcg_enabled() || no_aa32
|| cpu_isar_feature(jazelle
, cpu
));
1500 set_feature(env
, ARM_FEATURE_AUXCR
);
1503 if (arm_feature(env
, ARM_FEATURE_V5
)) {
1504 set_feature(env
, ARM_FEATURE_V4T
);
1506 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
1507 set_feature(env
, ARM_FEATURE_V7MP
);
1508 set_feature(env
, ARM_FEATURE_PXN
);
1510 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
1511 set_feature(env
, ARM_FEATURE_CBAR
);
1513 if (arm_feature(env
, ARM_FEATURE_THUMB2
) &&
1514 !arm_feature(env
, ARM_FEATURE_M
)) {
1515 set_feature(env
, ARM_FEATURE_THUMB_DSP
);
1519 * We rely on no XScale CPU having VFP so we can use the same bits in the
1520 * TB flags field for VECSTRIDE and XSCALE_CPAR.
1522 assert(!(arm_feature(env
, ARM_FEATURE_VFP
) &&
1523 arm_feature(env
, ARM_FEATURE_XSCALE
)));
1525 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1526 !arm_feature(env
, ARM_FEATURE_M
) &&
1527 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
1528 /* v7VMSA drops support for the old ARMv5 tiny pages, so we
1533 /* For CPUs which might have tiny 1K pages, or which have an
1534 * MPU and might have small region sizes, stick with 1K pages.
1538 if (!set_preferred_target_page_bits(pagebits
)) {
1539 /* This can only ever happen for hotplugging a CPU, or if
1540 * the board code incorrectly creates a CPU which it has
1541 * promised via minimum_page_size that it will not.
1543 error_setg(errp
, "This CPU requires a smaller page size than the "
1548 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
1549 * We don't support setting cluster ID ([16..23]) (known as Aff2
1550 * in later ARM ARM versions), or any of the higher affinity level fields,
1551 * so these bits always RAZ.
1553 if (cpu
->mp_affinity
== ARM64_AFFINITY_INVALID
) {
1554 cpu
->mp_affinity
= arm_cpu_mp_affinity(cs
->cpu_index
,
1555 ARM_DEFAULT_CPUS_PER_CLUSTER
);
1558 if (cpu
->reset_hivecs
) {
1559 cpu
->reset_sctlr
|= (1 << 13);
1563 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1564 cpu
->reset_sctlr
|= SCTLR_EE
;
1566 cpu
->reset_sctlr
|= SCTLR_B
;
1570 if (!cpu
->has_el3
) {
1571 /* If the has_el3 CPU property is disabled then we need to disable the
1574 unset_feature(env
, ARM_FEATURE_EL3
);
1576 /* Disable the security extension feature bits in the processor feature
1577 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
1579 cpu
->id_pfr1
&= ~0xf0;
1580 cpu
->isar
.id_aa64pfr0
&= ~0xf000;
1583 if (!cpu
->has_el2
) {
1584 unset_feature(env
, ARM_FEATURE_EL2
);
1587 if (!cpu
->has_pmu
) {
1588 unset_feature(env
, ARM_FEATURE_PMU
);
1590 if (arm_feature(env
, ARM_FEATURE_PMU
)) {
1593 if (!kvm_enabled()) {
1594 arm_register_pre_el_change_hook(cpu
, &pmu_pre_el_change
, 0);
1595 arm_register_el_change_hook(cpu
, &pmu_post_el_change
, 0);
1598 #ifndef CONFIG_USER_ONLY
1599 cpu
->pmu_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, arm_pmu_timer_cb
,
1603 cpu
->id_aa64dfr0
&= ~0xf00;
1604 cpu
->id_dfr0
&= ~(0xf << 24);
1609 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1610 /* Disable the hypervisor feature bits in the processor feature
1611 * registers if we don't have EL2. These are id_pfr1[15:12] and
1612 * id_aa64pfr0_el1[11:8].
1614 cpu
->isar
.id_aa64pfr0
&= ~0xf00;
1615 cpu
->id_pfr1
&= ~0xf000;
1618 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
1619 * to false or by setting pmsav7-dregion to 0.
1621 if (!cpu
->has_mpu
) {
1622 cpu
->pmsav7_dregion
= 0;
1624 if (cpu
->pmsav7_dregion
== 0) {
1625 cpu
->has_mpu
= false;
1628 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
1629 arm_feature(env
, ARM_FEATURE_V7
)) {
1630 uint32_t nr
= cpu
->pmsav7_dregion
;
1633 error_setg(errp
, "PMSAv7 MPU #regions invalid %" PRIu32
, nr
);
1638 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1640 env
->pmsav8
.rbar
[M_REG_NS
] = g_new0(uint32_t, nr
);
1641 env
->pmsav8
.rlar
[M_REG_NS
] = g_new0(uint32_t, nr
);
1642 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1643 env
->pmsav8
.rbar
[M_REG_S
] = g_new0(uint32_t, nr
);
1644 env
->pmsav8
.rlar
[M_REG_S
] = g_new0(uint32_t, nr
);
1647 env
->pmsav7
.drbar
= g_new0(uint32_t, nr
);
1648 env
->pmsav7
.drsr
= g_new0(uint32_t, nr
);
1649 env
->pmsav7
.dracr
= g_new0(uint32_t, nr
);
1654 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1655 uint32_t nr
= cpu
->sau_sregion
;
1658 error_setg(errp
, "v8M SAU #regions invalid %" PRIu32
, nr
);
1663 env
->sau
.rbar
= g_new0(uint32_t, nr
);
1664 env
->sau
.rlar
= g_new0(uint32_t, nr
);
1668 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
1669 set_feature(env
, ARM_FEATURE_VBAR
);
1672 register_cp_regs_for_features(cpu
);
1673 arm_cpu_register_gdb_regs_for_features(cpu
);
1675 init_cpreg_list(cpu
);
1677 #ifndef CONFIG_USER_ONLY
1678 MachineState
*ms
= MACHINE(qdev_get_machine());
1679 unsigned int smp_cpus
= ms
->smp
.cpus
;
1681 if (cpu
->has_el3
|| arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1684 if (!cpu
->secure_memory
) {
1685 cpu
->secure_memory
= cs
->memory
;
1687 cpu_address_space_init(cs
, ARMASIdx_S
, "cpu-secure-memory",
1688 cpu
->secure_memory
);
1692 cpu_address_space_init(cs
, ARMASIdx_NS
, "cpu-memory", cs
->memory
);
1694 /* No core_count specified, default to smp_cpus. */
1695 if (cpu
->core_count
== -1) {
1696 cpu
->core_count
= smp_cpus
;
1703 acc
->parent_realize(dev
, errp
);
1706 static ObjectClass
*arm_cpu_class_by_name(const char *cpu_model
)
1711 const char *cpunamestr
;
1713 cpuname
= g_strsplit(cpu_model
, ",", 1);
1714 cpunamestr
= cpuname
[0];
1715 #ifdef CONFIG_USER_ONLY
1716 /* For backwards compatibility usermode emulation allows "-cpu any",
1717 * which has the same semantics as "-cpu max".
1719 if (!strcmp(cpunamestr
, "any")) {
1723 typename
= g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr
);
1724 oc
= object_class_by_name(typename
);
1725 g_strfreev(cpuname
);
1727 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_ARM_CPU
) ||
1728 object_class_is_abstract(oc
)) {
1734 /* CPU models. These are not needed for the AArch64 linux-user build. */
1735 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1737 static void arm926_initfn(Object
*obj
)
1739 ARMCPU
*cpu
= ARM_CPU(obj
);
1741 cpu
->dtb_compatible
= "arm,arm926";
1742 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1743 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1744 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1745 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
1746 cpu
->midr
= 0x41069265;
1747 cpu
->reset_fpsid
= 0x41011090;
1748 cpu
->ctr
= 0x1dd20d2;
1749 cpu
->reset_sctlr
= 0x00090078;
1752 * ARMv5 does not have the ID_ISAR registers, but we can still
1753 * set the field to indicate Jazelle support within QEMU.
1755 cpu
->isar
.id_isar1
= FIELD_DP32(cpu
->isar
.id_isar1
, ID_ISAR1
, JAZELLE
, 1);
1757 * Similarly, we need to set MVFR0 fields to enable double precision
1758 * and short vector support even though ARMv5 doesn't have this register.
1760 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPSHVEC
, 1);
1761 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPDP
, 1);
1764 static void arm946_initfn(Object
*obj
)
1766 ARMCPU
*cpu
= ARM_CPU(obj
);
1768 cpu
->dtb_compatible
= "arm,arm946";
1769 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1770 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
1771 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1772 cpu
->midr
= 0x41059461;
1773 cpu
->ctr
= 0x0f004006;
1774 cpu
->reset_sctlr
= 0x00000078;
1777 static void arm1026_initfn(Object
*obj
)
1779 ARMCPU
*cpu
= ARM_CPU(obj
);
1781 cpu
->dtb_compatible
= "arm,arm1026";
1782 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1783 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1784 set_feature(&cpu
->env
, ARM_FEATURE_AUXCR
);
1785 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1786 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
1787 cpu
->midr
= 0x4106a262;
1788 cpu
->reset_fpsid
= 0x410110a0;
1789 cpu
->ctr
= 0x1dd20d2;
1790 cpu
->reset_sctlr
= 0x00090078;
1791 cpu
->reset_auxcr
= 1;
1794 * ARMv5 does not have the ID_ISAR registers, but we can still
1795 * set the field to indicate Jazelle support within QEMU.
1797 cpu
->isar
.id_isar1
= FIELD_DP32(cpu
->isar
.id_isar1
, ID_ISAR1
, JAZELLE
, 1);
1799 * Similarly, we need to set MVFR0 fields to enable double precision
1800 * and short vector support even though ARMv5 doesn't have this register.
1802 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPSHVEC
, 1);
1803 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPDP
, 1);
1806 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
1807 ARMCPRegInfo ifar
= {
1808 .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
1810 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifar_ns
),
1813 define_one_arm_cp_reg(cpu
, &ifar
);
1817 static void arm1136_r2_initfn(Object
*obj
)
1819 ARMCPU
*cpu
= ARM_CPU(obj
);
1820 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
1821 * older core than plain "arm1136". In particular this does not
1822 * have the v6K features.
1823 * These ID register values are correct for 1136 but may be wrong
1824 * for 1136_r2 (in particular r0p2 does not actually implement most
1825 * of the ID registers).
1828 cpu
->dtb_compatible
= "arm,arm1136";
1829 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
1830 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1831 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1832 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
1833 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
1834 cpu
->midr
= 0x4107b362;
1835 cpu
->reset_fpsid
= 0x410120b4;
1836 cpu
->isar
.mvfr0
= 0x11111111;
1837 cpu
->isar
.mvfr1
= 0x00000000;
1838 cpu
->ctr
= 0x1dd20d2;
1839 cpu
->reset_sctlr
= 0x00050078;
1840 cpu
->id_pfr0
= 0x111;
1844 cpu
->id_mmfr0
= 0x01130003;
1845 cpu
->id_mmfr1
= 0x10030302;
1846 cpu
->id_mmfr2
= 0x01222110;
1847 cpu
->isar
.id_isar0
= 0x00140011;
1848 cpu
->isar
.id_isar1
= 0x12002111;
1849 cpu
->isar
.id_isar2
= 0x11231111;
1850 cpu
->isar
.id_isar3
= 0x01102131;
1851 cpu
->isar
.id_isar4
= 0x141;
1852 cpu
->reset_auxcr
= 7;
1855 static void arm1136_initfn(Object
*obj
)
1857 ARMCPU
*cpu
= ARM_CPU(obj
);
1859 cpu
->dtb_compatible
= "arm,arm1136";
1860 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
1861 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
1862 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1863 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1864 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
1865 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
1866 cpu
->midr
= 0x4117b363;
1867 cpu
->reset_fpsid
= 0x410120b4;
1868 cpu
->isar
.mvfr0
= 0x11111111;
1869 cpu
->isar
.mvfr1
= 0x00000000;
1870 cpu
->ctr
= 0x1dd20d2;
1871 cpu
->reset_sctlr
= 0x00050078;
1872 cpu
->id_pfr0
= 0x111;
1876 cpu
->id_mmfr0
= 0x01130003;
1877 cpu
->id_mmfr1
= 0x10030302;
1878 cpu
->id_mmfr2
= 0x01222110;
1879 cpu
->isar
.id_isar0
= 0x00140011;
1880 cpu
->isar
.id_isar1
= 0x12002111;
1881 cpu
->isar
.id_isar2
= 0x11231111;
1882 cpu
->isar
.id_isar3
= 0x01102131;
1883 cpu
->isar
.id_isar4
= 0x141;
1884 cpu
->reset_auxcr
= 7;
1887 static void arm1176_initfn(Object
*obj
)
1889 ARMCPU
*cpu
= ARM_CPU(obj
);
1891 cpu
->dtb_compatible
= "arm,arm1176";
1892 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
1893 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1894 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
1895 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1896 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
1897 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
1898 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1899 cpu
->midr
= 0x410fb767;
1900 cpu
->reset_fpsid
= 0x410120b5;
1901 cpu
->isar
.mvfr0
= 0x11111111;
1902 cpu
->isar
.mvfr1
= 0x00000000;
1903 cpu
->ctr
= 0x1dd20d2;
1904 cpu
->reset_sctlr
= 0x00050078;
1905 cpu
->id_pfr0
= 0x111;
1906 cpu
->id_pfr1
= 0x11;
1907 cpu
->id_dfr0
= 0x33;
1909 cpu
->id_mmfr0
= 0x01130003;
1910 cpu
->id_mmfr1
= 0x10030302;
1911 cpu
->id_mmfr2
= 0x01222100;
1912 cpu
->isar
.id_isar0
= 0x0140011;
1913 cpu
->isar
.id_isar1
= 0x12002111;
1914 cpu
->isar
.id_isar2
= 0x11231121;
1915 cpu
->isar
.id_isar3
= 0x01102131;
1916 cpu
->isar
.id_isar4
= 0x01141;
1917 cpu
->reset_auxcr
= 7;
1920 static void arm11mpcore_initfn(Object
*obj
)
1922 ARMCPU
*cpu
= ARM_CPU(obj
);
1924 cpu
->dtb_compatible
= "arm,arm11mpcore";
1925 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
1926 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1927 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
1928 set_feature(&cpu
->env
, ARM_FEATURE_MPIDR
);
1929 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1930 cpu
->midr
= 0x410fb022;
1931 cpu
->reset_fpsid
= 0x410120b4;
1932 cpu
->isar
.mvfr0
= 0x11111111;
1933 cpu
->isar
.mvfr1
= 0x00000000;
1934 cpu
->ctr
= 0x1d192992; /* 32K icache 32K dcache */
1935 cpu
->id_pfr0
= 0x111;
1939 cpu
->id_mmfr0
= 0x01100103;
1940 cpu
->id_mmfr1
= 0x10020302;
1941 cpu
->id_mmfr2
= 0x01222000;
1942 cpu
->isar
.id_isar0
= 0x00100011;
1943 cpu
->isar
.id_isar1
= 0x12002111;
1944 cpu
->isar
.id_isar2
= 0x11221011;
1945 cpu
->isar
.id_isar3
= 0x01102131;
1946 cpu
->isar
.id_isar4
= 0x141;
1947 cpu
->reset_auxcr
= 1;
1950 static void cortex_m0_initfn(Object
*obj
)
1952 ARMCPU
*cpu
= ARM_CPU(obj
);
1953 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
1954 set_feature(&cpu
->env
, ARM_FEATURE_M
);
1956 cpu
->midr
= 0x410cc200;
1959 static void cortex_m3_initfn(Object
*obj
)
1961 ARMCPU
*cpu
= ARM_CPU(obj
);
1962 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1963 set_feature(&cpu
->env
, ARM_FEATURE_M
);
1964 set_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
);
1965 cpu
->midr
= 0x410fc231;
1966 cpu
->pmsav7_dregion
= 8;
1967 cpu
->id_pfr0
= 0x00000030;
1968 cpu
->id_pfr1
= 0x00000200;
1969 cpu
->id_dfr0
= 0x00100000;
1970 cpu
->id_afr0
= 0x00000000;
1971 cpu
->id_mmfr0
= 0x00000030;
1972 cpu
->id_mmfr1
= 0x00000000;
1973 cpu
->id_mmfr2
= 0x00000000;
1974 cpu
->id_mmfr3
= 0x00000000;
1975 cpu
->isar
.id_isar0
= 0x01141110;
1976 cpu
->isar
.id_isar1
= 0x02111000;
1977 cpu
->isar
.id_isar2
= 0x21112231;
1978 cpu
->isar
.id_isar3
= 0x01111110;
1979 cpu
->isar
.id_isar4
= 0x01310102;
1980 cpu
->isar
.id_isar5
= 0x00000000;
1981 cpu
->isar
.id_isar6
= 0x00000000;
1984 static void cortex_m4_initfn(Object
*obj
)
1986 ARMCPU
*cpu
= ARM_CPU(obj
);
1988 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1989 set_feature(&cpu
->env
, ARM_FEATURE_M
);
1990 set_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
);
1991 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
);
1992 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1993 cpu
->midr
= 0x410fc240; /* r0p0 */
1994 cpu
->pmsav7_dregion
= 8;
1995 cpu
->isar
.mvfr0
= 0x10110021;
1996 cpu
->isar
.mvfr1
= 0x11000011;
1997 cpu
->isar
.mvfr2
= 0x00000000;
1998 cpu
->id_pfr0
= 0x00000030;
1999 cpu
->id_pfr1
= 0x00000200;
2000 cpu
->id_dfr0
= 0x00100000;
2001 cpu
->id_afr0
= 0x00000000;
2002 cpu
->id_mmfr0
= 0x00000030;
2003 cpu
->id_mmfr1
= 0x00000000;
2004 cpu
->id_mmfr2
= 0x00000000;
2005 cpu
->id_mmfr3
= 0x00000000;
2006 cpu
->isar
.id_isar0
= 0x01141110;
2007 cpu
->isar
.id_isar1
= 0x02111000;
2008 cpu
->isar
.id_isar2
= 0x21112231;
2009 cpu
->isar
.id_isar3
= 0x01111110;
2010 cpu
->isar
.id_isar4
= 0x01310102;
2011 cpu
->isar
.id_isar5
= 0x00000000;
2012 cpu
->isar
.id_isar6
= 0x00000000;
2015 static void cortex_m7_initfn(Object
*obj
)
2017 ARMCPU
*cpu
= ARM_CPU(obj
);
2019 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
2020 set_feature(&cpu
->env
, ARM_FEATURE_M
);
2021 set_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
);
2022 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
);
2023 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
2024 cpu
->midr
= 0x411fc272; /* r1p2 */
2025 cpu
->pmsav7_dregion
= 8;
2026 cpu
->isar
.mvfr0
= 0x10110221;
2027 cpu
->isar
.mvfr1
= 0x12000011;
2028 cpu
->isar
.mvfr2
= 0x00000040;
2029 cpu
->id_pfr0
= 0x00000030;
2030 cpu
->id_pfr1
= 0x00000200;
2031 cpu
->id_dfr0
= 0x00100000;
2032 cpu
->id_afr0
= 0x00000000;
2033 cpu
->id_mmfr0
= 0x00100030;
2034 cpu
->id_mmfr1
= 0x00000000;
2035 cpu
->id_mmfr2
= 0x01000000;
2036 cpu
->id_mmfr3
= 0x00000000;
2037 cpu
->isar
.id_isar0
= 0x01101110;
2038 cpu
->isar
.id_isar1
= 0x02112000;
2039 cpu
->isar
.id_isar2
= 0x20232231;
2040 cpu
->isar
.id_isar3
= 0x01111131;
2041 cpu
->isar
.id_isar4
= 0x01310132;
2042 cpu
->isar
.id_isar5
= 0x00000000;
2043 cpu
->isar
.id_isar6
= 0x00000000;
2046 static void cortex_m33_initfn(Object
*obj
)
2048 ARMCPU
*cpu
= ARM_CPU(obj
);
2050 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
2051 set_feature(&cpu
->env
, ARM_FEATURE_M
);
2052 set_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
);
2053 set_feature(&cpu
->env
, ARM_FEATURE_M_SECURITY
);
2054 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
);
2055 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
2056 cpu
->midr
= 0x410fd213; /* r0p3 */
2057 cpu
->pmsav7_dregion
= 16;
2058 cpu
->sau_sregion
= 8;
2059 cpu
->isar
.mvfr0
= 0x10110021;
2060 cpu
->isar
.mvfr1
= 0x11000011;
2061 cpu
->isar
.mvfr2
= 0x00000040;
2062 cpu
->id_pfr0
= 0x00000030;
2063 cpu
->id_pfr1
= 0x00000210;
2064 cpu
->id_dfr0
= 0x00200000;
2065 cpu
->id_afr0
= 0x00000000;
2066 cpu
->id_mmfr0
= 0x00101F40;
2067 cpu
->id_mmfr1
= 0x00000000;
2068 cpu
->id_mmfr2
= 0x01000000;
2069 cpu
->id_mmfr3
= 0x00000000;
2070 cpu
->isar
.id_isar0
= 0x01101110;
2071 cpu
->isar
.id_isar1
= 0x02212000;
2072 cpu
->isar
.id_isar2
= 0x20232232;
2073 cpu
->isar
.id_isar3
= 0x01111131;
2074 cpu
->isar
.id_isar4
= 0x01310132;
2075 cpu
->isar
.id_isar5
= 0x00000000;
2076 cpu
->isar
.id_isar6
= 0x00000000;
2077 cpu
->clidr
= 0x00000000;
2078 cpu
->ctr
= 0x8000c000;
2081 static void arm_v7m_class_init(ObjectClass
*oc
, void *data
)
2083 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2084 CPUClass
*cc
= CPU_CLASS(oc
);
2087 #ifndef CONFIG_USER_ONLY
2088 cc
->do_interrupt
= arm_v7m_cpu_do_interrupt
;
2091 cc
->cpu_exec_interrupt
= arm_v7m_cpu_exec_interrupt
;
2094 static const ARMCPRegInfo cortexr5_cp_reginfo
[] = {
2095 /* Dummy the TCM region regs for the moment */
2096 { .name
= "ATCM", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
2097 .access
= PL1_RW
, .type
= ARM_CP_CONST
},
2098 { .name
= "BTCM", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
2099 .access
= PL1_RW
, .type
= ARM_CP_CONST
},
2100 { .name
= "DCACHE_INVAL", .cp
= 15, .opc1
= 0, .crn
= 15, .crm
= 5,
2101 .opc2
= 0, .access
= PL1_W
, .type
= ARM_CP_NOP
},
2105 static void cortex_r5_initfn(Object
*obj
)
2107 ARMCPU
*cpu
= ARM_CPU(obj
);
2109 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
2110 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
2111 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
2112 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
2113 cpu
->midr
= 0x411fc153; /* r1p3 */
2114 cpu
->id_pfr0
= 0x0131;
2115 cpu
->id_pfr1
= 0x001;
2116 cpu
->id_dfr0
= 0x010400;
2118 cpu
->id_mmfr0
= 0x0210030;
2119 cpu
->id_mmfr1
= 0x00000000;
2120 cpu
->id_mmfr2
= 0x01200000;
2121 cpu
->id_mmfr3
= 0x0211;
2122 cpu
->isar
.id_isar0
= 0x02101111;
2123 cpu
->isar
.id_isar1
= 0x13112111;
2124 cpu
->isar
.id_isar2
= 0x21232141;
2125 cpu
->isar
.id_isar3
= 0x01112131;
2126 cpu
->isar
.id_isar4
= 0x0010142;
2127 cpu
->isar
.id_isar5
= 0x0;
2128 cpu
->isar
.id_isar6
= 0x0;
2129 cpu
->mp_is_up
= true;
2130 cpu
->pmsav7_dregion
= 16;
2131 define_arm_cp_regs(cpu
, cortexr5_cp_reginfo
);
2134 static void cortex_r5f_initfn(Object
*obj
)
2136 ARMCPU
*cpu
= ARM_CPU(obj
);
2138 cortex_r5_initfn(obj
);
2139 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
2140 cpu
->isar
.mvfr0
= 0x10110221;
2141 cpu
->isar
.mvfr1
= 0x00000011;
2144 static const ARMCPRegInfo cortexa8_cp_reginfo
[] = {
2145 { .name
= "L2LOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 0,
2146 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2147 { .name
= "L2AUXCR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
2148 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2152 static void cortex_a8_initfn(Object
*obj
)
2154 ARMCPU
*cpu
= ARM_CPU(obj
);
2156 cpu
->dtb_compatible
= "arm,cortex-a8";
2157 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
2158 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
2159 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
2160 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
2161 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
2162 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
2163 cpu
->midr
= 0x410fc080;
2164 cpu
->reset_fpsid
= 0x410330c0;
2165 cpu
->isar
.mvfr0
= 0x11110222;
2166 cpu
->isar
.mvfr1
= 0x00011111;
2167 cpu
->ctr
= 0x82048004;
2168 cpu
->reset_sctlr
= 0x00c50078;
2169 cpu
->id_pfr0
= 0x1031;
2170 cpu
->id_pfr1
= 0x11;
2171 cpu
->id_dfr0
= 0x400;
2173 cpu
->id_mmfr0
= 0x31100003;
2174 cpu
->id_mmfr1
= 0x20000000;
2175 cpu
->id_mmfr2
= 0x01202000;
2176 cpu
->id_mmfr3
= 0x11;
2177 cpu
->isar
.id_isar0
= 0x00101111;
2178 cpu
->isar
.id_isar1
= 0x12112111;
2179 cpu
->isar
.id_isar2
= 0x21232031;
2180 cpu
->isar
.id_isar3
= 0x11112131;
2181 cpu
->isar
.id_isar4
= 0x00111142;
2182 cpu
->dbgdidr
= 0x15141000;
2183 cpu
->clidr
= (1 << 27) | (2 << 24) | 3;
2184 cpu
->ccsidr
[0] = 0xe007e01a; /* 16k L1 dcache. */
2185 cpu
->ccsidr
[1] = 0x2007e01a; /* 16k L1 icache. */
2186 cpu
->ccsidr
[2] = 0xf0000000; /* No L2 icache. */
2187 cpu
->reset_auxcr
= 2;
2188 define_arm_cp_regs(cpu
, cortexa8_cp_reginfo
);
2191 static const ARMCPRegInfo cortexa9_cp_reginfo
[] = {
2192 /* power_control should be set to maximum latency. Again,
2193 * default to 0 and set by private hook
2195 { .name
= "A9_PWRCTL", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
2196 .access
= PL1_RW
, .resetvalue
= 0,
2197 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_control
) },
2198 { .name
= "A9_DIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 1,
2199 .access
= PL1_RW
, .resetvalue
= 0,
2200 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_diagnostic
) },
2201 { .name
= "A9_PWRDIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 2,
2202 .access
= PL1_RW
, .resetvalue
= 0,
2203 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_diagnostic
) },
2204 { .name
= "NEONBUSY", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
2205 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
2206 /* TLB lockdown control */
2207 { .name
= "TLB_LOCKR", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 2,
2208 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
2209 { .name
= "TLB_LOCKW", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 4,
2210 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
2211 { .name
= "TLB_VA", .cp
= 15, .crn
= 15, .crm
= 5, .opc1
= 5, .opc2
= 2,
2212 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
2213 { .name
= "TLB_PA", .cp
= 15, .crn
= 15, .crm
= 6, .opc1
= 5, .opc2
= 2,
2214 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
2215 { .name
= "TLB_ATTR", .cp
= 15, .crn
= 15, .crm
= 7, .opc1
= 5, .opc2
= 2,
2216 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
2220 static void cortex_a9_initfn(Object
*obj
)
2222 ARMCPU
*cpu
= ARM_CPU(obj
);
2224 cpu
->dtb_compatible
= "arm,cortex-a9";
2225 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
2226 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
2227 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
2228 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
2229 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
2230 /* Note that A9 supports the MP extensions even for
2231 * A9UP and single-core A9MP (which are both different
2232 * and valid configurations; we don't model A9UP).
2234 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
2235 set_feature(&cpu
->env
, ARM_FEATURE_CBAR
);
2236 cpu
->midr
= 0x410fc090;
2237 cpu
->reset_fpsid
= 0x41033090;
2238 cpu
->isar
.mvfr0
= 0x11110222;
2239 cpu
->isar
.mvfr1
= 0x01111111;
2240 cpu
->ctr
= 0x80038003;
2241 cpu
->reset_sctlr
= 0x00c50078;
2242 cpu
->id_pfr0
= 0x1031;
2243 cpu
->id_pfr1
= 0x11;
2244 cpu
->id_dfr0
= 0x000;
2246 cpu
->id_mmfr0
= 0x00100103;
2247 cpu
->id_mmfr1
= 0x20000000;
2248 cpu
->id_mmfr2
= 0x01230000;
2249 cpu
->id_mmfr3
= 0x00002111;
2250 cpu
->isar
.id_isar0
= 0x00101111;
2251 cpu
->isar
.id_isar1
= 0x13112111;
2252 cpu
->isar
.id_isar2
= 0x21232041;
2253 cpu
->isar
.id_isar3
= 0x11112131;
2254 cpu
->isar
.id_isar4
= 0x00111142;
2255 cpu
->dbgdidr
= 0x35141000;
2256 cpu
->clidr
= (1 << 27) | (1 << 24) | 3;
2257 cpu
->ccsidr
[0] = 0xe00fe019; /* 16k L1 dcache. */
2258 cpu
->ccsidr
[1] = 0x200fe019; /* 16k L1 icache. */
2259 define_arm_cp_regs(cpu
, cortexa9_cp_reginfo
);
2262 #ifndef CONFIG_USER_ONLY
2263 static uint64_t a15_l2ctlr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2265 MachineState
*ms
= MACHINE(qdev_get_machine());
2267 /* Linux wants the number of processors from here.
2268 * Might as well set the interrupt-controller bit too.
2270 return ((ms
->smp
.cpus
- 1) << 24) | (1 << 23);
2274 static const ARMCPRegInfo cortexa15_cp_reginfo
[] = {
2275 #ifndef CONFIG_USER_ONLY
2276 { .name
= "L2CTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
2277 .access
= PL1_RW
, .resetvalue
= 0, .readfn
= a15_l2ctlr_read
,
2278 .writefn
= arm_cp_write_ignore
, },
2280 { .name
= "L2ECTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 3,
2281 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2285 static void cortex_a7_initfn(Object
*obj
)
2287 ARMCPU
*cpu
= ARM_CPU(obj
);
2289 cpu
->dtb_compatible
= "arm,cortex-a7";
2290 set_feature(&cpu
->env
, ARM_FEATURE_V7VE
);
2291 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
2292 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
2293 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
2294 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
2295 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
2296 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
2297 set_feature(&cpu
->env
, ARM_FEATURE_EL2
);
2298 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
2299 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
2300 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A7
;
2301 cpu
->midr
= 0x410fc075;
2302 cpu
->reset_fpsid
= 0x41023075;
2303 cpu
->isar
.mvfr0
= 0x10110222;
2304 cpu
->isar
.mvfr1
= 0x11111111;
2305 cpu
->ctr
= 0x84448003;
2306 cpu
->reset_sctlr
= 0x00c50078;
2307 cpu
->id_pfr0
= 0x00001131;
2308 cpu
->id_pfr1
= 0x00011011;
2309 cpu
->id_dfr0
= 0x02010555;
2310 cpu
->id_afr0
= 0x00000000;
2311 cpu
->id_mmfr0
= 0x10101105;
2312 cpu
->id_mmfr1
= 0x40000000;
2313 cpu
->id_mmfr2
= 0x01240000;
2314 cpu
->id_mmfr3
= 0x02102211;
2315 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
2316 * table 4-41 gives 0x02101110, which includes the arm div insns.
2318 cpu
->isar
.id_isar0
= 0x02101110;
2319 cpu
->isar
.id_isar1
= 0x13112111;
2320 cpu
->isar
.id_isar2
= 0x21232041;
2321 cpu
->isar
.id_isar3
= 0x11112131;
2322 cpu
->isar
.id_isar4
= 0x10011142;
2323 cpu
->dbgdidr
= 0x3515f005;
2324 cpu
->clidr
= 0x0a200023;
2325 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
2326 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
2327 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
2328 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
); /* Same as A15 */
2331 static void cortex_a15_initfn(Object
*obj
)
2333 ARMCPU
*cpu
= ARM_CPU(obj
);
2335 cpu
->dtb_compatible
= "arm,cortex-a15";
2336 set_feature(&cpu
->env
, ARM_FEATURE_V7VE
);
2337 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
2338 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
2339 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
2340 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
2341 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
2342 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
2343 set_feature(&cpu
->env
, ARM_FEATURE_EL2
);
2344 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
2345 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
2346 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A15
;
2347 cpu
->midr
= 0x412fc0f1;
2348 cpu
->reset_fpsid
= 0x410430f0;
2349 cpu
->isar
.mvfr0
= 0x10110222;
2350 cpu
->isar
.mvfr1
= 0x11111111;
2351 cpu
->ctr
= 0x8444c004;
2352 cpu
->reset_sctlr
= 0x00c50078;
2353 cpu
->id_pfr0
= 0x00001131;
2354 cpu
->id_pfr1
= 0x00011011;
2355 cpu
->id_dfr0
= 0x02010555;
2356 cpu
->id_afr0
= 0x00000000;
2357 cpu
->id_mmfr0
= 0x10201105;
2358 cpu
->id_mmfr1
= 0x20000000;
2359 cpu
->id_mmfr2
= 0x01240000;
2360 cpu
->id_mmfr3
= 0x02102211;
2361 cpu
->isar
.id_isar0
= 0x02101110;
2362 cpu
->isar
.id_isar1
= 0x13112111;
2363 cpu
->isar
.id_isar2
= 0x21232041;
2364 cpu
->isar
.id_isar3
= 0x11112131;
2365 cpu
->isar
.id_isar4
= 0x10011142;
2366 cpu
->dbgdidr
= 0x3515f021;
2367 cpu
->clidr
= 0x0a200023;
2368 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
2369 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
2370 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
2371 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
);
2374 static void ti925t_initfn(Object
*obj
)
2376 ARMCPU
*cpu
= ARM_CPU(obj
);
2377 set_feature(&cpu
->env
, ARM_FEATURE_V4T
);
2378 set_feature(&cpu
->env
, ARM_FEATURE_OMAPCP
);
2379 cpu
->midr
= ARM_CPUID_TI925T
;
2380 cpu
->ctr
= 0x5109149;
2381 cpu
->reset_sctlr
= 0x00000070;
2384 static void sa1100_initfn(Object
*obj
)
2386 ARMCPU
*cpu
= ARM_CPU(obj
);
2388 cpu
->dtb_compatible
= "intel,sa1100";
2389 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
2390 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
2391 cpu
->midr
= 0x4401A11B;
2392 cpu
->reset_sctlr
= 0x00000070;
2395 static void sa1110_initfn(Object
*obj
)
2397 ARMCPU
*cpu
= ARM_CPU(obj
);
2398 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
2399 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
2400 cpu
->midr
= 0x6901B119;
2401 cpu
->reset_sctlr
= 0x00000070;
2404 static void pxa250_initfn(Object
*obj
)
2406 ARMCPU
*cpu
= ARM_CPU(obj
);
2408 cpu
->dtb_compatible
= "marvell,xscale";
2409 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2410 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2411 cpu
->midr
= 0x69052100;
2412 cpu
->ctr
= 0xd172172;
2413 cpu
->reset_sctlr
= 0x00000078;
2416 static void pxa255_initfn(Object
*obj
)
2418 ARMCPU
*cpu
= ARM_CPU(obj
);
2420 cpu
->dtb_compatible
= "marvell,xscale";
2421 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2422 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2423 cpu
->midr
= 0x69052d00;
2424 cpu
->ctr
= 0xd172172;
2425 cpu
->reset_sctlr
= 0x00000078;
2428 static void pxa260_initfn(Object
*obj
)
2430 ARMCPU
*cpu
= ARM_CPU(obj
);
2432 cpu
->dtb_compatible
= "marvell,xscale";
2433 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2434 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2435 cpu
->midr
= 0x69052903;
2436 cpu
->ctr
= 0xd172172;
2437 cpu
->reset_sctlr
= 0x00000078;
2440 static void pxa261_initfn(Object
*obj
)
2442 ARMCPU
*cpu
= ARM_CPU(obj
);
2444 cpu
->dtb_compatible
= "marvell,xscale";
2445 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2446 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2447 cpu
->midr
= 0x69052d05;
2448 cpu
->ctr
= 0xd172172;
2449 cpu
->reset_sctlr
= 0x00000078;
2452 static void pxa262_initfn(Object
*obj
)
2454 ARMCPU
*cpu
= ARM_CPU(obj
);
2456 cpu
->dtb_compatible
= "marvell,xscale";
2457 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2458 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2459 cpu
->midr
= 0x69052d06;
2460 cpu
->ctr
= 0xd172172;
2461 cpu
->reset_sctlr
= 0x00000078;
2464 static void pxa270a0_initfn(Object
*obj
)
2466 ARMCPU
*cpu
= ARM_CPU(obj
);
2468 cpu
->dtb_compatible
= "marvell,xscale";
2469 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2470 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2471 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
2472 cpu
->midr
= 0x69054110;
2473 cpu
->ctr
= 0xd172172;
2474 cpu
->reset_sctlr
= 0x00000078;
2477 static void pxa270a1_initfn(Object
*obj
)
2479 ARMCPU
*cpu
= ARM_CPU(obj
);
2481 cpu
->dtb_compatible
= "marvell,xscale";
2482 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2483 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2484 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
2485 cpu
->midr
= 0x69054111;
2486 cpu
->ctr
= 0xd172172;
2487 cpu
->reset_sctlr
= 0x00000078;
2490 static void pxa270b0_initfn(Object
*obj
)
2492 ARMCPU
*cpu
= ARM_CPU(obj
);
2494 cpu
->dtb_compatible
= "marvell,xscale";
2495 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2496 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2497 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
2498 cpu
->midr
= 0x69054112;
2499 cpu
->ctr
= 0xd172172;
2500 cpu
->reset_sctlr
= 0x00000078;
2503 static void pxa270b1_initfn(Object
*obj
)
2505 ARMCPU
*cpu
= ARM_CPU(obj
);
2507 cpu
->dtb_compatible
= "marvell,xscale";
2508 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2509 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2510 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
2511 cpu
->midr
= 0x69054113;
2512 cpu
->ctr
= 0xd172172;
2513 cpu
->reset_sctlr
= 0x00000078;
2516 static void pxa270c0_initfn(Object
*obj
)
2518 ARMCPU
*cpu
= ARM_CPU(obj
);
2520 cpu
->dtb_compatible
= "marvell,xscale";
2521 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2522 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2523 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
2524 cpu
->midr
= 0x69054114;
2525 cpu
->ctr
= 0xd172172;
2526 cpu
->reset_sctlr
= 0x00000078;
2529 static void pxa270c5_initfn(Object
*obj
)
2531 ARMCPU
*cpu
= ARM_CPU(obj
);
2533 cpu
->dtb_compatible
= "marvell,xscale";
2534 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2535 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2536 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
2537 cpu
->midr
= 0x69054117;
2538 cpu
->ctr
= 0xd172172;
2539 cpu
->reset_sctlr
= 0x00000078;
2542 #ifndef TARGET_AARCH64
2543 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
2544 * otherwise, a CPU with as many features enabled as our emulation supports.
2545 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
2546 * this only needs to handle 32 bits.
2548 static void arm_max_initfn(Object
*obj
)
2550 ARMCPU
*cpu
= ARM_CPU(obj
);
2552 if (kvm_enabled()) {
2553 kvm_arm_set_cpu_features_from_host(cpu
);
2555 cortex_a15_initfn(obj
);
2557 /* old-style VFP short-vector support */
2558 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPSHVEC
, 1);
2560 #ifdef CONFIG_USER_ONLY
2561 /* We don't set these in system emulation mode for the moment,
2562 * since we don't correctly set (all of) the ID registers to
2565 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
2569 t
= cpu
->isar
.id_isar5
;
2570 t
= FIELD_DP32(t
, ID_ISAR5
, AES
, 2);
2571 t
= FIELD_DP32(t
, ID_ISAR5
, SHA1
, 1);
2572 t
= FIELD_DP32(t
, ID_ISAR5
, SHA2
, 1);
2573 t
= FIELD_DP32(t
, ID_ISAR5
, CRC32
, 1);
2574 t
= FIELD_DP32(t
, ID_ISAR5
, RDM
, 1);
2575 t
= FIELD_DP32(t
, ID_ISAR5
, VCMA
, 1);
2576 cpu
->isar
.id_isar5
= t
;
2578 t
= cpu
->isar
.id_isar6
;
2579 t
= FIELD_DP32(t
, ID_ISAR6
, JSCVT
, 1);
2580 t
= FIELD_DP32(t
, ID_ISAR6
, DP
, 1);
2581 t
= FIELD_DP32(t
, ID_ISAR6
, FHM
, 1);
2582 t
= FIELD_DP32(t
, ID_ISAR6
, SB
, 1);
2583 t
= FIELD_DP32(t
, ID_ISAR6
, SPECRES
, 1);
2584 cpu
->isar
.id_isar6
= t
;
2586 t
= cpu
->isar
.mvfr1
;
2587 t
= FIELD_DP32(t
, MVFR1
, FPHP
, 2); /* v8.0 FP support */
2588 cpu
->isar
.mvfr1
= t
;
2590 t
= cpu
->isar
.mvfr2
;
2591 t
= FIELD_DP32(t
, MVFR2
, SIMDMISC
, 3); /* SIMD MaxNum */
2592 t
= FIELD_DP32(t
, MVFR2
, FPMISC
, 4); /* FP MaxNum */
2593 cpu
->isar
.mvfr2
= t
;
2596 t
= FIELD_DP32(t
, ID_MMFR4
, HPDS
, 1); /* AA32HPD */
2604 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
2608 void (*initfn
)(Object
*obj
);
2609 void (*class_init
)(ObjectClass
*oc
, void *data
);
2612 static const ARMCPUInfo arm_cpus
[] = {
2613 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
2614 { .name
= "arm926", .initfn
= arm926_initfn
},
2615 { .name
= "arm946", .initfn
= arm946_initfn
},
2616 { .name
= "arm1026", .initfn
= arm1026_initfn
},
2617 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
2618 * older core than plain "arm1136". In particular this does not
2619 * have the v6K features.
2621 { .name
= "arm1136-r2", .initfn
= arm1136_r2_initfn
},
2622 { .name
= "arm1136", .initfn
= arm1136_initfn
},
2623 { .name
= "arm1176", .initfn
= arm1176_initfn
},
2624 { .name
= "arm11mpcore", .initfn
= arm11mpcore_initfn
},
2625 { .name
= "cortex-m0", .initfn
= cortex_m0_initfn
,
2626 .class_init
= arm_v7m_class_init
},
2627 { .name
= "cortex-m3", .initfn
= cortex_m3_initfn
,
2628 .class_init
= arm_v7m_class_init
},
2629 { .name
= "cortex-m4", .initfn
= cortex_m4_initfn
,
2630 .class_init
= arm_v7m_class_init
},
2631 { .name
= "cortex-m7", .initfn
= cortex_m7_initfn
,
2632 .class_init
= arm_v7m_class_init
},
2633 { .name
= "cortex-m33", .initfn
= cortex_m33_initfn
,
2634 .class_init
= arm_v7m_class_init
},
2635 { .name
= "cortex-r5", .initfn
= cortex_r5_initfn
},
2636 { .name
= "cortex-r5f", .initfn
= cortex_r5f_initfn
},
2637 { .name
= "cortex-a7", .initfn
= cortex_a7_initfn
},
2638 { .name
= "cortex-a8", .initfn
= cortex_a8_initfn
},
2639 { .name
= "cortex-a9", .initfn
= cortex_a9_initfn
},
2640 { .name
= "cortex-a15", .initfn
= cortex_a15_initfn
},
2641 { .name
= "ti925t", .initfn
= ti925t_initfn
},
2642 { .name
= "sa1100", .initfn
= sa1100_initfn
},
2643 { .name
= "sa1110", .initfn
= sa1110_initfn
},
2644 { .name
= "pxa250", .initfn
= pxa250_initfn
},
2645 { .name
= "pxa255", .initfn
= pxa255_initfn
},
2646 { .name
= "pxa260", .initfn
= pxa260_initfn
},
2647 { .name
= "pxa261", .initfn
= pxa261_initfn
},
2648 { .name
= "pxa262", .initfn
= pxa262_initfn
},
2649 /* "pxa270" is an alias for "pxa270-a0" */
2650 { .name
= "pxa270", .initfn
= pxa270a0_initfn
},
2651 { .name
= "pxa270-a0", .initfn
= pxa270a0_initfn
},
2652 { .name
= "pxa270-a1", .initfn
= pxa270a1_initfn
},
2653 { .name
= "pxa270-b0", .initfn
= pxa270b0_initfn
},
2654 { .name
= "pxa270-b1", .initfn
= pxa270b1_initfn
},
2655 { .name
= "pxa270-c0", .initfn
= pxa270c0_initfn
},
2656 { .name
= "pxa270-c5", .initfn
= pxa270c5_initfn
},
2657 #ifndef TARGET_AARCH64
2658 { .name
= "max", .initfn
= arm_max_initfn
},
2660 #ifdef CONFIG_USER_ONLY
2661 { .name
= "any", .initfn
= arm_max_initfn
},
2667 static Property arm_cpu_properties
[] = {
2668 DEFINE_PROP_BOOL("start-powered-off", ARMCPU
, start_powered_off
, false),
2669 DEFINE_PROP_UINT32("psci-conduit", ARMCPU
, psci_conduit
, 0),
2670 DEFINE_PROP_UINT32("midr", ARMCPU
, midr
, 0),
2671 DEFINE_PROP_UINT64("mp-affinity", ARMCPU
,
2672 mp_affinity
, ARM64_AFFINITY_INVALID
),
2673 DEFINE_PROP_INT32("node-id", ARMCPU
, node_id
, CPU_UNSET_NUMA_NODE_ID
),
2674 DEFINE_PROP_INT32("core-count", ARMCPU
, core_count
, -1),
2675 DEFINE_PROP_END_OF_LIST()
2678 static gchar
*arm_gdb_arch_name(CPUState
*cs
)
2680 ARMCPU
*cpu
= ARM_CPU(cs
);
2681 CPUARMState
*env
= &cpu
->env
;
2683 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
2684 return g_strdup("iwmmxt");
2686 return g_strdup("arm");
2689 static void arm_cpu_class_init(ObjectClass
*oc
, void *data
)
2691 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2692 CPUClass
*cc
= CPU_CLASS(acc
);
2693 DeviceClass
*dc
= DEVICE_CLASS(oc
);
2695 device_class_set_parent_realize(dc
, arm_cpu_realizefn
,
2696 &acc
->parent_realize
);
2698 device_class_set_props(dc
, arm_cpu_properties
);
2699 cpu_class_set_parent_reset(cc
, arm_cpu_reset
, &acc
->parent_reset
);
2701 cc
->class_by_name
= arm_cpu_class_by_name
;
2702 cc
->has_work
= arm_cpu_has_work
;
2703 cc
->cpu_exec_interrupt
= arm_cpu_exec_interrupt
;
2704 cc
->dump_state
= arm_cpu_dump_state
;
2705 cc
->set_pc
= arm_cpu_set_pc
;
2706 cc
->synchronize_from_tb
= arm_cpu_synchronize_from_tb
;
2707 cc
->gdb_read_register
= arm_cpu_gdb_read_register
;
2708 cc
->gdb_write_register
= arm_cpu_gdb_write_register
;
2709 #ifndef CONFIG_USER_ONLY
2710 cc
->do_interrupt
= arm_cpu_do_interrupt
;
2711 cc
->get_phys_page_attrs_debug
= arm_cpu_get_phys_page_attrs_debug
;
2712 cc
->asidx_from_attrs
= arm_asidx_from_attrs
;
2713 cc
->vmsd
= &vmstate_arm_cpu
;
2714 cc
->virtio_is_big_endian
= arm_cpu_virtio_is_big_endian
;
2715 cc
->write_elf64_note
= arm_cpu_write_elf64_note
;
2716 cc
->write_elf32_note
= arm_cpu_write_elf32_note
;
2718 cc
->gdb_num_core_regs
= 26;
2719 cc
->gdb_core_xml_file
= "arm-core.xml";
2720 cc
->gdb_arch_name
= arm_gdb_arch_name
;
2721 cc
->gdb_get_dynamic_xml
= arm_gdb_get_dynamic_xml
;
2722 cc
->gdb_stop_before_watchpoint
= true;
2723 cc
->disas_set_info
= arm_disas_set_info
;
2725 cc
->tcg_initialize
= arm_translate_init
;
2726 cc
->tlb_fill
= arm_cpu_tlb_fill
;
2727 cc
->debug_excp_handler
= arm_debug_excp_handler
;
2728 cc
->debug_check_watchpoint
= arm_debug_check_watchpoint
;
2729 #if !defined(CONFIG_USER_ONLY)
2730 cc
->do_unaligned_access
= arm_cpu_do_unaligned_access
;
2731 cc
->do_transaction_failed
= arm_cpu_do_transaction_failed
;
2732 cc
->adjust_watchpoint_address
= arm_adjust_watchpoint_address
;
2733 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
2738 static void arm_host_initfn(Object
*obj
)
2740 ARMCPU
*cpu
= ARM_CPU(obj
);
2742 kvm_arm_set_cpu_features_from_host(cpu
);
2743 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
2744 aarch64_add_sve_properties(obj
);
2746 arm_cpu_post_init(obj
);
2749 static const TypeInfo host_arm_cpu_type_info
= {
2750 .name
= TYPE_ARM_HOST_CPU
,
2751 #ifdef TARGET_AARCH64
2752 .parent
= TYPE_AARCH64_CPU
,
2754 .parent
= TYPE_ARM_CPU
,
2756 .instance_init
= arm_host_initfn
,
2761 static void arm_cpu_instance_init(Object
*obj
)
2763 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(obj
);
2765 acc
->info
->initfn(obj
);
2766 arm_cpu_post_init(obj
);
2769 static void cpu_register_class_init(ObjectClass
*oc
, void *data
)
2771 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2776 static void cpu_register(const ARMCPUInfo
*info
)
2778 TypeInfo type_info
= {
2779 .parent
= TYPE_ARM_CPU
,
2780 .instance_size
= sizeof(ARMCPU
),
2781 .instance_init
= arm_cpu_instance_init
,
2782 .class_size
= sizeof(ARMCPUClass
),
2783 .class_init
= info
->class_init
?: cpu_register_class_init
,
2784 .class_data
= (void *)info
,
2787 type_info
.name
= g_strdup_printf("%s-" TYPE_ARM_CPU
, info
->name
);
2788 type_register(&type_info
);
2789 g_free((void *)type_info
.name
);
2792 static const TypeInfo arm_cpu_type_info
= {
2793 .name
= TYPE_ARM_CPU
,
2795 .instance_size
= sizeof(ARMCPU
),
2796 .instance_init
= arm_cpu_initfn
,
2797 .instance_finalize
= arm_cpu_finalizefn
,
2799 .class_size
= sizeof(ARMCPUClass
),
2800 .class_init
= arm_cpu_class_init
,
2803 static const TypeInfo idau_interface_type_info
= {
2804 .name
= TYPE_IDAU_INTERFACE
,
2805 .parent
= TYPE_INTERFACE
,
2806 .class_size
= sizeof(IDAUInterfaceClass
),
2809 static void arm_cpu_register_types(void)
2811 const ARMCPUInfo
*info
= arm_cpus
;
2813 type_register_static(&arm_cpu_type_info
);
2814 type_register_static(&idau_interface_type_info
);
2816 while (info
->name
) {
2822 type_register_static(&host_arm_cpu_type_info
);
2826 type_init(arm_cpu_register_types
)