4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu/osdep.h"
22 #include "qemu/qemu-print.h"
23 #include "qemu-common.h"
24 #include "target/arm/idau.h"
25 #include "qemu/module.h"
26 #include "qapi/error.h"
27 #include "qapi/visitor.h"
29 #include "internals.h"
30 #include "exec/exec-all.h"
31 #include "hw/qdev-properties.h"
32 #if !defined(CONFIG_USER_ONLY)
33 #include "hw/loader.h"
34 #include "hw/boards.h"
36 #include "sysemu/sysemu.h"
37 #include "sysemu/tcg.h"
38 #include "sysemu/hw_accel.h"
40 #include "disas/capstone.h"
41 #include "fpu/softfloat.h"
43 static void arm_cpu_set_pc(CPUState
*cs
, vaddr value
)
45 ARMCPU
*cpu
= ARM_CPU(cs
);
46 CPUARMState
*env
= &cpu
->env
;
52 env
->regs
[15] = value
& ~1;
53 env
->thumb
= value
& 1;
57 static void arm_cpu_synchronize_from_tb(CPUState
*cs
, TranslationBlock
*tb
)
59 ARMCPU
*cpu
= ARM_CPU(cs
);
60 CPUARMState
*env
= &cpu
->env
;
63 * It's OK to look at env for the current mode here, because it's
64 * never possible for an AArch64 TB to chain to an AArch32 TB.
69 env
->regs
[15] = tb
->pc
;
73 static bool arm_cpu_has_work(CPUState
*cs
)
75 ARMCPU
*cpu
= ARM_CPU(cs
);
77 return (cpu
->power_state
!= PSCI_OFF
)
78 && cs
->interrupt_request
&
79 (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
80 | CPU_INTERRUPT_VFIQ
| CPU_INTERRUPT_VIRQ
81 | CPU_INTERRUPT_EXITTB
);
84 void arm_register_pre_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
87 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
90 entry
->opaque
= opaque
;
92 QLIST_INSERT_HEAD(&cpu
->pre_el_change_hooks
, entry
, node
);
95 void arm_register_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
98 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
101 entry
->opaque
= opaque
;
103 QLIST_INSERT_HEAD(&cpu
->el_change_hooks
, entry
, node
);
106 static void cp_reg_reset(gpointer key
, gpointer value
, gpointer opaque
)
108 /* Reset a single ARMCPRegInfo register */
109 ARMCPRegInfo
*ri
= value
;
110 ARMCPU
*cpu
= opaque
;
112 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
)) {
117 ri
->resetfn(&cpu
->env
, ri
);
121 /* A zero offset is never possible as it would be regs[0]
122 * so we use it to indicate that reset is being handled elsewhere.
123 * This is basically only used for fields in non-core coprocessors
124 * (like the pxa2xx ones).
126 if (!ri
->fieldoffset
) {
130 if (cpreg_field_is_64bit(ri
)) {
131 CPREG_FIELD64(&cpu
->env
, ri
) = ri
->resetvalue
;
133 CPREG_FIELD32(&cpu
->env
, ri
) = ri
->resetvalue
;
137 static void cp_reg_check_reset(gpointer key
, gpointer value
, gpointer opaque
)
139 /* Purely an assertion check: we've already done reset once,
140 * so now check that running the reset for the cpreg doesn't
141 * change its value. This traps bugs where two different cpregs
142 * both try to reset the same state field but to different values.
144 ARMCPRegInfo
*ri
= value
;
145 ARMCPU
*cpu
= opaque
;
146 uint64_t oldvalue
, newvalue
;
148 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
| ARM_CP_NO_RAW
)) {
152 oldvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
153 cp_reg_reset(key
, value
, opaque
);
154 newvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
155 assert(oldvalue
== newvalue
);
158 static void arm_cpu_reset(DeviceState
*dev
)
160 CPUState
*s
= CPU(dev
);
161 ARMCPU
*cpu
= ARM_CPU(s
);
162 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(cpu
);
163 CPUARMState
*env
= &cpu
->env
;
165 acc
->parent_reset(dev
);
167 memset(env
, 0, offsetof(CPUARMState
, end_reset_fields
));
169 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_reset
, cpu
);
170 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_check_reset
, cpu
);
172 env
->vfp
.xregs
[ARM_VFP_FPSID
] = cpu
->reset_fpsid
;
173 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = cpu
->isar
.mvfr0
;
174 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = cpu
->isar
.mvfr1
;
175 env
->vfp
.xregs
[ARM_VFP_MVFR2
] = cpu
->isar
.mvfr2
;
177 cpu
->power_state
= cpu
->start_powered_off
? PSCI_OFF
: PSCI_ON
;
178 s
->halted
= cpu
->start_powered_off
;
180 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
181 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
184 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
185 /* 64 bit CPUs always start in 64 bit mode */
187 #if defined(CONFIG_USER_ONLY)
188 env
->pstate
= PSTATE_MODE_EL0t
;
189 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
190 env
->cp15
.sctlr_el
[1] |= SCTLR_UCT
| SCTLR_UCI
| SCTLR_DZE
;
191 /* Enable all PAC keys. */
192 env
->cp15
.sctlr_el
[1] |= (SCTLR_EnIA
| SCTLR_EnIB
|
193 SCTLR_EnDA
| SCTLR_EnDB
);
194 /* and to the FP/Neon instructions */
195 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 2, 3);
196 /* and to the SVE instructions */
197 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 16, 2, 3);
198 /* with reasonable vector length */
199 if (cpu_isar_feature(aa64_sve
, cpu
)) {
200 env
->vfp
.zcr_el
[1] = MIN(cpu
->sve_max_vq
- 1, 3);
203 * Enable TBI0 and TBI1. While the real kernel only enables TBI0,
204 * turning on both here will produce smaller code and otherwise
205 * make no difference to the user-level emulation.
207 env
->cp15
.tcr_el
[1].raw_tcr
= (3ULL << 37);
209 /* Reset into the highest available EL */
210 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
211 env
->pstate
= PSTATE_MODE_EL3h
;
212 } else if (arm_feature(env
, ARM_FEATURE_EL2
)) {
213 env
->pstate
= PSTATE_MODE_EL2h
;
215 env
->pstate
= PSTATE_MODE_EL1h
;
217 env
->pc
= cpu
->rvbar
;
220 #if defined(CONFIG_USER_ONLY)
221 /* Userspace expects access to cp10 and cp11 for FP/Neon */
222 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 4, 0xf);
226 #if defined(CONFIG_USER_ONLY)
227 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
228 /* For user mode we must enable access to coprocessors */
229 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
230 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
231 env
->cp15
.c15_cpar
= 3;
232 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
233 env
->cp15
.c15_cpar
= 1;
238 * If the highest available EL is EL2, AArch32 will start in Hyp
239 * mode; otherwise it starts in SVC. Note that if we start in
240 * AArch64 then these values in the uncached_cpsr will be ignored.
242 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
243 !arm_feature(env
, ARM_FEATURE_EL3
)) {
244 env
->uncached_cpsr
= ARM_CPU_MODE_HYP
;
246 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
;
248 env
->daif
= PSTATE_D
| PSTATE_A
| PSTATE_I
| PSTATE_F
;
250 if (arm_feature(env
, ARM_FEATURE_M
)) {
251 uint32_t initial_msp
; /* Loaded from 0x0 */
252 uint32_t initial_pc
; /* Loaded from 0x4 */
256 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
257 env
->v7m
.secure
= true;
259 /* This bit resets to 0 if security is supported, but 1 if
260 * it is not. The bit is not present in v7M, but we set it
261 * here so we can avoid having to make checks on it conditional
262 * on ARM_FEATURE_V8 (we don't let the guest see the bit).
264 env
->v7m
.aircr
= R_V7M_AIRCR_BFHFNMINS_MASK
;
266 * Set NSACR to indicate "NS access permitted to everything";
267 * this avoids having to have all the tests of it being
268 * conditional on ARM_FEATURE_M_SECURITY. Note also that from
269 * v8.1M the guest-visible value of NSACR in a CPU without the
270 * Security Extension is 0xcff.
272 env
->v7m
.nsacr
= 0xcff;
275 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
276 * that it resets to 1, so QEMU always does that rather than making
277 * it dependent on CPU model. In v8M it is RES1.
279 env
->v7m
.ccr
[M_REG_NS
] = R_V7M_CCR_STKALIGN_MASK
;
280 env
->v7m
.ccr
[M_REG_S
] = R_V7M_CCR_STKALIGN_MASK
;
281 if (arm_feature(env
, ARM_FEATURE_V8
)) {
282 /* in v8M the NONBASETHRDENA bit [0] is RES1 */
283 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
284 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
286 if (!arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
287 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
288 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
291 if (cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
292 env
->v7m
.fpccr
[M_REG_NS
] = R_V7M_FPCCR_ASPEN_MASK
;
293 env
->v7m
.fpccr
[M_REG_S
] = R_V7M_FPCCR_ASPEN_MASK
|
294 R_V7M_FPCCR_LSPEN_MASK
| R_V7M_FPCCR_S_MASK
;
296 /* Unlike A/R profile, M profile defines the reset LR value */
297 env
->regs
[14] = 0xffffffff;
299 env
->v7m
.vecbase
[M_REG_S
] = cpu
->init_svtor
& 0xffffff80;
301 /* Load the initial SP and PC from offset 0 and 4 in the vector table */
302 vecbase
= env
->v7m
.vecbase
[env
->v7m
.secure
];
303 rom
= rom_ptr(vecbase
, 8);
305 /* Address zero is covered by ROM which hasn't yet been
306 * copied into physical memory.
308 initial_msp
= ldl_p(rom
);
309 initial_pc
= ldl_p(rom
+ 4);
311 /* Address zero not covered by a ROM blob, or the ROM blob
312 * is in non-modifiable memory and this is a second reset after
313 * it got copied into memory. In the latter case, rom_ptr
314 * will return a NULL pointer and we should use ldl_phys instead.
316 initial_msp
= ldl_phys(s
->as
, vecbase
);
317 initial_pc
= ldl_phys(s
->as
, vecbase
+ 4);
320 env
->regs
[13] = initial_msp
& 0xFFFFFFFC;
321 env
->regs
[15] = initial_pc
& ~1;
322 env
->thumb
= initial_pc
& 1;
325 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
326 * executing as AArch32 then check if highvecs are enabled and
327 * adjust the PC accordingly.
329 if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
330 env
->regs
[15] = 0xFFFF0000;
333 /* M profile requires that reset clears the exclusive monitor;
334 * A profile does not, but clearing it makes more sense than having it
335 * set with an exclusive access on address zero.
337 arm_clear_exclusive(env
);
339 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
342 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
343 if (cpu
->pmsav7_dregion
> 0) {
344 if (arm_feature(env
, ARM_FEATURE_V8
)) {
345 memset(env
->pmsav8
.rbar
[M_REG_NS
], 0,
346 sizeof(*env
->pmsav8
.rbar
[M_REG_NS
])
347 * cpu
->pmsav7_dregion
);
348 memset(env
->pmsav8
.rlar
[M_REG_NS
], 0,
349 sizeof(*env
->pmsav8
.rlar
[M_REG_NS
])
350 * cpu
->pmsav7_dregion
);
351 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
352 memset(env
->pmsav8
.rbar
[M_REG_S
], 0,
353 sizeof(*env
->pmsav8
.rbar
[M_REG_S
])
354 * cpu
->pmsav7_dregion
);
355 memset(env
->pmsav8
.rlar
[M_REG_S
], 0,
356 sizeof(*env
->pmsav8
.rlar
[M_REG_S
])
357 * cpu
->pmsav7_dregion
);
359 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
360 memset(env
->pmsav7
.drbar
, 0,
361 sizeof(*env
->pmsav7
.drbar
) * cpu
->pmsav7_dregion
);
362 memset(env
->pmsav7
.drsr
, 0,
363 sizeof(*env
->pmsav7
.drsr
) * cpu
->pmsav7_dregion
);
364 memset(env
->pmsav7
.dracr
, 0,
365 sizeof(*env
->pmsav7
.dracr
) * cpu
->pmsav7_dregion
);
368 env
->pmsav7
.rnr
[M_REG_NS
] = 0;
369 env
->pmsav7
.rnr
[M_REG_S
] = 0;
370 env
->pmsav8
.mair0
[M_REG_NS
] = 0;
371 env
->pmsav8
.mair0
[M_REG_S
] = 0;
372 env
->pmsav8
.mair1
[M_REG_NS
] = 0;
373 env
->pmsav8
.mair1
[M_REG_S
] = 0;
376 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
377 if (cpu
->sau_sregion
> 0) {
378 memset(env
->sau
.rbar
, 0, sizeof(*env
->sau
.rbar
) * cpu
->sau_sregion
);
379 memset(env
->sau
.rlar
, 0, sizeof(*env
->sau
.rlar
) * cpu
->sau_sregion
);
382 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
383 * the Cortex-M33 does.
388 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
389 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
390 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
391 set_float_detect_tininess(float_tininess_before_rounding
,
392 &env
->vfp
.fp_status
);
393 set_float_detect_tininess(float_tininess_before_rounding
,
394 &env
->vfp
.standard_fp_status
);
395 set_float_detect_tininess(float_tininess_before_rounding
,
396 &env
->vfp
.fp_status_f16
);
397 #ifndef CONFIG_USER_ONLY
399 kvm_arm_reset_vcpu(cpu
);
403 hw_breakpoint_update_all(cpu
);
404 hw_watchpoint_update_all(cpu
);
405 arm_rebuild_hflags(env
);
408 static inline bool arm_excp_unmasked(CPUState
*cs
, unsigned int excp_idx
,
409 unsigned int target_el
,
410 unsigned int cur_el
, bool secure
,
413 CPUARMState
*env
= cs
->env_ptr
;
414 bool pstate_unmasked
;
415 bool unmasked
= false;
418 * Don't take exceptions if they target a lower EL.
419 * This check should catch any exceptions that would not be taken
422 if (cur_el
> target_el
) {
428 pstate_unmasked
= !(env
->daif
& PSTATE_F
);
432 pstate_unmasked
= !(env
->daif
& PSTATE_I
);
436 if (secure
|| !(hcr_el2
& HCR_FMO
) || (hcr_el2
& HCR_TGE
)) {
437 /* VFIQs are only taken when hypervized and non-secure. */
440 return !(env
->daif
& PSTATE_F
);
442 if (secure
|| !(hcr_el2
& HCR_IMO
) || (hcr_el2
& HCR_TGE
)) {
443 /* VIRQs are only taken when hypervized and non-secure. */
446 return !(env
->daif
& PSTATE_I
);
448 g_assert_not_reached();
452 * Use the target EL, current execution state and SCR/HCR settings to
453 * determine whether the corresponding CPSR bit is used to mask the
456 if ((target_el
> cur_el
) && (target_el
!= 1)) {
457 /* Exceptions targeting a higher EL may not be maskable */
458 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
460 * 64-bit masking rules are simple: exceptions to EL3
461 * can't be masked, and exceptions to EL2 can only be
462 * masked from Secure state. The HCR and SCR settings
463 * don't affect the masking logic, only the interrupt routing.
465 if (target_el
== 3 || !secure
) {
470 * The old 32-bit-only environment has a more complicated
471 * masking setup. HCR and SCR bits not only affect interrupt
472 * routing but also change the behaviour of masking.
479 * If FIQs are routed to EL3 or EL2 then there are cases where
480 * we override the CPSR.F in determining if the exception is
481 * masked or not. If neither of these are set then we fall back
482 * to the CPSR.F setting otherwise we further assess the state
485 hcr
= hcr_el2
& HCR_FMO
;
486 scr
= (env
->cp15
.scr_el3
& SCR_FIQ
);
489 * When EL3 is 32-bit, the SCR.FW bit controls whether the
490 * CPSR.F bit masks FIQ interrupts when taken in non-secure
491 * state. If SCR.FW is set then FIQs can be masked by CPSR.F
492 * when non-secure but only when FIQs are only routed to EL3.
494 scr
= scr
&& !((env
->cp15
.scr_el3
& SCR_FW
) && !hcr
);
498 * When EL3 execution state is 32-bit, if HCR.IMO is set then
499 * we may override the CPSR.I masking when in non-secure state.
500 * The SCR.IRQ setting has already been taken into consideration
501 * when setting the target EL, so it does not have a further
504 hcr
= hcr_el2
& HCR_IMO
;
508 g_assert_not_reached();
511 if ((scr
|| hcr
) && !secure
) {
518 * The PSTATE bits only mask the interrupt if we have not overriden the
521 return unmasked
|| pstate_unmasked
;
524 bool arm_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
526 CPUClass
*cc
= CPU_GET_CLASS(cs
);
527 CPUARMState
*env
= cs
->env_ptr
;
528 uint32_t cur_el
= arm_current_el(env
);
529 bool secure
= arm_is_secure(env
);
530 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
534 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */
536 if (interrupt_request
& CPU_INTERRUPT_FIQ
) {
538 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
539 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
540 cur_el
, secure
, hcr_el2
)) {
544 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
546 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
547 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
548 cur_el
, secure
, hcr_el2
)) {
552 if (interrupt_request
& CPU_INTERRUPT_VIRQ
) {
553 excp_idx
= EXCP_VIRQ
;
555 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
556 cur_el
, secure
, hcr_el2
)) {
560 if (interrupt_request
& CPU_INTERRUPT_VFIQ
) {
561 excp_idx
= EXCP_VFIQ
;
563 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
564 cur_el
, secure
, hcr_el2
)) {
571 cs
->exception_index
= excp_idx
;
572 env
->exception
.target_el
= target_el
;
573 cc
->do_interrupt(cs
);
577 void arm_cpu_update_virq(ARMCPU
*cpu
)
580 * Update the interrupt level for VIRQ, which is the logical OR of
581 * the HCR_EL2.VI bit and the input line level from the GIC.
583 CPUARMState
*env
= &cpu
->env
;
584 CPUState
*cs
= CPU(cpu
);
586 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VI
) ||
587 (env
->irq_line_state
& CPU_INTERRUPT_VIRQ
);
589 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) != 0)) {
591 cpu_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
593 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
598 void arm_cpu_update_vfiq(ARMCPU
*cpu
)
601 * Update the interrupt level for VFIQ, which is the logical OR of
602 * the HCR_EL2.VF bit and the input line level from the GIC.
604 CPUARMState
*env
= &cpu
->env
;
605 CPUState
*cs
= CPU(cpu
);
607 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VF
) ||
608 (env
->irq_line_state
& CPU_INTERRUPT_VFIQ
);
610 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) != 0)) {
612 cpu_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
614 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
619 #ifndef CONFIG_USER_ONLY
620 static void arm_cpu_set_irq(void *opaque
, int irq
, int level
)
622 ARMCPU
*cpu
= opaque
;
623 CPUARMState
*env
= &cpu
->env
;
624 CPUState
*cs
= CPU(cpu
);
625 static const int mask
[] = {
626 [ARM_CPU_IRQ
] = CPU_INTERRUPT_HARD
,
627 [ARM_CPU_FIQ
] = CPU_INTERRUPT_FIQ
,
628 [ARM_CPU_VIRQ
] = CPU_INTERRUPT_VIRQ
,
629 [ARM_CPU_VFIQ
] = CPU_INTERRUPT_VFIQ
633 env
->irq_line_state
|= mask
[irq
];
635 env
->irq_line_state
&= ~mask
[irq
];
640 assert(arm_feature(env
, ARM_FEATURE_EL2
));
641 arm_cpu_update_virq(cpu
);
644 assert(arm_feature(env
, ARM_FEATURE_EL2
));
645 arm_cpu_update_vfiq(cpu
);
650 cpu_interrupt(cs
, mask
[irq
]);
652 cpu_reset_interrupt(cs
, mask
[irq
]);
656 g_assert_not_reached();
660 static void arm_cpu_kvm_set_irq(void *opaque
, int irq
, int level
)
663 ARMCPU
*cpu
= opaque
;
664 CPUARMState
*env
= &cpu
->env
;
665 CPUState
*cs
= CPU(cpu
);
666 uint32_t linestate_bit
;
671 irq_id
= KVM_ARM_IRQ_CPU_IRQ
;
672 linestate_bit
= CPU_INTERRUPT_HARD
;
675 irq_id
= KVM_ARM_IRQ_CPU_FIQ
;
676 linestate_bit
= CPU_INTERRUPT_FIQ
;
679 g_assert_not_reached();
683 env
->irq_line_state
|= linestate_bit
;
685 env
->irq_line_state
&= ~linestate_bit
;
687 kvm_arm_set_irq(cs
->cpu_index
, KVM_ARM_IRQ_TYPE_CPU
, irq_id
, !!level
);
691 static bool arm_cpu_virtio_is_big_endian(CPUState
*cs
)
693 ARMCPU
*cpu
= ARM_CPU(cs
);
694 CPUARMState
*env
= &cpu
->env
;
696 cpu_synchronize_state(cs
);
697 return arm_cpu_data_is_big_endian(env
);
703 print_insn_thumb1(bfd_vma pc
, disassemble_info
*info
)
705 return print_insn_arm(pc
| 1, info
);
708 static void arm_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
710 ARMCPU
*ac
= ARM_CPU(cpu
);
711 CPUARMState
*env
= &ac
->env
;
715 /* We might not be compiled with the A64 disassembler
716 * because it needs a C++ compiler. Leave print_insn
717 * unset in this case to use the caller default behaviour.
719 #if defined(CONFIG_ARM_A64_DIS)
720 info
->print_insn
= print_insn_arm_a64
;
722 info
->cap_arch
= CS_ARCH_ARM64
;
723 info
->cap_insn_unit
= 4;
724 info
->cap_insn_split
= 4;
728 info
->print_insn
= print_insn_thumb1
;
729 info
->cap_insn_unit
= 2;
730 info
->cap_insn_split
= 4;
731 cap_mode
= CS_MODE_THUMB
;
733 info
->print_insn
= print_insn_arm
;
734 info
->cap_insn_unit
= 4;
735 info
->cap_insn_split
= 4;
736 cap_mode
= CS_MODE_ARM
;
738 if (arm_feature(env
, ARM_FEATURE_V8
)) {
739 cap_mode
|= CS_MODE_V8
;
741 if (arm_feature(env
, ARM_FEATURE_M
)) {
742 cap_mode
|= CS_MODE_MCLASS
;
744 info
->cap_arch
= CS_ARCH_ARM
;
745 info
->cap_mode
= cap_mode
;
748 sctlr_b
= arm_sctlr_b(env
);
749 if (bswap_code(sctlr_b
)) {
750 #ifdef TARGET_WORDS_BIGENDIAN
751 info
->endian
= BFD_ENDIAN_LITTLE
;
753 info
->endian
= BFD_ENDIAN_BIG
;
756 info
->flags
&= ~INSN_ARM_BE32
;
757 #ifndef CONFIG_USER_ONLY
759 info
->flags
|= INSN_ARM_BE32
;
764 #ifdef TARGET_AARCH64
766 static void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
768 ARMCPU
*cpu
= ARM_CPU(cs
);
769 CPUARMState
*env
= &cpu
->env
;
770 uint32_t psr
= pstate_read(env
);
772 int el
= arm_current_el(env
);
773 const char *ns_status
;
775 qemu_fprintf(f
, " PC=%016" PRIx64
" ", env
->pc
);
776 for (i
= 0; i
< 32; i
++) {
778 qemu_fprintf(f
, " SP=%016" PRIx64
"\n", env
->xregs
[i
]);
780 qemu_fprintf(f
, "X%02d=%016" PRIx64
"%s", i
, env
->xregs
[i
],
781 (i
+ 2) % 3 ? " " : "\n");
785 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
786 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
790 qemu_fprintf(f
, "PSTATE=%08x %c%c%c%c %sEL%d%c",
792 psr
& PSTATE_N
? 'N' : '-',
793 psr
& PSTATE_Z
? 'Z' : '-',
794 psr
& PSTATE_C
? 'C' : '-',
795 psr
& PSTATE_V
? 'V' : '-',
798 psr
& PSTATE_SP
? 'h' : 't');
800 if (cpu_isar_feature(aa64_bti
, cpu
)) {
801 qemu_fprintf(f
, " BTYPE=%d", (psr
& PSTATE_BTYPE
) >> 10);
803 if (!(flags
& CPU_DUMP_FPU
)) {
804 qemu_fprintf(f
, "\n");
807 if (fp_exception_el(env
, el
) != 0) {
808 qemu_fprintf(f
, " FPU disabled\n");
811 qemu_fprintf(f
, " FPCR=%08x FPSR=%08x\n",
812 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
814 if (cpu_isar_feature(aa64_sve
, cpu
) && sve_exception_el(env
, el
) == 0) {
815 int j
, zcr_len
= sve_zcr_len_for_el(env
, el
);
817 for (i
= 0; i
<= FFR_PRED_NUM
; i
++) {
819 if (i
== FFR_PRED_NUM
) {
820 qemu_fprintf(f
, "FFR=");
821 /* It's last, so end the line. */
824 qemu_fprintf(f
, "P%02d=", i
);
837 /* More than one quadword per predicate. */
842 for (j
= zcr_len
/ 4; j
>= 0; j
--) {
844 if (j
* 4 + 4 <= zcr_len
+ 1) {
847 digits
= (zcr_len
% 4 + 1) * 4;
849 qemu_fprintf(f
, "%0*" PRIx64
"%s", digits
,
850 env
->vfp
.pregs
[i
].p
[j
],
851 j
? ":" : eol
? "\n" : " ");
855 for (i
= 0; i
< 32; i
++) {
857 qemu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
"%s",
858 i
, env
->vfp
.zregs
[i
].d
[1],
859 env
->vfp
.zregs
[i
].d
[0], i
& 1 ? "\n" : " ");
860 } else if (zcr_len
== 1) {
861 qemu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
862 ":%016" PRIx64
":%016" PRIx64
"\n",
863 i
, env
->vfp
.zregs
[i
].d
[3], env
->vfp
.zregs
[i
].d
[2],
864 env
->vfp
.zregs
[i
].d
[1], env
->vfp
.zregs
[i
].d
[0]);
866 for (j
= zcr_len
; j
>= 0; j
--) {
867 bool odd
= (zcr_len
- j
) % 2 != 0;
869 qemu_fprintf(f
, "Z%02d[%x-%x]=", i
, j
, j
- 1);
872 qemu_fprintf(f
, " [%x-%x]=", j
, j
- 1);
874 qemu_fprintf(f
, " [%x]=", j
);
877 qemu_fprintf(f
, "%016" PRIx64
":%016" PRIx64
"%s",
878 env
->vfp
.zregs
[i
].d
[j
* 2 + 1],
879 env
->vfp
.zregs
[i
].d
[j
* 2],
880 odd
|| j
== 0 ? "\n" : ":");
885 for (i
= 0; i
< 32; i
++) {
886 uint64_t *q
= aa64_vfp_qreg(env
, i
);
887 qemu_fprintf(f
, "Q%02d=%016" PRIx64
":%016" PRIx64
"%s",
888 i
, q
[1], q
[0], (i
& 1 ? "\n" : " "));
895 static inline void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
897 g_assert_not_reached();
902 static void arm_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
904 ARMCPU
*cpu
= ARM_CPU(cs
);
905 CPUARMState
*env
= &cpu
->env
;
909 aarch64_cpu_dump_state(cs
, f
, flags
);
913 for (i
= 0; i
< 16; i
++) {
914 qemu_fprintf(f
, "R%02d=%08x", i
, env
->regs
[i
]);
916 qemu_fprintf(f
, "\n");
918 qemu_fprintf(f
, " ");
922 if (arm_feature(env
, ARM_FEATURE_M
)) {
923 uint32_t xpsr
= xpsr_read(env
);
925 const char *ns_status
= "";
927 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
928 ns_status
= env
->v7m
.secure
? "S " : "NS ";
931 if (xpsr
& XPSR_EXCP
) {
934 if (env
->v7m
.control
[env
->v7m
.secure
] & R_V7M_CONTROL_NPRIV_MASK
) {
935 mode
= "unpriv-thread";
937 mode
= "priv-thread";
941 qemu_fprintf(f
, "XPSR=%08x %c%c%c%c %c %s%s\n",
943 xpsr
& XPSR_N
? 'N' : '-',
944 xpsr
& XPSR_Z
? 'Z' : '-',
945 xpsr
& XPSR_C
? 'C' : '-',
946 xpsr
& XPSR_V
? 'V' : '-',
947 xpsr
& XPSR_T
? 'T' : 'A',
951 uint32_t psr
= cpsr_read(env
);
952 const char *ns_status
= "";
954 if (arm_feature(env
, ARM_FEATURE_EL3
) &&
955 (psr
& CPSR_M
) != ARM_CPU_MODE_MON
) {
956 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
959 qemu_fprintf(f
, "PSR=%08x %c%c%c%c %c %s%s%d\n",
961 psr
& CPSR_N
? 'N' : '-',
962 psr
& CPSR_Z
? 'Z' : '-',
963 psr
& CPSR_C
? 'C' : '-',
964 psr
& CPSR_V
? 'V' : '-',
965 psr
& CPSR_T
? 'T' : 'A',
967 aarch32_mode_name(psr
), (psr
& 0x10) ? 32 : 26);
970 if (flags
& CPU_DUMP_FPU
) {
972 if (cpu_isar_feature(aa32_simd_r32
, cpu
)) {
974 } else if (cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
977 for (i
= 0; i
< numvfpregs
; i
++) {
978 uint64_t v
= *aa32_vfp_dreg(env
, i
);
979 qemu_fprintf(f
, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64
"\n",
981 i
* 2 + 1, (uint32_t)(v
>> 32),
984 qemu_fprintf(f
, "FPSCR: %08x\n", vfp_get_fpscr(env
));
988 uint64_t arm_cpu_mp_affinity(int idx
, uint8_t clustersz
)
990 uint32_t Aff1
= idx
/ clustersz
;
991 uint32_t Aff0
= idx
% clustersz
;
992 return (Aff1
<< ARM_AFF1_SHIFT
) | Aff0
;
995 static void cpreg_hashtable_data_destroy(gpointer data
)
998 * Destroy function for cpu->cp_regs hashtable data entries.
999 * We must free the name string because it was g_strdup()ed in
1000 * add_cpreg_to_hashtable(). It's OK to cast away the 'const'
1001 * from r->name because we know we definitely allocated it.
1003 ARMCPRegInfo
*r
= data
;
1005 g_free((void *)r
->name
);
1009 static void arm_cpu_initfn(Object
*obj
)
1011 ARMCPU
*cpu
= ARM_CPU(obj
);
1013 cpu_set_cpustate_pointers(cpu
);
1014 cpu
->cp_regs
= g_hash_table_new_full(g_int_hash
, g_int_equal
,
1015 g_free
, cpreg_hashtable_data_destroy
);
1017 QLIST_INIT(&cpu
->pre_el_change_hooks
);
1018 QLIST_INIT(&cpu
->el_change_hooks
);
1020 #ifndef CONFIG_USER_ONLY
1021 /* Our inbound IRQ and FIQ lines */
1022 if (kvm_enabled()) {
1023 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
1024 * the same interface as non-KVM CPUs.
1026 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_kvm_set_irq
, 4);
1028 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_set_irq
, 4);
1031 qdev_init_gpio_out(DEVICE(cpu
), cpu
->gt_timer_outputs
,
1032 ARRAY_SIZE(cpu
->gt_timer_outputs
));
1034 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->gicv3_maintenance_interrupt
,
1035 "gicv3-maintenance-interrupt", 1);
1036 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->pmu_interrupt
,
1037 "pmu-interrupt", 1);
1040 /* DTB consumers generally don't in fact care what the 'compatible'
1041 * string is, so always provide some string and trust that a hypothetical
1042 * picky DTB consumer will also provide a helpful error message.
1044 cpu
->dtb_compatible
= "qemu,unknown";
1045 cpu
->psci_version
= 1; /* By default assume PSCI v0.1 */
1046 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_NONE
;
1048 if (tcg_enabled()) {
1049 cpu
->psci_version
= 2; /* TCG implements PSCI 0.2 */
1053 static Property arm_cpu_gt_cntfrq_property
=
1054 DEFINE_PROP_UINT64("cntfrq", ARMCPU
, gt_cntfrq_hz
,
1055 NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
);
1057 static Property arm_cpu_reset_cbar_property
=
1058 DEFINE_PROP_UINT64("reset-cbar", ARMCPU
, reset_cbar
, 0);
1060 static Property arm_cpu_reset_hivecs_property
=
1061 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU
, reset_hivecs
, false);
1063 static Property arm_cpu_rvbar_property
=
1064 DEFINE_PROP_UINT64("rvbar", ARMCPU
, rvbar
, 0);
1066 #ifndef CONFIG_USER_ONLY
1067 static Property arm_cpu_has_el2_property
=
1068 DEFINE_PROP_BOOL("has_el2", ARMCPU
, has_el2
, true);
1070 static Property arm_cpu_has_el3_property
=
1071 DEFINE_PROP_BOOL("has_el3", ARMCPU
, has_el3
, true);
1074 static Property arm_cpu_cfgend_property
=
1075 DEFINE_PROP_BOOL("cfgend", ARMCPU
, cfgend
, false);
1077 static Property arm_cpu_has_vfp_property
=
1078 DEFINE_PROP_BOOL("vfp", ARMCPU
, has_vfp
, true);
1080 static Property arm_cpu_has_neon_property
=
1081 DEFINE_PROP_BOOL("neon", ARMCPU
, has_neon
, true);
1083 static Property arm_cpu_has_dsp_property
=
1084 DEFINE_PROP_BOOL("dsp", ARMCPU
, has_dsp
, true);
1086 static Property arm_cpu_has_mpu_property
=
1087 DEFINE_PROP_BOOL("has-mpu", ARMCPU
, has_mpu
, true);
1089 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
1090 * because the CPU initfn will have already set cpu->pmsav7_dregion to
1091 * the right value for that particular CPU type, and we don't want
1092 * to override that with an incorrect constant value.
1094 static Property arm_cpu_pmsav7_dregion_property
=
1095 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU
,
1097 qdev_prop_uint32
, uint32_t);
1099 static bool arm_get_pmu(Object
*obj
, Error
**errp
)
1101 ARMCPU
*cpu
= ARM_CPU(obj
);
1103 return cpu
->has_pmu
;
1106 static void arm_set_pmu(Object
*obj
, bool value
, Error
**errp
)
1108 ARMCPU
*cpu
= ARM_CPU(obj
);
1111 if (kvm_enabled() && !kvm_arm_pmu_supported(CPU(cpu
))) {
1112 error_setg(errp
, "'pmu' feature not supported by KVM on this host");
1115 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
1117 unset_feature(&cpu
->env
, ARM_FEATURE_PMU
);
1119 cpu
->has_pmu
= value
;
1122 unsigned int gt_cntfrq_period_ns(ARMCPU
*cpu
)
1125 * The exact approach to calculating guest ticks is:
1127 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz,
1128 * NANOSECONDS_PER_SECOND);
1130 * We don't do that. Rather we intentionally use integer division
1131 * truncation below and in the caller for the conversion of host monotonic
1132 * time to guest ticks to provide the exact inverse for the semantics of
1133 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so
1134 * it loses precision when representing frequencies where
1135 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to
1136 * provide an exact inverse leads to scheduling timers with negative
1137 * periods, which in turn leads to sticky behaviour in the guest.
1139 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor
1140 * cannot become zero.
1142 return NANOSECONDS_PER_SECOND
> cpu
->gt_cntfrq_hz
?
1143 NANOSECONDS_PER_SECOND
/ cpu
->gt_cntfrq_hz
: 1;
1146 void arm_cpu_post_init(Object
*obj
)
1148 ARMCPU
*cpu
= ARM_CPU(obj
);
1150 /* M profile implies PMSA. We have to do this here rather than
1151 * in realize with the other feature-implication checks because
1152 * we look at the PMSA bit to see if we should add some properties.
1154 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1155 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
1158 if (arm_feature(&cpu
->env
, ARM_FEATURE_CBAR
) ||
1159 arm_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
)) {
1160 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_cbar_property
);
1163 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1164 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_hivecs_property
);
1167 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1168 qdev_property_add_static(DEVICE(obj
), &arm_cpu_rvbar_property
);
1171 #ifndef CONFIG_USER_ONLY
1172 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
1173 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
1174 * prevent "has_el3" from existing on CPUs which cannot support EL3.
1176 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el3_property
);
1178 object_property_add_link(obj
, "secure-memory",
1180 (Object
**)&cpu
->secure_memory
,
1181 qdev_prop_allow_set_link_before_realize
,
1182 OBJ_PROP_LINK_STRONG
,
1186 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
)) {
1187 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el2_property
);
1191 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMU
)) {
1192 cpu
->has_pmu
= true;
1193 object_property_add_bool(obj
, "pmu", arm_get_pmu
, arm_set_pmu
,
1198 * Allow user to turn off VFP and Neon support, but only for TCG --
1199 * KVM does not currently allow us to lie to the guest about its
1200 * ID/feature registers, so the guest always sees what the host has.
1202 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)
1203 ? cpu_isar_feature(aa64_fp_simd
, cpu
)
1204 : cpu_isar_feature(aa32_vfp
, cpu
)) {
1205 cpu
->has_vfp
= true;
1206 if (!kvm_enabled()) {
1207 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_vfp_property
);
1211 if (arm_feature(&cpu
->env
, ARM_FEATURE_NEON
)) {
1212 cpu
->has_neon
= true;
1213 if (!kvm_enabled()) {
1214 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_neon_property
);
1218 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
) &&
1219 arm_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
)) {
1220 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_dsp_property
);
1223 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMSA
)) {
1224 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_mpu_property
);
1225 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1226 qdev_property_add_static(DEVICE(obj
),
1227 &arm_cpu_pmsav7_dregion_property
);
1231 if (arm_feature(&cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
1232 object_property_add_link(obj
, "idau", TYPE_IDAU_INTERFACE
, &cpu
->idau
,
1233 qdev_prop_allow_set_link_before_realize
,
1234 OBJ_PROP_LINK_STRONG
,
1237 * M profile: initial value of the Secure VTOR. We can't just use
1238 * a simple DEFINE_PROP_UINT32 for this because we want to permit
1239 * the property to be set after realize.
1241 object_property_add_uint32_ptr(obj
, "init-svtor",
1243 OBJ_PROP_FLAG_READWRITE
, &error_abort
);
1246 qdev_property_add_static(DEVICE(obj
), &arm_cpu_cfgend_property
);
1248 if (arm_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
)) {
1249 qdev_property_add_static(DEVICE(cpu
), &arm_cpu_gt_cntfrq_property
);
1253 static void arm_cpu_finalizefn(Object
*obj
)
1255 ARMCPU
*cpu
= ARM_CPU(obj
);
1256 ARMELChangeHook
*hook
, *next
;
1258 g_hash_table_destroy(cpu
->cp_regs
);
1260 QLIST_FOREACH_SAFE(hook
, &cpu
->pre_el_change_hooks
, node
, next
) {
1261 QLIST_REMOVE(hook
, node
);
1264 QLIST_FOREACH_SAFE(hook
, &cpu
->el_change_hooks
, node
, next
) {
1265 QLIST_REMOVE(hook
, node
);
1268 #ifndef CONFIG_USER_ONLY
1269 if (cpu
->pmu_timer
) {
1270 timer_del(cpu
->pmu_timer
);
1271 timer_deinit(cpu
->pmu_timer
);
1272 timer_free(cpu
->pmu_timer
);
1277 void arm_cpu_finalize_features(ARMCPU
*cpu
, Error
**errp
)
1279 Error
*local_err
= NULL
;
1281 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1282 arm_cpu_sve_finalize(cpu
, &local_err
);
1283 if (local_err
!= NULL
) {
1284 error_propagate(errp
, local_err
);
1290 static void arm_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
1292 CPUState
*cs
= CPU(dev
);
1293 ARMCPU
*cpu
= ARM_CPU(dev
);
1294 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(dev
);
1295 CPUARMState
*env
= &cpu
->env
;
1297 Error
*local_err
= NULL
;
1298 bool no_aa32
= false;
1300 /* If we needed to query the host kernel for the CPU features
1301 * then it's possible that might have failed in the initfn, but
1302 * this is the first point where we can report it.
1304 if (cpu
->host_cpu_probe_failed
) {
1305 if (!kvm_enabled()) {
1306 error_setg(errp
, "The 'host' CPU type can only be used with KVM");
1308 error_setg(errp
, "Failed to retrieve host CPU features");
1313 #ifndef CONFIG_USER_ONLY
1314 /* The NVIC and M-profile CPU are two halves of a single piece of
1315 * hardware; trying to use one without the other is a command line
1316 * error and will result in segfaults if not caught here.
1318 if (arm_feature(env
, ARM_FEATURE_M
)) {
1320 error_setg(errp
, "This board cannot be used with Cortex-M CPUs");
1325 error_setg(errp
, "This board can only be used with Cortex-M CPUs");
1333 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
1334 if (!cpu
->gt_cntfrq_hz
) {
1335 error_setg(errp
, "Invalid CNTFRQ: %"PRId64
"Hz",
1339 scale
= gt_cntfrq_period_ns(cpu
);
1341 scale
= GTIMER_SCALE
;
1344 cpu
->gt_timer
[GTIMER_PHYS
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1345 arm_gt_ptimer_cb
, cpu
);
1346 cpu
->gt_timer
[GTIMER_VIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1347 arm_gt_vtimer_cb
, cpu
);
1348 cpu
->gt_timer
[GTIMER_HYP
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1349 arm_gt_htimer_cb
, cpu
);
1350 cpu
->gt_timer
[GTIMER_SEC
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1351 arm_gt_stimer_cb
, cpu
);
1352 cpu
->gt_timer
[GTIMER_HYPVIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1353 arm_gt_hvtimer_cb
, cpu
);
1357 cpu_exec_realizefn(cs
, &local_err
);
1358 if (local_err
!= NULL
) {
1359 error_propagate(errp
, local_err
);
1363 arm_cpu_finalize_features(cpu
, &local_err
);
1364 if (local_err
!= NULL
) {
1365 error_propagate(errp
, local_err
);
1369 if (arm_feature(env
, ARM_FEATURE_AARCH64
) &&
1370 cpu
->has_vfp
!= cpu
->has_neon
) {
1372 * This is an architectural requirement for AArch64; AArch32 is
1373 * more flexible and permits VFP-no-Neon and Neon-no-VFP.
1376 "AArch64 CPUs must have both VFP and Neon or neither");
1380 if (!cpu
->has_vfp
) {
1384 t
= cpu
->isar
.id_aa64isar1
;
1385 t
= FIELD_DP64(t
, ID_AA64ISAR1
, JSCVT
, 0);
1386 cpu
->isar
.id_aa64isar1
= t
;
1388 t
= cpu
->isar
.id_aa64pfr0
;
1389 t
= FIELD_DP64(t
, ID_AA64PFR0
, FP
, 0xf);
1390 cpu
->isar
.id_aa64pfr0
= t
;
1392 u
= cpu
->isar
.id_isar6
;
1393 u
= FIELD_DP32(u
, ID_ISAR6
, JSCVT
, 0);
1394 cpu
->isar
.id_isar6
= u
;
1396 u
= cpu
->isar
.mvfr0
;
1397 u
= FIELD_DP32(u
, MVFR0
, FPSP
, 0);
1398 u
= FIELD_DP32(u
, MVFR0
, FPDP
, 0);
1399 u
= FIELD_DP32(u
, MVFR0
, FPTRAP
, 0);
1400 u
= FIELD_DP32(u
, MVFR0
, FPDIVIDE
, 0);
1401 u
= FIELD_DP32(u
, MVFR0
, FPSQRT
, 0);
1402 u
= FIELD_DP32(u
, MVFR0
, FPSHVEC
, 0);
1403 u
= FIELD_DP32(u
, MVFR0
, FPROUND
, 0);
1404 cpu
->isar
.mvfr0
= u
;
1406 u
= cpu
->isar
.mvfr1
;
1407 u
= FIELD_DP32(u
, MVFR1
, FPFTZ
, 0);
1408 u
= FIELD_DP32(u
, MVFR1
, FPDNAN
, 0);
1409 u
= FIELD_DP32(u
, MVFR1
, FPHP
, 0);
1410 cpu
->isar
.mvfr1
= u
;
1412 u
= cpu
->isar
.mvfr2
;
1413 u
= FIELD_DP32(u
, MVFR2
, FPMISC
, 0);
1414 cpu
->isar
.mvfr2
= u
;
1417 if (!cpu
->has_neon
) {
1421 unset_feature(env
, ARM_FEATURE_NEON
);
1423 t
= cpu
->isar
.id_aa64isar0
;
1424 t
= FIELD_DP64(t
, ID_AA64ISAR0
, DP
, 0);
1425 cpu
->isar
.id_aa64isar0
= t
;
1427 t
= cpu
->isar
.id_aa64isar1
;
1428 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FCMA
, 0);
1429 cpu
->isar
.id_aa64isar1
= t
;
1431 t
= cpu
->isar
.id_aa64pfr0
;
1432 t
= FIELD_DP64(t
, ID_AA64PFR0
, ADVSIMD
, 0xf);
1433 cpu
->isar
.id_aa64pfr0
= t
;
1435 u
= cpu
->isar
.id_isar5
;
1436 u
= FIELD_DP32(u
, ID_ISAR5
, RDM
, 0);
1437 u
= FIELD_DP32(u
, ID_ISAR5
, VCMA
, 0);
1438 cpu
->isar
.id_isar5
= u
;
1440 u
= cpu
->isar
.id_isar6
;
1441 u
= FIELD_DP32(u
, ID_ISAR6
, DP
, 0);
1442 u
= FIELD_DP32(u
, ID_ISAR6
, FHM
, 0);
1443 cpu
->isar
.id_isar6
= u
;
1445 u
= cpu
->isar
.mvfr1
;
1446 u
= FIELD_DP32(u
, MVFR1
, SIMDLS
, 0);
1447 u
= FIELD_DP32(u
, MVFR1
, SIMDINT
, 0);
1448 u
= FIELD_DP32(u
, MVFR1
, SIMDSP
, 0);
1449 u
= FIELD_DP32(u
, MVFR1
, SIMDHP
, 0);
1450 cpu
->isar
.mvfr1
= u
;
1452 u
= cpu
->isar
.mvfr2
;
1453 u
= FIELD_DP32(u
, MVFR2
, SIMDMISC
, 0);
1454 cpu
->isar
.mvfr2
= u
;
1457 if (!cpu
->has_neon
&& !cpu
->has_vfp
) {
1461 t
= cpu
->isar
.id_aa64isar0
;
1462 t
= FIELD_DP64(t
, ID_AA64ISAR0
, FHM
, 0);
1463 cpu
->isar
.id_aa64isar0
= t
;
1465 t
= cpu
->isar
.id_aa64isar1
;
1466 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FRINTTS
, 0);
1467 cpu
->isar
.id_aa64isar1
= t
;
1469 u
= cpu
->isar
.mvfr0
;
1470 u
= FIELD_DP32(u
, MVFR0
, SIMDREG
, 0);
1471 cpu
->isar
.mvfr0
= u
;
1473 /* Despite the name, this field covers both VFP and Neon */
1474 u
= cpu
->isar
.mvfr1
;
1475 u
= FIELD_DP32(u
, MVFR1
, SIMDFMAC
, 0);
1476 cpu
->isar
.mvfr1
= u
;
1479 if (arm_feature(env
, ARM_FEATURE_M
) && !cpu
->has_dsp
) {
1482 unset_feature(env
, ARM_FEATURE_THUMB_DSP
);
1484 u
= cpu
->isar
.id_isar1
;
1485 u
= FIELD_DP32(u
, ID_ISAR1
, EXTEND
, 1);
1486 cpu
->isar
.id_isar1
= u
;
1488 u
= cpu
->isar
.id_isar2
;
1489 u
= FIELD_DP32(u
, ID_ISAR2
, MULTU
, 1);
1490 u
= FIELD_DP32(u
, ID_ISAR2
, MULTS
, 1);
1491 cpu
->isar
.id_isar2
= u
;
1493 u
= cpu
->isar
.id_isar3
;
1494 u
= FIELD_DP32(u
, ID_ISAR3
, SIMD
, 1);
1495 u
= FIELD_DP32(u
, ID_ISAR3
, SATURATE
, 0);
1496 cpu
->isar
.id_isar3
= u
;
1499 /* Some features automatically imply others: */
1500 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1501 if (arm_feature(env
, ARM_FEATURE_M
)) {
1502 set_feature(env
, ARM_FEATURE_V7
);
1504 set_feature(env
, ARM_FEATURE_V7VE
);
1509 * There exist AArch64 cpus without AArch32 support. When KVM
1510 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
1511 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
1512 * As a general principle, we also do not make ID register
1513 * consistency checks anywhere unless using TCG, because only
1514 * for TCG would a consistency-check failure be a QEMU bug.
1516 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1517 no_aa32
= !cpu_isar_feature(aa64_aa32
, cpu
);
1520 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
1521 /* v7 Virtualization Extensions. In real hardware this implies
1522 * EL2 and also the presence of the Security Extensions.
1523 * For QEMU, for backwards-compatibility we implement some
1524 * CPUs or CPU configs which have no actual EL2 or EL3 but do
1525 * include the various other features that V7VE implies.
1526 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
1527 * Security Extensions is ARM_FEATURE_EL3.
1529 assert(!tcg_enabled() || no_aa32
||
1530 cpu_isar_feature(aa32_arm_div
, cpu
));
1531 set_feature(env
, ARM_FEATURE_LPAE
);
1532 set_feature(env
, ARM_FEATURE_V7
);
1534 if (arm_feature(env
, ARM_FEATURE_V7
)) {
1535 set_feature(env
, ARM_FEATURE_VAPA
);
1536 set_feature(env
, ARM_FEATURE_THUMB2
);
1537 set_feature(env
, ARM_FEATURE_MPIDR
);
1538 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1539 set_feature(env
, ARM_FEATURE_V6K
);
1541 set_feature(env
, ARM_FEATURE_V6
);
1544 /* Always define VBAR for V7 CPUs even if it doesn't exist in
1545 * non-EL3 configs. This is needed by some legacy boards.
1547 set_feature(env
, ARM_FEATURE_VBAR
);
1549 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
1550 set_feature(env
, ARM_FEATURE_V6
);
1551 set_feature(env
, ARM_FEATURE_MVFR
);
1553 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1554 set_feature(env
, ARM_FEATURE_V5
);
1555 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1556 assert(!tcg_enabled() || no_aa32
||
1557 cpu_isar_feature(aa32_jazelle
, cpu
));
1558 set_feature(env
, ARM_FEATURE_AUXCR
);
1561 if (arm_feature(env
, ARM_FEATURE_V5
)) {
1562 set_feature(env
, ARM_FEATURE_V4T
);
1564 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
1565 set_feature(env
, ARM_FEATURE_V7MP
);
1566 set_feature(env
, ARM_FEATURE_PXN
);
1568 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
1569 set_feature(env
, ARM_FEATURE_CBAR
);
1571 if (arm_feature(env
, ARM_FEATURE_THUMB2
) &&
1572 !arm_feature(env
, ARM_FEATURE_M
)) {
1573 set_feature(env
, ARM_FEATURE_THUMB_DSP
);
1577 * We rely on no XScale CPU having VFP so we can use the same bits in the
1578 * TB flags field for VECSTRIDE and XSCALE_CPAR.
1580 assert(arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
) ||
1581 !cpu_isar_feature(aa32_vfp_simd
, cpu
) ||
1582 !arm_feature(env
, ARM_FEATURE_XSCALE
));
1584 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1585 !arm_feature(env
, ARM_FEATURE_M
) &&
1586 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
1587 /* v7VMSA drops support for the old ARMv5 tiny pages, so we
1592 /* For CPUs which might have tiny 1K pages, or which have an
1593 * MPU and might have small region sizes, stick with 1K pages.
1597 if (!set_preferred_target_page_bits(pagebits
)) {
1598 /* This can only ever happen for hotplugging a CPU, or if
1599 * the board code incorrectly creates a CPU which it has
1600 * promised via minimum_page_size that it will not.
1602 error_setg(errp
, "This CPU requires a smaller page size than the "
1607 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
1608 * We don't support setting cluster ID ([16..23]) (known as Aff2
1609 * in later ARM ARM versions), or any of the higher affinity level fields,
1610 * so these bits always RAZ.
1612 if (cpu
->mp_affinity
== ARM64_AFFINITY_INVALID
) {
1613 cpu
->mp_affinity
= arm_cpu_mp_affinity(cs
->cpu_index
,
1614 ARM_DEFAULT_CPUS_PER_CLUSTER
);
1617 if (cpu
->reset_hivecs
) {
1618 cpu
->reset_sctlr
|= (1 << 13);
1622 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1623 cpu
->reset_sctlr
|= SCTLR_EE
;
1625 cpu
->reset_sctlr
|= SCTLR_B
;
1629 if (!cpu
->has_el3
) {
1630 /* If the has_el3 CPU property is disabled then we need to disable the
1633 unset_feature(env
, ARM_FEATURE_EL3
);
1635 /* Disable the security extension feature bits in the processor feature
1636 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
1638 cpu
->id_pfr1
&= ~0xf0;
1639 cpu
->isar
.id_aa64pfr0
&= ~0xf000;
1642 if (!cpu
->has_el2
) {
1643 unset_feature(env
, ARM_FEATURE_EL2
);
1646 if (!cpu
->has_pmu
) {
1647 unset_feature(env
, ARM_FEATURE_PMU
);
1649 if (arm_feature(env
, ARM_FEATURE_PMU
)) {
1652 if (!kvm_enabled()) {
1653 arm_register_pre_el_change_hook(cpu
, &pmu_pre_el_change
, 0);
1654 arm_register_el_change_hook(cpu
, &pmu_post_el_change
, 0);
1657 #ifndef CONFIG_USER_ONLY
1658 cpu
->pmu_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, arm_pmu_timer_cb
,
1662 cpu
->isar
.id_aa64dfr0
=
1663 FIELD_DP64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, PMUVER
, 0);
1664 cpu
->isar
.id_dfr0
= FIELD_DP32(cpu
->isar
.id_dfr0
, ID_DFR0
, PERFMON
, 0);
1669 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1670 /* Disable the hypervisor feature bits in the processor feature
1671 * registers if we don't have EL2. These are id_pfr1[15:12] and
1672 * id_aa64pfr0_el1[11:8].
1674 cpu
->isar
.id_aa64pfr0
&= ~0xf00;
1675 cpu
->id_pfr1
&= ~0xf000;
1678 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
1679 * to false or by setting pmsav7-dregion to 0.
1681 if (!cpu
->has_mpu
) {
1682 cpu
->pmsav7_dregion
= 0;
1684 if (cpu
->pmsav7_dregion
== 0) {
1685 cpu
->has_mpu
= false;
1688 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
1689 arm_feature(env
, ARM_FEATURE_V7
)) {
1690 uint32_t nr
= cpu
->pmsav7_dregion
;
1693 error_setg(errp
, "PMSAv7 MPU #regions invalid %" PRIu32
, nr
);
1698 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1700 env
->pmsav8
.rbar
[M_REG_NS
] = g_new0(uint32_t, nr
);
1701 env
->pmsav8
.rlar
[M_REG_NS
] = g_new0(uint32_t, nr
);
1702 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1703 env
->pmsav8
.rbar
[M_REG_S
] = g_new0(uint32_t, nr
);
1704 env
->pmsav8
.rlar
[M_REG_S
] = g_new0(uint32_t, nr
);
1707 env
->pmsav7
.drbar
= g_new0(uint32_t, nr
);
1708 env
->pmsav7
.drsr
= g_new0(uint32_t, nr
);
1709 env
->pmsav7
.dracr
= g_new0(uint32_t, nr
);
1714 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1715 uint32_t nr
= cpu
->sau_sregion
;
1718 error_setg(errp
, "v8M SAU #regions invalid %" PRIu32
, nr
);
1723 env
->sau
.rbar
= g_new0(uint32_t, nr
);
1724 env
->sau
.rlar
= g_new0(uint32_t, nr
);
1728 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
1729 set_feature(env
, ARM_FEATURE_VBAR
);
1732 register_cp_regs_for_features(cpu
);
1733 arm_cpu_register_gdb_regs_for_features(cpu
);
1735 init_cpreg_list(cpu
);
1737 #ifndef CONFIG_USER_ONLY
1738 MachineState
*ms
= MACHINE(qdev_get_machine());
1739 unsigned int smp_cpus
= ms
->smp
.cpus
;
1741 if (cpu
->has_el3
|| arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1744 if (!cpu
->secure_memory
) {
1745 cpu
->secure_memory
= cs
->memory
;
1747 cpu_address_space_init(cs
, ARMASIdx_S
, "cpu-secure-memory",
1748 cpu
->secure_memory
);
1752 cpu_address_space_init(cs
, ARMASIdx_NS
, "cpu-memory", cs
->memory
);
1754 /* No core_count specified, default to smp_cpus. */
1755 if (cpu
->core_count
== -1) {
1756 cpu
->core_count
= smp_cpus
;
1763 acc
->parent_realize(dev
, errp
);
1766 static ObjectClass
*arm_cpu_class_by_name(const char *cpu_model
)
1771 const char *cpunamestr
;
1773 cpuname
= g_strsplit(cpu_model
, ",", 1);
1774 cpunamestr
= cpuname
[0];
1775 #ifdef CONFIG_USER_ONLY
1776 /* For backwards compatibility usermode emulation allows "-cpu any",
1777 * which has the same semantics as "-cpu max".
1779 if (!strcmp(cpunamestr
, "any")) {
1783 typename
= g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr
);
1784 oc
= object_class_by_name(typename
);
1785 g_strfreev(cpuname
);
1787 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_ARM_CPU
) ||
1788 object_class_is_abstract(oc
)) {
1794 /* CPU models. These are not needed for the AArch64 linux-user build. */
1795 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1797 static const ARMCPRegInfo cortexa8_cp_reginfo
[] = {
1798 { .name
= "L2LOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 0,
1799 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1800 { .name
= "L2AUXCR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
1801 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1805 static void cortex_a8_initfn(Object
*obj
)
1807 ARMCPU
*cpu
= ARM_CPU(obj
);
1809 cpu
->dtb_compatible
= "arm,cortex-a8";
1810 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1811 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1812 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1813 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1814 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1815 cpu
->midr
= 0x410fc080;
1816 cpu
->reset_fpsid
= 0x410330c0;
1817 cpu
->isar
.mvfr0
= 0x11110222;
1818 cpu
->isar
.mvfr1
= 0x00011111;
1819 cpu
->ctr
= 0x82048004;
1820 cpu
->reset_sctlr
= 0x00c50078;
1821 cpu
->id_pfr0
= 0x1031;
1822 cpu
->id_pfr1
= 0x11;
1823 cpu
->isar
.id_dfr0
= 0x400;
1825 cpu
->isar
.id_mmfr0
= 0x31100003;
1826 cpu
->isar
.id_mmfr1
= 0x20000000;
1827 cpu
->isar
.id_mmfr2
= 0x01202000;
1828 cpu
->isar
.id_mmfr3
= 0x11;
1829 cpu
->isar
.id_isar0
= 0x00101111;
1830 cpu
->isar
.id_isar1
= 0x12112111;
1831 cpu
->isar
.id_isar2
= 0x21232031;
1832 cpu
->isar
.id_isar3
= 0x11112131;
1833 cpu
->isar
.id_isar4
= 0x00111142;
1834 cpu
->isar
.dbgdidr
= 0x15141000;
1835 cpu
->clidr
= (1 << 27) | (2 << 24) | 3;
1836 cpu
->ccsidr
[0] = 0xe007e01a; /* 16k L1 dcache. */
1837 cpu
->ccsidr
[1] = 0x2007e01a; /* 16k L1 icache. */
1838 cpu
->ccsidr
[2] = 0xf0000000; /* No L2 icache. */
1839 cpu
->reset_auxcr
= 2;
1840 define_arm_cp_regs(cpu
, cortexa8_cp_reginfo
);
1843 static const ARMCPRegInfo cortexa9_cp_reginfo
[] = {
1844 /* power_control should be set to maximum latency. Again,
1845 * default to 0 and set by private hook
1847 { .name
= "A9_PWRCTL", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
1848 .access
= PL1_RW
, .resetvalue
= 0,
1849 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_control
) },
1850 { .name
= "A9_DIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 1,
1851 .access
= PL1_RW
, .resetvalue
= 0,
1852 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_diagnostic
) },
1853 { .name
= "A9_PWRDIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 2,
1854 .access
= PL1_RW
, .resetvalue
= 0,
1855 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_diagnostic
) },
1856 { .name
= "NEONBUSY", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
1857 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1858 /* TLB lockdown control */
1859 { .name
= "TLB_LOCKR", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 2,
1860 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
1861 { .name
= "TLB_LOCKW", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 4,
1862 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
1863 { .name
= "TLB_VA", .cp
= 15, .crn
= 15, .crm
= 5, .opc1
= 5, .opc2
= 2,
1864 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1865 { .name
= "TLB_PA", .cp
= 15, .crn
= 15, .crm
= 6, .opc1
= 5, .opc2
= 2,
1866 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1867 { .name
= "TLB_ATTR", .cp
= 15, .crn
= 15, .crm
= 7, .opc1
= 5, .opc2
= 2,
1868 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1872 static void cortex_a9_initfn(Object
*obj
)
1874 ARMCPU
*cpu
= ARM_CPU(obj
);
1876 cpu
->dtb_compatible
= "arm,cortex-a9";
1877 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1878 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1879 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1880 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1881 /* Note that A9 supports the MP extensions even for
1882 * A9UP and single-core A9MP (which are both different
1883 * and valid configurations; we don't model A9UP).
1885 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
1886 set_feature(&cpu
->env
, ARM_FEATURE_CBAR
);
1887 cpu
->midr
= 0x410fc090;
1888 cpu
->reset_fpsid
= 0x41033090;
1889 cpu
->isar
.mvfr0
= 0x11110222;
1890 cpu
->isar
.mvfr1
= 0x01111111;
1891 cpu
->ctr
= 0x80038003;
1892 cpu
->reset_sctlr
= 0x00c50078;
1893 cpu
->id_pfr0
= 0x1031;
1894 cpu
->id_pfr1
= 0x11;
1895 cpu
->isar
.id_dfr0
= 0x000;
1897 cpu
->isar
.id_mmfr0
= 0x00100103;
1898 cpu
->isar
.id_mmfr1
= 0x20000000;
1899 cpu
->isar
.id_mmfr2
= 0x01230000;
1900 cpu
->isar
.id_mmfr3
= 0x00002111;
1901 cpu
->isar
.id_isar0
= 0x00101111;
1902 cpu
->isar
.id_isar1
= 0x13112111;
1903 cpu
->isar
.id_isar2
= 0x21232041;
1904 cpu
->isar
.id_isar3
= 0x11112131;
1905 cpu
->isar
.id_isar4
= 0x00111142;
1906 cpu
->isar
.dbgdidr
= 0x35141000;
1907 cpu
->clidr
= (1 << 27) | (1 << 24) | 3;
1908 cpu
->ccsidr
[0] = 0xe00fe019; /* 16k L1 dcache. */
1909 cpu
->ccsidr
[1] = 0x200fe019; /* 16k L1 icache. */
1910 define_arm_cp_regs(cpu
, cortexa9_cp_reginfo
);
1913 #ifndef CONFIG_USER_ONLY
1914 static uint64_t a15_l2ctlr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1916 MachineState
*ms
= MACHINE(qdev_get_machine());
1918 /* Linux wants the number of processors from here.
1919 * Might as well set the interrupt-controller bit too.
1921 return ((ms
->smp
.cpus
- 1) << 24) | (1 << 23);
1925 static const ARMCPRegInfo cortexa15_cp_reginfo
[] = {
1926 #ifndef CONFIG_USER_ONLY
1927 { .name
= "L2CTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
1928 .access
= PL1_RW
, .resetvalue
= 0, .readfn
= a15_l2ctlr_read
,
1929 .writefn
= arm_cp_write_ignore
, },
1931 { .name
= "L2ECTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 3,
1932 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1936 static void cortex_a7_initfn(Object
*obj
)
1938 ARMCPU
*cpu
= ARM_CPU(obj
);
1940 cpu
->dtb_compatible
= "arm,cortex-a7";
1941 set_feature(&cpu
->env
, ARM_FEATURE_V7VE
);
1942 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1943 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1944 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
1945 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1946 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
1947 set_feature(&cpu
->env
, ARM_FEATURE_EL2
);
1948 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1949 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
1950 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A7
;
1951 cpu
->midr
= 0x410fc075;
1952 cpu
->reset_fpsid
= 0x41023075;
1953 cpu
->isar
.mvfr0
= 0x10110222;
1954 cpu
->isar
.mvfr1
= 0x11111111;
1955 cpu
->ctr
= 0x84448003;
1956 cpu
->reset_sctlr
= 0x00c50078;
1957 cpu
->id_pfr0
= 0x00001131;
1958 cpu
->id_pfr1
= 0x00011011;
1959 cpu
->isar
.id_dfr0
= 0x02010555;
1960 cpu
->id_afr0
= 0x00000000;
1961 cpu
->isar
.id_mmfr0
= 0x10101105;
1962 cpu
->isar
.id_mmfr1
= 0x40000000;
1963 cpu
->isar
.id_mmfr2
= 0x01240000;
1964 cpu
->isar
.id_mmfr3
= 0x02102211;
1965 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
1966 * table 4-41 gives 0x02101110, which includes the arm div insns.
1968 cpu
->isar
.id_isar0
= 0x02101110;
1969 cpu
->isar
.id_isar1
= 0x13112111;
1970 cpu
->isar
.id_isar2
= 0x21232041;
1971 cpu
->isar
.id_isar3
= 0x11112131;
1972 cpu
->isar
.id_isar4
= 0x10011142;
1973 cpu
->isar
.dbgdidr
= 0x3515f005;
1974 cpu
->clidr
= 0x0a200023;
1975 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
1976 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
1977 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
1978 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
); /* Same as A15 */
1981 static void cortex_a15_initfn(Object
*obj
)
1983 ARMCPU
*cpu
= ARM_CPU(obj
);
1985 cpu
->dtb_compatible
= "arm,cortex-a15";
1986 set_feature(&cpu
->env
, ARM_FEATURE_V7VE
);
1987 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1988 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1989 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
1990 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1991 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
1992 set_feature(&cpu
->env
, ARM_FEATURE_EL2
);
1993 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1994 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
1995 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A15
;
1996 cpu
->midr
= 0x412fc0f1;
1997 cpu
->reset_fpsid
= 0x410430f0;
1998 cpu
->isar
.mvfr0
= 0x10110222;
1999 cpu
->isar
.mvfr1
= 0x11111111;
2000 cpu
->ctr
= 0x8444c004;
2001 cpu
->reset_sctlr
= 0x00c50078;
2002 cpu
->id_pfr0
= 0x00001131;
2003 cpu
->id_pfr1
= 0x00011011;
2004 cpu
->isar
.id_dfr0
= 0x02010555;
2005 cpu
->id_afr0
= 0x00000000;
2006 cpu
->isar
.id_mmfr0
= 0x10201105;
2007 cpu
->isar
.id_mmfr1
= 0x20000000;
2008 cpu
->isar
.id_mmfr2
= 0x01240000;
2009 cpu
->isar
.id_mmfr3
= 0x02102211;
2010 cpu
->isar
.id_isar0
= 0x02101110;
2011 cpu
->isar
.id_isar1
= 0x13112111;
2012 cpu
->isar
.id_isar2
= 0x21232041;
2013 cpu
->isar
.id_isar3
= 0x11112131;
2014 cpu
->isar
.id_isar4
= 0x10011142;
2015 cpu
->isar
.dbgdidr
= 0x3515f021;
2016 cpu
->clidr
= 0x0a200023;
2017 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
2018 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
2019 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
2020 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
);
2023 #ifndef TARGET_AARCH64
2024 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
2025 * otherwise, a CPU with as many features enabled as our emulation supports.
2026 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
2027 * this only needs to handle 32 bits.
2029 static void arm_max_initfn(Object
*obj
)
2031 ARMCPU
*cpu
= ARM_CPU(obj
);
2033 if (kvm_enabled()) {
2034 kvm_arm_set_cpu_features_from_host(cpu
);
2035 kvm_arm_add_vcpu_properties(obj
);
2037 cortex_a15_initfn(obj
);
2039 /* old-style VFP short-vector support */
2040 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPSHVEC
, 1);
2042 #ifdef CONFIG_USER_ONLY
2043 /* We don't set these in system emulation mode for the moment,
2044 * since we don't correctly set (all of) the ID registers to
2047 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
2051 t
= cpu
->isar
.id_isar5
;
2052 t
= FIELD_DP32(t
, ID_ISAR5
, AES
, 2);
2053 t
= FIELD_DP32(t
, ID_ISAR5
, SHA1
, 1);
2054 t
= FIELD_DP32(t
, ID_ISAR5
, SHA2
, 1);
2055 t
= FIELD_DP32(t
, ID_ISAR5
, CRC32
, 1);
2056 t
= FIELD_DP32(t
, ID_ISAR5
, RDM
, 1);
2057 t
= FIELD_DP32(t
, ID_ISAR5
, VCMA
, 1);
2058 cpu
->isar
.id_isar5
= t
;
2060 t
= cpu
->isar
.id_isar6
;
2061 t
= FIELD_DP32(t
, ID_ISAR6
, JSCVT
, 1);
2062 t
= FIELD_DP32(t
, ID_ISAR6
, DP
, 1);
2063 t
= FIELD_DP32(t
, ID_ISAR6
, FHM
, 1);
2064 t
= FIELD_DP32(t
, ID_ISAR6
, SB
, 1);
2065 t
= FIELD_DP32(t
, ID_ISAR6
, SPECRES
, 1);
2066 cpu
->isar
.id_isar6
= t
;
2068 t
= cpu
->isar
.mvfr1
;
2069 t
= FIELD_DP32(t
, MVFR1
, FPHP
, 2); /* v8.0 FP support */
2070 cpu
->isar
.mvfr1
= t
;
2072 t
= cpu
->isar
.mvfr2
;
2073 t
= FIELD_DP32(t
, MVFR2
, SIMDMISC
, 3); /* SIMD MaxNum */
2074 t
= FIELD_DP32(t
, MVFR2
, FPMISC
, 4); /* FP MaxNum */
2075 cpu
->isar
.mvfr2
= t
;
2077 t
= cpu
->isar
.id_mmfr3
;
2078 t
= FIELD_DP32(t
, ID_MMFR3
, PAN
, 2); /* ATS1E1 */
2079 cpu
->isar
.id_mmfr3
= t
;
2081 t
= cpu
->isar
.id_mmfr4
;
2082 t
= FIELD_DP32(t
, ID_MMFR4
, HPDS
, 1); /* AA32HPD */
2083 t
= FIELD_DP32(t
, ID_MMFR4
, AC2
, 1); /* ACTLR2, HACTLR2 */
2084 t
= FIELD_DP32(t
, ID_MMFR4
, CNP
, 1); /* TTCNP */
2085 t
= FIELD_DP32(t
, ID_MMFR4
, XNX
, 1); /* TTS2UXN */
2086 cpu
->isar
.id_mmfr4
= t
;
2093 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
2095 static const ARMCPUInfo arm_cpus
[] = {
2096 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
2097 { .name
= "cortex-a7", .initfn
= cortex_a7_initfn
},
2098 { .name
= "cortex-a8", .initfn
= cortex_a8_initfn
},
2099 { .name
= "cortex-a9", .initfn
= cortex_a9_initfn
},
2100 { .name
= "cortex-a15", .initfn
= cortex_a15_initfn
},
2101 #ifndef TARGET_AARCH64
2102 { .name
= "max", .initfn
= arm_max_initfn
},
2104 #ifdef CONFIG_USER_ONLY
2105 { .name
= "any", .initfn
= arm_max_initfn
},
2110 static Property arm_cpu_properties
[] = {
2111 DEFINE_PROP_BOOL("start-powered-off", ARMCPU
, start_powered_off
, false),
2112 DEFINE_PROP_UINT32("psci-conduit", ARMCPU
, psci_conduit
, 0),
2113 DEFINE_PROP_UINT64("midr", ARMCPU
, midr
, 0),
2114 DEFINE_PROP_UINT64("mp-affinity", ARMCPU
,
2115 mp_affinity
, ARM64_AFFINITY_INVALID
),
2116 DEFINE_PROP_INT32("node-id", ARMCPU
, node_id
, CPU_UNSET_NUMA_NODE_ID
),
2117 DEFINE_PROP_INT32("core-count", ARMCPU
, core_count
, -1),
2118 DEFINE_PROP_END_OF_LIST()
2121 static gchar
*arm_gdb_arch_name(CPUState
*cs
)
2123 ARMCPU
*cpu
= ARM_CPU(cs
);
2124 CPUARMState
*env
= &cpu
->env
;
2126 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
2127 return g_strdup("iwmmxt");
2129 return g_strdup("arm");
2132 static void arm_cpu_class_init(ObjectClass
*oc
, void *data
)
2134 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2135 CPUClass
*cc
= CPU_CLASS(acc
);
2136 DeviceClass
*dc
= DEVICE_CLASS(oc
);
2138 device_class_set_parent_realize(dc
, arm_cpu_realizefn
,
2139 &acc
->parent_realize
);
2141 device_class_set_props(dc
, arm_cpu_properties
);
2142 device_class_set_parent_reset(dc
, arm_cpu_reset
, &acc
->parent_reset
);
2144 cc
->class_by_name
= arm_cpu_class_by_name
;
2145 cc
->has_work
= arm_cpu_has_work
;
2146 cc
->cpu_exec_interrupt
= arm_cpu_exec_interrupt
;
2147 cc
->dump_state
= arm_cpu_dump_state
;
2148 cc
->set_pc
= arm_cpu_set_pc
;
2149 cc
->synchronize_from_tb
= arm_cpu_synchronize_from_tb
;
2150 cc
->gdb_read_register
= arm_cpu_gdb_read_register
;
2151 cc
->gdb_write_register
= arm_cpu_gdb_write_register
;
2152 #ifndef CONFIG_USER_ONLY
2153 cc
->do_interrupt
= arm_cpu_do_interrupt
;
2154 cc
->get_phys_page_attrs_debug
= arm_cpu_get_phys_page_attrs_debug
;
2155 cc
->asidx_from_attrs
= arm_asidx_from_attrs
;
2156 cc
->vmsd
= &vmstate_arm_cpu
;
2157 cc
->virtio_is_big_endian
= arm_cpu_virtio_is_big_endian
;
2158 cc
->write_elf64_note
= arm_cpu_write_elf64_note
;
2159 cc
->write_elf32_note
= arm_cpu_write_elf32_note
;
2161 cc
->gdb_num_core_regs
= 26;
2162 cc
->gdb_core_xml_file
= "arm-core.xml";
2163 cc
->gdb_arch_name
= arm_gdb_arch_name
;
2164 cc
->gdb_get_dynamic_xml
= arm_gdb_get_dynamic_xml
;
2165 cc
->gdb_stop_before_watchpoint
= true;
2166 cc
->disas_set_info
= arm_disas_set_info
;
2168 cc
->tcg_initialize
= arm_translate_init
;
2169 cc
->tlb_fill
= arm_cpu_tlb_fill
;
2170 cc
->debug_excp_handler
= arm_debug_excp_handler
;
2171 cc
->debug_check_watchpoint
= arm_debug_check_watchpoint
;
2172 #if !defined(CONFIG_USER_ONLY)
2173 cc
->do_unaligned_access
= arm_cpu_do_unaligned_access
;
2174 cc
->do_transaction_failed
= arm_cpu_do_transaction_failed
;
2175 cc
->adjust_watchpoint_address
= arm_adjust_watchpoint_address
;
2176 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
2181 static void arm_host_initfn(Object
*obj
)
2183 ARMCPU
*cpu
= ARM_CPU(obj
);
2185 kvm_arm_set_cpu_features_from_host(cpu
);
2186 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
2187 aarch64_add_sve_properties(obj
);
2189 kvm_arm_add_vcpu_properties(obj
);
2190 arm_cpu_post_init(obj
);
2193 static const TypeInfo host_arm_cpu_type_info
= {
2194 .name
= TYPE_ARM_HOST_CPU
,
2195 #ifdef TARGET_AARCH64
2196 .parent
= TYPE_AARCH64_CPU
,
2198 .parent
= TYPE_ARM_CPU
,
2200 .instance_init
= arm_host_initfn
,
2205 static void arm_cpu_instance_init(Object
*obj
)
2207 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(obj
);
2209 acc
->info
->initfn(obj
);
2210 arm_cpu_post_init(obj
);
2213 static void cpu_register_class_init(ObjectClass
*oc
, void *data
)
2215 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2220 void arm_cpu_register(const ARMCPUInfo
*info
)
2222 TypeInfo type_info
= {
2223 .parent
= TYPE_ARM_CPU
,
2224 .instance_size
= sizeof(ARMCPU
),
2225 .instance_init
= arm_cpu_instance_init
,
2226 .class_size
= sizeof(ARMCPUClass
),
2227 .class_init
= info
->class_init
?: cpu_register_class_init
,
2228 .class_data
= (void *)info
,
2231 type_info
.name
= g_strdup_printf("%s-" TYPE_ARM_CPU
, info
->name
);
2232 type_register(&type_info
);
2233 g_free((void *)type_info
.name
);
2236 static const TypeInfo arm_cpu_type_info
= {
2237 .name
= TYPE_ARM_CPU
,
2239 .instance_size
= sizeof(ARMCPU
),
2240 .instance_init
= arm_cpu_initfn
,
2241 .instance_finalize
= arm_cpu_finalizefn
,
2243 .class_size
= sizeof(ARMCPUClass
),
2244 .class_init
= arm_cpu_class_init
,
2247 static const TypeInfo idau_interface_type_info
= {
2248 .name
= TYPE_IDAU_INTERFACE
,
2249 .parent
= TYPE_INTERFACE
,
2250 .class_size
= sizeof(IDAUInterfaceClass
),
2253 static void arm_cpu_register_types(void)
2255 const size_t cpu_count
= ARRAY_SIZE(arm_cpus
);
2257 type_register_static(&arm_cpu_type_info
);
2260 type_register_static(&host_arm_cpu_type_info
);
2266 type_register_static(&idau_interface_type_info
);
2267 for (i
= 0; i
< cpu_count
; ++i
) {
2268 arm_cpu_register(&arm_cpus
[i
]);
2273 type_init(arm_cpu_register_types
)