4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu/osdep.h"
22 #include "qemu/qemu-print.h"
23 #include "qemu/timer.h"
25 #include "exec/page-vary.h"
26 #include "target/arm/idau.h"
27 #include "qemu/module.h"
28 #include "qapi/error.h"
31 #include "hw/core/tcg-cpu-ops.h"
32 #endif /* CONFIG_TCG */
33 #include "internals.h"
34 #include "cpu-features.h"
35 #include "exec/exec-all.h"
36 #include "hw/qdev-properties.h"
37 #if !defined(CONFIG_USER_ONLY)
38 #include "hw/loader.h"
39 #include "hw/boards.h"
41 #include "hw/intc/armv7m_nvic.h"
42 #endif /* CONFIG_TCG */
43 #endif /* !CONFIG_USER_ONLY */
44 #include "sysemu/tcg.h"
45 #include "sysemu/qtest.h"
46 #include "sysemu/hw_accel.h"
48 #include "disas/capstone.h"
49 #include "fpu/softfloat.h"
51 #include "target/arm/cpu-qom.h"
53 static void arm_cpu_set_pc(CPUState
*cs
, vaddr value
)
55 ARMCPU
*cpu
= ARM_CPU(cs
);
56 CPUARMState
*env
= &cpu
->env
;
62 env
->regs
[15] = value
& ~1;
63 env
->thumb
= value
& 1;
67 static vaddr
arm_cpu_get_pc(CPUState
*cs
)
69 ARMCPU
*cpu
= ARM_CPU(cs
);
70 CPUARMState
*env
= &cpu
->env
;
80 void arm_cpu_synchronize_from_tb(CPUState
*cs
,
81 const TranslationBlock
*tb
)
83 /* The program counter is always up to date with CF_PCREL. */
84 if (!(tb_cflags(tb
) & CF_PCREL
)) {
85 CPUARMState
*env
= cpu_env(cs
);
87 * It's OK to look at env for the current mode here, because it's
88 * never possible for an AArch64 TB to chain to an AArch32 TB.
93 env
->regs
[15] = tb
->pc
;
98 void arm_restore_state_to_opc(CPUState
*cs
,
99 const TranslationBlock
*tb
,
100 const uint64_t *data
)
102 CPUARMState
*env
= cpu_env(cs
);
105 if (tb_cflags(tb
) & CF_PCREL
) {
106 env
->pc
= (env
->pc
& TARGET_PAGE_MASK
) | data
[0];
110 env
->condexec_bits
= 0;
111 env
->exception
.syndrome
= data
[2] << ARM_INSN_START_WORD2_SHIFT
;
113 if (tb_cflags(tb
) & CF_PCREL
) {
114 env
->regs
[15] = (env
->regs
[15] & TARGET_PAGE_MASK
) | data
[0];
116 env
->regs
[15] = data
[0];
118 env
->condexec_bits
= data
[1];
119 env
->exception
.syndrome
= data
[2] << ARM_INSN_START_WORD2_SHIFT
;
122 #endif /* CONFIG_TCG */
124 static bool arm_cpu_has_work(CPUState
*cs
)
126 ARMCPU
*cpu
= ARM_CPU(cs
);
128 return (cpu
->power_state
!= PSCI_OFF
)
129 && cs
->interrupt_request
&
130 (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
131 | CPU_INTERRUPT_VFIQ
| CPU_INTERRUPT_VIRQ
| CPU_INTERRUPT_VSERR
132 | CPU_INTERRUPT_EXITTB
);
135 void arm_register_pre_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
138 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
141 entry
->opaque
= opaque
;
143 QLIST_INSERT_HEAD(&cpu
->pre_el_change_hooks
, entry
, node
);
146 void arm_register_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
149 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
152 entry
->opaque
= opaque
;
154 QLIST_INSERT_HEAD(&cpu
->el_change_hooks
, entry
, node
);
157 static void cp_reg_reset(gpointer key
, gpointer value
, gpointer opaque
)
159 /* Reset a single ARMCPRegInfo register */
160 ARMCPRegInfo
*ri
= value
;
161 ARMCPU
*cpu
= opaque
;
163 if (ri
->type
& (ARM_CP_SPECIAL_MASK
| ARM_CP_ALIAS
)) {
168 ri
->resetfn(&cpu
->env
, ri
);
172 /* A zero offset is never possible as it would be regs[0]
173 * so we use it to indicate that reset is being handled elsewhere.
174 * This is basically only used for fields in non-core coprocessors
175 * (like the pxa2xx ones).
177 if (!ri
->fieldoffset
) {
181 if (cpreg_field_is_64bit(ri
)) {
182 CPREG_FIELD64(&cpu
->env
, ri
) = ri
->resetvalue
;
184 CPREG_FIELD32(&cpu
->env
, ri
) = ri
->resetvalue
;
188 static void cp_reg_check_reset(gpointer key
, gpointer value
, gpointer opaque
)
190 /* Purely an assertion check: we've already done reset once,
191 * so now check that running the reset for the cpreg doesn't
192 * change its value. This traps bugs where two different cpregs
193 * both try to reset the same state field but to different values.
195 ARMCPRegInfo
*ri
= value
;
196 ARMCPU
*cpu
= opaque
;
197 uint64_t oldvalue
, newvalue
;
199 if (ri
->type
& (ARM_CP_SPECIAL_MASK
| ARM_CP_ALIAS
| ARM_CP_NO_RAW
)) {
203 oldvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
204 cp_reg_reset(key
, value
, opaque
);
205 newvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
206 assert(oldvalue
== newvalue
);
209 static void arm_cpu_reset_hold(Object
*obj
)
211 CPUState
*s
= CPU(obj
);
212 ARMCPU
*cpu
= ARM_CPU(s
);
213 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(cpu
);
214 CPUARMState
*env
= &cpu
->env
;
216 if (acc
->parent_phases
.hold
) {
217 acc
->parent_phases
.hold(obj
);
220 memset(env
, 0, offsetof(CPUARMState
, end_reset_fields
));
222 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_reset
, cpu
);
223 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_check_reset
, cpu
);
225 env
->vfp
.xregs
[ARM_VFP_FPSID
] = cpu
->reset_fpsid
;
226 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = cpu
->isar
.mvfr0
;
227 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = cpu
->isar
.mvfr1
;
228 env
->vfp
.xregs
[ARM_VFP_MVFR2
] = cpu
->isar
.mvfr2
;
230 cpu
->power_state
= s
->start_powered_off
? PSCI_OFF
: PSCI_ON
;
232 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
233 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
236 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
237 /* 64 bit CPUs always start in 64 bit mode */
239 #if defined(CONFIG_USER_ONLY)
240 env
->pstate
= PSTATE_MODE_EL0t
;
241 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
242 env
->cp15
.sctlr_el
[1] |= SCTLR_UCT
| SCTLR_UCI
| SCTLR_DZE
;
243 /* Enable all PAC keys. */
244 env
->cp15
.sctlr_el
[1] |= (SCTLR_EnIA
| SCTLR_EnIB
|
245 SCTLR_EnDA
| SCTLR_EnDB
);
246 /* Trap on btype=3 for PACIxSP. */
247 env
->cp15
.sctlr_el
[1] |= SCTLR_BT0
;
248 /* Trap on implementation defined registers. */
249 if (cpu_isar_feature(aa64_tidcp1
, cpu
)) {
250 env
->cp15
.sctlr_el
[1] |= SCTLR_TIDCP
;
252 /* and to the FP/Neon instructions */
253 env
->cp15
.cpacr_el1
= FIELD_DP64(env
->cp15
.cpacr_el1
,
255 /* and to the SVE instructions, with default vector length */
256 if (cpu_isar_feature(aa64_sve
, cpu
)) {
257 env
->cp15
.cpacr_el1
= FIELD_DP64(env
->cp15
.cpacr_el1
,
259 env
->vfp
.zcr_el
[1] = cpu
->sve_default_vq
- 1;
261 /* and for SME instructions, with default vector length, and TPIDR2 */
262 if (cpu_isar_feature(aa64_sme
, cpu
)) {
263 env
->cp15
.sctlr_el
[1] |= SCTLR_EnTP2
;
264 env
->cp15
.cpacr_el1
= FIELD_DP64(env
->cp15
.cpacr_el1
,
266 env
->vfp
.smcr_el
[1] = cpu
->sme_default_vq
- 1;
267 if (cpu_isar_feature(aa64_sme_fa64
, cpu
)) {
268 env
->vfp
.smcr_el
[1] = FIELD_DP64(env
->vfp
.smcr_el
[1],
273 * Enable 48-bit address space (TODO: take reserved_va into account).
274 * Enable TBI0 but not TBI1.
275 * Note that this must match useronly_clean_ptr.
277 env
->cp15
.tcr_el
[1] = 5 | (1ULL << 37);
280 if (cpu_isar_feature(aa64_mte
, cpu
)) {
281 /* Enable tag access, but leave TCF0 as No Effect (0). */
282 env
->cp15
.sctlr_el
[1] |= SCTLR_ATA0
;
284 * Exclude all tags, so that tag 0 is always used.
285 * This corresponds to Linux current->thread.gcr_incl = 0.
287 * Set RRND, so that helper_irg() will generate a seed later.
288 * Here in cpu_reset(), the crypto subsystem has not yet been
291 env
->cp15
.gcr_el1
= 0x1ffff;
294 * Disable access to SCXTNUM_EL0 from CSV2_1p2.
295 * This is not yet exposed from the Linux kernel in any way.
297 env
->cp15
.sctlr_el
[1] |= SCTLR_TSCXT
;
298 /* Disable access to Debug Communication Channel (DCC). */
299 env
->cp15
.mdscr_el1
|= 1 << 12;
300 /* Enable FEAT_MOPS */
301 env
->cp15
.sctlr_el
[1] |= SCTLR_MSCEN
;
303 /* Reset into the highest available EL */
304 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
305 env
->pstate
= PSTATE_MODE_EL3h
;
306 } else if (arm_feature(env
, ARM_FEATURE_EL2
)) {
307 env
->pstate
= PSTATE_MODE_EL2h
;
309 env
->pstate
= PSTATE_MODE_EL1h
;
312 /* Sample rvbar at reset. */
313 env
->cp15
.rvbar
= cpu
->rvbar_prop
;
314 env
->pc
= env
->cp15
.rvbar
;
317 #if defined(CONFIG_USER_ONLY)
318 /* Userspace expects access to cp10 and cp11 for FP/Neon */
319 env
->cp15
.cpacr_el1
= FIELD_DP64(env
->cp15
.cpacr_el1
,
321 env
->cp15
.cpacr_el1
= FIELD_DP64(env
->cp15
.cpacr_el1
,
324 if (arm_feature(env
, ARM_FEATURE_V8
)) {
325 env
->cp15
.rvbar
= cpu
->rvbar_prop
;
326 env
->regs
[15] = cpu
->rvbar_prop
;
330 #if defined(CONFIG_USER_ONLY)
331 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
332 /* For user mode we must enable access to coprocessors */
333 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
334 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
335 env
->cp15
.c15_cpar
= 3;
336 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
337 env
->cp15
.c15_cpar
= 1;
342 * If the highest available EL is EL2, AArch32 will start in Hyp
343 * mode; otherwise it starts in SVC. Note that if we start in
344 * AArch64 then these values in the uncached_cpsr will be ignored.
346 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
347 !arm_feature(env
, ARM_FEATURE_EL3
)) {
348 env
->uncached_cpsr
= ARM_CPU_MODE_HYP
;
350 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
;
352 env
->daif
= PSTATE_D
| PSTATE_A
| PSTATE_I
| PSTATE_F
;
354 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
355 * executing as AArch32 then check if highvecs are enabled and
356 * adjust the PC accordingly.
358 if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
359 env
->regs
[15] = 0xFFFF0000;
362 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
365 if (arm_feature(env
, ARM_FEATURE_M
)) {
366 #ifndef CONFIG_USER_ONLY
367 uint32_t initial_msp
; /* Loaded from 0x0 */
368 uint32_t initial_pc
; /* Loaded from 0x4 */
373 if (cpu_isar_feature(aa32_lob
, cpu
)) {
375 * LTPSIZE is constant 4 if MVE not implemented, and resets
376 * to an UNKNOWN value if MVE is implemented. We choose to
379 env
->v7m
.ltpsize
= 4;
380 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */
381 env
->v7m
.fpdscr
[M_REG_NS
] = 4 << FPCR_LTPSIZE_SHIFT
;
382 env
->v7m
.fpdscr
[M_REG_S
] = 4 << FPCR_LTPSIZE_SHIFT
;
385 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
386 env
->v7m
.secure
= true;
388 /* This bit resets to 0 if security is supported, but 1 if
389 * it is not. The bit is not present in v7M, but we set it
390 * here so we can avoid having to make checks on it conditional
391 * on ARM_FEATURE_V8 (we don't let the guest see the bit).
393 env
->v7m
.aircr
= R_V7M_AIRCR_BFHFNMINS_MASK
;
395 * Set NSACR to indicate "NS access permitted to everything";
396 * this avoids having to have all the tests of it being
397 * conditional on ARM_FEATURE_M_SECURITY. Note also that from
398 * v8.1M the guest-visible value of NSACR in a CPU without the
399 * Security Extension is 0xcff.
401 env
->v7m
.nsacr
= 0xcff;
404 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
405 * that it resets to 1, so QEMU always does that rather than making
406 * it dependent on CPU model. In v8M it is RES1.
408 env
->v7m
.ccr
[M_REG_NS
] = R_V7M_CCR_STKALIGN_MASK
;
409 env
->v7m
.ccr
[M_REG_S
] = R_V7M_CCR_STKALIGN_MASK
;
410 if (arm_feature(env
, ARM_FEATURE_V8
)) {
411 /* in v8M the NONBASETHRDENA bit [0] is RES1 */
412 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
413 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
415 if (!arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
416 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
417 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
420 if (cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
421 env
->v7m
.fpccr
[M_REG_NS
] = R_V7M_FPCCR_ASPEN_MASK
;
422 env
->v7m
.fpccr
[M_REG_S
] = R_V7M_FPCCR_ASPEN_MASK
|
423 R_V7M_FPCCR_LSPEN_MASK
| R_V7M_FPCCR_S_MASK
;
426 #ifndef CONFIG_USER_ONLY
427 /* Unlike A/R profile, M profile defines the reset LR value */
428 env
->regs
[14] = 0xffffffff;
430 env
->v7m
.vecbase
[M_REG_S
] = cpu
->init_svtor
& 0xffffff80;
431 env
->v7m
.vecbase
[M_REG_NS
] = cpu
->init_nsvtor
& 0xffffff80;
433 /* Load the initial SP and PC from offset 0 and 4 in the vector table */
434 vecbase
= env
->v7m
.vecbase
[env
->v7m
.secure
];
435 rom
= rom_ptr_for_as(s
->as
, vecbase
, 8);
437 /* Address zero is covered by ROM which hasn't yet been
438 * copied into physical memory.
440 initial_msp
= ldl_p(rom
);
441 initial_pc
= ldl_p(rom
+ 4);
443 /* Address zero not covered by a ROM blob, or the ROM blob
444 * is in non-modifiable memory and this is a second reset after
445 * it got copied into memory. In the latter case, rom_ptr
446 * will return a NULL pointer and we should use ldl_phys instead.
448 initial_msp
= ldl_phys(s
->as
, vecbase
);
449 initial_pc
= ldl_phys(s
->as
, vecbase
+ 4);
452 qemu_log_mask(CPU_LOG_INT
,
453 "Loaded reset SP 0x%x PC 0x%x from vector table\n",
454 initial_msp
, initial_pc
);
456 env
->regs
[13] = initial_msp
& 0xFFFFFFFC;
457 env
->regs
[15] = initial_pc
& ~1;
458 env
->thumb
= initial_pc
& 1;
461 * For user mode we run non-secure and with access to the FPU.
462 * The FPU context is active (ie does not need further setup)
463 * and is owned by non-secure.
465 env
->v7m
.secure
= false;
466 env
->v7m
.nsacr
= 0xcff;
467 env
->v7m
.cpacr
[M_REG_NS
] = 0xf0ffff;
468 env
->v7m
.fpccr
[M_REG_S
] &=
469 ~(R_V7M_FPCCR_LSPEN_MASK
| R_V7M_FPCCR_S_MASK
);
470 env
->v7m
.control
[M_REG_S
] |= R_V7M_CONTROL_FPCA_MASK
;
474 /* M profile requires that reset clears the exclusive monitor;
475 * A profile does not, but clearing it makes more sense than having it
476 * set with an exclusive access on address zero.
478 arm_clear_exclusive(env
);
480 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
481 if (cpu
->pmsav7_dregion
> 0) {
482 if (arm_feature(env
, ARM_FEATURE_V8
)) {
483 memset(env
->pmsav8
.rbar
[M_REG_NS
], 0,
484 sizeof(*env
->pmsav8
.rbar
[M_REG_NS
])
485 * cpu
->pmsav7_dregion
);
486 memset(env
->pmsav8
.rlar
[M_REG_NS
], 0,
487 sizeof(*env
->pmsav8
.rlar
[M_REG_NS
])
488 * cpu
->pmsav7_dregion
);
489 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
490 memset(env
->pmsav8
.rbar
[M_REG_S
], 0,
491 sizeof(*env
->pmsav8
.rbar
[M_REG_S
])
492 * cpu
->pmsav7_dregion
);
493 memset(env
->pmsav8
.rlar
[M_REG_S
], 0,
494 sizeof(*env
->pmsav8
.rlar
[M_REG_S
])
495 * cpu
->pmsav7_dregion
);
497 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
498 memset(env
->pmsav7
.drbar
, 0,
499 sizeof(*env
->pmsav7
.drbar
) * cpu
->pmsav7_dregion
);
500 memset(env
->pmsav7
.drsr
, 0,
501 sizeof(*env
->pmsav7
.drsr
) * cpu
->pmsav7_dregion
);
502 memset(env
->pmsav7
.dracr
, 0,
503 sizeof(*env
->pmsav7
.dracr
) * cpu
->pmsav7_dregion
);
507 if (cpu
->pmsav8r_hdregion
> 0) {
508 memset(env
->pmsav8
.hprbar
, 0,
509 sizeof(*env
->pmsav8
.hprbar
) * cpu
->pmsav8r_hdregion
);
510 memset(env
->pmsav8
.hprlar
, 0,
511 sizeof(*env
->pmsav8
.hprlar
) * cpu
->pmsav8r_hdregion
);
514 env
->pmsav7
.rnr
[M_REG_NS
] = 0;
515 env
->pmsav7
.rnr
[M_REG_S
] = 0;
516 env
->pmsav8
.mair0
[M_REG_NS
] = 0;
517 env
->pmsav8
.mair0
[M_REG_S
] = 0;
518 env
->pmsav8
.mair1
[M_REG_NS
] = 0;
519 env
->pmsav8
.mair1
[M_REG_S
] = 0;
522 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
523 if (cpu
->sau_sregion
> 0) {
524 memset(env
->sau
.rbar
, 0, sizeof(*env
->sau
.rbar
) * cpu
->sau_sregion
);
525 memset(env
->sau
.rlar
, 0, sizeof(*env
->sau
.rlar
) * cpu
->sau_sregion
);
528 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
529 * the Cortex-M33 does.
534 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
535 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
536 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
537 set_default_nan_mode(1, &env
->vfp
.standard_fp_status_f16
);
538 set_float_detect_tininess(float_tininess_before_rounding
,
539 &env
->vfp
.fp_status
);
540 set_float_detect_tininess(float_tininess_before_rounding
,
541 &env
->vfp
.standard_fp_status
);
542 set_float_detect_tininess(float_tininess_before_rounding
,
543 &env
->vfp
.fp_status_f16
);
544 set_float_detect_tininess(float_tininess_before_rounding
,
545 &env
->vfp
.standard_fp_status_f16
);
546 #ifndef CONFIG_USER_ONLY
548 kvm_arm_reset_vcpu(cpu
);
553 hw_breakpoint_update_all(cpu
);
554 hw_watchpoint_update_all(cpu
);
556 arm_rebuild_hflags(env
);
560 void arm_emulate_firmware_reset(CPUState
*cpustate
, int target_el
)
562 ARMCPU
*cpu
= ARM_CPU(cpustate
);
563 CPUARMState
*env
= &cpu
->env
;
564 bool have_el3
= arm_feature(env
, ARM_FEATURE_EL3
);
565 bool have_el2
= arm_feature(env
, ARM_FEATURE_EL2
);
568 * Check we have the EL we're aiming for. If that is the
569 * highest implemented EL, then cpu_reset has already done
583 if (!have_el3
&& !have_el2
) {
588 g_assert_not_reached();
593 * Set the EL3 state so code can run at EL2. This should match
594 * the requirements set by Linux in its booting spec.
597 env
->cp15
.scr_el3
|= SCR_RW
;
598 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
599 env
->cp15
.scr_el3
|= SCR_API
| SCR_APK
;
601 if (cpu_isar_feature(aa64_mte
, cpu
)) {
602 env
->cp15
.scr_el3
|= SCR_ATA
;
604 if (cpu_isar_feature(aa64_sve
, cpu
)) {
605 env
->cp15
.cptr_el
[3] |= R_CPTR_EL3_EZ_MASK
;
606 env
->vfp
.zcr_el
[3] = 0xf;
608 if (cpu_isar_feature(aa64_sme
, cpu
)) {
609 env
->cp15
.cptr_el
[3] |= R_CPTR_EL3_ESM_MASK
;
610 env
->cp15
.scr_el3
|= SCR_ENTP2
;
611 env
->vfp
.smcr_el
[3] = 0xf;
613 if (cpu_isar_feature(aa64_hcx
, cpu
)) {
614 env
->cp15
.scr_el3
|= SCR_HXEN
;
616 if (cpu_isar_feature(aa64_fgt
, cpu
)) {
617 env
->cp15
.scr_el3
|= SCR_FGTEN
;
621 if (target_el
== 2) {
622 /* If the guest is at EL2 then Linux expects the HVC insn to work */
623 env
->cp15
.scr_el3
|= SCR_HCE
;
626 /* Put CPU into non-secure state */
627 env
->cp15
.scr_el3
|= SCR_NS
;
628 /* Set NSACR.{CP11,CP10} so NS can access the FPU */
629 env
->cp15
.nsacr
|= 3 << 10;
632 if (have_el2
&& target_el
< 2) {
633 /* Set EL2 state so code can run at EL1. */
635 env
->cp15
.hcr_el2
|= HCR_RW
;
639 /* Set the CPU to the desired state */
641 env
->pstate
= aarch64_pstate_mode(target_el
, true);
643 static const uint32_t mode_for_el
[] = {
650 cpsr_write(env
, mode_for_el
[target_el
], CPSR_M
, CPSRWriteRaw
);
655 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
657 static inline bool arm_excp_unmasked(CPUState
*cs
, unsigned int excp_idx
,
658 unsigned int target_el
,
659 unsigned int cur_el
, bool secure
,
662 CPUARMState
*env
= cpu_env(cs
);
663 bool pstate_unmasked
;
664 bool unmasked
= false;
667 * Don't take exceptions if they target a lower EL.
668 * This check should catch any exceptions that would not be taken
671 if (cur_el
> target_el
) {
677 pstate_unmasked
= !(env
->daif
& PSTATE_F
);
681 pstate_unmasked
= !(env
->daif
& PSTATE_I
);
685 if (!(hcr_el2
& HCR_FMO
) || (hcr_el2
& HCR_TGE
)) {
686 /* VFIQs are only taken when hypervized. */
689 return !(env
->daif
& PSTATE_F
);
691 if (!(hcr_el2
& HCR_IMO
) || (hcr_el2
& HCR_TGE
)) {
692 /* VIRQs are only taken when hypervized. */
695 return !(env
->daif
& PSTATE_I
);
697 if (!(hcr_el2
& HCR_AMO
) || (hcr_el2
& HCR_TGE
)) {
698 /* VIRQs are only taken when hypervized. */
701 return !(env
->daif
& PSTATE_A
);
703 g_assert_not_reached();
707 * Use the target EL, current execution state and SCR/HCR settings to
708 * determine whether the corresponding CPSR bit is used to mask the
711 if ((target_el
> cur_el
) && (target_el
!= 1)) {
712 /* Exceptions targeting a higher EL may not be maskable */
713 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
717 * According to ARM DDI 0487H.a, an interrupt can be masked
718 * when HCR_E2H and HCR_TGE are both set regardless of the
719 * current Security state. Note that we need to revisit this
720 * part again once we need to support NMI.
722 if ((hcr_el2
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
727 /* Interrupt cannot be masked when the target EL is 3 */
731 g_assert_not_reached();
735 * The old 32-bit-only environment has a more complicated
736 * masking setup. HCR and SCR bits not only affect interrupt
737 * routing but also change the behaviour of masking.
744 * If FIQs are routed to EL3 or EL2 then there are cases where
745 * we override the CPSR.F in determining if the exception is
746 * masked or not. If neither of these are set then we fall back
747 * to the CPSR.F setting otherwise we further assess the state
750 hcr
= hcr_el2
& HCR_FMO
;
751 scr
= (env
->cp15
.scr_el3
& SCR_FIQ
);
754 * When EL3 is 32-bit, the SCR.FW bit controls whether the
755 * CPSR.F bit masks FIQ interrupts when taken in non-secure
756 * state. If SCR.FW is set then FIQs can be masked by CPSR.F
757 * when non-secure but only when FIQs are only routed to EL3.
759 scr
= scr
&& !((env
->cp15
.scr_el3
& SCR_FW
) && !hcr
);
763 * When EL3 execution state is 32-bit, if HCR.IMO is set then
764 * we may override the CPSR.I masking when in non-secure state.
765 * The SCR.IRQ setting has already been taken into consideration
766 * when setting the target EL, so it does not have a further
769 hcr
= hcr_el2
& HCR_IMO
;
773 g_assert_not_reached();
776 if ((scr
|| hcr
) && !secure
) {
783 * The PSTATE bits only mask the interrupt if we have not overridden the
786 return unmasked
|| pstate_unmasked
;
789 static bool arm_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
791 CPUClass
*cc
= CPU_GET_CLASS(cs
);
792 CPUARMState
*env
= cpu_env(cs
);
793 uint32_t cur_el
= arm_current_el(env
);
794 bool secure
= arm_is_secure(env
);
795 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
799 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */
801 if (interrupt_request
& CPU_INTERRUPT_FIQ
) {
803 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
804 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
805 cur_el
, secure
, hcr_el2
)) {
809 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
811 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
812 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
813 cur_el
, secure
, hcr_el2
)) {
817 if (interrupt_request
& CPU_INTERRUPT_VIRQ
) {
818 excp_idx
= EXCP_VIRQ
;
820 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
821 cur_el
, secure
, hcr_el2
)) {
825 if (interrupt_request
& CPU_INTERRUPT_VFIQ
) {
826 excp_idx
= EXCP_VFIQ
;
828 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
829 cur_el
, secure
, hcr_el2
)) {
833 if (interrupt_request
& CPU_INTERRUPT_VSERR
) {
834 excp_idx
= EXCP_VSERR
;
836 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
837 cur_el
, secure
, hcr_el2
)) {
838 /* Taking a virtual abort clears HCR_EL2.VSE */
839 env
->cp15
.hcr_el2
&= ~HCR_VSE
;
840 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VSERR
);
847 cs
->exception_index
= excp_idx
;
848 env
->exception
.target_el
= target_el
;
849 cc
->tcg_ops
->do_interrupt(cs
);
853 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
855 void arm_cpu_update_virq(ARMCPU
*cpu
)
858 * Update the interrupt level for VIRQ, which is the logical OR of
859 * the HCR_EL2.VI bit and the input line level from the GIC.
861 CPUARMState
*env
= &cpu
->env
;
862 CPUState
*cs
= CPU(cpu
);
864 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VI
) ||
865 (env
->irq_line_state
& CPU_INTERRUPT_VIRQ
);
867 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) != 0)) {
869 cpu_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
871 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
876 void arm_cpu_update_vfiq(ARMCPU
*cpu
)
879 * Update the interrupt level for VFIQ, which is the logical OR of
880 * the HCR_EL2.VF bit and the input line level from the GIC.
882 CPUARMState
*env
= &cpu
->env
;
883 CPUState
*cs
= CPU(cpu
);
885 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VF
) ||
886 (env
->irq_line_state
& CPU_INTERRUPT_VFIQ
);
888 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) != 0)) {
890 cpu_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
892 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
897 void arm_cpu_update_vserr(ARMCPU
*cpu
)
900 * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit.
902 CPUARMState
*env
= &cpu
->env
;
903 CPUState
*cs
= CPU(cpu
);
905 bool new_state
= env
->cp15
.hcr_el2
& HCR_VSE
;
907 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VSERR
) != 0)) {
909 cpu_interrupt(cs
, CPU_INTERRUPT_VSERR
);
911 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VSERR
);
916 #ifndef CONFIG_USER_ONLY
917 static void arm_cpu_set_irq(void *opaque
, int irq
, int level
)
919 ARMCPU
*cpu
= opaque
;
920 CPUARMState
*env
= &cpu
->env
;
921 CPUState
*cs
= CPU(cpu
);
922 static const int mask
[] = {
923 [ARM_CPU_IRQ
] = CPU_INTERRUPT_HARD
,
924 [ARM_CPU_FIQ
] = CPU_INTERRUPT_FIQ
,
925 [ARM_CPU_VIRQ
] = CPU_INTERRUPT_VIRQ
,
926 [ARM_CPU_VFIQ
] = CPU_INTERRUPT_VFIQ
929 if (!arm_feature(env
, ARM_FEATURE_EL2
) &&
930 (irq
== ARM_CPU_VIRQ
|| irq
== ARM_CPU_VFIQ
)) {
932 * The GIC might tell us about VIRQ and VFIQ state, but if we don't
933 * have EL2 support we don't care. (Unless the guest is doing something
934 * silly this will only be calls saying "level is still 0".)
940 env
->irq_line_state
|= mask
[irq
];
942 env
->irq_line_state
&= ~mask
[irq
];
947 arm_cpu_update_virq(cpu
);
950 arm_cpu_update_vfiq(cpu
);
955 cpu_interrupt(cs
, mask
[irq
]);
957 cpu_reset_interrupt(cs
, mask
[irq
]);
961 g_assert_not_reached();
965 static void arm_cpu_kvm_set_irq(void *opaque
, int irq
, int level
)
968 ARMCPU
*cpu
= opaque
;
969 CPUARMState
*env
= &cpu
->env
;
970 CPUState
*cs
= CPU(cpu
);
971 uint32_t linestate_bit
;
976 irq_id
= KVM_ARM_IRQ_CPU_IRQ
;
977 linestate_bit
= CPU_INTERRUPT_HARD
;
980 irq_id
= KVM_ARM_IRQ_CPU_FIQ
;
981 linestate_bit
= CPU_INTERRUPT_FIQ
;
984 g_assert_not_reached();
988 env
->irq_line_state
|= linestate_bit
;
990 env
->irq_line_state
&= ~linestate_bit
;
992 kvm_arm_set_irq(cs
->cpu_index
, KVM_ARM_IRQ_TYPE_CPU
, irq_id
, !!level
);
996 static bool arm_cpu_virtio_is_big_endian(CPUState
*cs
)
998 ARMCPU
*cpu
= ARM_CPU(cs
);
999 CPUARMState
*env
= &cpu
->env
;
1001 cpu_synchronize_state(cs
);
1002 return arm_cpu_data_is_big_endian(env
);
1007 static void arm_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
1009 ARMCPU
*ac
= ARM_CPU(cpu
);
1010 CPUARMState
*env
= &ac
->env
;
1014 info
->cap_arch
= CS_ARCH_ARM64
;
1015 info
->cap_insn_unit
= 4;
1016 info
->cap_insn_split
= 4;
1020 info
->cap_insn_unit
= 2;
1021 info
->cap_insn_split
= 4;
1022 cap_mode
= CS_MODE_THUMB
;
1024 info
->cap_insn_unit
= 4;
1025 info
->cap_insn_split
= 4;
1026 cap_mode
= CS_MODE_ARM
;
1028 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1029 cap_mode
|= CS_MODE_V8
;
1031 if (arm_feature(env
, ARM_FEATURE_M
)) {
1032 cap_mode
|= CS_MODE_MCLASS
;
1034 info
->cap_arch
= CS_ARCH_ARM
;
1035 info
->cap_mode
= cap_mode
;
1038 sctlr_b
= arm_sctlr_b(env
);
1039 if (bswap_code(sctlr_b
)) {
1040 #if TARGET_BIG_ENDIAN
1041 info
->endian
= BFD_ENDIAN_LITTLE
;
1043 info
->endian
= BFD_ENDIAN_BIG
;
1046 info
->flags
&= ~INSN_ARM_BE32
;
1047 #ifndef CONFIG_USER_ONLY
1049 info
->flags
|= INSN_ARM_BE32
;
1054 #ifdef TARGET_AARCH64
1056 static void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
1058 ARMCPU
*cpu
= ARM_CPU(cs
);
1059 CPUARMState
*env
= &cpu
->env
;
1060 uint32_t psr
= pstate_read(env
);
1062 int el
= arm_current_el(env
);
1063 uint64_t hcr
= arm_hcr_el2_eff(env
);
1064 const char *ns_status
;
1067 qemu_fprintf(f
, " PC=%016" PRIx64
" ", env
->pc
);
1068 for (i
= 0; i
< 32; i
++) {
1070 qemu_fprintf(f
, " SP=%016" PRIx64
"\n", env
->xregs
[i
]);
1072 qemu_fprintf(f
, "X%02d=%016" PRIx64
"%s", i
, env
->xregs
[i
],
1073 (i
+ 2) % 3 ? " " : "\n");
1077 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
1078 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
1082 qemu_fprintf(f
, "PSTATE=%08x %c%c%c%c %sEL%d%c",
1084 psr
& PSTATE_N
? 'N' : '-',
1085 psr
& PSTATE_Z
? 'Z' : '-',
1086 psr
& PSTATE_C
? 'C' : '-',
1087 psr
& PSTATE_V
? 'V' : '-',
1090 psr
& PSTATE_SP
? 'h' : 't');
1092 if (cpu_isar_feature(aa64_sme
, cpu
)) {
1093 qemu_fprintf(f
, " SVCR=%08" PRIx64
" %c%c",
1095 (FIELD_EX64(env
->svcr
, SVCR
, ZA
) ? 'Z' : '-'),
1096 (FIELD_EX64(env
->svcr
, SVCR
, SM
) ? 'S' : '-'));
1098 if (cpu_isar_feature(aa64_bti
, cpu
)) {
1099 qemu_fprintf(f
, " BTYPE=%d", (psr
& PSTATE_BTYPE
) >> 10);
1101 qemu_fprintf(f
, "%s%s%s",
1102 (hcr
& HCR_NV
) ? " NV" : "",
1103 (hcr
& HCR_NV1
) ? " NV1" : "",
1104 (hcr
& HCR_NV2
) ? " NV2" : "");
1105 if (!(flags
& CPU_DUMP_FPU
)) {
1106 qemu_fprintf(f
, "\n");
1109 if (fp_exception_el(env
, el
) != 0) {
1110 qemu_fprintf(f
, " FPU disabled\n");
1113 qemu_fprintf(f
, " FPCR=%08x FPSR=%08x\n",
1114 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
1116 if (cpu_isar_feature(aa64_sme
, cpu
) && FIELD_EX64(env
->svcr
, SVCR
, SM
)) {
1117 sve
= sme_exception_el(env
, el
) == 0;
1118 } else if (cpu_isar_feature(aa64_sve
, cpu
)) {
1119 sve
= sve_exception_el(env
, el
) == 0;
1125 int zcr_len
= sve_vqm1_for_el(env
, el
);
1127 for (i
= 0; i
<= FFR_PRED_NUM
; i
++) {
1129 if (i
== FFR_PRED_NUM
) {
1130 qemu_fprintf(f
, "FFR=");
1131 /* It's last, so end the line. */
1134 qemu_fprintf(f
, "P%02d=", i
);
1147 /* More than one quadword per predicate. */
1152 for (j
= zcr_len
/ 4; j
>= 0; j
--) {
1154 if (j
* 4 + 4 <= zcr_len
+ 1) {
1157 digits
= (zcr_len
% 4 + 1) * 4;
1159 qemu_fprintf(f
, "%0*" PRIx64
"%s", digits
,
1160 env
->vfp
.pregs
[i
].p
[j
],
1161 j
? ":" : eol
? "\n" : " ");
1167 * With vl=16, there are only 37 columns per register,
1168 * so output two registers per line.
1170 for (i
= 0; i
< 32; i
++) {
1171 qemu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
"%s",
1172 i
, env
->vfp
.zregs
[i
].d
[1],
1173 env
->vfp
.zregs
[i
].d
[0], i
& 1 ? "\n" : " ");
1176 for (i
= 0; i
< 32; i
++) {
1177 qemu_fprintf(f
, "Z%02d=", i
);
1178 for (j
= zcr_len
; j
>= 0; j
--) {
1179 qemu_fprintf(f
, "%016" PRIx64
":%016" PRIx64
"%s",
1180 env
->vfp
.zregs
[i
].d
[j
* 2 + 1],
1181 env
->vfp
.zregs
[i
].d
[j
* 2 + 0],
1187 for (i
= 0; i
< 32; i
++) {
1188 uint64_t *q
= aa64_vfp_qreg(env
, i
);
1189 qemu_fprintf(f
, "Q%02d=%016" PRIx64
":%016" PRIx64
"%s",
1190 i
, q
[1], q
[0], (i
& 1 ? "\n" : " "));
1194 if (cpu_isar_feature(aa64_sme
, cpu
) &&
1195 FIELD_EX64(env
->svcr
, SVCR
, ZA
) &&
1196 sme_exception_el(env
, el
) == 0) {
1197 int zcr_len
= sve_vqm1_for_el_sm(env
, el
, true);
1198 int svl
= (zcr_len
+ 1) * 16;
1199 int svl_lg10
= svl
< 100 ? 2 : 3;
1201 for (i
= 0; i
< svl
; i
++) {
1202 qemu_fprintf(f
, "ZA[%0*d]=", svl_lg10
, i
);
1203 for (j
= zcr_len
; j
>= 0; --j
) {
1204 qemu_fprintf(f
, "%016" PRIx64
":%016" PRIx64
"%c",
1205 env
->zarray
[i
].d
[2 * j
+ 1],
1206 env
->zarray
[i
].d
[2 * j
],
1215 static inline void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
1217 g_assert_not_reached();
1222 static void arm_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
1224 ARMCPU
*cpu
= ARM_CPU(cs
);
1225 CPUARMState
*env
= &cpu
->env
;
1229 aarch64_cpu_dump_state(cs
, f
, flags
);
1233 for (i
= 0; i
< 16; i
++) {
1234 qemu_fprintf(f
, "R%02d=%08x", i
, env
->regs
[i
]);
1236 qemu_fprintf(f
, "\n");
1238 qemu_fprintf(f
, " ");
1242 if (arm_feature(env
, ARM_FEATURE_M
)) {
1243 uint32_t xpsr
= xpsr_read(env
);
1245 const char *ns_status
= "";
1247 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1248 ns_status
= env
->v7m
.secure
? "S " : "NS ";
1251 if (xpsr
& XPSR_EXCP
) {
1254 if (env
->v7m
.control
[env
->v7m
.secure
] & R_V7M_CONTROL_NPRIV_MASK
) {
1255 mode
= "unpriv-thread";
1257 mode
= "priv-thread";
1261 qemu_fprintf(f
, "XPSR=%08x %c%c%c%c %c %s%s\n",
1263 xpsr
& XPSR_N
? 'N' : '-',
1264 xpsr
& XPSR_Z
? 'Z' : '-',
1265 xpsr
& XPSR_C
? 'C' : '-',
1266 xpsr
& XPSR_V
? 'V' : '-',
1267 xpsr
& XPSR_T
? 'T' : 'A',
1271 uint32_t psr
= cpsr_read(env
);
1272 const char *ns_status
= "";
1274 if (arm_feature(env
, ARM_FEATURE_EL3
) &&
1275 (psr
& CPSR_M
) != ARM_CPU_MODE_MON
) {
1276 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
1279 qemu_fprintf(f
, "PSR=%08x %c%c%c%c %c %s%s%d\n",
1281 psr
& CPSR_N
? 'N' : '-',
1282 psr
& CPSR_Z
? 'Z' : '-',
1283 psr
& CPSR_C
? 'C' : '-',
1284 psr
& CPSR_V
? 'V' : '-',
1285 psr
& CPSR_T
? 'T' : 'A',
1287 aarch32_mode_name(psr
), (psr
& 0x10) ? 32 : 26);
1290 if (flags
& CPU_DUMP_FPU
) {
1292 if (cpu_isar_feature(aa32_simd_r32
, cpu
)) {
1294 } else if (cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
1297 for (i
= 0; i
< numvfpregs
; i
++) {
1298 uint64_t v
= *aa32_vfp_dreg(env
, i
);
1299 qemu_fprintf(f
, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64
"\n",
1301 i
* 2 + 1, (uint32_t)(v
>> 32),
1304 qemu_fprintf(f
, "FPSCR: %08x\n", vfp_get_fpscr(env
));
1305 if (cpu_isar_feature(aa32_mve
, cpu
)) {
1306 qemu_fprintf(f
, "VPR: %08x\n", env
->v7m
.vpr
);
1311 uint64_t arm_build_mp_affinity(int idx
, uint8_t clustersz
)
1313 uint32_t Aff1
= idx
/ clustersz
;
1314 uint32_t Aff0
= idx
% clustersz
;
1315 return (Aff1
<< ARM_AFF1_SHIFT
) | Aff0
;
1318 uint64_t arm_cpu_mp_affinity(ARMCPU
*cpu
)
1320 return cpu
->mp_affinity
;
1323 static void arm_cpu_initfn(Object
*obj
)
1325 ARMCPU
*cpu
= ARM_CPU(obj
);
1327 cpu
->cp_regs
= g_hash_table_new_full(g_direct_hash
, g_direct_equal
,
1330 QLIST_INIT(&cpu
->pre_el_change_hooks
);
1331 QLIST_INIT(&cpu
->el_change_hooks
);
1333 #ifdef CONFIG_USER_ONLY
1334 # ifdef TARGET_AARCH64
1336 * The linux kernel defaults to 512-bit for SVE, and 256-bit for SME.
1337 * These values were chosen to fit within the default signal frame.
1338 * See documentation for /proc/sys/abi/{sve,sme}_default_vector_length,
1339 * and our corresponding cpu property.
1341 cpu
->sve_default_vq
= 4;
1342 cpu
->sme_default_vq
= 2;
1345 /* Our inbound IRQ and FIQ lines */
1346 if (kvm_enabled()) {
1347 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
1348 * the same interface as non-KVM CPUs.
1350 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_kvm_set_irq
, 4);
1352 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_set_irq
, 4);
1355 qdev_init_gpio_out(DEVICE(cpu
), cpu
->gt_timer_outputs
,
1356 ARRAY_SIZE(cpu
->gt_timer_outputs
));
1358 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->gicv3_maintenance_interrupt
,
1359 "gicv3-maintenance-interrupt", 1);
1360 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->pmu_interrupt
,
1361 "pmu-interrupt", 1);
1364 /* DTB consumers generally don't in fact care what the 'compatible'
1365 * string is, so always provide some string and trust that a hypothetical
1366 * picky DTB consumer will also provide a helpful error message.
1368 cpu
->dtb_compatible
= "qemu,unknown";
1369 cpu
->psci_version
= QEMU_PSCI_VERSION_0_1
; /* By default assume PSCI v0.1 */
1370 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_NONE
;
1372 if (tcg_enabled() || hvf_enabled()) {
1373 /* TCG and HVF implement PSCI 1.1 */
1374 cpu
->psci_version
= QEMU_PSCI_VERSION_1_1
;
1378 static Property arm_cpu_gt_cntfrq_property
=
1379 DEFINE_PROP_UINT64("cntfrq", ARMCPU
, gt_cntfrq_hz
,
1380 NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
);
1382 static Property arm_cpu_reset_cbar_property
=
1383 DEFINE_PROP_UINT64("reset-cbar", ARMCPU
, reset_cbar
, 0);
1385 static Property arm_cpu_reset_hivecs_property
=
1386 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU
, reset_hivecs
, false);
1388 #ifndef CONFIG_USER_ONLY
1389 static Property arm_cpu_has_el2_property
=
1390 DEFINE_PROP_BOOL("has_el2", ARMCPU
, has_el2
, true);
1392 static Property arm_cpu_has_el3_property
=
1393 DEFINE_PROP_BOOL("has_el3", ARMCPU
, has_el3
, true);
1396 static Property arm_cpu_cfgend_property
=
1397 DEFINE_PROP_BOOL("cfgend", ARMCPU
, cfgend
, false);
1399 static Property arm_cpu_has_vfp_property
=
1400 DEFINE_PROP_BOOL("vfp", ARMCPU
, has_vfp
, true);
1402 static Property arm_cpu_has_vfp_d32_property
=
1403 DEFINE_PROP_BOOL("vfp-d32", ARMCPU
, has_vfp_d32
, true);
1405 static Property arm_cpu_has_neon_property
=
1406 DEFINE_PROP_BOOL("neon", ARMCPU
, has_neon
, true);
1408 static Property arm_cpu_has_dsp_property
=
1409 DEFINE_PROP_BOOL("dsp", ARMCPU
, has_dsp
, true);
1411 static Property arm_cpu_has_mpu_property
=
1412 DEFINE_PROP_BOOL("has-mpu", ARMCPU
, has_mpu
, true);
1414 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
1415 * because the CPU initfn will have already set cpu->pmsav7_dregion to
1416 * the right value for that particular CPU type, and we don't want
1417 * to override that with an incorrect constant value.
1419 static Property arm_cpu_pmsav7_dregion_property
=
1420 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU
,
1422 qdev_prop_uint32
, uint32_t);
1424 static bool arm_get_pmu(Object
*obj
, Error
**errp
)
1426 ARMCPU
*cpu
= ARM_CPU(obj
);
1428 return cpu
->has_pmu
;
1431 static void arm_set_pmu(Object
*obj
, bool value
, Error
**errp
)
1433 ARMCPU
*cpu
= ARM_CPU(obj
);
1436 if (kvm_enabled() && !kvm_arm_pmu_supported()) {
1437 error_setg(errp
, "'pmu' feature not supported by KVM on this host");
1440 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
1442 unset_feature(&cpu
->env
, ARM_FEATURE_PMU
);
1444 cpu
->has_pmu
= value
;
1447 unsigned int gt_cntfrq_period_ns(ARMCPU
*cpu
)
1450 * The exact approach to calculating guest ticks is:
1452 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz,
1453 * NANOSECONDS_PER_SECOND);
1455 * We don't do that. Rather we intentionally use integer division
1456 * truncation below and in the caller for the conversion of host monotonic
1457 * time to guest ticks to provide the exact inverse for the semantics of
1458 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so
1459 * it loses precision when representing frequencies where
1460 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to
1461 * provide an exact inverse leads to scheduling timers with negative
1462 * periods, which in turn leads to sticky behaviour in the guest.
1464 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor
1465 * cannot become zero.
1467 return NANOSECONDS_PER_SECOND
> cpu
->gt_cntfrq_hz
?
1468 NANOSECONDS_PER_SECOND
/ cpu
->gt_cntfrq_hz
: 1;
1471 static void arm_cpu_propagate_feature_implications(ARMCPU
*cpu
)
1473 CPUARMState
*env
= &cpu
->env
;
1474 bool no_aa32
= false;
1477 * Some features automatically imply others: set the feature
1478 * bits explicitly for these cases.
1481 if (arm_feature(env
, ARM_FEATURE_M
)) {
1482 set_feature(env
, ARM_FEATURE_PMSA
);
1485 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1486 if (arm_feature(env
, ARM_FEATURE_M
)) {
1487 set_feature(env
, ARM_FEATURE_V7
);
1489 set_feature(env
, ARM_FEATURE_V7VE
);
1494 * There exist AArch64 cpus without AArch32 support. When KVM
1495 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
1496 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
1497 * As a general principle, we also do not make ID register
1498 * consistency checks anywhere unless using TCG, because only
1499 * for TCG would a consistency-check failure be a QEMU bug.
1501 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1502 no_aa32
= !cpu_isar_feature(aa64_aa32
, cpu
);
1505 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
1507 * v7 Virtualization Extensions. In real hardware this implies
1508 * EL2 and also the presence of the Security Extensions.
1509 * For QEMU, for backwards-compatibility we implement some
1510 * CPUs or CPU configs which have no actual EL2 or EL3 but do
1511 * include the various other features that V7VE implies.
1512 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
1513 * Security Extensions is ARM_FEATURE_EL3.
1515 assert(!tcg_enabled() || no_aa32
||
1516 cpu_isar_feature(aa32_arm_div
, cpu
));
1517 set_feature(env
, ARM_FEATURE_LPAE
);
1518 set_feature(env
, ARM_FEATURE_V7
);
1520 if (arm_feature(env
, ARM_FEATURE_V7
)) {
1521 set_feature(env
, ARM_FEATURE_VAPA
);
1522 set_feature(env
, ARM_FEATURE_THUMB2
);
1523 set_feature(env
, ARM_FEATURE_MPIDR
);
1524 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1525 set_feature(env
, ARM_FEATURE_V6K
);
1527 set_feature(env
, ARM_FEATURE_V6
);
1531 * Always define VBAR for V7 CPUs even if it doesn't exist in
1532 * non-EL3 configs. This is needed by some legacy boards.
1534 set_feature(env
, ARM_FEATURE_VBAR
);
1536 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
1537 set_feature(env
, ARM_FEATURE_V6
);
1538 set_feature(env
, ARM_FEATURE_MVFR
);
1540 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1541 set_feature(env
, ARM_FEATURE_V5
);
1542 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1543 assert(!tcg_enabled() || no_aa32
||
1544 cpu_isar_feature(aa32_jazelle
, cpu
));
1545 set_feature(env
, ARM_FEATURE_AUXCR
);
1548 if (arm_feature(env
, ARM_FEATURE_V5
)) {
1549 set_feature(env
, ARM_FEATURE_V4T
);
1551 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
1552 set_feature(env
, ARM_FEATURE_V7MP
);
1554 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
1555 set_feature(env
, ARM_FEATURE_CBAR
);
1557 if (arm_feature(env
, ARM_FEATURE_THUMB2
) &&
1558 !arm_feature(env
, ARM_FEATURE_M
)) {
1559 set_feature(env
, ARM_FEATURE_THUMB_DSP
);
1563 void arm_cpu_post_init(Object
*obj
)
1565 ARMCPU
*cpu
= ARM_CPU(obj
);
1568 * Some features imply others. Figure this out now, because we
1569 * are going to look at the feature bits in deciding which
1570 * properties to add.
1572 arm_cpu_propagate_feature_implications(cpu
);
1574 if (arm_feature(&cpu
->env
, ARM_FEATURE_CBAR
) ||
1575 arm_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
)) {
1576 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_cbar_property
);
1579 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1580 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_hivecs_property
);
1583 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1584 object_property_add_uint64_ptr(obj
, "rvbar",
1586 OBJ_PROP_FLAG_READWRITE
);
1589 #ifndef CONFIG_USER_ONLY
1590 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
1591 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
1592 * prevent "has_el3" from existing on CPUs which cannot support EL3.
1594 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el3_property
);
1596 object_property_add_link(obj
, "secure-memory",
1598 (Object
**)&cpu
->secure_memory
,
1599 qdev_prop_allow_set_link_before_realize
,
1600 OBJ_PROP_LINK_STRONG
);
1603 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
)) {
1604 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el2_property
);
1608 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMU
)) {
1609 cpu
->has_pmu
= true;
1610 object_property_add_bool(obj
, "pmu", arm_get_pmu
, arm_set_pmu
);
1614 * Allow user to turn off VFP and Neon support, but only for TCG --
1615 * KVM does not currently allow us to lie to the guest about its
1616 * ID/feature registers, so the guest always sees what the host has.
1618 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1619 if (cpu_isar_feature(aa64_fp_simd
, cpu
)) {
1620 cpu
->has_vfp
= true;
1621 cpu
->has_vfp_d32
= true;
1622 if (tcg_enabled() || qtest_enabled()) {
1623 qdev_property_add_static(DEVICE(obj
),
1624 &arm_cpu_has_vfp_property
);
1627 } else if (cpu_isar_feature(aa32_vfp
, cpu
)) {
1628 cpu
->has_vfp
= true;
1629 if (cpu_isar_feature(aa32_simd_r32
, cpu
)) {
1630 cpu
->has_vfp_d32
= true;
1632 * The permitted values of the SIMDReg bits [3:0] on
1633 * Armv8-A are either 0b0000 and 0b0010. On such CPUs,
1634 * make sure that has_vfp_d32 can not be set to false.
1636 if ((tcg_enabled() || qtest_enabled())
1637 && !(arm_feature(&cpu
->env
, ARM_FEATURE_V8
)
1638 && !arm_feature(&cpu
->env
, ARM_FEATURE_M
))) {
1639 qdev_property_add_static(DEVICE(obj
),
1640 &arm_cpu_has_vfp_d32_property
);
1645 if (arm_feature(&cpu
->env
, ARM_FEATURE_NEON
)) {
1646 cpu
->has_neon
= true;
1647 if (!kvm_enabled()) {
1648 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_neon_property
);
1652 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
) &&
1653 arm_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
)) {
1654 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_dsp_property
);
1657 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMSA
)) {
1658 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_mpu_property
);
1659 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1660 qdev_property_add_static(DEVICE(obj
),
1661 &arm_cpu_pmsav7_dregion_property
);
1665 if (arm_feature(&cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
1666 object_property_add_link(obj
, "idau", TYPE_IDAU_INTERFACE
, &cpu
->idau
,
1667 qdev_prop_allow_set_link_before_realize
,
1668 OBJ_PROP_LINK_STRONG
);
1670 * M profile: initial value of the Secure VTOR. We can't just use
1671 * a simple DEFINE_PROP_UINT32 for this because we want to permit
1672 * the property to be set after realize.
1674 object_property_add_uint32_ptr(obj
, "init-svtor",
1676 OBJ_PROP_FLAG_READWRITE
);
1678 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1680 * Initial value of the NS VTOR (for cores without the Security
1681 * extension, this is the only VTOR)
1683 object_property_add_uint32_ptr(obj
, "init-nsvtor",
1685 OBJ_PROP_FLAG_READWRITE
);
1688 /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */
1689 object_property_add_uint32_ptr(obj
, "psci-conduit",
1691 OBJ_PROP_FLAG_READWRITE
);
1693 qdev_property_add_static(DEVICE(obj
), &arm_cpu_cfgend_property
);
1695 if (arm_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
)) {
1696 qdev_property_add_static(DEVICE(cpu
), &arm_cpu_gt_cntfrq_property
);
1699 if (kvm_enabled()) {
1700 kvm_arm_add_vcpu_properties(cpu
);
1703 #ifndef CONFIG_USER_ONLY
1704 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
) &&
1705 cpu_isar_feature(aa64_mte
, cpu
)) {
1706 object_property_add_link(obj
, "tag-memory",
1708 (Object
**)&cpu
->tag_memory
,
1709 qdev_prop_allow_set_link_before_realize
,
1710 OBJ_PROP_LINK_STRONG
);
1712 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
1713 object_property_add_link(obj
, "secure-tag-memory",
1715 (Object
**)&cpu
->secure_tag_memory
,
1716 qdev_prop_allow_set_link_before_realize
,
1717 OBJ_PROP_LINK_STRONG
);
1723 static void arm_cpu_finalizefn(Object
*obj
)
1725 ARMCPU
*cpu
= ARM_CPU(obj
);
1726 ARMELChangeHook
*hook
, *next
;
1728 g_hash_table_destroy(cpu
->cp_regs
);
1730 QLIST_FOREACH_SAFE(hook
, &cpu
->pre_el_change_hooks
, node
, next
) {
1731 QLIST_REMOVE(hook
, node
);
1734 QLIST_FOREACH_SAFE(hook
, &cpu
->el_change_hooks
, node
, next
) {
1735 QLIST_REMOVE(hook
, node
);
1738 #ifndef CONFIG_USER_ONLY
1739 if (cpu
->pmu_timer
) {
1740 timer_free(cpu
->pmu_timer
);
1745 void arm_cpu_finalize_features(ARMCPU
*cpu
, Error
**errp
)
1747 Error
*local_err
= NULL
;
1749 #ifdef TARGET_AARCH64
1750 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1751 arm_cpu_sve_finalize(cpu
, &local_err
);
1752 if (local_err
!= NULL
) {
1753 error_propagate(errp
, local_err
);
1758 * FEAT_SME is not architecturally dependent on FEAT_SVE (unless
1759 * FEAT_SME_FA64 is present). However our implementation currently
1760 * assumes it, so if the user asked for sve=off then turn off SME also.
1761 * (KVM doesn't currently support SME at all.)
1763 if (cpu_isar_feature(aa64_sme
, cpu
) && !cpu_isar_feature(aa64_sve
, cpu
)) {
1764 object_property_set_bool(OBJECT(cpu
), "sme", false, &error_abort
);
1767 arm_cpu_sme_finalize(cpu
, &local_err
);
1768 if (local_err
!= NULL
) {
1769 error_propagate(errp
, local_err
);
1773 arm_cpu_pauth_finalize(cpu
, &local_err
);
1774 if (local_err
!= NULL
) {
1775 error_propagate(errp
, local_err
);
1779 arm_cpu_lpa2_finalize(cpu
, &local_err
);
1780 if (local_err
!= NULL
) {
1781 error_propagate(errp
, local_err
);
1787 if (kvm_enabled()) {
1788 kvm_arm_steal_time_finalize(cpu
, &local_err
);
1789 if (local_err
!= NULL
) {
1790 error_propagate(errp
, local_err
);
1796 static void arm_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
1798 CPUState
*cs
= CPU(dev
);
1799 ARMCPU
*cpu
= ARM_CPU(dev
);
1800 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(dev
);
1801 CPUARMState
*env
= &cpu
->env
;
1803 Error
*local_err
= NULL
;
1805 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
1806 /* Use pc-relative instructions in system-mode */
1807 cs
->tcg_cflags
|= CF_PCREL
;
1810 /* If we needed to query the host kernel for the CPU features
1811 * then it's possible that might have failed in the initfn, but
1812 * this is the first point where we can report it.
1814 if (cpu
->host_cpu_probe_failed
) {
1815 if (!kvm_enabled() && !hvf_enabled()) {
1816 error_setg(errp
, "The 'host' CPU type can only be used with KVM or HVF");
1818 error_setg(errp
, "Failed to retrieve host CPU features");
1823 #ifndef CONFIG_USER_ONLY
1824 /* The NVIC and M-profile CPU are two halves of a single piece of
1825 * hardware; trying to use one without the other is a command line
1826 * error and will result in segfaults if not caught here.
1828 if (arm_feature(env
, ARM_FEATURE_M
)) {
1830 error_setg(errp
, "This board cannot be used with Cortex-M CPUs");
1835 error_setg(errp
, "This board can only be used with Cortex-M CPUs");
1840 if (!tcg_enabled() && !qtest_enabled()) {
1842 * We assume that no accelerator except TCG (and the "not really an
1843 * accelerator" qtest) can handle these features, because Arm hardware
1844 * virtualization can't virtualize them.
1846 * Catch all the cases which might cause us to create more than one
1847 * address space for the CPU (otherwise we will assert() later in
1848 * cpu_address_space_init()).
1850 if (arm_feature(env
, ARM_FEATURE_M
)) {
1852 "Cannot enable %s when using an M-profile guest CPU",
1853 current_accel_name());
1858 "Cannot enable %s when guest CPU has EL3 enabled",
1859 current_accel_name());
1862 if (cpu
->tag_memory
) {
1864 "Cannot enable %s when guest CPUs has MTE enabled",
1865 current_accel_name());
1873 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
1874 if (!cpu
->gt_cntfrq_hz
) {
1875 error_setg(errp
, "Invalid CNTFRQ: %"PRId64
"Hz",
1879 scale
= gt_cntfrq_period_ns(cpu
);
1881 scale
= GTIMER_SCALE
;
1884 cpu
->gt_timer
[GTIMER_PHYS
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1885 arm_gt_ptimer_cb
, cpu
);
1886 cpu
->gt_timer
[GTIMER_VIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1887 arm_gt_vtimer_cb
, cpu
);
1888 cpu
->gt_timer
[GTIMER_HYP
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1889 arm_gt_htimer_cb
, cpu
);
1890 cpu
->gt_timer
[GTIMER_SEC
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1891 arm_gt_stimer_cb
, cpu
);
1892 cpu
->gt_timer
[GTIMER_HYPVIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1893 arm_gt_hvtimer_cb
, cpu
);
1897 cpu_exec_realizefn(cs
, &local_err
);
1898 if (local_err
!= NULL
) {
1899 error_propagate(errp
, local_err
);
1903 arm_cpu_finalize_features(cpu
, &local_err
);
1904 if (local_err
!= NULL
) {
1905 error_propagate(errp
, local_err
);
1909 #ifdef CONFIG_USER_ONLY
1911 * User mode relies on IC IVAU instructions to catch modification of
1914 * Clear CTR_EL0.DIC to ensure that software that honors these flags uses
1915 * IC IVAU even if the emulated processor does not normally require it.
1917 cpu
->ctr
= FIELD_DP64(cpu
->ctr
, CTR_EL0
, DIC
, 0);
1920 if (arm_feature(env
, ARM_FEATURE_AARCH64
) &&
1921 cpu
->has_vfp
!= cpu
->has_neon
) {
1923 * This is an architectural requirement for AArch64; AArch32 is
1924 * more flexible and permits VFP-no-Neon and Neon-no-VFP.
1927 "AArch64 CPUs must have both VFP and Neon or neither");
1931 if (cpu
->has_vfp_d32
!= cpu
->has_neon
) {
1932 error_setg(errp
, "ARM CPUs must have both VFP-D32 and Neon or neither");
1936 if (!cpu
->has_vfp_d32
) {
1939 u
= cpu
->isar
.mvfr0
;
1940 u
= FIELD_DP32(u
, MVFR0
, SIMDREG
, 1); /* 16 registers */
1941 cpu
->isar
.mvfr0
= u
;
1944 if (!cpu
->has_vfp
) {
1948 t
= cpu
->isar
.id_aa64isar1
;
1949 t
= FIELD_DP64(t
, ID_AA64ISAR1
, JSCVT
, 0);
1950 cpu
->isar
.id_aa64isar1
= t
;
1952 t
= cpu
->isar
.id_aa64pfr0
;
1953 t
= FIELD_DP64(t
, ID_AA64PFR0
, FP
, 0xf);
1954 cpu
->isar
.id_aa64pfr0
= t
;
1956 u
= cpu
->isar
.id_isar6
;
1957 u
= FIELD_DP32(u
, ID_ISAR6
, JSCVT
, 0);
1958 u
= FIELD_DP32(u
, ID_ISAR6
, BF16
, 0);
1959 cpu
->isar
.id_isar6
= u
;
1961 u
= cpu
->isar
.mvfr0
;
1962 u
= FIELD_DP32(u
, MVFR0
, FPSP
, 0);
1963 u
= FIELD_DP32(u
, MVFR0
, FPDP
, 0);
1964 u
= FIELD_DP32(u
, MVFR0
, FPDIVIDE
, 0);
1965 u
= FIELD_DP32(u
, MVFR0
, FPSQRT
, 0);
1966 u
= FIELD_DP32(u
, MVFR0
, FPROUND
, 0);
1967 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1968 u
= FIELD_DP32(u
, MVFR0
, FPTRAP
, 0);
1969 u
= FIELD_DP32(u
, MVFR0
, FPSHVEC
, 0);
1971 cpu
->isar
.mvfr0
= u
;
1973 u
= cpu
->isar
.mvfr1
;
1974 u
= FIELD_DP32(u
, MVFR1
, FPFTZ
, 0);
1975 u
= FIELD_DP32(u
, MVFR1
, FPDNAN
, 0);
1976 u
= FIELD_DP32(u
, MVFR1
, FPHP
, 0);
1977 if (arm_feature(env
, ARM_FEATURE_M
)) {
1978 u
= FIELD_DP32(u
, MVFR1
, FP16
, 0);
1980 cpu
->isar
.mvfr1
= u
;
1982 u
= cpu
->isar
.mvfr2
;
1983 u
= FIELD_DP32(u
, MVFR2
, FPMISC
, 0);
1984 cpu
->isar
.mvfr2
= u
;
1987 if (!cpu
->has_neon
) {
1991 unset_feature(env
, ARM_FEATURE_NEON
);
1993 t
= cpu
->isar
.id_aa64isar0
;
1994 t
= FIELD_DP64(t
, ID_AA64ISAR0
, AES
, 0);
1995 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SHA1
, 0);
1996 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SHA2
, 0);
1997 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SHA3
, 0);
1998 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SM3
, 0);
1999 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SM4
, 0);
2000 t
= FIELD_DP64(t
, ID_AA64ISAR0
, DP
, 0);
2001 cpu
->isar
.id_aa64isar0
= t
;
2003 t
= cpu
->isar
.id_aa64isar1
;
2004 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FCMA
, 0);
2005 t
= FIELD_DP64(t
, ID_AA64ISAR1
, BF16
, 0);
2006 t
= FIELD_DP64(t
, ID_AA64ISAR1
, I8MM
, 0);
2007 cpu
->isar
.id_aa64isar1
= t
;
2009 t
= cpu
->isar
.id_aa64pfr0
;
2010 t
= FIELD_DP64(t
, ID_AA64PFR0
, ADVSIMD
, 0xf);
2011 cpu
->isar
.id_aa64pfr0
= t
;
2013 u
= cpu
->isar
.id_isar5
;
2014 u
= FIELD_DP32(u
, ID_ISAR5
, AES
, 0);
2015 u
= FIELD_DP32(u
, ID_ISAR5
, SHA1
, 0);
2016 u
= FIELD_DP32(u
, ID_ISAR5
, SHA2
, 0);
2017 u
= FIELD_DP32(u
, ID_ISAR5
, RDM
, 0);
2018 u
= FIELD_DP32(u
, ID_ISAR5
, VCMA
, 0);
2019 cpu
->isar
.id_isar5
= u
;
2021 u
= cpu
->isar
.id_isar6
;
2022 u
= FIELD_DP32(u
, ID_ISAR6
, DP
, 0);
2023 u
= FIELD_DP32(u
, ID_ISAR6
, FHM
, 0);
2024 u
= FIELD_DP32(u
, ID_ISAR6
, BF16
, 0);
2025 u
= FIELD_DP32(u
, ID_ISAR6
, I8MM
, 0);
2026 cpu
->isar
.id_isar6
= u
;
2028 if (!arm_feature(env
, ARM_FEATURE_M
)) {
2029 u
= cpu
->isar
.mvfr1
;
2030 u
= FIELD_DP32(u
, MVFR1
, SIMDLS
, 0);
2031 u
= FIELD_DP32(u
, MVFR1
, SIMDINT
, 0);
2032 u
= FIELD_DP32(u
, MVFR1
, SIMDSP
, 0);
2033 u
= FIELD_DP32(u
, MVFR1
, SIMDHP
, 0);
2034 cpu
->isar
.mvfr1
= u
;
2036 u
= cpu
->isar
.mvfr2
;
2037 u
= FIELD_DP32(u
, MVFR2
, SIMDMISC
, 0);
2038 cpu
->isar
.mvfr2
= u
;
2042 if (!cpu
->has_neon
&& !cpu
->has_vfp
) {
2046 t
= cpu
->isar
.id_aa64isar0
;
2047 t
= FIELD_DP64(t
, ID_AA64ISAR0
, FHM
, 0);
2048 cpu
->isar
.id_aa64isar0
= t
;
2050 t
= cpu
->isar
.id_aa64isar1
;
2051 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FRINTTS
, 0);
2052 cpu
->isar
.id_aa64isar1
= t
;
2054 u
= cpu
->isar
.mvfr0
;
2055 u
= FIELD_DP32(u
, MVFR0
, SIMDREG
, 0);
2056 cpu
->isar
.mvfr0
= u
;
2058 /* Despite the name, this field covers both VFP and Neon */
2059 u
= cpu
->isar
.mvfr1
;
2060 u
= FIELD_DP32(u
, MVFR1
, SIMDFMAC
, 0);
2061 cpu
->isar
.mvfr1
= u
;
2064 if (arm_feature(env
, ARM_FEATURE_M
) && !cpu
->has_dsp
) {
2067 unset_feature(env
, ARM_FEATURE_THUMB_DSP
);
2069 u
= cpu
->isar
.id_isar1
;
2070 u
= FIELD_DP32(u
, ID_ISAR1
, EXTEND
, 1);
2071 cpu
->isar
.id_isar1
= u
;
2073 u
= cpu
->isar
.id_isar2
;
2074 u
= FIELD_DP32(u
, ID_ISAR2
, MULTU
, 1);
2075 u
= FIELD_DP32(u
, ID_ISAR2
, MULTS
, 1);
2076 cpu
->isar
.id_isar2
= u
;
2078 u
= cpu
->isar
.id_isar3
;
2079 u
= FIELD_DP32(u
, ID_ISAR3
, SIMD
, 1);
2080 u
= FIELD_DP32(u
, ID_ISAR3
, SATURATE
, 0);
2081 cpu
->isar
.id_isar3
= u
;
2086 * We rely on no XScale CPU having VFP so we can use the same bits in the
2087 * TB flags field for VECSTRIDE and XSCALE_CPAR.
2089 assert(arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
) ||
2090 !cpu_isar_feature(aa32_vfp_simd
, cpu
) ||
2091 !arm_feature(env
, ARM_FEATURE_XSCALE
));
2093 if (arm_feature(env
, ARM_FEATURE_V7
) &&
2094 !arm_feature(env
, ARM_FEATURE_M
) &&
2095 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
2096 /* v7VMSA drops support for the old ARMv5 tiny pages, so we
2101 /* For CPUs which might have tiny 1K pages, or which have an
2102 * MPU and might have small region sizes, stick with 1K pages.
2106 if (!set_preferred_target_page_bits(pagebits
)) {
2107 /* This can only ever happen for hotplugging a CPU, or if
2108 * the board code incorrectly creates a CPU which it has
2109 * promised via minimum_page_size that it will not.
2111 error_setg(errp
, "This CPU requires a smaller page size than the "
2116 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
2117 * We don't support setting cluster ID ([16..23]) (known as Aff2
2118 * in later ARM ARM versions), or any of the higher affinity level fields,
2119 * so these bits always RAZ.
2121 if (cpu
->mp_affinity
== ARM64_AFFINITY_INVALID
) {
2122 cpu
->mp_affinity
= arm_build_mp_affinity(cs
->cpu_index
,
2123 ARM_DEFAULT_CPUS_PER_CLUSTER
);
2126 if (cpu
->reset_hivecs
) {
2127 cpu
->reset_sctlr
|= (1 << 13);
2131 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
2132 cpu
->reset_sctlr
|= SCTLR_EE
;
2134 cpu
->reset_sctlr
|= SCTLR_B
;
2138 if (!arm_feature(env
, ARM_FEATURE_M
) && !cpu
->has_el3
) {
2139 /* If the has_el3 CPU property is disabled then we need to disable the
2142 unset_feature(env
, ARM_FEATURE_EL3
);
2145 * Disable the security extension feature bits in the processor
2146 * feature registers as well.
2148 cpu
->isar
.id_pfr1
= FIELD_DP32(cpu
->isar
.id_pfr1
, ID_PFR1
, SECURITY
, 0);
2149 cpu
->isar
.id_dfr0
= FIELD_DP32(cpu
->isar
.id_dfr0
, ID_DFR0
, COPSDBG
, 0);
2150 cpu
->isar
.id_aa64pfr0
= FIELD_DP64(cpu
->isar
.id_aa64pfr0
,
2151 ID_AA64PFR0
, EL3
, 0);
2153 /* Disable the realm management extension, which requires EL3. */
2154 cpu
->isar
.id_aa64pfr0
= FIELD_DP64(cpu
->isar
.id_aa64pfr0
,
2155 ID_AA64PFR0
, RME
, 0);
2158 if (!cpu
->has_el2
) {
2159 unset_feature(env
, ARM_FEATURE_EL2
);
2162 if (!cpu
->has_pmu
) {
2163 unset_feature(env
, ARM_FEATURE_PMU
);
2165 if (arm_feature(env
, ARM_FEATURE_PMU
)) {
2168 if (!kvm_enabled()) {
2169 arm_register_pre_el_change_hook(cpu
, &pmu_pre_el_change
, 0);
2170 arm_register_el_change_hook(cpu
, &pmu_post_el_change
, 0);
2173 #ifndef CONFIG_USER_ONLY
2174 cpu
->pmu_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, arm_pmu_timer_cb
,
2178 cpu
->isar
.id_aa64dfr0
=
2179 FIELD_DP64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, PMUVER
, 0);
2180 cpu
->isar
.id_dfr0
= FIELD_DP32(cpu
->isar
.id_dfr0
, ID_DFR0
, PERFMON
, 0);
2185 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
2187 * Disable the hypervisor feature bits in the processor feature
2188 * registers if we don't have EL2.
2190 cpu
->isar
.id_aa64pfr0
= FIELD_DP64(cpu
->isar
.id_aa64pfr0
,
2191 ID_AA64PFR0
, EL2
, 0);
2192 cpu
->isar
.id_pfr1
= FIELD_DP32(cpu
->isar
.id_pfr1
,
2193 ID_PFR1
, VIRTUALIZATION
, 0);
2196 if (cpu_isar_feature(aa64_mte
, cpu
)) {
2198 * The architectural range of GM blocksize is 2-6, however qemu
2199 * doesn't support blocksize of 2 (see HELPER(ldgm)).
2201 if (tcg_enabled()) {
2202 assert(cpu
->gm_blocksize
>= 3 && cpu
->gm_blocksize
<= 6);
2205 #ifndef CONFIG_USER_ONLY
2207 * If we do not have tag-memory provided by the machine,
2208 * reduce MTE support to instructions enabled at EL0.
2209 * This matches Cortex-A710 BROADCASTMTE input being LOW.
2211 if (cpu
->tag_memory
== NULL
) {
2212 cpu
->isar
.id_aa64pfr1
=
2213 FIELD_DP64(cpu
->isar
.id_aa64pfr1
, ID_AA64PFR1
, MTE
, 1);
2218 if (tcg_enabled()) {
2220 * Don't report some architectural features in the ID registers
2221 * where TCG does not yet implement it (not even a minimal
2222 * stub version). This avoids guests falling over when they
2223 * try to access the non-existent system registers for them.
2225 /* FEAT_SPE (Statistical Profiling Extension) */
2226 cpu
->isar
.id_aa64dfr0
=
2227 FIELD_DP64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, PMSVER
, 0);
2228 /* FEAT_TRBE (Trace Buffer Extension) */
2229 cpu
->isar
.id_aa64dfr0
=
2230 FIELD_DP64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, TRACEBUFFER
, 0);
2231 /* FEAT_TRF (Self-hosted Trace Extension) */
2232 cpu
->isar
.id_aa64dfr0
=
2233 FIELD_DP64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, TRACEFILT
, 0);
2235 FIELD_DP32(cpu
->isar
.id_dfr0
, ID_DFR0
, TRACEFILT
, 0);
2236 /* Trace Macrocell system register access */
2237 cpu
->isar
.id_aa64dfr0
=
2238 FIELD_DP64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, TRACEVER
, 0);
2240 FIELD_DP32(cpu
->isar
.id_dfr0
, ID_DFR0
, COPTRC
, 0);
2241 /* Memory mapped trace */
2243 FIELD_DP32(cpu
->isar
.id_dfr0
, ID_DFR0
, MMAPTRC
, 0);
2244 /* FEAT_AMU (Activity Monitors Extension) */
2245 cpu
->isar
.id_aa64pfr0
=
2246 FIELD_DP64(cpu
->isar
.id_aa64pfr0
, ID_AA64PFR0
, AMU
, 0);
2248 FIELD_DP32(cpu
->isar
.id_pfr0
, ID_PFR0
, AMU
, 0);
2249 /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */
2250 cpu
->isar
.id_aa64pfr0
=
2251 FIELD_DP64(cpu
->isar
.id_aa64pfr0
, ID_AA64PFR0
, MPAM
, 0);
2254 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
2255 * to false or by setting pmsav7-dregion to 0.
2257 if (!cpu
->has_mpu
|| cpu
->pmsav7_dregion
== 0) {
2258 cpu
->has_mpu
= false;
2259 cpu
->pmsav7_dregion
= 0;
2260 cpu
->pmsav8r_hdregion
= 0;
2263 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
2264 arm_feature(env
, ARM_FEATURE_V7
)) {
2265 uint32_t nr
= cpu
->pmsav7_dregion
;
2268 error_setg(errp
, "PMSAv7 MPU #regions invalid %" PRIu32
, nr
);
2273 if (arm_feature(env
, ARM_FEATURE_V8
)) {
2275 env
->pmsav8
.rbar
[M_REG_NS
] = g_new0(uint32_t, nr
);
2276 env
->pmsav8
.rlar
[M_REG_NS
] = g_new0(uint32_t, nr
);
2277 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
2278 env
->pmsav8
.rbar
[M_REG_S
] = g_new0(uint32_t, nr
);
2279 env
->pmsav8
.rlar
[M_REG_S
] = g_new0(uint32_t, nr
);
2282 env
->pmsav7
.drbar
= g_new0(uint32_t, nr
);
2283 env
->pmsav7
.drsr
= g_new0(uint32_t, nr
);
2284 env
->pmsav7
.dracr
= g_new0(uint32_t, nr
);
2288 if (cpu
->pmsav8r_hdregion
> 0xff) {
2289 error_setg(errp
, "PMSAv8 MPU EL2 #regions invalid %" PRIu32
,
2290 cpu
->pmsav8r_hdregion
);
2294 if (cpu
->pmsav8r_hdregion
) {
2295 env
->pmsav8
.hprbar
= g_new0(uint32_t,
2296 cpu
->pmsav8r_hdregion
);
2297 env
->pmsav8
.hprlar
= g_new0(uint32_t,
2298 cpu
->pmsav8r_hdregion
);
2302 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
2303 uint32_t nr
= cpu
->sau_sregion
;
2306 error_setg(errp
, "v8M SAU #regions invalid %" PRIu32
, nr
);
2311 env
->sau
.rbar
= g_new0(uint32_t, nr
);
2312 env
->sau
.rlar
= g_new0(uint32_t, nr
);
2316 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
2317 set_feature(env
, ARM_FEATURE_VBAR
);
2320 #ifndef CONFIG_USER_ONLY
2321 if (tcg_enabled() && cpu_isar_feature(aa64_rme
, cpu
)) {
2322 arm_register_el_change_hook(cpu
, >_rme_post_el_change
, 0);
2326 register_cp_regs_for_features(cpu
);
2327 arm_cpu_register_gdb_regs_for_features(cpu
);
2329 init_cpreg_list(cpu
);
2331 #ifndef CONFIG_USER_ONLY
2332 MachineState
*ms
= MACHINE(qdev_get_machine());
2333 unsigned int smp_cpus
= ms
->smp
.cpus
;
2334 bool has_secure
= cpu
->has_el3
|| arm_feature(env
, ARM_FEATURE_M_SECURITY
);
2337 * We must set cs->num_ases to the final value before
2338 * the first call to cpu_address_space_init.
2340 if (cpu
->tag_memory
!= NULL
) {
2341 cs
->num_ases
= 3 + has_secure
;
2343 cs
->num_ases
= 1 + has_secure
;
2347 if (!cpu
->secure_memory
) {
2348 cpu
->secure_memory
= cs
->memory
;
2350 cpu_address_space_init(cs
, ARMASIdx_S
, "cpu-secure-memory",
2351 cpu
->secure_memory
);
2354 if (cpu
->tag_memory
!= NULL
) {
2355 cpu_address_space_init(cs
, ARMASIdx_TagNS
, "cpu-tag-memory",
2358 cpu_address_space_init(cs
, ARMASIdx_TagS
, "cpu-tag-memory",
2359 cpu
->secure_tag_memory
);
2363 cpu_address_space_init(cs
, ARMASIdx_NS
, "cpu-memory", cs
->memory
);
2365 /* No core_count specified, default to smp_cpus. */
2366 if (cpu
->core_count
== -1) {
2367 cpu
->core_count
= smp_cpus
;
2371 if (tcg_enabled()) {
2372 int dcz_blocklen
= 4 << cpu
->dcz_blocksize
;
2375 * We only support DCZ blocklen that fits on one page.
2377 * Architectually this is always true. However TARGET_PAGE_SIZE
2378 * is variable and, for compatibility with -machine virt-2.7,
2379 * is only 1KiB, as an artifact of legacy ARMv5 subpage support.
2380 * But even then, while the largest architectural DCZ blocklen
2381 * is 2KiB, no cpu actually uses such a large blocklen.
2383 assert(dcz_blocklen
<= TARGET_PAGE_SIZE
);
2386 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say
2387 * both nibbles of each byte storing tag data may be written at once.
2388 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32.
2390 if (cpu_isar_feature(aa64_mte
, cpu
)) {
2391 assert(dcz_blocklen
>= 2 * TAG_GRANULE
);
2398 acc
->parent_realize(dev
, errp
);
2401 static ObjectClass
*arm_cpu_class_by_name(const char *cpu_model
)
2406 const char *cpunamestr
;
2408 cpuname
= g_strsplit(cpu_model
, ",", 1);
2409 cpunamestr
= cpuname
[0];
2410 #ifdef CONFIG_USER_ONLY
2411 /* For backwards compatibility usermode emulation allows "-cpu any",
2412 * which has the same semantics as "-cpu max".
2414 if (!strcmp(cpunamestr
, "any")) {
2418 typename
= g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr
);
2419 oc
= object_class_by_name(typename
);
2420 g_strfreev(cpuname
);
2426 static Property arm_cpu_properties
[] = {
2427 DEFINE_PROP_UINT64("midr", ARMCPU
, midr
, 0),
2428 DEFINE_PROP_UINT64("mp-affinity", ARMCPU
,
2429 mp_affinity
, ARM64_AFFINITY_INVALID
),
2430 DEFINE_PROP_INT32("node-id", ARMCPU
, node_id
, CPU_UNSET_NUMA_NODE_ID
),
2431 DEFINE_PROP_INT32("core-count", ARMCPU
, core_count
, -1),
2432 DEFINE_PROP_END_OF_LIST()
2435 static const gchar
*arm_gdb_arch_name(CPUState
*cs
)
2437 ARMCPU
*cpu
= ARM_CPU(cs
);
2438 CPUARMState
*env
= &cpu
->env
;
2440 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
2446 #ifndef CONFIG_USER_ONLY
2447 #include "hw/core/sysemu-cpu-ops.h"
2449 static const struct SysemuCPUOps arm_sysemu_ops
= {
2450 .get_phys_page_attrs_debug
= arm_cpu_get_phys_page_attrs_debug
,
2451 .asidx_from_attrs
= arm_asidx_from_attrs
,
2452 .write_elf32_note
= arm_cpu_write_elf32_note
,
2453 .write_elf64_note
= arm_cpu_write_elf64_note
,
2454 .virtio_is_big_endian
= arm_cpu_virtio_is_big_endian
,
2455 .legacy_vmsd
= &vmstate_arm_cpu
,
2460 static const struct TCGCPUOps arm_tcg_ops
= {
2461 .initialize
= arm_translate_init
,
2462 .synchronize_from_tb
= arm_cpu_synchronize_from_tb
,
2463 .debug_excp_handler
= arm_debug_excp_handler
,
2464 .restore_state_to_opc
= arm_restore_state_to_opc
,
2466 #ifdef CONFIG_USER_ONLY
2467 .record_sigsegv
= arm_cpu_record_sigsegv
,
2468 .record_sigbus
= arm_cpu_record_sigbus
,
2470 .tlb_fill
= arm_cpu_tlb_fill
,
2471 .cpu_exec_interrupt
= arm_cpu_exec_interrupt
,
2472 .do_interrupt
= arm_cpu_do_interrupt
,
2473 .do_transaction_failed
= arm_cpu_do_transaction_failed
,
2474 .do_unaligned_access
= arm_cpu_do_unaligned_access
,
2475 .adjust_watchpoint_address
= arm_adjust_watchpoint_address
,
2476 .debug_check_watchpoint
= arm_debug_check_watchpoint
,
2477 .debug_check_breakpoint
= arm_debug_check_breakpoint
,
2478 #endif /* !CONFIG_USER_ONLY */
2480 #endif /* CONFIG_TCG */
2482 static void arm_cpu_class_init(ObjectClass
*oc
, void *data
)
2484 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2485 CPUClass
*cc
= CPU_CLASS(acc
);
2486 DeviceClass
*dc
= DEVICE_CLASS(oc
);
2487 ResettableClass
*rc
= RESETTABLE_CLASS(oc
);
2489 device_class_set_parent_realize(dc
, arm_cpu_realizefn
,
2490 &acc
->parent_realize
);
2492 device_class_set_props(dc
, arm_cpu_properties
);
2494 resettable_class_set_parent_phases(rc
, NULL
, arm_cpu_reset_hold
, NULL
,
2495 &acc
->parent_phases
);
2497 cc
->class_by_name
= arm_cpu_class_by_name
;
2498 cc
->has_work
= arm_cpu_has_work
;
2499 cc
->dump_state
= arm_cpu_dump_state
;
2500 cc
->set_pc
= arm_cpu_set_pc
;
2501 cc
->get_pc
= arm_cpu_get_pc
;
2502 cc
->gdb_read_register
= arm_cpu_gdb_read_register
;
2503 cc
->gdb_write_register
= arm_cpu_gdb_write_register
;
2504 #ifndef CONFIG_USER_ONLY
2505 cc
->sysemu_ops
= &arm_sysemu_ops
;
2507 cc
->gdb_num_core_regs
= 26;
2508 cc
->gdb_arch_name
= arm_gdb_arch_name
;
2509 cc
->gdb_get_dynamic_xml
= arm_gdb_get_dynamic_xml
;
2510 cc
->gdb_stop_before_watchpoint
= true;
2511 cc
->disas_set_info
= arm_disas_set_info
;
2514 cc
->tcg_ops
= &arm_tcg_ops
;
2515 #endif /* CONFIG_TCG */
2518 static void arm_cpu_instance_init(Object
*obj
)
2520 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(obj
);
2522 acc
->info
->initfn(obj
);
2523 arm_cpu_post_init(obj
);
2526 static void cpu_register_class_init(ObjectClass
*oc
, void *data
)
2528 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2529 CPUClass
*cc
= CPU_CLASS(acc
);
2532 cc
->gdb_core_xml_file
= "arm-core.xml";
2535 void arm_cpu_register(const ARMCPUInfo
*info
)
2537 TypeInfo type_info
= {
2538 .parent
= TYPE_ARM_CPU
,
2539 .instance_init
= arm_cpu_instance_init
,
2540 .class_init
= info
->class_init
?: cpu_register_class_init
,
2541 .class_data
= (void *)info
,
2544 type_info
.name
= g_strdup_printf("%s-" TYPE_ARM_CPU
, info
->name
);
2545 type_register(&type_info
);
2546 g_free((void *)type_info
.name
);
2549 static const TypeInfo arm_cpu_type_info
= {
2550 .name
= TYPE_ARM_CPU
,
2552 .instance_size
= sizeof(ARMCPU
),
2553 .instance_align
= __alignof__(ARMCPU
),
2554 .instance_init
= arm_cpu_initfn
,
2555 .instance_finalize
= arm_cpu_finalizefn
,
2557 .class_size
= sizeof(ARMCPUClass
),
2558 .class_init
= arm_cpu_class_init
,
2561 static void arm_cpu_register_types(void)
2563 type_register_static(&arm_cpu_type_info
);
2566 type_init(arm_cpu_register_types
)