4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu/osdep.h"
22 #include "qemu/qemu-print.h"
23 #include "qemu/timer.h"
25 #include "exec/page-vary.h"
26 #include "target/arm/idau.h"
27 #include "qemu/module.h"
28 #include "qapi/error.h"
31 #include "hw/core/tcg-cpu-ops.h"
32 #endif /* CONFIG_TCG */
33 #include "internals.h"
34 #include "cpu-features.h"
35 #include "exec/exec-all.h"
36 #include "hw/qdev-properties.h"
37 #if !defined(CONFIG_USER_ONLY)
38 #include "hw/loader.h"
39 #include "hw/boards.h"
41 #include "hw/intc/armv7m_nvic.h"
42 #endif /* CONFIG_TCG */
43 #endif /* !CONFIG_USER_ONLY */
44 #include "sysemu/tcg.h"
45 #include "sysemu/qtest.h"
46 #include "sysemu/hw_accel.h"
48 #include "disas/capstone.h"
49 #include "fpu/softfloat.h"
52 static void arm_cpu_set_pc(CPUState
*cs
, vaddr value
)
54 ARMCPU
*cpu
= ARM_CPU(cs
);
55 CPUARMState
*env
= &cpu
->env
;
61 env
->regs
[15] = value
& ~1;
62 env
->thumb
= value
& 1;
66 static vaddr
arm_cpu_get_pc(CPUState
*cs
)
68 ARMCPU
*cpu
= ARM_CPU(cs
);
69 CPUARMState
*env
= &cpu
->env
;
79 void arm_cpu_synchronize_from_tb(CPUState
*cs
,
80 const TranslationBlock
*tb
)
82 /* The program counter is always up to date with CF_PCREL. */
83 if (!(tb_cflags(tb
) & CF_PCREL
)) {
84 CPUARMState
*env
= cpu_env(cs
);
86 * It's OK to look at env for the current mode here, because it's
87 * never possible for an AArch64 TB to chain to an AArch32 TB.
92 env
->regs
[15] = tb
->pc
;
97 void arm_restore_state_to_opc(CPUState
*cs
,
98 const TranslationBlock
*tb
,
101 CPUARMState
*env
= cpu_env(cs
);
104 if (tb_cflags(tb
) & CF_PCREL
) {
105 env
->pc
= (env
->pc
& TARGET_PAGE_MASK
) | data
[0];
109 env
->condexec_bits
= 0;
110 env
->exception
.syndrome
= data
[2] << ARM_INSN_START_WORD2_SHIFT
;
112 if (tb_cflags(tb
) & CF_PCREL
) {
113 env
->regs
[15] = (env
->regs
[15] & TARGET_PAGE_MASK
) | data
[0];
115 env
->regs
[15] = data
[0];
117 env
->condexec_bits
= data
[1];
118 env
->exception
.syndrome
= data
[2] << ARM_INSN_START_WORD2_SHIFT
;
121 #endif /* CONFIG_TCG */
123 static bool arm_cpu_has_work(CPUState
*cs
)
125 ARMCPU
*cpu
= ARM_CPU(cs
);
127 return (cpu
->power_state
!= PSCI_OFF
)
128 && cs
->interrupt_request
&
129 (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
130 | CPU_INTERRUPT_VFIQ
| CPU_INTERRUPT_VIRQ
| CPU_INTERRUPT_VSERR
131 | CPU_INTERRUPT_EXITTB
);
134 void arm_register_pre_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
137 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
140 entry
->opaque
= opaque
;
142 QLIST_INSERT_HEAD(&cpu
->pre_el_change_hooks
, entry
, node
);
145 void arm_register_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
148 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
151 entry
->opaque
= opaque
;
153 QLIST_INSERT_HEAD(&cpu
->el_change_hooks
, entry
, node
);
156 static void cp_reg_reset(gpointer key
, gpointer value
, gpointer opaque
)
158 /* Reset a single ARMCPRegInfo register */
159 ARMCPRegInfo
*ri
= value
;
160 ARMCPU
*cpu
= opaque
;
162 if (ri
->type
& (ARM_CP_SPECIAL_MASK
| ARM_CP_ALIAS
)) {
167 ri
->resetfn(&cpu
->env
, ri
);
171 /* A zero offset is never possible as it would be regs[0]
172 * so we use it to indicate that reset is being handled elsewhere.
173 * This is basically only used for fields in non-core coprocessors
174 * (like the pxa2xx ones).
176 if (!ri
->fieldoffset
) {
180 if (cpreg_field_is_64bit(ri
)) {
181 CPREG_FIELD64(&cpu
->env
, ri
) = ri
->resetvalue
;
183 CPREG_FIELD32(&cpu
->env
, ri
) = ri
->resetvalue
;
187 static void cp_reg_check_reset(gpointer key
, gpointer value
, gpointer opaque
)
189 /* Purely an assertion check: we've already done reset once,
190 * so now check that running the reset for the cpreg doesn't
191 * change its value. This traps bugs where two different cpregs
192 * both try to reset the same state field but to different values.
194 ARMCPRegInfo
*ri
= value
;
195 ARMCPU
*cpu
= opaque
;
196 uint64_t oldvalue
, newvalue
;
198 if (ri
->type
& (ARM_CP_SPECIAL_MASK
| ARM_CP_ALIAS
| ARM_CP_NO_RAW
)) {
202 oldvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
203 cp_reg_reset(key
, value
, opaque
);
204 newvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
205 assert(oldvalue
== newvalue
);
208 static void arm_cpu_reset_hold(Object
*obj
)
210 CPUState
*s
= CPU(obj
);
211 ARMCPU
*cpu
= ARM_CPU(s
);
212 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(cpu
);
213 CPUARMState
*env
= &cpu
->env
;
215 if (acc
->parent_phases
.hold
) {
216 acc
->parent_phases
.hold(obj
);
219 memset(env
, 0, offsetof(CPUARMState
, end_reset_fields
));
221 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_reset
, cpu
);
222 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_check_reset
, cpu
);
224 env
->vfp
.xregs
[ARM_VFP_FPSID
] = cpu
->reset_fpsid
;
225 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = cpu
->isar
.mvfr0
;
226 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = cpu
->isar
.mvfr1
;
227 env
->vfp
.xregs
[ARM_VFP_MVFR2
] = cpu
->isar
.mvfr2
;
229 cpu
->power_state
= s
->start_powered_off
? PSCI_OFF
: PSCI_ON
;
231 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
232 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
235 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
236 /* 64 bit CPUs always start in 64 bit mode */
238 #if defined(CONFIG_USER_ONLY)
239 env
->pstate
= PSTATE_MODE_EL0t
;
240 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
241 env
->cp15
.sctlr_el
[1] |= SCTLR_UCT
| SCTLR_UCI
| SCTLR_DZE
;
242 /* Enable all PAC keys. */
243 env
->cp15
.sctlr_el
[1] |= (SCTLR_EnIA
| SCTLR_EnIB
|
244 SCTLR_EnDA
| SCTLR_EnDB
);
245 /* Trap on btype=3 for PACIxSP. */
246 env
->cp15
.sctlr_el
[1] |= SCTLR_BT0
;
247 /* Trap on implementation defined registers. */
248 if (cpu_isar_feature(aa64_tidcp1
, cpu
)) {
249 env
->cp15
.sctlr_el
[1] |= SCTLR_TIDCP
;
251 /* and to the FP/Neon instructions */
252 env
->cp15
.cpacr_el1
= FIELD_DP64(env
->cp15
.cpacr_el1
,
254 /* and to the SVE instructions, with default vector length */
255 if (cpu_isar_feature(aa64_sve
, cpu
)) {
256 env
->cp15
.cpacr_el1
= FIELD_DP64(env
->cp15
.cpacr_el1
,
258 env
->vfp
.zcr_el
[1] = cpu
->sve_default_vq
- 1;
260 /* and for SME instructions, with default vector length, and TPIDR2 */
261 if (cpu_isar_feature(aa64_sme
, cpu
)) {
262 env
->cp15
.sctlr_el
[1] |= SCTLR_EnTP2
;
263 env
->cp15
.cpacr_el1
= FIELD_DP64(env
->cp15
.cpacr_el1
,
265 env
->vfp
.smcr_el
[1] = cpu
->sme_default_vq
- 1;
266 if (cpu_isar_feature(aa64_sme_fa64
, cpu
)) {
267 env
->vfp
.smcr_el
[1] = FIELD_DP64(env
->vfp
.smcr_el
[1],
272 * Enable 48-bit address space (TODO: take reserved_va into account).
273 * Enable TBI0 but not TBI1.
274 * Note that this must match useronly_clean_ptr.
276 env
->cp15
.tcr_el
[1] = 5 | (1ULL << 37);
279 if (cpu_isar_feature(aa64_mte
, cpu
)) {
280 /* Enable tag access, but leave TCF0 as No Effect (0). */
281 env
->cp15
.sctlr_el
[1] |= SCTLR_ATA0
;
283 * Exclude all tags, so that tag 0 is always used.
284 * This corresponds to Linux current->thread.gcr_incl = 0.
286 * Set RRND, so that helper_irg() will generate a seed later.
287 * Here in cpu_reset(), the crypto subsystem has not yet been
290 env
->cp15
.gcr_el1
= 0x1ffff;
293 * Disable access to SCXTNUM_EL0 from CSV2_1p2.
294 * This is not yet exposed from the Linux kernel in any way.
296 env
->cp15
.sctlr_el
[1] |= SCTLR_TSCXT
;
297 /* Disable access to Debug Communication Channel (DCC). */
298 env
->cp15
.mdscr_el1
|= 1 << 12;
299 /* Enable FEAT_MOPS */
300 env
->cp15
.sctlr_el
[1] |= SCTLR_MSCEN
;
302 /* Reset into the highest available EL */
303 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
304 env
->pstate
= PSTATE_MODE_EL3h
;
305 } else if (arm_feature(env
, ARM_FEATURE_EL2
)) {
306 env
->pstate
= PSTATE_MODE_EL2h
;
308 env
->pstate
= PSTATE_MODE_EL1h
;
311 /* Sample rvbar at reset. */
312 env
->cp15
.rvbar
= cpu
->rvbar_prop
;
313 env
->pc
= env
->cp15
.rvbar
;
316 #if defined(CONFIG_USER_ONLY)
317 /* Userspace expects access to cp10 and cp11 for FP/Neon */
318 env
->cp15
.cpacr_el1
= FIELD_DP64(env
->cp15
.cpacr_el1
,
320 env
->cp15
.cpacr_el1
= FIELD_DP64(env
->cp15
.cpacr_el1
,
323 if (arm_feature(env
, ARM_FEATURE_V8
)) {
324 env
->cp15
.rvbar
= cpu
->rvbar_prop
;
325 env
->regs
[15] = cpu
->rvbar_prop
;
329 #if defined(CONFIG_USER_ONLY)
330 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
331 /* For user mode we must enable access to coprocessors */
332 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
333 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
334 env
->cp15
.c15_cpar
= 3;
335 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
336 env
->cp15
.c15_cpar
= 1;
341 * If the highest available EL is EL2, AArch32 will start in Hyp
342 * mode; otherwise it starts in SVC. Note that if we start in
343 * AArch64 then these values in the uncached_cpsr will be ignored.
345 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
346 !arm_feature(env
, ARM_FEATURE_EL3
)) {
347 env
->uncached_cpsr
= ARM_CPU_MODE_HYP
;
349 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
;
351 env
->daif
= PSTATE_D
| PSTATE_A
| PSTATE_I
| PSTATE_F
;
353 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
354 * executing as AArch32 then check if highvecs are enabled and
355 * adjust the PC accordingly.
357 if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
358 env
->regs
[15] = 0xFFFF0000;
361 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
364 if (arm_feature(env
, ARM_FEATURE_M
)) {
365 #ifndef CONFIG_USER_ONLY
366 uint32_t initial_msp
; /* Loaded from 0x0 */
367 uint32_t initial_pc
; /* Loaded from 0x4 */
372 if (cpu_isar_feature(aa32_lob
, cpu
)) {
374 * LTPSIZE is constant 4 if MVE not implemented, and resets
375 * to an UNKNOWN value if MVE is implemented. We choose to
378 env
->v7m
.ltpsize
= 4;
379 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */
380 env
->v7m
.fpdscr
[M_REG_NS
] = 4 << FPCR_LTPSIZE_SHIFT
;
381 env
->v7m
.fpdscr
[M_REG_S
] = 4 << FPCR_LTPSIZE_SHIFT
;
384 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
385 env
->v7m
.secure
= true;
387 /* This bit resets to 0 if security is supported, but 1 if
388 * it is not. The bit is not present in v7M, but we set it
389 * here so we can avoid having to make checks on it conditional
390 * on ARM_FEATURE_V8 (we don't let the guest see the bit).
392 env
->v7m
.aircr
= R_V7M_AIRCR_BFHFNMINS_MASK
;
394 * Set NSACR to indicate "NS access permitted to everything";
395 * this avoids having to have all the tests of it being
396 * conditional on ARM_FEATURE_M_SECURITY. Note also that from
397 * v8.1M the guest-visible value of NSACR in a CPU without the
398 * Security Extension is 0xcff.
400 env
->v7m
.nsacr
= 0xcff;
403 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
404 * that it resets to 1, so QEMU always does that rather than making
405 * it dependent on CPU model. In v8M it is RES1.
407 env
->v7m
.ccr
[M_REG_NS
] = R_V7M_CCR_STKALIGN_MASK
;
408 env
->v7m
.ccr
[M_REG_S
] = R_V7M_CCR_STKALIGN_MASK
;
409 if (arm_feature(env
, ARM_FEATURE_V8
)) {
410 /* in v8M the NONBASETHRDENA bit [0] is RES1 */
411 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
412 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
414 if (!arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
415 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
416 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
419 if (cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
420 env
->v7m
.fpccr
[M_REG_NS
] = R_V7M_FPCCR_ASPEN_MASK
;
421 env
->v7m
.fpccr
[M_REG_S
] = R_V7M_FPCCR_ASPEN_MASK
|
422 R_V7M_FPCCR_LSPEN_MASK
| R_V7M_FPCCR_S_MASK
;
425 #ifndef CONFIG_USER_ONLY
426 /* Unlike A/R profile, M profile defines the reset LR value */
427 env
->regs
[14] = 0xffffffff;
429 env
->v7m
.vecbase
[M_REG_S
] = cpu
->init_svtor
& 0xffffff80;
430 env
->v7m
.vecbase
[M_REG_NS
] = cpu
->init_nsvtor
& 0xffffff80;
432 /* Load the initial SP and PC from offset 0 and 4 in the vector table */
433 vecbase
= env
->v7m
.vecbase
[env
->v7m
.secure
];
434 rom
= rom_ptr_for_as(s
->as
, vecbase
, 8);
436 /* Address zero is covered by ROM which hasn't yet been
437 * copied into physical memory.
439 initial_msp
= ldl_p(rom
);
440 initial_pc
= ldl_p(rom
+ 4);
442 /* Address zero not covered by a ROM blob, or the ROM blob
443 * is in non-modifiable memory and this is a second reset after
444 * it got copied into memory. In the latter case, rom_ptr
445 * will return a NULL pointer and we should use ldl_phys instead.
447 initial_msp
= ldl_phys(s
->as
, vecbase
);
448 initial_pc
= ldl_phys(s
->as
, vecbase
+ 4);
451 qemu_log_mask(CPU_LOG_INT
,
452 "Loaded reset SP 0x%x PC 0x%x from vector table\n",
453 initial_msp
, initial_pc
);
455 env
->regs
[13] = initial_msp
& 0xFFFFFFFC;
456 env
->regs
[15] = initial_pc
& ~1;
457 env
->thumb
= initial_pc
& 1;
460 * For user mode we run non-secure and with access to the FPU.
461 * The FPU context is active (ie does not need further setup)
462 * and is owned by non-secure.
464 env
->v7m
.secure
= false;
465 env
->v7m
.nsacr
= 0xcff;
466 env
->v7m
.cpacr
[M_REG_NS
] = 0xf0ffff;
467 env
->v7m
.fpccr
[M_REG_S
] &=
468 ~(R_V7M_FPCCR_LSPEN_MASK
| R_V7M_FPCCR_S_MASK
);
469 env
->v7m
.control
[M_REG_S
] |= R_V7M_CONTROL_FPCA_MASK
;
473 /* M profile requires that reset clears the exclusive monitor;
474 * A profile does not, but clearing it makes more sense than having it
475 * set with an exclusive access on address zero.
477 arm_clear_exclusive(env
);
479 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
480 if (cpu
->pmsav7_dregion
> 0) {
481 if (arm_feature(env
, ARM_FEATURE_V8
)) {
482 memset(env
->pmsav8
.rbar
[M_REG_NS
], 0,
483 sizeof(*env
->pmsav8
.rbar
[M_REG_NS
])
484 * cpu
->pmsav7_dregion
);
485 memset(env
->pmsav8
.rlar
[M_REG_NS
], 0,
486 sizeof(*env
->pmsav8
.rlar
[M_REG_NS
])
487 * cpu
->pmsav7_dregion
);
488 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
489 memset(env
->pmsav8
.rbar
[M_REG_S
], 0,
490 sizeof(*env
->pmsav8
.rbar
[M_REG_S
])
491 * cpu
->pmsav7_dregion
);
492 memset(env
->pmsav8
.rlar
[M_REG_S
], 0,
493 sizeof(*env
->pmsav8
.rlar
[M_REG_S
])
494 * cpu
->pmsav7_dregion
);
496 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
497 memset(env
->pmsav7
.drbar
, 0,
498 sizeof(*env
->pmsav7
.drbar
) * cpu
->pmsav7_dregion
);
499 memset(env
->pmsav7
.drsr
, 0,
500 sizeof(*env
->pmsav7
.drsr
) * cpu
->pmsav7_dregion
);
501 memset(env
->pmsav7
.dracr
, 0,
502 sizeof(*env
->pmsav7
.dracr
) * cpu
->pmsav7_dregion
);
506 if (cpu
->pmsav8r_hdregion
> 0) {
507 memset(env
->pmsav8
.hprbar
, 0,
508 sizeof(*env
->pmsav8
.hprbar
) * cpu
->pmsav8r_hdregion
);
509 memset(env
->pmsav8
.hprlar
, 0,
510 sizeof(*env
->pmsav8
.hprlar
) * cpu
->pmsav8r_hdregion
);
513 env
->pmsav7
.rnr
[M_REG_NS
] = 0;
514 env
->pmsav7
.rnr
[M_REG_S
] = 0;
515 env
->pmsav8
.mair0
[M_REG_NS
] = 0;
516 env
->pmsav8
.mair0
[M_REG_S
] = 0;
517 env
->pmsav8
.mair1
[M_REG_NS
] = 0;
518 env
->pmsav8
.mair1
[M_REG_S
] = 0;
521 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
522 if (cpu
->sau_sregion
> 0) {
523 memset(env
->sau
.rbar
, 0, sizeof(*env
->sau
.rbar
) * cpu
->sau_sregion
);
524 memset(env
->sau
.rlar
, 0, sizeof(*env
->sau
.rlar
) * cpu
->sau_sregion
);
527 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
528 * the Cortex-M33 does.
533 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
534 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
535 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
536 set_default_nan_mode(1, &env
->vfp
.standard_fp_status_f16
);
537 set_float_detect_tininess(float_tininess_before_rounding
,
538 &env
->vfp
.fp_status
);
539 set_float_detect_tininess(float_tininess_before_rounding
,
540 &env
->vfp
.standard_fp_status
);
541 set_float_detect_tininess(float_tininess_before_rounding
,
542 &env
->vfp
.fp_status_f16
);
543 set_float_detect_tininess(float_tininess_before_rounding
,
544 &env
->vfp
.standard_fp_status_f16
);
545 #ifndef CONFIG_USER_ONLY
547 kvm_arm_reset_vcpu(cpu
);
552 hw_breakpoint_update_all(cpu
);
553 hw_watchpoint_update_all(cpu
);
555 arm_rebuild_hflags(env
);
559 void arm_emulate_firmware_reset(CPUState
*cpustate
, int target_el
)
561 ARMCPU
*cpu
= ARM_CPU(cpustate
);
562 CPUARMState
*env
= &cpu
->env
;
563 bool have_el3
= arm_feature(env
, ARM_FEATURE_EL3
);
564 bool have_el2
= arm_feature(env
, ARM_FEATURE_EL2
);
567 * Check we have the EL we're aiming for. If that is the
568 * highest implemented EL, then cpu_reset has already done
582 if (!have_el3
&& !have_el2
) {
587 g_assert_not_reached();
592 * Set the EL3 state so code can run at EL2. This should match
593 * the requirements set by Linux in its booting spec.
596 env
->cp15
.scr_el3
|= SCR_RW
;
597 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
598 env
->cp15
.scr_el3
|= SCR_API
| SCR_APK
;
600 if (cpu_isar_feature(aa64_mte
, cpu
)) {
601 env
->cp15
.scr_el3
|= SCR_ATA
;
603 if (cpu_isar_feature(aa64_sve
, cpu
)) {
604 env
->cp15
.cptr_el
[3] |= R_CPTR_EL3_EZ_MASK
;
605 env
->vfp
.zcr_el
[3] = 0xf;
607 if (cpu_isar_feature(aa64_sme
, cpu
)) {
608 env
->cp15
.cptr_el
[3] |= R_CPTR_EL3_ESM_MASK
;
609 env
->cp15
.scr_el3
|= SCR_ENTP2
;
610 env
->vfp
.smcr_el
[3] = 0xf;
612 if (cpu_isar_feature(aa64_hcx
, cpu
)) {
613 env
->cp15
.scr_el3
|= SCR_HXEN
;
615 if (cpu_isar_feature(aa64_fgt
, cpu
)) {
616 env
->cp15
.scr_el3
|= SCR_FGTEN
;
620 if (target_el
== 2) {
621 /* If the guest is at EL2 then Linux expects the HVC insn to work */
622 env
->cp15
.scr_el3
|= SCR_HCE
;
625 /* Put CPU into non-secure state */
626 env
->cp15
.scr_el3
|= SCR_NS
;
627 /* Set NSACR.{CP11,CP10} so NS can access the FPU */
628 env
->cp15
.nsacr
|= 3 << 10;
631 if (have_el2
&& target_el
< 2) {
632 /* Set EL2 state so code can run at EL1. */
634 env
->cp15
.hcr_el2
|= HCR_RW
;
638 /* Set the CPU to the desired state */
640 env
->pstate
= aarch64_pstate_mode(target_el
, true);
642 static const uint32_t mode_for_el
[] = {
649 cpsr_write(env
, mode_for_el
[target_el
], CPSR_M
, CPSRWriteRaw
);
654 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
656 static inline bool arm_excp_unmasked(CPUState
*cs
, unsigned int excp_idx
,
657 unsigned int target_el
,
658 unsigned int cur_el
, bool secure
,
661 CPUARMState
*env
= cpu_env(cs
);
662 bool pstate_unmasked
;
663 bool unmasked
= false;
666 * Don't take exceptions if they target a lower EL.
667 * This check should catch any exceptions that would not be taken
670 if (cur_el
> target_el
) {
676 pstate_unmasked
= !(env
->daif
& PSTATE_F
);
680 pstate_unmasked
= !(env
->daif
& PSTATE_I
);
684 if (!(hcr_el2
& HCR_FMO
) || (hcr_el2
& HCR_TGE
)) {
685 /* VFIQs are only taken when hypervized. */
688 return !(env
->daif
& PSTATE_F
);
690 if (!(hcr_el2
& HCR_IMO
) || (hcr_el2
& HCR_TGE
)) {
691 /* VIRQs are only taken when hypervized. */
694 return !(env
->daif
& PSTATE_I
);
696 if (!(hcr_el2
& HCR_AMO
) || (hcr_el2
& HCR_TGE
)) {
697 /* VIRQs are only taken when hypervized. */
700 return !(env
->daif
& PSTATE_A
);
702 g_assert_not_reached();
706 * Use the target EL, current execution state and SCR/HCR settings to
707 * determine whether the corresponding CPSR bit is used to mask the
710 if ((target_el
> cur_el
) && (target_el
!= 1)) {
711 /* Exceptions targeting a higher EL may not be maskable */
712 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
716 * According to ARM DDI 0487H.a, an interrupt can be masked
717 * when HCR_E2H and HCR_TGE are both set regardless of the
718 * current Security state. Note that we need to revisit this
719 * part again once we need to support NMI.
721 if ((hcr_el2
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
726 /* Interrupt cannot be masked when the target EL is 3 */
730 g_assert_not_reached();
734 * The old 32-bit-only environment has a more complicated
735 * masking setup. HCR and SCR bits not only affect interrupt
736 * routing but also change the behaviour of masking.
743 * If FIQs are routed to EL3 or EL2 then there are cases where
744 * we override the CPSR.F in determining if the exception is
745 * masked or not. If neither of these are set then we fall back
746 * to the CPSR.F setting otherwise we further assess the state
749 hcr
= hcr_el2
& HCR_FMO
;
750 scr
= (env
->cp15
.scr_el3
& SCR_FIQ
);
753 * When EL3 is 32-bit, the SCR.FW bit controls whether the
754 * CPSR.F bit masks FIQ interrupts when taken in non-secure
755 * state. If SCR.FW is set then FIQs can be masked by CPSR.F
756 * when non-secure but only when FIQs are only routed to EL3.
758 scr
= scr
&& !((env
->cp15
.scr_el3
& SCR_FW
) && !hcr
);
762 * When EL3 execution state is 32-bit, if HCR.IMO is set then
763 * we may override the CPSR.I masking when in non-secure state.
764 * The SCR.IRQ setting has already been taken into consideration
765 * when setting the target EL, so it does not have a further
768 hcr
= hcr_el2
& HCR_IMO
;
772 g_assert_not_reached();
775 if ((scr
|| hcr
) && !secure
) {
782 * The PSTATE bits only mask the interrupt if we have not overridden the
785 return unmasked
|| pstate_unmasked
;
788 static bool arm_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
790 CPUClass
*cc
= CPU_GET_CLASS(cs
);
791 CPUARMState
*env
= cpu_env(cs
);
792 uint32_t cur_el
= arm_current_el(env
);
793 bool secure
= arm_is_secure(env
);
794 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
798 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */
800 if (interrupt_request
& CPU_INTERRUPT_FIQ
) {
802 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
803 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
804 cur_el
, secure
, hcr_el2
)) {
808 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
810 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
811 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
812 cur_el
, secure
, hcr_el2
)) {
816 if (interrupt_request
& CPU_INTERRUPT_VIRQ
) {
817 excp_idx
= EXCP_VIRQ
;
819 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
820 cur_el
, secure
, hcr_el2
)) {
824 if (interrupt_request
& CPU_INTERRUPT_VFIQ
) {
825 excp_idx
= EXCP_VFIQ
;
827 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
828 cur_el
, secure
, hcr_el2
)) {
832 if (interrupt_request
& CPU_INTERRUPT_VSERR
) {
833 excp_idx
= EXCP_VSERR
;
835 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
836 cur_el
, secure
, hcr_el2
)) {
837 /* Taking a virtual abort clears HCR_EL2.VSE */
838 env
->cp15
.hcr_el2
&= ~HCR_VSE
;
839 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VSERR
);
846 cs
->exception_index
= excp_idx
;
847 env
->exception
.target_el
= target_el
;
848 cc
->tcg_ops
->do_interrupt(cs
);
852 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
854 void arm_cpu_update_virq(ARMCPU
*cpu
)
857 * Update the interrupt level for VIRQ, which is the logical OR of
858 * the HCR_EL2.VI bit and the input line level from the GIC.
860 CPUARMState
*env
= &cpu
->env
;
861 CPUState
*cs
= CPU(cpu
);
863 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VI
) ||
864 (env
->irq_line_state
& CPU_INTERRUPT_VIRQ
);
866 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) != 0)) {
868 cpu_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
870 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
875 void arm_cpu_update_vfiq(ARMCPU
*cpu
)
878 * Update the interrupt level for VFIQ, which is the logical OR of
879 * the HCR_EL2.VF bit and the input line level from the GIC.
881 CPUARMState
*env
= &cpu
->env
;
882 CPUState
*cs
= CPU(cpu
);
884 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VF
) ||
885 (env
->irq_line_state
& CPU_INTERRUPT_VFIQ
);
887 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) != 0)) {
889 cpu_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
891 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
896 void arm_cpu_update_vserr(ARMCPU
*cpu
)
899 * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit.
901 CPUARMState
*env
= &cpu
->env
;
902 CPUState
*cs
= CPU(cpu
);
904 bool new_state
= env
->cp15
.hcr_el2
& HCR_VSE
;
906 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VSERR
) != 0)) {
908 cpu_interrupt(cs
, CPU_INTERRUPT_VSERR
);
910 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VSERR
);
915 #ifndef CONFIG_USER_ONLY
916 static void arm_cpu_set_irq(void *opaque
, int irq
, int level
)
918 ARMCPU
*cpu
= opaque
;
919 CPUARMState
*env
= &cpu
->env
;
920 CPUState
*cs
= CPU(cpu
);
921 static const int mask
[] = {
922 [ARM_CPU_IRQ
] = CPU_INTERRUPT_HARD
,
923 [ARM_CPU_FIQ
] = CPU_INTERRUPT_FIQ
,
924 [ARM_CPU_VIRQ
] = CPU_INTERRUPT_VIRQ
,
925 [ARM_CPU_VFIQ
] = CPU_INTERRUPT_VFIQ
928 if (!arm_feature(env
, ARM_FEATURE_EL2
) &&
929 (irq
== ARM_CPU_VIRQ
|| irq
== ARM_CPU_VFIQ
)) {
931 * The GIC might tell us about VIRQ and VFIQ state, but if we don't
932 * have EL2 support we don't care. (Unless the guest is doing something
933 * silly this will only be calls saying "level is still 0".)
939 env
->irq_line_state
|= mask
[irq
];
941 env
->irq_line_state
&= ~mask
[irq
];
946 arm_cpu_update_virq(cpu
);
949 arm_cpu_update_vfiq(cpu
);
954 cpu_interrupt(cs
, mask
[irq
]);
956 cpu_reset_interrupt(cs
, mask
[irq
]);
960 g_assert_not_reached();
964 static void arm_cpu_kvm_set_irq(void *opaque
, int irq
, int level
)
967 ARMCPU
*cpu
= opaque
;
968 CPUARMState
*env
= &cpu
->env
;
969 CPUState
*cs
= CPU(cpu
);
970 uint32_t linestate_bit
;
975 irq_id
= KVM_ARM_IRQ_CPU_IRQ
;
976 linestate_bit
= CPU_INTERRUPT_HARD
;
979 irq_id
= KVM_ARM_IRQ_CPU_FIQ
;
980 linestate_bit
= CPU_INTERRUPT_FIQ
;
983 g_assert_not_reached();
987 env
->irq_line_state
|= linestate_bit
;
989 env
->irq_line_state
&= ~linestate_bit
;
991 kvm_arm_set_irq(cs
->cpu_index
, KVM_ARM_IRQ_TYPE_CPU
, irq_id
, !!level
);
995 static bool arm_cpu_virtio_is_big_endian(CPUState
*cs
)
997 ARMCPU
*cpu
= ARM_CPU(cs
);
998 CPUARMState
*env
= &cpu
->env
;
1000 cpu_synchronize_state(cs
);
1001 return arm_cpu_data_is_big_endian(env
);
1006 static void arm_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
1008 ARMCPU
*ac
= ARM_CPU(cpu
);
1009 CPUARMState
*env
= &ac
->env
;
1013 info
->cap_arch
= CS_ARCH_ARM64
;
1014 info
->cap_insn_unit
= 4;
1015 info
->cap_insn_split
= 4;
1019 info
->cap_insn_unit
= 2;
1020 info
->cap_insn_split
= 4;
1021 cap_mode
= CS_MODE_THUMB
;
1023 info
->cap_insn_unit
= 4;
1024 info
->cap_insn_split
= 4;
1025 cap_mode
= CS_MODE_ARM
;
1027 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1028 cap_mode
|= CS_MODE_V8
;
1030 if (arm_feature(env
, ARM_FEATURE_M
)) {
1031 cap_mode
|= CS_MODE_MCLASS
;
1033 info
->cap_arch
= CS_ARCH_ARM
;
1034 info
->cap_mode
= cap_mode
;
1037 sctlr_b
= arm_sctlr_b(env
);
1038 if (bswap_code(sctlr_b
)) {
1039 #if TARGET_BIG_ENDIAN
1040 info
->endian
= BFD_ENDIAN_LITTLE
;
1042 info
->endian
= BFD_ENDIAN_BIG
;
1045 info
->flags
&= ~INSN_ARM_BE32
;
1046 #ifndef CONFIG_USER_ONLY
1048 info
->flags
|= INSN_ARM_BE32
;
1053 #ifdef TARGET_AARCH64
1055 static void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
1057 ARMCPU
*cpu
= ARM_CPU(cs
);
1058 CPUARMState
*env
= &cpu
->env
;
1059 uint32_t psr
= pstate_read(env
);
1061 int el
= arm_current_el(env
);
1062 uint64_t hcr
= arm_hcr_el2_eff(env
);
1063 const char *ns_status
;
1066 qemu_fprintf(f
, " PC=%016" PRIx64
" ", env
->pc
);
1067 for (i
= 0; i
< 32; i
++) {
1069 qemu_fprintf(f
, " SP=%016" PRIx64
"\n", env
->xregs
[i
]);
1071 qemu_fprintf(f
, "X%02d=%016" PRIx64
"%s", i
, env
->xregs
[i
],
1072 (i
+ 2) % 3 ? " " : "\n");
1076 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
1077 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
1081 qemu_fprintf(f
, "PSTATE=%08x %c%c%c%c %sEL%d%c",
1083 psr
& PSTATE_N
? 'N' : '-',
1084 psr
& PSTATE_Z
? 'Z' : '-',
1085 psr
& PSTATE_C
? 'C' : '-',
1086 psr
& PSTATE_V
? 'V' : '-',
1089 psr
& PSTATE_SP
? 'h' : 't');
1091 if (cpu_isar_feature(aa64_sme
, cpu
)) {
1092 qemu_fprintf(f
, " SVCR=%08" PRIx64
" %c%c",
1094 (FIELD_EX64(env
->svcr
, SVCR
, ZA
) ? 'Z' : '-'),
1095 (FIELD_EX64(env
->svcr
, SVCR
, SM
) ? 'S' : '-'));
1097 if (cpu_isar_feature(aa64_bti
, cpu
)) {
1098 qemu_fprintf(f
, " BTYPE=%d", (psr
& PSTATE_BTYPE
) >> 10);
1100 qemu_fprintf(f
, "%s%s%s",
1101 (hcr
& HCR_NV
) ? " NV" : "",
1102 (hcr
& HCR_NV1
) ? " NV1" : "",
1103 (hcr
& HCR_NV2
) ? " NV2" : "");
1104 if (!(flags
& CPU_DUMP_FPU
)) {
1105 qemu_fprintf(f
, "\n");
1108 if (fp_exception_el(env
, el
) != 0) {
1109 qemu_fprintf(f
, " FPU disabled\n");
1112 qemu_fprintf(f
, " FPCR=%08x FPSR=%08x\n",
1113 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
1115 if (cpu_isar_feature(aa64_sme
, cpu
) && FIELD_EX64(env
->svcr
, SVCR
, SM
)) {
1116 sve
= sme_exception_el(env
, el
) == 0;
1117 } else if (cpu_isar_feature(aa64_sve
, cpu
)) {
1118 sve
= sve_exception_el(env
, el
) == 0;
1124 int zcr_len
= sve_vqm1_for_el(env
, el
);
1126 for (i
= 0; i
<= FFR_PRED_NUM
; i
++) {
1128 if (i
== FFR_PRED_NUM
) {
1129 qemu_fprintf(f
, "FFR=");
1130 /* It's last, so end the line. */
1133 qemu_fprintf(f
, "P%02d=", i
);
1146 /* More than one quadword per predicate. */
1151 for (j
= zcr_len
/ 4; j
>= 0; j
--) {
1153 if (j
* 4 + 4 <= zcr_len
+ 1) {
1156 digits
= (zcr_len
% 4 + 1) * 4;
1158 qemu_fprintf(f
, "%0*" PRIx64
"%s", digits
,
1159 env
->vfp
.pregs
[i
].p
[j
],
1160 j
? ":" : eol
? "\n" : " ");
1166 * With vl=16, there are only 37 columns per register,
1167 * so output two registers per line.
1169 for (i
= 0; i
< 32; i
++) {
1170 qemu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
"%s",
1171 i
, env
->vfp
.zregs
[i
].d
[1],
1172 env
->vfp
.zregs
[i
].d
[0], i
& 1 ? "\n" : " ");
1175 for (i
= 0; i
< 32; i
++) {
1176 qemu_fprintf(f
, "Z%02d=", i
);
1177 for (j
= zcr_len
; j
>= 0; j
--) {
1178 qemu_fprintf(f
, "%016" PRIx64
":%016" PRIx64
"%s",
1179 env
->vfp
.zregs
[i
].d
[j
* 2 + 1],
1180 env
->vfp
.zregs
[i
].d
[j
* 2 + 0],
1186 for (i
= 0; i
< 32; i
++) {
1187 uint64_t *q
= aa64_vfp_qreg(env
, i
);
1188 qemu_fprintf(f
, "Q%02d=%016" PRIx64
":%016" PRIx64
"%s",
1189 i
, q
[1], q
[0], (i
& 1 ? "\n" : " "));
1193 if (cpu_isar_feature(aa64_sme
, cpu
) &&
1194 FIELD_EX64(env
->svcr
, SVCR
, ZA
) &&
1195 sme_exception_el(env
, el
) == 0) {
1196 int zcr_len
= sve_vqm1_for_el_sm(env
, el
, true);
1197 int svl
= (zcr_len
+ 1) * 16;
1198 int svl_lg10
= svl
< 100 ? 2 : 3;
1200 for (i
= 0; i
< svl
; i
++) {
1201 qemu_fprintf(f
, "ZA[%0*d]=", svl_lg10
, i
);
1202 for (j
= zcr_len
; j
>= 0; --j
) {
1203 qemu_fprintf(f
, "%016" PRIx64
":%016" PRIx64
"%c",
1204 env
->zarray
[i
].d
[2 * j
+ 1],
1205 env
->zarray
[i
].d
[2 * j
],
1214 static inline void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
1216 g_assert_not_reached();
1221 static void arm_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
1223 ARMCPU
*cpu
= ARM_CPU(cs
);
1224 CPUARMState
*env
= &cpu
->env
;
1228 aarch64_cpu_dump_state(cs
, f
, flags
);
1232 for (i
= 0; i
< 16; i
++) {
1233 qemu_fprintf(f
, "R%02d=%08x", i
, env
->regs
[i
]);
1235 qemu_fprintf(f
, "\n");
1237 qemu_fprintf(f
, " ");
1241 if (arm_feature(env
, ARM_FEATURE_M
)) {
1242 uint32_t xpsr
= xpsr_read(env
);
1244 const char *ns_status
= "";
1246 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1247 ns_status
= env
->v7m
.secure
? "S " : "NS ";
1250 if (xpsr
& XPSR_EXCP
) {
1253 if (env
->v7m
.control
[env
->v7m
.secure
] & R_V7M_CONTROL_NPRIV_MASK
) {
1254 mode
= "unpriv-thread";
1256 mode
= "priv-thread";
1260 qemu_fprintf(f
, "XPSR=%08x %c%c%c%c %c %s%s\n",
1262 xpsr
& XPSR_N
? 'N' : '-',
1263 xpsr
& XPSR_Z
? 'Z' : '-',
1264 xpsr
& XPSR_C
? 'C' : '-',
1265 xpsr
& XPSR_V
? 'V' : '-',
1266 xpsr
& XPSR_T
? 'T' : 'A',
1270 uint32_t psr
= cpsr_read(env
);
1271 const char *ns_status
= "";
1273 if (arm_feature(env
, ARM_FEATURE_EL3
) &&
1274 (psr
& CPSR_M
) != ARM_CPU_MODE_MON
) {
1275 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
1278 qemu_fprintf(f
, "PSR=%08x %c%c%c%c %c %s%s%d\n",
1280 psr
& CPSR_N
? 'N' : '-',
1281 psr
& CPSR_Z
? 'Z' : '-',
1282 psr
& CPSR_C
? 'C' : '-',
1283 psr
& CPSR_V
? 'V' : '-',
1284 psr
& CPSR_T
? 'T' : 'A',
1286 aarch32_mode_name(psr
), (psr
& 0x10) ? 32 : 26);
1289 if (flags
& CPU_DUMP_FPU
) {
1291 if (cpu_isar_feature(aa32_simd_r32
, cpu
)) {
1293 } else if (cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
1296 for (i
= 0; i
< numvfpregs
; i
++) {
1297 uint64_t v
= *aa32_vfp_dreg(env
, i
);
1298 qemu_fprintf(f
, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64
"\n",
1300 i
* 2 + 1, (uint32_t)(v
>> 32),
1303 qemu_fprintf(f
, "FPSCR: %08x\n", vfp_get_fpscr(env
));
1304 if (cpu_isar_feature(aa32_mve
, cpu
)) {
1305 qemu_fprintf(f
, "VPR: %08x\n", env
->v7m
.vpr
);
1310 uint64_t arm_cpu_mp_affinity(int idx
, uint8_t clustersz
)
1312 uint32_t Aff1
= idx
/ clustersz
;
1313 uint32_t Aff0
= idx
% clustersz
;
1314 return (Aff1
<< ARM_AFF1_SHIFT
) | Aff0
;
1317 static void arm_cpu_initfn(Object
*obj
)
1319 ARMCPU
*cpu
= ARM_CPU(obj
);
1321 cpu
->cp_regs
= g_hash_table_new_full(g_direct_hash
, g_direct_equal
,
1324 QLIST_INIT(&cpu
->pre_el_change_hooks
);
1325 QLIST_INIT(&cpu
->el_change_hooks
);
1327 #ifdef CONFIG_USER_ONLY
1328 # ifdef TARGET_AARCH64
1330 * The linux kernel defaults to 512-bit for SVE, and 256-bit for SME.
1331 * These values were chosen to fit within the default signal frame.
1332 * See documentation for /proc/sys/abi/{sve,sme}_default_vector_length,
1333 * and our corresponding cpu property.
1335 cpu
->sve_default_vq
= 4;
1336 cpu
->sme_default_vq
= 2;
1339 /* Our inbound IRQ and FIQ lines */
1340 if (kvm_enabled()) {
1341 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
1342 * the same interface as non-KVM CPUs.
1344 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_kvm_set_irq
, 4);
1346 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_set_irq
, 4);
1349 qdev_init_gpio_out(DEVICE(cpu
), cpu
->gt_timer_outputs
,
1350 ARRAY_SIZE(cpu
->gt_timer_outputs
));
1352 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->gicv3_maintenance_interrupt
,
1353 "gicv3-maintenance-interrupt", 1);
1354 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->pmu_interrupt
,
1355 "pmu-interrupt", 1);
1358 /* DTB consumers generally don't in fact care what the 'compatible'
1359 * string is, so always provide some string and trust that a hypothetical
1360 * picky DTB consumer will also provide a helpful error message.
1362 cpu
->dtb_compatible
= "qemu,unknown";
1363 cpu
->psci_version
= QEMU_PSCI_VERSION_0_1
; /* By default assume PSCI v0.1 */
1364 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_NONE
;
1366 if (tcg_enabled() || hvf_enabled()) {
1367 /* TCG and HVF implement PSCI 1.1 */
1368 cpu
->psci_version
= QEMU_PSCI_VERSION_1_1
;
1372 static Property arm_cpu_gt_cntfrq_property
=
1373 DEFINE_PROP_UINT64("cntfrq", ARMCPU
, gt_cntfrq_hz
,
1374 NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
);
1376 static Property arm_cpu_reset_cbar_property
=
1377 DEFINE_PROP_UINT64("reset-cbar", ARMCPU
, reset_cbar
, 0);
1379 static Property arm_cpu_reset_hivecs_property
=
1380 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU
, reset_hivecs
, false);
1382 #ifndef CONFIG_USER_ONLY
1383 static Property arm_cpu_has_el2_property
=
1384 DEFINE_PROP_BOOL("has_el2", ARMCPU
, has_el2
, true);
1386 static Property arm_cpu_has_el3_property
=
1387 DEFINE_PROP_BOOL("has_el3", ARMCPU
, has_el3
, true);
1390 static Property arm_cpu_cfgend_property
=
1391 DEFINE_PROP_BOOL("cfgend", ARMCPU
, cfgend
, false);
1393 static Property arm_cpu_has_vfp_property
=
1394 DEFINE_PROP_BOOL("vfp", ARMCPU
, has_vfp
, true);
1396 static Property arm_cpu_has_vfp_d32_property
=
1397 DEFINE_PROP_BOOL("vfp-d32", ARMCPU
, has_vfp_d32
, true);
1399 static Property arm_cpu_has_neon_property
=
1400 DEFINE_PROP_BOOL("neon", ARMCPU
, has_neon
, true);
1402 static Property arm_cpu_has_dsp_property
=
1403 DEFINE_PROP_BOOL("dsp", ARMCPU
, has_dsp
, true);
1405 static Property arm_cpu_has_mpu_property
=
1406 DEFINE_PROP_BOOL("has-mpu", ARMCPU
, has_mpu
, true);
1408 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
1409 * because the CPU initfn will have already set cpu->pmsav7_dregion to
1410 * the right value for that particular CPU type, and we don't want
1411 * to override that with an incorrect constant value.
1413 static Property arm_cpu_pmsav7_dregion_property
=
1414 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU
,
1416 qdev_prop_uint32
, uint32_t);
1418 static bool arm_get_pmu(Object
*obj
, Error
**errp
)
1420 ARMCPU
*cpu
= ARM_CPU(obj
);
1422 return cpu
->has_pmu
;
1425 static void arm_set_pmu(Object
*obj
, bool value
, Error
**errp
)
1427 ARMCPU
*cpu
= ARM_CPU(obj
);
1430 if (kvm_enabled() && !kvm_arm_pmu_supported()) {
1431 error_setg(errp
, "'pmu' feature not supported by KVM on this host");
1434 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
1436 unset_feature(&cpu
->env
, ARM_FEATURE_PMU
);
1438 cpu
->has_pmu
= value
;
1441 unsigned int gt_cntfrq_period_ns(ARMCPU
*cpu
)
1444 * The exact approach to calculating guest ticks is:
1446 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz,
1447 * NANOSECONDS_PER_SECOND);
1449 * We don't do that. Rather we intentionally use integer division
1450 * truncation below and in the caller for the conversion of host monotonic
1451 * time to guest ticks to provide the exact inverse for the semantics of
1452 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so
1453 * it loses precision when representing frequencies where
1454 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to
1455 * provide an exact inverse leads to scheduling timers with negative
1456 * periods, which in turn leads to sticky behaviour in the guest.
1458 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor
1459 * cannot become zero.
1461 return NANOSECONDS_PER_SECOND
> cpu
->gt_cntfrq_hz
?
1462 NANOSECONDS_PER_SECOND
/ cpu
->gt_cntfrq_hz
: 1;
1465 static void arm_cpu_propagate_feature_implications(ARMCPU
*cpu
)
1467 CPUARMState
*env
= &cpu
->env
;
1468 bool no_aa32
= false;
1471 * Some features automatically imply others: set the feature
1472 * bits explicitly for these cases.
1475 if (arm_feature(env
, ARM_FEATURE_M
)) {
1476 set_feature(env
, ARM_FEATURE_PMSA
);
1479 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1480 if (arm_feature(env
, ARM_FEATURE_M
)) {
1481 set_feature(env
, ARM_FEATURE_V7
);
1483 set_feature(env
, ARM_FEATURE_V7VE
);
1488 * There exist AArch64 cpus without AArch32 support. When KVM
1489 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
1490 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
1491 * As a general principle, we also do not make ID register
1492 * consistency checks anywhere unless using TCG, because only
1493 * for TCG would a consistency-check failure be a QEMU bug.
1495 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1496 no_aa32
= !cpu_isar_feature(aa64_aa32
, cpu
);
1499 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
1501 * v7 Virtualization Extensions. In real hardware this implies
1502 * EL2 and also the presence of the Security Extensions.
1503 * For QEMU, for backwards-compatibility we implement some
1504 * CPUs or CPU configs which have no actual EL2 or EL3 but do
1505 * include the various other features that V7VE implies.
1506 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
1507 * Security Extensions is ARM_FEATURE_EL3.
1509 assert(!tcg_enabled() || no_aa32
||
1510 cpu_isar_feature(aa32_arm_div
, cpu
));
1511 set_feature(env
, ARM_FEATURE_LPAE
);
1512 set_feature(env
, ARM_FEATURE_V7
);
1514 if (arm_feature(env
, ARM_FEATURE_V7
)) {
1515 set_feature(env
, ARM_FEATURE_VAPA
);
1516 set_feature(env
, ARM_FEATURE_THUMB2
);
1517 set_feature(env
, ARM_FEATURE_MPIDR
);
1518 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1519 set_feature(env
, ARM_FEATURE_V6K
);
1521 set_feature(env
, ARM_FEATURE_V6
);
1525 * Always define VBAR for V7 CPUs even if it doesn't exist in
1526 * non-EL3 configs. This is needed by some legacy boards.
1528 set_feature(env
, ARM_FEATURE_VBAR
);
1530 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
1531 set_feature(env
, ARM_FEATURE_V6
);
1532 set_feature(env
, ARM_FEATURE_MVFR
);
1534 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1535 set_feature(env
, ARM_FEATURE_V5
);
1536 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1537 assert(!tcg_enabled() || no_aa32
||
1538 cpu_isar_feature(aa32_jazelle
, cpu
));
1539 set_feature(env
, ARM_FEATURE_AUXCR
);
1542 if (arm_feature(env
, ARM_FEATURE_V5
)) {
1543 set_feature(env
, ARM_FEATURE_V4T
);
1545 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
1546 set_feature(env
, ARM_FEATURE_V7MP
);
1548 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
1549 set_feature(env
, ARM_FEATURE_CBAR
);
1551 if (arm_feature(env
, ARM_FEATURE_THUMB2
) &&
1552 !arm_feature(env
, ARM_FEATURE_M
)) {
1553 set_feature(env
, ARM_FEATURE_THUMB_DSP
);
1557 void arm_cpu_post_init(Object
*obj
)
1559 ARMCPU
*cpu
= ARM_CPU(obj
);
1562 * Some features imply others. Figure this out now, because we
1563 * are going to look at the feature bits in deciding which
1564 * properties to add.
1566 arm_cpu_propagate_feature_implications(cpu
);
1568 if (arm_feature(&cpu
->env
, ARM_FEATURE_CBAR
) ||
1569 arm_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
)) {
1570 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_cbar_property
);
1573 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1574 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_hivecs_property
);
1577 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1578 object_property_add_uint64_ptr(obj
, "rvbar",
1580 OBJ_PROP_FLAG_READWRITE
);
1583 #ifndef CONFIG_USER_ONLY
1584 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
1585 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
1586 * prevent "has_el3" from existing on CPUs which cannot support EL3.
1588 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el3_property
);
1590 object_property_add_link(obj
, "secure-memory",
1592 (Object
**)&cpu
->secure_memory
,
1593 qdev_prop_allow_set_link_before_realize
,
1594 OBJ_PROP_LINK_STRONG
);
1597 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
)) {
1598 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el2_property
);
1602 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMU
)) {
1603 cpu
->has_pmu
= true;
1604 object_property_add_bool(obj
, "pmu", arm_get_pmu
, arm_set_pmu
);
1608 * Allow user to turn off VFP and Neon support, but only for TCG --
1609 * KVM does not currently allow us to lie to the guest about its
1610 * ID/feature registers, so the guest always sees what the host has.
1612 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1613 if (cpu_isar_feature(aa64_fp_simd
, cpu
)) {
1614 cpu
->has_vfp
= true;
1615 cpu
->has_vfp_d32
= true;
1616 if (tcg_enabled() || qtest_enabled()) {
1617 qdev_property_add_static(DEVICE(obj
),
1618 &arm_cpu_has_vfp_property
);
1621 } else if (cpu_isar_feature(aa32_vfp
, cpu
)) {
1622 cpu
->has_vfp
= true;
1623 if (cpu_isar_feature(aa32_simd_r32
, cpu
)) {
1624 cpu
->has_vfp_d32
= true;
1626 * The permitted values of the SIMDReg bits [3:0] on
1627 * Armv8-A are either 0b0000 and 0b0010. On such CPUs,
1628 * make sure that has_vfp_d32 can not be set to false.
1630 if ((tcg_enabled() || qtest_enabled())
1631 && !(arm_feature(&cpu
->env
, ARM_FEATURE_V8
)
1632 && !arm_feature(&cpu
->env
, ARM_FEATURE_M
))) {
1633 qdev_property_add_static(DEVICE(obj
),
1634 &arm_cpu_has_vfp_d32_property
);
1639 if (arm_feature(&cpu
->env
, ARM_FEATURE_NEON
)) {
1640 cpu
->has_neon
= true;
1641 if (!kvm_enabled()) {
1642 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_neon_property
);
1646 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
) &&
1647 arm_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
)) {
1648 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_dsp_property
);
1651 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMSA
)) {
1652 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_mpu_property
);
1653 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1654 qdev_property_add_static(DEVICE(obj
),
1655 &arm_cpu_pmsav7_dregion_property
);
1659 if (arm_feature(&cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
1660 object_property_add_link(obj
, "idau", TYPE_IDAU_INTERFACE
, &cpu
->idau
,
1661 qdev_prop_allow_set_link_before_realize
,
1662 OBJ_PROP_LINK_STRONG
);
1664 * M profile: initial value of the Secure VTOR. We can't just use
1665 * a simple DEFINE_PROP_UINT32 for this because we want to permit
1666 * the property to be set after realize.
1668 object_property_add_uint32_ptr(obj
, "init-svtor",
1670 OBJ_PROP_FLAG_READWRITE
);
1672 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1674 * Initial value of the NS VTOR (for cores without the Security
1675 * extension, this is the only VTOR)
1677 object_property_add_uint32_ptr(obj
, "init-nsvtor",
1679 OBJ_PROP_FLAG_READWRITE
);
1682 /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */
1683 object_property_add_uint32_ptr(obj
, "psci-conduit",
1685 OBJ_PROP_FLAG_READWRITE
);
1687 qdev_property_add_static(DEVICE(obj
), &arm_cpu_cfgend_property
);
1689 if (arm_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
)) {
1690 qdev_property_add_static(DEVICE(cpu
), &arm_cpu_gt_cntfrq_property
);
1693 if (kvm_enabled()) {
1694 kvm_arm_add_vcpu_properties(cpu
);
1697 #ifndef CONFIG_USER_ONLY
1698 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
) &&
1699 cpu_isar_feature(aa64_mte
, cpu
)) {
1700 object_property_add_link(obj
, "tag-memory",
1702 (Object
**)&cpu
->tag_memory
,
1703 qdev_prop_allow_set_link_before_realize
,
1704 OBJ_PROP_LINK_STRONG
);
1706 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
1707 object_property_add_link(obj
, "secure-tag-memory",
1709 (Object
**)&cpu
->secure_tag_memory
,
1710 qdev_prop_allow_set_link_before_realize
,
1711 OBJ_PROP_LINK_STRONG
);
1717 static void arm_cpu_finalizefn(Object
*obj
)
1719 ARMCPU
*cpu
= ARM_CPU(obj
);
1720 ARMELChangeHook
*hook
, *next
;
1722 g_hash_table_destroy(cpu
->cp_regs
);
1724 QLIST_FOREACH_SAFE(hook
, &cpu
->pre_el_change_hooks
, node
, next
) {
1725 QLIST_REMOVE(hook
, node
);
1728 QLIST_FOREACH_SAFE(hook
, &cpu
->el_change_hooks
, node
, next
) {
1729 QLIST_REMOVE(hook
, node
);
1732 #ifndef CONFIG_USER_ONLY
1733 if (cpu
->pmu_timer
) {
1734 timer_free(cpu
->pmu_timer
);
1739 void arm_cpu_finalize_features(ARMCPU
*cpu
, Error
**errp
)
1741 Error
*local_err
= NULL
;
1743 #ifdef TARGET_AARCH64
1744 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1745 arm_cpu_sve_finalize(cpu
, &local_err
);
1746 if (local_err
!= NULL
) {
1747 error_propagate(errp
, local_err
);
1752 * FEAT_SME is not architecturally dependent on FEAT_SVE (unless
1753 * FEAT_SME_FA64 is present). However our implementation currently
1754 * assumes it, so if the user asked for sve=off then turn off SME also.
1755 * (KVM doesn't currently support SME at all.)
1757 if (cpu_isar_feature(aa64_sme
, cpu
) && !cpu_isar_feature(aa64_sve
, cpu
)) {
1758 object_property_set_bool(OBJECT(cpu
), "sme", false, &error_abort
);
1761 arm_cpu_sme_finalize(cpu
, &local_err
);
1762 if (local_err
!= NULL
) {
1763 error_propagate(errp
, local_err
);
1767 arm_cpu_pauth_finalize(cpu
, &local_err
);
1768 if (local_err
!= NULL
) {
1769 error_propagate(errp
, local_err
);
1773 arm_cpu_lpa2_finalize(cpu
, &local_err
);
1774 if (local_err
!= NULL
) {
1775 error_propagate(errp
, local_err
);
1781 if (kvm_enabled()) {
1782 kvm_arm_steal_time_finalize(cpu
, &local_err
);
1783 if (local_err
!= NULL
) {
1784 error_propagate(errp
, local_err
);
1790 static void arm_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
1792 CPUState
*cs
= CPU(dev
);
1793 ARMCPU
*cpu
= ARM_CPU(dev
);
1794 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(dev
);
1795 CPUARMState
*env
= &cpu
->env
;
1797 Error
*local_err
= NULL
;
1799 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
1800 /* Use pc-relative instructions in system-mode */
1801 cs
->tcg_cflags
|= CF_PCREL
;
1804 /* If we needed to query the host kernel for the CPU features
1805 * then it's possible that might have failed in the initfn, but
1806 * this is the first point where we can report it.
1808 if (cpu
->host_cpu_probe_failed
) {
1809 if (!kvm_enabled() && !hvf_enabled()) {
1810 error_setg(errp
, "The 'host' CPU type can only be used with KVM or HVF");
1812 error_setg(errp
, "Failed to retrieve host CPU features");
1817 #ifndef CONFIG_USER_ONLY
1818 /* The NVIC and M-profile CPU are two halves of a single piece of
1819 * hardware; trying to use one without the other is a command line
1820 * error and will result in segfaults if not caught here.
1822 if (arm_feature(env
, ARM_FEATURE_M
)) {
1824 error_setg(errp
, "This board cannot be used with Cortex-M CPUs");
1829 error_setg(errp
, "This board can only be used with Cortex-M CPUs");
1834 if (!tcg_enabled() && !qtest_enabled()) {
1836 * We assume that no accelerator except TCG (and the "not really an
1837 * accelerator" qtest) can handle these features, because Arm hardware
1838 * virtualization can't virtualize them.
1840 * Catch all the cases which might cause us to create more than one
1841 * address space for the CPU (otherwise we will assert() later in
1842 * cpu_address_space_init()).
1844 if (arm_feature(env
, ARM_FEATURE_M
)) {
1846 "Cannot enable %s when using an M-profile guest CPU",
1847 current_accel_name());
1852 "Cannot enable %s when guest CPU has EL3 enabled",
1853 current_accel_name());
1856 if (cpu
->tag_memory
) {
1858 "Cannot enable %s when guest CPUs has MTE enabled",
1859 current_accel_name());
1867 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
1868 if (!cpu
->gt_cntfrq_hz
) {
1869 error_setg(errp
, "Invalid CNTFRQ: %"PRId64
"Hz",
1873 scale
= gt_cntfrq_period_ns(cpu
);
1875 scale
= GTIMER_SCALE
;
1878 cpu
->gt_timer
[GTIMER_PHYS
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1879 arm_gt_ptimer_cb
, cpu
);
1880 cpu
->gt_timer
[GTIMER_VIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1881 arm_gt_vtimer_cb
, cpu
);
1882 cpu
->gt_timer
[GTIMER_HYP
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1883 arm_gt_htimer_cb
, cpu
);
1884 cpu
->gt_timer
[GTIMER_SEC
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1885 arm_gt_stimer_cb
, cpu
);
1886 cpu
->gt_timer
[GTIMER_HYPVIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1887 arm_gt_hvtimer_cb
, cpu
);
1891 cpu_exec_realizefn(cs
, &local_err
);
1892 if (local_err
!= NULL
) {
1893 error_propagate(errp
, local_err
);
1897 arm_cpu_finalize_features(cpu
, &local_err
);
1898 if (local_err
!= NULL
) {
1899 error_propagate(errp
, local_err
);
1903 #ifdef CONFIG_USER_ONLY
1905 * User mode relies on IC IVAU instructions to catch modification of
1908 * Clear CTR_EL0.DIC to ensure that software that honors these flags uses
1909 * IC IVAU even if the emulated processor does not normally require it.
1911 cpu
->ctr
= FIELD_DP64(cpu
->ctr
, CTR_EL0
, DIC
, 0);
1914 if (arm_feature(env
, ARM_FEATURE_AARCH64
) &&
1915 cpu
->has_vfp
!= cpu
->has_neon
) {
1917 * This is an architectural requirement for AArch64; AArch32 is
1918 * more flexible and permits VFP-no-Neon and Neon-no-VFP.
1921 "AArch64 CPUs must have both VFP and Neon or neither");
1925 if (cpu
->has_vfp_d32
!= cpu
->has_neon
) {
1926 error_setg(errp
, "ARM CPUs must have both VFP-D32 and Neon or neither");
1930 if (!cpu
->has_vfp_d32
) {
1933 u
= cpu
->isar
.mvfr0
;
1934 u
= FIELD_DP32(u
, MVFR0
, SIMDREG
, 1); /* 16 registers */
1935 cpu
->isar
.mvfr0
= u
;
1938 if (!cpu
->has_vfp
) {
1942 t
= cpu
->isar
.id_aa64isar1
;
1943 t
= FIELD_DP64(t
, ID_AA64ISAR1
, JSCVT
, 0);
1944 cpu
->isar
.id_aa64isar1
= t
;
1946 t
= cpu
->isar
.id_aa64pfr0
;
1947 t
= FIELD_DP64(t
, ID_AA64PFR0
, FP
, 0xf);
1948 cpu
->isar
.id_aa64pfr0
= t
;
1950 u
= cpu
->isar
.id_isar6
;
1951 u
= FIELD_DP32(u
, ID_ISAR6
, JSCVT
, 0);
1952 u
= FIELD_DP32(u
, ID_ISAR6
, BF16
, 0);
1953 cpu
->isar
.id_isar6
= u
;
1955 u
= cpu
->isar
.mvfr0
;
1956 u
= FIELD_DP32(u
, MVFR0
, FPSP
, 0);
1957 u
= FIELD_DP32(u
, MVFR0
, FPDP
, 0);
1958 u
= FIELD_DP32(u
, MVFR0
, FPDIVIDE
, 0);
1959 u
= FIELD_DP32(u
, MVFR0
, FPSQRT
, 0);
1960 u
= FIELD_DP32(u
, MVFR0
, FPROUND
, 0);
1961 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1962 u
= FIELD_DP32(u
, MVFR0
, FPTRAP
, 0);
1963 u
= FIELD_DP32(u
, MVFR0
, FPSHVEC
, 0);
1965 cpu
->isar
.mvfr0
= u
;
1967 u
= cpu
->isar
.mvfr1
;
1968 u
= FIELD_DP32(u
, MVFR1
, FPFTZ
, 0);
1969 u
= FIELD_DP32(u
, MVFR1
, FPDNAN
, 0);
1970 u
= FIELD_DP32(u
, MVFR1
, FPHP
, 0);
1971 if (arm_feature(env
, ARM_FEATURE_M
)) {
1972 u
= FIELD_DP32(u
, MVFR1
, FP16
, 0);
1974 cpu
->isar
.mvfr1
= u
;
1976 u
= cpu
->isar
.mvfr2
;
1977 u
= FIELD_DP32(u
, MVFR2
, FPMISC
, 0);
1978 cpu
->isar
.mvfr2
= u
;
1981 if (!cpu
->has_neon
) {
1985 unset_feature(env
, ARM_FEATURE_NEON
);
1987 t
= cpu
->isar
.id_aa64isar0
;
1988 t
= FIELD_DP64(t
, ID_AA64ISAR0
, AES
, 0);
1989 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SHA1
, 0);
1990 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SHA2
, 0);
1991 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SHA3
, 0);
1992 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SM3
, 0);
1993 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SM4
, 0);
1994 t
= FIELD_DP64(t
, ID_AA64ISAR0
, DP
, 0);
1995 cpu
->isar
.id_aa64isar0
= t
;
1997 t
= cpu
->isar
.id_aa64isar1
;
1998 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FCMA
, 0);
1999 t
= FIELD_DP64(t
, ID_AA64ISAR1
, BF16
, 0);
2000 t
= FIELD_DP64(t
, ID_AA64ISAR1
, I8MM
, 0);
2001 cpu
->isar
.id_aa64isar1
= t
;
2003 t
= cpu
->isar
.id_aa64pfr0
;
2004 t
= FIELD_DP64(t
, ID_AA64PFR0
, ADVSIMD
, 0xf);
2005 cpu
->isar
.id_aa64pfr0
= t
;
2007 u
= cpu
->isar
.id_isar5
;
2008 u
= FIELD_DP32(u
, ID_ISAR5
, AES
, 0);
2009 u
= FIELD_DP32(u
, ID_ISAR5
, SHA1
, 0);
2010 u
= FIELD_DP32(u
, ID_ISAR5
, SHA2
, 0);
2011 u
= FIELD_DP32(u
, ID_ISAR5
, RDM
, 0);
2012 u
= FIELD_DP32(u
, ID_ISAR5
, VCMA
, 0);
2013 cpu
->isar
.id_isar5
= u
;
2015 u
= cpu
->isar
.id_isar6
;
2016 u
= FIELD_DP32(u
, ID_ISAR6
, DP
, 0);
2017 u
= FIELD_DP32(u
, ID_ISAR6
, FHM
, 0);
2018 u
= FIELD_DP32(u
, ID_ISAR6
, BF16
, 0);
2019 u
= FIELD_DP32(u
, ID_ISAR6
, I8MM
, 0);
2020 cpu
->isar
.id_isar6
= u
;
2022 if (!arm_feature(env
, ARM_FEATURE_M
)) {
2023 u
= cpu
->isar
.mvfr1
;
2024 u
= FIELD_DP32(u
, MVFR1
, SIMDLS
, 0);
2025 u
= FIELD_DP32(u
, MVFR1
, SIMDINT
, 0);
2026 u
= FIELD_DP32(u
, MVFR1
, SIMDSP
, 0);
2027 u
= FIELD_DP32(u
, MVFR1
, SIMDHP
, 0);
2028 cpu
->isar
.mvfr1
= u
;
2030 u
= cpu
->isar
.mvfr2
;
2031 u
= FIELD_DP32(u
, MVFR2
, SIMDMISC
, 0);
2032 cpu
->isar
.mvfr2
= u
;
2036 if (!cpu
->has_neon
&& !cpu
->has_vfp
) {
2040 t
= cpu
->isar
.id_aa64isar0
;
2041 t
= FIELD_DP64(t
, ID_AA64ISAR0
, FHM
, 0);
2042 cpu
->isar
.id_aa64isar0
= t
;
2044 t
= cpu
->isar
.id_aa64isar1
;
2045 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FRINTTS
, 0);
2046 cpu
->isar
.id_aa64isar1
= t
;
2048 u
= cpu
->isar
.mvfr0
;
2049 u
= FIELD_DP32(u
, MVFR0
, SIMDREG
, 0);
2050 cpu
->isar
.mvfr0
= u
;
2052 /* Despite the name, this field covers both VFP and Neon */
2053 u
= cpu
->isar
.mvfr1
;
2054 u
= FIELD_DP32(u
, MVFR1
, SIMDFMAC
, 0);
2055 cpu
->isar
.mvfr1
= u
;
2058 if (arm_feature(env
, ARM_FEATURE_M
) && !cpu
->has_dsp
) {
2061 unset_feature(env
, ARM_FEATURE_THUMB_DSP
);
2063 u
= cpu
->isar
.id_isar1
;
2064 u
= FIELD_DP32(u
, ID_ISAR1
, EXTEND
, 1);
2065 cpu
->isar
.id_isar1
= u
;
2067 u
= cpu
->isar
.id_isar2
;
2068 u
= FIELD_DP32(u
, ID_ISAR2
, MULTU
, 1);
2069 u
= FIELD_DP32(u
, ID_ISAR2
, MULTS
, 1);
2070 cpu
->isar
.id_isar2
= u
;
2072 u
= cpu
->isar
.id_isar3
;
2073 u
= FIELD_DP32(u
, ID_ISAR3
, SIMD
, 1);
2074 u
= FIELD_DP32(u
, ID_ISAR3
, SATURATE
, 0);
2075 cpu
->isar
.id_isar3
= u
;
2080 * We rely on no XScale CPU having VFP so we can use the same bits in the
2081 * TB flags field for VECSTRIDE and XSCALE_CPAR.
2083 assert(arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
) ||
2084 !cpu_isar_feature(aa32_vfp_simd
, cpu
) ||
2085 !arm_feature(env
, ARM_FEATURE_XSCALE
));
2087 if (arm_feature(env
, ARM_FEATURE_V7
) &&
2088 !arm_feature(env
, ARM_FEATURE_M
) &&
2089 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
2090 /* v7VMSA drops support for the old ARMv5 tiny pages, so we
2095 /* For CPUs which might have tiny 1K pages, or which have an
2096 * MPU and might have small region sizes, stick with 1K pages.
2100 if (!set_preferred_target_page_bits(pagebits
)) {
2101 /* This can only ever happen for hotplugging a CPU, or if
2102 * the board code incorrectly creates a CPU which it has
2103 * promised via minimum_page_size that it will not.
2105 error_setg(errp
, "This CPU requires a smaller page size than the "
2110 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
2111 * We don't support setting cluster ID ([16..23]) (known as Aff2
2112 * in later ARM ARM versions), or any of the higher affinity level fields,
2113 * so these bits always RAZ.
2115 if (cpu
->mp_affinity
== ARM64_AFFINITY_INVALID
) {
2116 cpu
->mp_affinity
= arm_cpu_mp_affinity(cs
->cpu_index
,
2117 ARM_DEFAULT_CPUS_PER_CLUSTER
);
2120 if (cpu
->reset_hivecs
) {
2121 cpu
->reset_sctlr
|= (1 << 13);
2125 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
2126 cpu
->reset_sctlr
|= SCTLR_EE
;
2128 cpu
->reset_sctlr
|= SCTLR_B
;
2132 if (!arm_feature(env
, ARM_FEATURE_M
) && !cpu
->has_el3
) {
2133 /* If the has_el3 CPU property is disabled then we need to disable the
2136 unset_feature(env
, ARM_FEATURE_EL3
);
2139 * Disable the security extension feature bits in the processor
2140 * feature registers as well.
2142 cpu
->isar
.id_pfr1
= FIELD_DP32(cpu
->isar
.id_pfr1
, ID_PFR1
, SECURITY
, 0);
2143 cpu
->isar
.id_dfr0
= FIELD_DP32(cpu
->isar
.id_dfr0
, ID_DFR0
, COPSDBG
, 0);
2144 cpu
->isar
.id_aa64pfr0
= FIELD_DP64(cpu
->isar
.id_aa64pfr0
,
2145 ID_AA64PFR0
, EL3
, 0);
2147 /* Disable the realm management extension, which requires EL3. */
2148 cpu
->isar
.id_aa64pfr0
= FIELD_DP64(cpu
->isar
.id_aa64pfr0
,
2149 ID_AA64PFR0
, RME
, 0);
2152 if (!cpu
->has_el2
) {
2153 unset_feature(env
, ARM_FEATURE_EL2
);
2156 if (!cpu
->has_pmu
) {
2157 unset_feature(env
, ARM_FEATURE_PMU
);
2159 if (arm_feature(env
, ARM_FEATURE_PMU
)) {
2162 if (!kvm_enabled()) {
2163 arm_register_pre_el_change_hook(cpu
, &pmu_pre_el_change
, 0);
2164 arm_register_el_change_hook(cpu
, &pmu_post_el_change
, 0);
2167 #ifndef CONFIG_USER_ONLY
2168 cpu
->pmu_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, arm_pmu_timer_cb
,
2172 cpu
->isar
.id_aa64dfr0
=
2173 FIELD_DP64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, PMUVER
, 0);
2174 cpu
->isar
.id_dfr0
= FIELD_DP32(cpu
->isar
.id_dfr0
, ID_DFR0
, PERFMON
, 0);
2179 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
2181 * Disable the hypervisor feature bits in the processor feature
2182 * registers if we don't have EL2.
2184 cpu
->isar
.id_aa64pfr0
= FIELD_DP64(cpu
->isar
.id_aa64pfr0
,
2185 ID_AA64PFR0
, EL2
, 0);
2186 cpu
->isar
.id_pfr1
= FIELD_DP32(cpu
->isar
.id_pfr1
,
2187 ID_PFR1
, VIRTUALIZATION
, 0);
2190 if (cpu_isar_feature(aa64_mte
, cpu
)) {
2192 * The architectural range of GM blocksize is 2-6, however qemu
2193 * doesn't support blocksize of 2 (see HELPER(ldgm)).
2195 if (tcg_enabled()) {
2196 assert(cpu
->gm_blocksize
>= 3 && cpu
->gm_blocksize
<= 6);
2199 #ifndef CONFIG_USER_ONLY
2201 * If we do not have tag-memory provided by the machine,
2202 * reduce MTE support to instructions enabled at EL0.
2203 * This matches Cortex-A710 BROADCASTMTE input being LOW.
2205 if (cpu
->tag_memory
== NULL
) {
2206 cpu
->isar
.id_aa64pfr1
=
2207 FIELD_DP64(cpu
->isar
.id_aa64pfr1
, ID_AA64PFR1
, MTE
, 1);
2212 if (tcg_enabled()) {
2214 * Don't report some architectural features in the ID registers
2215 * where TCG does not yet implement it (not even a minimal
2216 * stub version). This avoids guests falling over when they
2217 * try to access the non-existent system registers for them.
2219 /* FEAT_SPE (Statistical Profiling Extension) */
2220 cpu
->isar
.id_aa64dfr0
=
2221 FIELD_DP64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, PMSVER
, 0);
2222 /* FEAT_TRBE (Trace Buffer Extension) */
2223 cpu
->isar
.id_aa64dfr0
=
2224 FIELD_DP64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, TRACEBUFFER
, 0);
2225 /* FEAT_TRF (Self-hosted Trace Extension) */
2226 cpu
->isar
.id_aa64dfr0
=
2227 FIELD_DP64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, TRACEFILT
, 0);
2229 FIELD_DP32(cpu
->isar
.id_dfr0
, ID_DFR0
, TRACEFILT
, 0);
2230 /* Trace Macrocell system register access */
2231 cpu
->isar
.id_aa64dfr0
=
2232 FIELD_DP64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, TRACEVER
, 0);
2234 FIELD_DP32(cpu
->isar
.id_dfr0
, ID_DFR0
, COPTRC
, 0);
2235 /* Memory mapped trace */
2237 FIELD_DP32(cpu
->isar
.id_dfr0
, ID_DFR0
, MMAPTRC
, 0);
2238 /* FEAT_AMU (Activity Monitors Extension) */
2239 cpu
->isar
.id_aa64pfr0
=
2240 FIELD_DP64(cpu
->isar
.id_aa64pfr0
, ID_AA64PFR0
, AMU
, 0);
2242 FIELD_DP32(cpu
->isar
.id_pfr0
, ID_PFR0
, AMU
, 0);
2243 /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */
2244 cpu
->isar
.id_aa64pfr0
=
2245 FIELD_DP64(cpu
->isar
.id_aa64pfr0
, ID_AA64PFR0
, MPAM
, 0);
2248 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
2249 * to false or by setting pmsav7-dregion to 0.
2251 if (!cpu
->has_mpu
|| cpu
->pmsav7_dregion
== 0) {
2252 cpu
->has_mpu
= false;
2253 cpu
->pmsav7_dregion
= 0;
2254 cpu
->pmsav8r_hdregion
= 0;
2257 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
2258 arm_feature(env
, ARM_FEATURE_V7
)) {
2259 uint32_t nr
= cpu
->pmsav7_dregion
;
2262 error_setg(errp
, "PMSAv7 MPU #regions invalid %" PRIu32
, nr
);
2267 if (arm_feature(env
, ARM_FEATURE_V8
)) {
2269 env
->pmsav8
.rbar
[M_REG_NS
] = g_new0(uint32_t, nr
);
2270 env
->pmsav8
.rlar
[M_REG_NS
] = g_new0(uint32_t, nr
);
2271 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
2272 env
->pmsav8
.rbar
[M_REG_S
] = g_new0(uint32_t, nr
);
2273 env
->pmsav8
.rlar
[M_REG_S
] = g_new0(uint32_t, nr
);
2276 env
->pmsav7
.drbar
= g_new0(uint32_t, nr
);
2277 env
->pmsav7
.drsr
= g_new0(uint32_t, nr
);
2278 env
->pmsav7
.dracr
= g_new0(uint32_t, nr
);
2282 if (cpu
->pmsav8r_hdregion
> 0xff) {
2283 error_setg(errp
, "PMSAv8 MPU EL2 #regions invalid %" PRIu32
,
2284 cpu
->pmsav8r_hdregion
);
2288 if (cpu
->pmsav8r_hdregion
) {
2289 env
->pmsav8
.hprbar
= g_new0(uint32_t,
2290 cpu
->pmsav8r_hdregion
);
2291 env
->pmsav8
.hprlar
= g_new0(uint32_t,
2292 cpu
->pmsav8r_hdregion
);
2296 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
2297 uint32_t nr
= cpu
->sau_sregion
;
2300 error_setg(errp
, "v8M SAU #regions invalid %" PRIu32
, nr
);
2305 env
->sau
.rbar
= g_new0(uint32_t, nr
);
2306 env
->sau
.rlar
= g_new0(uint32_t, nr
);
2310 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
2311 set_feature(env
, ARM_FEATURE_VBAR
);
2314 #ifndef CONFIG_USER_ONLY
2315 if (tcg_enabled() && cpu_isar_feature(aa64_rme
, cpu
)) {
2316 arm_register_el_change_hook(cpu
, >_rme_post_el_change
, 0);
2320 register_cp_regs_for_features(cpu
);
2321 arm_cpu_register_gdb_regs_for_features(cpu
);
2323 init_cpreg_list(cpu
);
2325 #ifndef CONFIG_USER_ONLY
2326 MachineState
*ms
= MACHINE(qdev_get_machine());
2327 unsigned int smp_cpus
= ms
->smp
.cpus
;
2328 bool has_secure
= cpu
->has_el3
|| arm_feature(env
, ARM_FEATURE_M_SECURITY
);
2331 * We must set cs->num_ases to the final value before
2332 * the first call to cpu_address_space_init.
2334 if (cpu
->tag_memory
!= NULL
) {
2335 cs
->num_ases
= 3 + has_secure
;
2337 cs
->num_ases
= 1 + has_secure
;
2341 if (!cpu
->secure_memory
) {
2342 cpu
->secure_memory
= cs
->memory
;
2344 cpu_address_space_init(cs
, ARMASIdx_S
, "cpu-secure-memory",
2345 cpu
->secure_memory
);
2348 if (cpu
->tag_memory
!= NULL
) {
2349 cpu_address_space_init(cs
, ARMASIdx_TagNS
, "cpu-tag-memory",
2352 cpu_address_space_init(cs
, ARMASIdx_TagS
, "cpu-tag-memory",
2353 cpu
->secure_tag_memory
);
2357 cpu_address_space_init(cs
, ARMASIdx_NS
, "cpu-memory", cs
->memory
);
2359 /* No core_count specified, default to smp_cpus. */
2360 if (cpu
->core_count
== -1) {
2361 cpu
->core_count
= smp_cpus
;
2365 if (tcg_enabled()) {
2366 int dcz_blocklen
= 4 << cpu
->dcz_blocksize
;
2369 * We only support DCZ blocklen that fits on one page.
2371 * Architectually this is always true. However TARGET_PAGE_SIZE
2372 * is variable and, for compatibility with -machine virt-2.7,
2373 * is only 1KiB, as an artifact of legacy ARMv5 subpage support.
2374 * But even then, while the largest architectural DCZ blocklen
2375 * is 2KiB, no cpu actually uses such a large blocklen.
2377 assert(dcz_blocklen
<= TARGET_PAGE_SIZE
);
2380 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say
2381 * both nibbles of each byte storing tag data may be written at once.
2382 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32.
2384 if (cpu_isar_feature(aa64_mte
, cpu
)) {
2385 assert(dcz_blocklen
>= 2 * TAG_GRANULE
);
2392 acc
->parent_realize(dev
, errp
);
2395 static ObjectClass
*arm_cpu_class_by_name(const char *cpu_model
)
2400 const char *cpunamestr
;
2402 cpuname
= g_strsplit(cpu_model
, ",", 1);
2403 cpunamestr
= cpuname
[0];
2404 #ifdef CONFIG_USER_ONLY
2405 /* For backwards compatibility usermode emulation allows "-cpu any",
2406 * which has the same semantics as "-cpu max".
2408 if (!strcmp(cpunamestr
, "any")) {
2412 typename
= g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr
);
2413 oc
= object_class_by_name(typename
);
2414 g_strfreev(cpuname
);
2420 static Property arm_cpu_properties
[] = {
2421 DEFINE_PROP_UINT64("midr", ARMCPU
, midr
, 0),
2422 DEFINE_PROP_UINT64("mp-affinity", ARMCPU
,
2423 mp_affinity
, ARM64_AFFINITY_INVALID
),
2424 DEFINE_PROP_INT32("node-id", ARMCPU
, node_id
, CPU_UNSET_NUMA_NODE_ID
),
2425 DEFINE_PROP_INT32("core-count", ARMCPU
, core_count
, -1),
2426 DEFINE_PROP_END_OF_LIST()
2429 static const gchar
*arm_gdb_arch_name(CPUState
*cs
)
2431 ARMCPU
*cpu
= ARM_CPU(cs
);
2432 CPUARMState
*env
= &cpu
->env
;
2434 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
2440 #ifndef CONFIG_USER_ONLY
2441 #include "hw/core/sysemu-cpu-ops.h"
2443 static const struct SysemuCPUOps arm_sysemu_ops
= {
2444 .get_phys_page_attrs_debug
= arm_cpu_get_phys_page_attrs_debug
,
2445 .asidx_from_attrs
= arm_asidx_from_attrs
,
2446 .write_elf32_note
= arm_cpu_write_elf32_note
,
2447 .write_elf64_note
= arm_cpu_write_elf64_note
,
2448 .virtio_is_big_endian
= arm_cpu_virtio_is_big_endian
,
2449 .legacy_vmsd
= &vmstate_arm_cpu
,
2454 static const struct TCGCPUOps arm_tcg_ops
= {
2455 .initialize
= arm_translate_init
,
2456 .synchronize_from_tb
= arm_cpu_synchronize_from_tb
,
2457 .debug_excp_handler
= arm_debug_excp_handler
,
2458 .restore_state_to_opc
= arm_restore_state_to_opc
,
2460 #ifdef CONFIG_USER_ONLY
2461 .record_sigsegv
= arm_cpu_record_sigsegv
,
2462 .record_sigbus
= arm_cpu_record_sigbus
,
2464 .tlb_fill
= arm_cpu_tlb_fill
,
2465 .cpu_exec_interrupt
= arm_cpu_exec_interrupt
,
2466 .do_interrupt
= arm_cpu_do_interrupt
,
2467 .do_transaction_failed
= arm_cpu_do_transaction_failed
,
2468 .do_unaligned_access
= arm_cpu_do_unaligned_access
,
2469 .adjust_watchpoint_address
= arm_adjust_watchpoint_address
,
2470 .debug_check_watchpoint
= arm_debug_check_watchpoint
,
2471 .debug_check_breakpoint
= arm_debug_check_breakpoint
,
2472 #endif /* !CONFIG_USER_ONLY */
2474 #endif /* CONFIG_TCG */
2476 static void arm_cpu_class_init(ObjectClass
*oc
, void *data
)
2478 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2479 CPUClass
*cc
= CPU_CLASS(acc
);
2480 DeviceClass
*dc
= DEVICE_CLASS(oc
);
2481 ResettableClass
*rc
= RESETTABLE_CLASS(oc
);
2483 device_class_set_parent_realize(dc
, arm_cpu_realizefn
,
2484 &acc
->parent_realize
);
2486 device_class_set_props(dc
, arm_cpu_properties
);
2488 resettable_class_set_parent_phases(rc
, NULL
, arm_cpu_reset_hold
, NULL
,
2489 &acc
->parent_phases
);
2491 cc
->class_by_name
= arm_cpu_class_by_name
;
2492 cc
->has_work
= arm_cpu_has_work
;
2493 cc
->dump_state
= arm_cpu_dump_state
;
2494 cc
->set_pc
= arm_cpu_set_pc
;
2495 cc
->get_pc
= arm_cpu_get_pc
;
2496 cc
->gdb_read_register
= arm_cpu_gdb_read_register
;
2497 cc
->gdb_write_register
= arm_cpu_gdb_write_register
;
2498 #ifndef CONFIG_USER_ONLY
2499 cc
->sysemu_ops
= &arm_sysemu_ops
;
2501 cc
->gdb_num_core_regs
= 26;
2502 cc
->gdb_arch_name
= arm_gdb_arch_name
;
2503 cc
->gdb_get_dynamic_xml
= arm_gdb_get_dynamic_xml
;
2504 cc
->gdb_stop_before_watchpoint
= true;
2505 cc
->disas_set_info
= arm_disas_set_info
;
2508 cc
->tcg_ops
= &arm_tcg_ops
;
2509 #endif /* CONFIG_TCG */
2512 static void arm_cpu_instance_init(Object
*obj
)
2514 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(obj
);
2516 acc
->info
->initfn(obj
);
2517 arm_cpu_post_init(obj
);
2520 static void cpu_register_class_init(ObjectClass
*oc
, void *data
)
2522 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2523 CPUClass
*cc
= CPU_CLASS(acc
);
2526 cc
->gdb_core_xml_file
= "arm-core.xml";
2529 void arm_cpu_register(const ARMCPUInfo
*info
)
2531 TypeInfo type_info
= {
2532 .parent
= TYPE_ARM_CPU
,
2533 .instance_init
= arm_cpu_instance_init
,
2534 .class_init
= info
->class_init
?: cpu_register_class_init
,
2535 .class_data
= (void *)info
,
2538 type_info
.name
= g_strdup_printf("%s-" TYPE_ARM_CPU
, info
->name
);
2539 type_register(&type_info
);
2540 g_free((void *)type_info
.name
);
2543 static const TypeInfo arm_cpu_type_info
= {
2544 .name
= TYPE_ARM_CPU
,
2546 .instance_size
= sizeof(ARMCPU
),
2547 .instance_align
= __alignof__(ARMCPU
),
2548 .instance_init
= arm_cpu_initfn
,
2549 .instance_finalize
= arm_cpu_finalizefn
,
2551 .class_size
= sizeof(ARMCPUClass
),
2552 .class_init
= arm_cpu_class_init
,
2555 static void arm_cpu_register_types(void)
2557 type_register_static(&arm_cpu_type_info
);
2560 type_init(arm_cpu_register_types
)