2 * AArch64 specific helpers
4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "exec/gdbstub.h"
23 #include "exec/helper-proto.h"
24 #include "qemu/host-utils.h"
26 #include "sysemu/sysemu.h"
27 #include "qemu/bitops.h"
28 #include "internals.h"
29 #include "qemu/crc32c.h"
30 #include "exec/exec-all.h"
31 #include "exec/cpu_ldst.h"
32 #include "qemu/int128.h"
34 #include "fpu/softfloat.h"
35 #include <zlib.h> /* For crc32 */
37 /* C2.4.7 Multiply and divide */
38 /* special cases for 0 and LLONG_MIN are mandated by the standard */
39 uint64_t HELPER(udiv64
)(uint64_t num
, uint64_t den
)
47 int64_t HELPER(sdiv64
)(int64_t num
, int64_t den
)
52 if (num
== LLONG_MIN
&& den
== -1) {
58 uint64_t HELPER(rbit64
)(uint64_t x
)
63 /* Convert a softfloat float_relation_ (as returned by
64 * the float*_compare functions) to the correct ARM
67 static inline uint32_t float_rel_to_flags(int res
)
71 case float_relation_equal
:
72 flags
= PSTATE_Z
| PSTATE_C
;
74 case float_relation_less
:
77 case float_relation_greater
:
80 case float_relation_unordered
:
82 flags
= PSTATE_C
| PSTATE_V
;
88 uint64_t HELPER(vfp_cmph_a64
)(float16 x
, float16 y
, void *fp_status
)
90 return float_rel_to_flags(float16_compare_quiet(x
, y
, fp_status
));
93 uint64_t HELPER(vfp_cmpeh_a64
)(float16 x
, float16 y
, void *fp_status
)
95 return float_rel_to_flags(float16_compare(x
, y
, fp_status
));
98 uint64_t HELPER(vfp_cmps_a64
)(float32 x
, float32 y
, void *fp_status
)
100 return float_rel_to_flags(float32_compare_quiet(x
, y
, fp_status
));
103 uint64_t HELPER(vfp_cmpes_a64
)(float32 x
, float32 y
, void *fp_status
)
105 return float_rel_to_flags(float32_compare(x
, y
, fp_status
));
108 uint64_t HELPER(vfp_cmpd_a64
)(float64 x
, float64 y
, void *fp_status
)
110 return float_rel_to_flags(float64_compare_quiet(x
, y
, fp_status
));
113 uint64_t HELPER(vfp_cmped_a64
)(float64 x
, float64 y
, void *fp_status
)
115 return float_rel_to_flags(float64_compare(x
, y
, fp_status
));
118 float32
HELPER(vfp_mulxs
)(float32 a
, float32 b
, void *fpstp
)
120 float_status
*fpst
= fpstp
;
122 a
= float32_squash_input_denormal(a
, fpst
);
123 b
= float32_squash_input_denormal(b
, fpst
);
125 if ((float32_is_zero(a
) && float32_is_infinity(b
)) ||
126 (float32_is_infinity(a
) && float32_is_zero(b
))) {
127 /* 2.0 with the sign bit set to sign(A) XOR sign(B) */
128 return make_float32((1U << 30) |
129 ((float32_val(a
) ^ float32_val(b
)) & (1U << 31)));
131 return float32_mul(a
, b
, fpst
);
134 float64
HELPER(vfp_mulxd
)(float64 a
, float64 b
, void *fpstp
)
136 float_status
*fpst
= fpstp
;
138 a
= float64_squash_input_denormal(a
, fpst
);
139 b
= float64_squash_input_denormal(b
, fpst
);
141 if ((float64_is_zero(a
) && float64_is_infinity(b
)) ||
142 (float64_is_infinity(a
) && float64_is_zero(b
))) {
143 /* 2.0 with the sign bit set to sign(A) XOR sign(B) */
144 return make_float64((1ULL << 62) |
145 ((float64_val(a
) ^ float64_val(b
)) & (1ULL << 63)));
147 return float64_mul(a
, b
, fpst
);
150 uint64_t HELPER(simd_tbl
)(CPUARMState
*env
, uint64_t result
, uint64_t indices
,
151 uint32_t rn
, uint32_t numregs
)
153 /* Helper function for SIMD TBL and TBX. We have to do the table
154 * lookup part for the 64 bits worth of indices we're passed in.
155 * result is the initial results vector (either zeroes for TBL
156 * or some guest values for TBX), rn the register number where
157 * the table starts, and numregs the number of registers in the table.
158 * We return the results of the lookups.
162 for (shift
= 0; shift
< 64; shift
+= 8) {
163 int index
= extract64(indices
, shift
, 8);
164 if (index
< 16 * numregs
) {
165 /* Convert index (a byte offset into the virtual table
166 * which is a series of 128-bit vectors concatenated)
167 * into the correct register element plus a bit offset
168 * into that element, bearing in mind that the table
169 * can wrap around from V31 to V0.
171 int elt
= (rn
* 2 + (index
>> 3)) % 64;
172 int bitidx
= (index
& 7) * 8;
173 uint64_t *q
= aa64_vfp_qreg(env
, elt
>> 1);
174 uint64_t val
= extract64(q
[elt
& 1], bitidx
, 8);
176 result
= deposit64(result
, shift
, 8, val
);
182 /* 64bit/double versions of the neon float compare functions */
183 uint64_t HELPER(neon_ceq_f64
)(float64 a
, float64 b
, void *fpstp
)
185 float_status
*fpst
= fpstp
;
186 return -float64_eq_quiet(a
, b
, fpst
);
189 uint64_t HELPER(neon_cge_f64
)(float64 a
, float64 b
, void *fpstp
)
191 float_status
*fpst
= fpstp
;
192 return -float64_le(b
, a
, fpst
);
195 uint64_t HELPER(neon_cgt_f64
)(float64 a
, float64 b
, void *fpstp
)
197 float_status
*fpst
= fpstp
;
198 return -float64_lt(b
, a
, fpst
);
201 /* Reciprocal step and sqrt step. Note that unlike the A32/T32
202 * versions, these do a fully fused multiply-add or
203 * multiply-add-and-halve.
205 #define float16_two make_float16(0x4000)
206 #define float16_three make_float16(0x4200)
207 #define float16_one_point_five make_float16(0x3e00)
209 #define float32_two make_float32(0x40000000)
210 #define float32_three make_float32(0x40400000)
211 #define float32_one_point_five make_float32(0x3fc00000)
213 #define float64_two make_float64(0x4000000000000000ULL)
214 #define float64_three make_float64(0x4008000000000000ULL)
215 #define float64_one_point_five make_float64(0x3FF8000000000000ULL)
217 float16
HELPER(recpsf_f16
)(float16 a
, float16 b
, void *fpstp
)
219 float_status
*fpst
= fpstp
;
221 a
= float16_squash_input_denormal(a
, fpst
);
222 b
= float16_squash_input_denormal(b
, fpst
);
225 if ((float16_is_infinity(a
) && float16_is_zero(b
)) ||
226 (float16_is_infinity(b
) && float16_is_zero(a
))) {
229 return float16_muladd(a
, b
, float16_two
, 0, fpst
);
232 float32
HELPER(recpsf_f32
)(float32 a
, float32 b
, void *fpstp
)
234 float_status
*fpst
= fpstp
;
236 a
= float32_squash_input_denormal(a
, fpst
);
237 b
= float32_squash_input_denormal(b
, fpst
);
240 if ((float32_is_infinity(a
) && float32_is_zero(b
)) ||
241 (float32_is_infinity(b
) && float32_is_zero(a
))) {
244 return float32_muladd(a
, b
, float32_two
, 0, fpst
);
247 float64
HELPER(recpsf_f64
)(float64 a
, float64 b
, void *fpstp
)
249 float_status
*fpst
= fpstp
;
251 a
= float64_squash_input_denormal(a
, fpst
);
252 b
= float64_squash_input_denormal(b
, fpst
);
255 if ((float64_is_infinity(a
) && float64_is_zero(b
)) ||
256 (float64_is_infinity(b
) && float64_is_zero(a
))) {
259 return float64_muladd(a
, b
, float64_two
, 0, fpst
);
262 float16
HELPER(rsqrtsf_f16
)(float16 a
, float16 b
, void *fpstp
)
264 float_status
*fpst
= fpstp
;
266 a
= float16_squash_input_denormal(a
, fpst
);
267 b
= float16_squash_input_denormal(b
, fpst
);
270 if ((float16_is_infinity(a
) && float16_is_zero(b
)) ||
271 (float16_is_infinity(b
) && float16_is_zero(a
))) {
272 return float16_one_point_five
;
274 return float16_muladd(a
, b
, float16_three
, float_muladd_halve_result
, fpst
);
277 float32
HELPER(rsqrtsf_f32
)(float32 a
, float32 b
, void *fpstp
)
279 float_status
*fpst
= fpstp
;
281 a
= float32_squash_input_denormal(a
, fpst
);
282 b
= float32_squash_input_denormal(b
, fpst
);
285 if ((float32_is_infinity(a
) && float32_is_zero(b
)) ||
286 (float32_is_infinity(b
) && float32_is_zero(a
))) {
287 return float32_one_point_five
;
289 return float32_muladd(a
, b
, float32_three
, float_muladd_halve_result
, fpst
);
292 float64
HELPER(rsqrtsf_f64
)(float64 a
, float64 b
, void *fpstp
)
294 float_status
*fpst
= fpstp
;
296 a
= float64_squash_input_denormal(a
, fpst
);
297 b
= float64_squash_input_denormal(b
, fpst
);
300 if ((float64_is_infinity(a
) && float64_is_zero(b
)) ||
301 (float64_is_infinity(b
) && float64_is_zero(a
))) {
302 return float64_one_point_five
;
304 return float64_muladd(a
, b
, float64_three
, float_muladd_halve_result
, fpst
);
307 /* Pairwise long add: add pairs of adjacent elements into
308 * double-width elements in the result (eg _s8 is an 8x8->16 op)
310 uint64_t HELPER(neon_addlp_s8
)(uint64_t a
)
312 uint64_t nsignmask
= 0x0080008000800080ULL
;
313 uint64_t wsignmask
= 0x8000800080008000ULL
;
314 uint64_t elementmask
= 0x00ff00ff00ff00ffULL
;
316 uint64_t res
, signres
;
318 /* Extract odd elements, sign extend each to a 16 bit field */
319 tmp1
= a
& elementmask
;
322 tmp1
= (tmp1
- nsignmask
) ^ wsignmask
;
323 /* Ditto for the even elements */
324 tmp2
= (a
>> 8) & elementmask
;
327 tmp2
= (tmp2
- nsignmask
) ^ wsignmask
;
329 /* calculate the result by summing bits 0..14, 16..22, etc,
330 * and then adjusting the sign bits 15, 23, etc manually.
331 * This ensures the addition can't overflow the 16 bit field.
333 signres
= (tmp1
^ tmp2
) & wsignmask
;
334 res
= (tmp1
& ~wsignmask
) + (tmp2
& ~wsignmask
);
340 uint64_t HELPER(neon_addlp_u8
)(uint64_t a
)
344 tmp
= a
& 0x00ff00ff00ff00ffULL
;
345 tmp
+= (a
>> 8) & 0x00ff00ff00ff00ffULL
;
349 uint64_t HELPER(neon_addlp_s16
)(uint64_t a
)
351 int32_t reslo
, reshi
;
353 reslo
= (int32_t)(int16_t)a
+ (int32_t)(int16_t)(a
>> 16);
354 reshi
= (int32_t)(int16_t)(a
>> 32) + (int32_t)(int16_t)(a
>> 48);
356 return (uint32_t)reslo
| (((uint64_t)reshi
) << 32);
359 uint64_t HELPER(neon_addlp_u16
)(uint64_t a
)
363 tmp
= a
& 0x0000ffff0000ffffULL
;
364 tmp
+= (a
>> 16) & 0x0000ffff0000ffffULL
;
368 /* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
369 float16
HELPER(frecpx_f16
)(float16 a
, void *fpstp
)
371 float_status
*fpst
= fpstp
;
372 uint16_t val16
, sbit
;
375 if (float16_is_any_nan(a
)) {
377 if (float16_is_signaling_nan(a
, fpst
)) {
378 float_raise(float_flag_invalid
, fpst
);
379 nan
= float16_maybe_silence_nan(a
, fpst
);
381 if (fpst
->default_nan_mode
) {
382 nan
= float16_default_nan(fpst
);
387 val16
= float16_val(a
);
388 sbit
= 0x8000 & val16
;
389 exp
= extract32(val16
, 10, 5);
392 return make_float16(deposit32(sbit
, 10, 5, 0x1e));
394 return make_float16(deposit32(sbit
, 10, 5, ~exp
));
398 float32
HELPER(frecpx_f32
)(float32 a
, void *fpstp
)
400 float_status
*fpst
= fpstp
;
401 uint32_t val32
, sbit
;
404 if (float32_is_any_nan(a
)) {
406 if (float32_is_signaling_nan(a
, fpst
)) {
407 float_raise(float_flag_invalid
, fpst
);
408 nan
= float32_maybe_silence_nan(a
, fpst
);
410 if (fpst
->default_nan_mode
) {
411 nan
= float32_default_nan(fpst
);
416 val32
= float32_val(a
);
417 sbit
= 0x80000000ULL
& val32
;
418 exp
= extract32(val32
, 23, 8);
421 return make_float32(sbit
| (0xfe << 23));
423 return make_float32(sbit
| (~exp
& 0xff) << 23);
427 float64
HELPER(frecpx_f64
)(float64 a
, void *fpstp
)
429 float_status
*fpst
= fpstp
;
430 uint64_t val64
, sbit
;
433 if (float64_is_any_nan(a
)) {
435 if (float64_is_signaling_nan(a
, fpst
)) {
436 float_raise(float_flag_invalid
, fpst
);
437 nan
= float64_maybe_silence_nan(a
, fpst
);
439 if (fpst
->default_nan_mode
) {
440 nan
= float64_default_nan(fpst
);
445 val64
= float64_val(a
);
446 sbit
= 0x8000000000000000ULL
& val64
;
447 exp
= extract64(float64_val(a
), 52, 11);
450 return make_float64(sbit
| (0x7feULL
<< 52));
452 return make_float64(sbit
| (~exp
& 0x7ffULL
) << 52);
456 float32
HELPER(fcvtx_f64_to_f32
)(float64 a
, CPUARMState
*env
)
458 /* Von Neumann rounding is implemented by using round-to-zero
459 * and then setting the LSB of the result if Inexact was raised.
462 float_status
*fpst
= &env
->vfp
.fp_status
;
463 float_status tstat
= *fpst
;
466 set_float_rounding_mode(float_round_to_zero
, &tstat
);
467 set_float_exception_flags(0, &tstat
);
468 r
= float64_to_float32(a
, &tstat
);
469 r
= float32_maybe_silence_nan(r
, &tstat
);
470 exflags
= get_float_exception_flags(&tstat
);
471 if (exflags
& float_flag_inexact
) {
472 r
= make_float32(float32_val(r
) | 1);
474 exflags
|= get_float_exception_flags(fpst
);
475 set_float_exception_flags(exflags
, fpst
);
479 /* 64-bit versions of the CRC helpers. Note that although the operation
480 * (and the prototypes of crc32c() and crc32() mean that only the bottom
481 * 32 bits of the accumulator and result are used, we pass and return
482 * uint64_t for convenience of the generated code. Unlike the 32-bit
483 * instruction set versions, val may genuinely have 64 bits of data in it.
484 * The upper bytes of val (above the number specified by 'bytes') must have
485 * been zeroed out by the caller.
487 uint64_t HELPER(crc32_64
)(uint64_t acc
, uint64_t val
, uint32_t bytes
)
493 /* zlib crc32 converts the accumulator and output to one's complement. */
494 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
497 uint64_t HELPER(crc32c_64
)(uint64_t acc
, uint64_t val
, uint32_t bytes
)
503 /* Linux crc32c converts the output to one's complement. */
504 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;
507 /* Returns 0 on success; 1 otherwise. */
508 static uint64_t do_paired_cmpxchg64_le(CPUARMState
*env
, uint64_t addr
,
509 uint64_t new_lo
, uint64_t new_hi
,
510 bool parallel
, uintptr_t ra
)
512 Int128 oldv
, cmpv
, newv
;
515 cmpv
= int128_make128(env
->exclusive_val
, env
->exclusive_high
);
516 newv
= int128_make128(new_lo
, new_hi
);
519 #ifndef CONFIG_ATOMIC128
520 cpu_loop_exit_atomic(ENV_GET_CPU(env
), ra
);
522 int mem_idx
= cpu_mmu_index(env
, false);
523 TCGMemOpIdx oi
= make_memop_idx(MO_LEQ
| MO_ALIGN_16
, mem_idx
);
524 oldv
= helper_atomic_cmpxchgo_le_mmu(env
, addr
, cmpv
, newv
, oi
, ra
);
525 success
= int128_eq(oldv
, cmpv
);
530 #ifdef CONFIG_USER_ONLY
531 /* ??? Enforce alignment. */
532 uint64_t *haddr
= g2h(addr
);
535 o0
= ldq_le_p(haddr
+ 0);
536 o1
= ldq_le_p(haddr
+ 1);
537 oldv
= int128_make128(o0
, o1
);
539 success
= int128_eq(oldv
, cmpv
);
541 stq_le_p(haddr
+ 0, int128_getlo(newv
));
542 stq_le_p(haddr
+ 1, int128_gethi(newv
));
546 int mem_idx
= cpu_mmu_index(env
, false);
547 TCGMemOpIdx oi0
= make_memop_idx(MO_LEQ
| MO_ALIGN_16
, mem_idx
);
548 TCGMemOpIdx oi1
= make_memop_idx(MO_LEQ
, mem_idx
);
550 o0
= helper_le_ldq_mmu(env
, addr
+ 0, oi0
, ra
);
551 o1
= helper_le_ldq_mmu(env
, addr
+ 8, oi1
, ra
);
552 oldv
= int128_make128(o0
, o1
);
554 success
= int128_eq(oldv
, cmpv
);
556 helper_le_stq_mmu(env
, addr
+ 0, int128_getlo(newv
), oi1
, ra
);
557 helper_le_stq_mmu(env
, addr
+ 8, int128_gethi(newv
), oi1
, ra
);
565 uint64_t HELPER(paired_cmpxchg64_le
)(CPUARMState
*env
, uint64_t addr
,
566 uint64_t new_lo
, uint64_t new_hi
)
568 return do_paired_cmpxchg64_le(env
, addr
, new_lo
, new_hi
, false, GETPC());
571 uint64_t HELPER(paired_cmpxchg64_le_parallel
)(CPUARMState
*env
, uint64_t addr
,
572 uint64_t new_lo
, uint64_t new_hi
)
574 return do_paired_cmpxchg64_le(env
, addr
, new_lo
, new_hi
, true, GETPC());
577 static uint64_t do_paired_cmpxchg64_be(CPUARMState
*env
, uint64_t addr
,
578 uint64_t new_lo
, uint64_t new_hi
,
579 bool parallel
, uintptr_t ra
)
581 Int128 oldv
, cmpv
, newv
;
584 /* high and low need to be switched here because this is not actually a
585 * 128bit store but two doublewords stored consecutively
587 cmpv
= int128_make128(env
->exclusive_high
, env
->exclusive_val
);
588 newv
= int128_make128(new_hi
, new_lo
);
591 #ifndef CONFIG_ATOMIC128
592 cpu_loop_exit_atomic(ENV_GET_CPU(env
), ra
);
594 int mem_idx
= cpu_mmu_index(env
, false);
595 TCGMemOpIdx oi
= make_memop_idx(MO_BEQ
| MO_ALIGN_16
, mem_idx
);
596 oldv
= helper_atomic_cmpxchgo_be_mmu(env
, addr
, cmpv
, newv
, oi
, ra
);
597 success
= int128_eq(oldv
, cmpv
);
602 #ifdef CONFIG_USER_ONLY
603 /* ??? Enforce alignment. */
604 uint64_t *haddr
= g2h(addr
);
607 o1
= ldq_be_p(haddr
+ 0);
608 o0
= ldq_be_p(haddr
+ 1);
609 oldv
= int128_make128(o0
, o1
);
611 success
= int128_eq(oldv
, cmpv
);
613 stq_be_p(haddr
+ 0, int128_gethi(newv
));
614 stq_be_p(haddr
+ 1, int128_getlo(newv
));
618 int mem_idx
= cpu_mmu_index(env
, false);
619 TCGMemOpIdx oi0
= make_memop_idx(MO_BEQ
| MO_ALIGN_16
, mem_idx
);
620 TCGMemOpIdx oi1
= make_memop_idx(MO_BEQ
, mem_idx
);
622 o1
= helper_be_ldq_mmu(env
, addr
+ 0, oi0
, ra
);
623 o0
= helper_be_ldq_mmu(env
, addr
+ 8, oi1
, ra
);
624 oldv
= int128_make128(o0
, o1
);
626 success
= int128_eq(oldv
, cmpv
);
628 helper_be_stq_mmu(env
, addr
+ 0, int128_gethi(newv
), oi1
, ra
);
629 helper_be_stq_mmu(env
, addr
+ 8, int128_getlo(newv
), oi1
, ra
);
637 uint64_t HELPER(paired_cmpxchg64_be
)(CPUARMState
*env
, uint64_t addr
,
638 uint64_t new_lo
, uint64_t new_hi
)
640 return do_paired_cmpxchg64_be(env
, addr
, new_lo
, new_hi
, false, GETPC());
643 uint64_t HELPER(paired_cmpxchg64_be_parallel
)(CPUARMState
*env
, uint64_t addr
,
644 uint64_t new_lo
, uint64_t new_hi
)
646 return do_paired_cmpxchg64_be(env
, addr
, new_lo
, new_hi
, true, GETPC());
650 * AdvSIMD half-precision
653 #define ADVSIMD_HELPER(name, suffix) HELPER(glue(glue(advsimd_, name), suffix))
655 #define ADVSIMD_HALFOP(name) \
656 float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \
658 float_status *fpst = fpstp; \
659 return float16_ ## name(a, b, fpst); \
668 ADVSIMD_HALFOP(minnum
)
669 ADVSIMD_HALFOP(maxnum
)
671 #define ADVSIMD_TWOHALFOP(name) \
672 uint32_t ADVSIMD_HELPER(name, 2h)(uint32_t two_a, uint32_t two_b, void *fpstp) \
674 float16 a1, a2, b1, b2; \
676 float_status *fpst = fpstp; \
677 a1 = extract32(two_a, 0, 16); \
678 a2 = extract32(two_a, 16, 16); \
679 b1 = extract32(two_b, 0, 16); \
680 b2 = extract32(two_b, 16, 16); \
681 r1 = float16_ ## name(a1, b1, fpst); \
682 r2 = float16_ ## name(a2, b2, fpst); \
683 return deposit32(r1, 16, 16, r2); \
686 ADVSIMD_TWOHALFOP(add
)
687 ADVSIMD_TWOHALFOP(sub
)
688 ADVSIMD_TWOHALFOP(mul
)
689 ADVSIMD_TWOHALFOP(div
)
690 ADVSIMD_TWOHALFOP(min
)
691 ADVSIMD_TWOHALFOP(max
)
692 ADVSIMD_TWOHALFOP(minnum
)
693 ADVSIMD_TWOHALFOP(maxnum
)
695 /* Data processing - scalar floating-point and advanced SIMD */
696 static float16
float16_mulx(float16 a
, float16 b
, void *fpstp
)
698 float_status
*fpst
= fpstp
;
700 a
= float16_squash_input_denormal(a
, fpst
);
701 b
= float16_squash_input_denormal(b
, fpst
);
703 if ((float16_is_zero(a
) && float16_is_infinity(b
)) ||
704 (float16_is_infinity(a
) && float16_is_zero(b
))) {
705 /* 2.0 with the sign bit set to sign(A) XOR sign(B) */
706 return make_float16((1U << 14) |
707 ((float16_val(a
) ^ float16_val(b
)) & (1U << 15)));
709 return float16_mul(a
, b
, fpst
);
713 ADVSIMD_TWOHALFOP(mulx
)
715 /* fused multiply-accumulate */
716 float16
HELPER(advsimd_muladdh
)(float16 a
, float16 b
, float16 c
, void *fpstp
)
718 float_status
*fpst
= fpstp
;
719 return float16_muladd(a
, b
, c
, 0, fpst
);
722 uint32_t HELPER(advsimd_muladd2h
)(uint32_t two_a
, uint32_t two_b
,
723 uint32_t two_c
, void *fpstp
)
725 float_status
*fpst
= fpstp
;
726 float16 a1
, a2
, b1
, b2
, c1
, c2
;
728 a1
= extract32(two_a
, 0, 16);
729 a2
= extract32(two_a
, 16, 16);
730 b1
= extract32(two_b
, 0, 16);
731 b2
= extract32(two_b
, 16, 16);
732 c1
= extract32(two_c
, 0, 16);
733 c2
= extract32(two_c
, 16, 16);
734 r1
= float16_muladd(a1
, b1
, c1
, 0, fpst
);
735 r2
= float16_muladd(a2
, b2
, c2
, 0, fpst
);
736 return deposit32(r1
, 16, 16, r2
);
740 * Floating point comparisons produce an integer result. Softfloat
741 * routines return float_relation types which we convert to the 0/-1
745 #define ADVSIMD_CMPRES(test) (test) ? 0xffff : 0
747 uint32_t HELPER(advsimd_ceq_f16
)(float16 a
, float16 b
, void *fpstp
)
749 float_status
*fpst
= fpstp
;
750 int compare
= float16_compare_quiet(a
, b
, fpst
);
751 return ADVSIMD_CMPRES(compare
== float_relation_equal
);
754 uint32_t HELPER(advsimd_cge_f16
)(float16 a
, float16 b
, void *fpstp
)
756 float_status
*fpst
= fpstp
;
757 int compare
= float16_compare(a
, b
, fpst
);
758 return ADVSIMD_CMPRES(compare
== float_relation_greater
||
759 compare
== float_relation_equal
);
762 uint32_t HELPER(advsimd_cgt_f16
)(float16 a
, float16 b
, void *fpstp
)
764 float_status
*fpst
= fpstp
;
765 int compare
= float16_compare(a
, b
, fpst
);
766 return ADVSIMD_CMPRES(compare
== float_relation_greater
);
769 uint32_t HELPER(advsimd_acge_f16
)(float16 a
, float16 b
, void *fpstp
)
771 float_status
*fpst
= fpstp
;
772 float16 f0
= float16_abs(a
);
773 float16 f1
= float16_abs(b
);
774 int compare
= float16_compare(f0
, f1
, fpst
);
775 return ADVSIMD_CMPRES(compare
== float_relation_greater
||
776 compare
== float_relation_equal
);
779 uint32_t HELPER(advsimd_acgt_f16
)(float16 a
, float16 b
, void *fpstp
)
781 float_status
*fpst
= fpstp
;
782 float16 f0
= float16_abs(a
);
783 float16 f1
= float16_abs(b
);
784 int compare
= float16_compare(f0
, f1
, fpst
);
785 return ADVSIMD_CMPRES(compare
== float_relation_greater
);
788 /* round to integral */
789 float16
HELPER(advsimd_rinth_exact
)(float16 x
, void *fp_status
)
791 return float16_round_to_int(x
, fp_status
);
794 float16
HELPER(advsimd_rinth
)(float16 x
, void *fp_status
)
796 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
799 ret
= float16_round_to_int(x
, fp_status
);
801 /* Suppress any inexact exceptions the conversion produced */
802 if (!(old_flags
& float_flag_inexact
)) {
803 new_flags
= get_float_exception_flags(fp_status
);
804 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
811 * Half-precision floating point conversion functions
813 * There are a multitude of conversion functions with various
814 * different rounding modes. This is dealt with by the calling code
815 * setting the mode appropriately before calling the helper.
818 uint32_t HELPER(advsimd_f16tosinth
)(float16 a
, void *fpstp
)
820 float_status
*fpst
= fpstp
;
822 /* Invalid if we are passed a NaN */
823 if (float16_is_any_nan(a
)) {
824 float_raise(float_flag_invalid
, fpst
);
827 return float16_to_int16(a
, fpst
);
830 uint32_t HELPER(advsimd_f16touinth
)(float16 a
, void *fpstp
)
832 float_status
*fpst
= fpstp
;
834 /* Invalid if we are passed a NaN */
835 if (float16_is_any_nan(a
)) {
836 float_raise(float_flag_invalid
, fpst
);
839 return float16_to_uint16(a
, fpst
);
843 * Square Root and Reciprocal square root
846 float16
HELPER(sqrt_f16
)(float16 a
, void *fpstp
)
848 float_status
*s
= fpstp
;
850 return float16_sqrt(a
, s
);