4 * This code is licensed under the GNU GPL v2 or later.
6 * SPDX-License-Identifier: GPL-2.0-or-later
9 #include "qemu/osdep.h"
13 #include "internals.h"
14 #include "exec/helper-proto.h"
15 #include "qemu/main-loop.h"
16 #include "qemu/timer.h"
17 #include "qemu/bitops.h"
18 #include "qemu/crc32c.h"
19 #include "qemu/qemu-print.h"
20 #include "exec/exec-all.h"
21 #include <zlib.h> /* For crc32 */
23 #include "sysemu/cpu-timers.h"
24 #include "sysemu/kvm.h"
25 #include "sysemu/tcg.h"
26 #include "qapi/error.h"
27 #include "qemu/guest-random.h"
29 #include "semihosting/common-semi.h"
33 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
35 static void switch_mode(CPUARMState
*env
, int mode
);
37 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
39 assert(ri
->fieldoffset
);
40 if (cpreg_field_is_64bit(ri
)) {
41 return CPREG_FIELD64(env
, ri
);
43 return CPREG_FIELD32(env
, ri
);
47 void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
49 assert(ri
->fieldoffset
);
50 if (cpreg_field_is_64bit(ri
)) {
51 CPREG_FIELD64(env
, ri
) = value
;
53 CPREG_FIELD32(env
, ri
) = value
;
57 static void *raw_ptr(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
59 return (char *)env
+ ri
->fieldoffset
;
62 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
64 /* Raw read of a coprocessor register (as needed for migration, etc). */
65 if (ri
->type
& ARM_CP_CONST
) {
66 return ri
->resetvalue
;
67 } else if (ri
->raw_readfn
) {
68 return ri
->raw_readfn(env
, ri
);
69 } else if (ri
->readfn
) {
70 return ri
->readfn(env
, ri
);
72 return raw_read(env
, ri
);
76 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
80 * Raw write of a coprocessor register (as needed for migration, etc).
81 * Note that constant registers are treated as write-ignored; the
82 * caller should check for success by whether a readback gives the
85 if (ri
->type
& ARM_CP_CONST
) {
87 } else if (ri
->raw_writefn
) {
88 ri
->raw_writefn(env
, ri
, v
);
89 } else if (ri
->writefn
) {
90 ri
->writefn(env
, ri
, v
);
92 raw_write(env
, ri
, v
);
96 static bool raw_accessors_invalid(const ARMCPRegInfo
*ri
)
99 * Return true if the regdef would cause an assertion if you called
100 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
101 * program bug for it not to have the NO_RAW flag).
102 * NB that returning false here doesn't necessarily mean that calling
103 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
104 * read/write access functions which are safe for raw use" from "has
105 * read/write access functions which have side effects but has forgotten
106 * to provide raw access functions".
107 * The tests here line up with the conditions in read/write_raw_cp_reg()
108 * and assertions in raw_read()/raw_write().
110 if ((ri
->type
& ARM_CP_CONST
) ||
112 ((ri
->raw_writefn
|| ri
->writefn
) && (ri
->raw_readfn
|| ri
->readfn
))) {
118 bool write_cpustate_to_list(ARMCPU
*cpu
, bool kvm_sync
)
120 /* Write the coprocessor state from cpu->env to the (index,value) list. */
124 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
125 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
126 const ARMCPRegInfo
*ri
;
129 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
134 if (ri
->type
& ARM_CP_NO_RAW
) {
138 newval
= read_raw_cp_reg(&cpu
->env
, ri
);
141 * Only sync if the previous list->cpustate sync succeeded.
142 * Rather than tracking the success/failure state for every
143 * item in the list, we just recheck "does the raw write we must
144 * have made in write_list_to_cpustate() read back OK" here.
146 uint64_t oldval
= cpu
->cpreg_values
[i
];
148 if (oldval
== newval
) {
152 write_raw_cp_reg(&cpu
->env
, ri
, oldval
);
153 if (read_raw_cp_reg(&cpu
->env
, ri
) != oldval
) {
157 write_raw_cp_reg(&cpu
->env
, ri
, newval
);
159 cpu
->cpreg_values
[i
] = newval
;
164 bool write_list_to_cpustate(ARMCPU
*cpu
)
169 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
170 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
171 uint64_t v
= cpu
->cpreg_values
[i
];
172 const ARMCPRegInfo
*ri
;
174 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
179 if (ri
->type
& ARM_CP_NO_RAW
) {
183 * Write value and confirm it reads back as written
184 * (to catch read-only registers and partially read-only
185 * registers where the incoming migration value doesn't match)
187 write_raw_cp_reg(&cpu
->env
, ri
, v
);
188 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
195 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
197 ARMCPU
*cpu
= opaque
;
198 uint32_t regidx
= (uintptr_t)key
;
199 const ARMCPRegInfo
*ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
201 if (!(ri
->type
& (ARM_CP_NO_RAW
| ARM_CP_ALIAS
))) {
202 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
203 /* The value array need not be initialized at this point */
204 cpu
->cpreg_array_len
++;
208 static void count_cpreg(gpointer key
, gpointer opaque
)
210 ARMCPU
*cpu
= opaque
;
211 const ARMCPRegInfo
*ri
;
213 ri
= g_hash_table_lookup(cpu
->cp_regs
, key
);
215 if (!(ri
->type
& (ARM_CP_NO_RAW
| ARM_CP_ALIAS
))) {
216 cpu
->cpreg_array_len
++;
220 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
222 uint64_t aidx
= cpreg_to_kvm_id((uintptr_t)a
);
223 uint64_t bidx
= cpreg_to_kvm_id((uintptr_t)b
);
234 void init_cpreg_list(ARMCPU
*cpu
)
237 * Initialise the cpreg_tuples[] array based on the cp_regs hash.
238 * Note that we require cpreg_tuples[] to be sorted by key ID.
243 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
244 keys
= g_list_sort(keys
, cpreg_key_compare
);
246 cpu
->cpreg_array_len
= 0;
248 g_list_foreach(keys
, count_cpreg
, cpu
);
250 arraylen
= cpu
->cpreg_array_len
;
251 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
252 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
253 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
254 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
255 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
256 cpu
->cpreg_array_len
= 0;
258 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
260 assert(cpu
->cpreg_array_len
== arraylen
);
266 * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0.
268 static CPAccessResult
access_el3_aa32ns(CPUARMState
*env
,
269 const ARMCPRegInfo
*ri
,
272 if (!is_a64(env
) && arm_current_el(env
) == 3 &&
273 arm_is_secure_below_el3(env
)) {
274 return CP_ACCESS_TRAP_UNCATEGORIZED
;
280 * Some secure-only AArch32 registers trap to EL3 if used from
281 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
282 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
283 * We assume that the .access field is set to PL1_RW.
285 static CPAccessResult
access_trap_aa32s_el1(CPUARMState
*env
,
286 const ARMCPRegInfo
*ri
,
289 if (arm_current_el(env
) == 3) {
292 if (arm_is_secure_below_el3(env
)) {
293 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
294 return CP_ACCESS_TRAP_EL2
;
296 return CP_ACCESS_TRAP_EL3
;
298 /* This will be EL1 NS and EL2 NS, which just UNDEF */
299 return CP_ACCESS_TRAP_UNCATEGORIZED
;
303 * Check for traps to performance monitor registers, which are controlled
304 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
306 static CPAccessResult
access_tpm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
309 int el
= arm_current_el(env
);
310 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
312 if (el
< 2 && (mdcr_el2
& MDCR_TPM
)) {
313 return CP_ACCESS_TRAP_EL2
;
315 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
316 return CP_ACCESS_TRAP_EL3
;
321 /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */
322 CPAccessResult
access_tvm_trvm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
325 if (arm_current_el(env
) == 1) {
326 uint64_t trap
= isread
? HCR_TRVM
: HCR_TVM
;
327 if (arm_hcr_el2_eff(env
) & trap
) {
328 return CP_ACCESS_TRAP_EL2
;
334 /* Check for traps from EL1 due to HCR_EL2.TSW. */
335 static CPAccessResult
access_tsw(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
338 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TSW
)) {
339 return CP_ACCESS_TRAP_EL2
;
344 /* Check for traps from EL1 due to HCR_EL2.TACR. */
345 static CPAccessResult
access_tacr(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
348 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TACR
)) {
349 return CP_ACCESS_TRAP_EL2
;
354 /* Check for traps from EL1 due to HCR_EL2.TTLB. */
355 static CPAccessResult
access_ttlb(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
358 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TTLB
)) {
359 return CP_ACCESS_TRAP_EL2
;
364 /* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBIS. */
365 static CPAccessResult
access_ttlbis(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
368 if (arm_current_el(env
) == 1 &&
369 (arm_hcr_el2_eff(env
) & (HCR_TTLB
| HCR_TTLBIS
))) {
370 return CP_ACCESS_TRAP_EL2
;
375 #ifdef TARGET_AARCH64
376 /* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBOS. */
377 static CPAccessResult
access_ttlbos(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
380 if (arm_current_el(env
) == 1 &&
381 (arm_hcr_el2_eff(env
) & (HCR_TTLB
| HCR_TTLBOS
))) {
382 return CP_ACCESS_TRAP_EL2
;
388 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
390 ARMCPU
*cpu
= env_archcpu(env
);
392 raw_write(env
, ri
, value
);
393 tlb_flush(CPU(cpu
)); /* Flush TLB as domain not tracked in TLB */
396 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
398 ARMCPU
*cpu
= env_archcpu(env
);
400 if (raw_read(env
, ri
) != value
) {
402 * Unlike real hardware the qemu TLB uses virtual addresses,
403 * not modified virtual addresses, so this causes a TLB flush.
406 raw_write(env
, ri
, value
);
410 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
413 ARMCPU
*cpu
= env_archcpu(env
);
415 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_PMSA
)
416 && !extended_addresses_enabled(env
)) {
418 * For VMSA (when not using the LPAE long descriptor page table
419 * format) this register includes the ASID, so do a TLB flush.
420 * For PMSA it is purely a process ID and no action is needed.
424 raw_write(env
, ri
, value
);
427 static int alle1_tlbmask(CPUARMState
*env
)
430 * Note that the 'ALL' scope must invalidate both stage 1 and
431 * stage 2 translations, whereas most other scopes only invalidate
432 * stage 1 translations.
434 return (ARMMMUIdxBit_E10_1
|
435 ARMMMUIdxBit_E10_1_PAN
|
437 ARMMMUIdxBit_Stage2
|
438 ARMMMUIdxBit_Stage2_S
);
442 /* IS variants of TLB operations must affect all cores */
443 static void tlbiall_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
446 CPUState
*cs
= env_cpu(env
);
448 tlb_flush_all_cpus_synced(cs
);
451 static void tlbiasid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
454 CPUState
*cs
= env_cpu(env
);
456 tlb_flush_all_cpus_synced(cs
);
459 static void tlbimva_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
462 CPUState
*cs
= env_cpu(env
);
464 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
467 static void tlbimvaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
470 CPUState
*cs
= env_cpu(env
);
472 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
476 * Non-IS variants of TLB operations are upgraded to
477 * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to
478 * force broadcast of these operations.
480 static bool tlb_force_broadcast(CPUARMState
*env
)
482 return arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_FB
);
485 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
488 /* Invalidate all (TLBIALL) */
489 CPUState
*cs
= env_cpu(env
);
491 if (tlb_force_broadcast(env
)) {
492 tlb_flush_all_cpus_synced(cs
);
498 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
501 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
502 CPUState
*cs
= env_cpu(env
);
504 value
&= TARGET_PAGE_MASK
;
505 if (tlb_force_broadcast(env
)) {
506 tlb_flush_page_all_cpus_synced(cs
, value
);
508 tlb_flush_page(cs
, value
);
512 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
515 /* Invalidate by ASID (TLBIASID) */
516 CPUState
*cs
= env_cpu(env
);
518 if (tlb_force_broadcast(env
)) {
519 tlb_flush_all_cpus_synced(cs
);
525 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
528 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
529 CPUState
*cs
= env_cpu(env
);
531 value
&= TARGET_PAGE_MASK
;
532 if (tlb_force_broadcast(env
)) {
533 tlb_flush_page_all_cpus_synced(cs
, value
);
535 tlb_flush_page(cs
, value
);
539 static void tlbiall_nsnh_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
542 CPUState
*cs
= env_cpu(env
);
544 tlb_flush_by_mmuidx(cs
, alle1_tlbmask(env
));
547 static void tlbiall_nsnh_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
550 CPUState
*cs
= env_cpu(env
);
552 tlb_flush_by_mmuidx_all_cpus_synced(cs
, alle1_tlbmask(env
));
556 static void tlbiall_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
559 CPUState
*cs
= env_cpu(env
);
561 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_E2
);
564 static void tlbiall_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
567 CPUState
*cs
= env_cpu(env
);
569 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_E2
);
572 static void tlbimva_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
575 CPUState
*cs
= env_cpu(env
);
576 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
578 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_E2
);
581 static void tlbimva_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
584 CPUState
*cs
= env_cpu(env
);
585 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
587 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
591 static void tlbiipas2_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
594 CPUState
*cs
= env_cpu(env
);
595 uint64_t pageaddr
= (value
& MAKE_64BIT_MASK(0, 28)) << 12;
597 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_Stage2
);
600 static void tlbiipas2is_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
603 CPUState
*cs
= env_cpu(env
);
604 uint64_t pageaddr
= (value
& MAKE_64BIT_MASK(0, 28)) << 12;
606 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, ARMMMUIdxBit_Stage2
);
609 static const ARMCPRegInfo cp_reginfo
[] = {
611 * Define the secure and non-secure FCSE identifier CP registers
612 * separately because there is no secure bank in V8 (no _EL3). This allows
613 * the secure register to be properly reset and migrated. There is also no
614 * v8 EL1 version of the register so the non-secure instance stands alone.
617 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
618 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
619 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_ns
),
620 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
621 { .name
= "FCSEIDR_S",
622 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
623 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
624 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_s
),
625 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
627 * Define the secure and non-secure context identifier CP registers
628 * separately because there is no secure bank in V8 (no _EL3). This allows
629 * the secure register to be properly reset and migrated. In the
630 * non-secure case, the 32-bit register will have reset and migration
631 * disabled during registration as it is handled by the 64-bit instance.
633 { .name
= "CONTEXTIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
634 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
635 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
636 .fgt
= FGT_CONTEXTIDR_EL1
,
637 .secure
= ARM_CP_SECSTATE_NS
,
638 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[1]),
639 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
640 { .name
= "CONTEXTIDR_S", .state
= ARM_CP_STATE_AA32
,
641 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
642 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
643 .secure
= ARM_CP_SECSTATE_S
,
644 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_s
),
645 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
648 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
650 * NB: Some of these registers exist in v8 but with more precise
651 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
653 /* MMU Domain access control / MPU write buffer control */
655 .cp
= 15, .opc1
= CP_ANY
, .crn
= 3, .crm
= CP_ANY
, .opc2
= CP_ANY
,
656 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
657 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
658 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
659 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
661 * ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
662 * For v6 and v5, these mappings are overly broad.
664 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 0,
665 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
666 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 1,
667 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
668 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 4,
669 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
670 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 8,
671 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
672 /* Cache maintenance ops; some of this space may be overridden later. */
673 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
674 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
675 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
678 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
680 * Not all pre-v6 cores implemented this WFI, so this is slightly
683 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
684 .access
= PL1_W
, .type
= ARM_CP_WFI
},
687 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
689 * Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
690 * is UNPREDICTABLE; we choose to NOP as most implementations do).
692 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
693 .access
= PL1_W
, .type
= ARM_CP_WFI
},
695 * L1 cache lockdown. Not architectural in v6 and earlier but in practice
696 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
697 * OMAPCP will override this space.
699 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
700 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
702 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
703 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
705 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
706 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
707 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
710 * We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
711 * implementing it as RAZ means the "debug architecture version" bits
712 * will read as a reserved value, which should cause Linux to not try
713 * to use the debug hardware.
715 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
716 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
718 * MMU TLB control. Note that the wildcarding means we cover not just
719 * the unified TLB ops but also the dside/iside/inner-shareable variants.
721 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
722 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
723 .type
= ARM_CP_NO_RAW
},
724 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
725 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
726 .type
= ARM_CP_NO_RAW
},
727 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
728 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
729 .type
= ARM_CP_NO_RAW
},
730 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
731 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
732 .type
= ARM_CP_NO_RAW
},
733 { .name
= "PRRR", .cp
= 15, .crn
= 10, .crm
= 2,
734 .opc1
= 0, .opc2
= 0, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
735 { .name
= "NMRR", .cp
= 15, .crn
= 10, .crm
= 2,
736 .opc1
= 0, .opc2
= 1, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
739 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
744 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
745 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
747 * ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
748 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
749 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
751 if (cpu_isar_feature(aa32_vfp_simd
, env_archcpu(env
))) {
752 /* VFP coprocessor: cp10 & cp11 [23:20] */
753 mask
|= R_CPACR_ASEDIS_MASK
|
754 R_CPACR_D32DIS_MASK
|
758 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
759 /* ASEDIS [31] bit is RAO/WI */
760 value
|= R_CPACR_ASEDIS_MASK
;
764 * VFPv3 and upwards with NEON implement 32 double precision
765 * registers (D0-D31).
767 if (!cpu_isar_feature(aa32_simd_r32
, env_archcpu(env
))) {
768 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
769 value
|= R_CPACR_D32DIS_MASK
;
776 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
777 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
779 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
780 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
781 mask
= R_CPACR_CP11_MASK
| R_CPACR_CP10_MASK
;
782 value
= (value
& ~mask
) | (env
->cp15
.cpacr_el1
& mask
);
785 env
->cp15
.cpacr_el1
= value
;
788 static uint64_t cpacr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
791 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
792 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
794 uint64_t value
= env
->cp15
.cpacr_el1
;
796 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
797 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
798 value
= ~(R_CPACR_CP11_MASK
| R_CPACR_CP10_MASK
);
804 static void cpacr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
807 * Call cpacr_write() so that we reset with the correct RAO bits set
808 * for our CPU features.
810 cpacr_write(env
, ri
, 0);
813 static CPAccessResult
cpacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
816 if (arm_feature(env
, ARM_FEATURE_V8
)) {
817 /* Check if CPACR accesses are to be trapped to EL2 */
818 if (arm_current_el(env
) == 1 && arm_is_el2_enabled(env
) &&
819 FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TCPAC
)) {
820 return CP_ACCESS_TRAP_EL2
;
821 /* Check if CPACR accesses are to be trapped to EL3 */
822 } else if (arm_current_el(env
) < 3 &&
823 FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TCPAC
)) {
824 return CP_ACCESS_TRAP_EL3
;
831 static CPAccessResult
cptr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
834 /* Check if CPTR accesses are set to trap to EL3 */
835 if (arm_current_el(env
) == 2 &&
836 FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TCPAC
)) {
837 return CP_ACCESS_TRAP_EL3
;
843 static const ARMCPRegInfo v6_cp_reginfo
[] = {
844 /* prefetch by MVA in v6, NOP in v7 */
845 { .name
= "MVA_prefetch",
846 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
847 .access
= PL1_W
, .type
= ARM_CP_NOP
},
849 * We need to break the TB after ISB to execute self-modifying code
850 * correctly and also to take any pending interrupts immediately.
851 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
853 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
854 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
, .writefn
= arm_cp_write_ignore
},
855 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
856 .access
= PL0_W
, .type
= ARM_CP_NOP
},
857 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
858 .access
= PL0_W
, .type
= ARM_CP_NOP
},
859 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
860 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
861 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ifar_s
),
862 offsetof(CPUARMState
, cp15
.ifar_ns
) },
865 * Watchpoint Fault Address Register : should actually only be present
866 * for 1136, 1176, 11MPCore.
868 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
869 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
870 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
871 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2, .accessfn
= cpacr_access
,
872 .fgt
= FGT_CPACR_EL1
,
873 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.cpacr_el1
),
874 .resetfn
= cpacr_reset
, .writefn
= cpacr_write
, .readfn
= cpacr_read
},
877 typedef struct pm_event
{
878 uint16_t number
; /* PMEVTYPER.evtCount is 16 bits wide */
879 /* If the event is supported on this CPU (used to generate PMCEID[01]) */
880 bool (*supported
)(CPUARMState
*);
882 * Retrieve the current count of the underlying event. The programmed
883 * counters hold a difference from the return value from this function
885 uint64_t (*get_count
)(CPUARMState
*);
887 * Return how many nanoseconds it will take (at a minimum) for count events
888 * to occur. A negative value indicates the counter will never overflow, or
889 * that the counter has otherwise arranged for the overflow bit to be set
890 * and the PMU interrupt to be raised on overflow.
892 int64_t (*ns_per_count
)(uint64_t);
895 static bool event_always_supported(CPUARMState
*env
)
900 static uint64_t swinc_get_count(CPUARMState
*env
)
903 * SW_INCR events are written directly to the pmevcntr's by writes to
904 * PMSWINC, so there is no underlying count maintained by the PMU itself
909 static int64_t swinc_ns_per(uint64_t ignored
)
915 * Return the underlying cycle count for the PMU cycle counters. If we're in
916 * usermode, simply return 0.
918 static uint64_t cycles_get_count(CPUARMState
*env
)
920 #ifndef CONFIG_USER_ONLY
921 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
922 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
924 return cpu_get_host_ticks();
928 #ifndef CONFIG_USER_ONLY
929 static int64_t cycles_ns_per(uint64_t cycles
)
931 return (ARM_CPU_FREQ
/ NANOSECONDS_PER_SECOND
) * cycles
;
934 static bool instructions_supported(CPUARMState
*env
)
936 return icount_enabled() == 1; /* Precise instruction counting */
939 static uint64_t instructions_get_count(CPUARMState
*env
)
941 return (uint64_t)icount_get_raw();
944 static int64_t instructions_ns_per(uint64_t icount
)
946 return icount_to_ns((int64_t)icount
);
950 static bool pmuv3p1_events_supported(CPUARMState
*env
)
952 /* For events which are supported in any v8.1 PMU */
953 return cpu_isar_feature(any_pmuv3p1
, env_archcpu(env
));
956 static bool pmuv3p4_events_supported(CPUARMState
*env
)
958 /* For events which are supported in any v8.1 PMU */
959 return cpu_isar_feature(any_pmuv3p4
, env_archcpu(env
));
962 static uint64_t zero_event_get_count(CPUARMState
*env
)
964 /* For events which on QEMU never fire, so their count is always zero */
968 static int64_t zero_event_ns_per(uint64_t cycles
)
970 /* An event which never fires can never overflow */
974 static const pm_event pm_events
[] = {
975 { .number
= 0x000, /* SW_INCR */
976 .supported
= event_always_supported
,
977 .get_count
= swinc_get_count
,
978 .ns_per_count
= swinc_ns_per
,
980 #ifndef CONFIG_USER_ONLY
981 { .number
= 0x008, /* INST_RETIRED, Instruction architecturally executed */
982 .supported
= instructions_supported
,
983 .get_count
= instructions_get_count
,
984 .ns_per_count
= instructions_ns_per
,
986 { .number
= 0x011, /* CPU_CYCLES, Cycle */
987 .supported
= event_always_supported
,
988 .get_count
= cycles_get_count
,
989 .ns_per_count
= cycles_ns_per
,
992 { .number
= 0x023, /* STALL_FRONTEND */
993 .supported
= pmuv3p1_events_supported
,
994 .get_count
= zero_event_get_count
,
995 .ns_per_count
= zero_event_ns_per
,
997 { .number
= 0x024, /* STALL_BACKEND */
998 .supported
= pmuv3p1_events_supported
,
999 .get_count
= zero_event_get_count
,
1000 .ns_per_count
= zero_event_ns_per
,
1002 { .number
= 0x03c, /* STALL */
1003 .supported
= pmuv3p4_events_supported
,
1004 .get_count
= zero_event_get_count
,
1005 .ns_per_count
= zero_event_ns_per
,
1010 * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of
1011 * events (i.e. the statistical profiling extension), this implementation
1012 * should first be updated to something sparse instead of the current
1013 * supported_event_map[] array.
1015 #define MAX_EVENT_ID 0x3c
1016 #define UNSUPPORTED_EVENT UINT16_MAX
1017 static uint16_t supported_event_map
[MAX_EVENT_ID
+ 1];
1020 * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map
1021 * of ARM event numbers to indices in our pm_events array.
1023 * Note: Events in the 0x40XX range are not currently supported.
1025 void pmu_init(ARMCPU
*cpu
)
1030 * Empty supported_event_map and cpu->pmceid[01] before adding supported
1033 for (i
= 0; i
< ARRAY_SIZE(supported_event_map
); i
++) {
1034 supported_event_map
[i
] = UNSUPPORTED_EVENT
;
1039 for (i
= 0; i
< ARRAY_SIZE(pm_events
); i
++) {
1040 const pm_event
*cnt
= &pm_events
[i
];
1041 assert(cnt
->number
<= MAX_EVENT_ID
);
1042 /* We do not currently support events in the 0x40xx range */
1043 assert(cnt
->number
<= 0x3f);
1045 if (cnt
->supported(&cpu
->env
)) {
1046 supported_event_map
[cnt
->number
] = i
;
1047 uint64_t event_mask
= 1ULL << (cnt
->number
& 0x1f);
1048 if (cnt
->number
& 0x20) {
1049 cpu
->pmceid1
|= event_mask
;
1051 cpu
->pmceid0
|= event_mask
;
1058 * Check at runtime whether a PMU event is supported for the current machine
1060 static bool event_supported(uint16_t number
)
1062 if (number
> MAX_EVENT_ID
) {
1065 return supported_event_map
[number
] != UNSUPPORTED_EVENT
;
1068 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1072 * Performance monitor registers user accessibility is controlled
1073 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
1074 * trapping to EL2 or EL3 for other accesses.
1076 int el
= arm_current_el(env
);
1077 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
1079 if (el
== 0 && !(env
->cp15
.c9_pmuserenr
& 1)) {
1080 return CP_ACCESS_TRAP
;
1082 if (el
< 2 && (mdcr_el2
& MDCR_TPM
)) {
1083 return CP_ACCESS_TRAP_EL2
;
1085 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
1086 return CP_ACCESS_TRAP_EL3
;
1089 return CP_ACCESS_OK
;
1092 static CPAccessResult
pmreg_access_xevcntr(CPUARMState
*env
,
1093 const ARMCPRegInfo
*ri
,
1096 /* ER: event counter read trap control */
1097 if (arm_feature(env
, ARM_FEATURE_V8
)
1098 && arm_current_el(env
) == 0
1099 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0
1101 return CP_ACCESS_OK
;
1104 return pmreg_access(env
, ri
, isread
);
1107 static CPAccessResult
pmreg_access_swinc(CPUARMState
*env
,
1108 const ARMCPRegInfo
*ri
,
1111 /* SW: software increment write trap control */
1112 if (arm_feature(env
, ARM_FEATURE_V8
)
1113 && arm_current_el(env
) == 0
1114 && (env
->cp15
.c9_pmuserenr
& (1 << 1)) != 0
1116 return CP_ACCESS_OK
;
1119 return pmreg_access(env
, ri
, isread
);
1122 static CPAccessResult
pmreg_access_selr(CPUARMState
*env
,
1123 const ARMCPRegInfo
*ri
,
1126 /* ER: event counter read trap control */
1127 if (arm_feature(env
, ARM_FEATURE_V8
)
1128 && arm_current_el(env
) == 0
1129 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0) {
1130 return CP_ACCESS_OK
;
1133 return pmreg_access(env
, ri
, isread
);
1136 static CPAccessResult
pmreg_access_ccntr(CPUARMState
*env
,
1137 const ARMCPRegInfo
*ri
,
1140 /* CR: cycle counter read trap control */
1141 if (arm_feature(env
, ARM_FEATURE_V8
)
1142 && arm_current_el(env
) == 0
1143 && (env
->cp15
.c9_pmuserenr
& (1 << 2)) != 0
1145 return CP_ACCESS_OK
;
1148 return pmreg_access(env
, ri
, isread
);
1152 * Bits in MDCR_EL2 and MDCR_EL3 which pmu_counter_enabled() looks at.
1153 * We use these to decide whether we need to wrap a write to MDCR_EL2
1154 * or MDCR_EL3 in pmu_op_start()/pmu_op_finish() calls.
1156 #define MDCR_EL2_PMU_ENABLE_BITS \
1157 (MDCR_HPME | MDCR_HPMD | MDCR_HPMN | MDCR_HCCD | MDCR_HLP)
1158 #define MDCR_EL3_PMU_ENABLE_BITS (MDCR_SPME | MDCR_SCCD)
1161 * Returns true if the counter (pass 31 for PMCCNTR) should count events using
1162 * the current EL, security state, and register configuration.
1164 static bool pmu_counter_enabled(CPUARMState
*env
, uint8_t counter
)
1167 bool e
, p
, u
, nsk
, nsu
, nsh
, m
;
1168 bool enabled
, prohibited
= false, filtered
;
1169 bool secure
= arm_is_secure(env
);
1170 int el
= arm_current_el(env
);
1171 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
1172 uint8_t hpmn
= mdcr_el2
& MDCR_HPMN
;
1174 if (!arm_feature(env
, ARM_FEATURE_PMU
)) {
1178 if (!arm_feature(env
, ARM_FEATURE_EL2
) ||
1179 (counter
< hpmn
|| counter
== 31)) {
1180 e
= env
->cp15
.c9_pmcr
& PMCRE
;
1182 e
= mdcr_el2
& MDCR_HPME
;
1184 enabled
= e
&& (env
->cp15
.c9_pmcnten
& (1 << counter
));
1186 /* Is event counting prohibited? */
1187 if (el
== 2 && (counter
< hpmn
|| counter
== 31)) {
1188 prohibited
= mdcr_el2
& MDCR_HPMD
;
1191 prohibited
= prohibited
|| !(env
->cp15
.mdcr_el3
& MDCR_SPME
);
1194 if (counter
== 31) {
1196 * The cycle counter defaults to running. PMCR.DP says "disable
1197 * the cycle counter when event counting is prohibited".
1198 * Some MDCR bits disable the cycle counter specifically.
1200 prohibited
= prohibited
&& env
->cp15
.c9_pmcr
& PMCRDP
;
1201 if (cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1203 prohibited
= prohibited
|| (env
->cp15
.mdcr_el3
& MDCR_SCCD
);
1206 prohibited
= prohibited
|| (mdcr_el2
& MDCR_HCCD
);
1211 if (counter
== 31) {
1212 filter
= env
->cp15
.pmccfiltr_el0
;
1214 filter
= env
->cp15
.c14_pmevtyper
[counter
];
1217 p
= filter
& PMXEVTYPER_P
;
1218 u
= filter
& PMXEVTYPER_U
;
1219 nsk
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSK
);
1220 nsu
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSU
);
1221 nsh
= arm_feature(env
, ARM_FEATURE_EL2
) && (filter
& PMXEVTYPER_NSH
);
1222 m
= arm_el_is_aa64(env
, 1) &&
1223 arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_M
);
1226 filtered
= secure
? u
: u
!= nsu
;
1227 } else if (el
== 1) {
1228 filtered
= secure
? p
: p
!= nsk
;
1229 } else if (el
== 2) {
1235 if (counter
!= 31) {
1237 * If not checking PMCCNTR, ensure the counter is setup to an event we
1240 uint16_t event
= filter
& PMXEVTYPER_EVTCOUNT
;
1241 if (!event_supported(event
)) {
1246 return enabled
&& !prohibited
&& !filtered
;
1249 static void pmu_update_irq(CPUARMState
*env
)
1251 ARMCPU
*cpu
= env_archcpu(env
);
1252 qemu_set_irq(cpu
->pmu_interrupt
, (env
->cp15
.c9_pmcr
& PMCRE
) &&
1253 (env
->cp15
.c9_pminten
& env
->cp15
.c9_pmovsr
));
1256 static bool pmccntr_clockdiv_enabled(CPUARMState
*env
)
1259 * Return true if the clock divider is enabled and the cycle counter
1260 * is supposed to tick only once every 64 clock cycles. This is
1261 * controlled by PMCR.D, but if PMCR.LC is set to enable the long
1262 * (64-bit) cycle counter PMCR.D has no effect.
1264 return (env
->cp15
.c9_pmcr
& (PMCRD
| PMCRLC
)) == PMCRD
;
1267 static bool pmevcntr_is_64_bit(CPUARMState
*env
, int counter
)
1269 /* Return true if the specified event counter is configured to be 64 bit */
1271 /* This isn't intended to be used with the cycle counter */
1272 assert(counter
< 31);
1274 if (!cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1278 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
1280 * MDCR_EL2.HLP still applies even when EL2 is disabled in the
1281 * current security state, so we don't use arm_mdcr_el2_eff() here.
1283 bool hlp
= env
->cp15
.mdcr_el2
& MDCR_HLP
;
1284 int hpmn
= env
->cp15
.mdcr_el2
& MDCR_HPMN
;
1286 if (counter
>= hpmn
) {
1290 return env
->cp15
.c9_pmcr
& PMCRLP
;
1294 * Ensure c15_ccnt is the guest-visible count so that operations such as
1295 * enabling/disabling the counter or filtering, modifying the count itself,
1296 * etc. can be done logically. This is essentially a no-op if the counter is
1297 * not enabled at the time of the call.
1299 static void pmccntr_op_start(CPUARMState
*env
)
1301 uint64_t cycles
= cycles_get_count(env
);
1303 if (pmu_counter_enabled(env
, 31)) {
1304 uint64_t eff_cycles
= cycles
;
1305 if (pmccntr_clockdiv_enabled(env
)) {
1309 uint64_t new_pmccntr
= eff_cycles
- env
->cp15
.c15_ccnt_delta
;
1311 uint64_t overflow_mask
= env
->cp15
.c9_pmcr
& PMCRLC
? \
1312 1ull << 63 : 1ull << 31;
1313 if (env
->cp15
.c15_ccnt
& ~new_pmccntr
& overflow_mask
) {
1314 env
->cp15
.c9_pmovsr
|= (1ULL << 31);
1315 pmu_update_irq(env
);
1318 env
->cp15
.c15_ccnt
= new_pmccntr
;
1320 env
->cp15
.c15_ccnt_delta
= cycles
;
1324 * If PMCCNTR is enabled, recalculate the delta between the clock and the
1325 * guest-visible count. A call to pmccntr_op_finish should follow every call to
1328 static void pmccntr_op_finish(CPUARMState
*env
)
1330 if (pmu_counter_enabled(env
, 31)) {
1331 #ifndef CONFIG_USER_ONLY
1332 /* Calculate when the counter will next overflow */
1333 uint64_t remaining_cycles
= -env
->cp15
.c15_ccnt
;
1334 if (!(env
->cp15
.c9_pmcr
& PMCRLC
)) {
1335 remaining_cycles
= (uint32_t)remaining_cycles
;
1337 int64_t overflow_in
= cycles_ns_per(remaining_cycles
);
1339 if (overflow_in
> 0) {
1340 int64_t overflow_at
;
1342 if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1343 overflow_in
, &overflow_at
)) {
1344 ARMCPU
*cpu
= env_archcpu(env
);
1345 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1350 uint64_t prev_cycles
= env
->cp15
.c15_ccnt_delta
;
1351 if (pmccntr_clockdiv_enabled(env
)) {
1354 env
->cp15
.c15_ccnt_delta
= prev_cycles
- env
->cp15
.c15_ccnt
;
1358 static void pmevcntr_op_start(CPUARMState
*env
, uint8_t counter
)
1361 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1363 if (event_supported(event
)) {
1364 uint16_t event_idx
= supported_event_map
[event
];
1365 count
= pm_events
[event_idx
].get_count(env
);
1368 if (pmu_counter_enabled(env
, counter
)) {
1369 uint64_t new_pmevcntr
= count
- env
->cp15
.c14_pmevcntr_delta
[counter
];
1370 uint64_t overflow_mask
= pmevcntr_is_64_bit(env
, counter
) ?
1371 1ULL << 63 : 1ULL << 31;
1373 if (env
->cp15
.c14_pmevcntr
[counter
] & ~new_pmevcntr
& overflow_mask
) {
1374 env
->cp15
.c9_pmovsr
|= (1 << counter
);
1375 pmu_update_irq(env
);
1377 env
->cp15
.c14_pmevcntr
[counter
] = new_pmevcntr
;
1379 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1382 static void pmevcntr_op_finish(CPUARMState
*env
, uint8_t counter
)
1384 if (pmu_counter_enabled(env
, counter
)) {
1385 #ifndef CONFIG_USER_ONLY
1386 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1387 uint16_t event_idx
= supported_event_map
[event
];
1388 uint64_t delta
= -(env
->cp15
.c14_pmevcntr
[counter
] + 1);
1389 int64_t overflow_in
;
1391 if (!pmevcntr_is_64_bit(env
, counter
)) {
1392 delta
= (uint32_t)delta
;
1394 overflow_in
= pm_events
[event_idx
].ns_per_count(delta
);
1396 if (overflow_in
> 0) {
1397 int64_t overflow_at
;
1399 if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1400 overflow_in
, &overflow_at
)) {
1401 ARMCPU
*cpu
= env_archcpu(env
);
1402 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1407 env
->cp15
.c14_pmevcntr_delta
[counter
] -=
1408 env
->cp15
.c14_pmevcntr
[counter
];
1412 void pmu_op_start(CPUARMState
*env
)
1415 pmccntr_op_start(env
);
1416 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1417 pmevcntr_op_start(env
, i
);
1421 void pmu_op_finish(CPUARMState
*env
)
1424 pmccntr_op_finish(env
);
1425 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1426 pmevcntr_op_finish(env
, i
);
1430 void pmu_pre_el_change(ARMCPU
*cpu
, void *ignored
)
1432 pmu_op_start(&cpu
->env
);
1435 void pmu_post_el_change(ARMCPU
*cpu
, void *ignored
)
1437 pmu_op_finish(&cpu
->env
);
1440 void arm_pmu_timer_cb(void *opaque
)
1442 ARMCPU
*cpu
= opaque
;
1445 * Update all the counter values based on the current underlying counts,
1446 * triggering interrupts to be raised, if necessary. pmu_op_finish() also
1447 * has the effect of setting the cpu->pmu_timer to the next earliest time a
1448 * counter may expire.
1450 pmu_op_start(&cpu
->env
);
1451 pmu_op_finish(&cpu
->env
);
1454 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1459 if (value
& PMCRC
) {
1460 /* The counter has been reset */
1461 env
->cp15
.c15_ccnt
= 0;
1464 if (value
& PMCRP
) {
1466 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1467 env
->cp15
.c14_pmevcntr
[i
] = 0;
1471 env
->cp15
.c9_pmcr
&= ~PMCR_WRITABLE_MASK
;
1472 env
->cp15
.c9_pmcr
|= (value
& PMCR_WRITABLE_MASK
);
1477 static void pmswinc_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1481 uint64_t overflow_mask
, new_pmswinc
;
1483 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1484 /* Increment a counter's count iff: */
1485 if ((value
& (1 << i
)) && /* counter's bit is set */
1486 /* counter is enabled and not filtered */
1487 pmu_counter_enabled(env
, i
) &&
1488 /* counter is SW_INCR */
1489 (env
->cp15
.c14_pmevtyper
[i
] & PMXEVTYPER_EVTCOUNT
) == 0x0) {
1490 pmevcntr_op_start(env
, i
);
1493 * Detect if this write causes an overflow since we can't predict
1494 * PMSWINC overflows like we can for other events
1496 new_pmswinc
= env
->cp15
.c14_pmevcntr
[i
] + 1;
1498 overflow_mask
= pmevcntr_is_64_bit(env
, i
) ?
1499 1ULL << 63 : 1ULL << 31;
1501 if (env
->cp15
.c14_pmevcntr
[i
] & ~new_pmswinc
& overflow_mask
) {
1502 env
->cp15
.c9_pmovsr
|= (1 << i
);
1503 pmu_update_irq(env
);
1506 env
->cp15
.c14_pmevcntr
[i
] = new_pmswinc
;
1508 pmevcntr_op_finish(env
, i
);
1513 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1516 pmccntr_op_start(env
);
1517 ret
= env
->cp15
.c15_ccnt
;
1518 pmccntr_op_finish(env
);
1522 static void pmselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1526 * The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1527 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1528 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1531 env
->cp15
.c9_pmselr
= value
& 0x1f;
1534 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1537 pmccntr_op_start(env
);
1538 env
->cp15
.c15_ccnt
= value
;
1539 pmccntr_op_finish(env
);
1542 static void pmccntr_write32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1545 uint64_t cur_val
= pmccntr_read(env
, NULL
);
1547 pmccntr_write(env
, ri
, deposit64(cur_val
, 0, 32, value
));
1550 static void pmccfiltr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1553 pmccntr_op_start(env
);
1554 env
->cp15
.pmccfiltr_el0
= value
& PMCCFILTR_EL0
;
1555 pmccntr_op_finish(env
);
1558 static void pmccfiltr_write_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1561 pmccntr_op_start(env
);
1562 /* M is not accessible from AArch32 */
1563 env
->cp15
.pmccfiltr_el0
= (env
->cp15
.pmccfiltr_el0
& PMCCFILTR_M
) |
1564 (value
& PMCCFILTR
);
1565 pmccntr_op_finish(env
);
1568 static uint64_t pmccfiltr_read_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1570 /* M is not visible in AArch32 */
1571 return env
->cp15
.pmccfiltr_el0
& PMCCFILTR
;
1574 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1578 value
&= pmu_counter_mask(env
);
1579 env
->cp15
.c9_pmcnten
|= value
;
1583 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1587 value
&= pmu_counter_mask(env
);
1588 env
->cp15
.c9_pmcnten
&= ~value
;
1592 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1595 value
&= pmu_counter_mask(env
);
1596 env
->cp15
.c9_pmovsr
&= ~value
;
1597 pmu_update_irq(env
);
1600 static void pmovsset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1603 value
&= pmu_counter_mask(env
);
1604 env
->cp15
.c9_pmovsr
|= value
;
1605 pmu_update_irq(env
);
1608 static void pmevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1609 uint64_t value
, const uint8_t counter
)
1611 if (counter
== 31) {
1612 pmccfiltr_write(env
, ri
, value
);
1613 } else if (counter
< pmu_num_counters(env
)) {
1614 pmevcntr_op_start(env
, counter
);
1617 * If this counter's event type is changing, store the current
1618 * underlying count for the new type in c14_pmevcntr_delta[counter] so
1619 * pmevcntr_op_finish has the correct baseline when it converts back to
1622 uint16_t old_event
= env
->cp15
.c14_pmevtyper
[counter
] &
1623 PMXEVTYPER_EVTCOUNT
;
1624 uint16_t new_event
= value
& PMXEVTYPER_EVTCOUNT
;
1625 if (old_event
!= new_event
) {
1627 if (event_supported(new_event
)) {
1628 uint16_t event_idx
= supported_event_map
[new_event
];
1629 count
= pm_events
[event_idx
].get_count(env
);
1631 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1634 env
->cp15
.c14_pmevtyper
[counter
] = value
& PMXEVTYPER_MASK
;
1635 pmevcntr_op_finish(env
, counter
);
1638 * Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1639 * PMSELR value is equal to or greater than the number of implemented
1640 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1644 static uint64_t pmevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1645 const uint8_t counter
)
1647 if (counter
== 31) {
1648 return env
->cp15
.pmccfiltr_el0
;
1649 } else if (counter
< pmu_num_counters(env
)) {
1650 return env
->cp15
.c14_pmevtyper
[counter
];
1653 * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1654 * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write().
1660 static void pmevtyper_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1663 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1664 pmevtyper_write(env
, ri
, value
, counter
);
1667 static void pmevtyper_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1670 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1671 env
->cp15
.c14_pmevtyper
[counter
] = value
;
1674 * pmevtyper_rawwrite is called between a pair of pmu_op_start and
1675 * pmu_op_finish calls when loading saved state for a migration. Because
1676 * we're potentially updating the type of event here, the value written to
1677 * c14_pmevcntr_delta by the preceding pmu_op_start call may be for a
1678 * different counter type. Therefore, we need to set this value to the
1679 * current count for the counter type we're writing so that pmu_op_finish
1680 * has the correct count for its calculation.
1682 uint16_t event
= value
& PMXEVTYPER_EVTCOUNT
;
1683 if (event_supported(event
)) {
1684 uint16_t event_idx
= supported_event_map
[event
];
1685 env
->cp15
.c14_pmevcntr_delta
[counter
] =
1686 pm_events
[event_idx
].get_count(env
);
1690 static uint64_t pmevtyper_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1692 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1693 return pmevtyper_read(env
, ri
, counter
);
1696 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1699 pmevtyper_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1702 static uint64_t pmxevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1704 return pmevtyper_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1707 static void pmevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1708 uint64_t value
, uint8_t counter
)
1710 if (!cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1711 /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */
1712 value
&= MAKE_64BIT_MASK(0, 32);
1714 if (counter
< pmu_num_counters(env
)) {
1715 pmevcntr_op_start(env
, counter
);
1716 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1717 pmevcntr_op_finish(env
, counter
);
1720 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1721 * are CONSTRAINED UNPREDICTABLE.
1725 static uint64_t pmevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1728 if (counter
< pmu_num_counters(env
)) {
1730 pmevcntr_op_start(env
, counter
);
1731 ret
= env
->cp15
.c14_pmevcntr
[counter
];
1732 pmevcntr_op_finish(env
, counter
);
1733 if (!cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1734 /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */
1735 ret
&= MAKE_64BIT_MASK(0, 32);
1740 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1741 * are CONSTRAINED UNPREDICTABLE.
1747 static void pmevcntr_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1750 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1751 pmevcntr_write(env
, ri
, value
, counter
);
1754 static uint64_t pmevcntr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1756 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1757 return pmevcntr_read(env
, ri
, counter
);
1760 static void pmevcntr_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1763 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1764 assert(counter
< pmu_num_counters(env
));
1765 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1766 pmevcntr_write(env
, ri
, value
, counter
);
1769 static uint64_t pmevcntr_rawread(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1771 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1772 assert(counter
< pmu_num_counters(env
));
1773 return env
->cp15
.c14_pmevcntr
[counter
];
1776 static void pmxevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1779 pmevcntr_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1782 static uint64_t pmxevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1784 return pmevcntr_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1787 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1790 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1791 env
->cp15
.c9_pmuserenr
= value
& 0xf;
1793 env
->cp15
.c9_pmuserenr
= value
& 1;
1797 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1800 /* We have no event counters so only the C bit can be changed */
1801 value
&= pmu_counter_mask(env
);
1802 env
->cp15
.c9_pminten
|= value
;
1803 pmu_update_irq(env
);
1806 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1809 value
&= pmu_counter_mask(env
);
1810 env
->cp15
.c9_pminten
&= ~value
;
1811 pmu_update_irq(env
);
1814 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1818 * Note that even though the AArch64 view of this register has bits
1819 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
1820 * architectural requirements for bits which are RES0 only in some
1821 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
1822 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
1824 raw_write(env
, ri
, value
& ~0x1FULL
);
1827 static void scr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1829 /* Begin with base v8.0 state. */
1830 uint64_t valid_mask
= 0x3fff;
1831 ARMCPU
*cpu
= env_archcpu(env
);
1835 * Because SCR_EL3 is the "real" cpreg and SCR is the alias, reset always
1836 * passes the reginfo for SCR_EL3, which has type ARM_CP_STATE_AA64.
1837 * Instead, choose the format based on the mode of EL3.
1839 if (arm_el_is_aa64(env
, 3)) {
1840 value
|= SCR_FW
| SCR_AW
; /* RES1 */
1841 valid_mask
&= ~SCR_NET
; /* RES0 */
1843 if (!cpu_isar_feature(aa64_aa32_el1
, cpu
) &&
1844 !cpu_isar_feature(aa64_aa32_el2
, cpu
)) {
1845 value
|= SCR_RW
; /* RAO/WI */
1847 if (cpu_isar_feature(aa64_ras
, cpu
)) {
1848 valid_mask
|= SCR_TERR
;
1850 if (cpu_isar_feature(aa64_lor
, cpu
)) {
1851 valid_mask
|= SCR_TLOR
;
1853 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
1854 valid_mask
|= SCR_API
| SCR_APK
;
1856 if (cpu_isar_feature(aa64_sel2
, cpu
)) {
1857 valid_mask
|= SCR_EEL2
;
1858 } else if (cpu_isar_feature(aa64_rme
, cpu
)) {
1859 /* With RME and without SEL2, NS is RES1 (R_GSWWH, I_DJJQJ). */
1862 if (cpu_isar_feature(aa64_mte
, cpu
)) {
1863 valid_mask
|= SCR_ATA
;
1865 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
1866 valid_mask
|= SCR_ENSCXT
;
1868 if (cpu_isar_feature(aa64_doublefault
, cpu
)) {
1869 valid_mask
|= SCR_EASE
| SCR_NMEA
;
1871 if (cpu_isar_feature(aa64_sme
, cpu
)) {
1872 valid_mask
|= SCR_ENTP2
;
1874 if (cpu_isar_feature(aa64_hcx
, cpu
)) {
1875 valid_mask
|= SCR_HXEN
;
1877 if (cpu_isar_feature(aa64_fgt
, cpu
)) {
1878 valid_mask
|= SCR_FGTEN
;
1880 if (cpu_isar_feature(aa64_rme
, cpu
)) {
1881 valid_mask
|= SCR_NSE
| SCR_GPF
;
1884 valid_mask
&= ~(SCR_RW
| SCR_ST
);
1885 if (cpu_isar_feature(aa32_ras
, cpu
)) {
1886 valid_mask
|= SCR_TERR
;
1890 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1891 valid_mask
&= ~SCR_HCE
;
1894 * On ARMv7, SMD (or SCD as it is called in v7) is only
1895 * supported if EL2 exists. The bit is UNK/SBZP when
1896 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
1897 * when EL2 is unavailable.
1898 * On ARMv8, this bit is always available.
1900 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1901 !arm_feature(env
, ARM_FEATURE_V8
)) {
1902 valid_mask
&= ~SCR_SMD
;
1906 /* Clear all-context RES0 bits. */
1907 value
&= valid_mask
;
1908 changed
= env
->cp15
.scr_el3
^ value
;
1909 env
->cp15
.scr_el3
= value
;
1912 * If SCR_EL3.{NS,NSE} changes, i.e. change of security state,
1913 * we must invalidate all TLBs below EL3.
1915 if (changed
& (SCR_NS
| SCR_NSE
)) {
1916 tlb_flush_by_mmuidx(env_cpu(env
), (ARMMMUIdxBit_E10_0
|
1917 ARMMMUIdxBit_E20_0
|
1918 ARMMMUIdxBit_E10_1
|
1919 ARMMMUIdxBit_E20_2
|
1920 ARMMMUIdxBit_E10_1_PAN
|
1921 ARMMMUIdxBit_E20_2_PAN
|
1926 static void scr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1929 * scr_write will set the RES1 bits on an AArch64-only CPU.
1930 * The reset value will be 0x30 on an AArch64-only CPU and 0 otherwise.
1932 scr_write(env
, ri
, 0);
1935 static CPAccessResult
access_tid4(CPUARMState
*env
,
1936 const ARMCPRegInfo
*ri
,
1939 if (arm_current_el(env
) == 1 &&
1940 (arm_hcr_el2_eff(env
) & (HCR_TID2
| HCR_TID4
))) {
1941 return CP_ACCESS_TRAP_EL2
;
1944 return CP_ACCESS_OK
;
1947 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1949 ARMCPU
*cpu
= env_archcpu(env
);
1952 * Acquire the CSSELR index from the bank corresponding to the CCSIDR
1955 uint32_t index
= A32_BANKED_REG_GET(env
, csselr
,
1956 ri
->secure
& ARM_CP_SECSTATE_S
);
1958 return cpu
->ccsidr
[index
];
1961 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1964 raw_write(env
, ri
, value
& 0xf);
1967 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1969 CPUState
*cs
= env_cpu(env
);
1970 bool el1
= arm_current_el(env
) == 1;
1971 uint64_t hcr_el2
= el1
? arm_hcr_el2_eff(env
) : 0;
1974 if (hcr_el2
& HCR_IMO
) {
1975 if (cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) {
1979 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
1984 if (hcr_el2
& HCR_FMO
) {
1985 if (cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) {
1989 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
1994 if (hcr_el2
& HCR_AMO
) {
1995 if (cs
->interrupt_request
& CPU_INTERRUPT_VSERR
) {
2003 static CPAccessResult
access_aa64_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2006 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID1
)) {
2007 return CP_ACCESS_TRAP_EL2
;
2010 return CP_ACCESS_OK
;
2013 static CPAccessResult
access_aa32_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2016 if (arm_feature(env
, ARM_FEATURE_V8
)) {
2017 return access_aa64_tid1(env
, ri
, isread
);
2020 return CP_ACCESS_OK
;
2023 static const ARMCPRegInfo v7_cp_reginfo
[] = {
2024 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
2025 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
2026 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2028 * Performance monitors are implementation defined in v7,
2029 * but with an ARM recommended set of registers, which we
2032 * Performance registers fall into three categories:
2033 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
2034 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
2035 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
2036 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
2037 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
2039 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
2040 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2041 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
2042 .writefn
= pmcntenset_write
,
2043 .accessfn
= pmreg_access
,
2045 .raw_writefn
= raw_write
},
2046 { .name
= "PMCNTENSET_EL0", .state
= ARM_CP_STATE_AA64
, .type
= ARM_CP_IO
,
2047 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 1,
2048 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2050 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
), .resetvalue
= 0,
2051 .writefn
= pmcntenset_write
, .raw_writefn
= raw_write
},
2052 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
2054 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
2055 .accessfn
= pmreg_access
,
2057 .writefn
= pmcntenclr_write
,
2058 .type
= ARM_CP_ALIAS
| ARM_CP_IO
},
2059 { .name
= "PMCNTENCLR_EL0", .state
= ARM_CP_STATE_AA64
,
2060 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 2,
2061 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2063 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2064 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
2065 .writefn
= pmcntenclr_write
},
2066 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
2067 .access
= PL0_RW
, .type
= ARM_CP_IO
,
2068 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2069 .accessfn
= pmreg_access
,
2071 .writefn
= pmovsr_write
,
2072 .raw_writefn
= raw_write
},
2073 { .name
= "PMOVSCLR_EL0", .state
= ARM_CP_STATE_AA64
,
2074 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 3,
2075 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2077 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2078 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2079 .writefn
= pmovsr_write
,
2080 .raw_writefn
= raw_write
},
2081 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
2082 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2083 .fgt
= FGT_PMSWINC_EL0
,
2084 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2085 .writefn
= pmswinc_write
},
2086 { .name
= "PMSWINC_EL0", .state
= ARM_CP_STATE_AA64
,
2087 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 4,
2088 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2089 .fgt
= FGT_PMSWINC_EL0
,
2090 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2091 .writefn
= pmswinc_write
},
2092 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
2093 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
2094 .fgt
= FGT_PMSELR_EL0
,
2095 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmselr
),
2096 .accessfn
= pmreg_access_selr
, .writefn
= pmselr_write
,
2097 .raw_writefn
= raw_write
},
2098 { .name
= "PMSELR_EL0", .state
= ARM_CP_STATE_AA64
,
2099 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 5,
2100 .access
= PL0_RW
, .accessfn
= pmreg_access_selr
,
2101 .fgt
= FGT_PMSELR_EL0
,
2102 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmselr
),
2103 .writefn
= pmselr_write
, .raw_writefn
= raw_write
, },
2104 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
2105 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2106 .fgt
= FGT_PMCCNTR_EL0
,
2107 .readfn
= pmccntr_read
, .writefn
= pmccntr_write32
,
2108 .accessfn
= pmreg_access_ccntr
},
2109 { .name
= "PMCCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2110 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 0,
2111 .access
= PL0_RW
, .accessfn
= pmreg_access_ccntr
,
2112 .fgt
= FGT_PMCCNTR_EL0
,
2114 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ccnt
),
2115 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
,
2116 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
, },
2117 { .name
= "PMCCFILTR", .cp
= 15, .opc1
= 0, .crn
= 14, .crm
= 15, .opc2
= 7,
2118 .writefn
= pmccfiltr_write_a32
, .readfn
= pmccfiltr_read_a32
,
2119 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2120 .fgt
= FGT_PMCCFILTR_EL0
,
2121 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2123 { .name
= "PMCCFILTR_EL0", .state
= ARM_CP_STATE_AA64
,
2124 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 15, .opc2
= 7,
2125 .writefn
= pmccfiltr_write
, .raw_writefn
= raw_write
,
2126 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2127 .fgt
= FGT_PMCCFILTR_EL0
,
2129 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmccfiltr_el0
),
2131 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
2132 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2133 .accessfn
= pmreg_access
,
2134 .fgt
= FGT_PMEVTYPERN_EL0
,
2135 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2136 { .name
= "PMXEVTYPER_EL0", .state
= ARM_CP_STATE_AA64
,
2137 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 1,
2138 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2139 .accessfn
= pmreg_access
,
2140 .fgt
= FGT_PMEVTYPERN_EL0
,
2141 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2142 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
2143 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2144 .accessfn
= pmreg_access_xevcntr
,
2145 .fgt
= FGT_PMEVCNTRN_EL0
,
2146 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2147 { .name
= "PMXEVCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2148 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 2,
2149 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2150 .accessfn
= pmreg_access_xevcntr
,
2151 .fgt
= FGT_PMEVCNTRN_EL0
,
2152 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2153 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
2154 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
,
2155 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmuserenr
),
2157 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2158 { .name
= "PMUSERENR_EL0", .state
= ARM_CP_STATE_AA64
,
2159 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 0,
2160 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
2161 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
2163 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2164 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
2165 .access
= PL1_RW
, .accessfn
= access_tpm
,
2167 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2168 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pminten
),
2170 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
2171 { .name
= "PMINTENSET_EL1", .state
= ARM_CP_STATE_AA64
,
2172 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 1,
2173 .access
= PL1_RW
, .accessfn
= access_tpm
,
2176 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2177 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
,
2178 .resetvalue
= 0x0 },
2179 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
2180 .access
= PL1_RW
, .accessfn
= access_tpm
,
2182 .type
= ARM_CP_ALIAS
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2183 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2184 .writefn
= pmintenclr_write
, },
2185 { .name
= "PMINTENCLR_EL1", .state
= ARM_CP_STATE_AA64
,
2186 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 2,
2187 .access
= PL1_RW
, .accessfn
= access_tpm
,
2189 .type
= ARM_CP_ALIAS
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2190 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2191 .writefn
= pmintenclr_write
},
2192 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
2193 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
2195 .accessfn
= access_tid4
,
2196 .fgt
= FGT_CCSIDR_EL1
,
2197 .readfn
= ccsidr_read
, .type
= ARM_CP_NO_RAW
},
2198 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
2199 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
2201 .accessfn
= access_tid4
,
2202 .fgt
= FGT_CSSELR_EL1
,
2203 .writefn
= csselr_write
, .resetvalue
= 0,
2204 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.csselr_s
),
2205 offsetof(CPUARMState
, cp15
.csselr_ns
) } },
2207 * Auxiliary ID register: this actually has an IMPDEF value but for now
2208 * just RAZ for all cores:
2210 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
2211 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
2212 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2213 .accessfn
= access_aa64_tid1
,
2214 .fgt
= FGT_AIDR_EL1
,
2217 * Auxiliary fault status registers: these also are IMPDEF, and we
2218 * choose to RAZ/WI for all cores.
2220 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2221 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
2222 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2223 .fgt
= FGT_AFSR0_EL1
,
2224 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2225 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2226 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
2227 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2228 .fgt
= FGT_AFSR1_EL1
,
2229 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2231 * MAIR can just read-as-written because we don't implement caches
2232 * and so don't need to care about memory attributes.
2234 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
2235 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2236 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2237 .fgt
= FGT_MAIR_EL1
,
2238 .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[1]),
2240 { .name
= "MAIR_EL3", .state
= ARM_CP_STATE_AA64
,
2241 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 2, .opc2
= 0,
2242 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[3]),
2245 * For non-long-descriptor page tables these are PRRR and NMRR;
2246 * regardless they still act as reads-as-written for QEMU.
2249 * MAIR0/1 are defined separately from their 64-bit counterpart which
2250 * allows them to assign the correct fieldoffset based on the endianness
2251 * handled in the field definitions.
2253 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
,
2254 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2255 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2256 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair0_s
),
2257 offsetof(CPUARMState
, cp15
.mair0_ns
) },
2258 .resetfn
= arm_cp_reset_ignore
},
2259 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
,
2260 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1,
2261 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2262 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair1_s
),
2263 offsetof(CPUARMState
, cp15
.mair1_ns
) },
2264 .resetfn
= arm_cp_reset_ignore
},
2265 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
2266 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
2268 .type
= ARM_CP_NO_RAW
, .access
= PL1_R
, .readfn
= isr_read
},
2269 /* 32 bit ITLB invalidates */
2270 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
2271 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2272 .writefn
= tlbiall_write
},
2273 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
2274 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2275 .writefn
= tlbimva_write
},
2276 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
2277 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2278 .writefn
= tlbiasid_write
},
2279 /* 32 bit DTLB invalidates */
2280 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
2281 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2282 .writefn
= tlbiall_write
},
2283 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
2284 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2285 .writefn
= tlbimva_write
},
2286 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
2287 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2288 .writefn
= tlbiasid_write
},
2289 /* 32 bit TLB invalidates */
2290 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
2291 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2292 .writefn
= tlbiall_write
},
2293 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
2294 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2295 .writefn
= tlbimva_write
},
2296 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
2297 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2298 .writefn
= tlbiasid_write
},
2299 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
2300 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2301 .writefn
= tlbimvaa_write
},
2304 static const ARMCPRegInfo v7mp_cp_reginfo
[] = {
2305 /* 32 bit TLB invalidates, Inner Shareable */
2306 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
2307 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2308 .writefn
= tlbiall_is_write
},
2309 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
2310 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2311 .writefn
= tlbimva_is_write
},
2312 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
2313 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2314 .writefn
= tlbiasid_is_write
},
2315 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
2316 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2317 .writefn
= tlbimvaa_is_write
},
2320 static const ARMCPRegInfo pmovsset_cp_reginfo
[] = {
2321 /* PMOVSSET is not implemented in v7 before v7ve */
2322 { .name
= "PMOVSSET", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 3,
2323 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2325 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2326 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2327 .writefn
= pmovsset_write
,
2328 .raw_writefn
= raw_write
},
2329 { .name
= "PMOVSSET_EL0", .state
= ARM_CP_STATE_AA64
,
2330 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 3,
2331 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2333 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2334 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2335 .writefn
= pmovsset_write
,
2336 .raw_writefn
= raw_write
},
2339 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2346 static CPAccessResult
teecr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2350 * HSTR.TTEE only exists in v7A, not v8A, but v8A doesn't have T2EE
2351 * at all, so we don't need to check whether we're v8A.
2353 if (arm_current_el(env
) < 2 && !arm_is_secure_below_el3(env
) &&
2354 (env
->cp15
.hstr_el2
& HSTR_TTEE
)) {
2355 return CP_ACCESS_TRAP_EL2
;
2357 return CP_ACCESS_OK
;
2360 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2363 if (arm_current_el(env
) == 0 && (env
->teecr
& 1)) {
2364 return CP_ACCESS_TRAP
;
2366 return teecr_access(env
, ri
, isread
);
2369 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
2370 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
2371 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
2373 .writefn
= teecr_write
, .accessfn
= teecr_access
},
2374 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
2375 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
2376 .accessfn
= teehbr_access
, .resetvalue
= 0 },
2379 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
2380 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
2381 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
2383 .fgt
= FGT_TPIDR_EL0
,
2384 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[0]), .resetvalue
= 0 },
2385 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
2387 .fgt
= FGT_TPIDR_EL0
,
2388 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrurw_s
),
2389 offsetoflow32(CPUARMState
, cp15
.tpidrurw_ns
) },
2390 .resetfn
= arm_cp_reset_ignore
},
2391 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
2392 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
2393 .access
= PL0_R
| PL1_W
,
2394 .fgt
= FGT_TPIDRRO_EL0
,
2395 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el
[0]),
2397 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
2398 .access
= PL0_R
| PL1_W
,
2399 .fgt
= FGT_TPIDRRO_EL0
,
2400 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidruro_s
),
2401 offsetoflow32(CPUARMState
, cp15
.tpidruro_ns
) },
2402 .resetfn
= arm_cp_reset_ignore
},
2403 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_AA64
,
2404 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
2406 .fgt
= FGT_TPIDR_EL1
,
2407 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[1]), .resetvalue
= 0 },
2408 { .name
= "TPIDRPRW", .opc1
= 0, .cp
= 15, .crn
= 13, .crm
= 0, .opc2
= 4,
2410 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrprw_s
),
2411 offsetoflow32(CPUARMState
, cp15
.tpidrprw_ns
) },
2415 #ifndef CONFIG_USER_ONLY
2417 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2421 * CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
2422 * Writable only at the highest implemented exception level.
2424 int el
= arm_current_el(env
);
2430 hcr
= arm_hcr_el2_eff(env
);
2431 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2432 cntkctl
= env
->cp15
.cnthctl_el2
;
2434 cntkctl
= env
->cp15
.c14_cntkctl
;
2436 if (!extract32(cntkctl
, 0, 2)) {
2437 return CP_ACCESS_TRAP
;
2441 if (!isread
&& ri
->state
== ARM_CP_STATE_AA32
&&
2442 arm_is_secure_below_el3(env
)) {
2443 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
2444 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2452 if (!isread
&& el
< arm_highest_el(env
)) {
2453 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2456 return CP_ACCESS_OK
;
2459 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
,
2462 unsigned int cur_el
= arm_current_el(env
);
2463 bool has_el2
= arm_is_el2_enabled(env
);
2464 uint64_t hcr
= arm_hcr_el2_eff(env
);
2468 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]CTEN. */
2469 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2470 return (extract32(env
->cp15
.cnthctl_el2
, timeridx
, 1)
2471 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2474 /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */
2475 if (!extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
2476 return CP_ACCESS_TRAP
;
2480 /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */
2481 if (has_el2
&& timeridx
== GTIMER_PHYS
&&
2483 ? !extract32(env
->cp15
.cnthctl_el2
, 10, 1)
2484 : !extract32(env
->cp15
.cnthctl_el2
, 0, 1))) {
2485 return CP_ACCESS_TRAP_EL2
;
2489 return CP_ACCESS_OK
;
2492 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
,
2495 unsigned int cur_el
= arm_current_el(env
);
2496 bool has_el2
= arm_is_el2_enabled(env
);
2497 uint64_t hcr
= arm_hcr_el2_eff(env
);
2501 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2502 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */
2503 return (extract32(env
->cp15
.cnthctl_el2
, 9 - timeridx
, 1)
2504 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2508 * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from
2509 * EL0 if EL0[PV]TEN is zero.
2511 if (!extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
2512 return CP_ACCESS_TRAP
;
2517 if (has_el2
&& timeridx
== GTIMER_PHYS
) {
2518 if (hcr
& HCR_E2H
) {
2519 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */
2520 if (!extract32(env
->cp15
.cnthctl_el2
, 11, 1)) {
2521 return CP_ACCESS_TRAP_EL2
;
2524 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2525 if (!extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2526 return CP_ACCESS_TRAP_EL2
;
2532 return CP_ACCESS_OK
;
2535 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
2536 const ARMCPRegInfo
*ri
,
2539 return gt_counter_access(env
, GTIMER_PHYS
, isread
);
2542 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
2543 const ARMCPRegInfo
*ri
,
2546 return gt_counter_access(env
, GTIMER_VIRT
, isread
);
2549 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2552 return gt_timer_access(env
, GTIMER_PHYS
, isread
);
2555 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2558 return gt_timer_access(env
, GTIMER_VIRT
, isread
);
2561 static CPAccessResult
gt_stimer_access(CPUARMState
*env
,
2562 const ARMCPRegInfo
*ri
,
2566 * The AArch64 register view of the secure physical timer is
2567 * always accessible from EL3, and configurably accessible from
2570 switch (arm_current_el(env
)) {
2572 if (!arm_is_secure(env
)) {
2573 return CP_ACCESS_TRAP
;
2575 if (!(env
->cp15
.scr_el3
& SCR_ST
)) {
2576 return CP_ACCESS_TRAP_EL3
;
2578 return CP_ACCESS_OK
;
2581 return CP_ACCESS_TRAP
;
2583 return CP_ACCESS_OK
;
2585 g_assert_not_reached();
2589 static uint64_t gt_get_countervalue(CPUARMState
*env
)
2591 ARMCPU
*cpu
= env_archcpu(env
);
2593 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / gt_cntfrq_period_ns(cpu
);
2596 static void gt_update_irq(ARMCPU
*cpu
, int timeridx
)
2598 CPUARMState
*env
= &cpu
->env
;
2599 uint64_t cnthctl
= env
->cp15
.cnthctl_el2
;
2600 ARMSecuritySpace ss
= arm_security_space(env
);
2601 /* ISTATUS && !IMASK */
2602 int irqstate
= (env
->cp15
.c14_timer
[timeridx
].ctl
& 6) == 4;
2605 * If bit CNTHCTL_EL2.CNT[VP]MASK is set, it overrides IMASK.
2606 * It is RES0 in Secure and NonSecure state.
2608 if ((ss
== ARMSS_Root
|| ss
== ARMSS_Realm
) &&
2609 ((timeridx
== GTIMER_VIRT
&& (cnthctl
& CNTHCTL_CNTVMASK
)) ||
2610 (timeridx
== GTIMER_PHYS
&& (cnthctl
& CNTHCTL_CNTPMASK
)))) {
2614 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2615 trace_arm_gt_update_irq(timeridx
, irqstate
);
2618 void gt_rme_post_el_change(ARMCPU
*cpu
, void *ignored
)
2621 * Changing security state between Root and Secure/NonSecure, which may
2622 * happen when switching EL, can change the effective value of CNTHCTL_EL2
2623 * mask bits. Update the IRQ state accordingly.
2625 gt_update_irq(cpu
, GTIMER_VIRT
);
2626 gt_update_irq(cpu
, GTIMER_PHYS
);
2629 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
2631 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
2635 * Timer enabled: calculate and set current ISTATUS, irq, and
2636 * reset timer to when ISTATUS next has to change
2638 uint64_t offset
= timeridx
== GTIMER_VIRT
?
2639 cpu
->env
.cp15
.cntvoff_el2
: 0;
2640 uint64_t count
= gt_get_countervalue(&cpu
->env
);
2641 /* Note that this must be unsigned 64 bit arithmetic: */
2642 int istatus
= count
- offset
>= gt
->cval
;
2645 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
2648 /* Next transition is when count rolls back over to zero */
2649 nexttick
= UINT64_MAX
;
2651 /* Next transition is when we hit cval */
2652 nexttick
= gt
->cval
+ offset
;
2655 * Note that the desired next expiry time might be beyond the
2656 * signed-64-bit range of a QEMUTimer -- in this case we just
2657 * set the timer for as far in the future as possible. When the
2658 * timer expires we will reset the timer for any remaining period.
2660 if (nexttick
> INT64_MAX
/ gt_cntfrq_period_ns(cpu
)) {
2661 timer_mod_ns(cpu
->gt_timer
[timeridx
], INT64_MAX
);
2663 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
2665 trace_arm_gt_recalc(timeridx
, nexttick
);
2667 /* Timer disabled: ISTATUS and timer output always clear */
2669 timer_del(cpu
->gt_timer
[timeridx
]);
2670 trace_arm_gt_recalc_disabled(timeridx
);
2672 gt_update_irq(cpu
, timeridx
);
2675 static void gt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2678 ARMCPU
*cpu
= env_archcpu(env
);
2680 timer_del(cpu
->gt_timer
[timeridx
]);
2683 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2685 return gt_get_countervalue(env
);
2688 static uint64_t gt_virt_cnt_offset(CPUARMState
*env
)
2692 switch (arm_current_el(env
)) {
2694 hcr
= arm_hcr_el2_eff(env
);
2695 if (hcr
& HCR_E2H
) {
2700 hcr
= arm_hcr_el2_eff(env
);
2701 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2707 return env
->cp15
.cntvoff_el2
;
2710 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2712 return gt_get_countervalue(env
) - gt_virt_cnt_offset(env
);
2715 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2719 trace_arm_gt_cval_write(timeridx
, value
);
2720 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
2721 gt_recalc_timer(env_archcpu(env
), timeridx
);
2724 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2727 uint64_t offset
= 0;
2731 case GTIMER_HYPVIRT
:
2732 offset
= gt_virt_cnt_offset(env
);
2736 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
2737 (gt_get_countervalue(env
) - offset
));
2740 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2744 uint64_t offset
= 0;
2748 case GTIMER_HYPVIRT
:
2749 offset
= gt_virt_cnt_offset(env
);
2753 trace_arm_gt_tval_write(timeridx
, value
);
2754 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) - offset
+
2755 sextract64(value
, 0, 32);
2756 gt_recalc_timer(env_archcpu(env
), timeridx
);
2759 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2763 ARMCPU
*cpu
= env_archcpu(env
);
2764 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
2766 trace_arm_gt_ctl_write(timeridx
, value
);
2767 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
2768 if ((oldval
^ value
) & 1) {
2769 /* Enable toggled */
2770 gt_recalc_timer(cpu
, timeridx
);
2771 } else if ((oldval
^ value
) & 2) {
2773 * IMASK toggled: don't need to recalculate,
2774 * just set the interrupt line based on ISTATUS
2776 trace_arm_gt_imask_toggle(timeridx
);
2777 gt_update_irq(cpu
, timeridx
);
2781 static void gt_phys_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2783 gt_timer_reset(env
, ri
, GTIMER_PHYS
);
2786 static void gt_phys_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2789 gt_cval_write(env
, ri
, GTIMER_PHYS
, value
);
2792 static uint64_t gt_phys_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2794 return gt_tval_read(env
, ri
, GTIMER_PHYS
);
2797 static void gt_phys_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2800 gt_tval_write(env
, ri
, GTIMER_PHYS
, value
);
2803 static void gt_phys_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2806 gt_ctl_write(env
, ri
, GTIMER_PHYS
, value
);
2809 static int gt_phys_redir_timeridx(CPUARMState
*env
)
2811 switch (arm_mmu_idx(env
)) {
2812 case ARMMMUIdx_E20_0
:
2813 case ARMMMUIdx_E20_2
:
2814 case ARMMMUIdx_E20_2_PAN
:
2821 static int gt_virt_redir_timeridx(CPUARMState
*env
)
2823 switch (arm_mmu_idx(env
)) {
2824 case ARMMMUIdx_E20_0
:
2825 case ARMMMUIdx_E20_2
:
2826 case ARMMMUIdx_E20_2_PAN
:
2827 return GTIMER_HYPVIRT
;
2833 static uint64_t gt_phys_redir_cval_read(CPUARMState
*env
,
2834 const ARMCPRegInfo
*ri
)
2836 int timeridx
= gt_phys_redir_timeridx(env
);
2837 return env
->cp15
.c14_timer
[timeridx
].cval
;
2840 static void gt_phys_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2843 int timeridx
= gt_phys_redir_timeridx(env
);
2844 gt_cval_write(env
, ri
, timeridx
, value
);
2847 static uint64_t gt_phys_redir_tval_read(CPUARMState
*env
,
2848 const ARMCPRegInfo
*ri
)
2850 int timeridx
= gt_phys_redir_timeridx(env
);
2851 return gt_tval_read(env
, ri
, timeridx
);
2854 static void gt_phys_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2857 int timeridx
= gt_phys_redir_timeridx(env
);
2858 gt_tval_write(env
, ri
, timeridx
, value
);
2861 static uint64_t gt_phys_redir_ctl_read(CPUARMState
*env
,
2862 const ARMCPRegInfo
*ri
)
2864 int timeridx
= gt_phys_redir_timeridx(env
);
2865 return env
->cp15
.c14_timer
[timeridx
].ctl
;
2868 static void gt_phys_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2871 int timeridx
= gt_phys_redir_timeridx(env
);
2872 gt_ctl_write(env
, ri
, timeridx
, value
);
2875 static void gt_virt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2877 gt_timer_reset(env
, ri
, GTIMER_VIRT
);
2880 static void gt_virt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2883 gt_cval_write(env
, ri
, GTIMER_VIRT
, value
);
2886 static uint64_t gt_virt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2888 return gt_tval_read(env
, ri
, GTIMER_VIRT
);
2891 static void gt_virt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2894 gt_tval_write(env
, ri
, GTIMER_VIRT
, value
);
2897 static void gt_virt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2900 gt_ctl_write(env
, ri
, GTIMER_VIRT
, value
);
2903 static void gt_cnthctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2906 ARMCPU
*cpu
= env_archcpu(env
);
2907 uint32_t oldval
= env
->cp15
.cnthctl_el2
;
2909 raw_write(env
, ri
, value
);
2911 if ((oldval
^ value
) & CNTHCTL_CNTVMASK
) {
2912 gt_update_irq(cpu
, GTIMER_VIRT
);
2913 } else if ((oldval
^ value
) & CNTHCTL_CNTPMASK
) {
2914 gt_update_irq(cpu
, GTIMER_PHYS
);
2918 static void gt_cntvoff_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2921 ARMCPU
*cpu
= env_archcpu(env
);
2923 trace_arm_gt_cntvoff_write(value
);
2924 raw_write(env
, ri
, value
);
2925 gt_recalc_timer(cpu
, GTIMER_VIRT
);
2928 static uint64_t gt_virt_redir_cval_read(CPUARMState
*env
,
2929 const ARMCPRegInfo
*ri
)
2931 int timeridx
= gt_virt_redir_timeridx(env
);
2932 return env
->cp15
.c14_timer
[timeridx
].cval
;
2935 static void gt_virt_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2938 int timeridx
= gt_virt_redir_timeridx(env
);
2939 gt_cval_write(env
, ri
, timeridx
, value
);
2942 static uint64_t gt_virt_redir_tval_read(CPUARMState
*env
,
2943 const ARMCPRegInfo
*ri
)
2945 int timeridx
= gt_virt_redir_timeridx(env
);
2946 return gt_tval_read(env
, ri
, timeridx
);
2949 static void gt_virt_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2952 int timeridx
= gt_virt_redir_timeridx(env
);
2953 gt_tval_write(env
, ri
, timeridx
, value
);
2956 static uint64_t gt_virt_redir_ctl_read(CPUARMState
*env
,
2957 const ARMCPRegInfo
*ri
)
2959 int timeridx
= gt_virt_redir_timeridx(env
);
2960 return env
->cp15
.c14_timer
[timeridx
].ctl
;
2963 static void gt_virt_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2966 int timeridx
= gt_virt_redir_timeridx(env
);
2967 gt_ctl_write(env
, ri
, timeridx
, value
);
2970 static void gt_hyp_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2972 gt_timer_reset(env
, ri
, GTIMER_HYP
);
2975 static void gt_hyp_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2978 gt_cval_write(env
, ri
, GTIMER_HYP
, value
);
2981 static uint64_t gt_hyp_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2983 return gt_tval_read(env
, ri
, GTIMER_HYP
);
2986 static void gt_hyp_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2989 gt_tval_write(env
, ri
, GTIMER_HYP
, value
);
2992 static void gt_hyp_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2995 gt_ctl_write(env
, ri
, GTIMER_HYP
, value
);
2998 static void gt_sec_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3000 gt_timer_reset(env
, ri
, GTIMER_SEC
);
3003 static void gt_sec_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3006 gt_cval_write(env
, ri
, GTIMER_SEC
, value
);
3009 static uint64_t gt_sec_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3011 return gt_tval_read(env
, ri
, GTIMER_SEC
);
3014 static void gt_sec_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3017 gt_tval_write(env
, ri
, GTIMER_SEC
, value
);
3020 static void gt_sec_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3023 gt_ctl_write(env
, ri
, GTIMER_SEC
, value
);
3026 static void gt_hv_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3028 gt_timer_reset(env
, ri
, GTIMER_HYPVIRT
);
3031 static void gt_hv_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3034 gt_cval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3037 static uint64_t gt_hv_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3039 return gt_tval_read(env
, ri
, GTIMER_HYPVIRT
);
3042 static void gt_hv_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3045 gt_tval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3048 static void gt_hv_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3051 gt_ctl_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3054 void arm_gt_ptimer_cb(void *opaque
)
3056 ARMCPU
*cpu
= opaque
;
3058 gt_recalc_timer(cpu
, GTIMER_PHYS
);
3061 void arm_gt_vtimer_cb(void *opaque
)
3063 ARMCPU
*cpu
= opaque
;
3065 gt_recalc_timer(cpu
, GTIMER_VIRT
);
3068 void arm_gt_htimer_cb(void *opaque
)
3070 ARMCPU
*cpu
= opaque
;
3072 gt_recalc_timer(cpu
, GTIMER_HYP
);
3075 void arm_gt_stimer_cb(void *opaque
)
3077 ARMCPU
*cpu
= opaque
;
3079 gt_recalc_timer(cpu
, GTIMER_SEC
);
3082 void arm_gt_hvtimer_cb(void *opaque
)
3084 ARMCPU
*cpu
= opaque
;
3086 gt_recalc_timer(cpu
, GTIMER_HYPVIRT
);
3089 static void arm_gt_cntfrq_reset(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
3091 ARMCPU
*cpu
= env_archcpu(env
);
3093 cpu
->env
.cp15
.c14_cntfrq
= cpu
->gt_cntfrq_hz
;
3096 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
3098 * Note that CNTFRQ is purely reads-as-written for the benefit
3099 * of software; writing it doesn't actually change the timer frequency.
3100 * Our reset value matches the fixed frequency we implement the timer at.
3102 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
3103 .type
= ARM_CP_ALIAS
,
3104 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
3105 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
3107 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
3108 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
3109 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
3110 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
3111 .resetfn
= arm_gt_cntfrq_reset
,
3113 /* overall control: mostly access permissions */
3114 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
3115 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
3117 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
3120 /* per-timer control */
3121 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
3122 .secure
= ARM_CP_SECSTATE_NS
,
3123 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3124 .accessfn
= gt_ptimer_access
,
3125 .fieldoffset
= offsetoflow32(CPUARMState
,
3126 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
3127 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
3128 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
3130 { .name
= "CNTP_CTL_S",
3131 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
3132 .secure
= ARM_CP_SECSTATE_S
,
3133 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3134 .accessfn
= gt_ptimer_access
,
3135 .fieldoffset
= offsetoflow32(CPUARMState
,
3136 cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3137 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3139 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
3140 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
3141 .type
= ARM_CP_IO
, .access
= PL0_RW
,
3142 .accessfn
= gt_ptimer_access
,
3143 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
3145 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
3146 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
3148 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
3149 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3150 .accessfn
= gt_vtimer_access
,
3151 .fieldoffset
= offsetoflow32(CPUARMState
,
3152 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
3153 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
3154 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
3156 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
3157 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
3158 .type
= ARM_CP_IO
, .access
= PL0_RW
,
3159 .accessfn
= gt_vtimer_access
,
3160 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
3162 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
3163 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
3165 /* TimerValue views: a 32 bit downcounting view of the underlying state */
3166 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
3167 .secure
= ARM_CP_SECSTATE_NS
,
3168 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3169 .accessfn
= gt_ptimer_access
,
3170 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
3172 { .name
= "CNTP_TVAL_S",
3173 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
3174 .secure
= ARM_CP_SECSTATE_S
,
3175 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3176 .accessfn
= gt_ptimer_access
,
3177 .readfn
= gt_sec_tval_read
, .writefn
= gt_sec_tval_write
,
3179 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3180 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
3181 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3182 .accessfn
= gt_ptimer_access
, .resetfn
= gt_phys_timer_reset
,
3183 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
3185 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
3186 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3187 .accessfn
= gt_vtimer_access
,
3188 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
3190 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3191 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
3192 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3193 .accessfn
= gt_vtimer_access
, .resetfn
= gt_virt_timer_reset
,
3194 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
3196 /* The counter itself */
3197 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
3198 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3199 .accessfn
= gt_pct_access
,
3200 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3202 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
3203 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
3204 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3205 .accessfn
= gt_pct_access
, .readfn
= gt_cnt_read
,
3207 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
3208 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3209 .accessfn
= gt_vct_access
,
3210 .readfn
= gt_virt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3212 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3213 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3214 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3215 .accessfn
= gt_vct_access
, .readfn
= gt_virt_cnt_read
,
3217 /* Comparison value, indicating when the timer goes off */
3218 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
3219 .secure
= ARM_CP_SECSTATE_NS
,
3221 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3222 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3223 .accessfn
= gt_ptimer_access
,
3224 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3225 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3227 { .name
= "CNTP_CVAL_S", .cp
= 15, .crm
= 14, .opc1
= 2,
3228 .secure
= ARM_CP_SECSTATE_S
,
3230 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3231 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3232 .accessfn
= gt_ptimer_access
,
3233 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3235 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3236 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
3239 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3240 .resetvalue
= 0, .accessfn
= gt_ptimer_access
,
3241 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3242 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3244 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
3246 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3247 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3248 .accessfn
= gt_vtimer_access
,
3249 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3250 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3252 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3253 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
3256 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3257 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
3258 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3259 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3262 * Secure timer -- this is actually restricted to only EL3
3263 * and configurably Secure-EL1 via the accessfn.
3265 { .name
= "CNTPS_TVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3266 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 0,
3267 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
,
3268 .accessfn
= gt_stimer_access
,
3269 .readfn
= gt_sec_tval_read
,
3270 .writefn
= gt_sec_tval_write
,
3271 .resetfn
= gt_sec_timer_reset
,
3273 { .name
= "CNTPS_CTL_EL1", .state
= ARM_CP_STATE_AA64
,
3274 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 1,
3275 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3276 .accessfn
= gt_stimer_access
,
3277 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3279 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3281 { .name
= "CNTPS_CVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3282 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 2,
3283 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3284 .accessfn
= gt_stimer_access
,
3285 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3286 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3290 static CPAccessResult
e2h_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3293 if (!(arm_hcr_el2_eff(env
) & HCR_E2H
)) {
3294 return CP_ACCESS_TRAP
;
3296 return CP_ACCESS_OK
;
3302 * In user-mode most of the generic timer registers are inaccessible
3303 * however modern kernels (4.12+) allow access to cntvct_el0
3306 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3308 ARMCPU
*cpu
= env_archcpu(env
);
3311 * Currently we have no support for QEMUTimer in linux-user so we
3312 * can't call gt_get_countervalue(env), instead we directly
3313 * call the lower level functions.
3315 return cpu_get_clock() / gt_cntfrq_period_ns(cpu
);
3318 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
3319 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
3320 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
3321 .type
= ARM_CP_CONST
, .access
= PL0_R
/* no PL1_RW in linux-user */,
3322 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
3323 .resetvalue
= NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
,
3325 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3326 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3327 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3328 .readfn
= gt_virt_cnt_read
,
3334 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3336 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3337 raw_write(env
, ri
, value
);
3338 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
3339 raw_write(env
, ri
, value
& 0xfffff6ff);
3341 raw_write(env
, ri
, value
& 0xfffff1ff);
3345 #ifndef CONFIG_USER_ONLY
3346 /* get_phys_addr() isn't present for user-mode-only targets */
3348 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3353 * The ATS12NSO* operations must trap to EL3 or EL2 if executed in
3354 * Secure EL1 (which can only happen if EL3 is AArch64).
3355 * They are simply UNDEF if executed from NS EL1.
3356 * They function normally from EL2 or EL3.
3358 if (arm_current_el(env
) == 1) {
3359 if (arm_is_secure_below_el3(env
)) {
3360 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
3361 return CP_ACCESS_TRAP_EL2
;
3363 return CP_ACCESS_TRAP_EL3
;
3365 return CP_ACCESS_TRAP_UNCATEGORIZED
;
3368 return CP_ACCESS_OK
;
3372 static int par_el1_shareability(GetPhysAddrResult
*res
)
3375 * The PAR_EL1.SH field must be 0b10 for Device or Normal-NC
3376 * memory -- see pseudocode PAREncodeShareability().
3378 if (((res
->cacheattrs
.attrs
& 0xf0) == 0) ||
3379 res
->cacheattrs
.attrs
== 0x44 || res
->cacheattrs
.attrs
== 0x40) {
3382 return res
->cacheattrs
.shareability
;
3385 static uint64_t do_ats_write(CPUARMState
*env
, uint64_t value
,
3386 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
3387 ARMSecuritySpace ss
)
3391 bool format64
= false;
3392 ARMMMUFaultInfo fi
= {};
3393 GetPhysAddrResult res
= {};
3396 * I_MXTJT: Granule protection checks are not performed on the final address
3397 * of a successful translation.
3399 ret
= get_phys_addr_with_space_nogpc(env
, value
, access_type
, mmu_idx
, ss
,
3403 * ATS operations only do S1 or S1+S2 translations, so we never
3404 * have to deal with the ARMCacheAttrs format for S2 only.
3406 assert(!res
.cacheattrs
.is_s2_format
);
3410 * Some kinds of translation fault must cause exceptions rather
3411 * than being reported in the PAR.
3413 int current_el
= arm_current_el(env
);
3415 uint32_t syn
, fsr
, fsc
;
3416 bool take_exc
= false;
3418 if (fi
.s1ptw
&& current_el
== 1
3419 && arm_mmu_idx_is_stage1_of_2(mmu_idx
)) {
3421 * Synchronous stage 2 fault on an access made as part of the
3422 * translation table walk for AT S1E0* or AT S1E1* insn
3423 * executed from NS EL1. If this is a synchronous external abort
3424 * and SCR_EL3.EA == 1, then we take a synchronous external abort
3425 * to EL3. Otherwise the fault is taken as an exception to EL2,
3426 * and HPFAR_EL2 holds the faulting IPA.
3428 if (fi
.type
== ARMFault_SyncExternalOnWalk
&&
3429 (env
->cp15
.scr_el3
& SCR_EA
)) {
3432 env
->cp15
.hpfar_el2
= extract64(fi
.s2addr
, 12, 47) << 4;
3433 if (arm_is_secure_below_el3(env
) && fi
.s1ns
) {
3434 env
->cp15
.hpfar_el2
|= HPFAR_NS
;
3439 } else if (fi
.type
== ARMFault_SyncExternalOnWalk
) {
3441 * Synchronous external aborts during a translation table walk
3442 * are taken as Data Abort exceptions.
3445 if (current_el
== 3) {
3451 target_el
= exception_target_el(env
);
3457 /* Construct FSR and FSC using same logic as arm_deliver_fault() */
3458 if (target_el
== 2 || arm_el_is_aa64(env
, target_el
) ||
3459 arm_s1_regime_using_lpae_format(env
, mmu_idx
)) {
3460 fsr
= arm_fi_to_lfsc(&fi
);
3461 fsc
= extract32(fsr
, 0, 6);
3463 fsr
= arm_fi_to_sfsc(&fi
);
3467 * Report exception with ESR indicating a fault due to a
3468 * translation table walk for a cache maintenance instruction.
3470 syn
= syn_data_abort_no_iss(current_el
== target_el
, 0,
3471 fi
.ea
, 1, fi
.s1ptw
, 1, fsc
);
3472 env
->exception
.vaddress
= value
;
3473 env
->exception
.fsr
= fsr
;
3474 raise_exception(env
, EXCP_DATA_ABORT
, syn
, target_el
);
3480 } else if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3483 * * TTBCR.EAE determines whether the result is returned using the
3484 * 32-bit or the 64-bit PAR format
3485 * * Instructions executed in Hyp mode always use the 64bit format
3487 * ATS1S2NSOxx uses the 64bit format if any of the following is true:
3488 * * The Non-secure TTBCR.EAE bit is set to 1
3489 * * The implementation includes EL2, and the value of HCR.VM is 1
3491 * (Note that HCR.DC makes HCR.VM behave as if it is 1.)
3493 * ATS1Hx always uses the 64bit format.
3495 format64
= arm_s1_regime_using_lpae_format(env
, mmu_idx
);
3497 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
3498 if (mmu_idx
== ARMMMUIdx_E10_0
||
3499 mmu_idx
== ARMMMUIdx_E10_1
||
3500 mmu_idx
== ARMMMUIdx_E10_1_PAN
) {
3501 format64
|= env
->cp15
.hcr_el2
& (HCR_VM
| HCR_DC
);
3503 format64
|= arm_current_el(env
) == 2;
3509 /* Create a 64-bit PAR */
3510 par64
= (1 << 11); /* LPAE bit always set */
3512 par64
|= res
.f
.phys_addr
& ~0xfffULL
;
3513 if (!res
.f
.attrs
.secure
) {
3514 par64
|= (1 << 9); /* NS */
3516 par64
|= (uint64_t)res
.cacheattrs
.attrs
<< 56; /* ATTR */
3517 par64
|= par_el1_shareability(&res
) << 7; /* SH */
3519 uint32_t fsr
= arm_fi_to_lfsc(&fi
);
3522 par64
|= (fsr
& 0x3f) << 1; /* FS */
3524 par64
|= (1 << 9); /* S */
3527 par64
|= (1 << 8); /* PTW */
3532 * fsr is a DFSR/IFSR value for the short descriptor
3533 * translation table format (with WnR always clear).
3534 * Convert it to a 32-bit PAR.
3537 /* We do not set any attribute bits in the PAR */
3538 if (res
.f
.lg_page_size
== 24
3539 && arm_feature(env
, ARM_FEATURE_V7
)) {
3540 par64
= (res
.f
.phys_addr
& 0xff000000) | (1 << 1);
3542 par64
= res
.f
.phys_addr
& 0xfffff000;
3544 if (!res
.f
.attrs
.secure
) {
3545 par64
|= (1 << 9); /* NS */
3548 uint32_t fsr
= arm_fi_to_sfsc(&fi
);
3550 par64
= ((fsr
& (1 << 10)) >> 5) | ((fsr
& (1 << 12)) >> 6) |
3551 ((fsr
& 0xf) << 1) | 1;
3556 #endif /* CONFIG_TCG */
3558 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3561 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3564 int el
= arm_current_el(env
);
3565 ARMSecuritySpace ss
= arm_security_space(env
);
3567 switch (ri
->opc2
& 6) {
3569 /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */
3572 mmu_idx
= ARMMMUIdx_E3
;
3575 g_assert(ss
!= ARMSS_Secure
); /* ARMv8.4-SecEL2 is 64-bit only */
3578 if (ri
->crm
== 9 && (env
->uncached_cpsr
& CPSR_PAN
)) {
3579 mmu_idx
= ARMMMUIdx_Stage1_E1_PAN
;
3581 mmu_idx
= ARMMMUIdx_Stage1_E1
;
3585 g_assert_not_reached();
3589 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
3592 mmu_idx
= ARMMMUIdx_E10_0
;
3595 g_assert(ss
!= ARMSS_Secure
); /* ARMv8.4-SecEL2 is 64-bit only */
3596 mmu_idx
= ARMMMUIdx_Stage1_E0
;
3599 mmu_idx
= ARMMMUIdx_Stage1_E0
;
3602 g_assert_not_reached();
3606 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
3607 mmu_idx
= ARMMMUIdx_E10_1
;
3608 ss
= ARMSS_NonSecure
;
3611 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
3612 mmu_idx
= ARMMMUIdx_E10_0
;
3613 ss
= ARMSS_NonSecure
;
3616 g_assert_not_reached();
3619 par64
= do_ats_write(env
, value
, access_type
, mmu_idx
, ss
);
3621 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3623 /* Handled by hardware accelerator. */
3624 g_assert_not_reached();
3625 #endif /* CONFIG_TCG */
3628 static void ats1h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3632 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3635 /* There is no SecureEL2 for AArch32. */
3636 par64
= do_ats_write(env
, value
, access_type
, ARMMMUIdx_E2
,
3639 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3641 /* Handled by hardware accelerator. */
3642 g_assert_not_reached();
3643 #endif /* CONFIG_TCG */
3646 static CPAccessResult
at_e012_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3650 * R_NYXTL: instruction is UNDEFINED if it applies to an Exception level
3651 * lower than EL3 and the combination SCR_EL3.{NSE,NS} is reserved. This can
3652 * only happen when executing at EL3 because that combination also causes an
3653 * illegal exception return. We don't need to check FEAT_RME either, because
3654 * scr_write() ensures that the NSE bit is not set otherwise.
3656 if ((env
->cp15
.scr_el3
& (SCR_NSE
| SCR_NS
)) == SCR_NSE
) {
3657 return CP_ACCESS_TRAP
;
3659 return CP_ACCESS_OK
;
3662 static CPAccessResult
at_s1e2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3665 if (arm_current_el(env
) == 3 &&
3666 !(env
->cp15
.scr_el3
& (SCR_NS
| SCR_EEL2
))) {
3667 return CP_ACCESS_TRAP
;
3669 return at_e012_access(env
, ri
, isread
);
3672 static void ats_write64(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3676 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3678 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
3679 bool regime_e20
= (hcr_el2
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
);
3681 switch (ri
->opc2
& 6) {
3684 case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */
3685 if (ri
->crm
== 9 && (env
->pstate
& PSTATE_PAN
)) {
3686 mmu_idx
= regime_e20
?
3687 ARMMMUIdx_E20_2_PAN
: ARMMMUIdx_Stage1_E1_PAN
;
3689 mmu_idx
= regime_e20
? ARMMMUIdx_E20_2
: ARMMMUIdx_Stage1_E1
;
3692 case 4: /* AT S1E2R, AT S1E2W */
3693 mmu_idx
= hcr_el2
& HCR_E2H
? ARMMMUIdx_E20_2
: ARMMMUIdx_E2
;
3695 case 6: /* AT S1E3R, AT S1E3W */
3696 mmu_idx
= ARMMMUIdx_E3
;
3699 g_assert_not_reached();
3702 case 2: /* AT S1E0R, AT S1E0W */
3703 mmu_idx
= regime_e20
? ARMMMUIdx_E20_0
: ARMMMUIdx_Stage1_E0
;
3705 case 4: /* AT S12E1R, AT S12E1W */
3706 mmu_idx
= regime_e20
? ARMMMUIdx_E20_2
: ARMMMUIdx_E10_1
;
3708 case 6: /* AT S12E0R, AT S12E0W */
3709 mmu_idx
= regime_e20
? ARMMMUIdx_E20_0
: ARMMMUIdx_E10_0
;
3712 g_assert_not_reached();
3715 env
->cp15
.par_el
[1] = do_ats_write(env
, value
, access_type
,
3716 mmu_idx
, arm_security_space(env
));
3718 /* Handled by hardware accelerator. */
3719 g_assert_not_reached();
3720 #endif /* CONFIG_TCG */
3724 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
3725 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
3726 .access
= PL1_RW
, .resetvalue
= 0,
3727 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.par_s
),
3728 offsetoflow32(CPUARMState
, cp15
.par_ns
) },
3729 .writefn
= par_write
},
3730 #ifndef CONFIG_USER_ONLY
3731 /* This underdecoding is safe because the reginfo is NO_RAW. */
3732 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
3733 .access
= PL1_W
, .accessfn
= ats_access
,
3734 .writefn
= ats_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
3738 /* Return basic MPU access permission bits. */
3739 static uint32_t simple_mpu_ap_bits(uint32_t val
)
3746 for (i
= 0; i
< 16; i
+= 2) {
3747 ret
|= (val
>> i
) & mask
;
3753 /* Pad basic MPU access permission bits to extended format. */
3754 static uint32_t extended_mpu_ap_bits(uint32_t val
)
3761 for (i
= 0; i
< 16; i
+= 2) {
3762 ret
|= (val
& mask
) << i
;
3768 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3771 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
3774 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3776 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
3779 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3782 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
3785 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3787 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
3790 static uint64_t pmsav7_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3792 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3798 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3802 static void pmsav7_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3805 ARMCPU
*cpu
= env_archcpu(env
);
3806 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3812 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3813 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3817 static void pmsav7_rgnr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3820 ARMCPU
*cpu
= env_archcpu(env
);
3821 uint32_t nrgs
= cpu
->pmsav7_dregion
;
3823 if (value
>= nrgs
) {
3824 qemu_log_mask(LOG_GUEST_ERROR
,
3825 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
3826 " > %" PRIu32
"\n", (uint32_t)value
, nrgs
);
3830 raw_write(env
, ri
, value
);
3833 static void prbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3836 ARMCPU
*cpu
= env_archcpu(env
);
3838 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3839 env
->pmsav8
.rbar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]] = value
;
3842 static uint64_t prbar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3844 return env
->pmsav8
.rbar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]];
3847 static void prlar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3850 ARMCPU
*cpu
= env_archcpu(env
);
3852 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3853 env
->pmsav8
.rlar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]] = value
;
3856 static uint64_t prlar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3858 return env
->pmsav8
.rlar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]];
3861 static void prselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3864 ARMCPU
*cpu
= env_archcpu(env
);
3867 * Ignore writes that would select not implemented region.
3868 * This is architecturally UNPREDICTABLE.
3870 if (value
>= cpu
->pmsav7_dregion
) {
3874 env
->pmsav7
.rnr
[M_REG_NS
] = value
;
3877 static void hprbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3880 ARMCPU
*cpu
= env_archcpu(env
);
3882 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3883 env
->pmsav8
.hprbar
[env
->pmsav8
.hprselr
] = value
;
3886 static uint64_t hprbar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3888 return env
->pmsav8
.hprbar
[env
->pmsav8
.hprselr
];
3891 static void hprlar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3894 ARMCPU
*cpu
= env_archcpu(env
);
3896 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3897 env
->pmsav8
.hprlar
[env
->pmsav8
.hprselr
] = value
;
3900 static uint64_t hprlar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3902 return env
->pmsav8
.hprlar
[env
->pmsav8
.hprselr
];
3905 static void hprenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3910 ARMCPU
*cpu
= env_archcpu(env
);
3912 /* Ignore writes to unimplemented regions */
3913 int rmax
= MIN(cpu
->pmsav8r_hdregion
, 32);
3914 value
&= MAKE_64BIT_MASK(0, rmax
);
3916 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3918 /* Register alias is only valid for first 32 indexes */
3919 for (n
= 0; n
< rmax
; ++n
) {
3920 bit
= extract32(value
, n
, 1);
3921 env
->pmsav8
.hprlar
[n
] = deposit32(
3922 env
->pmsav8
.hprlar
[n
], 0, 1, bit
);
3926 static uint64_t hprenr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3929 uint32_t result
= 0x0;
3930 ARMCPU
*cpu
= env_archcpu(env
);
3932 /* Register alias is only valid for first 32 indexes */
3933 for (n
= 0; n
< MIN(cpu
->pmsav8r_hdregion
, 32); ++n
) {
3934 if (env
->pmsav8
.hprlar
[n
] & 0x1) {
3935 result
|= (0x1 << n
);
3941 static void hprselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3944 ARMCPU
*cpu
= env_archcpu(env
);
3947 * Ignore writes that would select not implemented region.
3948 * This is architecturally UNPREDICTABLE.
3950 if (value
>= cpu
->pmsav8r_hdregion
) {
3954 env
->pmsav8
.hprselr
= value
;
3957 static void pmsav8r_regn_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3960 ARMCPU
*cpu
= env_archcpu(env
);
3961 uint8_t index
= (extract32(ri
->opc0
, 0, 1) << 4) |
3962 (extract32(ri
->crm
, 0, 3) << 1) | extract32(ri
->opc2
, 2, 1);
3964 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3967 if (index
>= cpu
->pmsav8r_hdregion
) {
3970 if (ri
->opc2
& 0x1) {
3971 env
->pmsav8
.hprlar
[index
] = value
;
3973 env
->pmsav8
.hprbar
[index
] = value
;
3976 if (index
>= cpu
->pmsav7_dregion
) {
3979 if (ri
->opc2
& 0x1) {
3980 env
->pmsav8
.rlar
[M_REG_NS
][index
] = value
;
3982 env
->pmsav8
.rbar
[M_REG_NS
][index
] = value
;
3987 static uint64_t pmsav8r_regn_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3989 ARMCPU
*cpu
= env_archcpu(env
);
3990 uint8_t index
= (extract32(ri
->opc0
, 0, 1) << 4) |
3991 (extract32(ri
->crm
, 0, 3) << 1) | extract32(ri
->opc2
, 2, 1);
3994 if (index
>= cpu
->pmsav8r_hdregion
) {
3997 if (ri
->opc2
& 0x1) {
3998 return env
->pmsav8
.hprlar
[index
];
4000 return env
->pmsav8
.hprbar
[index
];
4003 if (index
>= cpu
->pmsav7_dregion
) {
4006 if (ri
->opc2
& 0x1) {
4007 return env
->pmsav8
.rlar
[M_REG_NS
][index
];
4009 return env
->pmsav8
.rbar
[M_REG_NS
][index
];
4014 static const ARMCPRegInfo pmsav8r_cp_reginfo
[] = {
4016 .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 3, .opc2
= 0,
4017 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4018 .accessfn
= access_tvm_trvm
,
4019 .readfn
= prbar_read
, .writefn
= prbar_write
},
4021 .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 3, .opc2
= 1,
4022 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4023 .accessfn
= access_tvm_trvm
,
4024 .readfn
= prlar_read
, .writefn
= prlar_write
},
4025 { .name
= "PRSELR", .resetvalue
= 0,
4026 .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 2, .opc2
= 1,
4027 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4028 .writefn
= prselr_write
,
4029 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]) },
4030 { .name
= "HPRBAR", .resetvalue
= 0,
4031 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 3, .opc2
= 0,
4032 .access
= PL2_RW
, .type
= ARM_CP_NO_RAW
,
4033 .readfn
= hprbar_read
, .writefn
= hprbar_write
},
4035 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 3, .opc2
= 1,
4036 .access
= PL2_RW
, .type
= ARM_CP_NO_RAW
,
4037 .readfn
= hprlar_read
, .writefn
= hprlar_write
},
4038 { .name
= "HPRSELR", .resetvalue
= 0,
4039 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 2, .opc2
= 1,
4041 .writefn
= hprselr_write
,
4042 .fieldoffset
= offsetof(CPUARMState
, pmsav8
.hprselr
) },
4044 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 1, .opc2
= 1,
4045 .access
= PL2_RW
, .type
= ARM_CP_NO_RAW
,
4046 .readfn
= hprenr_read
, .writefn
= hprenr_write
},
4049 static const ARMCPRegInfo pmsav7_cp_reginfo
[] = {
4051 * Reset for all these registers is handled in arm_cpu_reset(),
4052 * because the PMSAv7 is also used by M-profile CPUs, which do
4053 * not register cpregs but still need the state to be reset.
4055 { .name
= "DRBAR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 0,
4056 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4057 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drbar
),
4058 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
4059 .resetfn
= arm_cp_reset_ignore
},
4060 { .name
= "DRSR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 2,
4061 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4062 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drsr
),
4063 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
4064 .resetfn
= arm_cp_reset_ignore
},
4065 { .name
= "DRACR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 4,
4066 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4067 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.dracr
),
4068 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
4069 .resetfn
= arm_cp_reset_ignore
},
4070 { .name
= "RGNR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 2, .opc2
= 0,
4072 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]),
4073 .writefn
= pmsav7_rgnr_write
,
4074 .resetfn
= arm_cp_reset_ignore
},
4077 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
4078 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
4079 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
4080 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
4081 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
4082 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
4083 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
4084 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
4085 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
4086 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
4088 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
4090 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
4092 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
4094 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
4096 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
4097 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
4099 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
4100 /* Protection region base and size registers */
4101 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
4102 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4103 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
4104 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
4105 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4106 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
4107 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
4108 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4109 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
4110 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
4111 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4112 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
4113 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
4114 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4115 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
4116 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
4117 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4118 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
4119 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
4120 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4121 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
4122 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
4123 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4124 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
4127 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4130 ARMCPU
*cpu
= env_archcpu(env
);
4132 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
4133 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
4135 * Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
4136 * using Long-descriptor translation table format
4138 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
4139 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
4141 * In an implementation that includes the Security Extensions
4142 * TTBCR has additional fields PD0 [4] and PD1 [5] for
4143 * Short-descriptor translation table format.
4145 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
4151 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
4153 * With LPAE the TTBCR could result in a change of ASID
4154 * via the TTBCR.A1 bit, so do a TLB flush.
4156 tlb_flush(CPU(cpu
));
4158 raw_write(env
, ri
, value
);
4161 static void vmsa_tcr_el12_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4164 ARMCPU
*cpu
= env_archcpu(env
);
4166 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
4167 tlb_flush(CPU(cpu
));
4168 raw_write(env
, ri
, value
);
4171 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4174 /* If the ASID changes (with a 64-bit write), we must flush the TLB. */
4175 if (cpreg_field_is_64bit(ri
) &&
4176 extract64(raw_read(env
, ri
) ^ value
, 48, 16) != 0) {
4177 ARMCPU
*cpu
= env_archcpu(env
);
4178 tlb_flush(CPU(cpu
));
4180 raw_write(env
, ri
, value
);
4183 static void vmsa_tcr_ttbr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4187 * If we are running with E2&0 regime, then an ASID is active.
4188 * Flush if that might be changing. Note we're not checking
4189 * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that
4190 * holds the active ASID, only checking the field that might.
4192 if (extract64(raw_read(env
, ri
) ^ value
, 48, 16) &&
4193 (arm_hcr_el2_eff(env
) & HCR_E2H
)) {
4194 uint16_t mask
= ARMMMUIdxBit_E20_2
|
4195 ARMMMUIdxBit_E20_2_PAN
|
4197 tlb_flush_by_mmuidx(env_cpu(env
), mask
);
4199 raw_write(env
, ri
, value
);
4202 static void vttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4205 ARMCPU
*cpu
= env_archcpu(env
);
4206 CPUState
*cs
= CPU(cpu
);
4209 * A change in VMID to the stage2 page table (Stage2) invalidates
4210 * the stage2 and combined stage 1&2 tlbs (EL10_1 and EL10_0).
4212 if (extract64(raw_read(env
, ri
) ^ value
, 48, 16) != 0) {
4213 tlb_flush_by_mmuidx(cs
, alle1_tlbmask(env
));
4215 raw_write(env
, ri
, value
);
4218 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo
[] = {
4219 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
4220 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .type
= ARM_CP_ALIAS
,
4221 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dfsr_s
),
4222 offsetoflow32(CPUARMState
, cp15
.dfsr_ns
) }, },
4223 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
4224 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
4225 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.ifsr_s
),
4226 offsetoflow32(CPUARMState
, cp15
.ifsr_ns
) } },
4227 { .name
= "DFAR", .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 0, .opc2
= 0,
4228 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
4229 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.dfar_s
),
4230 offsetof(CPUARMState
, cp15
.dfar_ns
) } },
4231 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_AA64
,
4232 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
4233 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4235 .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
4239 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
4240 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
4241 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
4242 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4244 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
4245 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
4246 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 0,
4247 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4248 .fgt
= FGT_TTBR0_EL1
,
4249 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0, .raw_writefn
= raw_write
,
4250 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
4251 offsetof(CPUARMState
, cp15
.ttbr0_ns
) } },
4252 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
4253 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 1,
4254 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4255 .fgt
= FGT_TTBR1_EL1
,
4256 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0, .raw_writefn
= raw_write
,
4257 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
4258 offsetof(CPUARMState
, cp15
.ttbr1_ns
) } },
4259 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
4260 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
4261 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4263 .writefn
= vmsa_tcr_el12_write
,
4264 .raw_writefn
= raw_write
,
4266 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[1]) },
4267 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
4268 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4269 .type
= ARM_CP_ALIAS
, .writefn
= vmsa_ttbcr_write
,
4270 .raw_writefn
= raw_write
,
4271 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tcr_el
[3]),
4272 offsetoflow32(CPUARMState
, cp15
.tcr_el
[1])} },
4276 * Note that unlike TTBCR, writing to TTBCR2 does not require flushing
4277 * qemu tlbs nor adjusting cached masks.
4279 static const ARMCPRegInfo ttbcr2_reginfo
= {
4280 .name
= "TTBCR2", .cp
= 15, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 3,
4281 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4282 .type
= ARM_CP_ALIAS
,
4283 .bank_fieldoffsets
= {
4284 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[3]),
4285 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[1]),
4289 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4292 env
->cp15
.c15_ticonfig
= value
& 0xe7;
4293 /* The OS_TYPE bit in this register changes the reported CPUID! */
4294 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
4295 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
4298 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4301 env
->cp15
.c15_threadid
= value
& 0xffff;
4304 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4307 /* Wait-for-interrupt (deprecated) */
4308 cpu_interrupt(env_cpu(env
), CPU_INTERRUPT_HALT
);
4311 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4315 * On OMAP there are registers indicating the max/min index of dcache lines
4316 * containing a dirty line; cache flush operations have to reset these.
4318 env
->cp15
.c15_i_max
= 0x000;
4319 env
->cp15
.c15_i_min
= 0xff0;
4322 static const ARMCPRegInfo omap_cp_reginfo
[] = {
4323 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
4324 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
4325 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
4327 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
4328 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
4329 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
4331 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
4332 .writefn
= omap_ticonfig_write
},
4333 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
4335 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
4336 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
4337 .access
= PL1_RW
, .resetvalue
= 0xff0,
4338 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
4339 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
4341 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
4342 .writefn
= omap_threadid_write
},
4343 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
4344 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
4345 .type
= ARM_CP_NO_RAW
,
4346 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
4348 * TODO: Peripheral port remap register:
4349 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
4350 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
4353 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
4354 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
4355 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
,
4356 .writefn
= omap_cachemaint_write
},
4357 { .name
= "C9", .cp
= 15, .crn
= 9,
4358 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
4359 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
4362 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4365 env
->cp15
.c15_cpar
= value
& 0x3fff;
4368 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
4369 { .name
= "XSCALE_CPAR",
4370 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
4371 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
4372 .writefn
= xscale_cpar_write
, },
4373 { .name
= "XSCALE_AUXCR",
4374 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
4375 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
4378 * XScale specific cache-lockdown: since we have no cache we NOP these
4379 * and hope the guest does not really rely on cache behaviour.
4381 { .name
= "XSCALE_LOCK_ICACHE_LINE",
4382 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
4383 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4384 { .name
= "XSCALE_UNLOCK_ICACHE",
4385 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
4386 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4387 { .name
= "XSCALE_DCACHE_LOCK",
4388 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
4389 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
4390 { .name
= "XSCALE_UNLOCK_DCACHE",
4391 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
4392 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4395 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
4397 * RAZ/WI the whole crn=15 space, when we don't have a more specific
4398 * implementation of this implementation-defined space.
4399 * Ideally this should eventually disappear in favour of actually
4400 * implementing the correct behaviour for all cores.
4402 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
4403 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
4405 .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
| ARM_CP_OVERRIDE
,
4409 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
4410 /* Cache status: RAZ because we have no cache so it's always clean */
4411 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
4412 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4416 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
4417 /* We never have a block transfer operation in progress */
4418 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
4419 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4421 /* The cache ops themselves: these all NOP for QEMU */
4422 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
4423 .access
= PL1_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4424 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
4425 .access
= PL1_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4426 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
4427 .access
= PL0_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4428 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
4429 .access
= PL0_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4430 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
4431 .access
= PL0_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4432 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
4433 .access
= PL1_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4436 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
4438 * The cache test-and-clean instructions always return (1 << 30)
4439 * to indicate that there are no dirty cache lines.
4441 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
4442 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4443 .resetvalue
= (1 << 30) },
4444 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
4445 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4446 .resetvalue
= (1 << 30) },
4449 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
4450 /* Ignore ReadBuffer accesses */
4451 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
4452 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
4453 .access
= PL1_RW
, .resetvalue
= 0,
4454 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
},
4457 static uint64_t midr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4459 unsigned int cur_el
= arm_current_el(env
);
4461 if (arm_is_el2_enabled(env
) && cur_el
== 1) {
4462 return env
->cp15
.vpidr_el2
;
4464 return raw_read(env
, ri
);
4467 static uint64_t mpidr_read_val(CPUARMState
*env
)
4469 ARMCPU
*cpu
= env_archcpu(env
);
4470 uint64_t mpidr
= cpu
->mp_affinity
;
4472 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
4473 mpidr
|= (1U << 31);
4475 * Cores which are uniprocessor (non-coherent)
4476 * but still implement the MP extensions set
4477 * bit 30. (For instance, Cortex-R5).
4479 if (cpu
->mp_is_up
) {
4480 mpidr
|= (1u << 30);
4486 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4488 unsigned int cur_el
= arm_current_el(env
);
4490 if (arm_is_el2_enabled(env
) && cur_el
== 1) {
4491 return env
->cp15
.vmpidr_el2
;
4493 return mpidr_read_val(env
);
4496 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
4498 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
4499 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
4500 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4501 .fgt
= FGT_AMAIR_EL1
,
4502 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4503 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
4504 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
4505 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4506 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4507 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
4508 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .resetvalue
= 0,
4509 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.par_s
),
4510 offsetof(CPUARMState
, cp15
.par_ns
)} },
4511 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
4512 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4513 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4514 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
4515 offsetof(CPUARMState
, cp15
.ttbr0_ns
) },
4516 .writefn
= vmsa_ttbr_write
, .raw_writefn
= raw_write
},
4517 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
4518 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4519 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4520 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
4521 offsetof(CPUARMState
, cp15
.ttbr1_ns
) },
4522 .writefn
= vmsa_ttbr_write
, .raw_writefn
= raw_write
},
4525 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4527 return vfp_get_fpcr(env
);
4530 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4533 vfp_set_fpcr(env
, value
);
4536 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4538 return vfp_get_fpsr(env
);
4541 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4544 vfp_set_fpsr(env
, value
);
4547 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4550 if (arm_current_el(env
) == 0 && !(arm_sctlr(env
, 0) & SCTLR_UMA
)) {
4551 return CP_ACCESS_TRAP
;
4553 return CP_ACCESS_OK
;
4556 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4559 env
->daif
= value
& PSTATE_DAIF
;
4562 static uint64_t aa64_pan_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4564 return env
->pstate
& PSTATE_PAN
;
4567 static void aa64_pan_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4570 env
->pstate
= (env
->pstate
& ~PSTATE_PAN
) | (value
& PSTATE_PAN
);
4573 static const ARMCPRegInfo pan_reginfo
= {
4574 .name
= "PAN", .state
= ARM_CP_STATE_AA64
,
4575 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 3,
4576 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4577 .readfn
= aa64_pan_read
, .writefn
= aa64_pan_write
4580 static uint64_t aa64_uao_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4582 return env
->pstate
& PSTATE_UAO
;
4585 static void aa64_uao_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4588 env
->pstate
= (env
->pstate
& ~PSTATE_UAO
) | (value
& PSTATE_UAO
);
4591 static const ARMCPRegInfo uao_reginfo
= {
4592 .name
= "UAO", .state
= ARM_CP_STATE_AA64
,
4593 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 4,
4594 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4595 .readfn
= aa64_uao_read
, .writefn
= aa64_uao_write
4598 static uint64_t aa64_dit_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4600 return env
->pstate
& PSTATE_DIT
;
4603 static void aa64_dit_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4606 env
->pstate
= (env
->pstate
& ~PSTATE_DIT
) | (value
& PSTATE_DIT
);
4609 static const ARMCPRegInfo dit_reginfo
= {
4610 .name
= "DIT", .state
= ARM_CP_STATE_AA64
,
4611 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 5,
4612 .type
= ARM_CP_NO_RAW
, .access
= PL0_RW
,
4613 .readfn
= aa64_dit_read
, .writefn
= aa64_dit_write
4616 static uint64_t aa64_ssbs_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4618 return env
->pstate
& PSTATE_SSBS
;
4621 static void aa64_ssbs_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4624 env
->pstate
= (env
->pstate
& ~PSTATE_SSBS
) | (value
& PSTATE_SSBS
);
4627 static const ARMCPRegInfo ssbs_reginfo
= {
4628 .name
= "SSBS", .state
= ARM_CP_STATE_AA64
,
4629 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 6,
4630 .type
= ARM_CP_NO_RAW
, .access
= PL0_RW
,
4631 .readfn
= aa64_ssbs_read
, .writefn
= aa64_ssbs_write
4634 static CPAccessResult
aa64_cacheop_poc_access(CPUARMState
*env
,
4635 const ARMCPRegInfo
*ri
,
4638 /* Cache invalidate/clean to Point of Coherency or Persistence... */
4639 switch (arm_current_el(env
)) {
4641 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4642 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4643 return CP_ACCESS_TRAP
;
4647 /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */
4648 if (arm_hcr_el2_eff(env
) & HCR_TPCP
) {
4649 return CP_ACCESS_TRAP_EL2
;
4653 return CP_ACCESS_OK
;
4656 static CPAccessResult
do_cacheop_pou_access(CPUARMState
*env
, uint64_t hcrflags
)
4658 /* Cache invalidate/clean to Point of Unification... */
4659 switch (arm_current_el(env
)) {
4661 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4662 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4663 return CP_ACCESS_TRAP
;
4667 /* ... EL1 must trap to EL2 if relevant HCR_EL2 flags are set. */
4668 if (arm_hcr_el2_eff(env
) & hcrflags
) {
4669 return CP_ACCESS_TRAP_EL2
;
4673 return CP_ACCESS_OK
;
4676 static CPAccessResult
access_ticab(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4679 return do_cacheop_pou_access(env
, HCR_TICAB
| HCR_TPU
);
4682 static CPAccessResult
access_tocu(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4685 return do_cacheop_pou_access(env
, HCR_TOCU
| HCR_TPU
);
4689 * See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
4690 * Page D4-1736 (DDI0487A.b)
4693 static int vae1_tlbmask(CPUARMState
*env
)
4695 uint64_t hcr
= arm_hcr_el2_eff(env
);
4698 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4699 mask
= ARMMMUIdxBit_E20_2
|
4700 ARMMMUIdxBit_E20_2_PAN
|
4703 mask
= ARMMMUIdxBit_E10_1
|
4704 ARMMMUIdxBit_E10_1_PAN
|
4710 static int vae2_tlbmask(CPUARMState
*env
)
4712 uint64_t hcr
= arm_hcr_el2_eff(env
);
4715 if (hcr
& HCR_E2H
) {
4716 mask
= ARMMMUIdxBit_E20_2
|
4717 ARMMMUIdxBit_E20_2_PAN
|
4720 mask
= ARMMMUIdxBit_E2
;
4725 /* Return 56 if TBI is enabled, 64 otherwise. */
4726 static int tlbbits_for_regime(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
4729 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
4730 int tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
4731 int select
= extract64(addr
, 55, 1);
4733 return (tbi
>> select
) & 1 ? 56 : 64;
4736 static int vae1_tlbbits(CPUARMState
*env
, uint64_t addr
)
4738 uint64_t hcr
= arm_hcr_el2_eff(env
);
4741 /* Only the regime of the mmu_idx below is significant. */
4742 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4743 mmu_idx
= ARMMMUIdx_E20_0
;
4745 mmu_idx
= ARMMMUIdx_E10_0
;
4748 return tlbbits_for_regime(env
, mmu_idx
, addr
);
4751 static int vae2_tlbbits(CPUARMState
*env
, uint64_t addr
)
4753 uint64_t hcr
= arm_hcr_el2_eff(env
);
4757 * Only the regime of the mmu_idx below is significant.
4758 * Regime EL2&0 has two ranges with separate TBI configuration, while EL2
4761 if (hcr
& HCR_E2H
) {
4762 mmu_idx
= ARMMMUIdx_E20_2
;
4764 mmu_idx
= ARMMMUIdx_E2
;
4767 return tlbbits_for_regime(env
, mmu_idx
, addr
);
4770 static void tlbi_aa64_vmalle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4773 CPUState
*cs
= env_cpu(env
);
4774 int mask
= vae1_tlbmask(env
);
4776 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4779 static void tlbi_aa64_vmalle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4782 CPUState
*cs
= env_cpu(env
);
4783 int mask
= vae1_tlbmask(env
);
4785 if (tlb_force_broadcast(env
)) {
4786 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4788 tlb_flush_by_mmuidx(cs
, mask
);
4792 static int e2_tlbmask(CPUARMState
*env
)
4794 return (ARMMMUIdxBit_E20_0
|
4795 ARMMMUIdxBit_E20_2
|
4796 ARMMMUIdxBit_E20_2_PAN
|
4800 static void tlbi_aa64_alle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4803 CPUState
*cs
= env_cpu(env
);
4804 int mask
= alle1_tlbmask(env
);
4806 tlb_flush_by_mmuidx(cs
, mask
);
4809 static void tlbi_aa64_alle2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4812 CPUState
*cs
= env_cpu(env
);
4813 int mask
= e2_tlbmask(env
);
4815 tlb_flush_by_mmuidx(cs
, mask
);
4818 static void tlbi_aa64_alle3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4821 ARMCPU
*cpu
= env_archcpu(env
);
4822 CPUState
*cs
= CPU(cpu
);
4824 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_E3
);
4827 static void tlbi_aa64_alle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4830 CPUState
*cs
= env_cpu(env
);
4831 int mask
= alle1_tlbmask(env
);
4833 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4836 static void tlbi_aa64_alle2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4839 CPUState
*cs
= env_cpu(env
);
4840 int mask
= e2_tlbmask(env
);
4842 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4845 static void tlbi_aa64_alle3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4848 CPUState
*cs
= env_cpu(env
);
4850 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_E3
);
4853 static void tlbi_aa64_vae2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4857 * Invalidate by VA, EL2
4858 * Currently handles both VAE2 and VALE2, since we don't support
4859 * flush-last-level-only.
4861 CPUState
*cs
= env_cpu(env
);
4862 int mask
= vae2_tlbmask(env
);
4863 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4864 int bits
= vae2_tlbbits(env
, pageaddr
);
4866 tlb_flush_page_bits_by_mmuidx(cs
, pageaddr
, mask
, bits
);
4869 static void tlbi_aa64_vae3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4873 * Invalidate by VA, EL3
4874 * Currently handles both VAE3 and VALE3, since we don't support
4875 * flush-last-level-only.
4877 ARMCPU
*cpu
= env_archcpu(env
);
4878 CPUState
*cs
= CPU(cpu
);
4879 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4881 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_E3
);
4884 static void tlbi_aa64_vae1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4887 CPUState
*cs
= env_cpu(env
);
4888 int mask
= vae1_tlbmask(env
);
4889 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4890 int bits
= vae1_tlbbits(env
, pageaddr
);
4892 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4895 static void tlbi_aa64_vae1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4899 * Invalidate by VA, EL1&0 (AArch64 version).
4900 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
4901 * since we don't support flush-for-specific-ASID-only or
4902 * flush-last-level-only.
4904 CPUState
*cs
= env_cpu(env
);
4905 int mask
= vae1_tlbmask(env
);
4906 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4907 int bits
= vae1_tlbbits(env
, pageaddr
);
4909 if (tlb_force_broadcast(env
)) {
4910 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4912 tlb_flush_page_bits_by_mmuidx(cs
, pageaddr
, mask
, bits
);
4916 static void tlbi_aa64_vae2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4919 CPUState
*cs
= env_cpu(env
);
4920 int mask
= vae2_tlbmask(env
);
4921 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4922 int bits
= vae2_tlbbits(env
, pageaddr
);
4924 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4927 static void tlbi_aa64_vae3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4930 CPUState
*cs
= env_cpu(env
);
4931 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4932 int bits
= tlbbits_for_regime(env
, ARMMMUIdx_E3
, pageaddr
);
4934 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4935 ARMMMUIdxBit_E3
, bits
);
4938 static int ipas2e1_tlbmask(CPUARMState
*env
, int64_t value
)
4941 * The MSB of value is the NS field, which only applies if SEL2
4942 * is implemented and SCR_EL3.NS is not set (i.e. in secure mode).
4945 && cpu_isar_feature(aa64_sel2
, env_archcpu(env
))
4946 && arm_is_secure_below_el3(env
)
4947 ? ARMMMUIdxBit_Stage2_S
4948 : ARMMMUIdxBit_Stage2
);
4951 static void tlbi_aa64_ipas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4954 CPUState
*cs
= env_cpu(env
);
4955 int mask
= ipas2e1_tlbmask(env
, value
);
4956 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4958 if (tlb_force_broadcast(env
)) {
4959 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
);
4961 tlb_flush_page_by_mmuidx(cs
, pageaddr
, mask
);
4965 static void tlbi_aa64_ipas2e1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4968 CPUState
*cs
= env_cpu(env
);
4969 int mask
= ipas2e1_tlbmask(env
, value
);
4970 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4972 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
);
4975 #ifdef TARGET_AARCH64
4981 static ARMGranuleSize
tlbi_range_tg_to_gran_size(int tg
)
4984 * Note that the TLBI range TG field encoding differs from both
4985 * TG0 and TG1 encodings.
4999 static TLBIRange
tlbi_aa64_get_range(CPUARMState
*env
, ARMMMUIdx mmuidx
,
5002 unsigned int page_size_granule
, page_shift
, num
, scale
, exponent
;
5003 /* Extract one bit to represent the va selector in use. */
5004 uint64_t select
= sextract64(value
, 36, 1);
5005 ARMVAParameters param
= aa64_va_parameters(env
, select
, mmuidx
, true, false);
5006 TLBIRange ret
= { };
5007 ARMGranuleSize gran
;
5009 page_size_granule
= extract64(value
, 46, 2);
5010 gran
= tlbi_range_tg_to_gran_size(page_size_granule
);
5012 /* The granule encoded in value must match the granule in use. */
5013 if (gran
!= param
.gran
) {
5014 qemu_log_mask(LOG_GUEST_ERROR
, "Invalid tlbi page size granule %d\n",
5019 page_shift
= arm_granule_bits(gran
);
5020 num
= extract64(value
, 39, 5);
5021 scale
= extract64(value
, 44, 2);
5022 exponent
= (5 * scale
) + 1;
5024 ret
.length
= (num
+ 1) << (exponent
+ page_shift
);
5027 ret
.base
= sextract64(value
, 0, 37);
5029 ret
.base
= extract64(value
, 0, 37);
5033 * With DS=1, BaseADDR is always shifted 16 so that it is able
5034 * to address all 52 va bits. The input address is perforce
5035 * aligned on a 64k boundary regardless of translation granule.
5039 ret
.base
<<= page_shift
;
5044 static void do_rvae_write(CPUARMState
*env
, uint64_t value
,
5045 int idxmap
, bool synced
)
5047 ARMMMUIdx one_idx
= ARM_MMU_IDX_A
| ctz32(idxmap
);
5051 range
= tlbi_aa64_get_range(env
, one_idx
, value
);
5052 bits
= tlbbits_for_regime(env
, one_idx
, range
.base
);
5055 tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env
),
5061 tlb_flush_range_by_mmuidx(env_cpu(env
), range
.base
,
5062 range
.length
, idxmap
, bits
);
5066 static void tlbi_aa64_rvae1_write(CPUARMState
*env
,
5067 const ARMCPRegInfo
*ri
,
5071 * Invalidate by VA range, EL1&0.
5072 * Currently handles all of RVAE1, RVAAE1, RVAALE1 and RVALE1,
5073 * since we don't support flush-for-specific-ASID-only or
5074 * flush-last-level-only.
5077 do_rvae_write(env
, value
, vae1_tlbmask(env
),
5078 tlb_force_broadcast(env
));
5081 static void tlbi_aa64_rvae1is_write(CPUARMState
*env
,
5082 const ARMCPRegInfo
*ri
,
5086 * Invalidate by VA range, Inner/Outer Shareable EL1&0.
5087 * Currently handles all of RVAE1IS, RVAE1OS, RVAAE1IS, RVAAE1OS,
5088 * RVAALE1IS, RVAALE1OS, RVALE1IS and RVALE1OS, since we don't support
5089 * flush-for-specific-ASID-only, flush-last-level-only or inner/outer
5090 * shareable specific flushes.
5093 do_rvae_write(env
, value
, vae1_tlbmask(env
), true);
5096 static void tlbi_aa64_rvae2_write(CPUARMState
*env
,
5097 const ARMCPRegInfo
*ri
,
5101 * Invalidate by VA range, EL2.
5102 * Currently handles all of RVAE2 and RVALE2,
5103 * since we don't support flush-for-specific-ASID-only or
5104 * flush-last-level-only.
5107 do_rvae_write(env
, value
, vae2_tlbmask(env
),
5108 tlb_force_broadcast(env
));
5113 static void tlbi_aa64_rvae2is_write(CPUARMState
*env
,
5114 const ARMCPRegInfo
*ri
,
5118 * Invalidate by VA range, Inner/Outer Shareable, EL2.
5119 * Currently handles all of RVAE2IS, RVAE2OS, RVALE2IS and RVALE2OS,
5120 * since we don't support flush-for-specific-ASID-only,
5121 * flush-last-level-only or inner/outer shareable specific flushes.
5124 do_rvae_write(env
, value
, vae2_tlbmask(env
), true);
5128 static void tlbi_aa64_rvae3_write(CPUARMState
*env
,
5129 const ARMCPRegInfo
*ri
,
5133 * Invalidate by VA range, EL3.
5134 * Currently handles all of RVAE3 and RVALE3,
5135 * since we don't support flush-for-specific-ASID-only or
5136 * flush-last-level-only.
5139 do_rvae_write(env
, value
, ARMMMUIdxBit_E3
, tlb_force_broadcast(env
));
5142 static void tlbi_aa64_rvae3is_write(CPUARMState
*env
,
5143 const ARMCPRegInfo
*ri
,
5147 * Invalidate by VA range, EL3, Inner/Outer Shareable.
5148 * Currently handles all of RVAE3IS, RVAE3OS, RVALE3IS and RVALE3OS,
5149 * since we don't support flush-for-specific-ASID-only,
5150 * flush-last-level-only or inner/outer specific flushes.
5153 do_rvae_write(env
, value
, ARMMMUIdxBit_E3
, true);
5156 static void tlbi_aa64_ripas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5159 do_rvae_write(env
, value
, ipas2e1_tlbmask(env
, value
),
5160 tlb_force_broadcast(env
));
5163 static void tlbi_aa64_ripas2e1is_write(CPUARMState
*env
,
5164 const ARMCPRegInfo
*ri
,
5167 do_rvae_write(env
, value
, ipas2e1_tlbmask(env
, value
), true);
5171 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5174 int cur_el
= arm_current_el(env
);
5177 uint64_t hcr
= arm_hcr_el2_eff(env
);
5180 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
5181 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_DZE
)) {
5182 return CP_ACCESS_TRAP_EL2
;
5185 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_DZE
)) {
5186 return CP_ACCESS_TRAP
;
5188 if (hcr
& HCR_TDZ
) {
5189 return CP_ACCESS_TRAP_EL2
;
5192 } else if (hcr
& HCR_TDZ
) {
5193 return CP_ACCESS_TRAP_EL2
;
5196 return CP_ACCESS_OK
;
5199 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5201 ARMCPU
*cpu
= env_archcpu(env
);
5202 int dzp_bit
= 1 << 4;
5204 /* DZP indicates whether DC ZVA access is allowed */
5205 if (aa64_zva_access(env
, NULL
, false) == CP_ACCESS_OK
) {
5208 return cpu
->dcz_blocksize
| dzp_bit
;
5211 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5214 if (!(env
->pstate
& PSTATE_SP
)) {
5216 * Access to SP_EL0 is undefined if it's being used as
5217 * the stack pointer.
5219 return CP_ACCESS_TRAP_UNCATEGORIZED
;
5221 return CP_ACCESS_OK
;
5224 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5226 return env
->pstate
& PSTATE_SP
;
5229 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
5231 update_spsel(env
, val
);
5234 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5237 ARMCPU
*cpu
= env_archcpu(env
);
5239 if (arm_feature(env
, ARM_FEATURE_PMSA
) && !cpu
->has_mpu
) {
5240 /* M bit is RAZ/WI for PMSA with no MPU implemented */
5244 /* ??? Lots of these bits are not implemented. */
5246 if (ri
->state
== ARM_CP_STATE_AA64
&& !cpu_isar_feature(aa64_mte
, cpu
)) {
5247 if (ri
->opc1
== 6) { /* SCTLR_EL3 */
5248 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF
| SCTLR_ATA
);
5250 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF0
| SCTLR_TCF
|
5251 SCTLR_ATA0
| SCTLR_ATA
);
5255 if (raw_read(env
, ri
) == value
) {
5257 * Skip the TLB flush if nothing actually changed; Linux likes
5258 * to do a lot of pointless SCTLR writes.
5263 raw_write(env
, ri
, value
);
5265 /* This may enable/disable the MMU, so do a TLB flush. */
5266 tlb_flush(CPU(cpu
));
5268 if (tcg_enabled() && ri
->type
& ARM_CP_SUPPRESS_TB_END
) {
5270 * Normally we would always end the TB on an SCTLR write; see the
5271 * comment in ARMCPRegInfo sctlr initialization below for why Xscale
5272 * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild
5273 * of hflags from the translator, so do it here.
5275 arm_rebuild_hflags(env
);
5279 static void mdcr_el3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5283 * Some MDCR_EL3 bits affect whether PMU counters are running:
5284 * if we are trying to change any of those then we must
5285 * bracket this update with PMU start/finish calls.
5287 bool pmu_op
= (env
->cp15
.mdcr_el3
^ value
) & MDCR_EL3_PMU_ENABLE_BITS
;
5292 env
->cp15
.mdcr_el3
= value
;
5298 static void sdcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5301 /* Not all bits defined for MDCR_EL3 exist in the AArch32 SDCR */
5302 mdcr_el3_write(env
, ri
, value
& SDCR_VALID_MASK
);
5305 static void mdcr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5309 * Some MDCR_EL2 bits affect whether PMU counters are running:
5310 * if we are trying to change any of those then we must
5311 * bracket this update with PMU start/finish calls.
5313 bool pmu_op
= (env
->cp15
.mdcr_el2
^ value
) & MDCR_EL2_PMU_ENABLE_BITS
;
5318 env
->cp15
.mdcr_el2
= value
;
5324 #ifdef CONFIG_USER_ONLY
5326 * `IC IVAU` is handled to improve compatibility with JITs that dual-map their
5327 * code to get around W^X restrictions, where one region is writable and the
5328 * other is executable.
5330 * Since the executable region is never written to we cannot detect code
5331 * changes when running in user mode, and rely on the emulated JIT telling us
5332 * that the code has changed by executing this instruction.
5334 static void ic_ivau_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5337 uint64_t icache_line_mask
, start_address
, end_address
;
5340 cpu
= env_archcpu(env
);
5342 icache_line_mask
= (4 << extract32(cpu
->ctr
, 0, 4)) - 1;
5343 start_address
= value
& ~icache_line_mask
;
5344 end_address
= value
| icache_line_mask
;
5348 tb_invalidate_phys_range(start_address
, end_address
);
5354 static const ARMCPRegInfo v8_cp_reginfo
[] = {
5356 * Minimal set of EL0-visible registers. This will need to be expanded
5357 * significantly for system emulation of AArch64 CPUs.
5359 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
5360 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
5361 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
5362 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
5363 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
5364 .type
= ARM_CP_NO_RAW
,
5365 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
5366 .fieldoffset
= offsetof(CPUARMState
, daif
),
5367 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
5368 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
5369 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
5370 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
5371 .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
5372 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
5373 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
5374 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
5375 .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
5376 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
5377 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
5378 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
,
5379 .fgt
= FGT_DCZID_EL0
,
5380 .readfn
= aa64_dczid_read
},
5381 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
5382 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
5383 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
5384 #ifndef CONFIG_USER_ONLY
5385 /* Avoid overhead of an access check that always passes in user-mode */
5386 .accessfn
= aa64_zva_access
,
5390 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
5391 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
5392 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
5394 * Instruction cache ops. All of these except `IC IVAU` NOP because we
5395 * don't emulate caches.
5397 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
5398 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
5399 .access
= PL1_W
, .type
= ARM_CP_NOP
,
5400 .fgt
= FGT_ICIALLUIS
,
5401 .accessfn
= access_ticab
},
5402 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
5403 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
5404 .access
= PL1_W
, .type
= ARM_CP_NOP
,
5406 .accessfn
= access_tocu
},
5407 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
5408 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
5411 .accessfn
= access_tocu
,
5412 #ifdef CONFIG_USER_ONLY
5413 .type
= ARM_CP_NO_RAW
,
5414 .writefn
= ic_ivau_write
5419 /* Cache ops: all NOPs since we don't emulate caches */
5420 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
5421 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
5422 .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
,
5424 .type
= ARM_CP_NOP
},
5425 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
5426 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
5428 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
5429 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
5430 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
5431 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5433 .accessfn
= aa64_cacheop_poc_access
},
5434 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
5435 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
5437 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
5438 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
5439 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
5440 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5442 .accessfn
= access_tocu
},
5443 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
5444 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
5445 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5447 .accessfn
= aa64_cacheop_poc_access
},
5448 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
5449 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
5451 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
5452 /* TLBI operations */
5453 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
5454 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
5455 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5456 .fgt
= FGT_TLBIVMALLE1IS
,
5457 .writefn
= tlbi_aa64_vmalle1is_write
},
5458 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
5459 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
5460 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5461 .fgt
= FGT_TLBIVAE1IS
,
5462 .writefn
= tlbi_aa64_vae1is_write
},
5463 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
5464 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
5465 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5466 .fgt
= FGT_TLBIASIDE1IS
,
5467 .writefn
= tlbi_aa64_vmalle1is_write
},
5468 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
5469 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
5470 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5471 .fgt
= FGT_TLBIVAAE1IS
,
5472 .writefn
= tlbi_aa64_vae1is_write
},
5473 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
5474 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
5475 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5476 .fgt
= FGT_TLBIVALE1IS
,
5477 .writefn
= tlbi_aa64_vae1is_write
},
5478 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
5479 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
5480 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5481 .fgt
= FGT_TLBIVAALE1IS
,
5482 .writefn
= tlbi_aa64_vae1is_write
},
5483 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
5484 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
5485 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5486 .fgt
= FGT_TLBIVMALLE1
,
5487 .writefn
= tlbi_aa64_vmalle1_write
},
5488 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
5489 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
5490 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5491 .fgt
= FGT_TLBIVAE1
,
5492 .writefn
= tlbi_aa64_vae1_write
},
5493 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
5494 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
5495 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5496 .fgt
= FGT_TLBIASIDE1
,
5497 .writefn
= tlbi_aa64_vmalle1_write
},
5498 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
5499 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
5500 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5501 .fgt
= FGT_TLBIVAAE1
,
5502 .writefn
= tlbi_aa64_vae1_write
},
5503 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
5504 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
5505 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5506 .fgt
= FGT_TLBIVALE1
,
5507 .writefn
= tlbi_aa64_vae1_write
},
5508 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
5509 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
5510 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5511 .fgt
= FGT_TLBIVAALE1
,
5512 .writefn
= tlbi_aa64_vae1_write
},
5513 { .name
= "TLBI_IPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
5514 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
5515 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5516 .writefn
= tlbi_aa64_ipas2e1is_write
},
5517 { .name
= "TLBI_IPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
5518 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
5519 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5520 .writefn
= tlbi_aa64_ipas2e1is_write
},
5521 { .name
= "TLBI_ALLE1IS", .state
= ARM_CP_STATE_AA64
,
5522 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
5523 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5524 .writefn
= tlbi_aa64_alle1is_write
},
5525 { .name
= "TLBI_VMALLS12E1IS", .state
= ARM_CP_STATE_AA64
,
5526 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 6,
5527 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5528 .writefn
= tlbi_aa64_alle1is_write
},
5529 { .name
= "TLBI_IPAS2E1", .state
= ARM_CP_STATE_AA64
,
5530 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
5531 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5532 .writefn
= tlbi_aa64_ipas2e1_write
},
5533 { .name
= "TLBI_IPAS2LE1", .state
= ARM_CP_STATE_AA64
,
5534 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
5535 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5536 .writefn
= tlbi_aa64_ipas2e1_write
},
5537 { .name
= "TLBI_ALLE1", .state
= ARM_CP_STATE_AA64
,
5538 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
5539 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5540 .writefn
= tlbi_aa64_alle1_write
},
5541 { .name
= "TLBI_VMALLS12E1", .state
= ARM_CP_STATE_AA64
,
5542 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 6,
5543 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5544 .writefn
= tlbi_aa64_alle1is_write
},
5545 #ifndef CONFIG_USER_ONLY
5546 /* 64 bit address translation operations */
5547 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
5548 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
5549 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5551 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5552 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
5553 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
5554 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5556 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5557 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
5558 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
5559 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5561 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5562 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
5563 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
5564 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5566 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5567 { .name
= "AT_S12E1R", .state
= ARM_CP_STATE_AA64
,
5568 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 4,
5569 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5570 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5571 { .name
= "AT_S12E1W", .state
= ARM_CP_STATE_AA64
,
5572 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 5,
5573 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5574 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5575 { .name
= "AT_S12E0R", .state
= ARM_CP_STATE_AA64
,
5576 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 6,
5577 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5578 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5579 { .name
= "AT_S12E0W", .state
= ARM_CP_STATE_AA64
,
5580 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 7,
5581 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5582 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5583 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
5584 { .name
= "AT_S1E3R", .state
= ARM_CP_STATE_AA64
,
5585 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 0,
5586 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5587 .writefn
= ats_write64
},
5588 { .name
= "AT_S1E3W", .state
= ARM_CP_STATE_AA64
,
5589 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 1,
5590 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5591 .writefn
= ats_write64
},
5592 { .name
= "PAR_EL1", .state
= ARM_CP_STATE_AA64
,
5593 .type
= ARM_CP_ALIAS
,
5594 .opc0
= 3, .opc1
= 0, .crn
= 7, .crm
= 4, .opc2
= 0,
5595 .access
= PL1_RW
, .resetvalue
= 0,
5597 .fieldoffset
= offsetof(CPUARMState
, cp15
.par_el
[1]),
5598 .writefn
= par_write
},
5600 /* TLB invalidate last level of translation table walk */
5601 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
5602 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
5603 .writefn
= tlbimva_is_write
},
5604 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
5605 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
5606 .writefn
= tlbimvaa_is_write
},
5607 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
5608 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
5609 .writefn
= tlbimva_write
},
5610 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
5611 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
5612 .writefn
= tlbimvaa_write
},
5613 { .name
= "TLBIMVALH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
5614 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5615 .writefn
= tlbimva_hyp_write
},
5616 { .name
= "TLBIMVALHIS",
5617 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
5618 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5619 .writefn
= tlbimva_hyp_is_write
},
5620 { .name
= "TLBIIPAS2",
5621 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
5622 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5623 .writefn
= tlbiipas2_hyp_write
},
5624 { .name
= "TLBIIPAS2IS",
5625 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
5626 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5627 .writefn
= tlbiipas2is_hyp_write
},
5628 { .name
= "TLBIIPAS2L",
5629 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
5630 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5631 .writefn
= tlbiipas2_hyp_write
},
5632 { .name
= "TLBIIPAS2LIS",
5633 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
5634 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5635 .writefn
= tlbiipas2is_hyp_write
},
5636 /* 32 bit cache operations */
5637 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
5638 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_ticab
},
5639 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
5640 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5641 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
5642 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tocu
},
5643 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
5644 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tocu
},
5645 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
5646 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5647 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
5648 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5649 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
5650 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5651 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
5652 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5653 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
5654 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5655 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
5656 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5657 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
5658 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tocu
},
5659 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
5660 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5661 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
5662 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5663 /* MMU Domain access control / MPU write buffer control */
5664 { .name
= "DACR", .cp
= 15, .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
5665 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
5666 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5667 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
5668 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
5669 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
5670 .type
= ARM_CP_ALIAS
,
5671 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
5673 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
5674 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
5675 .type
= ARM_CP_ALIAS
,
5676 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
5678 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_SVC
]) },
5680 * We rely on the access checks not allowing the guest to write to the
5681 * state field when SPSel indicates that it's being used as the stack
5684 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
5685 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
5686 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
5687 .type
= ARM_CP_ALIAS
,
5688 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
5689 { .name
= "SP_EL1", .state
= ARM_CP_STATE_AA64
,
5690 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 1, .opc2
= 0,
5691 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_KEEP
,
5692 .fieldoffset
= offsetof(CPUARMState
, sp_el
[1]) },
5693 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
5694 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
5695 .type
= ARM_CP_NO_RAW
,
5696 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
5697 { .name
= "FPEXC32_EL2", .state
= ARM_CP_STATE_AA64
,
5698 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 3, .opc2
= 0,
5700 .type
= ARM_CP_ALIAS
| ARM_CP_FPU
| ARM_CP_EL3_NO_EL2_KEEP
,
5701 .fieldoffset
= offsetof(CPUARMState
, vfp
.xregs
[ARM_VFP_FPEXC
]) },
5702 { .name
= "DACR32_EL2", .state
= ARM_CP_STATE_AA64
,
5703 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 0, .opc2
= 0,
5704 .access
= PL2_RW
, .resetvalue
= 0, .type
= ARM_CP_EL3_NO_EL2_KEEP
,
5705 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5706 .fieldoffset
= offsetof(CPUARMState
, cp15
.dacr32_el2
) },
5707 { .name
= "IFSR32_EL2", .state
= ARM_CP_STATE_AA64
,
5708 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 0, .opc2
= 1,
5709 .access
= PL2_RW
, .resetvalue
= 0, .type
= ARM_CP_EL3_NO_EL2_KEEP
,
5710 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr32_el2
) },
5711 { .name
= "SPSR_IRQ", .state
= ARM_CP_STATE_AA64
,
5712 .type
= ARM_CP_ALIAS
,
5713 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 0,
5715 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_IRQ
]) },
5716 { .name
= "SPSR_ABT", .state
= ARM_CP_STATE_AA64
,
5717 .type
= ARM_CP_ALIAS
,
5718 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 1,
5720 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_ABT
]) },
5721 { .name
= "SPSR_UND", .state
= ARM_CP_STATE_AA64
,
5722 .type
= ARM_CP_ALIAS
,
5723 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 2,
5725 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_UND
]) },
5726 { .name
= "SPSR_FIQ", .state
= ARM_CP_STATE_AA64
,
5727 .type
= ARM_CP_ALIAS
,
5728 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 3,
5730 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_FIQ
]) },
5731 { .name
= "MDCR_EL3", .state
= ARM_CP_STATE_AA64
,
5733 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 3, .opc2
= 1,
5736 .writefn
= mdcr_el3_write
,
5737 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el3
) },
5738 { .name
= "SDCR", .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5739 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 1,
5740 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5741 .writefn
= sdcr_write
,
5742 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.mdcr_el3
) },
5745 static void do_hcr_write(CPUARMState
*env
, uint64_t value
, uint64_t valid_mask
)
5747 ARMCPU
*cpu
= env_archcpu(env
);
5749 if (arm_feature(env
, ARM_FEATURE_V8
)) {
5750 valid_mask
|= MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */
5752 valid_mask
|= MAKE_64BIT_MASK(0, 28); /* ARMv7VE */
5755 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5756 valid_mask
&= ~HCR_HCD
;
5757 } else if (cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
5759 * Architecturally HCR.TSC is RES0 if EL3 is not implemented.
5760 * However, if we're using the SMC PSCI conduit then QEMU is
5761 * effectively acting like EL3 firmware and so the guest at
5762 * EL2 should retain the ability to prevent EL1 from being
5763 * able to make SMC calls into the ersatz firmware, so in
5764 * that case HCR.TSC should be read/write.
5766 valid_mask
&= ~HCR_TSC
;
5769 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5770 if (cpu_isar_feature(aa64_vh
, cpu
)) {
5771 valid_mask
|= HCR_E2H
;
5773 if (cpu_isar_feature(aa64_ras
, cpu
)) {
5774 valid_mask
|= HCR_TERR
| HCR_TEA
;
5776 if (cpu_isar_feature(aa64_lor
, cpu
)) {
5777 valid_mask
|= HCR_TLOR
;
5779 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
5780 valid_mask
|= HCR_API
| HCR_APK
;
5782 if (cpu_isar_feature(aa64_mte
, cpu
)) {
5783 valid_mask
|= HCR_ATA
| HCR_DCT
| HCR_TID5
;
5785 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
5786 valid_mask
|= HCR_ENSCXT
;
5788 if (cpu_isar_feature(aa64_fwb
, cpu
)) {
5789 valid_mask
|= HCR_FWB
;
5791 if (cpu_isar_feature(aa64_rme
, cpu
)) {
5792 valid_mask
|= HCR_GPF
;
5796 if (cpu_isar_feature(any_evt
, cpu
)) {
5797 valid_mask
|= HCR_TTLBIS
| HCR_TTLBOS
| HCR_TICAB
| HCR_TOCU
| HCR_TID4
;
5798 } else if (cpu_isar_feature(any_half_evt
, cpu
)) {
5799 valid_mask
|= HCR_TICAB
| HCR_TOCU
| HCR_TID4
;
5802 /* Clear RES0 bits. */
5803 value
&= valid_mask
;
5806 * These bits change the MMU setup:
5807 * HCR_VM enables stage 2 translation
5808 * HCR_PTW forbids certain page-table setups
5809 * HCR_DC disables stage1 and enables stage2 translation
5810 * HCR_DCT enables tagging on (disabled) stage1 translation
5811 * HCR_FWB changes the interpretation of stage2 descriptor bits
5813 if ((env
->cp15
.hcr_el2
^ value
) &
5814 (HCR_VM
| HCR_PTW
| HCR_DC
| HCR_DCT
| HCR_FWB
)) {
5815 tlb_flush(CPU(cpu
));
5817 env
->cp15
.hcr_el2
= value
;
5820 * Updates to VI and VF require us to update the status of
5821 * virtual interrupts, which are the logical OR of these bits
5822 * and the state of the input lines from the GIC. (This requires
5823 * that we have the iothread lock, which is done by marking the
5824 * reginfo structs as ARM_CP_IO.)
5825 * Note that if a write to HCR pends a VIRQ or VFIQ it is never
5826 * possible for it to be taken immediately, because VIRQ and
5827 * VFIQ are masked unless running at EL0 or EL1, and HCR
5828 * can only be written at EL2.
5830 g_assert(qemu_mutex_iothread_locked());
5831 arm_cpu_update_virq(cpu
);
5832 arm_cpu_update_vfiq(cpu
);
5833 arm_cpu_update_vserr(cpu
);
5836 static void hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
5838 do_hcr_write(env
, value
, 0);
5841 static void hcr_writehigh(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5844 /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */
5845 value
= deposit64(env
->cp15
.hcr_el2
, 32, 32, value
);
5846 do_hcr_write(env
, value
, MAKE_64BIT_MASK(0, 32));
5849 static void hcr_writelow(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5852 /* Handle HCR write, i.e. write to low half of HCR_EL2 */
5853 value
= deposit64(env
->cp15
.hcr_el2
, 0, 32, value
);
5854 do_hcr_write(env
, value
, MAKE_64BIT_MASK(32, 32));
5858 * Return the effective value of HCR_EL2, at the given security state.
5859 * Bits that are not included here:
5860 * RW (read from SCR_EL3.RW as needed)
5862 uint64_t arm_hcr_el2_eff_secstate(CPUARMState
*env
, ARMSecuritySpace space
)
5864 uint64_t ret
= env
->cp15
.hcr_el2
;
5866 assert(space
!= ARMSS_Root
);
5868 if (!arm_is_el2_enabled_secstate(env
, space
)) {
5870 * "This register has no effect if EL2 is not enabled in the
5871 * current Security state". This is ARMv8.4-SecEL2 speak for
5872 * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1).
5874 * Prior to that, the language was "In an implementation that
5875 * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
5876 * as if this field is 0 for all purposes other than a direct
5877 * read or write access of HCR_EL2". With lots of enumeration
5878 * on a per-field basis. In current QEMU, this is condition
5879 * is arm_is_secure_below_el3.
5881 * Since the v8.4 language applies to the entire register, and
5882 * appears to be backward compatible, use that.
5888 * For a cpu that supports both aarch64 and aarch32, we can set bits
5889 * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32.
5890 * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32.
5892 if (!arm_el_is_aa64(env
, 2)) {
5893 uint64_t aa32_valid
;
5896 * These bits are up-to-date as of ARMv8.6.
5897 * For HCR, it's easiest to list just the 2 bits that are invalid.
5898 * For HCR2, list those that are valid.
5900 aa32_valid
= MAKE_64BIT_MASK(0, 32) & ~(HCR_RW
| HCR_TDZ
);
5901 aa32_valid
|= (HCR_CD
| HCR_ID
| HCR_TERR
| HCR_TEA
| HCR_MIOCNCE
|
5902 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_TTLBIS
);
5906 if (ret
& HCR_TGE
) {
5907 /* These bits are up-to-date as of ARMv8.6. */
5908 if (ret
& HCR_E2H
) {
5909 ret
&= ~(HCR_VM
| HCR_FMO
| HCR_IMO
| HCR_AMO
|
5910 HCR_BSU_MASK
| HCR_DC
| HCR_TWI
| HCR_TWE
|
5911 HCR_TID0
| HCR_TID2
| HCR_TPCP
| HCR_TPU
|
5912 HCR_TDZ
| HCR_CD
| HCR_ID
| HCR_MIOCNCE
|
5913 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_ENSCXT
|
5914 HCR_TTLBIS
| HCR_TTLBOS
| HCR_TID5
);
5916 ret
|= HCR_FMO
| HCR_IMO
| HCR_AMO
;
5918 ret
&= ~(HCR_SWIO
| HCR_PTW
| HCR_VF
| HCR_VI
| HCR_VSE
|
5919 HCR_FB
| HCR_TID1
| HCR_TID3
| HCR_TSC
| HCR_TACR
|
5920 HCR_TSW
| HCR_TTLB
| HCR_TVM
| HCR_HCD
| HCR_TRVM
|
5927 uint64_t arm_hcr_el2_eff(CPUARMState
*env
)
5929 if (arm_feature(env
, ARM_FEATURE_M
)) {
5932 return arm_hcr_el2_eff_secstate(env
, arm_security_space_below_el3(env
));
5936 * Corresponds to ARM pseudocode function ELIsInHost().
5938 bool el_is_in_host(CPUARMState
*env
, int el
)
5943 * Since we only care about E2H and TGE, we can skip arm_hcr_el2_eff().
5944 * Perform the simplest bit tests first, and validate EL2 afterward.
5947 return false; /* EL1 or EL3 */
5951 * Note that hcr_write() checks isar_feature_aa64_vh(),
5952 * aka HaveVirtHostExt(), in allowing HCR_E2H to be set.
5954 mask
= el
? HCR_E2H
: HCR_E2H
| HCR_TGE
;
5955 if ((env
->cp15
.hcr_el2
& mask
) != mask
) {
5959 /* TGE and/or E2H set: double check those bits are currently legal. */
5960 return arm_is_el2_enabled(env
) && arm_el_is_aa64(env
, 2);
5963 static void hcrx_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5966 uint64_t valid_mask
= 0;
5968 /* FEAT_MOPS adds MSCEn and MCE2 */
5969 if (cpu_isar_feature(aa64_mops
, env_archcpu(env
))) {
5970 valid_mask
|= HCRX_MSCEN
| HCRX_MCE2
;
5973 /* Clear RES0 bits. */
5974 env
->cp15
.hcrx_el2
= value
& valid_mask
;
5977 static CPAccessResult
access_hxen(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5980 if (arm_current_el(env
) < 3
5981 && arm_feature(env
, ARM_FEATURE_EL3
)
5982 && !(env
->cp15
.scr_el3
& SCR_HXEN
)) {
5983 return CP_ACCESS_TRAP_EL3
;
5985 return CP_ACCESS_OK
;
5988 static const ARMCPRegInfo hcrx_el2_reginfo
= {
5989 .name
= "HCRX_EL2", .state
= ARM_CP_STATE_AA64
,
5990 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 2,
5991 .access
= PL2_RW
, .writefn
= hcrx_write
, .accessfn
= access_hxen
,
5992 .fieldoffset
= offsetof(CPUARMState
, cp15
.hcrx_el2
),
5995 /* Return the effective value of HCRX_EL2. */
5996 uint64_t arm_hcrx_el2_eff(CPUARMState
*env
)
5999 * The bits in this register behave as 0 for all purposes other than
6000 * direct reads of the register if SCR_EL3.HXEn is 0.
6001 * If EL2 is not enabled in the current security state, then the
6002 * bit may behave as if 0, or as if 1, depending on the bit.
6003 * For the moment, we treat the EL2-disabled case as taking
6004 * priority over the HXEn-disabled case. This is true for the only
6005 * bit for a feature which we implement where the answer is different
6006 * for the two cases (MSCEn for FEAT_MOPS).
6007 * This may need to be revisited for future bits.
6009 if (!arm_is_el2_enabled(env
)) {
6011 if (cpu_isar_feature(aa64_mops
, env_archcpu(env
))) {
6012 /* MSCEn behaves as 1 if EL2 is not enabled */
6017 if (arm_feature(env
, ARM_FEATURE_EL3
) && !(env
->cp15
.scr_el3
& SCR_HXEN
)) {
6020 return env
->cp15
.hcrx_el2
;
6023 static void cptr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6027 * For A-profile AArch32 EL3, if NSACR.CP10
6028 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
6030 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
6031 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
6032 uint64_t mask
= R_HCPTR_TCP11_MASK
| R_HCPTR_TCP10_MASK
;
6033 value
= (value
& ~mask
) | (env
->cp15
.cptr_el
[2] & mask
);
6035 env
->cp15
.cptr_el
[2] = value
;
6038 static uint64_t cptr_el2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6041 * For A-profile AArch32 EL3, if NSACR.CP10
6042 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
6044 uint64_t value
= env
->cp15
.cptr_el
[2];
6046 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
6047 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
6048 value
|= R_HCPTR_TCP11_MASK
| R_HCPTR_TCP10_MASK
;
6053 static const ARMCPRegInfo el2_cp_reginfo
[] = {
6054 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
6056 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
6057 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
6058 .writefn
= hcr_write
, .raw_writefn
= raw_write
},
6059 { .name
= "HCR", .state
= ARM_CP_STATE_AA32
,
6060 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
6061 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
6062 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
6063 .writefn
= hcr_writelow
},
6064 { .name
= "HACR_EL2", .state
= ARM_CP_STATE_BOTH
,
6065 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 7,
6066 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6067 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
6068 .type
= ARM_CP_ALIAS
,
6069 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
6071 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
6072 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_BOTH
,
6073 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
6074 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
6075 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_BOTH
,
6076 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
6077 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
6078 { .name
= "HIFAR", .state
= ARM_CP_STATE_AA32
,
6079 .type
= ARM_CP_ALIAS
,
6080 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 2,
6082 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.far_el
[2]) },
6083 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
6084 .type
= ARM_CP_ALIAS
,
6085 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
6087 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_HYP
]) },
6088 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_BOTH
,
6089 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
6090 .access
= PL2_RW
, .writefn
= vbar_write
,
6091 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
6093 { .name
= "SP_EL2", .state
= ARM_CP_STATE_AA64
,
6094 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 1, .opc2
= 0,
6095 .access
= PL3_RW
, .type
= ARM_CP_ALIAS
,
6096 .fieldoffset
= offsetof(CPUARMState
, sp_el
[2]) },
6097 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
6098 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
6099 .access
= PL2_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
6100 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[2]),
6101 .readfn
= cptr_el2_read
, .writefn
= cptr_el2_write
},
6102 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
6103 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
6104 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[2]),
6106 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
6107 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
6108 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
6109 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el
[2]) },
6110 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
6111 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
6112 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6114 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
6115 { .name
= "HAMAIR1", .state
= ARM_CP_STATE_AA32
,
6116 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
6117 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6119 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
6120 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
6121 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6123 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
6124 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
6125 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6127 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
6128 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
6129 .access
= PL2_RW
, .writefn
= vmsa_tcr_el12_write
,
6130 .raw_writefn
= raw_write
,
6131 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[2]) },
6132 { .name
= "VTCR", .state
= ARM_CP_STATE_AA32
,
6133 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
6134 .type
= ARM_CP_ALIAS
,
6135 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
6136 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vtcr_el2
) },
6137 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_AA64
,
6138 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
6140 /* no .writefn needed as this can't cause an ASID change */
6141 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
6142 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
6143 .cp
= 15, .opc1
= 6, .crm
= 2,
6144 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
6145 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
6146 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
),
6147 .writefn
= vttbr_write
, .raw_writefn
= raw_write
},
6148 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
6149 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
6150 .access
= PL2_RW
, .writefn
= vttbr_write
, .raw_writefn
= raw_write
,
6151 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
) },
6152 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
6153 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
6154 .access
= PL2_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
6155 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[2]) },
6156 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
6157 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
6158 .access
= PL2_RW
, .resetvalue
= 0,
6159 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[2]) },
6160 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
6161 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
6162 .access
= PL2_RW
, .resetvalue
= 0,
6163 .writefn
= vmsa_tcr_ttbr_el2_write
, .raw_writefn
= raw_write
,
6164 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
6165 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
6166 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
6167 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
6168 { .name
= "TLBIALLNSNH",
6169 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
6170 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6171 .writefn
= tlbiall_nsnh_write
},
6172 { .name
= "TLBIALLNSNHIS",
6173 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
6174 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6175 .writefn
= tlbiall_nsnh_is_write
},
6176 { .name
= "TLBIALLH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
6177 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6178 .writefn
= tlbiall_hyp_write
},
6179 { .name
= "TLBIALLHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
6180 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6181 .writefn
= tlbiall_hyp_is_write
},
6182 { .name
= "TLBIMVAH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
6183 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6184 .writefn
= tlbimva_hyp_write
},
6185 { .name
= "TLBIMVAHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
6186 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6187 .writefn
= tlbimva_hyp_is_write
},
6188 { .name
= "TLBI_ALLE2", .state
= ARM_CP_STATE_AA64
,
6189 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
6190 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6191 .writefn
= tlbi_aa64_alle2_write
},
6192 { .name
= "TLBI_VAE2", .state
= ARM_CP_STATE_AA64
,
6193 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
6194 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6195 .writefn
= tlbi_aa64_vae2_write
},
6196 { .name
= "TLBI_VALE2", .state
= ARM_CP_STATE_AA64
,
6197 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
6198 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6199 .writefn
= tlbi_aa64_vae2_write
},
6200 { .name
= "TLBI_ALLE2IS", .state
= ARM_CP_STATE_AA64
,
6201 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
6202 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6203 .writefn
= tlbi_aa64_alle2is_write
},
6204 { .name
= "TLBI_VAE2IS", .state
= ARM_CP_STATE_AA64
,
6205 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
6206 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6207 .writefn
= tlbi_aa64_vae2is_write
},
6208 { .name
= "TLBI_VALE2IS", .state
= ARM_CP_STATE_AA64
,
6209 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
6210 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6211 .writefn
= tlbi_aa64_vae2is_write
},
6212 #ifndef CONFIG_USER_ONLY
6214 * Unlike the other EL2-related AT operations, these must
6215 * UNDEF from EL3 if EL2 is not implemented, which is why we
6216 * define them here rather than with the rest of the AT ops.
6218 { .name
= "AT_S1E2R", .state
= ARM_CP_STATE_AA64
,
6219 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
6220 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
6221 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
| ARM_CP_EL3_NO_EL2_UNDEF
,
6222 .writefn
= ats_write64
},
6223 { .name
= "AT_S1E2W", .state
= ARM_CP_STATE_AA64
,
6224 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
6225 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
6226 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
| ARM_CP_EL3_NO_EL2_UNDEF
,
6227 .writefn
= ats_write64
},
6229 * The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
6230 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
6231 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
6232 * to behave as if SCR.NS was 1.
6234 { .name
= "ATS1HR", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
6236 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
6237 { .name
= "ATS1HW", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
6239 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
6240 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
6241 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
6243 * ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
6244 * reset values as IMPDEF. We choose to reset to 3 to comply with
6245 * both ARMv7 and ARMv8.
6247 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 3,
6248 .writefn
= gt_cnthctl_write
, .raw_writefn
= raw_write
,
6249 .fieldoffset
= offsetof(CPUARMState
, cp15
.cnthctl_el2
) },
6250 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
6251 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
6252 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 0,
6253 .writefn
= gt_cntvoff_write
,
6254 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
6255 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
6256 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
| ARM_CP_IO
,
6257 .writefn
= gt_cntvoff_write
,
6258 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
6259 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
6260 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
6261 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
6262 .type
= ARM_CP_IO
, .access
= PL2_RW
,
6263 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
6264 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
6265 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
6266 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_IO
,
6267 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
6268 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
6269 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
6270 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
6271 .resetfn
= gt_hyp_timer_reset
,
6272 .readfn
= gt_hyp_tval_read
, .writefn
= gt_hyp_tval_write
},
6273 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
6275 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
6277 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].ctl
),
6279 .writefn
= gt_hyp_ctl_write
, .raw_writefn
= raw_write
},
6281 { .name
= "HPFAR", .state
= ARM_CP_STATE_AA32
,
6282 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
6283 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
6284 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
6285 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_AA64
,
6286 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
6288 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
6289 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
6290 .cp
= 15, .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
6292 .fieldoffset
= offsetof(CPUARMState
, cp15
.hstr_el2
) },
6295 static const ARMCPRegInfo el2_v8_cp_reginfo
[] = {
6296 { .name
= "HCR2", .state
= ARM_CP_STATE_AA32
,
6297 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
6298 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
6300 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.hcr_el2
),
6301 .writefn
= hcr_writehigh
},
6304 static CPAccessResult
sel2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6307 if (arm_current_el(env
) == 3 || arm_is_secure_below_el3(env
)) {
6308 return CP_ACCESS_OK
;
6310 return CP_ACCESS_TRAP_UNCATEGORIZED
;
6313 static const ARMCPRegInfo el2_sec_cp_reginfo
[] = {
6314 { .name
= "VSTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
6315 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 6, .opc2
= 0,
6316 .access
= PL2_RW
, .accessfn
= sel2_access
,
6317 .fieldoffset
= offsetof(CPUARMState
, cp15
.vsttbr_el2
) },
6318 { .name
= "VSTCR_EL2", .state
= ARM_CP_STATE_AA64
,
6319 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 6, .opc2
= 2,
6320 .access
= PL2_RW
, .accessfn
= sel2_access
,
6321 .fieldoffset
= offsetof(CPUARMState
, cp15
.vstcr_el2
) },
6324 static CPAccessResult
nsacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6328 * The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
6329 * At Secure EL1 it traps to EL3 or EL2.
6331 if (arm_current_el(env
) == 3) {
6332 return CP_ACCESS_OK
;
6334 if (arm_is_secure_below_el3(env
)) {
6335 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
6336 return CP_ACCESS_TRAP_EL2
;
6338 return CP_ACCESS_TRAP_EL3
;
6340 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
6342 return CP_ACCESS_OK
;
6344 return CP_ACCESS_TRAP_UNCATEGORIZED
;
6347 static const ARMCPRegInfo el3_cp_reginfo
[] = {
6348 { .name
= "SCR_EL3", .state
= ARM_CP_STATE_AA64
,
6349 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 0,
6350 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.scr_el3
),
6351 .resetfn
= scr_reset
, .writefn
= scr_write
, .raw_writefn
= raw_write
},
6352 { .name
= "SCR", .type
= ARM_CP_ALIAS
| ARM_CP_NEWEL
,
6353 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 0,
6354 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
6355 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.scr_el3
),
6356 .writefn
= scr_write
, .raw_writefn
= raw_write
},
6357 { .name
= "SDER32_EL3", .state
= ARM_CP_STATE_AA64
,
6358 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 1,
6359 .access
= PL3_RW
, .resetvalue
= 0,
6360 .fieldoffset
= offsetof(CPUARMState
, cp15
.sder
) },
6362 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 1,
6363 .access
= PL3_RW
, .resetvalue
= 0,
6364 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.sder
) },
6365 { .name
= "MVBAR", .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
6366 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
6367 .writefn
= vbar_write
, .resetvalue
= 0,
6368 .fieldoffset
= offsetof(CPUARMState
, cp15
.mvbar
) },
6369 { .name
= "TTBR0_EL3", .state
= ARM_CP_STATE_AA64
,
6370 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 0,
6371 .access
= PL3_RW
, .resetvalue
= 0,
6372 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[3]) },
6373 { .name
= "TCR_EL3", .state
= ARM_CP_STATE_AA64
,
6374 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 2,
6376 /* no .writefn needed as this can't cause an ASID change */
6378 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[3]) },
6379 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
6380 .type
= ARM_CP_ALIAS
,
6381 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
6383 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
6384 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
6385 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
6386 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
6387 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
6388 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
6389 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
6390 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
6391 .type
= ARM_CP_ALIAS
,
6392 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
6394 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_MON
]) },
6395 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
6396 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
6397 .access
= PL3_RW
, .writefn
= vbar_write
,
6398 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
6400 { .name
= "CPTR_EL3", .state
= ARM_CP_STATE_AA64
,
6401 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 2,
6402 .access
= PL3_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
6403 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[3]) },
6404 { .name
= "TPIDR_EL3", .state
= ARM_CP_STATE_AA64
,
6405 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 2,
6406 .access
= PL3_RW
, .resetvalue
= 0,
6407 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[3]) },
6408 { .name
= "AMAIR_EL3", .state
= ARM_CP_STATE_AA64
,
6409 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 3, .opc2
= 0,
6410 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6412 { .name
= "AFSR0_EL3", .state
= ARM_CP_STATE_BOTH
,
6413 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 0,
6414 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6416 { .name
= "AFSR1_EL3", .state
= ARM_CP_STATE_BOTH
,
6417 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 1,
6418 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6420 { .name
= "TLBI_ALLE3IS", .state
= ARM_CP_STATE_AA64
,
6421 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 0,
6422 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6423 .writefn
= tlbi_aa64_alle3is_write
},
6424 { .name
= "TLBI_VAE3IS", .state
= ARM_CP_STATE_AA64
,
6425 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 1,
6426 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6427 .writefn
= tlbi_aa64_vae3is_write
},
6428 { .name
= "TLBI_VALE3IS", .state
= ARM_CP_STATE_AA64
,
6429 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 5,
6430 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6431 .writefn
= tlbi_aa64_vae3is_write
},
6432 { .name
= "TLBI_ALLE3", .state
= ARM_CP_STATE_AA64
,
6433 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 0,
6434 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6435 .writefn
= tlbi_aa64_alle3_write
},
6436 { .name
= "TLBI_VAE3", .state
= ARM_CP_STATE_AA64
,
6437 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 1,
6438 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6439 .writefn
= tlbi_aa64_vae3_write
},
6440 { .name
= "TLBI_VALE3", .state
= ARM_CP_STATE_AA64
,
6441 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 5,
6442 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6443 .writefn
= tlbi_aa64_vae3_write
},
6446 #ifndef CONFIG_USER_ONLY
6447 /* Test if system register redirection is to occur in the current state. */
6448 static bool redirect_for_e2h(CPUARMState
*env
)
6450 return arm_current_el(env
) == 2 && (arm_hcr_el2_eff(env
) & HCR_E2H
);
6453 static uint64_t el2_e2h_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6457 if (redirect_for_e2h(env
)) {
6458 /* Switch to the saved EL2 version of the register. */
6460 readfn
= ri
->readfn
;
6462 readfn
= ri
->orig_readfn
;
6464 if (readfn
== NULL
) {
6467 return readfn(env
, ri
);
6470 static void el2_e2h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6475 if (redirect_for_e2h(env
)) {
6476 /* Switch to the saved EL2 version of the register. */
6478 writefn
= ri
->writefn
;
6480 writefn
= ri
->orig_writefn
;
6482 if (writefn
== NULL
) {
6483 writefn
= raw_write
;
6485 writefn(env
, ri
, value
);
6488 static void define_arm_vh_e2h_redirects_aliases(ARMCPU
*cpu
)
6491 uint32_t src_key
, dst_key
, new_key
;
6492 const char *src_name
, *dst_name
, *new_name
;
6493 bool (*feature
)(const ARMISARegisters
*id
);
6496 #define K(op0, op1, crn, crm, op2) \
6497 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
6499 static const struct E2HAlias aliases
[] = {
6500 { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0),
6501 "SCTLR", "SCTLR_EL2", "SCTLR_EL12" },
6502 { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2),
6503 "CPACR", "CPTR_EL2", "CPACR_EL12" },
6504 { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0),
6505 "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" },
6506 { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1),
6507 "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" },
6508 { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2),
6509 "TCR_EL1", "TCR_EL2", "TCR_EL12" },
6510 { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0),
6511 "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" },
6512 { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1),
6513 "ELR_EL1", "ELR_EL2", "ELR_EL12" },
6514 { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0),
6515 "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" },
6516 { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1),
6517 "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" },
6518 { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0),
6519 "ESR_EL1", "ESR_EL2", "ESR_EL12" },
6520 { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0),
6521 "FAR_EL1", "FAR_EL2", "FAR_EL12" },
6522 { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0),
6523 "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" },
6524 { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0),
6525 "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" },
6526 { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0),
6527 "VBAR", "VBAR_EL2", "VBAR_EL12" },
6528 { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1),
6529 "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" },
6530 { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0),
6531 "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" },
6534 * Note that redirection of ZCR is mentioned in the description
6535 * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but
6536 * not in the summary table.
6538 { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0),
6539 "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve
},
6540 { K(3, 0, 1, 2, 6), K(3, 4, 1, 2, 6), K(3, 5, 1, 2, 6),
6541 "SMCR_EL1", "SMCR_EL2", "SMCR_EL12", isar_feature_aa64_sme
},
6543 { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0),
6544 "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte
},
6546 { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7),
6547 "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12",
6548 isar_feature_aa64_scxtnum
},
6550 /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
6551 /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
6557 for (i
= 0; i
< ARRAY_SIZE(aliases
); i
++) {
6558 const struct E2HAlias
*a
= &aliases
[i
];
6559 ARMCPRegInfo
*src_reg
, *dst_reg
, *new_reg
;
6562 if (a
->feature
&& !a
->feature(&cpu
->isar
)) {
6566 src_reg
= g_hash_table_lookup(cpu
->cp_regs
,
6567 (gpointer
)(uintptr_t)a
->src_key
);
6568 dst_reg
= g_hash_table_lookup(cpu
->cp_regs
,
6569 (gpointer
)(uintptr_t)a
->dst_key
);
6570 g_assert(src_reg
!= NULL
);
6571 g_assert(dst_reg
!= NULL
);
6573 /* Cross-compare names to detect typos in the keys. */
6574 g_assert(strcmp(src_reg
->name
, a
->src_name
) == 0);
6575 g_assert(strcmp(dst_reg
->name
, a
->dst_name
) == 0);
6577 /* None of the core system registers use opaque; we will. */
6578 g_assert(src_reg
->opaque
== NULL
);
6580 /* Create alias before redirection so we dup the right data. */
6581 new_reg
= g_memdup(src_reg
, sizeof(ARMCPRegInfo
));
6583 new_reg
->name
= a
->new_name
;
6584 new_reg
->type
|= ARM_CP_ALIAS
;
6585 /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */
6586 new_reg
->access
&= PL2_RW
| PL3_RW
;
6588 ok
= g_hash_table_insert(cpu
->cp_regs
,
6589 (gpointer
)(uintptr_t)a
->new_key
, new_reg
);
6592 src_reg
->opaque
= dst_reg
;
6593 src_reg
->orig_readfn
= src_reg
->readfn
?: raw_read
;
6594 src_reg
->orig_writefn
= src_reg
->writefn
?: raw_write
;
6595 if (!src_reg
->raw_readfn
) {
6596 src_reg
->raw_readfn
= raw_read
;
6598 if (!src_reg
->raw_writefn
) {
6599 src_reg
->raw_writefn
= raw_write
;
6601 src_reg
->readfn
= el2_e2h_read
;
6602 src_reg
->writefn
= el2_e2h_write
;
6607 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6610 int cur_el
= arm_current_el(env
);
6613 uint64_t hcr
= arm_hcr_el2_eff(env
);
6616 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
6617 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_UCT
)) {
6618 return CP_ACCESS_TRAP_EL2
;
6621 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_UCT
)) {
6622 return CP_ACCESS_TRAP
;
6624 if (hcr
& HCR_TID2
) {
6625 return CP_ACCESS_TRAP_EL2
;
6628 } else if (hcr
& HCR_TID2
) {
6629 return CP_ACCESS_TRAP_EL2
;
6633 if (arm_current_el(env
) < 2 && arm_hcr_el2_eff(env
) & HCR_TID2
) {
6634 return CP_ACCESS_TRAP_EL2
;
6637 return CP_ACCESS_OK
;
6641 * Check for traps to RAS registers, which are controlled
6642 * by HCR_EL2.TERR and SCR_EL3.TERR.
6644 static CPAccessResult
access_terr(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6647 int el
= arm_current_el(env
);
6649 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TERR
)) {
6650 return CP_ACCESS_TRAP_EL2
;
6652 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TERR
)) {
6653 return CP_ACCESS_TRAP_EL3
;
6655 return CP_ACCESS_OK
;
6658 static uint64_t disr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6660 int el
= arm_current_el(env
);
6662 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_AMO
)) {
6663 return env
->cp15
.vdisr_el2
;
6665 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_EA
)) {
6666 return 0; /* RAZ/WI */
6668 return env
->cp15
.disr_el1
;
6671 static void disr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
6673 int el
= arm_current_el(env
);
6675 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_AMO
)) {
6676 env
->cp15
.vdisr_el2
= val
;
6679 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_EA
)) {
6680 return; /* RAZ/WI */
6682 env
->cp15
.disr_el1
= val
;
6686 * Minimal RAS implementation with no Error Records.
6687 * Which means that all of the Error Record registers:
6695 * ERXPFGCDN_EL1 (RASv1p1)
6696 * ERXPFGCTL_EL1 (RASv1p1)
6697 * ERXPFGF_EL1 (RASv1p1)
6701 * may generate UNDEFINED, which is the effect we get by not
6702 * listing them at all.
6704 * These registers have fine-grained trap bits, but UNDEF-to-EL1
6705 * is higher priority than FGT-to-EL2 so we do not need to list them
6706 * in order to check for an FGT.
6708 static const ARMCPRegInfo minimal_ras_reginfo
[] = {
6709 { .name
= "DISR_EL1", .state
= ARM_CP_STATE_BOTH
,
6710 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 1,
6711 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.disr_el1
),
6712 .readfn
= disr_read
, .writefn
= disr_write
, .raw_writefn
= raw_write
},
6713 { .name
= "ERRIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
6714 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 3, .opc2
= 0,
6715 .access
= PL1_R
, .accessfn
= access_terr
,
6716 .fgt
= FGT_ERRIDR_EL1
,
6717 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6718 { .name
= "VDISR_EL2", .state
= ARM_CP_STATE_BOTH
,
6719 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 1, .opc2
= 1,
6720 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.vdisr_el2
) },
6721 { .name
= "VSESR_EL2", .state
= ARM_CP_STATE_BOTH
,
6722 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 3,
6723 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.vsesr_el2
) },
6727 * Return the exception level to which exceptions should be taken
6728 * via SVEAccessTrap. This excludes the check for whether the exception
6729 * should be routed through AArch64.AdvSIMDFPAccessTrap. That can easily
6730 * be found by testing 0 < fp_exception_el < sve_exception_el.
6732 * C.f. the ARM pseudocode function CheckSVEEnabled. Note that the
6733 * pseudocode does *not* separate out the FP trap checks, but has them
6734 * all in one function.
6736 int sve_exception_el(CPUARMState
*env
, int el
)
6738 #ifndef CONFIG_USER_ONLY
6739 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6740 switch (FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, ZEN
)) {
6752 if (el
<= 2 && arm_is_el2_enabled(env
)) {
6753 /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */
6754 if (env
->cp15
.hcr_el2
& HCR_E2H
) {
6755 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, ZEN
)) {
6757 if (el
!= 0 || !(env
->cp15
.hcr_el2
& HCR_TGE
)) {
6766 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TZ
)) {
6772 /* CPTR_EL3. Since EZ is negative we must check for EL3. */
6773 if (arm_feature(env
, ARM_FEATURE_EL3
)
6774 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, EZ
)) {
6782 * Return the exception level to which exceptions should be taken for SME.
6783 * C.f. the ARM pseudocode function CheckSMEAccess.
6785 int sme_exception_el(CPUARMState
*env
, int el
)
6787 #ifndef CONFIG_USER_ONLY
6788 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6789 switch (FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, SMEN
)) {
6801 if (el
<= 2 && arm_is_el2_enabled(env
)) {
6802 /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */
6803 if (env
->cp15
.hcr_el2
& HCR_E2H
) {
6804 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, SMEN
)) {
6806 if (el
!= 0 || !(env
->cp15
.hcr_el2
& HCR_TGE
)) {
6815 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TSM
)) {
6821 /* CPTR_EL3. Since ESM is negative we must check for EL3. */
6822 if (arm_feature(env
, ARM_FEATURE_EL3
)
6823 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, ESM
)) {
6831 * Given that SVE is enabled, return the vector length for EL.
6833 uint32_t sve_vqm1_for_el_sm(CPUARMState
*env
, int el
, bool sm
)
6835 ARMCPU
*cpu
= env_archcpu(env
);
6836 uint64_t *cr
= env
->vfp
.zcr_el
;
6837 uint32_t map
= cpu
->sve_vq
.map
;
6838 uint32_t len
= ARM_MAX_VQ
- 1;
6841 cr
= env
->vfp
.smcr_el
;
6842 map
= cpu
->sme_vq
.map
;
6845 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6846 len
= MIN(len
, 0xf & (uint32_t)cr
[1]);
6848 if (el
<= 2 && arm_feature(env
, ARM_FEATURE_EL2
)) {
6849 len
= MIN(len
, 0xf & (uint32_t)cr
[2]);
6851 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6852 len
= MIN(len
, 0xf & (uint32_t)cr
[3]);
6855 map
&= MAKE_64BIT_MASK(0, len
+ 1);
6857 return 31 - clz32(map
);
6860 /* Bit 0 is always set for Normal SVE -- not so for Streaming SVE. */
6862 return ctz32(cpu
->sme_vq
.map
);
6865 uint32_t sve_vqm1_for_el(CPUARMState
*env
, int el
)
6867 return sve_vqm1_for_el_sm(env
, el
, FIELD_EX64(env
->svcr
, SVCR
, SM
));
6870 static void zcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6873 int cur_el
= arm_current_el(env
);
6874 int old_len
= sve_vqm1_for_el(env
, cur_el
);
6877 /* Bits other than [3:0] are RAZ/WI. */
6878 QEMU_BUILD_BUG_ON(ARM_MAX_VQ
> 16);
6879 raw_write(env
, ri
, value
& 0xf);
6882 * Because we arrived here, we know both FP and SVE are enabled;
6883 * otherwise we would have trapped access to the ZCR_ELn register.
6885 new_len
= sve_vqm1_for_el(env
, cur_el
);
6886 if (new_len
< old_len
) {
6887 aarch64_sve_narrow_vq(env
, new_len
+ 1);
6891 static const ARMCPRegInfo zcr_reginfo
[] = {
6892 { .name
= "ZCR_EL1", .state
= ARM_CP_STATE_AA64
,
6893 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 0,
6894 .access
= PL1_RW
, .type
= ARM_CP_SVE
,
6895 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[1]),
6896 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
6897 { .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
6898 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
6899 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
6900 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[2]),
6901 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
6902 { .name
= "ZCR_EL3", .state
= ARM_CP_STATE_AA64
,
6903 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 0,
6904 .access
= PL3_RW
, .type
= ARM_CP_SVE
,
6905 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[3]),
6906 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
6909 #ifdef TARGET_AARCH64
6910 static CPAccessResult
access_tpidr2(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6913 int el
= arm_current_el(env
);
6916 uint64_t sctlr
= arm_sctlr(env
, el
);
6917 if (!(sctlr
& SCTLR_EnTP2
)) {
6918 return CP_ACCESS_TRAP
;
6921 /* TODO: FEAT_FGT */
6923 && arm_feature(env
, ARM_FEATURE_EL3
)
6924 && !(env
->cp15
.scr_el3
& SCR_ENTP2
)) {
6925 return CP_ACCESS_TRAP_EL3
;
6927 return CP_ACCESS_OK
;
6930 static CPAccessResult
access_esm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6933 /* TODO: FEAT_FGT for SMPRI_EL1 but not SMPRIMAP_EL2 */
6934 if (arm_current_el(env
) < 3
6935 && arm_feature(env
, ARM_FEATURE_EL3
)
6936 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, ESM
)) {
6937 return CP_ACCESS_TRAP_EL3
;
6939 return CP_ACCESS_OK
;
6943 static void arm_reset_sve_state(CPUARMState
*env
)
6945 memset(env
->vfp
.zregs
, 0, sizeof(env
->vfp
.zregs
));
6946 /* Recall that FFR is stored as pregs[16]. */
6947 memset(env
->vfp
.pregs
, 0, sizeof(env
->vfp
.pregs
));
6948 vfp_set_fpcr(env
, 0x0800009f);
6951 void aarch64_set_svcr(CPUARMState
*env
, uint64_t new, uint64_t mask
)
6953 uint64_t change
= (env
->svcr
^ new) & mask
;
6958 env
->svcr
^= change
;
6960 if (change
& R_SVCR_SM_MASK
) {
6961 arm_reset_sve_state(env
);
6967 * SetPSTATE_ZA zeros on enable and disable. We can zero this only
6968 * on enable: while disabled, the storage is inaccessible and the
6969 * value does not matter. We're not saving the storage in vmstate
6970 * when disabled either.
6972 if (change
& new & R_SVCR_ZA_MASK
) {
6973 memset(env
->zarray
, 0, sizeof(env
->zarray
));
6976 if (tcg_enabled()) {
6977 arm_rebuild_hflags(env
);
6981 static void svcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6984 aarch64_set_svcr(env
, value
, -1);
6987 static void smcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6990 int cur_el
= arm_current_el(env
);
6991 int old_len
= sve_vqm1_for_el(env
, cur_el
);
6994 QEMU_BUILD_BUG_ON(ARM_MAX_VQ
> R_SMCR_LEN_MASK
+ 1);
6995 value
&= R_SMCR_LEN_MASK
| R_SMCR_FA64_MASK
;
6996 raw_write(env
, ri
, value
);
6999 * Note that it is CONSTRAINED UNPREDICTABLE what happens to ZA storage
7000 * when SVL is widened (old values kept, or zeros). Choose to keep the
7001 * current values for simplicity. But for QEMU internals, we must still
7002 * apply the narrower SVL to the Zregs and Pregs -- see the comment
7003 * above aarch64_sve_narrow_vq.
7005 new_len
= sve_vqm1_for_el(env
, cur_el
);
7006 if (new_len
< old_len
) {
7007 aarch64_sve_narrow_vq(env
, new_len
+ 1);
7011 static const ARMCPRegInfo sme_reginfo
[] = {
7012 { .name
= "TPIDR2_EL0", .state
= ARM_CP_STATE_AA64
,
7013 .opc0
= 3, .opc1
= 3, .crn
= 13, .crm
= 0, .opc2
= 5,
7014 .access
= PL0_RW
, .accessfn
= access_tpidr2
,
7015 .fgt
= FGT_NTPIDR2_EL0
,
7016 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr2_el0
) },
7017 { .name
= "SVCR", .state
= ARM_CP_STATE_AA64
,
7018 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 2,
7019 .access
= PL0_RW
, .type
= ARM_CP_SME
,
7020 .fieldoffset
= offsetof(CPUARMState
, svcr
),
7021 .writefn
= svcr_write
, .raw_writefn
= raw_write
},
7022 { .name
= "SMCR_EL1", .state
= ARM_CP_STATE_AA64
,
7023 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 6,
7024 .access
= PL1_RW
, .type
= ARM_CP_SME
,
7025 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[1]),
7026 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
7027 { .name
= "SMCR_EL2", .state
= ARM_CP_STATE_AA64
,
7028 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 6,
7029 .access
= PL2_RW
, .type
= ARM_CP_SME
,
7030 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[2]),
7031 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
7032 { .name
= "SMCR_EL3", .state
= ARM_CP_STATE_AA64
,
7033 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 6,
7034 .access
= PL3_RW
, .type
= ARM_CP_SME
,
7035 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[3]),
7036 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
7037 { .name
= "SMIDR_EL1", .state
= ARM_CP_STATE_AA64
,
7038 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 6,
7039 .access
= PL1_R
, .accessfn
= access_aa64_tid1
,
7041 * IMPLEMENTOR = 0 (software)
7042 * REVISION = 0 (implementation defined)
7043 * SMPS = 0 (no streaming execution priority in QEMU)
7044 * AFFINITY = 0 (streaming sve mode not shared with other PEs)
7046 .type
= ARM_CP_CONST
, .resetvalue
= 0, },
7048 * Because SMIDR_EL1.SMPS is 0, SMPRI_EL1 and SMPRIMAP_EL2 are RES 0.
7050 { .name
= "SMPRI_EL1", .state
= ARM_CP_STATE_AA64
,
7051 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 4,
7052 .access
= PL1_RW
, .accessfn
= access_esm
,
7053 .fgt
= FGT_NSMPRI_EL1
,
7054 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7055 { .name
= "SMPRIMAP_EL2", .state
= ARM_CP_STATE_AA64
,
7056 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 5,
7057 .access
= PL2_RW
, .accessfn
= access_esm
,
7058 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7061 static void tlbi_aa64_paall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7064 CPUState
*cs
= env_cpu(env
);
7069 static void gpccr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7072 /* L0GPTSZ is RO; other bits not mentioned are RES0. */
7073 uint64_t rw_mask
= R_GPCCR_PPS_MASK
| R_GPCCR_IRGN_MASK
|
7074 R_GPCCR_ORGN_MASK
| R_GPCCR_SH_MASK
| R_GPCCR_PGS_MASK
|
7075 R_GPCCR_GPC_MASK
| R_GPCCR_GPCP_MASK
;
7077 env
->cp15
.gpccr_el3
= (value
& rw_mask
) | (env
->cp15
.gpccr_el3
& ~rw_mask
);
7080 static void gpccr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7082 env
->cp15
.gpccr_el3
= FIELD_DP64(0, GPCCR
, L0GPTSZ
,
7083 env_archcpu(env
)->reset_l0gptsz
);
7086 static void tlbi_aa64_paallos_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7089 CPUState
*cs
= env_cpu(env
);
7091 tlb_flush_all_cpus_synced(cs
);
7094 static const ARMCPRegInfo rme_reginfo
[] = {
7095 { .name
= "GPCCR_EL3", .state
= ARM_CP_STATE_AA64
,
7096 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 1, .opc2
= 6,
7097 .access
= PL3_RW
, .writefn
= gpccr_write
, .resetfn
= gpccr_reset
,
7098 .fieldoffset
= offsetof(CPUARMState
, cp15
.gpccr_el3
) },
7099 { .name
= "GPTBR_EL3", .state
= ARM_CP_STATE_AA64
,
7100 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 1, .opc2
= 4,
7101 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.gptbr_el3
) },
7102 { .name
= "MFAR_EL3", .state
= ARM_CP_STATE_AA64
,
7103 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 5,
7104 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mfar_el3
) },
7105 { .name
= "TLBI_PAALL", .state
= ARM_CP_STATE_AA64
,
7106 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 4,
7107 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7108 .writefn
= tlbi_aa64_paall_write
},
7109 { .name
= "TLBI_PAALLOS", .state
= ARM_CP_STATE_AA64
,
7110 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 4,
7111 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7112 .writefn
= tlbi_aa64_paallos_write
},
7114 * QEMU does not have a way to invalidate by physical address, thus
7115 * invalidating a range of physical addresses is accomplished by
7116 * flushing all tlb entries in the outer shareable domain,
7117 * just like PAALLOS.
7119 { .name
= "TLBI_RPALOS", .state
= ARM_CP_STATE_AA64
,
7120 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 4, .opc2
= 7,
7121 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7122 .writefn
= tlbi_aa64_paallos_write
},
7123 { .name
= "TLBI_RPAOS", .state
= ARM_CP_STATE_AA64
,
7124 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 4, .opc2
= 3,
7125 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7126 .writefn
= tlbi_aa64_paallos_write
},
7127 { .name
= "DC_CIPAPA", .state
= ARM_CP_STATE_AA64
,
7128 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 14, .opc2
= 1,
7129 .access
= PL3_W
, .type
= ARM_CP_NOP
},
7132 static const ARMCPRegInfo rme_mte_reginfo
[] = {
7133 { .name
= "DC_CIGDPAPA", .state
= ARM_CP_STATE_AA64
,
7134 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 14, .opc2
= 5,
7135 .access
= PL3_W
, .type
= ARM_CP_NOP
},
7137 #endif /* TARGET_AARCH64 */
7139 static void define_pmu_regs(ARMCPU
*cpu
)
7142 * v7 performance monitor control register: same implementor
7143 * field as main ID register, and we implement four counters in
7144 * addition to the cycle count register.
7146 unsigned int i
, pmcrn
= pmu_num_counters(&cpu
->env
);
7147 ARMCPRegInfo pmcr
= {
7148 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
7150 .fgt
= FGT_PMCR_EL0
,
7151 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7152 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcr
),
7153 .accessfn
= pmreg_access
, .writefn
= pmcr_write
,
7154 .raw_writefn
= raw_write
,
7156 ARMCPRegInfo pmcr64
= {
7157 .name
= "PMCR_EL0", .state
= ARM_CP_STATE_AA64
,
7158 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 0,
7159 .access
= PL0_RW
, .accessfn
= pmreg_access
,
7160 .fgt
= FGT_PMCR_EL0
,
7162 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
7163 .resetvalue
= cpu
->isar
.reset_pmcr_el0
,
7164 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
7167 define_one_arm_cp_reg(cpu
, &pmcr
);
7168 define_one_arm_cp_reg(cpu
, &pmcr64
);
7169 for (i
= 0; i
< pmcrn
; i
++) {
7170 char *pmevcntr_name
= g_strdup_printf("PMEVCNTR%d", i
);
7171 char *pmevcntr_el0_name
= g_strdup_printf("PMEVCNTR%d_EL0", i
);
7172 char *pmevtyper_name
= g_strdup_printf("PMEVTYPER%d", i
);
7173 char *pmevtyper_el0_name
= g_strdup_printf("PMEVTYPER%d_EL0", i
);
7174 ARMCPRegInfo pmev_regs
[] = {
7175 { .name
= pmevcntr_name
, .cp
= 15, .crn
= 14,
7176 .crm
= 8 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
7177 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7178 .fgt
= FGT_PMEVCNTRN_EL0
,
7179 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
7180 .accessfn
= pmreg_access_xevcntr
},
7181 { .name
= pmevcntr_el0_name
, .state
= ARM_CP_STATE_AA64
,
7182 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 8 | (3 & (i
>> 3)),
7183 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access_xevcntr
,
7185 .fgt
= FGT_PMEVCNTRN_EL0
,
7186 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
7187 .raw_readfn
= pmevcntr_rawread
,
7188 .raw_writefn
= pmevcntr_rawwrite
},
7189 { .name
= pmevtyper_name
, .cp
= 15, .crn
= 14,
7190 .crm
= 12 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
7191 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7192 .fgt
= FGT_PMEVTYPERN_EL0
,
7193 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
7194 .accessfn
= pmreg_access
},
7195 { .name
= pmevtyper_el0_name
, .state
= ARM_CP_STATE_AA64
,
7196 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 12 | (3 & (i
>> 3)),
7197 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access
,
7198 .fgt
= FGT_PMEVTYPERN_EL0
,
7200 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
7201 .raw_writefn
= pmevtyper_rawwrite
},
7203 define_arm_cp_regs(cpu
, pmev_regs
);
7204 g_free(pmevcntr_name
);
7205 g_free(pmevcntr_el0_name
);
7206 g_free(pmevtyper_name
);
7207 g_free(pmevtyper_el0_name
);
7209 if (cpu_isar_feature(aa32_pmuv3p1
, cpu
)) {
7210 ARMCPRegInfo v81_pmu_regs
[] = {
7211 { .name
= "PMCEID2", .state
= ARM_CP_STATE_AA32
,
7212 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 4,
7213 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7214 .fgt
= FGT_PMCEIDN_EL0
,
7215 .resetvalue
= extract64(cpu
->pmceid0
, 32, 32) },
7216 { .name
= "PMCEID3", .state
= ARM_CP_STATE_AA32
,
7217 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 5,
7218 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7219 .fgt
= FGT_PMCEIDN_EL0
,
7220 .resetvalue
= extract64(cpu
->pmceid1
, 32, 32) },
7222 define_arm_cp_regs(cpu
, v81_pmu_regs
);
7224 if (cpu_isar_feature(any_pmuv3p4
, cpu
)) {
7225 static const ARMCPRegInfo v84_pmmir
= {
7226 .name
= "PMMIR_EL1", .state
= ARM_CP_STATE_BOTH
,
7227 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 6,
7228 .access
= PL1_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7229 .fgt
= FGT_PMMIR_EL1
,
7232 define_one_arm_cp_reg(cpu
, &v84_pmmir
);
7236 #ifndef CONFIG_USER_ONLY
7238 * We don't know until after realize whether there's a GICv3
7239 * attached, and that is what registers the gicv3 sysregs.
7240 * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
7243 static uint64_t id_pfr1_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7245 ARMCPU
*cpu
= env_archcpu(env
);
7246 uint64_t pfr1
= cpu
->isar
.id_pfr1
;
7248 if (env
->gicv3state
) {
7254 static uint64_t id_aa64pfr0_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7256 ARMCPU
*cpu
= env_archcpu(env
);
7257 uint64_t pfr0
= cpu
->isar
.id_aa64pfr0
;
7259 if (env
->gicv3state
) {
7267 * Shared logic between LORID and the rest of the LOR* registers.
7268 * Secure state exclusion has already been dealt with.
7270 static CPAccessResult
access_lor_ns(CPUARMState
*env
,
7271 const ARMCPRegInfo
*ri
, bool isread
)
7273 int el
= arm_current_el(env
);
7275 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TLOR
)) {
7276 return CP_ACCESS_TRAP_EL2
;
7278 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TLOR
)) {
7279 return CP_ACCESS_TRAP_EL3
;
7281 return CP_ACCESS_OK
;
7284 static CPAccessResult
access_lor_other(CPUARMState
*env
,
7285 const ARMCPRegInfo
*ri
, bool isread
)
7287 if (arm_is_secure_below_el3(env
)) {
7288 /* Access denied in secure mode. */
7289 return CP_ACCESS_TRAP
;
7291 return access_lor_ns(env
, ri
, isread
);
7295 * A trivial implementation of ARMv8.1-LOR leaves all of these
7296 * registers fixed at 0, which indicates that there are zero
7297 * supported Limited Ordering regions.
7299 static const ARMCPRegInfo lor_reginfo
[] = {
7300 { .name
= "LORSA_EL1", .state
= ARM_CP_STATE_AA64
,
7301 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 0,
7302 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7303 .fgt
= FGT_LORSA_EL1
,
7304 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7305 { .name
= "LOREA_EL1", .state
= ARM_CP_STATE_AA64
,
7306 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 1,
7307 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7308 .fgt
= FGT_LOREA_EL1
,
7309 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7310 { .name
= "LORN_EL1", .state
= ARM_CP_STATE_AA64
,
7311 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 2,
7312 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7313 .fgt
= FGT_LORN_EL1
,
7314 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7315 { .name
= "LORC_EL1", .state
= ARM_CP_STATE_AA64
,
7316 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 3,
7317 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7318 .fgt
= FGT_LORC_EL1
,
7319 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7320 { .name
= "LORID_EL1", .state
= ARM_CP_STATE_AA64
,
7321 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 7,
7322 .access
= PL1_R
, .accessfn
= access_lor_ns
,
7323 .fgt
= FGT_LORID_EL1
,
7324 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7327 #ifdef TARGET_AARCH64
7328 static CPAccessResult
access_pauth(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7331 int el
= arm_current_el(env
);
7334 arm_is_el2_enabled(env
) &&
7335 !(arm_hcr_el2_eff(env
) & HCR_APK
)) {
7336 return CP_ACCESS_TRAP_EL2
;
7339 arm_feature(env
, ARM_FEATURE_EL3
) &&
7340 !(env
->cp15
.scr_el3
& SCR_APK
)) {
7341 return CP_ACCESS_TRAP_EL3
;
7343 return CP_ACCESS_OK
;
7346 static const ARMCPRegInfo pauth_reginfo
[] = {
7347 { .name
= "APDAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7348 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 0,
7349 .access
= PL1_RW
, .accessfn
= access_pauth
,
7351 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.lo
) },
7352 { .name
= "APDAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7353 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 1,
7354 .access
= PL1_RW
, .accessfn
= access_pauth
,
7356 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.hi
) },
7357 { .name
= "APDBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7358 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 2,
7359 .access
= PL1_RW
, .accessfn
= access_pauth
,
7361 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.lo
) },
7362 { .name
= "APDBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7363 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 3,
7364 .access
= PL1_RW
, .accessfn
= access_pauth
,
7366 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.hi
) },
7367 { .name
= "APGAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7368 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 0,
7369 .access
= PL1_RW
, .accessfn
= access_pauth
,
7371 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.lo
) },
7372 { .name
= "APGAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7373 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 1,
7374 .access
= PL1_RW
, .accessfn
= access_pauth
,
7376 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.hi
) },
7377 { .name
= "APIAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7378 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 0,
7379 .access
= PL1_RW
, .accessfn
= access_pauth
,
7381 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.lo
) },
7382 { .name
= "APIAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7383 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 1,
7384 .access
= PL1_RW
, .accessfn
= access_pauth
,
7386 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.hi
) },
7387 { .name
= "APIBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7388 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 2,
7389 .access
= PL1_RW
, .accessfn
= access_pauth
,
7391 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.lo
) },
7392 { .name
= "APIBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7393 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 3,
7394 .access
= PL1_RW
, .accessfn
= access_pauth
,
7396 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.hi
) },
7399 static const ARMCPRegInfo tlbirange_reginfo
[] = {
7400 { .name
= "TLBI_RVAE1IS", .state
= ARM_CP_STATE_AA64
,
7401 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 1,
7402 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7403 .fgt
= FGT_TLBIRVAE1IS
,
7404 .writefn
= tlbi_aa64_rvae1is_write
},
7405 { .name
= "TLBI_RVAAE1IS", .state
= ARM_CP_STATE_AA64
,
7406 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 3,
7407 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7408 .fgt
= FGT_TLBIRVAAE1IS
,
7409 .writefn
= tlbi_aa64_rvae1is_write
},
7410 { .name
= "TLBI_RVALE1IS", .state
= ARM_CP_STATE_AA64
,
7411 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 5,
7412 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7413 .fgt
= FGT_TLBIRVALE1IS
,
7414 .writefn
= tlbi_aa64_rvae1is_write
},
7415 { .name
= "TLBI_RVAALE1IS", .state
= ARM_CP_STATE_AA64
,
7416 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 7,
7417 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7418 .fgt
= FGT_TLBIRVAALE1IS
,
7419 .writefn
= tlbi_aa64_rvae1is_write
},
7420 { .name
= "TLBI_RVAE1OS", .state
= ARM_CP_STATE_AA64
,
7421 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
7422 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7423 .fgt
= FGT_TLBIRVAE1OS
,
7424 .writefn
= tlbi_aa64_rvae1is_write
},
7425 { .name
= "TLBI_RVAAE1OS", .state
= ARM_CP_STATE_AA64
,
7426 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 3,
7427 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7428 .fgt
= FGT_TLBIRVAAE1OS
,
7429 .writefn
= tlbi_aa64_rvae1is_write
},
7430 { .name
= "TLBI_RVALE1OS", .state
= ARM_CP_STATE_AA64
,
7431 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 5,
7432 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7433 .fgt
= FGT_TLBIRVALE1OS
,
7434 .writefn
= tlbi_aa64_rvae1is_write
},
7435 { .name
= "TLBI_RVAALE1OS", .state
= ARM_CP_STATE_AA64
,
7436 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 7,
7437 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7438 .fgt
= FGT_TLBIRVAALE1OS
,
7439 .writefn
= tlbi_aa64_rvae1is_write
},
7440 { .name
= "TLBI_RVAE1", .state
= ARM_CP_STATE_AA64
,
7441 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
7442 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7443 .fgt
= FGT_TLBIRVAE1
,
7444 .writefn
= tlbi_aa64_rvae1_write
},
7445 { .name
= "TLBI_RVAAE1", .state
= ARM_CP_STATE_AA64
,
7446 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 3,
7447 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7448 .fgt
= FGT_TLBIRVAAE1
,
7449 .writefn
= tlbi_aa64_rvae1_write
},
7450 { .name
= "TLBI_RVALE1", .state
= ARM_CP_STATE_AA64
,
7451 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 5,
7452 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7453 .fgt
= FGT_TLBIRVALE1
,
7454 .writefn
= tlbi_aa64_rvae1_write
},
7455 { .name
= "TLBI_RVAALE1", .state
= ARM_CP_STATE_AA64
,
7456 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 7,
7457 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7458 .fgt
= FGT_TLBIRVAALE1
,
7459 .writefn
= tlbi_aa64_rvae1_write
},
7460 { .name
= "TLBI_RIPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
7461 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 2,
7462 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7463 .writefn
= tlbi_aa64_ripas2e1is_write
},
7464 { .name
= "TLBI_RIPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
7465 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 6,
7466 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7467 .writefn
= tlbi_aa64_ripas2e1is_write
},
7468 { .name
= "TLBI_RVAE2IS", .state
= ARM_CP_STATE_AA64
,
7469 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 2, .opc2
= 1,
7470 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7471 .writefn
= tlbi_aa64_rvae2is_write
},
7472 { .name
= "TLBI_RVALE2IS", .state
= ARM_CP_STATE_AA64
,
7473 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 2, .opc2
= 5,
7474 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7475 .writefn
= tlbi_aa64_rvae2is_write
},
7476 { .name
= "TLBI_RIPAS2E1", .state
= ARM_CP_STATE_AA64
,
7477 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 2,
7478 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7479 .writefn
= tlbi_aa64_ripas2e1_write
},
7480 { .name
= "TLBI_RIPAS2LE1", .state
= ARM_CP_STATE_AA64
,
7481 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 6,
7482 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7483 .writefn
= tlbi_aa64_ripas2e1_write
},
7484 { .name
= "TLBI_RVAE2OS", .state
= ARM_CP_STATE_AA64
,
7485 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 5, .opc2
= 1,
7486 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7487 .writefn
= tlbi_aa64_rvae2is_write
},
7488 { .name
= "TLBI_RVALE2OS", .state
= ARM_CP_STATE_AA64
,
7489 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 5, .opc2
= 5,
7490 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7491 .writefn
= tlbi_aa64_rvae2is_write
},
7492 { .name
= "TLBI_RVAE2", .state
= ARM_CP_STATE_AA64
,
7493 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 6, .opc2
= 1,
7494 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7495 .writefn
= tlbi_aa64_rvae2_write
},
7496 { .name
= "TLBI_RVALE2", .state
= ARM_CP_STATE_AA64
,
7497 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 6, .opc2
= 5,
7498 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7499 .writefn
= tlbi_aa64_rvae2_write
},
7500 { .name
= "TLBI_RVAE3IS", .state
= ARM_CP_STATE_AA64
,
7501 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 2, .opc2
= 1,
7502 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7503 .writefn
= tlbi_aa64_rvae3is_write
},
7504 { .name
= "TLBI_RVALE3IS", .state
= ARM_CP_STATE_AA64
,
7505 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 2, .opc2
= 5,
7506 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7507 .writefn
= tlbi_aa64_rvae3is_write
},
7508 { .name
= "TLBI_RVAE3OS", .state
= ARM_CP_STATE_AA64
,
7509 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 5, .opc2
= 1,
7510 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7511 .writefn
= tlbi_aa64_rvae3is_write
},
7512 { .name
= "TLBI_RVALE3OS", .state
= ARM_CP_STATE_AA64
,
7513 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 5, .opc2
= 5,
7514 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7515 .writefn
= tlbi_aa64_rvae3is_write
},
7516 { .name
= "TLBI_RVAE3", .state
= ARM_CP_STATE_AA64
,
7517 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 6, .opc2
= 1,
7518 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7519 .writefn
= tlbi_aa64_rvae3_write
},
7520 { .name
= "TLBI_RVALE3", .state
= ARM_CP_STATE_AA64
,
7521 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 6, .opc2
= 5,
7522 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7523 .writefn
= tlbi_aa64_rvae3_write
},
7526 static const ARMCPRegInfo tlbios_reginfo
[] = {
7527 { .name
= "TLBI_VMALLE1OS", .state
= ARM_CP_STATE_AA64
,
7528 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 0,
7529 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7530 .fgt
= FGT_TLBIVMALLE1OS
,
7531 .writefn
= tlbi_aa64_vmalle1is_write
},
7532 { .name
= "TLBI_VAE1OS", .state
= ARM_CP_STATE_AA64
,
7533 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 1,
7534 .fgt
= FGT_TLBIVAE1OS
,
7535 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7536 .writefn
= tlbi_aa64_vae1is_write
},
7537 { .name
= "TLBI_ASIDE1OS", .state
= ARM_CP_STATE_AA64
,
7538 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 2,
7539 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7540 .fgt
= FGT_TLBIASIDE1OS
,
7541 .writefn
= tlbi_aa64_vmalle1is_write
},
7542 { .name
= "TLBI_VAAE1OS", .state
= ARM_CP_STATE_AA64
,
7543 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 3,
7544 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7545 .fgt
= FGT_TLBIVAAE1OS
,
7546 .writefn
= tlbi_aa64_vae1is_write
},
7547 { .name
= "TLBI_VALE1OS", .state
= ARM_CP_STATE_AA64
,
7548 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 5,
7549 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7550 .fgt
= FGT_TLBIVALE1OS
,
7551 .writefn
= tlbi_aa64_vae1is_write
},
7552 { .name
= "TLBI_VAALE1OS", .state
= ARM_CP_STATE_AA64
,
7553 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 7,
7554 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7555 .fgt
= FGT_TLBIVAALE1OS
,
7556 .writefn
= tlbi_aa64_vae1is_write
},
7557 { .name
= "TLBI_ALLE2OS", .state
= ARM_CP_STATE_AA64
,
7558 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 0,
7559 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7560 .writefn
= tlbi_aa64_alle2is_write
},
7561 { .name
= "TLBI_VAE2OS", .state
= ARM_CP_STATE_AA64
,
7562 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 1,
7563 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7564 .writefn
= tlbi_aa64_vae2is_write
},
7565 { .name
= "TLBI_ALLE1OS", .state
= ARM_CP_STATE_AA64
,
7566 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 4,
7567 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7568 .writefn
= tlbi_aa64_alle1is_write
},
7569 { .name
= "TLBI_VALE2OS", .state
= ARM_CP_STATE_AA64
,
7570 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 5,
7571 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7572 .writefn
= tlbi_aa64_vae2is_write
},
7573 { .name
= "TLBI_VMALLS12E1OS", .state
= ARM_CP_STATE_AA64
,
7574 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 6,
7575 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7576 .writefn
= tlbi_aa64_alle1is_write
},
7577 { .name
= "TLBI_IPAS2E1OS", .state
= ARM_CP_STATE_AA64
,
7578 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 0,
7579 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7580 { .name
= "TLBI_RIPAS2E1OS", .state
= ARM_CP_STATE_AA64
,
7581 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 3,
7582 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7583 { .name
= "TLBI_IPAS2LE1OS", .state
= ARM_CP_STATE_AA64
,
7584 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 4,
7585 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7586 { .name
= "TLBI_RIPAS2LE1OS", .state
= ARM_CP_STATE_AA64
,
7587 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 7,
7588 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7589 { .name
= "TLBI_ALLE3OS", .state
= ARM_CP_STATE_AA64
,
7590 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 0,
7591 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7592 .writefn
= tlbi_aa64_alle3is_write
},
7593 { .name
= "TLBI_VAE3OS", .state
= ARM_CP_STATE_AA64
,
7594 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 1,
7595 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7596 .writefn
= tlbi_aa64_vae3is_write
},
7597 { .name
= "TLBI_VALE3OS", .state
= ARM_CP_STATE_AA64
,
7598 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 5,
7599 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7600 .writefn
= tlbi_aa64_vae3is_write
},
7603 static uint64_t rndr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7608 /* Success sets NZCV = 0000. */
7609 env
->NF
= env
->CF
= env
->VF
= 0, env
->ZF
= 1;
7611 if (qemu_guest_getrandom(&ret
, sizeof(ret
), &err
) < 0) {
7613 * ??? Failed, for unknown reasons in the crypto subsystem.
7614 * The best we can do is log the reason and return the
7615 * timed-out indication to the guest. There is no reason
7616 * we know to expect this failure to be transitory, so the
7617 * guest may well hang retrying the operation.
7619 qemu_log_mask(LOG_UNIMP
, "%s: Crypto failure: %s",
7620 ri
->name
, error_get_pretty(err
));
7623 env
->ZF
= 0; /* NZCF = 0100 */
7629 /* We do not support re-seeding, so the two registers operate the same. */
7630 static const ARMCPRegInfo rndr_reginfo
[] = {
7631 { .name
= "RNDR", .state
= ARM_CP_STATE_AA64
,
7632 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
7633 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 0,
7634 .access
= PL0_R
, .readfn
= rndr_readfn
},
7635 { .name
= "RNDRRS", .state
= ARM_CP_STATE_AA64
,
7636 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
7637 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 1,
7638 .access
= PL0_R
, .readfn
= rndr_readfn
},
7641 static void dccvap_writefn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
,
7644 ARMCPU
*cpu
= env_archcpu(env
);
7645 /* CTR_EL0 System register -> DminLine, bits [19:16] */
7646 uint64_t dline_size
= 4 << ((cpu
->ctr
>> 16) & 0xF);
7647 uint64_t vaddr_in
= (uint64_t) value
;
7648 uint64_t vaddr
= vaddr_in
& ~(dline_size
- 1);
7650 int mem_idx
= cpu_mmu_index(env
, false);
7652 /* This won't be crossing page boundaries */
7653 haddr
= probe_read(env
, vaddr
, dline_size
, mem_idx
, GETPC());
7655 #ifndef CONFIG_USER_ONLY
7660 /* RCU lock is already being held */
7661 mr
= memory_region_from_host(haddr
, &offset
);
7664 memory_region_writeback(mr
, offset
, dline_size
);
7666 #endif /*CONFIG_USER_ONLY*/
7670 static const ARMCPRegInfo dcpop_reg
[] = {
7671 { .name
= "DC_CVAP", .state
= ARM_CP_STATE_AA64
,
7672 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 1,
7673 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
7675 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
7678 static const ARMCPRegInfo dcpodp_reg
[] = {
7679 { .name
= "DC_CVADP", .state
= ARM_CP_STATE_AA64
,
7680 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 1,
7681 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
7683 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
7686 static CPAccessResult
access_aa64_tid5(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7689 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID5
)) {
7690 return CP_ACCESS_TRAP_EL2
;
7693 return CP_ACCESS_OK
;
7696 static CPAccessResult
access_mte(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7699 int el
= arm_current_el(env
);
7701 if (el
< 2 && arm_is_el2_enabled(env
)) {
7702 uint64_t hcr
= arm_hcr_el2_eff(env
);
7703 if (!(hcr
& HCR_ATA
) && (!(hcr
& HCR_E2H
) || !(hcr
& HCR_TGE
))) {
7704 return CP_ACCESS_TRAP_EL2
;
7708 arm_feature(env
, ARM_FEATURE_EL3
) &&
7709 !(env
->cp15
.scr_el3
& SCR_ATA
)) {
7710 return CP_ACCESS_TRAP_EL3
;
7712 return CP_ACCESS_OK
;
7715 static uint64_t tco_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7717 return env
->pstate
& PSTATE_TCO
;
7720 static void tco_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
7722 env
->pstate
= (env
->pstate
& ~PSTATE_TCO
) | (val
& PSTATE_TCO
);
7725 static const ARMCPRegInfo mte_reginfo
[] = {
7726 { .name
= "TFSRE0_EL1", .state
= ARM_CP_STATE_AA64
,
7727 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 1,
7728 .access
= PL1_RW
, .accessfn
= access_mte
,
7729 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[0]) },
7730 { .name
= "TFSR_EL1", .state
= ARM_CP_STATE_AA64
,
7731 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 0,
7732 .access
= PL1_RW
, .accessfn
= access_mte
,
7733 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[1]) },
7734 { .name
= "TFSR_EL2", .state
= ARM_CP_STATE_AA64
,
7735 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 6, .opc2
= 0,
7736 .access
= PL2_RW
, .accessfn
= access_mte
,
7737 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[2]) },
7738 { .name
= "TFSR_EL3", .state
= ARM_CP_STATE_AA64
,
7739 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 6, .opc2
= 0,
7741 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[3]) },
7742 { .name
= "RGSR_EL1", .state
= ARM_CP_STATE_AA64
,
7743 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 5,
7744 .access
= PL1_RW
, .accessfn
= access_mte
,
7745 .fieldoffset
= offsetof(CPUARMState
, cp15
.rgsr_el1
) },
7746 { .name
= "GCR_EL1", .state
= ARM_CP_STATE_AA64
,
7747 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 6,
7748 .access
= PL1_RW
, .accessfn
= access_mte
,
7749 .fieldoffset
= offsetof(CPUARMState
, cp15
.gcr_el1
) },
7750 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
7751 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
7752 .type
= ARM_CP_NO_RAW
,
7753 .access
= PL0_RW
, .readfn
= tco_read
, .writefn
= tco_write
},
7754 { .name
= "DC_IGVAC", .state
= ARM_CP_STATE_AA64
,
7755 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 3,
7756 .type
= ARM_CP_NOP
, .access
= PL1_W
,
7758 .accessfn
= aa64_cacheop_poc_access
},
7759 { .name
= "DC_IGSW", .state
= ARM_CP_STATE_AA64
,
7760 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 4,
7762 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7763 { .name
= "DC_IGDVAC", .state
= ARM_CP_STATE_AA64
,
7764 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 5,
7765 .type
= ARM_CP_NOP
, .access
= PL1_W
,
7767 .accessfn
= aa64_cacheop_poc_access
},
7768 { .name
= "DC_IGDSW", .state
= ARM_CP_STATE_AA64
,
7769 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 6,
7771 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7772 { .name
= "DC_CGSW", .state
= ARM_CP_STATE_AA64
,
7773 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 4,
7775 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7776 { .name
= "DC_CGDSW", .state
= ARM_CP_STATE_AA64
,
7777 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 6,
7779 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7780 { .name
= "DC_CIGSW", .state
= ARM_CP_STATE_AA64
,
7781 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 4,
7783 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7784 { .name
= "DC_CIGDSW", .state
= ARM_CP_STATE_AA64
,
7785 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 6,
7787 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
7790 static const ARMCPRegInfo mte_tco_ro_reginfo
[] = {
7791 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
7792 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
7793 .type
= ARM_CP_CONST
, .access
= PL0_RW
, },
7796 static const ARMCPRegInfo mte_el0_cacheop_reginfo
[] = {
7797 { .name
= "DC_CGVAC", .state
= ARM_CP_STATE_AA64
,
7798 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 3,
7799 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7801 .accessfn
= aa64_cacheop_poc_access
},
7802 { .name
= "DC_CGDVAC", .state
= ARM_CP_STATE_AA64
,
7803 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 5,
7804 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7806 .accessfn
= aa64_cacheop_poc_access
},
7807 { .name
= "DC_CGVAP", .state
= ARM_CP_STATE_AA64
,
7808 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 3,
7809 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7811 .accessfn
= aa64_cacheop_poc_access
},
7812 { .name
= "DC_CGDVAP", .state
= ARM_CP_STATE_AA64
,
7813 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 5,
7814 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7816 .accessfn
= aa64_cacheop_poc_access
},
7817 { .name
= "DC_CGVADP", .state
= ARM_CP_STATE_AA64
,
7818 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 3,
7819 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7821 .accessfn
= aa64_cacheop_poc_access
},
7822 { .name
= "DC_CGDVADP", .state
= ARM_CP_STATE_AA64
,
7823 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 5,
7824 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7826 .accessfn
= aa64_cacheop_poc_access
},
7827 { .name
= "DC_CIGVAC", .state
= ARM_CP_STATE_AA64
,
7828 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 3,
7829 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7831 .accessfn
= aa64_cacheop_poc_access
},
7832 { .name
= "DC_CIGDVAC", .state
= ARM_CP_STATE_AA64
,
7833 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 5,
7834 .type
= ARM_CP_NOP
, .access
= PL0_W
,
7836 .accessfn
= aa64_cacheop_poc_access
},
7837 { .name
= "DC_GVA", .state
= ARM_CP_STATE_AA64
,
7838 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 3,
7839 .access
= PL0_W
, .type
= ARM_CP_DC_GVA
,
7840 #ifndef CONFIG_USER_ONLY
7841 /* Avoid overhead of an access check that always passes in user-mode */
7842 .accessfn
= aa64_zva_access
,
7846 { .name
= "DC_GZVA", .state
= ARM_CP_STATE_AA64
,
7847 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 4,
7848 .access
= PL0_W
, .type
= ARM_CP_DC_GZVA
,
7849 #ifndef CONFIG_USER_ONLY
7850 /* Avoid overhead of an access check that always passes in user-mode */
7851 .accessfn
= aa64_zva_access
,
7857 static CPAccessResult
access_scxtnum(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7860 uint64_t hcr
= arm_hcr_el2_eff(env
);
7861 int el
= arm_current_el(env
);
7863 if (el
== 0 && !((hcr
& HCR_E2H
) && (hcr
& HCR_TGE
))) {
7864 if (env
->cp15
.sctlr_el
[1] & SCTLR_TSCXT
) {
7865 if (hcr
& HCR_TGE
) {
7866 return CP_ACCESS_TRAP_EL2
;
7868 return CP_ACCESS_TRAP
;
7870 } else if (el
< 2 && (env
->cp15
.sctlr_el
[2] & SCTLR_TSCXT
)) {
7871 return CP_ACCESS_TRAP_EL2
;
7873 if (el
< 2 && arm_is_el2_enabled(env
) && !(hcr
& HCR_ENSCXT
)) {
7874 return CP_ACCESS_TRAP_EL2
;
7877 && arm_feature(env
, ARM_FEATURE_EL3
)
7878 && !(env
->cp15
.scr_el3
& SCR_ENSCXT
)) {
7879 return CP_ACCESS_TRAP_EL3
;
7881 return CP_ACCESS_OK
;
7884 static const ARMCPRegInfo scxtnum_reginfo
[] = {
7885 { .name
= "SCXTNUM_EL0", .state
= ARM_CP_STATE_AA64
,
7886 .opc0
= 3, .opc1
= 3, .crn
= 13, .crm
= 0, .opc2
= 7,
7887 .access
= PL0_RW
, .accessfn
= access_scxtnum
,
7888 .fgt
= FGT_SCXTNUM_EL0
,
7889 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[0]) },
7890 { .name
= "SCXTNUM_EL1", .state
= ARM_CP_STATE_AA64
,
7891 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 7,
7892 .access
= PL1_RW
, .accessfn
= access_scxtnum
,
7893 .fgt
= FGT_SCXTNUM_EL1
,
7894 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[1]) },
7895 { .name
= "SCXTNUM_EL2", .state
= ARM_CP_STATE_AA64
,
7896 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 7,
7897 .access
= PL2_RW
, .accessfn
= access_scxtnum
,
7898 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[2]) },
7899 { .name
= "SCXTNUM_EL3", .state
= ARM_CP_STATE_AA64
,
7900 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 7,
7902 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[3]) },
7905 static CPAccessResult
access_fgt(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7908 if (arm_current_el(env
) == 2 &&
7909 arm_feature(env
, ARM_FEATURE_EL3
) && !(env
->cp15
.scr_el3
& SCR_FGTEN
)) {
7910 return CP_ACCESS_TRAP_EL3
;
7912 return CP_ACCESS_OK
;
7915 static const ARMCPRegInfo fgt_reginfo
[] = {
7916 { .name
= "HFGRTR_EL2", .state
= ARM_CP_STATE_AA64
,
7917 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
7918 .access
= PL2_RW
, .accessfn
= access_fgt
,
7919 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_read
[FGTREG_HFGRTR
]) },
7920 { .name
= "HFGWTR_EL2", .state
= ARM_CP_STATE_AA64
,
7921 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 5,
7922 .access
= PL2_RW
, .accessfn
= access_fgt
,
7923 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_write
[FGTREG_HFGWTR
]) },
7924 { .name
= "HDFGRTR_EL2", .state
= ARM_CP_STATE_AA64
,
7925 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 1, .opc2
= 4,
7926 .access
= PL2_RW
, .accessfn
= access_fgt
,
7927 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_read
[FGTREG_HDFGRTR
]) },
7928 { .name
= "HDFGWTR_EL2", .state
= ARM_CP_STATE_AA64
,
7929 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 1, .opc2
= 5,
7930 .access
= PL2_RW
, .accessfn
= access_fgt
,
7931 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_write
[FGTREG_HDFGWTR
]) },
7932 { .name
= "HFGITR_EL2", .state
= ARM_CP_STATE_AA64
,
7933 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 6,
7934 .access
= PL2_RW
, .accessfn
= access_fgt
,
7935 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_exec
[FGTREG_HFGITR
]) },
7937 #endif /* TARGET_AARCH64 */
7939 static CPAccessResult
access_predinv(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7942 int el
= arm_current_el(env
);
7945 uint64_t sctlr
= arm_sctlr(env
, el
);
7946 if (!(sctlr
& SCTLR_EnRCTX
)) {
7947 return CP_ACCESS_TRAP
;
7949 } else if (el
== 1) {
7950 uint64_t hcr
= arm_hcr_el2_eff(env
);
7952 return CP_ACCESS_TRAP_EL2
;
7955 return CP_ACCESS_OK
;
7958 static const ARMCPRegInfo predinv_reginfo
[] = {
7959 { .name
= "CFP_RCTX", .state
= ARM_CP_STATE_AA64
,
7960 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 4,
7962 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7963 { .name
= "DVP_RCTX", .state
= ARM_CP_STATE_AA64
,
7964 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 5,
7966 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7967 { .name
= "CPP_RCTX", .state
= ARM_CP_STATE_AA64
,
7968 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 7,
7970 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7972 * Note the AArch32 opcodes have a different OPC1.
7974 { .name
= "CFPRCTX", .state
= ARM_CP_STATE_AA32
,
7975 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 4,
7977 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7978 { .name
= "DVPRCTX", .state
= ARM_CP_STATE_AA32
,
7979 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 5,
7981 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7982 { .name
= "CPPRCTX", .state
= ARM_CP_STATE_AA32
,
7983 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 7,
7985 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
7988 static uint64_t ccsidr2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7990 /* Read the high 32 bits of the current CCSIDR */
7991 return extract64(ccsidr_read(env
, ri
), 32, 32);
7994 static const ARMCPRegInfo ccsidr2_reginfo
[] = {
7995 { .name
= "CCSIDR2", .state
= ARM_CP_STATE_BOTH
,
7996 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 2,
7998 .accessfn
= access_tid4
,
7999 .readfn
= ccsidr2_read
, .type
= ARM_CP_NO_RAW
},
8002 static CPAccessResult
access_aa64_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8005 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID3
)) {
8006 return CP_ACCESS_TRAP_EL2
;
8009 return CP_ACCESS_OK
;
8012 static CPAccessResult
access_aa32_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8015 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8016 return access_aa64_tid3(env
, ri
, isread
);
8019 return CP_ACCESS_OK
;
8022 static CPAccessResult
access_jazelle(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8025 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID0
)) {
8026 return CP_ACCESS_TRAP_EL2
;
8029 return CP_ACCESS_OK
;
8032 static CPAccessResult
access_joscr_jmcr(CPUARMState
*env
,
8033 const ARMCPRegInfo
*ri
, bool isread
)
8036 * HSTR.TJDBX traps JOSCR and JMCR accesses, but it exists only
8037 * in v7A, not in v8A.
8039 if (!arm_feature(env
, ARM_FEATURE_V8
) &&
8040 arm_current_el(env
) < 2 && !arm_is_secure_below_el3(env
) &&
8041 (env
->cp15
.hstr_el2
& HSTR_TJDBX
)) {
8042 return CP_ACCESS_TRAP_EL2
;
8044 return CP_ACCESS_OK
;
8047 static const ARMCPRegInfo jazelle_regs
[] = {
8049 .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 7, .opc2
= 0,
8050 .access
= PL1_R
, .accessfn
= access_jazelle
,
8051 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8053 .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 7, .opc2
= 0,
8054 .accessfn
= access_joscr_jmcr
,
8055 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8057 .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 7, .opc2
= 0,
8058 .accessfn
= access_joscr_jmcr
,
8059 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8062 static const ARMCPRegInfo contextidr_el2
= {
8063 .name
= "CONTEXTIDR_EL2", .state
= ARM_CP_STATE_AA64
,
8064 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 1,
8066 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[2])
8069 static const ARMCPRegInfo vhe_reginfo
[] = {
8070 { .name
= "TTBR1_EL2", .state
= ARM_CP_STATE_AA64
,
8071 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 1,
8072 .access
= PL2_RW
, .writefn
= vmsa_tcr_ttbr_el2_write
,
8073 .raw_writefn
= raw_write
,
8074 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr1_el
[2]) },
8075 #ifndef CONFIG_USER_ONLY
8076 { .name
= "CNTHV_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
8077 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 2,
8079 offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].cval
),
8080 .type
= ARM_CP_IO
, .access
= PL2_RW
,
8081 .writefn
= gt_hv_cval_write
, .raw_writefn
= raw_write
},
8082 { .name
= "CNTHV_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
8083 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 0,
8084 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
8085 .resetfn
= gt_hv_timer_reset
,
8086 .readfn
= gt_hv_tval_read
, .writefn
= gt_hv_tval_write
},
8087 { .name
= "CNTHV_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
8089 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 1,
8091 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].ctl
),
8092 .writefn
= gt_hv_ctl_write
, .raw_writefn
= raw_write
},
8093 { .name
= "CNTP_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
8094 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 1,
8095 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
8096 .access
= PL2_RW
, .accessfn
= e2h_access
,
8097 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
8098 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
},
8099 { .name
= "CNTV_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
8100 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 1,
8101 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
8102 .access
= PL2_RW
, .accessfn
= e2h_access
,
8103 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
8104 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
},
8105 { .name
= "CNTP_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
8106 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 0,
8107 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
8108 .access
= PL2_RW
, .accessfn
= e2h_access
,
8109 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
},
8110 { .name
= "CNTV_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
8111 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 0,
8112 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
8113 .access
= PL2_RW
, .accessfn
= e2h_access
,
8114 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
},
8115 { .name
= "CNTP_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
8116 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 2,
8117 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
8118 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
8119 .access
= PL2_RW
, .accessfn
= e2h_access
,
8120 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
},
8121 { .name
= "CNTV_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
8122 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 2,
8123 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
8124 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
8125 .access
= PL2_RW
, .accessfn
= e2h_access
,
8126 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
},
8130 #ifndef CONFIG_USER_ONLY
8131 static const ARMCPRegInfo ats1e1_reginfo
[] = {
8132 { .name
= "AT_S1E1RP", .state
= ARM_CP_STATE_AA64
,
8133 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
8134 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
8135 .fgt
= FGT_ATS1E1RP
,
8136 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
8137 { .name
= "AT_S1E1WP", .state
= ARM_CP_STATE_AA64
,
8138 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
8139 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
8140 .fgt
= FGT_ATS1E1WP
,
8141 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
8144 static const ARMCPRegInfo ats1cp_reginfo
[] = {
8145 { .name
= "ATS1CPRP",
8146 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
8147 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
8148 .writefn
= ats_write
},
8149 { .name
= "ATS1CPWP",
8150 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
8151 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
8152 .writefn
= ats_write
},
8157 * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and
8158 * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field
8159 * is non-zero, which is never for ARMv7, optionally in ARMv8
8160 * and mandatorily for ARMv8.2 and up.
8161 * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's
8162 * implementation is RAZ/WI we can ignore this detail, as we
8165 static const ARMCPRegInfo actlr2_hactlr2_reginfo
[] = {
8166 { .name
= "ACTLR2", .state
= ARM_CP_STATE_AA32
,
8167 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 3,
8168 .access
= PL1_RW
, .accessfn
= access_tacr
,
8169 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8170 { .name
= "HACTLR2", .state
= ARM_CP_STATE_AA32
,
8171 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 3,
8172 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
8176 void register_cp_regs_for_features(ARMCPU
*cpu
)
8178 /* Register all the coprocessor registers based on feature bits */
8179 CPUARMState
*env
= &cpu
->env
;
8180 if (arm_feature(env
, ARM_FEATURE_M
)) {
8181 /* M profile has no coprocessor registers */
8185 define_arm_cp_regs(cpu
, cp_reginfo
);
8186 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
8188 * Must go early as it is full of wildcards that may be
8189 * overridden by later definitions.
8191 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
8194 if (arm_feature(env
, ARM_FEATURE_V6
)) {
8195 /* The ID registers all have impdef reset values */
8196 ARMCPRegInfo v6_idregs
[] = {
8197 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
8198 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
8199 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8200 .accessfn
= access_aa32_tid3
,
8201 .resetvalue
= cpu
->isar
.id_pfr0
},
8203 * ID_PFR1 is not a plain ARM_CP_CONST because we don't know
8204 * the value of the GIC field until after we define these regs.
8206 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
8207 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
8208 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
8209 .accessfn
= access_aa32_tid3
,
8210 #ifdef CONFIG_USER_ONLY
8211 .type
= ARM_CP_CONST
,
8212 .resetvalue
= cpu
->isar
.id_pfr1
,
8214 .type
= ARM_CP_NO_RAW
,
8215 .accessfn
= access_aa32_tid3
,
8216 .readfn
= id_pfr1_read
,
8217 .writefn
= arm_cp_write_ignore
8220 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
8221 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
8222 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8223 .accessfn
= access_aa32_tid3
,
8224 .resetvalue
= cpu
->isar
.id_dfr0
},
8225 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
8226 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
8227 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8228 .accessfn
= access_aa32_tid3
,
8229 .resetvalue
= cpu
->id_afr0
},
8230 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
8231 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
8232 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8233 .accessfn
= access_aa32_tid3
,
8234 .resetvalue
= cpu
->isar
.id_mmfr0
},
8235 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
8236 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
8237 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8238 .accessfn
= access_aa32_tid3
,
8239 .resetvalue
= cpu
->isar
.id_mmfr1
},
8240 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
8241 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
8242 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8243 .accessfn
= access_aa32_tid3
,
8244 .resetvalue
= cpu
->isar
.id_mmfr2
},
8245 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
8246 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
8247 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8248 .accessfn
= access_aa32_tid3
,
8249 .resetvalue
= cpu
->isar
.id_mmfr3
},
8250 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
8251 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
8252 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8253 .accessfn
= access_aa32_tid3
,
8254 .resetvalue
= cpu
->isar
.id_isar0
},
8255 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
8256 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
8257 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8258 .accessfn
= access_aa32_tid3
,
8259 .resetvalue
= cpu
->isar
.id_isar1
},
8260 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
8261 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
8262 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8263 .accessfn
= access_aa32_tid3
,
8264 .resetvalue
= cpu
->isar
.id_isar2
},
8265 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
8266 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
8267 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8268 .accessfn
= access_aa32_tid3
,
8269 .resetvalue
= cpu
->isar
.id_isar3
},
8270 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
8271 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
8272 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8273 .accessfn
= access_aa32_tid3
,
8274 .resetvalue
= cpu
->isar
.id_isar4
},
8275 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
8276 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
8277 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8278 .accessfn
= access_aa32_tid3
,
8279 .resetvalue
= cpu
->isar
.id_isar5
},
8280 { .name
= "ID_MMFR4", .state
= ARM_CP_STATE_BOTH
,
8281 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 6,
8282 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8283 .accessfn
= access_aa32_tid3
,
8284 .resetvalue
= cpu
->isar
.id_mmfr4
},
8285 { .name
= "ID_ISAR6", .state
= ARM_CP_STATE_BOTH
,
8286 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 7,
8287 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8288 .accessfn
= access_aa32_tid3
,
8289 .resetvalue
= cpu
->isar
.id_isar6
},
8291 define_arm_cp_regs(cpu
, v6_idregs
);
8292 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
8294 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
8296 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
8297 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
8299 if (arm_feature(env
, ARM_FEATURE_V7MP
) &&
8300 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
8301 define_arm_cp_regs(cpu
, v7mp_cp_reginfo
);
8303 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
8304 define_arm_cp_regs(cpu
, pmovsset_cp_reginfo
);
8306 if (arm_feature(env
, ARM_FEATURE_V7
)) {
8307 ARMCPRegInfo clidr
= {
8308 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
8309 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
8310 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8311 .accessfn
= access_tid4
,
8312 .fgt
= FGT_CLIDR_EL1
,
8313 .resetvalue
= cpu
->clidr
8315 define_one_arm_cp_reg(cpu
, &clidr
);
8316 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
8317 define_debug_regs(cpu
);
8318 define_pmu_regs(cpu
);
8320 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
8322 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8324 * v8 ID registers, which all have impdef reset values.
8325 * Note that within the ID register ranges the unused slots
8326 * must all RAZ, not UNDEF; future architecture versions may
8327 * define new registers here.
8328 * ID registers which are AArch64 views of the AArch32 ID registers
8329 * which already existed in v6 and v7 are handled elsewhere,
8333 ARMCPRegInfo v8_idregs
[] = {
8335 * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system
8336 * emulation because we don't know the right value for the
8337 * GIC field until after we define these regs.
8339 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8340 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
8342 #ifdef CONFIG_USER_ONLY
8343 .type
= ARM_CP_CONST
,
8344 .resetvalue
= cpu
->isar
.id_aa64pfr0
8346 .type
= ARM_CP_NO_RAW
,
8347 .accessfn
= access_aa64_tid3
,
8348 .readfn
= id_aa64pfr0_read
,
8349 .writefn
= arm_cp_write_ignore
8352 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8353 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
8354 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8355 .accessfn
= access_aa64_tid3
,
8356 .resetvalue
= cpu
->isar
.id_aa64pfr1
},
8357 { .name
= "ID_AA64PFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8358 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 2,
8359 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8360 .accessfn
= access_aa64_tid3
,
8362 { .name
= "ID_AA64PFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8363 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 3,
8364 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8365 .accessfn
= access_aa64_tid3
,
8367 { .name
= "ID_AA64ZFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8368 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 4,
8369 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8370 .accessfn
= access_aa64_tid3
,
8371 .resetvalue
= cpu
->isar
.id_aa64zfr0
},
8372 { .name
= "ID_AA64SMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8373 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 5,
8374 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8375 .accessfn
= access_aa64_tid3
,
8376 .resetvalue
= cpu
->isar
.id_aa64smfr0
},
8377 { .name
= "ID_AA64PFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8378 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 6,
8379 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8380 .accessfn
= access_aa64_tid3
,
8382 { .name
= "ID_AA64PFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8383 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 7,
8384 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8385 .accessfn
= access_aa64_tid3
,
8387 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8388 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
8389 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8390 .accessfn
= access_aa64_tid3
,
8391 .resetvalue
= cpu
->isar
.id_aa64dfr0
},
8392 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8393 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
8394 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8395 .accessfn
= access_aa64_tid3
,
8396 .resetvalue
= cpu
->isar
.id_aa64dfr1
},
8397 { .name
= "ID_AA64DFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8398 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 2,
8399 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8400 .accessfn
= access_aa64_tid3
,
8402 { .name
= "ID_AA64DFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8403 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 3,
8404 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8405 .accessfn
= access_aa64_tid3
,
8407 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8408 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
8409 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8410 .accessfn
= access_aa64_tid3
,
8411 .resetvalue
= cpu
->id_aa64afr0
},
8412 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8413 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
8414 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8415 .accessfn
= access_aa64_tid3
,
8416 .resetvalue
= cpu
->id_aa64afr1
},
8417 { .name
= "ID_AA64AFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8418 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 6,
8419 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8420 .accessfn
= access_aa64_tid3
,
8422 { .name
= "ID_AA64AFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8423 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 7,
8424 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8425 .accessfn
= access_aa64_tid3
,
8427 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
8428 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
8429 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8430 .accessfn
= access_aa64_tid3
,
8431 .resetvalue
= cpu
->isar
.id_aa64isar0
},
8432 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
8433 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
8434 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8435 .accessfn
= access_aa64_tid3
,
8436 .resetvalue
= cpu
->isar
.id_aa64isar1
},
8437 { .name
= "ID_AA64ISAR2_EL1", .state
= ARM_CP_STATE_AA64
,
8438 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 2,
8439 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8440 .accessfn
= access_aa64_tid3
,
8441 .resetvalue
= cpu
->isar
.id_aa64isar2
},
8442 { .name
= "ID_AA64ISAR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8443 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 3,
8444 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8445 .accessfn
= access_aa64_tid3
,
8447 { .name
= "ID_AA64ISAR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8448 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 4,
8449 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8450 .accessfn
= access_aa64_tid3
,
8452 { .name
= "ID_AA64ISAR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8453 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 5,
8454 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8455 .accessfn
= access_aa64_tid3
,
8457 { .name
= "ID_AA64ISAR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8458 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 6,
8459 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8460 .accessfn
= access_aa64_tid3
,
8462 { .name
= "ID_AA64ISAR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8463 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 7,
8464 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8465 .accessfn
= access_aa64_tid3
,
8467 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8468 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
8469 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8470 .accessfn
= access_aa64_tid3
,
8471 .resetvalue
= cpu
->isar
.id_aa64mmfr0
},
8472 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8473 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
8474 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8475 .accessfn
= access_aa64_tid3
,
8476 .resetvalue
= cpu
->isar
.id_aa64mmfr1
},
8477 { .name
= "ID_AA64MMFR2_EL1", .state
= ARM_CP_STATE_AA64
,
8478 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 2,
8479 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8480 .accessfn
= access_aa64_tid3
,
8481 .resetvalue
= cpu
->isar
.id_aa64mmfr2
},
8482 { .name
= "ID_AA64MMFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8483 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 3,
8484 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8485 .accessfn
= access_aa64_tid3
,
8487 { .name
= "ID_AA64MMFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8488 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 4,
8489 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8490 .accessfn
= access_aa64_tid3
,
8492 { .name
= "ID_AA64MMFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8493 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 5,
8494 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8495 .accessfn
= access_aa64_tid3
,
8497 { .name
= "ID_AA64MMFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8498 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 6,
8499 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8500 .accessfn
= access_aa64_tid3
,
8502 { .name
= "ID_AA64MMFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8503 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 7,
8504 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8505 .accessfn
= access_aa64_tid3
,
8507 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8508 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
8509 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8510 .accessfn
= access_aa64_tid3
,
8511 .resetvalue
= cpu
->isar
.mvfr0
},
8512 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8513 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
8514 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8515 .accessfn
= access_aa64_tid3
,
8516 .resetvalue
= cpu
->isar
.mvfr1
},
8517 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
8518 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
8519 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8520 .accessfn
= access_aa64_tid3
,
8521 .resetvalue
= cpu
->isar
.mvfr2
},
8523 * "0, c0, c3, {0,1,2}" are the encodings corresponding to
8524 * AArch64 MVFR[012]_EL1. Define the STATE_AA32 encoding
8525 * as RAZ, since it is in the "reserved for future ID
8526 * registers, RAZ" part of the AArch32 encoding space.
8528 { .name
= "RES_0_C0_C3_0", .state
= ARM_CP_STATE_AA32
,
8529 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
8530 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8531 .accessfn
= access_aa64_tid3
,
8533 { .name
= "RES_0_C0_C3_1", .state
= ARM_CP_STATE_AA32
,
8534 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
8535 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8536 .accessfn
= access_aa64_tid3
,
8538 { .name
= "RES_0_C0_C3_2", .state
= ARM_CP_STATE_AA32
,
8539 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
8540 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8541 .accessfn
= access_aa64_tid3
,
8544 * Other encodings in "0, c0, c3, ..." are STATE_BOTH because
8545 * they're also RAZ for AArch64, and in v8 are gradually
8546 * being filled with AArch64-view-of-AArch32-ID-register
8547 * for new ID registers.
8549 { .name
= "RES_0_C0_C3_3", .state
= ARM_CP_STATE_BOTH
,
8550 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 3,
8551 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8552 .accessfn
= access_aa64_tid3
,
8554 { .name
= "ID_PFR2", .state
= ARM_CP_STATE_BOTH
,
8555 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 4,
8556 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8557 .accessfn
= access_aa64_tid3
,
8558 .resetvalue
= cpu
->isar
.id_pfr2
},
8559 { .name
= "ID_DFR1", .state
= ARM_CP_STATE_BOTH
,
8560 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 5,
8561 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8562 .accessfn
= access_aa64_tid3
,
8563 .resetvalue
= cpu
->isar
.id_dfr1
},
8564 { .name
= "ID_MMFR5", .state
= ARM_CP_STATE_BOTH
,
8565 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 6,
8566 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8567 .accessfn
= access_aa64_tid3
,
8568 .resetvalue
= cpu
->isar
.id_mmfr5
},
8569 { .name
= "RES_0_C0_C3_7", .state
= ARM_CP_STATE_BOTH
,
8570 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 7,
8571 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8572 .accessfn
= access_aa64_tid3
,
8574 { .name
= "PMCEID0", .state
= ARM_CP_STATE_AA32
,
8575 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 6,
8576 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8577 .fgt
= FGT_PMCEIDN_EL0
,
8578 .resetvalue
= extract64(cpu
->pmceid0
, 0, 32) },
8579 { .name
= "PMCEID0_EL0", .state
= ARM_CP_STATE_AA64
,
8580 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 6,
8581 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8582 .fgt
= FGT_PMCEIDN_EL0
,
8583 .resetvalue
= cpu
->pmceid0
},
8584 { .name
= "PMCEID1", .state
= ARM_CP_STATE_AA32
,
8585 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 7,
8586 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8587 .fgt
= FGT_PMCEIDN_EL0
,
8588 .resetvalue
= extract64(cpu
->pmceid1
, 0, 32) },
8589 { .name
= "PMCEID1_EL0", .state
= ARM_CP_STATE_AA64
,
8590 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 7,
8591 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8592 .fgt
= FGT_PMCEIDN_EL0
,
8593 .resetvalue
= cpu
->pmceid1
},
8595 #ifdef CONFIG_USER_ONLY
8596 static const ARMCPRegUserSpaceInfo v8_user_idregs
[] = {
8597 { .name
= "ID_AA64PFR0_EL1",
8598 .exported_bits
= R_ID_AA64PFR0_FP_MASK
|
8599 R_ID_AA64PFR0_ADVSIMD_MASK
|
8600 R_ID_AA64PFR0_SVE_MASK
|
8601 R_ID_AA64PFR0_DIT_MASK
,
8602 .fixed_bits
= (0x1u
<< R_ID_AA64PFR0_EL0_SHIFT
) |
8603 (0x1u
<< R_ID_AA64PFR0_EL1_SHIFT
) },
8604 { .name
= "ID_AA64PFR1_EL1",
8605 .exported_bits
= R_ID_AA64PFR1_BT_MASK
|
8606 R_ID_AA64PFR1_SSBS_MASK
|
8607 R_ID_AA64PFR1_MTE_MASK
|
8608 R_ID_AA64PFR1_SME_MASK
},
8609 { .name
= "ID_AA64PFR*_EL1_RESERVED",
8611 { .name
= "ID_AA64ZFR0_EL1",
8612 .exported_bits
= R_ID_AA64ZFR0_SVEVER_MASK
|
8613 R_ID_AA64ZFR0_AES_MASK
|
8614 R_ID_AA64ZFR0_BITPERM_MASK
|
8615 R_ID_AA64ZFR0_BFLOAT16_MASK
|
8616 R_ID_AA64ZFR0_SHA3_MASK
|
8617 R_ID_AA64ZFR0_SM4_MASK
|
8618 R_ID_AA64ZFR0_I8MM_MASK
|
8619 R_ID_AA64ZFR0_F32MM_MASK
|
8620 R_ID_AA64ZFR0_F64MM_MASK
},
8621 { .name
= "ID_AA64SMFR0_EL1",
8622 .exported_bits
= R_ID_AA64SMFR0_F32F32_MASK
|
8623 R_ID_AA64SMFR0_BI32I32_MASK
|
8624 R_ID_AA64SMFR0_B16F32_MASK
|
8625 R_ID_AA64SMFR0_F16F32_MASK
|
8626 R_ID_AA64SMFR0_I8I32_MASK
|
8627 R_ID_AA64SMFR0_F16F16_MASK
|
8628 R_ID_AA64SMFR0_B16B16_MASK
|
8629 R_ID_AA64SMFR0_I16I32_MASK
|
8630 R_ID_AA64SMFR0_F64F64_MASK
|
8631 R_ID_AA64SMFR0_I16I64_MASK
|
8632 R_ID_AA64SMFR0_SMEVER_MASK
|
8633 R_ID_AA64SMFR0_FA64_MASK
},
8634 { .name
= "ID_AA64MMFR0_EL1",
8635 .exported_bits
= R_ID_AA64MMFR0_ECV_MASK
,
8636 .fixed_bits
= (0xfu
<< R_ID_AA64MMFR0_TGRAN64_SHIFT
) |
8637 (0xfu
<< R_ID_AA64MMFR0_TGRAN4_SHIFT
) },
8638 { .name
= "ID_AA64MMFR1_EL1",
8639 .exported_bits
= R_ID_AA64MMFR1_AFP_MASK
},
8640 { .name
= "ID_AA64MMFR2_EL1",
8641 .exported_bits
= R_ID_AA64MMFR2_AT_MASK
},
8642 { .name
= "ID_AA64MMFR*_EL1_RESERVED",
8644 { .name
= "ID_AA64DFR0_EL1",
8645 .fixed_bits
= (0x6u
<< R_ID_AA64DFR0_DEBUGVER_SHIFT
) },
8646 { .name
= "ID_AA64DFR1_EL1" },
8647 { .name
= "ID_AA64DFR*_EL1_RESERVED",
8649 { .name
= "ID_AA64AFR*",
8651 { .name
= "ID_AA64ISAR0_EL1",
8652 .exported_bits
= R_ID_AA64ISAR0_AES_MASK
|
8653 R_ID_AA64ISAR0_SHA1_MASK
|
8654 R_ID_AA64ISAR0_SHA2_MASK
|
8655 R_ID_AA64ISAR0_CRC32_MASK
|
8656 R_ID_AA64ISAR0_ATOMIC_MASK
|
8657 R_ID_AA64ISAR0_RDM_MASK
|
8658 R_ID_AA64ISAR0_SHA3_MASK
|
8659 R_ID_AA64ISAR0_SM3_MASK
|
8660 R_ID_AA64ISAR0_SM4_MASK
|
8661 R_ID_AA64ISAR0_DP_MASK
|
8662 R_ID_AA64ISAR0_FHM_MASK
|
8663 R_ID_AA64ISAR0_TS_MASK
|
8664 R_ID_AA64ISAR0_RNDR_MASK
},
8665 { .name
= "ID_AA64ISAR1_EL1",
8666 .exported_bits
= R_ID_AA64ISAR1_DPB_MASK
|
8667 R_ID_AA64ISAR1_APA_MASK
|
8668 R_ID_AA64ISAR1_API_MASK
|
8669 R_ID_AA64ISAR1_JSCVT_MASK
|
8670 R_ID_AA64ISAR1_FCMA_MASK
|
8671 R_ID_AA64ISAR1_LRCPC_MASK
|
8672 R_ID_AA64ISAR1_GPA_MASK
|
8673 R_ID_AA64ISAR1_GPI_MASK
|
8674 R_ID_AA64ISAR1_FRINTTS_MASK
|
8675 R_ID_AA64ISAR1_SB_MASK
|
8676 R_ID_AA64ISAR1_BF16_MASK
|
8677 R_ID_AA64ISAR1_DGH_MASK
|
8678 R_ID_AA64ISAR1_I8MM_MASK
},
8679 { .name
= "ID_AA64ISAR2_EL1",
8680 .exported_bits
= R_ID_AA64ISAR2_WFXT_MASK
|
8681 R_ID_AA64ISAR2_RPRES_MASK
|
8682 R_ID_AA64ISAR2_GPA3_MASK
|
8683 R_ID_AA64ISAR2_APA3_MASK
|
8684 R_ID_AA64ISAR2_MOPS_MASK
|
8685 R_ID_AA64ISAR2_BC_MASK
|
8686 R_ID_AA64ISAR2_RPRFM_MASK
|
8687 R_ID_AA64ISAR2_CSSC_MASK
},
8688 { .name
= "ID_AA64ISAR*_EL1_RESERVED",
8691 modify_arm_cp_regs(v8_idregs
, v8_user_idregs
);
8694 * RVBAR_EL1 and RMR_EL1 only implemented if EL1 is the highest EL.
8695 * TODO: For RMR, a write with bit 1 set should do something with
8696 * cpu_reset(). In the meantime, "the bit is strictly a request",
8697 * so we are in spec just ignoring writes.
8699 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
8700 !arm_feature(env
, ARM_FEATURE_EL2
)) {
8701 ARMCPRegInfo el1_reset_regs
[] = {
8702 { .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_BOTH
,
8703 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
8705 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
) },
8706 { .name
= "RMR_EL1", .state
= ARM_CP_STATE_BOTH
,
8707 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 2,
8708 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
8709 .resetvalue
= arm_feature(env
, ARM_FEATURE_AARCH64
) }
8711 define_arm_cp_regs(cpu
, el1_reset_regs
);
8713 define_arm_cp_regs(cpu
, v8_idregs
);
8714 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
8716 for (i
= 4; i
< 16; i
++) {
8718 * Encodings in "0, c0, {c4-c7}, {0-7}" are RAZ for AArch32.
8719 * For pre-v8 cores there are RAZ patterns for these in
8720 * id_pre_v8_midr_cp_reginfo[]; for v8 we do that here.
8721 * v8 extends the "must RAZ" part of the ID register space
8722 * to also cover c0, 0, c{8-15}, {0-7}.
8723 * These are STATE_AA32 because in the AArch64 sysreg space
8724 * c4-c7 is where the AArch64 ID registers live (and we've
8725 * already defined those in v8_idregs[]), and c8-c15 are not
8726 * "must RAZ" for AArch64.
8728 g_autofree
char *name
= g_strdup_printf("RES_0_C0_C%d_X", i
);
8729 ARMCPRegInfo v8_aa32_raz_idregs
= {
8731 .state
= ARM_CP_STATE_AA32
,
8732 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= CP_ANY
,
8733 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8734 .accessfn
= access_aa64_tid3
,
8736 define_one_arm_cp_reg(cpu
, &v8_aa32_raz_idregs
);
8741 * Register the base EL2 cpregs.
8742 * Pre v8, these registers are implemented only as part of the
8743 * Virtualization Extensions (EL2 present). Beginning with v8,
8744 * if EL2 is missing but EL3 is enabled, mostly these become
8745 * RES0 from EL3, with some specific exceptions.
8747 if (arm_feature(env
, ARM_FEATURE_EL2
)
8748 || (arm_feature(env
, ARM_FEATURE_EL3
)
8749 && arm_feature(env
, ARM_FEATURE_V8
))) {
8750 uint64_t vmpidr_def
= mpidr_read_val(env
);
8751 ARMCPRegInfo vpidr_regs
[] = {
8752 { .name
= "VPIDR", .state
= ARM_CP_STATE_AA32
,
8753 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
8754 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
8755 .resetvalue
= cpu
->midr
,
8756 .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_C_NZ
,
8757 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vpidr_el2
) },
8758 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
8759 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
8760 .access
= PL2_RW
, .resetvalue
= cpu
->midr
,
8761 .type
= ARM_CP_EL3_NO_EL2_C_NZ
,
8762 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
8763 { .name
= "VMPIDR", .state
= ARM_CP_STATE_AA32
,
8764 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
8765 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
8766 .resetvalue
= vmpidr_def
,
8767 .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_C_NZ
,
8768 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vmpidr_el2
) },
8769 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
8770 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
8771 .access
= PL2_RW
, .resetvalue
= vmpidr_def
,
8772 .type
= ARM_CP_EL3_NO_EL2_C_NZ
,
8773 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
8776 * The only field of MDCR_EL2 that has a defined architectural reset
8777 * value is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
8779 ARMCPRegInfo mdcr_el2
= {
8780 .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
, .type
= ARM_CP_IO
,
8781 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
8782 .writefn
= mdcr_el2_write
,
8783 .access
= PL2_RW
, .resetvalue
= pmu_num_counters(env
),
8784 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el2
),
8786 define_one_arm_cp_reg(cpu
, &mdcr_el2
);
8787 define_arm_cp_regs(cpu
, vpidr_regs
);
8788 define_arm_cp_regs(cpu
, el2_cp_reginfo
);
8789 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8790 define_arm_cp_regs(cpu
, el2_v8_cp_reginfo
);
8792 if (cpu_isar_feature(aa64_sel2
, cpu
)) {
8793 define_arm_cp_regs(cpu
, el2_sec_cp_reginfo
);
8796 * RVBAR_EL2 and RMR_EL2 only implemented if EL2 is the highest EL.
8797 * See commentary near RMR_EL1.
8799 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
8800 static const ARMCPRegInfo el2_reset_regs
[] = {
8801 { .name
= "RVBAR_EL2", .state
= ARM_CP_STATE_AA64
,
8802 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 1,
8804 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
) },
8805 { .name
= "RVBAR", .type
= ARM_CP_ALIAS
,
8806 .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
8808 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
) },
8809 { .name
= "RMR_EL2", .state
= ARM_CP_STATE_AA64
,
8810 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 2,
8811 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 1 },
8813 define_arm_cp_regs(cpu
, el2_reset_regs
);
8817 /* Register the base EL3 cpregs. */
8818 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
8819 define_arm_cp_regs(cpu
, el3_cp_reginfo
);
8820 ARMCPRegInfo el3_regs
[] = {
8821 { .name
= "RVBAR_EL3", .state
= ARM_CP_STATE_AA64
,
8822 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 1,
8824 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
), },
8825 { .name
= "RMR_EL3", .state
= ARM_CP_STATE_AA64
,
8826 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 2,
8827 .access
= PL3_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 1 },
8828 { .name
= "RMR", .state
= ARM_CP_STATE_AA32
,
8829 .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 2,
8830 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
8831 .resetvalue
= arm_feature(env
, ARM_FEATURE_AARCH64
) },
8832 { .name
= "SCTLR_EL3", .state
= ARM_CP_STATE_AA64
,
8833 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 0,
8835 .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
8836 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[3]),
8837 .resetvalue
= cpu
->reset_sctlr
},
8840 define_arm_cp_regs(cpu
, el3_regs
);
8843 * The behaviour of NSACR is sufficiently various that we don't
8844 * try to describe it in a single reginfo:
8845 * if EL3 is 64 bit, then trap to EL3 from S EL1,
8846 * reads as constant 0xc00 from NS EL1 and NS EL2
8847 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
8848 * if v7 without EL3, register doesn't exist
8849 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
8851 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
8852 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
8853 static const ARMCPRegInfo nsacr
= {
8854 .name
= "NSACR", .type
= ARM_CP_CONST
,
8855 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
8856 .access
= PL1_RW
, .accessfn
= nsacr_access
,
8859 define_one_arm_cp_reg(cpu
, &nsacr
);
8861 static const ARMCPRegInfo nsacr
= {
8863 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
8864 .access
= PL3_RW
| PL1_R
,
8866 .fieldoffset
= offsetof(CPUARMState
, cp15
.nsacr
)
8868 define_one_arm_cp_reg(cpu
, &nsacr
);
8871 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8872 static const ARMCPRegInfo nsacr
= {
8873 .name
= "NSACR", .type
= ARM_CP_CONST
,
8874 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
8878 define_one_arm_cp_reg(cpu
, &nsacr
);
8882 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
8883 if (arm_feature(env
, ARM_FEATURE_V6
)) {
8884 /* PMSAv6 not implemented */
8885 assert(arm_feature(env
, ARM_FEATURE_V7
));
8886 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
8887 define_arm_cp_regs(cpu
, pmsav7_cp_reginfo
);
8889 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
8892 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
8893 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
8894 /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */
8895 if (cpu_isar_feature(aa32_hpd
, cpu
)) {
8896 define_one_arm_cp_reg(cpu
, &ttbcr2_reginfo
);
8899 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
8900 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
8902 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
8903 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
8905 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
8906 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
8908 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
8909 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
8911 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
8912 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
8914 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
8915 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
8917 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
8918 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
8920 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
8921 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
8923 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
8924 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
8926 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
8927 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
8929 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
8930 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
8932 if (cpu_isar_feature(aa32_jazelle
, cpu
)) {
8933 define_arm_cp_regs(cpu
, jazelle_regs
);
8936 * Slightly awkwardly, the OMAP and StrongARM cores need all of
8937 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
8938 * be read-only (ie write causes UNDEF exception).
8941 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
8943 * Pre-v8 MIDR space.
8944 * Note that the MIDR isn't a simple constant register because
8945 * of the TI925 behaviour where writes to another register can
8946 * cause the MIDR value to change.
8948 * Unimplemented registers in the c15 0 0 0 space default to
8949 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
8950 * and friends override accordingly.
8953 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
8954 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
8955 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
8956 .readfn
= midr_read
,
8957 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
8958 .type
= ARM_CP_OVERRIDE
},
8959 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
8961 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
8962 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8964 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
8965 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8967 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
8968 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8970 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
8971 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8973 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
8974 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8976 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
8977 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
8978 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
8979 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
, .resetvalue
= cpu
->midr
,
8980 .fgt
= FGT_MIDR_EL1
,
8981 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
8982 .readfn
= midr_read
},
8983 /* crn = 0 op1 = 0 crm = 0 op2 = 7 : AArch32 aliases of MIDR */
8984 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
8985 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 7,
8986 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
8987 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
8988 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
8990 .accessfn
= access_aa64_tid1
,
8991 .fgt
= FGT_REVIDR_EL1
,
8992 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->revidr
},
8994 ARMCPRegInfo id_v8_midr_alias_cp_reginfo
= {
8995 .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
8996 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
8997 .access
= PL1_R
, .resetvalue
= cpu
->midr
8999 ARMCPRegInfo id_cp_reginfo
[] = {
9000 /* These are common to v8 and pre-v8 */
9002 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
9003 .access
= PL1_R
, .accessfn
= ctr_el0_access
,
9004 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
9005 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
9006 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
9007 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
9009 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
9010 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
9012 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
9014 .accessfn
= access_aa32_tid1
,
9015 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9017 /* TLBTR is specific to VMSA */
9018 ARMCPRegInfo id_tlbtr_reginfo
= {
9020 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
9022 .accessfn
= access_aa32_tid1
,
9023 .type
= ARM_CP_CONST
, .resetvalue
= 0,
9025 /* MPUIR is specific to PMSA V6+ */
9026 ARMCPRegInfo id_mpuir_reginfo
= {
9028 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
9029 .access
= PL1_R
, .type
= ARM_CP_CONST
,
9030 .resetvalue
= cpu
->pmsav7_dregion
<< 8
9032 /* HMPUIR is specific to PMSA V8 */
9033 ARMCPRegInfo id_hmpuir_reginfo
= {
9035 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 4,
9036 .access
= PL2_R
, .type
= ARM_CP_CONST
,
9037 .resetvalue
= cpu
->pmsav8r_hdregion
9039 static const ARMCPRegInfo crn0_wi_reginfo
= {
9040 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
9041 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
9042 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
9044 #ifdef CONFIG_USER_ONLY
9045 static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo
[] = {
9046 { .name
= "MIDR_EL1",
9047 .exported_bits
= R_MIDR_EL1_REVISION_MASK
|
9048 R_MIDR_EL1_PARTNUM_MASK
|
9049 R_MIDR_EL1_ARCHITECTURE_MASK
|
9050 R_MIDR_EL1_VARIANT_MASK
|
9051 R_MIDR_EL1_IMPLEMENTER_MASK
},
9052 { .name
= "REVIDR_EL1" },
9054 modify_arm_cp_regs(id_v8_midr_cp_reginfo
, id_v8_user_midr_cp_reginfo
);
9056 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
9057 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
9060 * Register the blanket "writes ignored" value first to cover the
9061 * whole space. Then update the specific ID registers to allow write
9062 * access, so that they ignore writes rather than causing them to
9065 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
9066 for (i
= 0; i
< ARRAY_SIZE(id_pre_v8_midr_cp_reginfo
); ++i
) {
9067 id_pre_v8_midr_cp_reginfo
[i
].access
= PL1_RW
;
9069 for (i
= 0; i
< ARRAY_SIZE(id_cp_reginfo
); ++i
) {
9070 id_cp_reginfo
[i
].access
= PL1_RW
;
9072 id_mpuir_reginfo
.access
= PL1_RW
;
9073 id_tlbtr_reginfo
.access
= PL1_RW
;
9075 if (arm_feature(env
, ARM_FEATURE_V8
)) {
9076 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
9077 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
9078 define_one_arm_cp_reg(cpu
, &id_v8_midr_alias_cp_reginfo
);
9081 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
9083 define_arm_cp_regs(cpu
, id_cp_reginfo
);
9084 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
9085 define_one_arm_cp_reg(cpu
, &id_tlbtr_reginfo
);
9086 } else if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
9087 arm_feature(env
, ARM_FEATURE_V8
)) {
9091 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
9092 define_one_arm_cp_reg(cpu
, &id_hmpuir_reginfo
);
9093 define_arm_cp_regs(cpu
, pmsav8r_cp_reginfo
);
9095 /* Register alias is only valid for first 32 indexes */
9096 for (i
= 0; i
< MIN(cpu
->pmsav7_dregion
, 32); ++i
) {
9097 uint8_t crm
= 0b1000 | extract32(i
, 1, 3);
9098 uint8_t opc1
= extract32(i
, 4, 1);
9099 uint8_t opc2
= extract32(i
, 0, 1) << 2;
9101 tmp_string
= g_strdup_printf("PRBAR%u", i
);
9102 ARMCPRegInfo tmp_prbarn_reginfo
= {
9103 .name
= tmp_string
, .type
= ARM_CP_ALIAS
| ARM_CP_NO_RAW
,
9104 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
9105 .access
= PL1_RW
, .resetvalue
= 0,
9106 .accessfn
= access_tvm_trvm
,
9107 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
9109 define_one_arm_cp_reg(cpu
, &tmp_prbarn_reginfo
);
9112 opc2
= extract32(i
, 0, 1) << 2 | 0x1;
9113 tmp_string
= g_strdup_printf("PRLAR%u", i
);
9114 ARMCPRegInfo tmp_prlarn_reginfo
= {
9115 .name
= tmp_string
, .type
= ARM_CP_ALIAS
| ARM_CP_NO_RAW
,
9116 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
9117 .access
= PL1_RW
, .resetvalue
= 0,
9118 .accessfn
= access_tvm_trvm
,
9119 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
9121 define_one_arm_cp_reg(cpu
, &tmp_prlarn_reginfo
);
9125 /* Register alias is only valid for first 32 indexes */
9126 for (i
= 0; i
< MIN(cpu
->pmsav8r_hdregion
, 32); ++i
) {
9127 uint8_t crm
= 0b1000 | extract32(i
, 1, 3);
9128 uint8_t opc1
= 0b100 | extract32(i
, 4, 1);
9129 uint8_t opc2
= extract32(i
, 0, 1) << 2;
9131 tmp_string
= g_strdup_printf("HPRBAR%u", i
);
9132 ARMCPRegInfo tmp_hprbarn_reginfo
= {
9134 .type
= ARM_CP_NO_RAW
,
9135 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
9136 .access
= PL2_RW
, .resetvalue
= 0,
9137 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
9139 define_one_arm_cp_reg(cpu
, &tmp_hprbarn_reginfo
);
9142 opc2
= extract32(i
, 0, 1) << 2 | 0x1;
9143 tmp_string
= g_strdup_printf("HPRLAR%u", i
);
9144 ARMCPRegInfo tmp_hprlarn_reginfo
= {
9146 .type
= ARM_CP_NO_RAW
,
9147 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
9148 .access
= PL2_RW
, .resetvalue
= 0,
9149 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
9151 define_one_arm_cp_reg(cpu
, &tmp_hprlarn_reginfo
);
9154 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
9155 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
9159 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
9160 ARMCPRegInfo mpidr_cp_reginfo
[] = {
9161 { .name
= "MPIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
9162 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
9163 .fgt
= FGT_MPIDR_EL1
,
9164 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_RAW
},
9166 #ifdef CONFIG_USER_ONLY
9167 static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo
[] = {
9168 { .name
= "MPIDR_EL1",
9169 .fixed_bits
= 0x0000000080000000 },
9171 modify_arm_cp_regs(mpidr_cp_reginfo
, mpidr_user_cp_reginfo
);
9173 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
9176 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
9177 ARMCPRegInfo auxcr_reginfo
[] = {
9178 { .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
9179 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
9180 .access
= PL1_RW
, .accessfn
= access_tacr
,
9181 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->reset_auxcr
},
9182 { .name
= "ACTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
9183 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 1,
9184 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
9186 { .name
= "ACTLR_EL3", .state
= ARM_CP_STATE_AA64
,
9187 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 1,
9188 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
9191 define_arm_cp_regs(cpu
, auxcr_reginfo
);
9192 if (cpu_isar_feature(aa32_ac2
, cpu
)) {
9193 define_arm_cp_regs(cpu
, actlr2_hactlr2_reginfo
);
9197 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
9199 * CBAR is IMPDEF, but common on Arm Cortex-A implementations.
9200 * There are two flavours:
9201 * (1) older 32-bit only cores have a simple 32-bit CBAR
9202 * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a
9203 * 32-bit register visible to AArch32 at a different encoding
9204 * to the "flavour 1" register and with the bits rearranged to
9205 * be able to squash a 64-bit address into the 32-bit view.
9206 * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but
9207 * in future if we support AArch32-only configs of some of the
9208 * AArch64 cores we might need to add a specific feature flag
9209 * to indicate cores with "flavour 2" CBAR.
9211 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
9212 /* 32 bit view is [31:18] 0...0 [43:32]. */
9213 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
9214 | extract64(cpu
->reset_cbar
, 32, 12);
9215 ARMCPRegInfo cbar_reginfo
[] = {
9217 .type
= ARM_CP_CONST
,
9218 .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 1, .opc2
= 0,
9219 .access
= PL1_R
, .resetvalue
= cbar32
},
9220 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
9221 .type
= ARM_CP_CONST
,
9222 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
9223 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
9225 /* We don't implement a r/w 64 bit CBAR currently */
9226 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
9227 define_arm_cp_regs(cpu
, cbar_reginfo
);
9229 ARMCPRegInfo cbar
= {
9231 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
9232 .access
= PL1_R
| PL3_W
, .resetvalue
= cpu
->reset_cbar
,
9233 .fieldoffset
= offsetof(CPUARMState
,
9234 cp15
.c15_config_base_address
)
9236 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
9237 cbar
.access
= PL1_R
;
9238 cbar
.fieldoffset
= 0;
9239 cbar
.type
= ARM_CP_CONST
;
9241 define_one_arm_cp_reg(cpu
, &cbar
);
9245 if (arm_feature(env
, ARM_FEATURE_VBAR
)) {
9246 static const ARMCPRegInfo vbar_cp_reginfo
[] = {
9247 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
9248 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
9249 .access
= PL1_RW
, .writefn
= vbar_write
,
9250 .fgt
= FGT_VBAR_EL1
,
9251 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.vbar_s
),
9252 offsetof(CPUARMState
, cp15
.vbar_ns
) },
9255 define_arm_cp_regs(cpu
, vbar_cp_reginfo
);
9258 /* Generic registers whose values depend on the implementation */
9260 ARMCPRegInfo sctlr
= {
9261 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
9262 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
9263 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
9264 .fgt
= FGT_SCTLR_EL1
,
9265 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.sctlr_s
),
9266 offsetof(CPUARMState
, cp15
.sctlr_ns
) },
9267 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
9268 .raw_writefn
= raw_write
,
9270 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
9272 * Normally we would always end the TB on an SCTLR write, but Linux
9273 * arch/arm/mach-pxa/sleep.S expects two instructions following
9274 * an MMU enable to execute from cache. Imitate this behaviour.
9276 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
9278 define_one_arm_cp_reg(cpu
, &sctlr
);
9280 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
9281 arm_feature(env
, ARM_FEATURE_V8
)) {
9282 ARMCPRegInfo vsctlr
= {
9283 .name
= "VSCTLR", .state
= ARM_CP_STATE_AA32
,
9284 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
9285 .access
= PL2_RW
, .resetvalue
= 0x0,
9286 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vsctlr
),
9288 define_one_arm_cp_reg(cpu
, &vsctlr
);
9292 if (cpu_isar_feature(aa64_lor
, cpu
)) {
9293 define_arm_cp_regs(cpu
, lor_reginfo
);
9295 if (cpu_isar_feature(aa64_pan
, cpu
)) {
9296 define_one_arm_cp_reg(cpu
, &pan_reginfo
);
9298 #ifndef CONFIG_USER_ONLY
9299 if (cpu_isar_feature(aa64_ats1e1
, cpu
)) {
9300 define_arm_cp_regs(cpu
, ats1e1_reginfo
);
9302 if (cpu_isar_feature(aa32_ats1e1
, cpu
)) {
9303 define_arm_cp_regs(cpu
, ats1cp_reginfo
);
9306 if (cpu_isar_feature(aa64_uao
, cpu
)) {
9307 define_one_arm_cp_reg(cpu
, &uao_reginfo
);
9310 if (cpu_isar_feature(aa64_dit
, cpu
)) {
9311 define_one_arm_cp_reg(cpu
, &dit_reginfo
);
9313 if (cpu_isar_feature(aa64_ssbs
, cpu
)) {
9314 define_one_arm_cp_reg(cpu
, &ssbs_reginfo
);
9316 if (cpu_isar_feature(any_ras
, cpu
)) {
9317 define_arm_cp_regs(cpu
, minimal_ras_reginfo
);
9320 if (cpu_isar_feature(aa64_vh
, cpu
) ||
9321 cpu_isar_feature(aa64_debugv8p2
, cpu
)) {
9322 define_one_arm_cp_reg(cpu
, &contextidr_el2
);
9324 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
9325 define_arm_cp_regs(cpu
, vhe_reginfo
);
9328 if (cpu_isar_feature(aa64_sve
, cpu
)) {
9329 define_arm_cp_regs(cpu
, zcr_reginfo
);
9332 if (cpu_isar_feature(aa64_hcx
, cpu
)) {
9333 define_one_arm_cp_reg(cpu
, &hcrx_el2_reginfo
);
9336 #ifdef TARGET_AARCH64
9337 if (cpu_isar_feature(aa64_sme
, cpu
)) {
9338 define_arm_cp_regs(cpu
, sme_reginfo
);
9340 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
9341 define_arm_cp_regs(cpu
, pauth_reginfo
);
9343 if (cpu_isar_feature(aa64_rndr
, cpu
)) {
9344 define_arm_cp_regs(cpu
, rndr_reginfo
);
9346 if (cpu_isar_feature(aa64_tlbirange
, cpu
)) {
9347 define_arm_cp_regs(cpu
, tlbirange_reginfo
);
9349 if (cpu_isar_feature(aa64_tlbios
, cpu
)) {
9350 define_arm_cp_regs(cpu
, tlbios_reginfo
);
9352 /* Data Cache clean instructions up to PoP */
9353 if (cpu_isar_feature(aa64_dcpop
, cpu
)) {
9354 define_one_arm_cp_reg(cpu
, dcpop_reg
);
9356 if (cpu_isar_feature(aa64_dcpodp
, cpu
)) {
9357 define_one_arm_cp_reg(cpu
, dcpodp_reg
);
9362 * If full MTE is enabled, add all of the system registers.
9363 * If only "instructions available at EL0" are enabled,
9364 * then define only a RAZ/WI version of PSTATE.TCO.
9366 if (cpu_isar_feature(aa64_mte
, cpu
)) {
9367 ARMCPRegInfo gmid_reginfo
= {
9368 .name
= "GMID_EL1", .state
= ARM_CP_STATE_AA64
,
9369 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 4,
9370 .access
= PL1_R
, .accessfn
= access_aa64_tid5
,
9371 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->gm_blocksize
,
9373 define_one_arm_cp_reg(cpu
, &gmid_reginfo
);
9374 define_arm_cp_regs(cpu
, mte_reginfo
);
9375 define_arm_cp_regs(cpu
, mte_el0_cacheop_reginfo
);
9376 } else if (cpu_isar_feature(aa64_mte_insn_reg
, cpu
)) {
9377 define_arm_cp_regs(cpu
, mte_tco_ro_reginfo
);
9378 define_arm_cp_regs(cpu
, mte_el0_cacheop_reginfo
);
9381 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
9382 define_arm_cp_regs(cpu
, scxtnum_reginfo
);
9385 if (cpu_isar_feature(aa64_fgt
, cpu
)) {
9386 define_arm_cp_regs(cpu
, fgt_reginfo
);
9389 if (cpu_isar_feature(aa64_rme
, cpu
)) {
9390 define_arm_cp_regs(cpu
, rme_reginfo
);
9391 if (cpu_isar_feature(aa64_mte
, cpu
)) {
9392 define_arm_cp_regs(cpu
, rme_mte_reginfo
);
9397 if (cpu_isar_feature(any_predinv
, cpu
)) {
9398 define_arm_cp_regs(cpu
, predinv_reginfo
);
9401 if (cpu_isar_feature(any_ccidx
, cpu
)) {
9402 define_arm_cp_regs(cpu
, ccsidr2_reginfo
);
9405 #ifndef CONFIG_USER_ONLY
9407 * Register redirections and aliases must be done last,
9408 * after the registers from the other extensions have been defined.
9410 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
9411 define_arm_vh_e2h_redirects_aliases(cpu
);
9416 /* Sort alphabetically by type name, except for "any". */
9417 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
9419 ObjectClass
*class_a
= (ObjectClass
*)a
;
9420 ObjectClass
*class_b
= (ObjectClass
*)b
;
9421 const char *name_a
, *name_b
;
9423 name_a
= object_class_get_name(class_a
);
9424 name_b
= object_class_get_name(class_b
);
9425 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
9427 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
9430 return strcmp(name_a
, name_b
);
9434 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
9436 ObjectClass
*oc
= data
;
9437 CPUClass
*cc
= CPU_CLASS(oc
);
9438 const char *typename
;
9441 typename
= object_class_get_name(oc
);
9442 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
9443 if (cc
->deprecation_note
) {
9444 qemu_printf(" %s (deprecated)\n", name
);
9446 qemu_printf(" %s\n", name
);
9451 void arm_cpu_list(void)
9455 list
= object_class_get_list(TYPE_ARM_CPU
, false);
9456 list
= g_slist_sort(list
, arm_cpu_list_compare
);
9457 qemu_printf("Available CPUs:\n");
9458 g_slist_foreach(list
, arm_cpu_list_entry
, NULL
);
9463 * Private utility function for define_one_arm_cp_reg_with_opaque():
9464 * add a single reginfo struct to the hash table.
9466 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
9467 void *opaque
, CPState state
,
9468 CPSecureState secstate
,
9469 int crm
, int opc1
, int opc2
,
9472 CPUARMState
*env
= &cpu
->env
;
9475 bool is64
= r
->type
& ARM_CP_64BIT
;
9476 bool ns
= secstate
& ARM_CP_SECSTATE_NS
;
9482 case ARM_CP_STATE_AA32
:
9483 /* We assume it is a cp15 register if the .cp field is left unset. */
9484 if (cp
== 0 && r
->state
== ARM_CP_STATE_BOTH
) {
9487 key
= ENCODE_CP_REG(cp
, is64
, ns
, r
->crn
, crm
, opc1
, opc2
);
9489 case ARM_CP_STATE_AA64
:
9491 * To allow abbreviation of ARMCPRegInfo definitions, we treat
9492 * cp == 0 as equivalent to the value for "standard guest-visible
9493 * sysreg". STATE_BOTH definitions are also always "standard sysreg"
9494 * in their AArch64 view (the .cp value may be non-zero for the
9495 * benefit of the AArch32 view).
9497 if (cp
== 0 || r
->state
== ARM_CP_STATE_BOTH
) {
9498 cp
= CP_REG_ARM64_SYSREG_CP
;
9500 key
= ENCODE_AA64_CP_REG(cp
, r
->crn
, crm
, r
->opc0
, opc1
, opc2
);
9503 g_assert_not_reached();
9506 /* Overriding of an existing definition must be explicitly requested. */
9507 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
9508 const ARMCPRegInfo
*oldreg
= get_arm_cp_reginfo(cpu
->cp_regs
, key
);
9510 assert(oldreg
->type
& ARM_CP_OVERRIDE
);
9515 * Eliminate registers that are not present because the EL is missing.
9516 * Doing this here makes it easier to put all registers for a given
9517 * feature into the same ARMCPRegInfo array and define them all at once.
9520 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
9522 * An EL2 register without EL2 but with EL3 is (usually) RES0.
9523 * See rule RJFFP in section D1.1.3 of DDI0487H.a.
9525 int min_el
= ctz32(r
->access
) / 2;
9526 if (min_el
== 2 && !arm_feature(env
, ARM_FEATURE_EL2
)) {
9527 if (r
->type
& ARM_CP_EL3_NO_EL2_UNDEF
) {
9530 make_const
= !(r
->type
& ARM_CP_EL3_NO_EL2_KEEP
);
9533 CPAccessRights max_el
= (arm_feature(env
, ARM_FEATURE_EL2
)
9535 if ((r
->access
& max_el
) == 0) {
9540 /* Combine cpreg and name into one allocation. */
9541 name_len
= strlen(name
) + 1;
9542 r2
= g_malloc(sizeof(*r2
) + name_len
);
9544 r2
->name
= memcpy(r2
+ 1, name
, name_len
);
9547 * Update fields to match the instantiation, overwiting wildcards
9548 * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH.
9555 r2
->secure
= secstate
;
9557 r2
->opaque
= opaque
;
9561 /* This should not have been a very special register to begin. */
9562 int old_special
= r2
->type
& ARM_CP_SPECIAL_MASK
;
9563 assert(old_special
== 0 || old_special
== ARM_CP_NOP
);
9565 * Set the special function to CONST, retaining the other flags.
9566 * This is important for e.g. ARM_CP_SVE so that we still
9567 * take the SVE trap if CPTR_EL3.EZ == 0.
9569 r2
->type
= (r2
->type
& ~ARM_CP_SPECIAL_MASK
) | ARM_CP_CONST
;
9571 * Usually, these registers become RES0, but there are a few
9572 * special cases like VPIDR_EL2 which have a constant non-zero
9573 * value with writes ignored.
9575 if (!(r
->type
& ARM_CP_EL3_NO_EL2_C_NZ
)) {
9579 * ARM_CP_CONST has precedence, so removing the callbacks and
9580 * offsets are not strictly necessary, but it is potentially
9581 * less confusing to debug later.
9585 r2
->raw_readfn
= NULL
;
9586 r2
->raw_writefn
= NULL
;
9588 r2
->fieldoffset
= 0;
9589 r2
->bank_fieldoffsets
[0] = 0;
9590 r2
->bank_fieldoffsets
[1] = 0;
9592 bool isbanked
= r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1];
9596 * Register is banked (using both entries in array).
9597 * Overwriting fieldoffset as the array is only used to define
9598 * banked registers but later only fieldoffset is used.
9600 r2
->fieldoffset
= r
->bank_fieldoffsets
[ns
];
9602 if (state
== ARM_CP_STATE_AA32
) {
9605 * If the register is banked then we don't need to migrate or
9606 * reset the 32-bit instance in certain cases:
9608 * 1) If the register has both 32-bit and 64-bit instances
9609 * then we can count on the 64-bit instance taking care
9610 * of the non-secure bank.
9611 * 2) If ARMv8 is enabled then we can count on a 64-bit
9612 * version taking care of the secure bank. This requires
9613 * that separate 32 and 64-bit definitions are provided.
9615 if ((r
->state
== ARM_CP_STATE_BOTH
&& ns
) ||
9616 (arm_feature(env
, ARM_FEATURE_V8
) && !ns
)) {
9617 r2
->type
|= ARM_CP_ALIAS
;
9619 } else if ((secstate
!= r
->secure
) && !ns
) {
9621 * The register is not banked so we only want to allow
9622 * migration of the non-secure instance.
9624 r2
->type
|= ARM_CP_ALIAS
;
9627 if (HOST_BIG_ENDIAN
&&
9628 r
->state
== ARM_CP_STATE_BOTH
&& r2
->fieldoffset
) {
9629 r2
->fieldoffset
+= sizeof(uint32_t);
9635 * By convention, for wildcarded registers only the first
9636 * entry is used for migration; the others are marked as
9637 * ALIAS so we don't try to transfer the register
9638 * multiple times. Special registers (ie NOP/WFI) are
9639 * never migratable and not even raw-accessible.
9641 if (r2
->type
& ARM_CP_SPECIAL_MASK
) {
9642 r2
->type
|= ARM_CP_NO_RAW
;
9644 if (((r
->crm
== CP_ANY
) && crm
!= 0) ||
9645 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
9646 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
9647 r2
->type
|= ARM_CP_ALIAS
| ARM_CP_NO_GDB
;
9651 * Check that raw accesses are either forbidden or handled. Note that
9652 * we can't assert this earlier because the setup of fieldoffset for
9653 * banked registers has to be done first.
9655 if (!(r2
->type
& ARM_CP_NO_RAW
)) {
9656 assert(!raw_accessors_invalid(r2
));
9659 g_hash_table_insert(cpu
->cp_regs
, (gpointer
)(uintptr_t)key
, r2
);
9663 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
9664 const ARMCPRegInfo
*r
, void *opaque
)
9667 * Define implementations of coprocessor registers.
9668 * We store these in a hashtable because typically
9669 * there are less than 150 registers in a space which
9670 * is 16*16*16*8*8 = 262144 in size.
9671 * Wildcarding is supported for the crm, opc1 and opc2 fields.
9672 * If a register is defined twice then the second definition is
9673 * used, so this can be used to define some generic registers and
9674 * then override them with implementation specific variations.
9675 * At least one of the original and the second definition should
9676 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
9677 * against accidental use.
9679 * The state field defines whether the register is to be
9680 * visible in the AArch32 or AArch64 execution state. If the
9681 * state is set to ARM_CP_STATE_BOTH then we synthesise a
9682 * reginfo structure for the AArch32 view, which sees the lower
9683 * 32 bits of the 64 bit register.
9685 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
9686 * be wildcarded. AArch64 registers are always considered to be 64
9687 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
9688 * the register, if any.
9690 int crm
, opc1
, opc2
;
9691 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
9692 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
9693 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
9694 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
9695 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
9696 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
9699 /* 64 bit registers have only CRm and Opc1 fields */
9700 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
9701 /* op0 only exists in the AArch64 encodings */
9702 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
9703 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
9704 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
9706 * This API is only for Arm's system coprocessors (14 and 15) or
9707 * (M-profile or v7A-and-earlier only) for implementation defined
9708 * coprocessors in the range 0..7. Our decode assumes this, since
9709 * 8..13 can be used for other insns including VFP and Neon. See
9710 * valid_cp() in translate.c. Assert here that we haven't tried
9711 * to use an invalid coprocessor number.
9714 case ARM_CP_STATE_BOTH
:
9715 /* 0 has a special meaning, but otherwise the same rules as AA32. */
9720 case ARM_CP_STATE_AA32
:
9721 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) &&
9722 !arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
9723 assert(r
->cp
>= 14 && r
->cp
<= 15);
9725 assert(r
->cp
< 8 || (r
->cp
>= 14 && r
->cp
<= 15));
9728 case ARM_CP_STATE_AA64
:
9729 assert(r
->cp
== 0 || r
->cp
== CP_REG_ARM64_SYSREG_CP
);
9732 g_assert_not_reached();
9735 * The AArch64 pseudocode CheckSystemAccess() specifies that op1
9736 * encodes a minimum access level for the register. We roll this
9737 * runtime check into our general permission check code, so check
9738 * here that the reginfo's specified permissions are strict enough
9739 * to encompass the generic architectural permission check.
9741 if (r
->state
!= ARM_CP_STATE_AA32
) {
9742 CPAccessRights mask
;
9745 /* min_EL EL1, but some accessible to EL0 via kernel ABI */
9746 mask
= PL0U_R
| PL1_RW
;
9766 /* min_EL EL1, secure mode only (we don't check the latter) */
9770 /* broken reginfo with out-of-range opc1 */
9771 g_assert_not_reached();
9773 /* assert our permissions are not too lax (stricter is fine) */
9774 assert((r
->access
& ~mask
) == 0);
9778 * Check that the register definition has enough info to handle
9779 * reads and writes if they are permitted.
9781 if (!(r
->type
& (ARM_CP_SPECIAL_MASK
| ARM_CP_CONST
))) {
9782 if (r
->access
& PL3_R
) {
9783 assert((r
->fieldoffset
||
9784 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
9787 if (r
->access
& PL3_W
) {
9788 assert((r
->fieldoffset
||
9789 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
9794 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
9795 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
9796 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
9797 for (state
= ARM_CP_STATE_AA32
;
9798 state
<= ARM_CP_STATE_AA64
; state
++) {
9799 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
9802 if (state
== ARM_CP_STATE_AA32
) {
9804 * Under AArch32 CP registers can be common
9805 * (same for secure and non-secure world) or banked.
9809 switch (r
->secure
) {
9810 case ARM_CP_SECSTATE_S
:
9811 case ARM_CP_SECSTATE_NS
:
9812 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
9813 r
->secure
, crm
, opc1
, opc2
,
9816 case ARM_CP_SECSTATE_BOTH
:
9817 name
= g_strdup_printf("%s_S", r
->name
);
9818 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
9820 crm
, opc1
, opc2
, name
);
9822 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
9824 crm
, opc1
, opc2
, r
->name
);
9827 g_assert_not_reached();
9831 * AArch64 registers get mapped to non-secure instance
9834 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
9836 crm
, opc1
, opc2
, r
->name
);
9844 /* Define a whole list of registers */
9845 void define_arm_cp_regs_with_opaque_len(ARMCPU
*cpu
, const ARMCPRegInfo
*regs
,
9846 void *opaque
, size_t len
)
9849 for (i
= 0; i
< len
; ++i
) {
9850 define_one_arm_cp_reg_with_opaque(cpu
, regs
+ i
, opaque
);
9855 * Modify ARMCPRegInfo for access from userspace.
9857 * This is a data driven modification directed by
9858 * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as
9859 * user-space cannot alter any values and dynamic values pertaining to
9860 * execution state are hidden from user space view anyway.
9862 void modify_arm_cp_regs_with_len(ARMCPRegInfo
*regs
, size_t regs_len
,
9863 const ARMCPRegUserSpaceInfo
*mods
,
9866 for (size_t mi
= 0; mi
< mods_len
; ++mi
) {
9867 const ARMCPRegUserSpaceInfo
*m
= mods
+ mi
;
9868 GPatternSpec
*pat
= NULL
;
9871 pat
= g_pattern_spec_new(m
->name
);
9873 for (size_t ri
= 0; ri
< regs_len
; ++ri
) {
9874 ARMCPRegInfo
*r
= regs
+ ri
;
9876 if (pat
&& g_pattern_match_string(pat
, r
->name
)) {
9877 r
->type
= ARM_CP_CONST
;
9881 } else if (strcmp(r
->name
, m
->name
) == 0) {
9882 r
->type
= ARM_CP_CONST
;
9884 r
->resetvalue
&= m
->exported_bits
;
9885 r
->resetvalue
|= m
->fixed_bits
;
9890 g_pattern_spec_free(pat
);
9895 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
9897 return g_hash_table_lookup(cpregs
, (gpointer
)(uintptr_t)encoded_cp
);
9900 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
9903 /* Helper coprocessor write function for write-ignore registers */
9906 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
9908 /* Helper coprocessor write function for read-as-zero registers */
9912 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
9914 /* Helper coprocessor reset function for do-nothing-on-reset registers */
9917 static int bad_mode_switch(CPUARMState
*env
, int mode
, CPSRWriteType write_type
)
9920 * Return true if it is not valid for us to switch to
9921 * this CPU mode (ie all the UNPREDICTABLE cases in
9922 * the ARM ARM CPSRWriteByInstr pseudocode).
9925 /* Changes to or from Hyp via MSR and CPS are illegal. */
9926 if (write_type
== CPSRWriteByInstr
&&
9927 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_HYP
||
9928 mode
== ARM_CPU_MODE_HYP
)) {
9933 case ARM_CPU_MODE_USR
:
9935 case ARM_CPU_MODE_SYS
:
9936 case ARM_CPU_MODE_SVC
:
9937 case ARM_CPU_MODE_ABT
:
9938 case ARM_CPU_MODE_UND
:
9939 case ARM_CPU_MODE_IRQ
:
9940 case ARM_CPU_MODE_FIQ
:
9942 * Note that we don't implement the IMPDEF NSACR.RFR which in v7
9943 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
9946 * If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
9947 * and CPS are treated as illegal mode changes.
9949 if (write_type
== CPSRWriteByInstr
&&
9950 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
&&
9951 (arm_hcr_el2_eff(env
) & HCR_TGE
)) {
9955 case ARM_CPU_MODE_HYP
:
9956 return !arm_is_el2_enabled(env
) || arm_current_el(env
) < 2;
9957 case ARM_CPU_MODE_MON
:
9958 return arm_current_el(env
) < 3;
9964 uint32_t cpsr_read(CPUARMState
*env
)
9967 ZF
= (env
->ZF
== 0);
9968 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
9969 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
9970 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
9971 | ((env
->condexec_bits
& 0xfc) << 8)
9972 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
9975 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
,
9976 CPSRWriteType write_type
)
9978 uint32_t changed_daif
;
9979 bool rebuild_hflags
= (write_type
!= CPSRWriteRaw
) &&
9980 (mask
& (CPSR_M
| CPSR_E
| CPSR_IL
));
9982 if (mask
& CPSR_NZCV
) {
9983 env
->ZF
= (~val
) & CPSR_Z
;
9985 env
->CF
= (val
>> 29) & 1;
9986 env
->VF
= (val
<< 3) & 0x80000000;
9988 if (mask
& CPSR_Q
) {
9989 env
->QF
= ((val
& CPSR_Q
) != 0);
9991 if (mask
& CPSR_T
) {
9992 env
->thumb
= ((val
& CPSR_T
) != 0);
9994 if (mask
& CPSR_IT_0_1
) {
9995 env
->condexec_bits
&= ~3;
9996 env
->condexec_bits
|= (val
>> 25) & 3;
9998 if (mask
& CPSR_IT_2_7
) {
9999 env
->condexec_bits
&= 3;
10000 env
->condexec_bits
|= (val
>> 8) & 0xfc;
10002 if (mask
& CPSR_GE
) {
10003 env
->GE
= (val
>> 16) & 0xf;
10007 * In a V7 implementation that includes the security extensions but does
10008 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
10009 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
10010 * bits respectively.
10012 * In a V8 implementation, it is permitted for privileged software to
10013 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
10015 if (write_type
!= CPSRWriteRaw
&& !arm_feature(env
, ARM_FEATURE_V8
) &&
10016 arm_feature(env
, ARM_FEATURE_EL3
) &&
10017 !arm_feature(env
, ARM_FEATURE_EL2
) &&
10018 !arm_is_secure(env
)) {
10020 changed_daif
= (env
->daif
^ val
) & mask
;
10022 if (changed_daif
& CPSR_A
) {
10024 * Check to see if we are allowed to change the masking of async
10025 * abort exceptions from a non-secure state.
10027 if (!(env
->cp15
.scr_el3
& SCR_AW
)) {
10028 qemu_log_mask(LOG_GUEST_ERROR
,
10029 "Ignoring attempt to switch CPSR_A flag from "
10030 "non-secure world with SCR.AW bit clear\n");
10035 if (changed_daif
& CPSR_F
) {
10037 * Check to see if we are allowed to change the masking of FIQ
10038 * exceptions from a non-secure state.
10040 if (!(env
->cp15
.scr_el3
& SCR_FW
)) {
10041 qemu_log_mask(LOG_GUEST_ERROR
,
10042 "Ignoring attempt to switch CPSR_F flag from "
10043 "non-secure world with SCR.FW bit clear\n");
10048 * Check whether non-maskable FIQ (NMFI) support is enabled.
10049 * If this bit is set software is not allowed to mask
10050 * FIQs, but is allowed to set CPSR_F to 0.
10052 if ((A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_NMFI
) &&
10054 qemu_log_mask(LOG_GUEST_ERROR
,
10055 "Ignoring attempt to enable CPSR_F flag "
10056 "(non-maskable FIQ [NMFI] support enabled)\n");
10062 env
->daif
&= ~(CPSR_AIF
& mask
);
10063 env
->daif
|= val
& CPSR_AIF
& mask
;
10065 if (write_type
!= CPSRWriteRaw
&&
10066 ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
)) {
10067 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
) {
10069 * Note that we can only get here in USR mode if this is a
10070 * gdb stub write; for this case we follow the architectural
10071 * behaviour for guest writes in USR mode of ignoring an attempt
10072 * to switch mode. (Those are caught by translate.c for writes
10073 * triggered by guest instructions.)
10076 } else if (bad_mode_switch(env
, val
& CPSR_M
, write_type
)) {
10078 * Attempt to switch to an invalid mode: this is UNPREDICTABLE in
10079 * v7, and has defined behaviour in v8:
10080 * + leave CPSR.M untouched
10081 * + allow changes to the other CPSR fields
10083 * For user changes via the GDB stub, we don't set PSTATE.IL,
10084 * as this would be unnecessarily harsh for a user error.
10087 if (write_type
!= CPSRWriteByGDBStub
&&
10088 arm_feature(env
, ARM_FEATURE_V8
)) {
10092 qemu_log_mask(LOG_GUEST_ERROR
,
10093 "Illegal AArch32 mode switch attempt from %s to %s\n",
10094 aarch32_mode_name(env
->uncached_cpsr
),
10095 aarch32_mode_name(val
));
10097 qemu_log_mask(CPU_LOG_INT
, "%s %s to %s PC 0x%" PRIx32
"\n",
10098 write_type
== CPSRWriteExceptionReturn
?
10099 "Exception return from AArch32" :
10100 "AArch32 mode switch from",
10101 aarch32_mode_name(env
->uncached_cpsr
),
10102 aarch32_mode_name(val
), env
->regs
[15]);
10103 switch_mode(env
, val
& CPSR_M
);
10106 mask
&= ~CACHED_CPSR_BITS
;
10107 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
10108 if (tcg_enabled() && rebuild_hflags
) {
10109 arm_rebuild_hflags(env
);
10113 /* Sign/zero extend */
10114 uint32_t HELPER(sxtb16
)(uint32_t x
)
10117 res
= (uint16_t)(int8_t)x
;
10118 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
10122 static void handle_possible_div0_trap(CPUARMState
*env
, uintptr_t ra
)
10125 * Take a division-by-zero exception if necessary; otherwise return
10126 * to get the usual non-trapping division behaviour (result of 0)
10128 if (arm_feature(env
, ARM_FEATURE_M
)
10129 && (env
->v7m
.ccr
[env
->v7m
.secure
] & R_V7M_CCR_DIV_0_TRP_MASK
)) {
10130 raise_exception_ra(env
, EXCP_DIVBYZERO
, 0, 1, ra
);
10134 uint32_t HELPER(uxtb16
)(uint32_t x
)
10137 res
= (uint16_t)(uint8_t)x
;
10138 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
10142 int32_t HELPER(sdiv
)(CPUARMState
*env
, int32_t num
, int32_t den
)
10145 handle_possible_div0_trap(env
, GETPC());
10148 if (num
== INT_MIN
&& den
== -1) {
10154 uint32_t HELPER(udiv
)(CPUARMState
*env
, uint32_t num
, uint32_t den
)
10157 handle_possible_div0_trap(env
, GETPC());
10163 uint32_t HELPER(rbit
)(uint32_t x
)
10165 return revbit32(x
);
10168 #ifdef CONFIG_USER_ONLY
10170 static void switch_mode(CPUARMState
*env
, int mode
)
10172 ARMCPU
*cpu
= env_archcpu(env
);
10174 if (mode
!= ARM_CPU_MODE_USR
) {
10175 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
10179 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
10180 uint32_t cur_el
, bool secure
)
10185 void aarch64_sync_64_to_32(CPUARMState
*env
)
10187 g_assert_not_reached();
10192 static void switch_mode(CPUARMState
*env
, int mode
)
10197 old_mode
= env
->uncached_cpsr
& CPSR_M
;
10198 if (mode
== old_mode
) {
10202 if (old_mode
== ARM_CPU_MODE_FIQ
) {
10203 memcpy(env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
10204 memcpy(env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
10205 } else if (mode
== ARM_CPU_MODE_FIQ
) {
10206 memcpy(env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
10207 memcpy(env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
10210 i
= bank_number(old_mode
);
10211 env
->banked_r13
[i
] = env
->regs
[13];
10212 env
->banked_spsr
[i
] = env
->spsr
;
10214 i
= bank_number(mode
);
10215 env
->regs
[13] = env
->banked_r13
[i
];
10216 env
->spsr
= env
->banked_spsr
[i
];
10218 env
->banked_r14
[r14_bank_number(old_mode
)] = env
->regs
[14];
10219 env
->regs
[14] = env
->banked_r14
[r14_bank_number(mode
)];
10223 * Physical Interrupt Target EL Lookup Table
10225 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
10227 * The below multi-dimensional table is used for looking up the target
10228 * exception level given numerous condition criteria. Specifically, the
10229 * target EL is based on SCR and HCR routing controls as well as the
10230 * currently executing EL and secure state.
10233 * target_el_table[2][2][2][2][2][4]
10234 * | | | | | +--- Current EL
10235 * | | | | +------ Non-secure(0)/Secure(1)
10236 * | | | +--------- HCR mask override
10237 * | | +------------ SCR exec state control
10238 * | +--------------- SCR mask override
10239 * +------------------ 32-bit(0)/64-bit(1) EL3
10241 * The table values are as such:
10243 * -1 = Cannot occur
10245 * The ARM ARM target EL table includes entries indicating that an "exception
10246 * is not taken". The two cases where this is applicable are:
10247 * 1) An exception is taken from EL3 but the SCR does not have the exception
10249 * 2) An exception is taken from EL2 but the HCR does not have the exception
10251 * In these two cases, the below table contain a target of EL1. This value is
10252 * returned as it is expected that the consumer of the table data will check
10253 * for "target EL >= current EL" to ensure the exception is not taken.
10257 * BIT IRQ IMO Non-secure Secure
10258 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
10260 static const int8_t target_el_table
[2][2][2][2][2][4] = {
10261 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
10262 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
10263 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
10264 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
10265 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
10266 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
10267 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
10268 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
10269 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
10270 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 2, 2, -1, 1 },},},
10271 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, 1, 1 },},
10272 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 2, 2, 2, 1 },},},},
10273 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
10274 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
10275 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},
10276 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},},},},
10280 * Determine the target EL for physical exceptions
10282 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
10283 uint32_t cur_el
, bool secure
)
10285 CPUARMState
*env
= cpu_env(cs
);
10290 /* Is the highest EL AArch64? */
10291 bool is64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
10294 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
10295 rw
= ((env
->cp15
.scr_el3
& SCR_RW
) == SCR_RW
);
10298 * Either EL2 is the highest EL (and so the EL2 register width
10299 * is given by is64); or there is no EL2 or EL3, in which case
10300 * the value of 'rw' does not affect the table lookup anyway.
10305 hcr_el2
= arm_hcr_el2_eff(env
);
10306 switch (excp_idx
) {
10308 scr
= ((env
->cp15
.scr_el3
& SCR_IRQ
) == SCR_IRQ
);
10309 hcr
= hcr_el2
& HCR_IMO
;
10312 scr
= ((env
->cp15
.scr_el3
& SCR_FIQ
) == SCR_FIQ
);
10313 hcr
= hcr_el2
& HCR_FMO
;
10316 scr
= ((env
->cp15
.scr_el3
& SCR_EA
) == SCR_EA
);
10317 hcr
= hcr_el2
& HCR_AMO
;
10322 * For these purposes, TGE and AMO/IMO/FMO both force the
10323 * interrupt to EL2. Fold TGE into the bit extracted above.
10325 hcr
|= (hcr_el2
& HCR_TGE
) != 0;
10327 /* Perform a table-lookup for the target EL given the current state */
10328 target_el
= target_el_table
[is64
][scr
][rw
][hcr
][secure
][cur_el
];
10330 assert(target_el
> 0);
10335 void arm_log_exception(CPUState
*cs
)
10337 int idx
= cs
->exception_index
;
10339 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
10340 const char *exc
= NULL
;
10341 static const char * const excnames
[] = {
10342 [EXCP_UDEF
] = "Undefined Instruction",
10343 [EXCP_SWI
] = "SVC",
10344 [EXCP_PREFETCH_ABORT
] = "Prefetch Abort",
10345 [EXCP_DATA_ABORT
] = "Data Abort",
10346 [EXCP_IRQ
] = "IRQ",
10347 [EXCP_FIQ
] = "FIQ",
10348 [EXCP_BKPT
] = "Breakpoint",
10349 [EXCP_EXCEPTION_EXIT
] = "QEMU v7M exception exit",
10350 [EXCP_KERNEL_TRAP
] = "QEMU intercept of kernel commpage",
10351 [EXCP_HVC
] = "Hypervisor Call",
10352 [EXCP_HYP_TRAP
] = "Hypervisor Trap",
10353 [EXCP_SMC
] = "Secure Monitor Call",
10354 [EXCP_VIRQ
] = "Virtual IRQ",
10355 [EXCP_VFIQ
] = "Virtual FIQ",
10356 [EXCP_SEMIHOST
] = "Semihosting call",
10357 [EXCP_NOCP
] = "v7M NOCP UsageFault",
10358 [EXCP_INVSTATE
] = "v7M INVSTATE UsageFault",
10359 [EXCP_STKOF
] = "v8M STKOF UsageFault",
10360 [EXCP_LAZYFP
] = "v7M exception during lazy FP stacking",
10361 [EXCP_LSERR
] = "v8M LSERR UsageFault",
10362 [EXCP_UNALIGNED
] = "v7M UNALIGNED UsageFault",
10363 [EXCP_DIVBYZERO
] = "v7M DIVBYZERO UsageFault",
10364 [EXCP_VSERR
] = "Virtual SERR",
10365 [EXCP_GPC
] = "Granule Protection Check",
10368 if (idx
>= 0 && idx
< ARRAY_SIZE(excnames
)) {
10369 exc
= excnames
[idx
];
10374 qemu_log_mask(CPU_LOG_INT
, "Taking exception %d [%s] on CPU %d\n",
10375 idx
, exc
, cs
->cpu_index
);
10380 * Function used to synchronize QEMU's AArch64 register set with AArch32
10381 * register set. This is necessary when switching between AArch32 and AArch64
10384 void aarch64_sync_32_to_64(CPUARMState
*env
)
10387 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
10389 /* We can blanket copy R[0:7] to X[0:7] */
10390 for (i
= 0; i
< 8; i
++) {
10391 env
->xregs
[i
] = env
->regs
[i
];
10395 * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
10396 * Otherwise, they come from the banked user regs.
10398 if (mode
== ARM_CPU_MODE_FIQ
) {
10399 for (i
= 8; i
< 13; i
++) {
10400 env
->xregs
[i
] = env
->usr_regs
[i
- 8];
10403 for (i
= 8; i
< 13; i
++) {
10404 env
->xregs
[i
] = env
->regs
[i
];
10409 * Registers x13-x23 are the various mode SP and FP registers. Registers
10410 * r13 and r14 are only copied if we are in that mode, otherwise we copy
10411 * from the mode banked register.
10413 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
10414 env
->xregs
[13] = env
->regs
[13];
10415 env
->xregs
[14] = env
->regs
[14];
10417 env
->xregs
[13] = env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)];
10418 /* HYP is an exception in that it is copied from r14 */
10419 if (mode
== ARM_CPU_MODE_HYP
) {
10420 env
->xregs
[14] = env
->regs
[14];
10422 env
->xregs
[14] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)];
10426 if (mode
== ARM_CPU_MODE_HYP
) {
10427 env
->xregs
[15] = env
->regs
[13];
10429 env
->xregs
[15] = env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)];
10432 if (mode
== ARM_CPU_MODE_IRQ
) {
10433 env
->xregs
[16] = env
->regs
[14];
10434 env
->xregs
[17] = env
->regs
[13];
10436 env
->xregs
[16] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)];
10437 env
->xregs
[17] = env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)];
10440 if (mode
== ARM_CPU_MODE_SVC
) {
10441 env
->xregs
[18] = env
->regs
[14];
10442 env
->xregs
[19] = env
->regs
[13];
10444 env
->xregs
[18] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)];
10445 env
->xregs
[19] = env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)];
10448 if (mode
== ARM_CPU_MODE_ABT
) {
10449 env
->xregs
[20] = env
->regs
[14];
10450 env
->xregs
[21] = env
->regs
[13];
10452 env
->xregs
[20] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)];
10453 env
->xregs
[21] = env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)];
10456 if (mode
== ARM_CPU_MODE_UND
) {
10457 env
->xregs
[22] = env
->regs
[14];
10458 env
->xregs
[23] = env
->regs
[13];
10460 env
->xregs
[22] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)];
10461 env
->xregs
[23] = env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)];
10465 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
10466 * mode, then we can copy from r8-r14. Otherwise, we copy from the
10467 * FIQ bank for r8-r14.
10469 if (mode
== ARM_CPU_MODE_FIQ
) {
10470 for (i
= 24; i
< 31; i
++) {
10471 env
->xregs
[i
] = env
->regs
[i
- 16]; /* X[24:30] <- R[8:14] */
10474 for (i
= 24; i
< 29; i
++) {
10475 env
->xregs
[i
] = env
->fiq_regs
[i
- 24];
10477 env
->xregs
[29] = env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)];
10478 env
->xregs
[30] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)];
10481 env
->pc
= env
->regs
[15];
10485 * Function used to synchronize QEMU's AArch32 register set with AArch64
10486 * register set. This is necessary when switching between AArch32 and AArch64
10489 void aarch64_sync_64_to_32(CPUARMState
*env
)
10492 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
10494 /* We can blanket copy X[0:7] to R[0:7] */
10495 for (i
= 0; i
< 8; i
++) {
10496 env
->regs
[i
] = env
->xregs
[i
];
10500 * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
10501 * Otherwise, we copy x8-x12 into the banked user regs.
10503 if (mode
== ARM_CPU_MODE_FIQ
) {
10504 for (i
= 8; i
< 13; i
++) {
10505 env
->usr_regs
[i
- 8] = env
->xregs
[i
];
10508 for (i
= 8; i
< 13; i
++) {
10509 env
->regs
[i
] = env
->xregs
[i
];
10514 * Registers r13 & r14 depend on the current mode.
10515 * If we are in a given mode, we copy the corresponding x registers to r13
10516 * and r14. Otherwise, we copy the x register to the banked r13 and r14
10519 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
10520 env
->regs
[13] = env
->xregs
[13];
10521 env
->regs
[14] = env
->xregs
[14];
10523 env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[13];
10526 * HYP is an exception in that it does not have its own banked r14 but
10527 * shares the USR r14
10529 if (mode
== ARM_CPU_MODE_HYP
) {
10530 env
->regs
[14] = env
->xregs
[14];
10532 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[14];
10536 if (mode
== ARM_CPU_MODE_HYP
) {
10537 env
->regs
[13] = env
->xregs
[15];
10539 env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)] = env
->xregs
[15];
10542 if (mode
== ARM_CPU_MODE_IRQ
) {
10543 env
->regs
[14] = env
->xregs
[16];
10544 env
->regs
[13] = env
->xregs
[17];
10546 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[16];
10547 env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[17];
10550 if (mode
== ARM_CPU_MODE_SVC
) {
10551 env
->regs
[14] = env
->xregs
[18];
10552 env
->regs
[13] = env
->xregs
[19];
10554 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[18];
10555 env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[19];
10558 if (mode
== ARM_CPU_MODE_ABT
) {
10559 env
->regs
[14] = env
->xregs
[20];
10560 env
->regs
[13] = env
->xregs
[21];
10562 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[20];
10563 env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[21];
10566 if (mode
== ARM_CPU_MODE_UND
) {
10567 env
->regs
[14] = env
->xregs
[22];
10568 env
->regs
[13] = env
->xregs
[23];
10570 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[22];
10571 env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[23];
10575 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
10576 * mode, then we can copy to r8-r14. Otherwise, we copy to the
10577 * FIQ bank for r8-r14.
10579 if (mode
== ARM_CPU_MODE_FIQ
) {
10580 for (i
= 24; i
< 31; i
++) {
10581 env
->regs
[i
- 16] = env
->xregs
[i
]; /* X[24:30] -> R[8:14] */
10584 for (i
= 24; i
< 29; i
++) {
10585 env
->fiq_regs
[i
- 24] = env
->xregs
[i
];
10587 env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[29];
10588 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[30];
10591 env
->regs
[15] = env
->pc
;
10594 static void take_aarch32_exception(CPUARMState
*env
, int new_mode
,
10595 uint32_t mask
, uint32_t offset
,
10600 /* Change the CPU state so as to actually take the exception. */
10601 switch_mode(env
, new_mode
);
10604 * For exceptions taken to AArch32 we must clear the SS bit in both
10605 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
10607 env
->pstate
&= ~PSTATE_SS
;
10608 env
->spsr
= cpsr_read(env
);
10609 /* Clear IT bits. */
10610 env
->condexec_bits
= 0;
10611 /* Switch to the new mode, and to the correct instruction set. */
10612 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
10614 /* This must be after mode switching. */
10615 new_el
= arm_current_el(env
);
10617 /* Set new mode endianness */
10618 env
->uncached_cpsr
&= ~CPSR_E
;
10619 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_EE
) {
10620 env
->uncached_cpsr
|= CPSR_E
;
10622 /* J and IL must always be cleared for exception entry */
10623 env
->uncached_cpsr
&= ~(CPSR_IL
| CPSR_J
);
10626 if (cpu_isar_feature(aa32_ssbs
, env_archcpu(env
))) {
10627 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_DSSBS_32
) {
10628 env
->uncached_cpsr
|= CPSR_SSBS
;
10630 env
->uncached_cpsr
&= ~CPSR_SSBS
;
10634 if (new_mode
== ARM_CPU_MODE_HYP
) {
10635 env
->thumb
= (env
->cp15
.sctlr_el
[2] & SCTLR_TE
) != 0;
10636 env
->elr_el
[2] = env
->regs
[15];
10638 /* CPSR.PAN is normally preserved preserved unless... */
10639 if (cpu_isar_feature(aa32_pan
, env_archcpu(env
))) {
10642 if (!arm_is_secure_below_el3(env
)) {
10643 /* ... the target is EL3, from non-secure state. */
10644 env
->uncached_cpsr
&= ~CPSR_PAN
;
10647 /* ... the target is EL3, from secure state ... */
10650 /* ... the target is EL1 and SCTLR.SPAN is 0. */
10651 if (!(env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
)) {
10652 env
->uncached_cpsr
|= CPSR_PAN
;
10658 * this is a lie, as there was no c1_sys on V4T/V5, but who cares
10659 * and we should just guard the thumb mode on V4
10661 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
10663 (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_TE
) != 0;
10665 env
->regs
[14] = env
->regs
[15] + offset
;
10667 env
->regs
[15] = newpc
;
10669 if (tcg_enabled()) {
10670 arm_rebuild_hflags(env
);
10674 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState
*cs
)
10677 * Handle exception entry to Hyp mode; this is sufficiently
10678 * different to entry to other AArch32 modes that we handle it
10681 * The vector table entry used is always the 0x14 Hyp mode entry point,
10682 * unless this is an UNDEF/SVC/HVC/abort taken from Hyp to Hyp.
10683 * The offset applied to the preferred return address is always zero
10684 * (see DDI0487C.a section G1.12.3).
10685 * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values.
10687 uint32_t addr
, mask
;
10688 ARMCPU
*cpu
= ARM_CPU(cs
);
10689 CPUARMState
*env
= &cpu
->env
;
10691 switch (cs
->exception_index
) {
10699 /* Fall through to prefetch abort. */
10700 case EXCP_PREFETCH_ABORT
:
10701 env
->cp15
.ifar_s
= env
->exception
.vaddress
;
10702 qemu_log_mask(CPU_LOG_INT
, "...with HIFAR 0x%x\n",
10703 (uint32_t)env
->exception
.vaddress
);
10706 case EXCP_DATA_ABORT
:
10707 env
->cp15
.dfar_s
= env
->exception
.vaddress
;
10708 qemu_log_mask(CPU_LOG_INT
, "...with HDFAR 0x%x\n",
10709 (uint32_t)env
->exception
.vaddress
);
10721 case EXCP_HYP_TRAP
:
10725 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
10728 if (cs
->exception_index
!= EXCP_IRQ
&& cs
->exception_index
!= EXCP_FIQ
) {
10729 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
10731 * QEMU syndrome values are v8-style. v7 has the IL bit
10732 * UNK/SBZP for "field not valid" cases, where v8 uses RES1.
10733 * If this is a v7 CPU, squash the IL bit in those cases.
10735 if (cs
->exception_index
== EXCP_PREFETCH_ABORT
||
10736 (cs
->exception_index
== EXCP_DATA_ABORT
&&
10737 !(env
->exception
.syndrome
& ARM_EL_ISV
)) ||
10738 syn_get_ec(env
->exception
.syndrome
) == EC_UNCATEGORIZED
) {
10739 env
->exception
.syndrome
&= ~ARM_EL_IL
;
10742 env
->cp15
.esr_el
[2] = env
->exception
.syndrome
;
10745 if (arm_current_el(env
) != 2 && addr
< 0x14) {
10750 if (!(env
->cp15
.scr_el3
& SCR_EA
)) {
10753 if (!(env
->cp15
.scr_el3
& SCR_IRQ
)) {
10756 if (!(env
->cp15
.scr_el3
& SCR_FIQ
)) {
10760 addr
+= env
->cp15
.hvbar
;
10762 take_aarch32_exception(env
, ARM_CPU_MODE_HYP
, mask
, 0, addr
);
10765 static void arm_cpu_do_interrupt_aarch32(CPUState
*cs
)
10767 ARMCPU
*cpu
= ARM_CPU(cs
);
10768 CPUARMState
*env
= &cpu
->env
;
10775 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
10776 switch (syn_get_ec(env
->exception
.syndrome
)) {
10777 case EC_BREAKPOINT
:
10778 case EC_BREAKPOINT_SAME_EL
:
10781 case EC_WATCHPOINT
:
10782 case EC_WATCHPOINT_SAME_EL
:
10788 case EC_VECTORCATCH
:
10797 env
->cp15
.mdscr_el1
= deposit64(env
->cp15
.mdscr_el1
, 2, 4, moe
);
10800 if (env
->exception
.target_el
== 2) {
10801 arm_cpu_do_interrupt_aarch32_hyp(cs
);
10805 switch (cs
->exception_index
) {
10807 new_mode
= ARM_CPU_MODE_UND
;
10817 new_mode
= ARM_CPU_MODE_SVC
;
10820 /* The PC already points to the next instruction. */
10824 /* Fall through to prefetch abort. */
10825 case EXCP_PREFETCH_ABORT
:
10826 A32_BANKED_CURRENT_REG_SET(env
, ifsr
, env
->exception
.fsr
);
10827 A32_BANKED_CURRENT_REG_SET(env
, ifar
, env
->exception
.vaddress
);
10828 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
10829 env
->exception
.fsr
, (uint32_t)env
->exception
.vaddress
);
10830 new_mode
= ARM_CPU_MODE_ABT
;
10832 mask
= CPSR_A
| CPSR_I
;
10835 case EXCP_DATA_ABORT
:
10836 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
10837 A32_BANKED_CURRENT_REG_SET(env
, dfar
, env
->exception
.vaddress
);
10838 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
10839 env
->exception
.fsr
,
10840 (uint32_t)env
->exception
.vaddress
);
10841 new_mode
= ARM_CPU_MODE_ABT
;
10843 mask
= CPSR_A
| CPSR_I
;
10847 new_mode
= ARM_CPU_MODE_IRQ
;
10849 /* Disable IRQ and imprecise data aborts. */
10850 mask
= CPSR_A
| CPSR_I
;
10852 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
10853 /* IRQ routed to monitor mode */
10854 new_mode
= ARM_CPU_MODE_MON
;
10859 new_mode
= ARM_CPU_MODE_FIQ
;
10861 /* Disable FIQ, IRQ and imprecise data aborts. */
10862 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
10863 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
10864 /* FIQ routed to monitor mode */
10865 new_mode
= ARM_CPU_MODE_MON
;
10870 new_mode
= ARM_CPU_MODE_IRQ
;
10872 /* Disable IRQ and imprecise data aborts. */
10873 mask
= CPSR_A
| CPSR_I
;
10877 new_mode
= ARM_CPU_MODE_FIQ
;
10879 /* Disable FIQ, IRQ and imprecise data aborts. */
10880 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
10886 * Note that this is reported as a data abort, but the DFAR
10887 * has an UNKNOWN value. Construct the SError syndrome from
10888 * AET and ExT fields.
10890 ARMMMUFaultInfo fi
= { .type
= ARMFault_AsyncExternal
, };
10892 if (extended_addresses_enabled(env
)) {
10893 env
->exception
.fsr
= arm_fi_to_lfsc(&fi
);
10895 env
->exception
.fsr
= arm_fi_to_sfsc(&fi
);
10897 env
->exception
.fsr
|= env
->cp15
.vsesr_el2
& 0xd000;
10898 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
10899 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x\n",
10900 env
->exception
.fsr
);
10902 new_mode
= ARM_CPU_MODE_ABT
;
10904 mask
= CPSR_A
| CPSR_I
;
10909 new_mode
= ARM_CPU_MODE_MON
;
10911 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
10915 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
10916 return; /* Never happens. Keep compiler happy. */
10919 if (new_mode
== ARM_CPU_MODE_MON
) {
10920 addr
+= env
->cp15
.mvbar
;
10921 } else if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
10922 /* High vectors. When enabled, base address cannot be remapped. */
10923 addr
+= 0xffff0000;
10926 * ARM v7 architectures provide a vector base address register to remap
10927 * the interrupt vector table.
10928 * This register is only followed in non-monitor mode, and is banked.
10929 * Note: only bits 31:5 are valid.
10931 addr
+= A32_BANKED_CURRENT_REG_GET(env
, vbar
);
10934 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
10935 env
->cp15
.scr_el3
&= ~SCR_NS
;
10938 take_aarch32_exception(env
, new_mode
, mask
, offset
, addr
);
10941 static int aarch64_regnum(CPUARMState
*env
, int aarch32_reg
)
10944 * Return the register number of the AArch64 view of the AArch32
10945 * register @aarch32_reg. The CPUARMState CPSR is assumed to still
10946 * be that of the AArch32 mode the exception came from.
10948 int mode
= env
->uncached_cpsr
& CPSR_M
;
10950 switch (aarch32_reg
) {
10952 return aarch32_reg
;
10954 return mode
== ARM_CPU_MODE_FIQ
? aarch32_reg
+ 16 : aarch32_reg
;
10957 case ARM_CPU_MODE_USR
:
10958 case ARM_CPU_MODE_SYS
:
10960 case ARM_CPU_MODE_HYP
:
10962 case ARM_CPU_MODE_IRQ
:
10964 case ARM_CPU_MODE_SVC
:
10966 case ARM_CPU_MODE_ABT
:
10968 case ARM_CPU_MODE_UND
:
10970 case ARM_CPU_MODE_FIQ
:
10973 g_assert_not_reached();
10977 case ARM_CPU_MODE_USR
:
10978 case ARM_CPU_MODE_SYS
:
10979 case ARM_CPU_MODE_HYP
:
10981 case ARM_CPU_MODE_IRQ
:
10983 case ARM_CPU_MODE_SVC
:
10985 case ARM_CPU_MODE_ABT
:
10987 case ARM_CPU_MODE_UND
:
10989 case ARM_CPU_MODE_FIQ
:
10992 g_assert_not_reached();
10997 g_assert_not_reached();
11001 static uint32_t cpsr_read_for_spsr_elx(CPUARMState
*env
)
11003 uint32_t ret
= cpsr_read(env
);
11005 /* Move DIT to the correct location for SPSR_ELx */
11006 if (ret
& CPSR_DIT
) {
11010 /* Merge PSTATE.SS into SPSR_ELx */
11011 ret
|= env
->pstate
& PSTATE_SS
;
11016 static bool syndrome_is_sync_extabt(uint32_t syndrome
)
11018 /* Return true if this syndrome value is a synchronous external abort */
11019 switch (syn_get_ec(syndrome
)) {
11021 case EC_INSNABORT_SAME_EL
:
11023 case EC_DATAABORT_SAME_EL
:
11024 /* Look at fault status code for all the synchronous ext abort cases */
11025 switch (syndrome
& 0x3f) {
11041 /* Handle exception entry to a target EL which is using AArch64 */
11042 static void arm_cpu_do_interrupt_aarch64(CPUState
*cs
)
11044 ARMCPU
*cpu
= ARM_CPU(cs
);
11045 CPUARMState
*env
= &cpu
->env
;
11046 unsigned int new_el
= env
->exception
.target_el
;
11047 target_ulong addr
= env
->cp15
.vbar_el
[new_el
];
11048 unsigned int new_mode
= aarch64_pstate_mode(new_el
, true);
11049 unsigned int old_mode
;
11050 unsigned int cur_el
= arm_current_el(env
);
11053 if (tcg_enabled()) {
11055 * Note that new_el can never be 0. If cur_el is 0, then
11056 * el0_a64 is is_a64(), else el0_a64 is ignored.
11058 aarch64_sve_change_el(env
, cur_el
, new_el
, is_a64(env
));
11061 if (cur_el
< new_el
) {
11063 * Entry vector offset depends on whether the implemented EL
11064 * immediately lower than the target level is using AArch32 or AArch64
11071 is_aa64
= (env
->cp15
.scr_el3
& SCR_RW
) != 0;
11074 hcr
= arm_hcr_el2_eff(env
);
11075 if ((hcr
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
11076 is_aa64
= (hcr
& HCR_RW
) != 0;
11081 is_aa64
= is_a64(env
);
11084 g_assert_not_reached();
11092 } else if (pstate_read(env
) & PSTATE_SP
) {
11096 switch (cs
->exception_index
) {
11098 qemu_log_mask(CPU_LOG_INT
, "...with MFAR 0x%" PRIx64
"\n",
11099 env
->cp15
.mfar_el3
);
11101 case EXCP_PREFETCH_ABORT
:
11102 case EXCP_DATA_ABORT
:
11104 * FEAT_DoubleFault allows synchronous external aborts taken to EL3
11105 * to be taken to the SError vector entrypoint.
11107 if (new_el
== 3 && (env
->cp15
.scr_el3
& SCR_EASE
) &&
11108 syndrome_is_sync_extabt(env
->exception
.syndrome
)) {
11111 env
->cp15
.far_el
[new_el
] = env
->exception
.vaddress
;
11112 qemu_log_mask(CPU_LOG_INT
, "...with FAR 0x%" PRIx64
"\n",
11113 env
->cp15
.far_el
[new_el
]);
11119 case EXCP_HYP_TRAP
:
11121 switch (syn_get_ec(env
->exception
.syndrome
)) {
11122 case EC_ADVSIMDFPACCESSTRAP
:
11124 * QEMU internal FP/SIMD syndromes from AArch32 include the
11125 * TA and coproc fields which are only exposed if the exception
11126 * is taken to AArch32 Hyp mode. Mask them out to get a valid
11127 * AArch64 format syndrome.
11129 env
->exception
.syndrome
&= ~MAKE_64BIT_MASK(0, 20);
11131 case EC_CP14RTTRAP
:
11132 case EC_CP15RTTRAP
:
11133 case EC_CP14DTTRAP
:
11135 * For a trap on AArch32 MRC/MCR/LDC/STC the Rt field is currently
11136 * the raw register field from the insn; when taking this to
11137 * AArch64 we must convert it to the AArch64 view of the register
11138 * number. Notice that we read a 4-bit AArch32 register number and
11139 * write back a 5-bit AArch64 one.
11141 rt
= extract32(env
->exception
.syndrome
, 5, 4);
11142 rt
= aarch64_regnum(env
, rt
);
11143 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
11146 case EC_CP15RRTTRAP
:
11147 case EC_CP14RRTTRAP
:
11148 /* Similarly for MRRC/MCRR traps for Rt and Rt2 fields */
11149 rt
= extract32(env
->exception
.syndrome
, 5, 4);
11150 rt
= aarch64_regnum(env
, rt
);
11151 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
11153 rt
= extract32(env
->exception
.syndrome
, 10, 4);
11154 rt
= aarch64_regnum(env
, rt
);
11155 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
11159 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
11171 /* Construct the SError syndrome from IDS and ISS fields. */
11172 env
->exception
.syndrome
= syn_serror(env
->cp15
.vsesr_el2
& 0x1ffffff);
11173 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
11176 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
11180 old_mode
= pstate_read(env
);
11181 aarch64_save_sp(env
, arm_current_el(env
));
11182 env
->elr_el
[new_el
] = env
->pc
;
11184 old_mode
= cpsr_read_for_spsr_elx(env
);
11185 env
->elr_el
[new_el
] = env
->regs
[15];
11187 aarch64_sync_32_to_64(env
);
11189 env
->condexec_bits
= 0;
11191 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = old_mode
;
11193 qemu_log_mask(CPU_LOG_INT
, "...with ELR 0x%" PRIx64
"\n",
11194 env
->elr_el
[new_el
]);
11196 if (cpu_isar_feature(aa64_pan
, cpu
)) {
11197 /* The value of PSTATE.PAN is normally preserved, except when ... */
11198 new_mode
|= old_mode
& PSTATE_PAN
;
11201 /* ... the target is EL2 with HCR_EL2.{E2H,TGE} == '11' ... */
11202 if ((arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
))
11203 != (HCR_E2H
| HCR_TGE
)) {
11208 /* ... the target is EL1 ... */
11209 /* ... and SCTLR_ELx.SPAN == 0, then set to 1. */
11210 if ((env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
) == 0) {
11211 new_mode
|= PSTATE_PAN
;
11216 if (cpu_isar_feature(aa64_mte
, cpu
)) {
11217 new_mode
|= PSTATE_TCO
;
11220 if (cpu_isar_feature(aa64_ssbs
, cpu
)) {
11221 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_DSSBS_64
) {
11222 new_mode
|= PSTATE_SSBS
;
11224 new_mode
&= ~PSTATE_SSBS
;
11228 pstate_write(env
, PSTATE_DAIF
| new_mode
);
11229 env
->aarch64
= true;
11230 aarch64_restore_sp(env
, new_el
);
11232 if (tcg_enabled()) {
11233 helper_rebuild_hflags_a64(env
, new_el
);
11238 qemu_log_mask(CPU_LOG_INT
, "...to EL%d PC 0x%" PRIx64
" PSTATE 0x%x\n",
11239 new_el
, env
->pc
, pstate_read(env
));
11243 * Do semihosting call and set the appropriate return value. All the
11244 * permission and validity checks have been done at translate time.
11246 * We only see semihosting exceptions in TCG only as they are not
11247 * trapped to the hypervisor in KVM.
11250 static void tcg_handle_semihosting(CPUState
*cs
)
11252 ARMCPU
*cpu
= ARM_CPU(cs
);
11253 CPUARMState
*env
= &cpu
->env
;
11256 qemu_log_mask(CPU_LOG_INT
,
11257 "...handling as semihosting call 0x%" PRIx64
"\n",
11259 do_common_semihosting(cs
);
11262 qemu_log_mask(CPU_LOG_INT
,
11263 "...handling as semihosting call 0x%x\n",
11265 do_common_semihosting(cs
);
11266 env
->regs
[15] += env
->thumb
? 2 : 4;
11272 * Handle a CPU exception for A and R profile CPUs.
11273 * Do any appropriate logging, handle PSCI calls, and then hand off
11274 * to the AArch64-entry or AArch32-entry function depending on the
11275 * target exception level's register width.
11277 * Note: this is used for both TCG (as the do_interrupt tcg op),
11278 * and KVM to re-inject guest debug exceptions, and to
11279 * inject a Synchronous-External-Abort.
11281 void arm_cpu_do_interrupt(CPUState
*cs
)
11283 ARMCPU
*cpu
= ARM_CPU(cs
);
11284 CPUARMState
*env
= &cpu
->env
;
11285 unsigned int new_el
= env
->exception
.target_el
;
11287 assert(!arm_feature(env
, ARM_FEATURE_M
));
11289 arm_log_exception(cs
);
11290 qemu_log_mask(CPU_LOG_INT
, "...from EL%d to EL%d\n", arm_current_el(env
),
11292 if (qemu_loglevel_mask(CPU_LOG_INT
)
11293 && !excp_is_internal(cs
->exception_index
)) {
11294 qemu_log_mask(CPU_LOG_INT
, "...with ESR 0x%x/0x%" PRIx32
"\n",
11295 syn_get_ec(env
->exception
.syndrome
),
11296 env
->exception
.syndrome
);
11299 if (tcg_enabled() && arm_is_psci_call(cpu
, cs
->exception_index
)) {
11300 arm_handle_psci_call(cpu
);
11301 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
11306 * Semihosting semantics depend on the register width of the code
11307 * that caused the exception, not the target exception level, so
11308 * must be handled here.
11311 if (cs
->exception_index
== EXCP_SEMIHOST
) {
11312 tcg_handle_semihosting(cs
);
11318 * Hooks may change global state so BQL should be held, also the
11319 * BQL needs to be held for any modification of
11320 * cs->interrupt_request.
11322 g_assert(qemu_mutex_iothread_locked());
11324 arm_call_pre_el_change_hook(cpu
);
11326 assert(!excp_is_internal(cs
->exception_index
));
11327 if (arm_el_is_aa64(env
, new_el
)) {
11328 arm_cpu_do_interrupt_aarch64(cs
);
11330 arm_cpu_do_interrupt_aarch32(cs
);
11333 arm_call_el_change_hook(cpu
);
11335 if (!kvm_enabled()) {
11336 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
11339 #endif /* !CONFIG_USER_ONLY */
11341 uint64_t arm_sctlr(CPUARMState
*env
, int el
)
11343 /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */
11345 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, 0);
11346 el
= mmu_idx
== ARMMMUIdx_E20_0
? 2 : 1;
11348 return env
->cp15
.sctlr_el
[el
];
11351 int aa64_va_parameter_tbi(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11353 if (regime_has_2_ranges(mmu_idx
)) {
11354 return extract64(tcr
, 37, 2);
11355 } else if (regime_is_stage2(mmu_idx
)) {
11356 return 0; /* VTCR_EL2 */
11358 /* Replicate the single TBI bit so we always have 2 bits. */
11359 return extract32(tcr
, 20, 1) * 3;
11363 int aa64_va_parameter_tbid(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11365 if (regime_has_2_ranges(mmu_idx
)) {
11366 return extract64(tcr
, 51, 2);
11367 } else if (regime_is_stage2(mmu_idx
)) {
11368 return 0; /* VTCR_EL2 */
11370 /* Replicate the single TBID bit so we always have 2 bits. */
11371 return extract32(tcr
, 29, 1) * 3;
11375 int aa64_va_parameter_tcma(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11377 if (regime_has_2_ranges(mmu_idx
)) {
11378 return extract64(tcr
, 57, 2);
11380 /* Replicate the single TCMA bit so we always have 2 bits. */
11381 return extract32(tcr
, 30, 1) * 3;
11385 static ARMGranuleSize
tg0_to_gran_size(int tg
)
11395 return GranInvalid
;
11399 static ARMGranuleSize
tg1_to_gran_size(int tg
)
11409 return GranInvalid
;
11413 static inline bool have4k(ARMCPU
*cpu
, bool stage2
)
11415 return stage2
? cpu_isar_feature(aa64_tgran4_2
, cpu
)
11416 : cpu_isar_feature(aa64_tgran4
, cpu
);
11419 static inline bool have16k(ARMCPU
*cpu
, bool stage2
)
11421 return stage2
? cpu_isar_feature(aa64_tgran16_2
, cpu
)
11422 : cpu_isar_feature(aa64_tgran16
, cpu
);
11425 static inline bool have64k(ARMCPU
*cpu
, bool stage2
)
11427 return stage2
? cpu_isar_feature(aa64_tgran64_2
, cpu
)
11428 : cpu_isar_feature(aa64_tgran64
, cpu
);
11431 static ARMGranuleSize
sanitize_gran_size(ARMCPU
*cpu
, ARMGranuleSize gran
,
11436 if (have4k(cpu
, stage2
)) {
11441 if (have16k(cpu
, stage2
)) {
11446 if (have64k(cpu
, stage2
)) {
11454 * If the guest selects a granule size that isn't implemented,
11455 * the architecture requires that we behave as if it selected one
11456 * that is (with an IMPDEF choice of which one to pick). We choose
11457 * to implement the smallest supported granule size.
11459 if (have4k(cpu
, stage2
)) {
11462 if (have16k(cpu
, stage2
)) {
11465 assert(have64k(cpu
, stage2
));
11469 ARMVAParameters
aa64_va_parameters(CPUARMState
*env
, uint64_t va
,
11470 ARMMMUIdx mmu_idx
, bool data
,
11473 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
11474 bool epd
, hpd
, tsz_oob
, ds
, ha
, hd
;
11475 int select
, tsz
, tbi
, max_tsz
, min_tsz
, ps
, sh
;
11476 ARMGranuleSize gran
;
11477 ARMCPU
*cpu
= env_archcpu(env
);
11478 bool stage2
= regime_is_stage2(mmu_idx
);
11480 if (!regime_has_2_ranges(mmu_idx
)) {
11482 tsz
= extract32(tcr
, 0, 6);
11483 gran
= tg0_to_gran_size(extract32(tcr
, 14, 2));
11488 hpd
= extract32(tcr
, 24, 1);
11491 sh
= extract32(tcr
, 12, 2);
11492 ps
= extract32(tcr
, 16, 3);
11493 ha
= extract32(tcr
, 21, 1) && cpu_isar_feature(aa64_hafs
, cpu
);
11494 hd
= extract32(tcr
, 22, 1) && cpu_isar_feature(aa64_hdbs
, cpu
);
11495 ds
= extract64(tcr
, 32, 1);
11500 * Bit 55 is always between the two regions, and is canonical for
11501 * determining if address tagging is enabled.
11503 select
= extract64(va
, 55, 1);
11505 tsz
= extract32(tcr
, 0, 6);
11506 gran
= tg0_to_gran_size(extract32(tcr
, 14, 2));
11507 epd
= extract32(tcr
, 7, 1);
11508 sh
= extract32(tcr
, 12, 2);
11509 hpd
= extract64(tcr
, 41, 1);
11510 e0pd
= extract64(tcr
, 55, 1);
11512 tsz
= extract32(tcr
, 16, 6);
11513 gran
= tg1_to_gran_size(extract32(tcr
, 30, 2));
11514 epd
= extract32(tcr
, 23, 1);
11515 sh
= extract32(tcr
, 28, 2);
11516 hpd
= extract64(tcr
, 42, 1);
11517 e0pd
= extract64(tcr
, 56, 1);
11519 ps
= extract64(tcr
, 32, 3);
11520 ha
= extract64(tcr
, 39, 1) && cpu_isar_feature(aa64_hafs
, cpu
);
11521 hd
= extract64(tcr
, 40, 1) && cpu_isar_feature(aa64_hdbs
, cpu
);
11522 ds
= extract64(tcr
, 59, 1);
11524 if (e0pd
&& cpu_isar_feature(aa64_e0pd
, cpu
) &&
11525 regime_is_user(env
, mmu_idx
)) {
11530 gran
= sanitize_gran_size(cpu
, gran
, stage2
);
11532 if (cpu_isar_feature(aa64_st
, cpu
)) {
11533 max_tsz
= 48 - (gran
== Gran64K
);
11539 * DS is RES0 unless FEAT_LPA2 is supported for the given page size;
11540 * adjust the effective value of DS, as documented.
11543 if (gran
== Gran64K
) {
11544 if (cpu_isar_feature(aa64_lva
, cpu
)) {
11549 if (regime_is_stage2(mmu_idx
)) {
11550 if (gran
== Gran16K
) {
11551 ds
= cpu_isar_feature(aa64_tgran16_2_lpa2
, cpu
);
11553 ds
= cpu_isar_feature(aa64_tgran4_2_lpa2
, cpu
);
11556 if (gran
== Gran16K
) {
11557 ds
= cpu_isar_feature(aa64_tgran16_lpa2
, cpu
);
11559 ds
= cpu_isar_feature(aa64_tgran4_lpa2
, cpu
);
11567 if (stage2
&& el1_is_aa32
) {
11569 * For AArch32 EL1 the min txsz (and thus max IPA size) requirements
11570 * are loosened: a configured IPA of 40 bits is permitted even if
11571 * the implemented PA is less than that (and so a 40 bit IPA would
11572 * fault for an AArch64 EL1). See R_DTLMN.
11574 min_tsz
= MIN(min_tsz
, 24);
11577 if (tsz
> max_tsz
) {
11580 } else if (tsz
< min_tsz
) {
11587 /* Present TBI as a composite with TBID. */
11588 tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
11590 tbi
&= ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
11592 tbi
= (tbi
>> select
) & 1;
11594 return (ARMVAParameters
) {
11602 .tsz_oob
= tsz_oob
,
11611 * Note that signed overflow is undefined in C. The following routines are
11612 * careful to use unsigned types where modulo arithmetic is required.
11613 * Failure to do so _will_ break on newer gcc.
11616 /* Signed saturating arithmetic. */
11618 /* Perform 16-bit signed saturating addition. */
11619 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
11624 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
11634 /* Perform 8-bit signed saturating addition. */
11635 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
11640 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
11650 /* Perform 16-bit signed saturating subtraction. */
11651 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
11656 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
11666 /* Perform 8-bit signed saturating subtraction. */
11667 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
11672 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
11682 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
11683 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
11684 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
11685 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
11688 #include "op_addsub.h"
11690 /* Unsigned saturating arithmetic. */
11691 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
11701 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
11710 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
11720 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
11729 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
11730 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
11731 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
11732 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
11735 #include "op_addsub.h"
11737 /* Signed modulo arithmetic. */
11738 #define SARITH16(a, b, n, op) do { \
11740 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
11741 RESULT(sum, n, 16); \
11743 ge |= 3 << (n * 2); \
11746 #define SARITH8(a, b, n, op) do { \
11748 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
11749 RESULT(sum, n, 8); \
11755 #define ADD16(a, b, n) SARITH16(a, b, n, +)
11756 #define SUB16(a, b, n) SARITH16(a, b, n, -)
11757 #define ADD8(a, b, n) SARITH8(a, b, n, +)
11758 #define SUB8(a, b, n) SARITH8(a, b, n, -)
11762 #include "op_addsub.h"
11764 /* Unsigned modulo arithmetic. */
11765 #define ADD16(a, b, n) do { \
11767 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
11768 RESULT(sum, n, 16); \
11769 if ((sum >> 16) == 1) \
11770 ge |= 3 << (n * 2); \
11773 #define ADD8(a, b, n) do { \
11775 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
11776 RESULT(sum, n, 8); \
11777 if ((sum >> 8) == 1) \
11781 #define SUB16(a, b, n) do { \
11783 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
11784 RESULT(sum, n, 16); \
11785 if ((sum >> 16) == 0) \
11786 ge |= 3 << (n * 2); \
11789 #define SUB8(a, b, n) do { \
11791 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
11792 RESULT(sum, n, 8); \
11793 if ((sum >> 8) == 0) \
11800 #include "op_addsub.h"
11802 /* Halved signed arithmetic. */
11803 #define ADD16(a, b, n) \
11804 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
11805 #define SUB16(a, b, n) \
11806 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
11807 #define ADD8(a, b, n) \
11808 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
11809 #define SUB8(a, b, n) \
11810 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
11813 #include "op_addsub.h"
11815 /* Halved unsigned arithmetic. */
11816 #define ADD16(a, b, n) \
11817 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
11818 #define SUB16(a, b, n) \
11819 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
11820 #define ADD8(a, b, n) \
11821 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
11822 #define SUB8(a, b, n) \
11823 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
11826 #include "op_addsub.h"
11828 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
11837 /* Unsigned sum of absolute byte differences. */
11838 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
11841 sum
= do_usad(a
, b
);
11842 sum
+= do_usad(a
>> 8, b
>> 8);
11843 sum
+= do_usad(a
>> 16, b
>> 16);
11844 sum
+= do_usad(a
>> 24, b
>> 24);
11848 /* For ARMv6 SEL instruction. */
11849 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
11864 mask
|= 0xff000000;
11866 return (a
& mask
) | (b
& ~mask
);
11871 * The upper bytes of val (above the number specified by 'bytes') must have
11872 * been zeroed out by the caller.
11874 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
11878 stl_le_p(buf
, val
);
11880 /* zlib crc32 converts the accumulator and output to one's complement. */
11881 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
11884 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
11888 stl_le_p(buf
, val
);
11890 /* Linux crc32c converts the output to one's complement. */
11891 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;
11895 * Return the exception level to which FP-disabled exceptions should
11896 * be taken, or 0 if FP is enabled.
11898 int fp_exception_el(CPUARMState
*env
, int cur_el
)
11900 #ifndef CONFIG_USER_ONLY
11904 * CPACR and the CPTR registers don't exist before v6, so FP is
11905 * always accessible
11907 if (!arm_feature(env
, ARM_FEATURE_V6
)) {
11911 if (arm_feature(env
, ARM_FEATURE_M
)) {
11912 /* CPACR can cause a NOCP UsageFault taken to current security state */
11913 if (!v7m_cpacr_pass(env
, env
->v7m
.secure
, cur_el
!= 0)) {
11917 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) && !env
->v7m
.secure
) {
11918 if (!extract32(env
->v7m
.nsacr
, 10, 1)) {
11919 /* FP insns cause a NOCP UsageFault taken to Secure */
11927 hcr_el2
= arm_hcr_el2_eff(env
);
11930 * The CPACR controls traps to EL1, or PL1 if we're 32 bit:
11931 * 0, 2 : trap EL0 and EL1/PL1 accesses
11932 * 1 : trap only EL0 accesses
11933 * 3 : trap no accesses
11934 * This register is ignored if E2H+TGE are both set.
11936 if ((hcr_el2
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
11937 int fpen
= FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, FPEN
);
11947 /* Trap from Secure PL0 or PL1 to Secure PL1. */
11948 if (!arm_el_is_aa64(env
, 3)
11949 && (cur_el
== 3 || arm_is_secure_below_el3(env
))) {
11960 * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode
11961 * to control non-secure access to the FPU. It doesn't have any
11962 * effect if EL3 is AArch64 or if EL3 doesn't exist at all.
11964 if ((arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
11965 cur_el
<= 2 && !arm_is_secure_below_el3(env
))) {
11966 if (!extract32(env
->cp15
.nsacr
, 10, 1)) {
11967 /* FP insns act as UNDEF */
11968 return cur_el
== 2 ? 2 : 1;
11973 * CPTR_EL2 is present in v7VE or v8, and changes format
11974 * with HCR_EL2.E2H (regardless of TGE).
11977 if (hcr_el2
& HCR_E2H
) {
11978 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, FPEN
)) {
11980 if (cur_el
!= 0 || !(hcr_el2
& HCR_TGE
)) {
11988 } else if (arm_is_el2_enabled(env
)) {
11989 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TFP
)) {
11995 /* CPTR_EL3 : present in v8 */
11996 if (FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TFP
)) {
11997 /* Trap all FP ops to EL3 */
12004 /* Return the exception level we're running at if this is our mmu_idx */
12005 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx
)
12007 if (mmu_idx
& ARM_MMU_IDX_M
) {
12008 return mmu_idx
& ARM_MMU_IDX_M_PRIV
;
12012 case ARMMMUIdx_E10_0
:
12013 case ARMMMUIdx_E20_0
:
12015 case ARMMMUIdx_E10_1
:
12016 case ARMMMUIdx_E10_1_PAN
:
12019 case ARMMMUIdx_E20_2
:
12020 case ARMMMUIdx_E20_2_PAN
:
12025 g_assert_not_reached();
12030 ARMMMUIdx
arm_v7m_mmu_idx_for_secstate(CPUARMState
*env
, bool secstate
)
12032 g_assert_not_reached();
12036 static bool arm_pan_enabled(CPUARMState
*env
)
12039 return env
->pstate
& PSTATE_PAN
;
12041 return env
->uncached_cpsr
& CPSR_PAN
;
12045 ARMMMUIdx
arm_mmu_idx_el(CPUARMState
*env
, int el
)
12050 if (arm_feature(env
, ARM_FEATURE_M
)) {
12051 return arm_v7m_mmu_idx_for_secstate(env
, env
->v7m
.secure
);
12054 /* See ARM pseudo-function ELIsInHost. */
12057 hcr
= arm_hcr_el2_eff(env
);
12058 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
12059 idx
= ARMMMUIdx_E20_0
;
12061 idx
= ARMMMUIdx_E10_0
;
12065 if (arm_pan_enabled(env
)) {
12066 idx
= ARMMMUIdx_E10_1_PAN
;
12068 idx
= ARMMMUIdx_E10_1
;
12072 /* Note that TGE does not apply at EL2. */
12073 if (arm_hcr_el2_eff(env
) & HCR_E2H
) {
12074 if (arm_pan_enabled(env
)) {
12075 idx
= ARMMMUIdx_E20_2_PAN
;
12077 idx
= ARMMMUIdx_E20_2
;
12080 idx
= ARMMMUIdx_E2
;
12084 return ARMMMUIdx_E3
;
12086 g_assert_not_reached();
12092 ARMMMUIdx
arm_mmu_idx(CPUARMState
*env
)
12094 return arm_mmu_idx_el(env
, arm_current_el(env
));
12097 static bool mve_no_pred(CPUARMState
*env
)
12100 * Return true if there is definitely no predication of MVE
12101 * instructions by VPR or LTPSIZE. (Returning false even if there
12102 * isn't any predication is OK; generated code will just be
12104 * If the CPU does not implement MVE then this TB flag is always 0.
12106 * NOTE: if you change this logic, the "recalculate s->mve_no_pred"
12107 * logic in gen_update_fp_context() needs to be updated to match.
12109 * We do not include the effect of the ECI bits here -- they are
12110 * tracked in other TB flags. This simplifies the logic for
12111 * "when did we emit code that changes the MVE_NO_PRED TB flag
12112 * and thus need to end the TB?".
12114 if (cpu_isar_feature(aa32_mve
, env_archcpu(env
))) {
12117 if (env
->v7m
.vpr
) {
12120 if (env
->v7m
.ltpsize
< 4) {
12126 void cpu_get_tb_cpu_state(CPUARMState
*env
, vaddr
*pc
,
12127 uint64_t *cs_base
, uint32_t *pflags
)
12129 CPUARMTBFlags flags
;
12131 assert_hflags_rebuild_correctly(env
);
12132 flags
= env
->hflags
;
12134 if (EX_TBFLAG_ANY(flags
, AARCH64_STATE
)) {
12136 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
12137 DP_TBFLAG_A64(flags
, BTYPE
, env
->btype
);
12140 *pc
= env
->regs
[15];
12142 if (arm_feature(env
, ARM_FEATURE_M
)) {
12143 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
12144 FIELD_EX32(env
->v7m
.fpccr
[M_REG_S
], V7M_FPCCR
, S
)
12145 != env
->v7m
.secure
) {
12146 DP_TBFLAG_M32(flags
, FPCCR_S_WRONG
, 1);
12149 if ((env
->v7m
.fpccr
[env
->v7m
.secure
] & R_V7M_FPCCR_ASPEN_MASK
) &&
12150 (!(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_FPCA_MASK
) ||
12151 (env
->v7m
.secure
&&
12152 !(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
)))) {
12154 * ASPEN is set, but FPCA/SFPA indicate that there is no
12155 * active FP context; we must create a new FP context before
12156 * executing any FP insn.
12158 DP_TBFLAG_M32(flags
, NEW_FP_CTXT_NEEDED
, 1);
12161 bool is_secure
= env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_S_MASK
;
12162 if (env
->v7m
.fpccr
[is_secure
] & R_V7M_FPCCR_LSPACT_MASK
) {
12163 DP_TBFLAG_M32(flags
, LSPACT
, 1);
12166 if (mve_no_pred(env
)) {
12167 DP_TBFLAG_M32(flags
, MVE_NO_PRED
, 1);
12171 * Note that XSCALE_CPAR shares bits with VECSTRIDE.
12172 * Note that VECLEN+VECSTRIDE are RES0 for M-profile.
12174 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
12175 DP_TBFLAG_A32(flags
, XSCALE_CPAR
, env
->cp15
.c15_cpar
);
12177 DP_TBFLAG_A32(flags
, VECLEN
, env
->vfp
.vec_len
);
12178 DP_TBFLAG_A32(flags
, VECSTRIDE
, env
->vfp
.vec_stride
);
12180 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)) {
12181 DP_TBFLAG_A32(flags
, VFPEN
, 1);
12185 DP_TBFLAG_AM32(flags
, THUMB
, env
->thumb
);
12186 DP_TBFLAG_AM32(flags
, CONDEXEC
, env
->condexec_bits
);
12190 * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
12191 * states defined in the ARM ARM for software singlestep:
12192 * SS_ACTIVE PSTATE.SS State
12193 * 0 x Inactive (the TB flag for SS is always 0)
12194 * 1 0 Active-pending
12195 * 1 1 Active-not-pending
12196 * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB.
12198 if (EX_TBFLAG_ANY(flags
, SS_ACTIVE
) && (env
->pstate
& PSTATE_SS
)) {
12199 DP_TBFLAG_ANY(flags
, PSTATE__SS
, 1);
12202 *pflags
= flags
.flags
;
12203 *cs_base
= flags
.flags2
;
12206 #ifdef TARGET_AARCH64
12208 * The manual says that when SVE is enabled and VQ is widened the
12209 * implementation is allowed to zero the previously inaccessible
12210 * portion of the registers. The corollary to that is that when
12211 * SVE is enabled and VQ is narrowed we are also allowed to zero
12212 * the now inaccessible portion of the registers.
12214 * The intent of this is that no predicate bit beyond VQ is ever set.
12215 * Which means that some operations on predicate registers themselves
12216 * may operate on full uint64_t or even unrolled across the maximum
12217 * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally
12218 * may well be cheaper than conditionals to restrict the operation
12219 * to the relevant portion of a uint16_t[16].
12221 void aarch64_sve_narrow_vq(CPUARMState
*env
, unsigned vq
)
12226 assert(vq
>= 1 && vq
<= ARM_MAX_VQ
);
12227 assert(vq
<= env_archcpu(env
)->sve_max_vq
);
12229 /* Zap the high bits of the zregs. */
12230 for (i
= 0; i
< 32; i
++) {
12231 memset(&env
->vfp
.zregs
[i
].d
[2 * vq
], 0, 16 * (ARM_MAX_VQ
- vq
));
12234 /* Zap the high bits of the pregs and ffr. */
12237 pmask
= ~(-1ULL << (16 * (vq
& 3)));
12239 for (j
= vq
/ 4; j
< ARM_MAX_VQ
/ 4; j
++) {
12240 for (i
= 0; i
< 17; ++i
) {
12241 env
->vfp
.pregs
[i
].p
[j
] &= pmask
;
12247 static uint32_t sve_vqm1_for_el_sm_ena(CPUARMState
*env
, int el
, bool sm
)
12252 exc_el
= sme_exception_el(env
, el
);
12254 exc_el
= sve_exception_el(env
, el
);
12257 return 0; /* disabled */
12259 return sve_vqm1_for_el_sm(env
, el
, sm
);
12263 * Notice a change in SVE vector size when changing EL.
12265 void aarch64_sve_change_el(CPUARMState
*env
, int old_el
,
12266 int new_el
, bool el0_a64
)
12268 ARMCPU
*cpu
= env_archcpu(env
);
12269 int old_len
, new_len
;
12270 bool old_a64
, new_a64
, sm
;
12272 /* Nothing to do if no SVE. */
12273 if (!cpu_isar_feature(aa64_sve
, cpu
)) {
12277 /* Nothing to do if FP is disabled in either EL. */
12278 if (fp_exception_el(env
, old_el
) || fp_exception_el(env
, new_el
)) {
12282 old_a64
= old_el
? arm_el_is_aa64(env
, old_el
) : el0_a64
;
12283 new_a64
= new_el
? arm_el_is_aa64(env
, new_el
) : el0_a64
;
12286 * Both AArch64.TakeException and AArch64.ExceptionReturn
12287 * invoke ResetSVEState when taking an exception from, or
12288 * returning to, AArch32 state when PSTATE.SM is enabled.
12290 sm
= FIELD_EX64(env
->svcr
, SVCR
, SM
);
12291 if (old_a64
!= new_a64
&& sm
) {
12292 arm_reset_sve_state(env
);
12297 * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
12298 * at ELx, or not available because the EL is in AArch32 state, then
12299 * for all purposes other than a direct read, the ZCR_ELx.LEN field
12300 * has an effective value of 0".
12302 * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0).
12303 * If we ignore aa32 state, we would fail to see the vq4->vq0 transition
12304 * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that
12305 * we already have the correct register contents when encountering the
12306 * vq0->vq0 transition between EL0->EL1.
12308 old_len
= new_len
= 0;
12310 old_len
= sve_vqm1_for_el_sm_ena(env
, old_el
, sm
);
12313 new_len
= sve_vqm1_for_el_sm_ena(env
, new_el
, sm
);
12316 /* When changing vector length, clear inaccessible state. */
12317 if (new_len
< old_len
) {
12318 aarch64_sve_narrow_vq(env
, new_len
+ 1);
12323 #ifndef CONFIG_USER_ONLY
12324 ARMSecuritySpace
arm_security_space(CPUARMState
*env
)
12326 if (arm_feature(env
, ARM_FEATURE_M
)) {
12327 return arm_secure_to_space(env
->v7m
.secure
);
12331 * If EL3 is not supported then the secure state is implementation
12332 * defined, in which case QEMU defaults to non-secure.
12334 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
12335 return ARMSS_NonSecure
;
12338 /* Check for AArch64 EL3 or AArch32 Mon. */
12340 if (extract32(env
->pstate
, 2, 2) == 3) {
12341 if (cpu_isar_feature(aa64_rme
, env_archcpu(env
))) {
12344 return ARMSS_Secure
;
12348 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
12349 return ARMSS_Secure
;
12353 return arm_security_space_below_el3(env
);
12356 ARMSecuritySpace
arm_security_space_below_el3(CPUARMState
*env
)
12358 assert(!arm_feature(env
, ARM_FEATURE_M
));
12361 * If EL3 is not supported then the secure state is implementation
12362 * defined, in which case QEMU defaults to non-secure.
12364 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
12365 return ARMSS_NonSecure
;
12369 * Note NSE cannot be set without RME, and NSE & !NS is Reserved.
12370 * Ignoring NSE when !NS retains consistency without having to
12371 * modify other predicates.
12373 if (!(env
->cp15
.scr_el3
& SCR_NS
)) {
12374 return ARMSS_Secure
;
12375 } else if (env
->cp15
.scr_el3
& SCR_NSE
) {
12376 return ARMSS_Realm
;
12378 return ARMSS_NonSecure
;
12381 #endif /* !CONFIG_USER_ONLY */