4 * This code is licensed under the GNU GPL v2 or later.
6 * SPDX-License-Identifier: GPL-2.0-or-later
9 #include "qemu/osdep.h"
13 #include "internals.h"
14 #include "cpu-features.h"
15 #include "exec/helper-proto.h"
16 #include "qemu/main-loop.h"
17 #include "qemu/timer.h"
18 #include "qemu/bitops.h"
19 #include "qemu/crc32c.h"
20 #include "qemu/qemu-print.h"
21 #include "exec/exec-all.h"
22 #include <zlib.h> /* For crc32 */
24 #include "sysemu/cpu-timers.h"
25 #include "sysemu/kvm.h"
26 #include "sysemu/tcg.h"
27 #include "qapi/error.h"
28 #include "qemu/guest-random.h"
30 #include "semihosting/common-semi.h"
34 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
36 static void switch_mode(CPUARMState
*env
, int mode
);
38 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
40 assert(ri
->fieldoffset
);
41 if (cpreg_field_is_64bit(ri
)) {
42 return CPREG_FIELD64(env
, ri
);
44 return CPREG_FIELD32(env
, ri
);
48 void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
50 assert(ri
->fieldoffset
);
51 if (cpreg_field_is_64bit(ri
)) {
52 CPREG_FIELD64(env
, ri
) = value
;
54 CPREG_FIELD32(env
, ri
) = value
;
58 static void *raw_ptr(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
60 return (char *)env
+ ri
->fieldoffset
;
63 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
65 /* Raw read of a coprocessor register (as needed for migration, etc). */
66 if (ri
->type
& ARM_CP_CONST
) {
67 return ri
->resetvalue
;
68 } else if (ri
->raw_readfn
) {
69 return ri
->raw_readfn(env
, ri
);
70 } else if (ri
->readfn
) {
71 return ri
->readfn(env
, ri
);
73 return raw_read(env
, ri
);
77 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
81 * Raw write of a coprocessor register (as needed for migration, etc).
82 * Note that constant registers are treated as write-ignored; the
83 * caller should check for success by whether a readback gives the
86 if (ri
->type
& ARM_CP_CONST
) {
88 } else if (ri
->raw_writefn
) {
89 ri
->raw_writefn(env
, ri
, v
);
90 } else if (ri
->writefn
) {
91 ri
->writefn(env
, ri
, v
);
93 raw_write(env
, ri
, v
);
97 static bool raw_accessors_invalid(const ARMCPRegInfo
*ri
)
100 * Return true if the regdef would cause an assertion if you called
101 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
102 * program bug for it not to have the NO_RAW flag).
103 * NB that returning false here doesn't necessarily mean that calling
104 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
105 * read/write access functions which are safe for raw use" from "has
106 * read/write access functions which have side effects but has forgotten
107 * to provide raw access functions".
108 * The tests here line up with the conditions in read/write_raw_cp_reg()
109 * and assertions in raw_read()/raw_write().
111 if ((ri
->type
& ARM_CP_CONST
) ||
113 ((ri
->raw_writefn
|| ri
->writefn
) && (ri
->raw_readfn
|| ri
->readfn
))) {
119 bool write_cpustate_to_list(ARMCPU
*cpu
, bool kvm_sync
)
121 /* Write the coprocessor state from cpu->env to the (index,value) list. */
125 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
126 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
127 const ARMCPRegInfo
*ri
;
130 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
135 if (ri
->type
& ARM_CP_NO_RAW
) {
139 newval
= read_raw_cp_reg(&cpu
->env
, ri
);
142 * Only sync if the previous list->cpustate sync succeeded.
143 * Rather than tracking the success/failure state for every
144 * item in the list, we just recheck "does the raw write we must
145 * have made in write_list_to_cpustate() read back OK" here.
147 uint64_t oldval
= cpu
->cpreg_values
[i
];
149 if (oldval
== newval
) {
153 write_raw_cp_reg(&cpu
->env
, ri
, oldval
);
154 if (read_raw_cp_reg(&cpu
->env
, ri
) != oldval
) {
158 write_raw_cp_reg(&cpu
->env
, ri
, newval
);
160 cpu
->cpreg_values
[i
] = newval
;
165 bool write_list_to_cpustate(ARMCPU
*cpu
)
170 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
171 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
172 uint64_t v
= cpu
->cpreg_values
[i
];
173 const ARMCPRegInfo
*ri
;
175 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
180 if (ri
->type
& ARM_CP_NO_RAW
) {
184 * Write value and confirm it reads back as written
185 * (to catch read-only registers and partially read-only
186 * registers where the incoming migration value doesn't match)
188 write_raw_cp_reg(&cpu
->env
, ri
, v
);
189 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
196 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
198 ARMCPU
*cpu
= opaque
;
199 uint32_t regidx
= (uintptr_t)key
;
200 const ARMCPRegInfo
*ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
202 if (!(ri
->type
& (ARM_CP_NO_RAW
| ARM_CP_ALIAS
))) {
203 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
204 /* The value array need not be initialized at this point */
205 cpu
->cpreg_array_len
++;
209 static void count_cpreg(gpointer key
, gpointer opaque
)
211 ARMCPU
*cpu
= opaque
;
212 const ARMCPRegInfo
*ri
;
214 ri
= g_hash_table_lookup(cpu
->cp_regs
, key
);
216 if (!(ri
->type
& (ARM_CP_NO_RAW
| ARM_CP_ALIAS
))) {
217 cpu
->cpreg_array_len
++;
221 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
223 uint64_t aidx
= cpreg_to_kvm_id((uintptr_t)a
);
224 uint64_t bidx
= cpreg_to_kvm_id((uintptr_t)b
);
235 void init_cpreg_list(ARMCPU
*cpu
)
238 * Initialise the cpreg_tuples[] array based on the cp_regs hash.
239 * Note that we require cpreg_tuples[] to be sorted by key ID.
244 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
245 keys
= g_list_sort(keys
, cpreg_key_compare
);
247 cpu
->cpreg_array_len
= 0;
249 g_list_foreach(keys
, count_cpreg
, cpu
);
251 arraylen
= cpu
->cpreg_array_len
;
252 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
253 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
254 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
255 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
256 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
257 cpu
->cpreg_array_len
= 0;
259 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
261 assert(cpu
->cpreg_array_len
== arraylen
);
266 static bool arm_pan_enabled(CPUARMState
*env
)
269 if ((arm_hcr_el2_eff(env
) & (HCR_NV
| HCR_NV1
)) == (HCR_NV
| HCR_NV1
)) {
272 return env
->pstate
& PSTATE_PAN
;
274 return env
->uncached_cpsr
& CPSR_PAN
;
279 * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0.
281 static CPAccessResult
access_el3_aa32ns(CPUARMState
*env
,
282 const ARMCPRegInfo
*ri
,
285 if (!is_a64(env
) && arm_current_el(env
) == 3 &&
286 arm_is_secure_below_el3(env
)) {
287 return CP_ACCESS_TRAP_UNCATEGORIZED
;
293 * Some secure-only AArch32 registers trap to EL3 if used from
294 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
295 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
296 * We assume that the .access field is set to PL1_RW.
298 static CPAccessResult
access_trap_aa32s_el1(CPUARMState
*env
,
299 const ARMCPRegInfo
*ri
,
302 if (arm_current_el(env
) == 3) {
305 if (arm_is_secure_below_el3(env
)) {
306 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
307 return CP_ACCESS_TRAP_EL2
;
309 return CP_ACCESS_TRAP_EL3
;
311 /* This will be EL1 NS and EL2 NS, which just UNDEF */
312 return CP_ACCESS_TRAP_UNCATEGORIZED
;
316 * Check for traps to performance monitor registers, which are controlled
317 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
319 static CPAccessResult
access_tpm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
322 int el
= arm_current_el(env
);
323 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
325 if (el
< 2 && (mdcr_el2
& MDCR_TPM
)) {
326 return CP_ACCESS_TRAP_EL2
;
328 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
329 return CP_ACCESS_TRAP_EL3
;
334 /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */
335 CPAccessResult
access_tvm_trvm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
338 if (arm_current_el(env
) == 1) {
339 uint64_t trap
= isread
? HCR_TRVM
: HCR_TVM
;
340 if (arm_hcr_el2_eff(env
) & trap
) {
341 return CP_ACCESS_TRAP_EL2
;
347 /* Check for traps from EL1 due to HCR_EL2.TSW. */
348 static CPAccessResult
access_tsw(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
351 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TSW
)) {
352 return CP_ACCESS_TRAP_EL2
;
357 /* Check for traps from EL1 due to HCR_EL2.TACR. */
358 static CPAccessResult
access_tacr(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
361 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TACR
)) {
362 return CP_ACCESS_TRAP_EL2
;
367 /* Check for traps from EL1 due to HCR_EL2.TTLB. */
368 static CPAccessResult
access_ttlb(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
371 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TTLB
)) {
372 return CP_ACCESS_TRAP_EL2
;
377 /* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBIS. */
378 static CPAccessResult
access_ttlbis(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
381 if (arm_current_el(env
) == 1 &&
382 (arm_hcr_el2_eff(env
) & (HCR_TTLB
| HCR_TTLBIS
))) {
383 return CP_ACCESS_TRAP_EL2
;
388 #ifdef TARGET_AARCH64
389 /* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBOS. */
390 static CPAccessResult
access_ttlbos(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
393 if (arm_current_el(env
) == 1 &&
394 (arm_hcr_el2_eff(env
) & (HCR_TTLB
| HCR_TTLBOS
))) {
395 return CP_ACCESS_TRAP_EL2
;
401 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
403 ARMCPU
*cpu
= env_archcpu(env
);
405 raw_write(env
, ri
, value
);
406 tlb_flush(CPU(cpu
)); /* Flush TLB as domain not tracked in TLB */
409 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
411 ARMCPU
*cpu
= env_archcpu(env
);
413 if (raw_read(env
, ri
) != value
) {
415 * Unlike real hardware the qemu TLB uses virtual addresses,
416 * not modified virtual addresses, so this causes a TLB flush.
419 raw_write(env
, ri
, value
);
423 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
426 ARMCPU
*cpu
= env_archcpu(env
);
428 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_PMSA
)
429 && !extended_addresses_enabled(env
)) {
431 * For VMSA (when not using the LPAE long descriptor page table
432 * format) this register includes the ASID, so do a TLB flush.
433 * For PMSA it is purely a process ID and no action is needed.
437 raw_write(env
, ri
, value
);
440 static int alle1_tlbmask(CPUARMState
*env
)
443 * Note that the 'ALL' scope must invalidate both stage 1 and
444 * stage 2 translations, whereas most other scopes only invalidate
445 * stage 1 translations.
447 return (ARMMMUIdxBit_E10_1
|
448 ARMMMUIdxBit_E10_1_PAN
|
450 ARMMMUIdxBit_Stage2
|
451 ARMMMUIdxBit_Stage2_S
);
455 /* IS variants of TLB operations must affect all cores */
456 static void tlbiall_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
459 CPUState
*cs
= env_cpu(env
);
461 tlb_flush_all_cpus_synced(cs
);
464 static void tlbiasid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
467 CPUState
*cs
= env_cpu(env
);
469 tlb_flush_all_cpus_synced(cs
);
472 static void tlbimva_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
475 CPUState
*cs
= env_cpu(env
);
477 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
480 static void tlbimvaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
483 CPUState
*cs
= env_cpu(env
);
485 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
489 * Non-IS variants of TLB operations are upgraded to
490 * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to
491 * force broadcast of these operations.
493 static bool tlb_force_broadcast(CPUARMState
*env
)
495 return arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_FB
);
498 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
501 /* Invalidate all (TLBIALL) */
502 CPUState
*cs
= env_cpu(env
);
504 if (tlb_force_broadcast(env
)) {
505 tlb_flush_all_cpus_synced(cs
);
511 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
514 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
515 CPUState
*cs
= env_cpu(env
);
517 value
&= TARGET_PAGE_MASK
;
518 if (tlb_force_broadcast(env
)) {
519 tlb_flush_page_all_cpus_synced(cs
, value
);
521 tlb_flush_page(cs
, value
);
525 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
528 /* Invalidate by ASID (TLBIASID) */
529 CPUState
*cs
= env_cpu(env
);
531 if (tlb_force_broadcast(env
)) {
532 tlb_flush_all_cpus_synced(cs
);
538 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
541 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
542 CPUState
*cs
= env_cpu(env
);
544 value
&= TARGET_PAGE_MASK
;
545 if (tlb_force_broadcast(env
)) {
546 tlb_flush_page_all_cpus_synced(cs
, value
);
548 tlb_flush_page(cs
, value
);
552 static void tlbiall_nsnh_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
555 CPUState
*cs
= env_cpu(env
);
557 tlb_flush_by_mmuidx(cs
, alle1_tlbmask(env
));
560 static void tlbiall_nsnh_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
563 CPUState
*cs
= env_cpu(env
);
565 tlb_flush_by_mmuidx_all_cpus_synced(cs
, alle1_tlbmask(env
));
569 static void tlbiall_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
572 CPUState
*cs
= env_cpu(env
);
574 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_E2
);
577 static void tlbiall_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
580 CPUState
*cs
= env_cpu(env
);
582 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_E2
);
585 static void tlbimva_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
588 CPUState
*cs
= env_cpu(env
);
589 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
591 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_E2
);
594 static void tlbimva_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
597 CPUState
*cs
= env_cpu(env
);
598 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
600 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
604 static void tlbiipas2_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
607 CPUState
*cs
= env_cpu(env
);
608 uint64_t pageaddr
= (value
& MAKE_64BIT_MASK(0, 28)) << 12;
610 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_Stage2
);
613 static void tlbiipas2is_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
616 CPUState
*cs
= env_cpu(env
);
617 uint64_t pageaddr
= (value
& MAKE_64BIT_MASK(0, 28)) << 12;
619 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, ARMMMUIdxBit_Stage2
);
622 static const ARMCPRegInfo cp_reginfo
[] = {
624 * Define the secure and non-secure FCSE identifier CP registers
625 * separately because there is no secure bank in V8 (no _EL3). This allows
626 * the secure register to be properly reset and migrated. There is also no
627 * v8 EL1 version of the register so the non-secure instance stands alone.
630 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
631 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
632 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_ns
),
633 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
634 { .name
= "FCSEIDR_S",
635 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
636 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
637 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_s
),
638 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
640 * Define the secure and non-secure context identifier CP registers
641 * separately because there is no secure bank in V8 (no _EL3). This allows
642 * the secure register to be properly reset and migrated. In the
643 * non-secure case, the 32-bit register will have reset and migration
644 * disabled during registration as it is handled by the 64-bit instance.
646 { .name
= "CONTEXTIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
647 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
648 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
649 .fgt
= FGT_CONTEXTIDR_EL1
,
650 .nv2_redirect_offset
= 0x108 | NV2_REDIR_NV1
,
651 .secure
= ARM_CP_SECSTATE_NS
,
652 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[1]),
653 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
654 { .name
= "CONTEXTIDR_S", .state
= ARM_CP_STATE_AA32
,
655 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
656 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
657 .secure
= ARM_CP_SECSTATE_S
,
658 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_s
),
659 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
662 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
664 * NB: Some of these registers exist in v8 but with more precise
665 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
667 /* MMU Domain access control / MPU write buffer control */
669 .cp
= 15, .opc1
= CP_ANY
, .crn
= 3, .crm
= CP_ANY
, .opc2
= CP_ANY
,
670 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
671 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
672 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
673 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
675 * ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
676 * For v6 and v5, these mappings are overly broad.
678 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 0,
679 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
680 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 1,
681 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
682 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 4,
683 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
684 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 8,
685 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
686 /* Cache maintenance ops; some of this space may be overridden later. */
687 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
688 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
689 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
692 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
694 * Not all pre-v6 cores implemented this WFI, so this is slightly
697 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
698 .access
= PL1_W
, .type
= ARM_CP_WFI
},
701 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
703 * Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
704 * is UNPREDICTABLE; we choose to NOP as most implementations do).
706 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
707 .access
= PL1_W
, .type
= ARM_CP_WFI
},
709 * L1 cache lockdown. Not architectural in v6 and earlier but in practice
710 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
711 * OMAPCP will override this space.
713 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
714 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
716 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
717 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
719 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
720 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
721 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
724 * We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
725 * implementing it as RAZ means the "debug architecture version" bits
726 * will read as a reserved value, which should cause Linux to not try
727 * to use the debug hardware.
729 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
730 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
732 * MMU TLB control. Note that the wildcarding means we cover not just
733 * the unified TLB ops but also the dside/iside/inner-shareable variants.
735 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
736 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
737 .type
= ARM_CP_NO_RAW
},
738 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
739 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
740 .type
= ARM_CP_NO_RAW
},
741 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
742 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
743 .type
= ARM_CP_NO_RAW
},
744 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
745 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
746 .type
= ARM_CP_NO_RAW
},
747 { .name
= "PRRR", .cp
= 15, .crn
= 10, .crm
= 2,
748 .opc1
= 0, .opc2
= 0, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
749 { .name
= "NMRR", .cp
= 15, .crn
= 10, .crm
= 2,
750 .opc1
= 0, .opc2
= 1, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
753 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
758 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
759 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
761 * ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
762 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
763 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
765 if (cpu_isar_feature(aa32_vfp_simd
, env_archcpu(env
))) {
766 /* VFP coprocessor: cp10 & cp11 [23:20] */
767 mask
|= R_CPACR_ASEDIS_MASK
|
768 R_CPACR_D32DIS_MASK
|
772 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
773 /* ASEDIS [31] bit is RAO/WI */
774 value
|= R_CPACR_ASEDIS_MASK
;
778 * VFPv3 and upwards with NEON implement 32 double precision
779 * registers (D0-D31).
781 if (!cpu_isar_feature(aa32_simd_r32
, env_archcpu(env
))) {
782 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
783 value
|= R_CPACR_D32DIS_MASK
;
790 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
791 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
793 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
794 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
795 mask
= R_CPACR_CP11_MASK
| R_CPACR_CP10_MASK
;
796 value
= (value
& ~mask
) | (env
->cp15
.cpacr_el1
& mask
);
799 env
->cp15
.cpacr_el1
= value
;
802 static uint64_t cpacr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
805 * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR.CP10
806 * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00.
808 uint64_t value
= env
->cp15
.cpacr_el1
;
810 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
811 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
812 value
= ~(R_CPACR_CP11_MASK
| R_CPACR_CP10_MASK
);
818 static void cpacr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
821 * Call cpacr_write() so that we reset with the correct RAO bits set
822 * for our CPU features.
824 cpacr_write(env
, ri
, 0);
827 static CPAccessResult
cpacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
830 if (arm_feature(env
, ARM_FEATURE_V8
)) {
831 /* Check if CPACR accesses are to be trapped to EL2 */
832 if (arm_current_el(env
) == 1 && arm_is_el2_enabled(env
) &&
833 FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TCPAC
)) {
834 return CP_ACCESS_TRAP_EL2
;
835 /* Check if CPACR accesses are to be trapped to EL3 */
836 } else if (arm_current_el(env
) < 3 &&
837 FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TCPAC
)) {
838 return CP_ACCESS_TRAP_EL3
;
845 static CPAccessResult
cptr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
848 /* Check if CPTR accesses are set to trap to EL3 */
849 if (arm_current_el(env
) == 2 &&
850 FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TCPAC
)) {
851 return CP_ACCESS_TRAP_EL3
;
857 static const ARMCPRegInfo v6_cp_reginfo
[] = {
858 /* prefetch by MVA in v6, NOP in v7 */
859 { .name
= "MVA_prefetch",
860 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
861 .access
= PL1_W
, .type
= ARM_CP_NOP
},
863 * We need to break the TB after ISB to execute self-modifying code
864 * correctly and also to take any pending interrupts immediately.
865 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
867 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
868 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
, .writefn
= arm_cp_write_ignore
},
869 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
870 .access
= PL0_W
, .type
= ARM_CP_NOP
},
871 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
872 .access
= PL0_W
, .type
= ARM_CP_NOP
},
873 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
874 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
875 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ifar_s
),
876 offsetof(CPUARMState
, cp15
.ifar_ns
) },
879 * Watchpoint Fault Address Register : should actually only be present
880 * for 1136, 1176, 11MPCore.
882 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
883 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
884 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
885 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2, .accessfn
= cpacr_access
,
886 .fgt
= FGT_CPACR_EL1
,
887 .nv2_redirect_offset
= 0x100 | NV2_REDIR_NV1
,
888 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.cpacr_el1
),
889 .resetfn
= cpacr_reset
, .writefn
= cpacr_write
, .readfn
= cpacr_read
},
892 typedef struct pm_event
{
893 uint16_t number
; /* PMEVTYPER.evtCount is 16 bits wide */
894 /* If the event is supported on this CPU (used to generate PMCEID[01]) */
895 bool (*supported
)(CPUARMState
*);
897 * Retrieve the current count of the underlying event. The programmed
898 * counters hold a difference from the return value from this function
900 uint64_t (*get_count
)(CPUARMState
*);
902 * Return how many nanoseconds it will take (at a minimum) for count events
903 * to occur. A negative value indicates the counter will never overflow, or
904 * that the counter has otherwise arranged for the overflow bit to be set
905 * and the PMU interrupt to be raised on overflow.
907 int64_t (*ns_per_count
)(uint64_t);
910 static bool event_always_supported(CPUARMState
*env
)
915 static uint64_t swinc_get_count(CPUARMState
*env
)
918 * SW_INCR events are written directly to the pmevcntr's by writes to
919 * PMSWINC, so there is no underlying count maintained by the PMU itself
924 static int64_t swinc_ns_per(uint64_t ignored
)
930 * Return the underlying cycle count for the PMU cycle counters. If we're in
931 * usermode, simply return 0.
933 static uint64_t cycles_get_count(CPUARMState
*env
)
935 #ifndef CONFIG_USER_ONLY
936 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
937 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
939 return cpu_get_host_ticks();
943 #ifndef CONFIG_USER_ONLY
944 static int64_t cycles_ns_per(uint64_t cycles
)
946 return (ARM_CPU_FREQ
/ NANOSECONDS_PER_SECOND
) * cycles
;
949 static bool instructions_supported(CPUARMState
*env
)
951 /* Precise instruction counting */
952 return icount_enabled() == ICOUNT_PRECISE
;
955 static uint64_t instructions_get_count(CPUARMState
*env
)
957 assert(icount_enabled() == ICOUNT_PRECISE
);
958 return (uint64_t)icount_get_raw();
961 static int64_t instructions_ns_per(uint64_t icount
)
963 assert(icount_enabled() == ICOUNT_PRECISE
);
964 return icount_to_ns((int64_t)icount
);
968 static bool pmuv3p1_events_supported(CPUARMState
*env
)
970 /* For events which are supported in any v8.1 PMU */
971 return cpu_isar_feature(any_pmuv3p1
, env_archcpu(env
));
974 static bool pmuv3p4_events_supported(CPUARMState
*env
)
976 /* For events which are supported in any v8.1 PMU */
977 return cpu_isar_feature(any_pmuv3p4
, env_archcpu(env
));
980 static uint64_t zero_event_get_count(CPUARMState
*env
)
982 /* For events which on QEMU never fire, so their count is always zero */
986 static int64_t zero_event_ns_per(uint64_t cycles
)
988 /* An event which never fires can never overflow */
992 static const pm_event pm_events
[] = {
993 { .number
= 0x000, /* SW_INCR */
994 .supported
= event_always_supported
,
995 .get_count
= swinc_get_count
,
996 .ns_per_count
= swinc_ns_per
,
998 #ifndef CONFIG_USER_ONLY
999 { .number
= 0x008, /* INST_RETIRED, Instruction architecturally executed */
1000 .supported
= instructions_supported
,
1001 .get_count
= instructions_get_count
,
1002 .ns_per_count
= instructions_ns_per
,
1004 { .number
= 0x011, /* CPU_CYCLES, Cycle */
1005 .supported
= event_always_supported
,
1006 .get_count
= cycles_get_count
,
1007 .ns_per_count
= cycles_ns_per
,
1010 { .number
= 0x023, /* STALL_FRONTEND */
1011 .supported
= pmuv3p1_events_supported
,
1012 .get_count
= zero_event_get_count
,
1013 .ns_per_count
= zero_event_ns_per
,
1015 { .number
= 0x024, /* STALL_BACKEND */
1016 .supported
= pmuv3p1_events_supported
,
1017 .get_count
= zero_event_get_count
,
1018 .ns_per_count
= zero_event_ns_per
,
1020 { .number
= 0x03c, /* STALL */
1021 .supported
= pmuv3p4_events_supported
,
1022 .get_count
= zero_event_get_count
,
1023 .ns_per_count
= zero_event_ns_per
,
1028 * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of
1029 * events (i.e. the statistical profiling extension), this implementation
1030 * should first be updated to something sparse instead of the current
1031 * supported_event_map[] array.
1033 #define MAX_EVENT_ID 0x3c
1034 #define UNSUPPORTED_EVENT UINT16_MAX
1035 static uint16_t supported_event_map
[MAX_EVENT_ID
+ 1];
1038 * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a map
1039 * of ARM event numbers to indices in our pm_events array.
1041 * Note: Events in the 0x40XX range are not currently supported.
1043 void pmu_init(ARMCPU
*cpu
)
1048 * Empty supported_event_map and cpu->pmceid[01] before adding supported
1051 for (i
= 0; i
< ARRAY_SIZE(supported_event_map
); i
++) {
1052 supported_event_map
[i
] = UNSUPPORTED_EVENT
;
1057 for (i
= 0; i
< ARRAY_SIZE(pm_events
); i
++) {
1058 const pm_event
*cnt
= &pm_events
[i
];
1059 assert(cnt
->number
<= MAX_EVENT_ID
);
1060 /* We do not currently support events in the 0x40xx range */
1061 assert(cnt
->number
<= 0x3f);
1063 if (cnt
->supported(&cpu
->env
)) {
1064 supported_event_map
[cnt
->number
] = i
;
1065 uint64_t event_mask
= 1ULL << (cnt
->number
& 0x1f);
1066 if (cnt
->number
& 0x20) {
1067 cpu
->pmceid1
|= event_mask
;
1069 cpu
->pmceid0
|= event_mask
;
1076 * Check at runtime whether a PMU event is supported for the current machine
1078 static bool event_supported(uint16_t number
)
1080 if (number
> MAX_EVENT_ID
) {
1083 return supported_event_map
[number
] != UNSUPPORTED_EVENT
;
1086 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1090 * Performance monitor registers user accessibility is controlled
1091 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
1092 * trapping to EL2 or EL3 for other accesses.
1094 int el
= arm_current_el(env
);
1095 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
1097 if (el
== 0 && !(env
->cp15
.c9_pmuserenr
& 1)) {
1098 return CP_ACCESS_TRAP
;
1100 if (el
< 2 && (mdcr_el2
& MDCR_TPM
)) {
1101 return CP_ACCESS_TRAP_EL2
;
1103 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
1104 return CP_ACCESS_TRAP_EL3
;
1107 return CP_ACCESS_OK
;
1110 static CPAccessResult
pmreg_access_xevcntr(CPUARMState
*env
,
1111 const ARMCPRegInfo
*ri
,
1114 /* ER: event counter read trap control */
1115 if (arm_feature(env
, ARM_FEATURE_V8
)
1116 && arm_current_el(env
) == 0
1117 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0
1119 return CP_ACCESS_OK
;
1122 return pmreg_access(env
, ri
, isread
);
1125 static CPAccessResult
pmreg_access_swinc(CPUARMState
*env
,
1126 const ARMCPRegInfo
*ri
,
1129 /* SW: software increment write trap control */
1130 if (arm_feature(env
, ARM_FEATURE_V8
)
1131 && arm_current_el(env
) == 0
1132 && (env
->cp15
.c9_pmuserenr
& (1 << 1)) != 0
1134 return CP_ACCESS_OK
;
1137 return pmreg_access(env
, ri
, isread
);
1140 static CPAccessResult
pmreg_access_selr(CPUARMState
*env
,
1141 const ARMCPRegInfo
*ri
,
1144 /* ER: event counter read trap control */
1145 if (arm_feature(env
, ARM_FEATURE_V8
)
1146 && arm_current_el(env
) == 0
1147 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0) {
1148 return CP_ACCESS_OK
;
1151 return pmreg_access(env
, ri
, isread
);
1154 static CPAccessResult
pmreg_access_ccntr(CPUARMState
*env
,
1155 const ARMCPRegInfo
*ri
,
1158 /* CR: cycle counter read trap control */
1159 if (arm_feature(env
, ARM_FEATURE_V8
)
1160 && arm_current_el(env
) == 0
1161 && (env
->cp15
.c9_pmuserenr
& (1 << 2)) != 0
1163 return CP_ACCESS_OK
;
1166 return pmreg_access(env
, ri
, isread
);
1170 * Bits in MDCR_EL2 and MDCR_EL3 which pmu_counter_enabled() looks at.
1171 * We use these to decide whether we need to wrap a write to MDCR_EL2
1172 * or MDCR_EL3 in pmu_op_start()/pmu_op_finish() calls.
1174 #define MDCR_EL2_PMU_ENABLE_BITS \
1175 (MDCR_HPME | MDCR_HPMD | MDCR_HPMN | MDCR_HCCD | MDCR_HLP)
1176 #define MDCR_EL3_PMU_ENABLE_BITS (MDCR_SPME | MDCR_SCCD)
1179 * Returns true if the counter (pass 31 for PMCCNTR) should count events using
1180 * the current EL, security state, and register configuration.
1182 static bool pmu_counter_enabled(CPUARMState
*env
, uint8_t counter
)
1185 bool e
, p
, u
, nsk
, nsu
, nsh
, m
;
1186 bool enabled
, prohibited
= false, filtered
;
1187 bool secure
= arm_is_secure(env
);
1188 int el
= arm_current_el(env
);
1189 uint64_t mdcr_el2
= arm_mdcr_el2_eff(env
);
1190 uint8_t hpmn
= mdcr_el2
& MDCR_HPMN
;
1192 if (!arm_feature(env
, ARM_FEATURE_PMU
)) {
1196 if (!arm_feature(env
, ARM_FEATURE_EL2
) ||
1197 (counter
< hpmn
|| counter
== 31)) {
1198 e
= env
->cp15
.c9_pmcr
& PMCRE
;
1200 e
= mdcr_el2
& MDCR_HPME
;
1202 enabled
= e
&& (env
->cp15
.c9_pmcnten
& (1 << counter
));
1204 /* Is event counting prohibited? */
1205 if (el
== 2 && (counter
< hpmn
|| counter
== 31)) {
1206 prohibited
= mdcr_el2
& MDCR_HPMD
;
1209 prohibited
= prohibited
|| !(env
->cp15
.mdcr_el3
& MDCR_SPME
);
1212 if (counter
== 31) {
1214 * The cycle counter defaults to running. PMCR.DP says "disable
1215 * the cycle counter when event counting is prohibited".
1216 * Some MDCR bits disable the cycle counter specifically.
1218 prohibited
= prohibited
&& env
->cp15
.c9_pmcr
& PMCRDP
;
1219 if (cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1221 prohibited
= prohibited
|| (env
->cp15
.mdcr_el3
& MDCR_SCCD
);
1224 prohibited
= prohibited
|| (mdcr_el2
& MDCR_HCCD
);
1229 if (counter
== 31) {
1230 filter
= env
->cp15
.pmccfiltr_el0
;
1232 filter
= env
->cp15
.c14_pmevtyper
[counter
];
1235 p
= filter
& PMXEVTYPER_P
;
1236 u
= filter
& PMXEVTYPER_U
;
1237 nsk
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSK
);
1238 nsu
= arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_NSU
);
1239 nsh
= arm_feature(env
, ARM_FEATURE_EL2
) && (filter
& PMXEVTYPER_NSH
);
1240 m
= arm_el_is_aa64(env
, 1) &&
1241 arm_feature(env
, ARM_FEATURE_EL3
) && (filter
& PMXEVTYPER_M
);
1244 filtered
= secure
? u
: u
!= nsu
;
1245 } else if (el
== 1) {
1246 filtered
= secure
? p
: p
!= nsk
;
1247 } else if (el
== 2) {
1253 if (counter
!= 31) {
1255 * If not checking PMCCNTR, ensure the counter is setup to an event we
1258 uint16_t event
= filter
& PMXEVTYPER_EVTCOUNT
;
1259 if (!event_supported(event
)) {
1264 return enabled
&& !prohibited
&& !filtered
;
1267 static void pmu_update_irq(CPUARMState
*env
)
1269 ARMCPU
*cpu
= env_archcpu(env
);
1270 qemu_set_irq(cpu
->pmu_interrupt
, (env
->cp15
.c9_pmcr
& PMCRE
) &&
1271 (env
->cp15
.c9_pminten
& env
->cp15
.c9_pmovsr
));
1274 static bool pmccntr_clockdiv_enabled(CPUARMState
*env
)
1277 * Return true if the clock divider is enabled and the cycle counter
1278 * is supposed to tick only once every 64 clock cycles. This is
1279 * controlled by PMCR.D, but if PMCR.LC is set to enable the long
1280 * (64-bit) cycle counter PMCR.D has no effect.
1282 return (env
->cp15
.c9_pmcr
& (PMCRD
| PMCRLC
)) == PMCRD
;
1285 static bool pmevcntr_is_64_bit(CPUARMState
*env
, int counter
)
1287 /* Return true if the specified event counter is configured to be 64 bit */
1289 /* This isn't intended to be used with the cycle counter */
1290 assert(counter
< 31);
1292 if (!cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1296 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
1298 * MDCR_EL2.HLP still applies even when EL2 is disabled in the
1299 * current security state, so we don't use arm_mdcr_el2_eff() here.
1301 bool hlp
= env
->cp15
.mdcr_el2
& MDCR_HLP
;
1302 int hpmn
= env
->cp15
.mdcr_el2
& MDCR_HPMN
;
1304 if (counter
>= hpmn
) {
1308 return env
->cp15
.c9_pmcr
& PMCRLP
;
1312 * Ensure c15_ccnt is the guest-visible count so that operations such as
1313 * enabling/disabling the counter or filtering, modifying the count itself,
1314 * etc. can be done logically. This is essentially a no-op if the counter is
1315 * not enabled at the time of the call.
1317 static void pmccntr_op_start(CPUARMState
*env
)
1319 uint64_t cycles
= cycles_get_count(env
);
1321 if (pmu_counter_enabled(env
, 31)) {
1322 uint64_t eff_cycles
= cycles
;
1323 if (pmccntr_clockdiv_enabled(env
)) {
1327 uint64_t new_pmccntr
= eff_cycles
- env
->cp15
.c15_ccnt_delta
;
1329 uint64_t overflow_mask
= env
->cp15
.c9_pmcr
& PMCRLC
? \
1330 1ull << 63 : 1ull << 31;
1331 if (env
->cp15
.c15_ccnt
& ~new_pmccntr
& overflow_mask
) {
1332 env
->cp15
.c9_pmovsr
|= (1ULL << 31);
1333 pmu_update_irq(env
);
1336 env
->cp15
.c15_ccnt
= new_pmccntr
;
1338 env
->cp15
.c15_ccnt_delta
= cycles
;
1342 * If PMCCNTR is enabled, recalculate the delta between the clock and the
1343 * guest-visible count. A call to pmccntr_op_finish should follow every call to
1346 static void pmccntr_op_finish(CPUARMState
*env
)
1348 if (pmu_counter_enabled(env
, 31)) {
1349 #ifndef CONFIG_USER_ONLY
1350 /* Calculate when the counter will next overflow */
1351 uint64_t remaining_cycles
= -env
->cp15
.c15_ccnt
;
1352 if (!(env
->cp15
.c9_pmcr
& PMCRLC
)) {
1353 remaining_cycles
= (uint32_t)remaining_cycles
;
1355 int64_t overflow_in
= cycles_ns_per(remaining_cycles
);
1357 if (overflow_in
> 0) {
1358 int64_t overflow_at
;
1360 if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1361 overflow_in
, &overflow_at
)) {
1362 ARMCPU
*cpu
= env_archcpu(env
);
1363 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1368 uint64_t prev_cycles
= env
->cp15
.c15_ccnt_delta
;
1369 if (pmccntr_clockdiv_enabled(env
)) {
1372 env
->cp15
.c15_ccnt_delta
= prev_cycles
- env
->cp15
.c15_ccnt
;
1376 static void pmevcntr_op_start(CPUARMState
*env
, uint8_t counter
)
1379 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1381 if (event_supported(event
)) {
1382 uint16_t event_idx
= supported_event_map
[event
];
1383 count
= pm_events
[event_idx
].get_count(env
);
1386 if (pmu_counter_enabled(env
, counter
)) {
1387 uint64_t new_pmevcntr
= count
- env
->cp15
.c14_pmevcntr_delta
[counter
];
1388 uint64_t overflow_mask
= pmevcntr_is_64_bit(env
, counter
) ?
1389 1ULL << 63 : 1ULL << 31;
1391 if (env
->cp15
.c14_pmevcntr
[counter
] & ~new_pmevcntr
& overflow_mask
) {
1392 env
->cp15
.c9_pmovsr
|= (1 << counter
);
1393 pmu_update_irq(env
);
1395 env
->cp15
.c14_pmevcntr
[counter
] = new_pmevcntr
;
1397 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1400 static void pmevcntr_op_finish(CPUARMState
*env
, uint8_t counter
)
1402 if (pmu_counter_enabled(env
, counter
)) {
1403 #ifndef CONFIG_USER_ONLY
1404 uint16_t event
= env
->cp15
.c14_pmevtyper
[counter
] & PMXEVTYPER_EVTCOUNT
;
1405 uint16_t event_idx
= supported_event_map
[event
];
1406 uint64_t delta
= -(env
->cp15
.c14_pmevcntr
[counter
] + 1);
1407 int64_t overflow_in
;
1409 if (!pmevcntr_is_64_bit(env
, counter
)) {
1410 delta
= (uint32_t)delta
;
1412 overflow_in
= pm_events
[event_idx
].ns_per_count(delta
);
1414 if (overflow_in
> 0) {
1415 int64_t overflow_at
;
1417 if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1418 overflow_in
, &overflow_at
)) {
1419 ARMCPU
*cpu
= env_archcpu(env
);
1420 timer_mod_anticipate_ns(cpu
->pmu_timer
, overflow_at
);
1425 env
->cp15
.c14_pmevcntr_delta
[counter
] -=
1426 env
->cp15
.c14_pmevcntr
[counter
];
1430 void pmu_op_start(CPUARMState
*env
)
1433 pmccntr_op_start(env
);
1434 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1435 pmevcntr_op_start(env
, i
);
1439 void pmu_op_finish(CPUARMState
*env
)
1442 pmccntr_op_finish(env
);
1443 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1444 pmevcntr_op_finish(env
, i
);
1448 void pmu_pre_el_change(ARMCPU
*cpu
, void *ignored
)
1450 pmu_op_start(&cpu
->env
);
1453 void pmu_post_el_change(ARMCPU
*cpu
, void *ignored
)
1455 pmu_op_finish(&cpu
->env
);
1458 void arm_pmu_timer_cb(void *opaque
)
1460 ARMCPU
*cpu
= opaque
;
1463 * Update all the counter values based on the current underlying counts,
1464 * triggering interrupts to be raised, if necessary. pmu_op_finish() also
1465 * has the effect of setting the cpu->pmu_timer to the next earliest time a
1466 * counter may expire.
1468 pmu_op_start(&cpu
->env
);
1469 pmu_op_finish(&cpu
->env
);
1472 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1477 if (value
& PMCRC
) {
1478 /* The counter has been reset */
1479 env
->cp15
.c15_ccnt
= 0;
1482 if (value
& PMCRP
) {
1484 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1485 env
->cp15
.c14_pmevcntr
[i
] = 0;
1489 env
->cp15
.c9_pmcr
&= ~PMCR_WRITABLE_MASK
;
1490 env
->cp15
.c9_pmcr
|= (value
& PMCR_WRITABLE_MASK
);
1495 static uint64_t pmcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1497 uint64_t pmcr
= env
->cp15
.c9_pmcr
;
1500 * If EL2 is implemented and enabled for the current security state, reads
1501 * of PMCR.N from EL1 or EL0 return the value of MDCR_EL2.HPMN or HDCR.HPMN.
1503 if (arm_current_el(env
) <= 1 && arm_is_el2_enabled(env
)) {
1504 pmcr
&= ~PMCRN_MASK
;
1505 pmcr
|= (env
->cp15
.mdcr_el2
& MDCR_HPMN
) << PMCRN_SHIFT
;
1511 static void pmswinc_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1515 uint64_t overflow_mask
, new_pmswinc
;
1517 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
1518 /* Increment a counter's count iff: */
1519 if ((value
& (1 << i
)) && /* counter's bit is set */
1520 /* counter is enabled and not filtered */
1521 pmu_counter_enabled(env
, i
) &&
1522 /* counter is SW_INCR */
1523 (env
->cp15
.c14_pmevtyper
[i
] & PMXEVTYPER_EVTCOUNT
) == 0x0) {
1524 pmevcntr_op_start(env
, i
);
1527 * Detect if this write causes an overflow since we can't predict
1528 * PMSWINC overflows like we can for other events
1530 new_pmswinc
= env
->cp15
.c14_pmevcntr
[i
] + 1;
1532 overflow_mask
= pmevcntr_is_64_bit(env
, i
) ?
1533 1ULL << 63 : 1ULL << 31;
1535 if (env
->cp15
.c14_pmevcntr
[i
] & ~new_pmswinc
& overflow_mask
) {
1536 env
->cp15
.c9_pmovsr
|= (1 << i
);
1537 pmu_update_irq(env
);
1540 env
->cp15
.c14_pmevcntr
[i
] = new_pmswinc
;
1542 pmevcntr_op_finish(env
, i
);
1547 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1550 pmccntr_op_start(env
);
1551 ret
= env
->cp15
.c15_ccnt
;
1552 pmccntr_op_finish(env
);
1556 static void pmselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1560 * The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1561 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1562 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1565 env
->cp15
.c9_pmselr
= value
& 0x1f;
1568 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1571 pmccntr_op_start(env
);
1572 env
->cp15
.c15_ccnt
= value
;
1573 pmccntr_op_finish(env
);
1576 static void pmccntr_write32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1579 uint64_t cur_val
= pmccntr_read(env
, NULL
);
1581 pmccntr_write(env
, ri
, deposit64(cur_val
, 0, 32, value
));
1584 static void pmccfiltr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1587 pmccntr_op_start(env
);
1588 env
->cp15
.pmccfiltr_el0
= value
& PMCCFILTR_EL0
;
1589 pmccntr_op_finish(env
);
1592 static void pmccfiltr_write_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1595 pmccntr_op_start(env
);
1596 /* M is not accessible from AArch32 */
1597 env
->cp15
.pmccfiltr_el0
= (env
->cp15
.pmccfiltr_el0
& PMCCFILTR_M
) |
1598 (value
& PMCCFILTR
);
1599 pmccntr_op_finish(env
);
1602 static uint64_t pmccfiltr_read_a32(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1604 /* M is not visible in AArch32 */
1605 return env
->cp15
.pmccfiltr_el0
& PMCCFILTR
;
1608 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1612 value
&= pmu_counter_mask(env
);
1613 env
->cp15
.c9_pmcnten
|= value
;
1617 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1621 value
&= pmu_counter_mask(env
);
1622 env
->cp15
.c9_pmcnten
&= ~value
;
1626 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1629 value
&= pmu_counter_mask(env
);
1630 env
->cp15
.c9_pmovsr
&= ~value
;
1631 pmu_update_irq(env
);
1634 static void pmovsset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1637 value
&= pmu_counter_mask(env
);
1638 env
->cp15
.c9_pmovsr
|= value
;
1639 pmu_update_irq(env
);
1642 static void pmevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1643 uint64_t value
, const uint8_t counter
)
1645 if (counter
== 31) {
1646 pmccfiltr_write(env
, ri
, value
);
1647 } else if (counter
< pmu_num_counters(env
)) {
1648 pmevcntr_op_start(env
, counter
);
1651 * If this counter's event type is changing, store the current
1652 * underlying count for the new type in c14_pmevcntr_delta[counter] so
1653 * pmevcntr_op_finish has the correct baseline when it converts back to
1656 uint16_t old_event
= env
->cp15
.c14_pmevtyper
[counter
] &
1657 PMXEVTYPER_EVTCOUNT
;
1658 uint16_t new_event
= value
& PMXEVTYPER_EVTCOUNT
;
1659 if (old_event
!= new_event
) {
1661 if (event_supported(new_event
)) {
1662 uint16_t event_idx
= supported_event_map
[new_event
];
1663 count
= pm_events
[event_idx
].get_count(env
);
1665 env
->cp15
.c14_pmevcntr_delta
[counter
] = count
;
1668 env
->cp15
.c14_pmevtyper
[counter
] = value
& PMXEVTYPER_MASK
;
1669 pmevcntr_op_finish(env
, counter
);
1672 * Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1673 * PMSELR value is equal to or greater than the number of implemented
1674 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1678 static uint64_t pmevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1679 const uint8_t counter
)
1681 if (counter
== 31) {
1682 return env
->cp15
.pmccfiltr_el0
;
1683 } else if (counter
< pmu_num_counters(env
)) {
1684 return env
->cp15
.c14_pmevtyper
[counter
];
1687 * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1688 * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write().
1694 static void pmevtyper_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1697 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1698 pmevtyper_write(env
, ri
, value
, counter
);
1701 static void pmevtyper_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1704 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1705 env
->cp15
.c14_pmevtyper
[counter
] = value
;
1708 * pmevtyper_rawwrite is called between a pair of pmu_op_start and
1709 * pmu_op_finish calls when loading saved state for a migration. Because
1710 * we're potentially updating the type of event here, the value written to
1711 * c14_pmevcntr_delta by the preceding pmu_op_start call may be for a
1712 * different counter type. Therefore, we need to set this value to the
1713 * current count for the counter type we're writing so that pmu_op_finish
1714 * has the correct count for its calculation.
1716 uint16_t event
= value
& PMXEVTYPER_EVTCOUNT
;
1717 if (event_supported(event
)) {
1718 uint16_t event_idx
= supported_event_map
[event
];
1719 env
->cp15
.c14_pmevcntr_delta
[counter
] =
1720 pm_events
[event_idx
].get_count(env
);
1724 static uint64_t pmevtyper_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1726 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1727 return pmevtyper_read(env
, ri
, counter
);
1730 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1733 pmevtyper_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1736 static uint64_t pmxevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1738 return pmevtyper_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1741 static void pmevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1742 uint64_t value
, uint8_t counter
)
1744 if (!cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1745 /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */
1746 value
&= MAKE_64BIT_MASK(0, 32);
1748 if (counter
< pmu_num_counters(env
)) {
1749 pmevcntr_op_start(env
, counter
);
1750 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1751 pmevcntr_op_finish(env
, counter
);
1754 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1755 * are CONSTRAINED UNPREDICTABLE.
1759 static uint64_t pmevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1762 if (counter
< pmu_num_counters(env
)) {
1764 pmevcntr_op_start(env
, counter
);
1765 ret
= env
->cp15
.c14_pmevcntr
[counter
];
1766 pmevcntr_op_finish(env
, counter
);
1767 if (!cpu_isar_feature(any_pmuv3p5
, env_archcpu(env
))) {
1768 /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */
1769 ret
&= MAKE_64BIT_MASK(0, 32);
1774 * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
1775 * are CONSTRAINED UNPREDICTABLE.
1781 static void pmevcntr_writefn(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1784 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1785 pmevcntr_write(env
, ri
, value
, counter
);
1788 static uint64_t pmevcntr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1790 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1791 return pmevcntr_read(env
, ri
, counter
);
1794 static void pmevcntr_rawwrite(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1797 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1798 assert(counter
< pmu_num_counters(env
));
1799 env
->cp15
.c14_pmevcntr
[counter
] = value
;
1800 pmevcntr_write(env
, ri
, value
, counter
);
1803 static uint64_t pmevcntr_rawread(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1805 uint8_t counter
= ((ri
->crm
& 3) << 3) | (ri
->opc2
& 7);
1806 assert(counter
< pmu_num_counters(env
));
1807 return env
->cp15
.c14_pmevcntr
[counter
];
1810 static void pmxevcntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1813 pmevcntr_write(env
, ri
, value
, env
->cp15
.c9_pmselr
& 31);
1816 static uint64_t pmxevcntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1818 return pmevcntr_read(env
, ri
, env
->cp15
.c9_pmselr
& 31);
1821 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1824 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1825 env
->cp15
.c9_pmuserenr
= value
& 0xf;
1827 env
->cp15
.c9_pmuserenr
= value
& 1;
1831 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1834 /* We have no event counters so only the C bit can be changed */
1835 value
&= pmu_counter_mask(env
);
1836 env
->cp15
.c9_pminten
|= value
;
1837 pmu_update_irq(env
);
1840 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1843 value
&= pmu_counter_mask(env
);
1844 env
->cp15
.c9_pminten
&= ~value
;
1845 pmu_update_irq(env
);
1848 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1852 * Note that even though the AArch64 view of this register has bits
1853 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
1854 * architectural requirements for bits which are RES0 only in some
1855 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
1856 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
1858 raw_write(env
, ri
, value
& ~0x1FULL
);
1861 static void scr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1863 /* Begin with base v8.0 state. */
1864 uint64_t valid_mask
= 0x3fff;
1865 ARMCPU
*cpu
= env_archcpu(env
);
1869 * Because SCR_EL3 is the "real" cpreg and SCR is the alias, reset always
1870 * passes the reginfo for SCR_EL3, which has type ARM_CP_STATE_AA64.
1871 * Instead, choose the format based on the mode of EL3.
1873 if (arm_el_is_aa64(env
, 3)) {
1874 value
|= SCR_FW
| SCR_AW
; /* RES1 */
1875 valid_mask
&= ~SCR_NET
; /* RES0 */
1877 if (!cpu_isar_feature(aa64_aa32_el1
, cpu
) &&
1878 !cpu_isar_feature(aa64_aa32_el2
, cpu
)) {
1879 value
|= SCR_RW
; /* RAO/WI */
1881 if (cpu_isar_feature(aa64_ras
, cpu
)) {
1882 valid_mask
|= SCR_TERR
;
1884 if (cpu_isar_feature(aa64_lor
, cpu
)) {
1885 valid_mask
|= SCR_TLOR
;
1887 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
1888 valid_mask
|= SCR_API
| SCR_APK
;
1890 if (cpu_isar_feature(aa64_sel2
, cpu
)) {
1891 valid_mask
|= SCR_EEL2
;
1892 } else if (cpu_isar_feature(aa64_rme
, cpu
)) {
1893 /* With RME and without SEL2, NS is RES1 (R_GSWWH, I_DJJQJ). */
1896 if (cpu_isar_feature(aa64_mte
, cpu
)) {
1897 valid_mask
|= SCR_ATA
;
1899 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
1900 valid_mask
|= SCR_ENSCXT
;
1902 if (cpu_isar_feature(aa64_doublefault
, cpu
)) {
1903 valid_mask
|= SCR_EASE
| SCR_NMEA
;
1905 if (cpu_isar_feature(aa64_sme
, cpu
)) {
1906 valid_mask
|= SCR_ENTP2
;
1908 if (cpu_isar_feature(aa64_hcx
, cpu
)) {
1909 valid_mask
|= SCR_HXEN
;
1911 if (cpu_isar_feature(aa64_fgt
, cpu
)) {
1912 valid_mask
|= SCR_FGTEN
;
1914 if (cpu_isar_feature(aa64_rme
, cpu
)) {
1915 valid_mask
|= SCR_NSE
| SCR_GPF
;
1918 valid_mask
&= ~(SCR_RW
| SCR_ST
);
1919 if (cpu_isar_feature(aa32_ras
, cpu
)) {
1920 valid_mask
|= SCR_TERR
;
1924 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1925 valid_mask
&= ~SCR_HCE
;
1928 * On ARMv7, SMD (or SCD as it is called in v7) is only
1929 * supported if EL2 exists. The bit is UNK/SBZP when
1930 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
1931 * when EL2 is unavailable.
1932 * On ARMv8, this bit is always available.
1934 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1935 !arm_feature(env
, ARM_FEATURE_V8
)) {
1936 valid_mask
&= ~SCR_SMD
;
1940 /* Clear all-context RES0 bits. */
1941 value
&= valid_mask
;
1942 changed
= env
->cp15
.scr_el3
^ value
;
1943 env
->cp15
.scr_el3
= value
;
1946 * If SCR_EL3.{NS,NSE} changes, i.e. change of security state,
1947 * we must invalidate all TLBs below EL3.
1949 if (changed
& (SCR_NS
| SCR_NSE
)) {
1950 tlb_flush_by_mmuidx(env_cpu(env
), (ARMMMUIdxBit_E10_0
|
1951 ARMMMUIdxBit_E20_0
|
1952 ARMMMUIdxBit_E10_1
|
1953 ARMMMUIdxBit_E20_2
|
1954 ARMMMUIdxBit_E10_1_PAN
|
1955 ARMMMUIdxBit_E20_2_PAN
|
1960 static void scr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1963 * scr_write will set the RES1 bits on an AArch64-only CPU.
1964 * The reset value will be 0x30 on an AArch64-only CPU and 0 otherwise.
1966 scr_write(env
, ri
, 0);
1969 static CPAccessResult
access_tid4(CPUARMState
*env
,
1970 const ARMCPRegInfo
*ri
,
1973 if (arm_current_el(env
) == 1 &&
1974 (arm_hcr_el2_eff(env
) & (HCR_TID2
| HCR_TID4
))) {
1975 return CP_ACCESS_TRAP_EL2
;
1978 return CP_ACCESS_OK
;
1981 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1983 ARMCPU
*cpu
= env_archcpu(env
);
1986 * Acquire the CSSELR index from the bank corresponding to the CCSIDR
1989 uint32_t index
= A32_BANKED_REG_GET(env
, csselr
,
1990 ri
->secure
& ARM_CP_SECSTATE_S
);
1992 return cpu
->ccsidr
[index
];
1995 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1998 raw_write(env
, ri
, value
& 0xf);
2001 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2003 CPUState
*cs
= env_cpu(env
);
2004 bool el1
= arm_current_el(env
) == 1;
2005 uint64_t hcr_el2
= el1
? arm_hcr_el2_eff(env
) : 0;
2008 if (hcr_el2
& HCR_IMO
) {
2009 if (cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) {
2013 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
2018 if (hcr_el2
& HCR_FMO
) {
2019 if (cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) {
2023 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
2028 if (hcr_el2
& HCR_AMO
) {
2029 if (cs
->interrupt_request
& CPU_INTERRUPT_VSERR
) {
2037 static CPAccessResult
access_aa64_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2040 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID1
)) {
2041 return CP_ACCESS_TRAP_EL2
;
2044 return CP_ACCESS_OK
;
2047 static CPAccessResult
access_aa32_tid1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2050 if (arm_feature(env
, ARM_FEATURE_V8
)) {
2051 return access_aa64_tid1(env
, ri
, isread
);
2054 return CP_ACCESS_OK
;
2057 static const ARMCPRegInfo v7_cp_reginfo
[] = {
2058 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
2059 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
2060 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2062 * Performance monitors are implementation defined in v7,
2063 * but with an ARM recommended set of registers, which we
2066 * Performance registers fall into three categories:
2067 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
2068 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
2069 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
2070 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
2071 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
2073 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
2074 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2075 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
2076 .writefn
= pmcntenset_write
,
2077 .accessfn
= pmreg_access
,
2079 .raw_writefn
= raw_write
},
2080 { .name
= "PMCNTENSET_EL0", .state
= ARM_CP_STATE_AA64
, .type
= ARM_CP_IO
,
2081 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 1,
2082 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2084 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
), .resetvalue
= 0,
2085 .writefn
= pmcntenset_write
, .raw_writefn
= raw_write
},
2086 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
2088 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
2089 .accessfn
= pmreg_access
,
2091 .writefn
= pmcntenclr_write
,
2092 .type
= ARM_CP_ALIAS
| ARM_CP_IO
},
2093 { .name
= "PMCNTENCLR_EL0", .state
= ARM_CP_STATE_AA64
,
2094 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 2,
2095 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2097 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2098 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
2099 .writefn
= pmcntenclr_write
},
2100 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
2101 .access
= PL0_RW
, .type
= ARM_CP_IO
,
2102 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2103 .accessfn
= pmreg_access
,
2105 .writefn
= pmovsr_write
,
2106 .raw_writefn
= raw_write
},
2107 { .name
= "PMOVSCLR_EL0", .state
= ARM_CP_STATE_AA64
,
2108 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 3,
2109 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2111 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2112 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2113 .writefn
= pmovsr_write
,
2114 .raw_writefn
= raw_write
},
2115 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
2116 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2117 .fgt
= FGT_PMSWINC_EL0
,
2118 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2119 .writefn
= pmswinc_write
},
2120 { .name
= "PMSWINC_EL0", .state
= ARM_CP_STATE_AA64
,
2121 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 4,
2122 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
,
2123 .fgt
= FGT_PMSWINC_EL0
,
2124 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2125 .writefn
= pmswinc_write
},
2126 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
2127 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
2128 .fgt
= FGT_PMSELR_EL0
,
2129 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmselr
),
2130 .accessfn
= pmreg_access_selr
, .writefn
= pmselr_write
,
2131 .raw_writefn
= raw_write
},
2132 { .name
= "PMSELR_EL0", .state
= ARM_CP_STATE_AA64
,
2133 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 5,
2134 .access
= PL0_RW
, .accessfn
= pmreg_access_selr
,
2135 .fgt
= FGT_PMSELR_EL0
,
2136 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmselr
),
2137 .writefn
= pmselr_write
, .raw_writefn
= raw_write
, },
2138 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
2139 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2140 .fgt
= FGT_PMCCNTR_EL0
,
2141 .readfn
= pmccntr_read
, .writefn
= pmccntr_write32
,
2142 .accessfn
= pmreg_access_ccntr
},
2143 { .name
= "PMCCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2144 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 0,
2145 .access
= PL0_RW
, .accessfn
= pmreg_access_ccntr
,
2146 .fgt
= FGT_PMCCNTR_EL0
,
2148 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ccnt
),
2149 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
,
2150 .raw_readfn
= raw_read
, .raw_writefn
= raw_write
, },
2151 { .name
= "PMCCFILTR", .cp
= 15, .opc1
= 0, .crn
= 14, .crm
= 15, .opc2
= 7,
2152 .writefn
= pmccfiltr_write_a32
, .readfn
= pmccfiltr_read_a32
,
2153 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2154 .fgt
= FGT_PMCCFILTR_EL0
,
2155 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2157 { .name
= "PMCCFILTR_EL0", .state
= ARM_CP_STATE_AA64
,
2158 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 15, .opc2
= 7,
2159 .writefn
= pmccfiltr_write
, .raw_writefn
= raw_write
,
2160 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2161 .fgt
= FGT_PMCCFILTR_EL0
,
2163 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmccfiltr_el0
),
2165 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
2166 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2167 .accessfn
= pmreg_access
,
2168 .fgt
= FGT_PMEVTYPERN_EL0
,
2169 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2170 { .name
= "PMXEVTYPER_EL0", .state
= ARM_CP_STATE_AA64
,
2171 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 1,
2172 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2173 .accessfn
= pmreg_access
,
2174 .fgt
= FGT_PMEVTYPERN_EL0
,
2175 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
2176 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
2177 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2178 .accessfn
= pmreg_access_xevcntr
,
2179 .fgt
= FGT_PMEVCNTRN_EL0
,
2180 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2181 { .name
= "PMXEVCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
2182 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 2,
2183 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2184 .accessfn
= pmreg_access_xevcntr
,
2185 .fgt
= FGT_PMEVCNTRN_EL0
,
2186 .writefn
= pmxevcntr_write
, .readfn
= pmxevcntr_read
},
2187 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
2188 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
,
2189 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmuserenr
),
2191 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2192 { .name
= "PMUSERENR_EL0", .state
= ARM_CP_STATE_AA64
,
2193 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 0,
2194 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
2195 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
2197 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
2198 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
2199 .access
= PL1_RW
, .accessfn
= access_tpm
,
2201 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2202 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pminten
),
2204 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
2205 { .name
= "PMINTENSET_EL1", .state
= ARM_CP_STATE_AA64
,
2206 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 1,
2207 .access
= PL1_RW
, .accessfn
= access_tpm
,
2210 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2211 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
,
2212 .resetvalue
= 0x0 },
2213 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
2214 .access
= PL1_RW
, .accessfn
= access_tpm
,
2216 .type
= ARM_CP_ALIAS
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2217 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2218 .writefn
= pmintenclr_write
, },
2219 { .name
= "PMINTENCLR_EL1", .state
= ARM_CP_STATE_AA64
,
2220 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 2,
2221 .access
= PL1_RW
, .accessfn
= access_tpm
,
2223 .type
= ARM_CP_ALIAS
| ARM_CP_IO
| ARM_CP_NO_RAW
,
2224 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
2225 .writefn
= pmintenclr_write
},
2226 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
2227 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
2229 .accessfn
= access_tid4
,
2230 .fgt
= FGT_CCSIDR_EL1
,
2231 .readfn
= ccsidr_read
, .type
= ARM_CP_NO_RAW
},
2232 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
2233 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
2235 .accessfn
= access_tid4
,
2236 .fgt
= FGT_CSSELR_EL1
,
2237 .writefn
= csselr_write
, .resetvalue
= 0,
2238 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.csselr_s
),
2239 offsetof(CPUARMState
, cp15
.csselr_ns
) } },
2241 * Auxiliary ID register: this actually has an IMPDEF value but for now
2242 * just RAZ for all cores:
2244 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
2245 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
2246 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2247 .accessfn
= access_aa64_tid1
,
2248 .fgt
= FGT_AIDR_EL1
,
2251 * Auxiliary fault status registers: these also are IMPDEF, and we
2252 * choose to RAZ/WI for all cores.
2254 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2255 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
2256 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2257 .fgt
= FGT_AFSR0_EL1
,
2258 .nv2_redirect_offset
= 0x128 | NV2_REDIR_NV1
,
2259 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2260 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2261 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
2262 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2263 .fgt
= FGT_AFSR1_EL1
,
2264 .nv2_redirect_offset
= 0x130 | NV2_REDIR_NV1
,
2265 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2267 * MAIR can just read-as-written because we don't implement caches
2268 * and so don't need to care about memory attributes.
2270 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
2271 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2272 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2273 .fgt
= FGT_MAIR_EL1
,
2274 .nv2_redirect_offset
= 0x140 | NV2_REDIR_NV1
,
2275 .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[1]),
2277 { .name
= "MAIR_EL3", .state
= ARM_CP_STATE_AA64
,
2278 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 2, .opc2
= 0,
2279 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[3]),
2282 * For non-long-descriptor page tables these are PRRR and NMRR;
2283 * regardless they still act as reads-as-written for QEMU.
2286 * MAIR0/1 are defined separately from their 64-bit counterpart which
2287 * allows them to assign the correct fieldoffset based on the endianness
2288 * handled in the field definitions.
2290 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
,
2291 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
2292 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2293 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair0_s
),
2294 offsetof(CPUARMState
, cp15
.mair0_ns
) },
2295 .resetfn
= arm_cp_reset_ignore
},
2296 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
,
2297 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1,
2298 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
2299 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair1_s
),
2300 offsetof(CPUARMState
, cp15
.mair1_ns
) },
2301 .resetfn
= arm_cp_reset_ignore
},
2302 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
2303 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
2305 .type
= ARM_CP_NO_RAW
, .access
= PL1_R
, .readfn
= isr_read
},
2306 /* 32 bit ITLB invalidates */
2307 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
2308 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2309 .writefn
= tlbiall_write
},
2310 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
2311 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2312 .writefn
= tlbimva_write
},
2313 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
2314 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2315 .writefn
= tlbiasid_write
},
2316 /* 32 bit DTLB invalidates */
2317 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
2318 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2319 .writefn
= tlbiall_write
},
2320 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
2321 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2322 .writefn
= tlbimva_write
},
2323 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
2324 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2325 .writefn
= tlbiasid_write
},
2326 /* 32 bit TLB invalidates */
2327 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
2328 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2329 .writefn
= tlbiall_write
},
2330 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
2331 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2332 .writefn
= tlbimva_write
},
2333 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
2334 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2335 .writefn
= tlbiasid_write
},
2336 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
2337 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
2338 .writefn
= tlbimvaa_write
},
2341 static const ARMCPRegInfo v7mp_cp_reginfo
[] = {
2342 /* 32 bit TLB invalidates, Inner Shareable */
2343 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
2344 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2345 .writefn
= tlbiall_is_write
},
2346 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
2347 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2348 .writefn
= tlbimva_is_write
},
2349 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
2350 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2351 .writefn
= tlbiasid_is_write
},
2352 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
2353 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
2354 .writefn
= tlbimvaa_is_write
},
2357 static const ARMCPRegInfo pmovsset_cp_reginfo
[] = {
2358 /* PMOVSSET is not implemented in v7 before v7ve */
2359 { .name
= "PMOVSSET", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 3,
2360 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2362 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2363 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmovsr
),
2364 .writefn
= pmovsset_write
,
2365 .raw_writefn
= raw_write
},
2366 { .name
= "PMOVSSET_EL0", .state
= ARM_CP_STATE_AA64
,
2367 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 3,
2368 .access
= PL0_RW
, .accessfn
= pmreg_access
,
2370 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
2371 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
2372 .writefn
= pmovsset_write
,
2373 .raw_writefn
= raw_write
},
2376 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2383 static CPAccessResult
teecr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2387 * HSTR.TTEE only exists in v7A, not v8A, but v8A doesn't have T2EE
2388 * at all, so we don't need to check whether we're v8A.
2390 if (arm_current_el(env
) < 2 && !arm_is_secure_below_el3(env
) &&
2391 (env
->cp15
.hstr_el2
& HSTR_TTEE
)) {
2392 return CP_ACCESS_TRAP_EL2
;
2394 return CP_ACCESS_OK
;
2397 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2400 if (arm_current_el(env
) == 0 && (env
->teecr
& 1)) {
2401 return CP_ACCESS_TRAP
;
2403 return teecr_access(env
, ri
, isread
);
2406 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
2407 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
2408 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
2410 .writefn
= teecr_write
, .accessfn
= teecr_access
},
2411 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
2412 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
2413 .accessfn
= teehbr_access
, .resetvalue
= 0 },
2416 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
2417 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
2418 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
2420 .fgt
= FGT_TPIDR_EL0
,
2421 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[0]), .resetvalue
= 0 },
2422 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
2424 .fgt
= FGT_TPIDR_EL0
,
2425 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrurw_s
),
2426 offsetoflow32(CPUARMState
, cp15
.tpidrurw_ns
) },
2427 .resetfn
= arm_cp_reset_ignore
},
2428 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
2429 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
2430 .access
= PL0_R
| PL1_W
,
2431 .fgt
= FGT_TPIDRRO_EL0
,
2432 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el
[0]),
2434 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
2435 .access
= PL0_R
| PL1_W
,
2436 .fgt
= FGT_TPIDRRO_EL0
,
2437 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidruro_s
),
2438 offsetoflow32(CPUARMState
, cp15
.tpidruro_ns
) },
2439 .resetfn
= arm_cp_reset_ignore
},
2440 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_AA64
,
2441 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
2443 .fgt
= FGT_TPIDR_EL1
,
2444 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[1]), .resetvalue
= 0 },
2445 { .name
= "TPIDRPRW", .opc1
= 0, .cp
= 15, .crn
= 13, .crm
= 0, .opc2
= 4,
2447 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrprw_s
),
2448 offsetoflow32(CPUARMState
, cp15
.tpidrprw_ns
) },
2452 #ifndef CONFIG_USER_ONLY
2454 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2458 * CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
2459 * Writable only at the highest implemented exception level.
2461 int el
= arm_current_el(env
);
2467 hcr
= arm_hcr_el2_eff(env
);
2468 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2469 cntkctl
= env
->cp15
.cnthctl_el2
;
2471 cntkctl
= env
->cp15
.c14_cntkctl
;
2473 if (!extract32(cntkctl
, 0, 2)) {
2474 return CP_ACCESS_TRAP
;
2478 if (!isread
&& ri
->state
== ARM_CP_STATE_AA32
&&
2479 arm_is_secure_below_el3(env
)) {
2480 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
2481 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2489 if (!isread
&& el
< arm_highest_el(env
)) {
2490 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2493 return CP_ACCESS_OK
;
2496 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
,
2499 unsigned int cur_el
= arm_current_el(env
);
2500 bool has_el2
= arm_is_el2_enabled(env
);
2501 uint64_t hcr
= arm_hcr_el2_eff(env
);
2505 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]CTEN. */
2506 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2507 return (extract32(env
->cp15
.cnthctl_el2
, timeridx
, 1)
2508 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2511 /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */
2512 if (!extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
2513 return CP_ACCESS_TRAP
;
2517 /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */
2518 if (has_el2
&& timeridx
== GTIMER_PHYS
&&
2520 ? !extract32(env
->cp15
.cnthctl_el2
, 10, 1)
2521 : !extract32(env
->cp15
.cnthctl_el2
, 0, 1))) {
2522 return CP_ACCESS_TRAP_EL2
;
2526 return CP_ACCESS_OK
;
2529 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
,
2532 unsigned int cur_el
= arm_current_el(env
);
2533 bool has_el2
= arm_is_el2_enabled(env
);
2534 uint64_t hcr
= arm_hcr_el2_eff(env
);
2538 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2539 /* If HCR_EL2.<E2H,TGE> == '11': check CNTHCTL_EL2.EL0[PV]TEN. */
2540 return (extract32(env
->cp15
.cnthctl_el2
, 9 - timeridx
, 1)
2541 ? CP_ACCESS_OK
: CP_ACCESS_TRAP_EL2
);
2545 * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from
2546 * EL0 if EL0[PV]TEN is zero.
2548 if (!extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
2549 return CP_ACCESS_TRAP
;
2554 if (has_el2
&& timeridx
== GTIMER_PHYS
) {
2555 if (hcr
& HCR_E2H
) {
2556 /* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */
2557 if (!extract32(env
->cp15
.cnthctl_el2
, 11, 1)) {
2558 return CP_ACCESS_TRAP_EL2
;
2561 /* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
2562 if (!extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
2563 return CP_ACCESS_TRAP_EL2
;
2569 return CP_ACCESS_OK
;
2572 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
2573 const ARMCPRegInfo
*ri
,
2576 return gt_counter_access(env
, GTIMER_PHYS
, isread
);
2579 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
2580 const ARMCPRegInfo
*ri
,
2583 return gt_counter_access(env
, GTIMER_VIRT
, isread
);
2586 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2589 return gt_timer_access(env
, GTIMER_PHYS
, isread
);
2592 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2595 return gt_timer_access(env
, GTIMER_VIRT
, isread
);
2598 static CPAccessResult
gt_stimer_access(CPUARMState
*env
,
2599 const ARMCPRegInfo
*ri
,
2603 * The AArch64 register view of the secure physical timer is
2604 * always accessible from EL3, and configurably accessible from
2607 switch (arm_current_el(env
)) {
2609 if (!arm_is_secure(env
)) {
2610 return CP_ACCESS_TRAP
;
2612 if (!(env
->cp15
.scr_el3
& SCR_ST
)) {
2613 return CP_ACCESS_TRAP_EL3
;
2615 return CP_ACCESS_OK
;
2618 return CP_ACCESS_TRAP
;
2620 return CP_ACCESS_OK
;
2622 g_assert_not_reached();
2626 static uint64_t gt_get_countervalue(CPUARMState
*env
)
2628 ARMCPU
*cpu
= env_archcpu(env
);
2630 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / gt_cntfrq_period_ns(cpu
);
2633 static void gt_update_irq(ARMCPU
*cpu
, int timeridx
)
2635 CPUARMState
*env
= &cpu
->env
;
2636 uint64_t cnthctl
= env
->cp15
.cnthctl_el2
;
2637 ARMSecuritySpace ss
= arm_security_space(env
);
2638 /* ISTATUS && !IMASK */
2639 int irqstate
= (env
->cp15
.c14_timer
[timeridx
].ctl
& 6) == 4;
2642 * If bit CNTHCTL_EL2.CNT[VP]MASK is set, it overrides IMASK.
2643 * It is RES0 in Secure and NonSecure state.
2645 if ((ss
== ARMSS_Root
|| ss
== ARMSS_Realm
) &&
2646 ((timeridx
== GTIMER_VIRT
&& (cnthctl
& CNTHCTL_CNTVMASK
)) ||
2647 (timeridx
== GTIMER_PHYS
&& (cnthctl
& CNTHCTL_CNTPMASK
)))) {
2651 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
2652 trace_arm_gt_update_irq(timeridx
, irqstate
);
2655 void gt_rme_post_el_change(ARMCPU
*cpu
, void *ignored
)
2658 * Changing security state between Root and Secure/NonSecure, which may
2659 * happen when switching EL, can change the effective value of CNTHCTL_EL2
2660 * mask bits. Update the IRQ state accordingly.
2662 gt_update_irq(cpu
, GTIMER_VIRT
);
2663 gt_update_irq(cpu
, GTIMER_PHYS
);
2666 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
2668 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
2672 * Timer enabled: calculate and set current ISTATUS, irq, and
2673 * reset timer to when ISTATUS next has to change
2675 uint64_t offset
= timeridx
== GTIMER_VIRT
?
2676 cpu
->env
.cp15
.cntvoff_el2
: 0;
2677 uint64_t count
= gt_get_countervalue(&cpu
->env
);
2678 /* Note that this must be unsigned 64 bit arithmetic: */
2679 int istatus
= count
- offset
>= gt
->cval
;
2682 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
2686 * Next transition is when (count - offset) rolls back over to 0.
2687 * If offset > count then this is when count == offset;
2688 * if offset <= count then this is when count == offset + 2^64
2689 * For the latter case we set nexttick to an "as far in future
2690 * as possible" value and let the code below handle it.
2692 if (offset
> count
) {
2695 nexttick
= UINT64_MAX
;
2699 * Next transition is when (count - offset) == cval, i.e.
2700 * when count == (cval + offset).
2701 * If that would overflow, then again we set up the next interrupt
2702 * for "as far in the future as possible" for the code below.
2704 if (uadd64_overflow(gt
->cval
, offset
, &nexttick
)) {
2705 nexttick
= UINT64_MAX
;
2709 * Note that the desired next expiry time might be beyond the
2710 * signed-64-bit range of a QEMUTimer -- in this case we just
2711 * set the timer for as far in the future as possible. When the
2712 * timer expires we will reset the timer for any remaining period.
2714 if (nexttick
> INT64_MAX
/ gt_cntfrq_period_ns(cpu
)) {
2715 timer_mod_ns(cpu
->gt_timer
[timeridx
], INT64_MAX
);
2717 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
2719 trace_arm_gt_recalc(timeridx
, nexttick
);
2721 /* Timer disabled: ISTATUS and timer output always clear */
2723 timer_del(cpu
->gt_timer
[timeridx
]);
2724 trace_arm_gt_recalc_disabled(timeridx
);
2726 gt_update_irq(cpu
, timeridx
);
2729 static void gt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2732 ARMCPU
*cpu
= env_archcpu(env
);
2734 timer_del(cpu
->gt_timer
[timeridx
]);
2737 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2739 return gt_get_countervalue(env
);
2742 static uint64_t gt_virt_cnt_offset(CPUARMState
*env
)
2746 switch (arm_current_el(env
)) {
2748 hcr
= arm_hcr_el2_eff(env
);
2749 if (hcr
& HCR_E2H
) {
2754 hcr
= arm_hcr_el2_eff(env
);
2755 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
2761 return env
->cp15
.cntvoff_el2
;
2764 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2766 return gt_get_countervalue(env
) - gt_virt_cnt_offset(env
);
2769 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2773 trace_arm_gt_cval_write(timeridx
, value
);
2774 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
2775 gt_recalc_timer(env_archcpu(env
), timeridx
);
2778 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2781 uint64_t offset
= 0;
2785 case GTIMER_HYPVIRT
:
2786 offset
= gt_virt_cnt_offset(env
);
2790 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
2791 (gt_get_countervalue(env
) - offset
));
2794 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2798 uint64_t offset
= 0;
2802 case GTIMER_HYPVIRT
:
2803 offset
= gt_virt_cnt_offset(env
);
2807 trace_arm_gt_tval_write(timeridx
, value
);
2808 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) - offset
+
2809 sextract64(value
, 0, 32);
2810 gt_recalc_timer(env_archcpu(env
), timeridx
);
2813 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2817 ARMCPU
*cpu
= env_archcpu(env
);
2818 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
2820 trace_arm_gt_ctl_write(timeridx
, value
);
2821 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
2822 if ((oldval
^ value
) & 1) {
2823 /* Enable toggled */
2824 gt_recalc_timer(cpu
, timeridx
);
2825 } else if ((oldval
^ value
) & 2) {
2827 * IMASK toggled: don't need to recalculate,
2828 * just set the interrupt line based on ISTATUS
2830 trace_arm_gt_imask_toggle(timeridx
);
2831 gt_update_irq(cpu
, timeridx
);
2835 static void gt_phys_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2837 gt_timer_reset(env
, ri
, GTIMER_PHYS
);
2840 static void gt_phys_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2843 gt_cval_write(env
, ri
, GTIMER_PHYS
, value
);
2846 static uint64_t gt_phys_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2848 return gt_tval_read(env
, ri
, GTIMER_PHYS
);
2851 static void gt_phys_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2854 gt_tval_write(env
, ri
, GTIMER_PHYS
, value
);
2857 static void gt_phys_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2860 gt_ctl_write(env
, ri
, GTIMER_PHYS
, value
);
2863 static int gt_phys_redir_timeridx(CPUARMState
*env
)
2865 switch (arm_mmu_idx(env
)) {
2866 case ARMMMUIdx_E20_0
:
2867 case ARMMMUIdx_E20_2
:
2868 case ARMMMUIdx_E20_2_PAN
:
2875 static int gt_virt_redir_timeridx(CPUARMState
*env
)
2877 switch (arm_mmu_idx(env
)) {
2878 case ARMMMUIdx_E20_0
:
2879 case ARMMMUIdx_E20_2
:
2880 case ARMMMUIdx_E20_2_PAN
:
2881 return GTIMER_HYPVIRT
;
2887 static uint64_t gt_phys_redir_cval_read(CPUARMState
*env
,
2888 const ARMCPRegInfo
*ri
)
2890 int timeridx
= gt_phys_redir_timeridx(env
);
2891 return env
->cp15
.c14_timer
[timeridx
].cval
;
2894 static void gt_phys_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2897 int timeridx
= gt_phys_redir_timeridx(env
);
2898 gt_cval_write(env
, ri
, timeridx
, value
);
2901 static uint64_t gt_phys_redir_tval_read(CPUARMState
*env
,
2902 const ARMCPRegInfo
*ri
)
2904 int timeridx
= gt_phys_redir_timeridx(env
);
2905 return gt_tval_read(env
, ri
, timeridx
);
2908 static void gt_phys_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2911 int timeridx
= gt_phys_redir_timeridx(env
);
2912 gt_tval_write(env
, ri
, timeridx
, value
);
2915 static uint64_t gt_phys_redir_ctl_read(CPUARMState
*env
,
2916 const ARMCPRegInfo
*ri
)
2918 int timeridx
= gt_phys_redir_timeridx(env
);
2919 return env
->cp15
.c14_timer
[timeridx
].ctl
;
2922 static void gt_phys_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2925 int timeridx
= gt_phys_redir_timeridx(env
);
2926 gt_ctl_write(env
, ri
, timeridx
, value
);
2929 static void gt_virt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2931 gt_timer_reset(env
, ri
, GTIMER_VIRT
);
2934 static void gt_virt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2937 gt_cval_write(env
, ri
, GTIMER_VIRT
, value
);
2940 static uint64_t gt_virt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2942 return gt_tval_read(env
, ri
, GTIMER_VIRT
);
2945 static void gt_virt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2948 gt_tval_write(env
, ri
, GTIMER_VIRT
, value
);
2951 static void gt_virt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2954 gt_ctl_write(env
, ri
, GTIMER_VIRT
, value
);
2957 static void gt_cnthctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2960 ARMCPU
*cpu
= env_archcpu(env
);
2961 uint32_t oldval
= env
->cp15
.cnthctl_el2
;
2963 raw_write(env
, ri
, value
);
2965 if ((oldval
^ value
) & CNTHCTL_CNTVMASK
) {
2966 gt_update_irq(cpu
, GTIMER_VIRT
);
2967 } else if ((oldval
^ value
) & CNTHCTL_CNTPMASK
) {
2968 gt_update_irq(cpu
, GTIMER_PHYS
);
2972 static void gt_cntvoff_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2975 ARMCPU
*cpu
= env_archcpu(env
);
2977 trace_arm_gt_cntvoff_write(value
);
2978 raw_write(env
, ri
, value
);
2979 gt_recalc_timer(cpu
, GTIMER_VIRT
);
2982 static uint64_t gt_virt_redir_cval_read(CPUARMState
*env
,
2983 const ARMCPRegInfo
*ri
)
2985 int timeridx
= gt_virt_redir_timeridx(env
);
2986 return env
->cp15
.c14_timer
[timeridx
].cval
;
2989 static void gt_virt_redir_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2992 int timeridx
= gt_virt_redir_timeridx(env
);
2993 gt_cval_write(env
, ri
, timeridx
, value
);
2996 static uint64_t gt_virt_redir_tval_read(CPUARMState
*env
,
2997 const ARMCPRegInfo
*ri
)
2999 int timeridx
= gt_virt_redir_timeridx(env
);
3000 return gt_tval_read(env
, ri
, timeridx
);
3003 static void gt_virt_redir_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3006 int timeridx
= gt_virt_redir_timeridx(env
);
3007 gt_tval_write(env
, ri
, timeridx
, value
);
3010 static uint64_t gt_virt_redir_ctl_read(CPUARMState
*env
,
3011 const ARMCPRegInfo
*ri
)
3013 int timeridx
= gt_virt_redir_timeridx(env
);
3014 return env
->cp15
.c14_timer
[timeridx
].ctl
;
3017 static void gt_virt_redir_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3020 int timeridx
= gt_virt_redir_timeridx(env
);
3021 gt_ctl_write(env
, ri
, timeridx
, value
);
3024 static void gt_hyp_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3026 gt_timer_reset(env
, ri
, GTIMER_HYP
);
3029 static void gt_hyp_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3032 gt_cval_write(env
, ri
, GTIMER_HYP
, value
);
3035 static uint64_t gt_hyp_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3037 return gt_tval_read(env
, ri
, GTIMER_HYP
);
3040 static void gt_hyp_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3043 gt_tval_write(env
, ri
, GTIMER_HYP
, value
);
3046 static void gt_hyp_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3049 gt_ctl_write(env
, ri
, GTIMER_HYP
, value
);
3052 static void gt_sec_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3054 gt_timer_reset(env
, ri
, GTIMER_SEC
);
3057 static void gt_sec_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3060 gt_cval_write(env
, ri
, GTIMER_SEC
, value
);
3063 static uint64_t gt_sec_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3065 return gt_tval_read(env
, ri
, GTIMER_SEC
);
3068 static void gt_sec_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3071 gt_tval_write(env
, ri
, GTIMER_SEC
, value
);
3074 static void gt_sec_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3077 gt_ctl_write(env
, ri
, GTIMER_SEC
, value
);
3080 static void gt_hv_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3082 gt_timer_reset(env
, ri
, GTIMER_HYPVIRT
);
3085 static void gt_hv_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3088 gt_cval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3091 static uint64_t gt_hv_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3093 return gt_tval_read(env
, ri
, GTIMER_HYPVIRT
);
3096 static void gt_hv_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3099 gt_tval_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3102 static void gt_hv_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3105 gt_ctl_write(env
, ri
, GTIMER_HYPVIRT
, value
);
3108 void arm_gt_ptimer_cb(void *opaque
)
3110 ARMCPU
*cpu
= opaque
;
3112 gt_recalc_timer(cpu
, GTIMER_PHYS
);
3115 void arm_gt_vtimer_cb(void *opaque
)
3117 ARMCPU
*cpu
= opaque
;
3119 gt_recalc_timer(cpu
, GTIMER_VIRT
);
3122 void arm_gt_htimer_cb(void *opaque
)
3124 ARMCPU
*cpu
= opaque
;
3126 gt_recalc_timer(cpu
, GTIMER_HYP
);
3129 void arm_gt_stimer_cb(void *opaque
)
3131 ARMCPU
*cpu
= opaque
;
3133 gt_recalc_timer(cpu
, GTIMER_SEC
);
3136 void arm_gt_hvtimer_cb(void *opaque
)
3138 ARMCPU
*cpu
= opaque
;
3140 gt_recalc_timer(cpu
, GTIMER_HYPVIRT
);
3143 static void arm_gt_cntfrq_reset(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
3145 ARMCPU
*cpu
= env_archcpu(env
);
3147 cpu
->env
.cp15
.c14_cntfrq
= cpu
->gt_cntfrq_hz
;
3150 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
3152 * Note that CNTFRQ is purely reads-as-written for the benefit
3153 * of software; writing it doesn't actually change the timer frequency.
3154 * Our reset value matches the fixed frequency we implement the timer at.
3156 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
3157 .type
= ARM_CP_ALIAS
,
3158 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
3159 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
3161 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
3162 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
3163 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
3164 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
3165 .resetfn
= arm_gt_cntfrq_reset
,
3167 /* overall control: mostly access permissions */
3168 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
3169 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
3171 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
3174 /* per-timer control */
3175 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
3176 .secure
= ARM_CP_SECSTATE_NS
,
3177 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3178 .accessfn
= gt_ptimer_access
,
3179 .fieldoffset
= offsetoflow32(CPUARMState
,
3180 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
3181 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
3182 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
3184 { .name
= "CNTP_CTL_S",
3185 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
3186 .secure
= ARM_CP_SECSTATE_S
,
3187 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3188 .accessfn
= gt_ptimer_access
,
3189 .fieldoffset
= offsetoflow32(CPUARMState
,
3190 cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3191 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3193 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
3194 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
3195 .type
= ARM_CP_IO
, .access
= PL0_RW
,
3196 .accessfn
= gt_ptimer_access
,
3197 .nv2_redirect_offset
= 0x180 | NV2_REDIR_NV1
,
3198 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
3200 .readfn
= gt_phys_redir_ctl_read
, .raw_readfn
= raw_read
,
3201 .writefn
= gt_phys_redir_ctl_write
, .raw_writefn
= raw_write
,
3203 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
3204 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL0_RW
,
3205 .accessfn
= gt_vtimer_access
,
3206 .fieldoffset
= offsetoflow32(CPUARMState
,
3207 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
3208 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
3209 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
3211 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
3212 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
3213 .type
= ARM_CP_IO
, .access
= PL0_RW
,
3214 .accessfn
= gt_vtimer_access
,
3215 .nv2_redirect_offset
= 0x170 | NV2_REDIR_NV1
,
3216 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
3218 .readfn
= gt_virt_redir_ctl_read
, .raw_readfn
= raw_read
,
3219 .writefn
= gt_virt_redir_ctl_write
, .raw_writefn
= raw_write
,
3221 /* TimerValue views: a 32 bit downcounting view of the underlying state */
3222 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
3223 .secure
= ARM_CP_SECSTATE_NS
,
3224 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3225 .accessfn
= gt_ptimer_access
,
3226 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
3228 { .name
= "CNTP_TVAL_S",
3229 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
3230 .secure
= ARM_CP_SECSTATE_S
,
3231 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3232 .accessfn
= gt_ptimer_access
,
3233 .readfn
= gt_sec_tval_read
, .writefn
= gt_sec_tval_write
,
3235 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3236 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
3237 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3238 .accessfn
= gt_ptimer_access
, .resetfn
= gt_phys_timer_reset
,
3239 .readfn
= gt_phys_redir_tval_read
, .writefn
= gt_phys_redir_tval_write
,
3241 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
3242 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3243 .accessfn
= gt_vtimer_access
,
3244 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
3246 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3247 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
3248 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL0_RW
,
3249 .accessfn
= gt_vtimer_access
, .resetfn
= gt_virt_timer_reset
,
3250 .readfn
= gt_virt_redir_tval_read
, .writefn
= gt_virt_redir_tval_write
,
3252 /* The counter itself */
3253 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
3254 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3255 .accessfn
= gt_pct_access
,
3256 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3258 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
3259 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
3260 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3261 .accessfn
= gt_pct_access
, .readfn
= gt_cnt_read
,
3263 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
3264 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
3265 .accessfn
= gt_vct_access
,
3266 .readfn
= gt_virt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
3268 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3269 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3270 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3271 .accessfn
= gt_vct_access
, .readfn
= gt_virt_cnt_read
,
3273 /* Comparison value, indicating when the timer goes off */
3274 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
3275 .secure
= ARM_CP_SECSTATE_NS
,
3277 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3278 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3279 .accessfn
= gt_ptimer_access
,
3280 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3281 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3283 { .name
= "CNTP_CVAL_S", .cp
= 15, .crm
= 14, .opc1
= 2,
3284 .secure
= ARM_CP_SECSTATE_S
,
3286 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3287 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3288 .accessfn
= gt_ptimer_access
,
3289 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3291 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3292 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
3295 .nv2_redirect_offset
= 0x178 | NV2_REDIR_NV1
,
3296 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
3297 .resetvalue
= 0, .accessfn
= gt_ptimer_access
,
3298 .readfn
= gt_phys_redir_cval_read
, .raw_readfn
= raw_read
,
3299 .writefn
= gt_phys_redir_cval_write
, .raw_writefn
= raw_write
,
3301 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
3303 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
3304 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3305 .accessfn
= gt_vtimer_access
,
3306 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3307 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3309 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
3310 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
3313 .nv2_redirect_offset
= 0x168 | NV2_REDIR_NV1
,
3314 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
3315 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
3316 .readfn
= gt_virt_redir_cval_read
, .raw_readfn
= raw_read
,
3317 .writefn
= gt_virt_redir_cval_write
, .raw_writefn
= raw_write
,
3320 * Secure timer -- this is actually restricted to only EL3
3321 * and configurably Secure-EL1 via the accessfn.
3323 { .name
= "CNTPS_TVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3324 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 0,
3325 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
,
3326 .accessfn
= gt_stimer_access
,
3327 .readfn
= gt_sec_tval_read
,
3328 .writefn
= gt_sec_tval_write
,
3329 .resetfn
= gt_sec_timer_reset
,
3331 { .name
= "CNTPS_CTL_EL1", .state
= ARM_CP_STATE_AA64
,
3332 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 1,
3333 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3334 .accessfn
= gt_stimer_access
,
3335 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].ctl
),
3337 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
3339 { .name
= "CNTPS_CVAL_EL1", .state
= ARM_CP_STATE_AA64
,
3340 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 2,
3341 .type
= ARM_CP_IO
, .access
= PL1_RW
,
3342 .accessfn
= gt_stimer_access
,
3343 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
3344 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
3351 * In user-mode most of the generic timer registers are inaccessible
3352 * however modern kernels (4.12+) allow access to cntvct_el0
3355 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3357 ARMCPU
*cpu
= env_archcpu(env
);
3360 * Currently we have no support for QEMUTimer in linux-user so we
3361 * can't call gt_get_countervalue(env), instead we directly
3362 * call the lower level functions.
3364 return cpu_get_clock() / gt_cntfrq_period_ns(cpu
);
3367 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
3368 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
3369 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
3370 .type
= ARM_CP_CONST
, .access
= PL0_R
/* no PL1_RW in linux-user */,
3371 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
3372 .resetvalue
= NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
,
3374 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
3375 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
3376 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
3377 .readfn
= gt_virt_cnt_read
,
3383 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3385 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3386 raw_write(env
, ri
, value
);
3387 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
3388 raw_write(env
, ri
, value
& 0xfffff6ff);
3390 raw_write(env
, ri
, value
& 0xfffff1ff);
3394 #ifndef CONFIG_USER_ONLY
3395 /* get_phys_addr() isn't present for user-mode-only targets */
3397 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3402 * The ATS12NSO* operations must trap to EL3 or EL2 if executed in
3403 * Secure EL1 (which can only happen if EL3 is AArch64).
3404 * They are simply UNDEF if executed from NS EL1.
3405 * They function normally from EL2 or EL3.
3407 if (arm_current_el(env
) == 1) {
3408 if (arm_is_secure_below_el3(env
)) {
3409 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
3410 return CP_ACCESS_TRAP_EL2
;
3412 return CP_ACCESS_TRAP_EL3
;
3414 return CP_ACCESS_TRAP_UNCATEGORIZED
;
3417 return CP_ACCESS_OK
;
3421 static int par_el1_shareability(GetPhysAddrResult
*res
)
3424 * The PAR_EL1.SH field must be 0b10 for Device or Normal-NC
3425 * memory -- see pseudocode PAREncodeShareability().
3427 if (((res
->cacheattrs
.attrs
& 0xf0) == 0) ||
3428 res
->cacheattrs
.attrs
== 0x44 || res
->cacheattrs
.attrs
== 0x40) {
3431 return res
->cacheattrs
.shareability
;
3434 static uint64_t do_ats_write(CPUARMState
*env
, uint64_t value
,
3435 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
3436 ARMSecuritySpace ss
)
3440 bool format64
= false;
3441 ARMMMUFaultInfo fi
= {};
3442 GetPhysAddrResult res
= {};
3445 * I_MXTJT: Granule protection checks are not performed on the final address
3446 * of a successful translation.
3448 ret
= get_phys_addr_with_space_nogpc(env
, value
, access_type
, mmu_idx
, ss
,
3452 * ATS operations only do S1 or S1+S2 translations, so we never
3453 * have to deal with the ARMCacheAttrs format for S2 only.
3455 assert(!res
.cacheattrs
.is_s2_format
);
3459 * Some kinds of translation fault must cause exceptions rather
3460 * than being reported in the PAR.
3462 int current_el
= arm_current_el(env
);
3464 uint32_t syn
, fsr
, fsc
;
3465 bool take_exc
= false;
3467 if (fi
.s1ptw
&& current_el
== 1
3468 && arm_mmu_idx_is_stage1_of_2(mmu_idx
)) {
3470 * Synchronous stage 2 fault on an access made as part of the
3471 * translation table walk for AT S1E0* or AT S1E1* insn
3472 * executed from NS EL1. If this is a synchronous external abort
3473 * and SCR_EL3.EA == 1, then we take a synchronous external abort
3474 * to EL3. Otherwise the fault is taken as an exception to EL2,
3475 * and HPFAR_EL2 holds the faulting IPA.
3477 if (fi
.type
== ARMFault_SyncExternalOnWalk
&&
3478 (env
->cp15
.scr_el3
& SCR_EA
)) {
3481 env
->cp15
.hpfar_el2
= extract64(fi
.s2addr
, 12, 47) << 4;
3482 if (arm_is_secure_below_el3(env
) && fi
.s1ns
) {
3483 env
->cp15
.hpfar_el2
|= HPFAR_NS
;
3488 } else if (fi
.type
== ARMFault_SyncExternalOnWalk
) {
3490 * Synchronous external aborts during a translation table walk
3491 * are taken as Data Abort exceptions.
3494 if (current_el
== 3) {
3500 target_el
= exception_target_el(env
);
3506 /* Construct FSR and FSC using same logic as arm_deliver_fault() */
3507 if (target_el
== 2 || arm_el_is_aa64(env
, target_el
) ||
3508 arm_s1_regime_using_lpae_format(env
, mmu_idx
)) {
3509 fsr
= arm_fi_to_lfsc(&fi
);
3510 fsc
= extract32(fsr
, 0, 6);
3512 fsr
= arm_fi_to_sfsc(&fi
);
3516 * Report exception with ESR indicating a fault due to a
3517 * translation table walk for a cache maintenance instruction.
3519 syn
= syn_data_abort_no_iss(current_el
== target_el
, 0,
3520 fi
.ea
, 1, fi
.s1ptw
, 1, fsc
);
3521 env
->exception
.vaddress
= value
;
3522 env
->exception
.fsr
= fsr
;
3523 raise_exception(env
, EXCP_DATA_ABORT
, syn
, target_el
);
3529 } else if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
3532 * * TTBCR.EAE determines whether the result is returned using the
3533 * 32-bit or the 64-bit PAR format
3534 * * Instructions executed in Hyp mode always use the 64bit format
3536 * ATS1S2NSOxx uses the 64bit format if any of the following is true:
3537 * * The Non-secure TTBCR.EAE bit is set to 1
3538 * * The implementation includes EL2, and the value of HCR.VM is 1
3540 * (Note that HCR.DC makes HCR.VM behave as if it is 1.)
3542 * ATS1Hx always uses the 64bit format.
3544 format64
= arm_s1_regime_using_lpae_format(env
, mmu_idx
);
3546 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
3547 if (mmu_idx
== ARMMMUIdx_E10_0
||
3548 mmu_idx
== ARMMMUIdx_E10_1
||
3549 mmu_idx
== ARMMMUIdx_E10_1_PAN
) {
3550 format64
|= env
->cp15
.hcr_el2
& (HCR_VM
| HCR_DC
);
3552 format64
|= arm_current_el(env
) == 2;
3558 /* Create a 64-bit PAR */
3559 par64
= (1 << 11); /* LPAE bit always set */
3561 par64
|= res
.f
.phys_addr
& ~0xfffULL
;
3562 if (!res
.f
.attrs
.secure
) {
3563 par64
|= (1 << 9); /* NS */
3565 par64
|= (uint64_t)res
.cacheattrs
.attrs
<< 56; /* ATTR */
3566 par64
|= par_el1_shareability(&res
) << 7; /* SH */
3568 uint32_t fsr
= arm_fi_to_lfsc(&fi
);
3571 par64
|= (fsr
& 0x3f) << 1; /* FS */
3573 par64
|= (1 << 9); /* S */
3576 par64
|= (1 << 8); /* PTW */
3581 * fsr is a DFSR/IFSR value for the short descriptor
3582 * translation table format (with WnR always clear).
3583 * Convert it to a 32-bit PAR.
3586 /* We do not set any attribute bits in the PAR */
3587 if (res
.f
.lg_page_size
== 24
3588 && arm_feature(env
, ARM_FEATURE_V7
)) {
3589 par64
= (res
.f
.phys_addr
& 0xff000000) | (1 << 1);
3591 par64
= res
.f
.phys_addr
& 0xfffff000;
3593 if (!res
.f
.attrs
.secure
) {
3594 par64
|= (1 << 9); /* NS */
3597 uint32_t fsr
= arm_fi_to_sfsc(&fi
);
3599 par64
= ((fsr
& (1 << 10)) >> 5) | ((fsr
& (1 << 12)) >> 6) |
3600 ((fsr
& 0xf) << 1) | 1;
3605 #endif /* CONFIG_TCG */
3607 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3610 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3613 int el
= arm_current_el(env
);
3614 ARMSecuritySpace ss
= arm_security_space(env
);
3616 switch (ri
->opc2
& 6) {
3618 /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */
3621 mmu_idx
= ARMMMUIdx_E3
;
3624 g_assert(ss
!= ARMSS_Secure
); /* ARMv8.4-SecEL2 is 64-bit only */
3627 if (ri
->crm
== 9 && arm_pan_enabled(env
)) {
3628 mmu_idx
= ARMMMUIdx_Stage1_E1_PAN
;
3630 mmu_idx
= ARMMMUIdx_Stage1_E1
;
3634 g_assert_not_reached();
3638 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
3641 mmu_idx
= ARMMMUIdx_E10_0
;
3644 g_assert(ss
!= ARMSS_Secure
); /* ARMv8.4-SecEL2 is 64-bit only */
3645 mmu_idx
= ARMMMUIdx_Stage1_E0
;
3648 mmu_idx
= ARMMMUIdx_Stage1_E0
;
3651 g_assert_not_reached();
3655 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
3656 mmu_idx
= ARMMMUIdx_E10_1
;
3657 ss
= ARMSS_NonSecure
;
3660 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
3661 mmu_idx
= ARMMMUIdx_E10_0
;
3662 ss
= ARMSS_NonSecure
;
3665 g_assert_not_reached();
3668 par64
= do_ats_write(env
, value
, access_type
, mmu_idx
, ss
);
3670 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3672 /* Handled by hardware accelerator. */
3673 g_assert_not_reached();
3674 #endif /* CONFIG_TCG */
3677 static void ats1h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3681 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3684 /* There is no SecureEL2 for AArch32. */
3685 par64
= do_ats_write(env
, value
, access_type
, ARMMMUIdx_E2
,
3688 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
3690 /* Handled by hardware accelerator. */
3691 g_assert_not_reached();
3692 #endif /* CONFIG_TCG */
3695 static CPAccessResult
at_e012_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3699 * R_NYXTL: instruction is UNDEFINED if it applies to an Exception level
3700 * lower than EL3 and the combination SCR_EL3.{NSE,NS} is reserved. This can
3701 * only happen when executing at EL3 because that combination also causes an
3702 * illegal exception return. We don't need to check FEAT_RME either, because
3703 * scr_write() ensures that the NSE bit is not set otherwise.
3705 if ((env
->cp15
.scr_el3
& (SCR_NSE
| SCR_NS
)) == SCR_NSE
) {
3706 return CP_ACCESS_TRAP
;
3708 return CP_ACCESS_OK
;
3711 static CPAccessResult
at_s1e2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3714 if (arm_current_el(env
) == 3 &&
3715 !(env
->cp15
.scr_el3
& (SCR_NS
| SCR_EEL2
))) {
3716 return CP_ACCESS_TRAP
;
3718 return at_e012_access(env
, ri
, isread
);
3721 static CPAccessResult
at_s1e01_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3724 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_AT
)) {
3725 return CP_ACCESS_TRAP_EL2
;
3727 return at_e012_access(env
, ri
, isread
);
3730 static void ats_write64(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3734 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
3736 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
3737 bool regime_e20
= (hcr_el2
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
);
3739 switch (ri
->opc2
& 6) {
3742 case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */
3743 if (ri
->crm
== 9 && arm_pan_enabled(env
)) {
3744 mmu_idx
= regime_e20
?
3745 ARMMMUIdx_E20_2_PAN
: ARMMMUIdx_Stage1_E1_PAN
;
3747 mmu_idx
= regime_e20
? ARMMMUIdx_E20_2
: ARMMMUIdx_Stage1_E1
;
3750 case 4: /* AT S1E2R, AT S1E2W */
3751 mmu_idx
= hcr_el2
& HCR_E2H
? ARMMMUIdx_E20_2
: ARMMMUIdx_E2
;
3753 case 6: /* AT S1E3R, AT S1E3W */
3754 mmu_idx
= ARMMMUIdx_E3
;
3757 g_assert_not_reached();
3760 case 2: /* AT S1E0R, AT S1E0W */
3761 mmu_idx
= regime_e20
? ARMMMUIdx_E20_0
: ARMMMUIdx_Stage1_E0
;
3763 case 4: /* AT S12E1R, AT S12E1W */
3764 mmu_idx
= regime_e20
? ARMMMUIdx_E20_2
: ARMMMUIdx_E10_1
;
3766 case 6: /* AT S12E0R, AT S12E0W */
3767 mmu_idx
= regime_e20
? ARMMMUIdx_E20_0
: ARMMMUIdx_E10_0
;
3770 g_assert_not_reached();
3773 env
->cp15
.par_el
[1] = do_ats_write(env
, value
, access_type
,
3774 mmu_idx
, arm_security_space(env
));
3776 /* Handled by hardware accelerator. */
3777 g_assert_not_reached();
3778 #endif /* CONFIG_TCG */
3782 /* Return basic MPU access permission bits. */
3783 static uint32_t simple_mpu_ap_bits(uint32_t val
)
3790 for (i
= 0; i
< 16; i
+= 2) {
3791 ret
|= (val
>> i
) & mask
;
3797 /* Pad basic MPU access permission bits to extended format. */
3798 static uint32_t extended_mpu_ap_bits(uint32_t val
)
3805 for (i
= 0; i
< 16; i
+= 2) {
3806 ret
|= (val
& mask
) << i
;
3812 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3815 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
3818 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3820 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
3823 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3826 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
3829 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3831 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
3834 static uint64_t pmsav7_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3836 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3842 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3846 static void pmsav7_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3849 ARMCPU
*cpu
= env_archcpu(env
);
3850 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
3856 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
3857 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3861 static void pmsav7_rgnr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3864 ARMCPU
*cpu
= env_archcpu(env
);
3865 uint32_t nrgs
= cpu
->pmsav7_dregion
;
3867 if (value
>= nrgs
) {
3868 qemu_log_mask(LOG_GUEST_ERROR
,
3869 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
3870 " > %" PRIu32
"\n", (uint32_t)value
, nrgs
);
3874 raw_write(env
, ri
, value
);
3877 static void prbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3880 ARMCPU
*cpu
= env_archcpu(env
);
3882 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3883 env
->pmsav8
.rbar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]] = value
;
3886 static uint64_t prbar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3888 return env
->pmsav8
.rbar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]];
3891 static void prlar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3894 ARMCPU
*cpu
= env_archcpu(env
);
3896 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3897 env
->pmsav8
.rlar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]] = value
;
3900 static uint64_t prlar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3902 return env
->pmsav8
.rlar
[M_REG_NS
][env
->pmsav7
.rnr
[M_REG_NS
]];
3905 static void prselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3908 ARMCPU
*cpu
= env_archcpu(env
);
3911 * Ignore writes that would select not implemented region.
3912 * This is architecturally UNPREDICTABLE.
3914 if (value
>= cpu
->pmsav7_dregion
) {
3918 env
->pmsav7
.rnr
[M_REG_NS
] = value
;
3921 static void hprbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3924 ARMCPU
*cpu
= env_archcpu(env
);
3926 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3927 env
->pmsav8
.hprbar
[env
->pmsav8
.hprselr
] = value
;
3930 static uint64_t hprbar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3932 return env
->pmsav8
.hprbar
[env
->pmsav8
.hprselr
];
3935 static void hprlar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3938 ARMCPU
*cpu
= env_archcpu(env
);
3940 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3941 env
->pmsav8
.hprlar
[env
->pmsav8
.hprselr
] = value
;
3944 static uint64_t hprlar_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3946 return env
->pmsav8
.hprlar
[env
->pmsav8
.hprselr
];
3949 static void hprenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3954 ARMCPU
*cpu
= env_archcpu(env
);
3956 /* Ignore writes to unimplemented regions */
3957 int rmax
= MIN(cpu
->pmsav8r_hdregion
, 32);
3958 value
&= MAKE_64BIT_MASK(0, rmax
);
3960 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
3962 /* Register alias is only valid for first 32 indexes */
3963 for (n
= 0; n
< rmax
; ++n
) {
3964 bit
= extract32(value
, n
, 1);
3965 env
->pmsav8
.hprlar
[n
] = deposit32(
3966 env
->pmsav8
.hprlar
[n
], 0, 1, bit
);
3970 static uint64_t hprenr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3973 uint32_t result
= 0x0;
3974 ARMCPU
*cpu
= env_archcpu(env
);
3976 /* Register alias is only valid for first 32 indexes */
3977 for (n
= 0; n
< MIN(cpu
->pmsav8r_hdregion
, 32); ++n
) {
3978 if (env
->pmsav8
.hprlar
[n
] & 0x1) {
3979 result
|= (0x1 << n
);
3985 static void hprselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3988 ARMCPU
*cpu
= env_archcpu(env
);
3991 * Ignore writes that would select not implemented region.
3992 * This is architecturally UNPREDICTABLE.
3994 if (value
>= cpu
->pmsav8r_hdregion
) {
3998 env
->pmsav8
.hprselr
= value
;
4001 static void pmsav8r_regn_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4004 ARMCPU
*cpu
= env_archcpu(env
);
4005 uint8_t index
= (extract32(ri
->opc0
, 0, 1) << 4) |
4006 (extract32(ri
->crm
, 0, 3) << 1) | extract32(ri
->opc2
, 2, 1);
4008 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
4011 if (index
>= cpu
->pmsav8r_hdregion
) {
4014 if (ri
->opc2
& 0x1) {
4015 env
->pmsav8
.hprlar
[index
] = value
;
4017 env
->pmsav8
.hprbar
[index
] = value
;
4020 if (index
>= cpu
->pmsav7_dregion
) {
4023 if (ri
->opc2
& 0x1) {
4024 env
->pmsav8
.rlar
[M_REG_NS
][index
] = value
;
4026 env
->pmsav8
.rbar
[M_REG_NS
][index
] = value
;
4031 static uint64_t pmsav8r_regn_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4033 ARMCPU
*cpu
= env_archcpu(env
);
4034 uint8_t index
= (extract32(ri
->opc0
, 0, 1) << 4) |
4035 (extract32(ri
->crm
, 0, 3) << 1) | extract32(ri
->opc2
, 2, 1);
4038 if (index
>= cpu
->pmsav8r_hdregion
) {
4041 if (ri
->opc2
& 0x1) {
4042 return env
->pmsav8
.hprlar
[index
];
4044 return env
->pmsav8
.hprbar
[index
];
4047 if (index
>= cpu
->pmsav7_dregion
) {
4050 if (ri
->opc2
& 0x1) {
4051 return env
->pmsav8
.rlar
[M_REG_NS
][index
];
4053 return env
->pmsav8
.rbar
[M_REG_NS
][index
];
4058 static const ARMCPRegInfo pmsav8r_cp_reginfo
[] = {
4060 .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 3, .opc2
= 0,
4061 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4062 .accessfn
= access_tvm_trvm
,
4063 .readfn
= prbar_read
, .writefn
= prbar_write
},
4065 .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 3, .opc2
= 1,
4066 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4067 .accessfn
= access_tvm_trvm
,
4068 .readfn
= prlar_read
, .writefn
= prlar_write
},
4069 { .name
= "PRSELR", .resetvalue
= 0,
4070 .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 2, .opc2
= 1,
4071 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4072 .writefn
= prselr_write
,
4073 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]) },
4074 { .name
= "HPRBAR", .resetvalue
= 0,
4075 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 3, .opc2
= 0,
4076 .access
= PL2_RW
, .type
= ARM_CP_NO_RAW
,
4077 .readfn
= hprbar_read
, .writefn
= hprbar_write
},
4079 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 3, .opc2
= 1,
4080 .access
= PL2_RW
, .type
= ARM_CP_NO_RAW
,
4081 .readfn
= hprlar_read
, .writefn
= hprlar_write
},
4082 { .name
= "HPRSELR", .resetvalue
= 0,
4083 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 2, .opc2
= 1,
4085 .writefn
= hprselr_write
,
4086 .fieldoffset
= offsetof(CPUARMState
, pmsav8
.hprselr
) },
4088 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 1, .opc2
= 1,
4089 .access
= PL2_RW
, .type
= ARM_CP_NO_RAW
,
4090 .readfn
= hprenr_read
, .writefn
= hprenr_write
},
4093 static const ARMCPRegInfo pmsav7_cp_reginfo
[] = {
4095 * Reset for all these registers is handled in arm_cpu_reset(),
4096 * because the PMSAv7 is also used by M-profile CPUs, which do
4097 * not register cpregs but still need the state to be reset.
4099 { .name
= "DRBAR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 0,
4100 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4101 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drbar
),
4102 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
4103 .resetfn
= arm_cp_reset_ignore
},
4104 { .name
= "DRSR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 2,
4105 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4106 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drsr
),
4107 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
4108 .resetfn
= arm_cp_reset_ignore
},
4109 { .name
= "DRACR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 4,
4110 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
4111 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.dracr
),
4112 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
4113 .resetfn
= arm_cp_reset_ignore
},
4114 { .name
= "RGNR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 2, .opc2
= 0,
4116 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]),
4117 .writefn
= pmsav7_rgnr_write
,
4118 .resetfn
= arm_cp_reset_ignore
},
4121 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
4122 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
4123 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
4124 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
4125 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
4126 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
4127 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
4128 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
4129 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
4130 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
4132 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
4134 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
4136 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
4138 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
4140 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
4141 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
4143 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
4144 /* Protection region base and size registers */
4145 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
4146 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4147 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
4148 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
4149 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4150 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
4151 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
4152 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4153 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
4154 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
4155 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4156 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
4157 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
4158 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4159 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
4160 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
4161 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4162 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
4163 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
4164 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4165 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
4166 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
4167 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
4168 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
4171 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4174 ARMCPU
*cpu
= env_archcpu(env
);
4176 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
4177 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
4179 * Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
4180 * using Long-descriptor translation table format
4182 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
4183 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
4185 * In an implementation that includes the Security Extensions
4186 * TTBCR has additional fields PD0 [4] and PD1 [5] for
4187 * Short-descriptor translation table format.
4189 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
4195 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
4197 * With LPAE the TTBCR could result in a change of ASID
4198 * via the TTBCR.A1 bit, so do a TLB flush.
4200 tlb_flush(CPU(cpu
));
4202 raw_write(env
, ri
, value
);
4205 static void vmsa_tcr_el12_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4208 ARMCPU
*cpu
= env_archcpu(env
);
4210 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
4211 tlb_flush(CPU(cpu
));
4212 raw_write(env
, ri
, value
);
4215 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4218 /* If the ASID changes (with a 64-bit write), we must flush the TLB. */
4219 if (cpreg_field_is_64bit(ri
) &&
4220 extract64(raw_read(env
, ri
) ^ value
, 48, 16) != 0) {
4221 ARMCPU
*cpu
= env_archcpu(env
);
4222 tlb_flush(CPU(cpu
));
4224 raw_write(env
, ri
, value
);
4227 static void vmsa_tcr_ttbr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4231 * If we are running with E2&0 regime, then an ASID is active.
4232 * Flush if that might be changing. Note we're not checking
4233 * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that
4234 * holds the active ASID, only checking the field that might.
4236 if (extract64(raw_read(env
, ri
) ^ value
, 48, 16) &&
4237 (arm_hcr_el2_eff(env
) & HCR_E2H
)) {
4238 uint16_t mask
= ARMMMUIdxBit_E20_2
|
4239 ARMMMUIdxBit_E20_2_PAN
|
4241 tlb_flush_by_mmuidx(env_cpu(env
), mask
);
4243 raw_write(env
, ri
, value
);
4246 static void vttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4249 ARMCPU
*cpu
= env_archcpu(env
);
4250 CPUState
*cs
= CPU(cpu
);
4253 * A change in VMID to the stage2 page table (Stage2) invalidates
4254 * the stage2 and combined stage 1&2 tlbs (EL10_1 and EL10_0).
4256 if (extract64(raw_read(env
, ri
) ^ value
, 48, 16) != 0) {
4257 tlb_flush_by_mmuidx(cs
, alle1_tlbmask(env
));
4259 raw_write(env
, ri
, value
);
4262 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo
[] = {
4263 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
4264 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .type
= ARM_CP_ALIAS
,
4265 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dfsr_s
),
4266 offsetoflow32(CPUARMState
, cp15
.dfsr_ns
) }, },
4267 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
4268 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
4269 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.ifsr_s
),
4270 offsetoflow32(CPUARMState
, cp15
.ifsr_ns
) } },
4271 { .name
= "DFAR", .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 0, .opc2
= 0,
4272 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
4273 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.dfar_s
),
4274 offsetof(CPUARMState
, cp15
.dfar_ns
) } },
4275 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_AA64
,
4276 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
4277 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4279 .nv2_redirect_offset
= 0x220 | NV2_REDIR_NV1
,
4280 .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
4284 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
4285 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
4286 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
4287 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4289 .nv2_redirect_offset
= 0x138 | NV2_REDIR_NV1
,
4290 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
4291 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
4292 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 0,
4293 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4294 .fgt
= FGT_TTBR0_EL1
,
4295 .nv2_redirect_offset
= 0x200 | NV2_REDIR_NV1
,
4296 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0, .raw_writefn
= raw_write
,
4297 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
4298 offsetof(CPUARMState
, cp15
.ttbr0_ns
) } },
4299 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
4300 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 1,
4301 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4302 .fgt
= FGT_TTBR1_EL1
,
4303 .nv2_redirect_offset
= 0x210 | NV2_REDIR_NV1
,
4304 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0, .raw_writefn
= raw_write
,
4305 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
4306 offsetof(CPUARMState
, cp15
.ttbr1_ns
) } },
4307 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
4308 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
4309 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4311 .nv2_redirect_offset
= 0x120 | NV2_REDIR_NV1
,
4312 .writefn
= vmsa_tcr_el12_write
,
4313 .raw_writefn
= raw_write
,
4315 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[1]) },
4316 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
4317 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4318 .type
= ARM_CP_ALIAS
, .writefn
= vmsa_ttbcr_write
,
4319 .raw_writefn
= raw_write
,
4320 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tcr_el
[3]),
4321 offsetoflow32(CPUARMState
, cp15
.tcr_el
[1])} },
4325 * Note that unlike TTBCR, writing to TTBCR2 does not require flushing
4326 * qemu tlbs nor adjusting cached masks.
4328 static const ARMCPRegInfo ttbcr2_reginfo
= {
4329 .name
= "TTBCR2", .cp
= 15, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 3,
4330 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4331 .type
= ARM_CP_ALIAS
,
4332 .bank_fieldoffsets
= {
4333 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[3]),
4334 offsetofhigh32(CPUARMState
, cp15
.tcr_el
[1]),
4338 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4341 env
->cp15
.c15_ticonfig
= value
& 0xe7;
4342 /* The OS_TYPE bit in this register changes the reported CPUID! */
4343 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
4344 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
4347 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4350 env
->cp15
.c15_threadid
= value
& 0xffff;
4353 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4356 /* Wait-for-interrupt (deprecated) */
4357 cpu_interrupt(env_cpu(env
), CPU_INTERRUPT_HALT
);
4360 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4364 * On OMAP there are registers indicating the max/min index of dcache lines
4365 * containing a dirty line; cache flush operations have to reset these.
4367 env
->cp15
.c15_i_max
= 0x000;
4368 env
->cp15
.c15_i_min
= 0xff0;
4371 static const ARMCPRegInfo omap_cp_reginfo
[] = {
4372 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
4373 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
4374 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
4376 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
4377 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
4378 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
4380 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
4381 .writefn
= omap_ticonfig_write
},
4382 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
4384 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
4385 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
4386 .access
= PL1_RW
, .resetvalue
= 0xff0,
4387 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
4388 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
4390 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
4391 .writefn
= omap_threadid_write
},
4392 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
4393 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
4394 .type
= ARM_CP_NO_RAW
,
4395 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
4397 * TODO: Peripheral port remap register:
4398 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
4399 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
4402 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
4403 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
4404 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
,
4405 .writefn
= omap_cachemaint_write
},
4406 { .name
= "C9", .cp
= 15, .crn
= 9,
4407 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
4408 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
4411 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4414 env
->cp15
.c15_cpar
= value
& 0x3fff;
4417 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
4418 { .name
= "XSCALE_CPAR",
4419 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
4420 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
4421 .writefn
= xscale_cpar_write
, },
4422 { .name
= "XSCALE_AUXCR",
4423 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
4424 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
4427 * XScale specific cache-lockdown: since we have no cache we NOP these
4428 * and hope the guest does not really rely on cache behaviour.
4430 { .name
= "XSCALE_LOCK_ICACHE_LINE",
4431 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
4432 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4433 { .name
= "XSCALE_UNLOCK_ICACHE",
4434 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
4435 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4436 { .name
= "XSCALE_DCACHE_LOCK",
4437 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
4438 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
4439 { .name
= "XSCALE_UNLOCK_DCACHE",
4440 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
4441 .access
= PL1_W
, .type
= ARM_CP_NOP
},
4444 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
4446 * RAZ/WI the whole crn=15 space, when we don't have a more specific
4447 * implementation of this implementation-defined space.
4448 * Ideally this should eventually disappear in favour of actually
4449 * implementing the correct behaviour for all cores.
4451 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
4452 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
4454 .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
| ARM_CP_OVERRIDE
,
4458 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
4459 /* Cache status: RAZ because we have no cache so it's always clean */
4460 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
4461 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4465 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
4466 /* We never have a block transfer operation in progress */
4467 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
4468 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4470 /* The cache ops themselves: these all NOP for QEMU */
4471 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
4472 .access
= PL1_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4473 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
4474 .access
= PL1_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4475 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
4476 .access
= PL0_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4477 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
4478 .access
= PL0_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4479 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
4480 .access
= PL0_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4481 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
4482 .access
= PL1_W
, .type
= ARM_CP_NOP
| ARM_CP_64BIT
},
4485 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
4487 * The cache test-and-clean instructions always return (1 << 30)
4488 * to indicate that there are no dirty cache lines.
4490 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
4491 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4492 .resetvalue
= (1 << 30) },
4493 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
4494 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
4495 .resetvalue
= (1 << 30) },
4498 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
4499 /* Ignore ReadBuffer accesses */
4500 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
4501 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
4502 .access
= PL1_RW
, .resetvalue
= 0,
4503 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
},
4506 static uint64_t midr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4508 unsigned int cur_el
= arm_current_el(env
);
4510 if (arm_is_el2_enabled(env
) && cur_el
== 1) {
4511 return env
->cp15
.vpidr_el2
;
4513 return raw_read(env
, ri
);
4516 static uint64_t mpidr_read_val(CPUARMState
*env
)
4518 ARMCPU
*cpu
= env_archcpu(env
);
4519 uint64_t mpidr
= cpu
->mp_affinity
;
4521 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
4522 mpidr
|= (1U << 31);
4524 * Cores which are uniprocessor (non-coherent)
4525 * but still implement the MP extensions set
4526 * bit 30. (For instance, Cortex-R5).
4528 if (cpu
->mp_is_up
) {
4529 mpidr
|= (1u << 30);
4535 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4537 unsigned int cur_el
= arm_current_el(env
);
4539 if (arm_is_el2_enabled(env
) && cur_el
== 1) {
4540 return env
->cp15
.vmpidr_el2
;
4542 return mpidr_read_val(env
);
4545 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
4547 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
4548 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
4549 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4550 .fgt
= FGT_AMAIR_EL1
,
4551 .nv2_redirect_offset
= 0x148 | NV2_REDIR_NV1
,
4552 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4553 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
4554 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
4555 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4556 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4557 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
4558 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .resetvalue
= 0,
4559 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.par_s
),
4560 offsetof(CPUARMState
, cp15
.par_ns
)} },
4561 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
4562 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4563 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4564 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
4565 offsetof(CPUARMState
, cp15
.ttbr0_ns
) },
4566 .writefn
= vmsa_ttbr_write
, .raw_writefn
= raw_write
},
4567 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
4568 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
4569 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
4570 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
4571 offsetof(CPUARMState
, cp15
.ttbr1_ns
) },
4572 .writefn
= vmsa_ttbr_write
, .raw_writefn
= raw_write
},
4575 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4577 return vfp_get_fpcr(env
);
4580 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4583 vfp_set_fpcr(env
, value
);
4586 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4588 return vfp_get_fpsr(env
);
4591 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4594 vfp_set_fpsr(env
, value
);
4597 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4600 if (arm_current_el(env
) == 0 && !(arm_sctlr(env
, 0) & SCTLR_UMA
)) {
4601 return CP_ACCESS_TRAP
;
4603 return CP_ACCESS_OK
;
4606 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4609 env
->daif
= value
& PSTATE_DAIF
;
4612 static uint64_t aa64_pan_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4614 return env
->pstate
& PSTATE_PAN
;
4617 static void aa64_pan_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4620 env
->pstate
= (env
->pstate
& ~PSTATE_PAN
) | (value
& PSTATE_PAN
);
4623 static const ARMCPRegInfo pan_reginfo
= {
4624 .name
= "PAN", .state
= ARM_CP_STATE_AA64
,
4625 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 3,
4626 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4627 .readfn
= aa64_pan_read
, .writefn
= aa64_pan_write
4630 static uint64_t aa64_uao_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4632 return env
->pstate
& PSTATE_UAO
;
4635 static void aa64_uao_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4638 env
->pstate
= (env
->pstate
& ~PSTATE_UAO
) | (value
& PSTATE_UAO
);
4641 static const ARMCPRegInfo uao_reginfo
= {
4642 .name
= "UAO", .state
= ARM_CP_STATE_AA64
,
4643 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 4,
4644 .type
= ARM_CP_NO_RAW
, .access
= PL1_RW
,
4645 .readfn
= aa64_uao_read
, .writefn
= aa64_uao_write
4648 static uint64_t aa64_dit_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4650 return env
->pstate
& PSTATE_DIT
;
4653 static void aa64_dit_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4656 env
->pstate
= (env
->pstate
& ~PSTATE_DIT
) | (value
& PSTATE_DIT
);
4659 static const ARMCPRegInfo dit_reginfo
= {
4660 .name
= "DIT", .state
= ARM_CP_STATE_AA64
,
4661 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 5,
4662 .type
= ARM_CP_NO_RAW
, .access
= PL0_RW
,
4663 .readfn
= aa64_dit_read
, .writefn
= aa64_dit_write
4666 static uint64_t aa64_ssbs_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4668 return env
->pstate
& PSTATE_SSBS
;
4671 static void aa64_ssbs_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4674 env
->pstate
= (env
->pstate
& ~PSTATE_SSBS
) | (value
& PSTATE_SSBS
);
4677 static const ARMCPRegInfo ssbs_reginfo
= {
4678 .name
= "SSBS", .state
= ARM_CP_STATE_AA64
,
4679 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 6,
4680 .type
= ARM_CP_NO_RAW
, .access
= PL0_RW
,
4681 .readfn
= aa64_ssbs_read
, .writefn
= aa64_ssbs_write
4684 static CPAccessResult
aa64_cacheop_poc_access(CPUARMState
*env
,
4685 const ARMCPRegInfo
*ri
,
4688 /* Cache invalidate/clean to Point of Coherency or Persistence... */
4689 switch (arm_current_el(env
)) {
4691 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4692 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4693 return CP_ACCESS_TRAP
;
4697 /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */
4698 if (arm_hcr_el2_eff(env
) & HCR_TPCP
) {
4699 return CP_ACCESS_TRAP_EL2
;
4703 return CP_ACCESS_OK
;
4706 static CPAccessResult
do_cacheop_pou_access(CPUARMState
*env
, uint64_t hcrflags
)
4708 /* Cache invalidate/clean to Point of Unification... */
4709 switch (arm_current_el(env
)) {
4711 /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
4712 if (!(arm_sctlr(env
, 0) & SCTLR_UCI
)) {
4713 return CP_ACCESS_TRAP
;
4717 /* ... EL1 must trap to EL2 if relevant HCR_EL2 flags are set. */
4718 if (arm_hcr_el2_eff(env
) & hcrflags
) {
4719 return CP_ACCESS_TRAP_EL2
;
4723 return CP_ACCESS_OK
;
4726 static CPAccessResult
access_ticab(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4729 return do_cacheop_pou_access(env
, HCR_TICAB
| HCR_TPU
);
4732 static CPAccessResult
access_tocu(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4735 return do_cacheop_pou_access(env
, HCR_TOCU
| HCR_TPU
);
4739 * See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
4740 * Page D4-1736 (DDI0487A.b)
4743 static int vae1_tlbmask(CPUARMState
*env
)
4745 uint64_t hcr
= arm_hcr_el2_eff(env
);
4748 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4749 mask
= ARMMMUIdxBit_E20_2
|
4750 ARMMMUIdxBit_E20_2_PAN
|
4753 mask
= ARMMMUIdxBit_E10_1
|
4754 ARMMMUIdxBit_E10_1_PAN
|
4760 static int vae2_tlbmask(CPUARMState
*env
)
4762 uint64_t hcr
= arm_hcr_el2_eff(env
);
4765 if (hcr
& HCR_E2H
) {
4766 mask
= ARMMMUIdxBit_E20_2
|
4767 ARMMMUIdxBit_E20_2_PAN
|
4770 mask
= ARMMMUIdxBit_E2
;
4775 /* Return 56 if TBI is enabled, 64 otherwise. */
4776 static int tlbbits_for_regime(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
4779 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
4780 int tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
4781 int select
= extract64(addr
, 55, 1);
4783 return (tbi
>> select
) & 1 ? 56 : 64;
4786 static int vae1_tlbbits(CPUARMState
*env
, uint64_t addr
)
4788 uint64_t hcr
= arm_hcr_el2_eff(env
);
4791 /* Only the regime of the mmu_idx below is significant. */
4792 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
4793 mmu_idx
= ARMMMUIdx_E20_0
;
4795 mmu_idx
= ARMMMUIdx_E10_0
;
4798 return tlbbits_for_regime(env
, mmu_idx
, addr
);
4801 static int vae2_tlbbits(CPUARMState
*env
, uint64_t addr
)
4803 uint64_t hcr
= arm_hcr_el2_eff(env
);
4807 * Only the regime of the mmu_idx below is significant.
4808 * Regime EL2&0 has two ranges with separate TBI configuration, while EL2
4811 if (hcr
& HCR_E2H
) {
4812 mmu_idx
= ARMMMUIdx_E20_2
;
4814 mmu_idx
= ARMMMUIdx_E2
;
4817 return tlbbits_for_regime(env
, mmu_idx
, addr
);
4820 static void tlbi_aa64_vmalle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4823 CPUState
*cs
= env_cpu(env
);
4824 int mask
= vae1_tlbmask(env
);
4826 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4829 static void tlbi_aa64_vmalle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4832 CPUState
*cs
= env_cpu(env
);
4833 int mask
= vae1_tlbmask(env
);
4835 if (tlb_force_broadcast(env
)) {
4836 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4838 tlb_flush_by_mmuidx(cs
, mask
);
4842 static int e2_tlbmask(CPUARMState
*env
)
4844 return (ARMMMUIdxBit_E20_0
|
4845 ARMMMUIdxBit_E20_2
|
4846 ARMMMUIdxBit_E20_2_PAN
|
4850 static void tlbi_aa64_alle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4853 CPUState
*cs
= env_cpu(env
);
4854 int mask
= alle1_tlbmask(env
);
4856 tlb_flush_by_mmuidx(cs
, mask
);
4859 static void tlbi_aa64_alle2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4862 CPUState
*cs
= env_cpu(env
);
4863 int mask
= e2_tlbmask(env
);
4865 tlb_flush_by_mmuidx(cs
, mask
);
4868 static void tlbi_aa64_alle3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4871 ARMCPU
*cpu
= env_archcpu(env
);
4872 CPUState
*cs
= CPU(cpu
);
4874 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_E3
);
4877 static void tlbi_aa64_alle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4880 CPUState
*cs
= env_cpu(env
);
4881 int mask
= alle1_tlbmask(env
);
4883 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4886 static void tlbi_aa64_alle2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4889 CPUState
*cs
= env_cpu(env
);
4890 int mask
= e2_tlbmask(env
);
4892 tlb_flush_by_mmuidx_all_cpus_synced(cs
, mask
);
4895 static void tlbi_aa64_alle3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4898 CPUState
*cs
= env_cpu(env
);
4900 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_E3
);
4903 static void tlbi_aa64_vae2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4907 * Invalidate by VA, EL2
4908 * Currently handles both VAE2 and VALE2, since we don't support
4909 * flush-last-level-only.
4911 CPUState
*cs
= env_cpu(env
);
4912 int mask
= vae2_tlbmask(env
);
4913 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4914 int bits
= vae2_tlbbits(env
, pageaddr
);
4916 tlb_flush_page_bits_by_mmuidx(cs
, pageaddr
, mask
, bits
);
4919 static void tlbi_aa64_vae3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4923 * Invalidate by VA, EL3
4924 * Currently handles both VAE3 and VALE3, since we don't support
4925 * flush-last-level-only.
4927 ARMCPU
*cpu
= env_archcpu(env
);
4928 CPUState
*cs
= CPU(cpu
);
4929 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4931 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_E3
);
4934 static void tlbi_aa64_vae1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4937 CPUState
*cs
= env_cpu(env
);
4938 int mask
= vae1_tlbmask(env
);
4939 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4940 int bits
= vae1_tlbbits(env
, pageaddr
);
4942 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4945 static void tlbi_aa64_vae1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4949 * Invalidate by VA, EL1&0 (AArch64 version).
4950 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
4951 * since we don't support flush-for-specific-ASID-only or
4952 * flush-last-level-only.
4954 CPUState
*cs
= env_cpu(env
);
4955 int mask
= vae1_tlbmask(env
);
4956 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4957 int bits
= vae1_tlbbits(env
, pageaddr
);
4959 if (tlb_force_broadcast(env
)) {
4960 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4962 tlb_flush_page_bits_by_mmuidx(cs
, pageaddr
, mask
, bits
);
4966 static void tlbi_aa64_vae2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4969 CPUState
*cs
= env_cpu(env
);
4970 int mask
= vae2_tlbmask(env
);
4971 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4972 int bits
= vae2_tlbbits(env
, pageaddr
);
4974 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
, bits
);
4977 static void tlbi_aa64_vae3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4980 CPUState
*cs
= env_cpu(env
);
4981 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
4982 int bits
= tlbbits_for_regime(env
, ARMMMUIdx_E3
, pageaddr
);
4984 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
4985 ARMMMUIdxBit_E3
, bits
);
4988 static int ipas2e1_tlbmask(CPUARMState
*env
, int64_t value
)
4991 * The MSB of value is the NS field, which only applies if SEL2
4992 * is implemented and SCR_EL3.NS is not set (i.e. in secure mode).
4995 && cpu_isar_feature(aa64_sel2
, env_archcpu(env
))
4996 && arm_is_secure_below_el3(env
)
4997 ? ARMMMUIdxBit_Stage2_S
4998 : ARMMMUIdxBit_Stage2
);
5001 static void tlbi_aa64_ipas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5004 CPUState
*cs
= env_cpu(env
);
5005 int mask
= ipas2e1_tlbmask(env
, value
);
5006 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
5008 if (tlb_force_broadcast(env
)) {
5009 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
);
5011 tlb_flush_page_by_mmuidx(cs
, pageaddr
, mask
);
5015 static void tlbi_aa64_ipas2e1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5018 CPUState
*cs
= env_cpu(env
);
5019 int mask
= ipas2e1_tlbmask(env
, value
);
5020 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
5022 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
, mask
);
5025 #ifdef TARGET_AARCH64
5031 static ARMGranuleSize
tlbi_range_tg_to_gran_size(int tg
)
5034 * Note that the TLBI range TG field encoding differs from both
5035 * TG0 and TG1 encodings.
5049 static TLBIRange
tlbi_aa64_get_range(CPUARMState
*env
, ARMMMUIdx mmuidx
,
5052 unsigned int page_size_granule
, page_shift
, num
, scale
, exponent
;
5053 /* Extract one bit to represent the va selector in use. */
5054 uint64_t select
= sextract64(value
, 36, 1);
5055 ARMVAParameters param
= aa64_va_parameters(env
, select
, mmuidx
, true, false);
5056 TLBIRange ret
= { };
5057 ARMGranuleSize gran
;
5059 page_size_granule
= extract64(value
, 46, 2);
5060 gran
= tlbi_range_tg_to_gran_size(page_size_granule
);
5062 /* The granule encoded in value must match the granule in use. */
5063 if (gran
!= param
.gran
) {
5064 qemu_log_mask(LOG_GUEST_ERROR
, "Invalid tlbi page size granule %d\n",
5069 page_shift
= arm_granule_bits(gran
);
5070 num
= extract64(value
, 39, 5);
5071 scale
= extract64(value
, 44, 2);
5072 exponent
= (5 * scale
) + 1;
5074 ret
.length
= (num
+ 1) << (exponent
+ page_shift
);
5077 ret
.base
= sextract64(value
, 0, 37);
5079 ret
.base
= extract64(value
, 0, 37);
5083 * With DS=1, BaseADDR is always shifted 16 so that it is able
5084 * to address all 52 va bits. The input address is perforce
5085 * aligned on a 64k boundary regardless of translation granule.
5089 ret
.base
<<= page_shift
;
5094 static void do_rvae_write(CPUARMState
*env
, uint64_t value
,
5095 int idxmap
, bool synced
)
5097 ARMMMUIdx one_idx
= ARM_MMU_IDX_A
| ctz32(idxmap
);
5101 range
= tlbi_aa64_get_range(env
, one_idx
, value
);
5102 bits
= tlbbits_for_regime(env
, one_idx
, range
.base
);
5105 tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env
),
5111 tlb_flush_range_by_mmuidx(env_cpu(env
), range
.base
,
5112 range
.length
, idxmap
, bits
);
5116 static void tlbi_aa64_rvae1_write(CPUARMState
*env
,
5117 const ARMCPRegInfo
*ri
,
5121 * Invalidate by VA range, EL1&0.
5122 * Currently handles all of RVAE1, RVAAE1, RVAALE1 and RVALE1,
5123 * since we don't support flush-for-specific-ASID-only or
5124 * flush-last-level-only.
5127 do_rvae_write(env
, value
, vae1_tlbmask(env
),
5128 tlb_force_broadcast(env
));
5131 static void tlbi_aa64_rvae1is_write(CPUARMState
*env
,
5132 const ARMCPRegInfo
*ri
,
5136 * Invalidate by VA range, Inner/Outer Shareable EL1&0.
5137 * Currently handles all of RVAE1IS, RVAE1OS, RVAAE1IS, RVAAE1OS,
5138 * RVAALE1IS, RVAALE1OS, RVALE1IS and RVALE1OS, since we don't support
5139 * flush-for-specific-ASID-only, flush-last-level-only or inner/outer
5140 * shareable specific flushes.
5143 do_rvae_write(env
, value
, vae1_tlbmask(env
), true);
5146 static void tlbi_aa64_rvae2_write(CPUARMState
*env
,
5147 const ARMCPRegInfo
*ri
,
5151 * Invalidate by VA range, EL2.
5152 * Currently handles all of RVAE2 and RVALE2,
5153 * since we don't support flush-for-specific-ASID-only or
5154 * flush-last-level-only.
5157 do_rvae_write(env
, value
, vae2_tlbmask(env
),
5158 tlb_force_broadcast(env
));
5163 static void tlbi_aa64_rvae2is_write(CPUARMState
*env
,
5164 const ARMCPRegInfo
*ri
,
5168 * Invalidate by VA range, Inner/Outer Shareable, EL2.
5169 * Currently handles all of RVAE2IS, RVAE2OS, RVALE2IS and RVALE2OS,
5170 * since we don't support flush-for-specific-ASID-only,
5171 * flush-last-level-only or inner/outer shareable specific flushes.
5174 do_rvae_write(env
, value
, vae2_tlbmask(env
), true);
5178 static void tlbi_aa64_rvae3_write(CPUARMState
*env
,
5179 const ARMCPRegInfo
*ri
,
5183 * Invalidate by VA range, EL3.
5184 * Currently handles all of RVAE3 and RVALE3,
5185 * since we don't support flush-for-specific-ASID-only or
5186 * flush-last-level-only.
5189 do_rvae_write(env
, value
, ARMMMUIdxBit_E3
, tlb_force_broadcast(env
));
5192 static void tlbi_aa64_rvae3is_write(CPUARMState
*env
,
5193 const ARMCPRegInfo
*ri
,
5197 * Invalidate by VA range, EL3, Inner/Outer Shareable.
5198 * Currently handles all of RVAE3IS, RVAE3OS, RVALE3IS and RVALE3OS,
5199 * since we don't support flush-for-specific-ASID-only,
5200 * flush-last-level-only or inner/outer specific flushes.
5203 do_rvae_write(env
, value
, ARMMMUIdxBit_E3
, true);
5206 static void tlbi_aa64_ripas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5209 do_rvae_write(env
, value
, ipas2e1_tlbmask(env
, value
),
5210 tlb_force_broadcast(env
));
5213 static void tlbi_aa64_ripas2e1is_write(CPUARMState
*env
,
5214 const ARMCPRegInfo
*ri
,
5217 do_rvae_write(env
, value
, ipas2e1_tlbmask(env
, value
), true);
5221 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5224 int cur_el
= arm_current_el(env
);
5227 uint64_t hcr
= arm_hcr_el2_eff(env
);
5230 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
5231 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_DZE
)) {
5232 return CP_ACCESS_TRAP_EL2
;
5235 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_DZE
)) {
5236 return CP_ACCESS_TRAP
;
5238 if (hcr
& HCR_TDZ
) {
5239 return CP_ACCESS_TRAP_EL2
;
5242 } else if (hcr
& HCR_TDZ
) {
5243 return CP_ACCESS_TRAP_EL2
;
5246 return CP_ACCESS_OK
;
5249 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5251 ARMCPU
*cpu
= env_archcpu(env
);
5252 int dzp_bit
= 1 << 4;
5254 /* DZP indicates whether DC ZVA access is allowed */
5255 if (aa64_zva_access(env
, NULL
, false) == CP_ACCESS_OK
) {
5258 return cpu
->dcz_blocksize
| dzp_bit
;
5261 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5264 if (!(env
->pstate
& PSTATE_SP
)) {
5266 * Access to SP_EL0 is undefined if it's being used as
5267 * the stack pointer.
5269 return CP_ACCESS_TRAP_UNCATEGORIZED
;
5271 return CP_ACCESS_OK
;
5274 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5276 return env
->pstate
& PSTATE_SP
;
5279 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
5281 update_spsel(env
, val
);
5284 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5287 ARMCPU
*cpu
= env_archcpu(env
);
5289 if (arm_feature(env
, ARM_FEATURE_PMSA
) && !cpu
->has_mpu
) {
5290 /* M bit is RAZ/WI for PMSA with no MPU implemented */
5294 /* ??? Lots of these bits are not implemented. */
5296 if (ri
->state
== ARM_CP_STATE_AA64
&& !cpu_isar_feature(aa64_mte
, cpu
)) {
5297 if (ri
->opc1
== 6) { /* SCTLR_EL3 */
5298 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF
| SCTLR_ATA
);
5300 value
&= ~(SCTLR_ITFSB
| SCTLR_TCF0
| SCTLR_TCF
|
5301 SCTLR_ATA0
| SCTLR_ATA
);
5305 if (raw_read(env
, ri
) == value
) {
5307 * Skip the TLB flush if nothing actually changed; Linux likes
5308 * to do a lot of pointless SCTLR writes.
5313 raw_write(env
, ri
, value
);
5315 /* This may enable/disable the MMU, so do a TLB flush. */
5316 tlb_flush(CPU(cpu
));
5318 if (tcg_enabled() && ri
->type
& ARM_CP_SUPPRESS_TB_END
) {
5320 * Normally we would always end the TB on an SCTLR write; see the
5321 * comment in ARMCPRegInfo sctlr initialization below for why Xscale
5322 * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebuild
5323 * of hflags from the translator, so do it here.
5325 arm_rebuild_hflags(env
);
5329 static void mdcr_el3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5333 * Some MDCR_EL3 bits affect whether PMU counters are running:
5334 * if we are trying to change any of those then we must
5335 * bracket this update with PMU start/finish calls.
5337 bool pmu_op
= (env
->cp15
.mdcr_el3
^ value
) & MDCR_EL3_PMU_ENABLE_BITS
;
5342 env
->cp15
.mdcr_el3
= value
;
5348 static void sdcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5351 /* Not all bits defined for MDCR_EL3 exist in the AArch32 SDCR */
5352 mdcr_el3_write(env
, ri
, value
& SDCR_VALID_MASK
);
5355 static void mdcr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5359 * Some MDCR_EL2 bits affect whether PMU counters are running:
5360 * if we are trying to change any of those then we must
5361 * bracket this update with PMU start/finish calls.
5363 bool pmu_op
= (env
->cp15
.mdcr_el2
^ value
) & MDCR_EL2_PMU_ENABLE_BITS
;
5368 env
->cp15
.mdcr_el2
= value
;
5374 static CPAccessResult
access_nv1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5377 if (arm_current_el(env
) == 1) {
5378 uint64_t hcr_nv
= arm_hcr_el2_eff(env
) & (HCR_NV
| HCR_NV1
| HCR_NV2
);
5380 if (hcr_nv
== (HCR_NV
| HCR_NV1
)) {
5381 return CP_ACCESS_TRAP_EL2
;
5384 return CP_ACCESS_OK
;
5387 #ifdef CONFIG_USER_ONLY
5389 * `IC IVAU` is handled to improve compatibility with JITs that dual-map their
5390 * code to get around W^X restrictions, where one region is writable and the
5391 * other is executable.
5393 * Since the executable region is never written to we cannot detect code
5394 * changes when running in user mode, and rely on the emulated JIT telling us
5395 * that the code has changed by executing this instruction.
5397 static void ic_ivau_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5400 uint64_t icache_line_mask
, start_address
, end_address
;
5403 cpu
= env_archcpu(env
);
5405 icache_line_mask
= (4 << extract32(cpu
->ctr
, 0, 4)) - 1;
5406 start_address
= value
& ~icache_line_mask
;
5407 end_address
= value
| icache_line_mask
;
5411 tb_invalidate_phys_range(start_address
, end_address
);
5417 static const ARMCPRegInfo v8_cp_reginfo
[] = {
5419 * Minimal set of EL0-visible registers. This will need to be expanded
5420 * significantly for system emulation of AArch64 CPUs.
5422 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
5423 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
5424 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
5425 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
5426 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
5427 .type
= ARM_CP_NO_RAW
,
5428 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
5429 .fieldoffset
= offsetof(CPUARMState
, daif
),
5430 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
5431 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
5432 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
5433 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
5434 .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
5435 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
5436 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
5437 .access
= PL0_RW
, .type
= ARM_CP_FPU
| ARM_CP_SUPPRESS_TB_END
,
5438 .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
5439 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
5440 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
5441 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
,
5442 .fgt
= FGT_DCZID_EL0
,
5443 .readfn
= aa64_dczid_read
},
5444 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
5445 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
5446 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
5447 #ifndef CONFIG_USER_ONLY
5448 /* Avoid overhead of an access check that always passes in user-mode */
5449 .accessfn
= aa64_zva_access
,
5453 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
5454 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
5455 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
5457 * Instruction cache ops. All of these except `IC IVAU` NOP because we
5458 * don't emulate caches.
5460 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
5461 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
5462 .access
= PL1_W
, .type
= ARM_CP_NOP
,
5463 .fgt
= FGT_ICIALLUIS
,
5464 .accessfn
= access_ticab
},
5465 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
5466 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
5467 .access
= PL1_W
, .type
= ARM_CP_NOP
,
5469 .accessfn
= access_tocu
},
5470 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
5471 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
5474 .accessfn
= access_tocu
,
5475 #ifdef CONFIG_USER_ONLY
5476 .type
= ARM_CP_NO_RAW
,
5477 .writefn
= ic_ivau_write
5482 /* Cache ops: all NOPs since we don't emulate caches */
5483 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
5484 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
5485 .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
,
5487 .type
= ARM_CP_NOP
},
5488 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
5489 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
5491 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
5492 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
5493 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
5494 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5496 .accessfn
= aa64_cacheop_poc_access
},
5497 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
5498 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
5500 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
5501 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
5502 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
5503 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5505 .accessfn
= access_tocu
},
5506 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
5507 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
5508 .access
= PL0_W
, .type
= ARM_CP_NOP
,
5510 .accessfn
= aa64_cacheop_poc_access
},
5511 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
5512 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
5514 .access
= PL1_W
, .accessfn
= access_tsw
, .type
= ARM_CP_NOP
},
5515 /* TLBI operations */
5516 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
5517 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
5518 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5519 .fgt
= FGT_TLBIVMALLE1IS
,
5520 .writefn
= tlbi_aa64_vmalle1is_write
},
5521 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
5522 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
5523 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5524 .fgt
= FGT_TLBIVAE1IS
,
5525 .writefn
= tlbi_aa64_vae1is_write
},
5526 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
5527 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
5528 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5529 .fgt
= FGT_TLBIASIDE1IS
,
5530 .writefn
= tlbi_aa64_vmalle1is_write
},
5531 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
5532 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
5533 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5534 .fgt
= FGT_TLBIVAAE1IS
,
5535 .writefn
= tlbi_aa64_vae1is_write
},
5536 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
5537 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
5538 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5539 .fgt
= FGT_TLBIVALE1IS
,
5540 .writefn
= tlbi_aa64_vae1is_write
},
5541 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
5542 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
5543 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
5544 .fgt
= FGT_TLBIVAALE1IS
,
5545 .writefn
= tlbi_aa64_vae1is_write
},
5546 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
5547 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
5548 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5549 .fgt
= FGT_TLBIVMALLE1
,
5550 .writefn
= tlbi_aa64_vmalle1_write
},
5551 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
5552 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
5553 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5554 .fgt
= FGT_TLBIVAE1
,
5555 .writefn
= tlbi_aa64_vae1_write
},
5556 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
5557 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
5558 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5559 .fgt
= FGT_TLBIASIDE1
,
5560 .writefn
= tlbi_aa64_vmalle1_write
},
5561 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
5562 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
5563 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5564 .fgt
= FGT_TLBIVAAE1
,
5565 .writefn
= tlbi_aa64_vae1_write
},
5566 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
5567 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
5568 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5569 .fgt
= FGT_TLBIVALE1
,
5570 .writefn
= tlbi_aa64_vae1_write
},
5571 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
5572 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
5573 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
5574 .fgt
= FGT_TLBIVAALE1
,
5575 .writefn
= tlbi_aa64_vae1_write
},
5576 { .name
= "TLBI_IPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
5577 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
5578 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5579 .writefn
= tlbi_aa64_ipas2e1is_write
},
5580 { .name
= "TLBI_IPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
5581 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
5582 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5583 .writefn
= tlbi_aa64_ipas2e1is_write
},
5584 { .name
= "TLBI_ALLE1IS", .state
= ARM_CP_STATE_AA64
,
5585 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
5586 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5587 .writefn
= tlbi_aa64_alle1is_write
},
5588 { .name
= "TLBI_VMALLS12E1IS", .state
= ARM_CP_STATE_AA64
,
5589 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 6,
5590 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5591 .writefn
= tlbi_aa64_alle1is_write
},
5592 { .name
= "TLBI_IPAS2E1", .state
= ARM_CP_STATE_AA64
,
5593 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
5594 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5595 .writefn
= tlbi_aa64_ipas2e1_write
},
5596 { .name
= "TLBI_IPAS2LE1", .state
= ARM_CP_STATE_AA64
,
5597 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
5598 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5599 .writefn
= tlbi_aa64_ipas2e1_write
},
5600 { .name
= "TLBI_ALLE1", .state
= ARM_CP_STATE_AA64
,
5601 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
5602 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5603 .writefn
= tlbi_aa64_alle1_write
},
5604 { .name
= "TLBI_VMALLS12E1", .state
= ARM_CP_STATE_AA64
,
5605 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 6,
5606 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
5607 .writefn
= tlbi_aa64_alle1is_write
},
5608 #ifndef CONFIG_USER_ONLY
5609 /* 64 bit address translation operations */
5610 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
5611 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
5612 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5614 .accessfn
= at_s1e01_access
, .writefn
= ats_write64
},
5615 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
5616 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
5617 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5619 .accessfn
= at_s1e01_access
, .writefn
= ats_write64
},
5620 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
5621 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
5622 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5624 .accessfn
= at_s1e01_access
, .writefn
= ats_write64
},
5625 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
5626 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
5627 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5629 .accessfn
= at_s1e01_access
, .writefn
= ats_write64
},
5630 { .name
= "AT_S12E1R", .state
= ARM_CP_STATE_AA64
,
5631 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 4,
5632 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5633 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5634 { .name
= "AT_S12E1W", .state
= ARM_CP_STATE_AA64
,
5635 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 5,
5636 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5637 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5638 { .name
= "AT_S12E0R", .state
= ARM_CP_STATE_AA64
,
5639 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 6,
5640 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5641 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5642 { .name
= "AT_S12E0W", .state
= ARM_CP_STATE_AA64
,
5643 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 7,
5644 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5645 .accessfn
= at_e012_access
, .writefn
= ats_write64
},
5646 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
5647 { .name
= "AT_S1E3R", .state
= ARM_CP_STATE_AA64
,
5648 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 0,
5649 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5650 .writefn
= ats_write64
},
5651 { .name
= "AT_S1E3W", .state
= ARM_CP_STATE_AA64
,
5652 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 1,
5653 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
5654 .writefn
= ats_write64
},
5655 { .name
= "PAR_EL1", .state
= ARM_CP_STATE_AA64
,
5656 .type
= ARM_CP_ALIAS
,
5657 .opc0
= 3, .opc1
= 0, .crn
= 7, .crm
= 4, .opc2
= 0,
5658 .access
= PL1_RW
, .resetvalue
= 0,
5660 .fieldoffset
= offsetof(CPUARMState
, cp15
.par_el
[1]),
5661 .writefn
= par_write
},
5663 /* TLB invalidate last level of translation table walk */
5664 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
5665 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
5666 .writefn
= tlbimva_is_write
},
5667 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
5668 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlbis
,
5669 .writefn
= tlbimvaa_is_write
},
5670 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
5671 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
5672 .writefn
= tlbimva_write
},
5673 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
5674 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .accessfn
= access_ttlb
,
5675 .writefn
= tlbimvaa_write
},
5676 { .name
= "TLBIMVALH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
5677 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5678 .writefn
= tlbimva_hyp_write
},
5679 { .name
= "TLBIMVALHIS",
5680 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
5681 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5682 .writefn
= tlbimva_hyp_is_write
},
5683 { .name
= "TLBIIPAS2",
5684 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
5685 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5686 .writefn
= tlbiipas2_hyp_write
},
5687 { .name
= "TLBIIPAS2IS",
5688 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
5689 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5690 .writefn
= tlbiipas2is_hyp_write
},
5691 { .name
= "TLBIIPAS2L",
5692 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
5693 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5694 .writefn
= tlbiipas2_hyp_write
},
5695 { .name
= "TLBIIPAS2LIS",
5696 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
5697 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
5698 .writefn
= tlbiipas2is_hyp_write
},
5699 /* 32 bit cache operations */
5700 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
5701 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_ticab
},
5702 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
5703 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5704 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
5705 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tocu
},
5706 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
5707 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tocu
},
5708 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
5709 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5710 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
5711 .type
= ARM_CP_NOP
, .access
= PL1_W
},
5712 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
5713 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5714 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
5715 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5716 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
5717 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5718 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
5719 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5720 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
5721 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tocu
},
5722 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
5723 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= aa64_cacheop_poc_access
},
5724 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
5725 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
5726 /* MMU Domain access control / MPU write buffer control */
5727 { .name
= "DACR", .cp
= 15, .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
5728 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
, .resetvalue
= 0,
5729 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5730 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
5731 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
5732 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
5733 .type
= ARM_CP_ALIAS
,
5734 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
5735 .access
= PL1_RW
, .accessfn
= access_nv1
,
5736 .nv2_redirect_offset
= 0x230 | NV2_REDIR_NV1
,
5737 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
5738 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
5739 .type
= ARM_CP_ALIAS
,
5740 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
5741 .access
= PL1_RW
, .accessfn
= access_nv1
,
5742 .nv2_redirect_offset
= 0x160 | NV2_REDIR_NV1
,
5743 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_SVC
]) },
5745 * We rely on the access checks not allowing the guest to write to the
5746 * state field when SPSel indicates that it's being used as the stack
5749 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
5750 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
5751 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
5752 .type
= ARM_CP_ALIAS
,
5753 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
5754 { .name
= "SP_EL1", .state
= ARM_CP_STATE_AA64
,
5755 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 1, .opc2
= 0,
5756 .nv2_redirect_offset
= 0x240,
5757 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_KEEP
,
5758 .fieldoffset
= offsetof(CPUARMState
, sp_el
[1]) },
5759 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
5760 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
5761 .type
= ARM_CP_NO_RAW
,
5762 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
5763 { .name
= "SPSR_IRQ", .state
= ARM_CP_STATE_AA64
,
5764 .type
= ARM_CP_ALIAS
,
5765 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 0,
5767 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_IRQ
]) },
5768 { .name
= "SPSR_ABT", .state
= ARM_CP_STATE_AA64
,
5769 .type
= ARM_CP_ALIAS
,
5770 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 1,
5772 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_ABT
]) },
5773 { .name
= "SPSR_UND", .state
= ARM_CP_STATE_AA64
,
5774 .type
= ARM_CP_ALIAS
,
5775 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 2,
5777 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_UND
]) },
5778 { .name
= "SPSR_FIQ", .state
= ARM_CP_STATE_AA64
,
5779 .type
= ARM_CP_ALIAS
,
5780 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 3,
5782 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_FIQ
]) },
5783 { .name
= "MDCR_EL3", .state
= ARM_CP_STATE_AA64
,
5785 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 3, .opc2
= 1,
5788 .writefn
= mdcr_el3_write
,
5789 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el3
) },
5790 { .name
= "SDCR", .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
5791 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 1,
5792 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
5793 .writefn
= sdcr_write
,
5794 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.mdcr_el3
) },
5797 /* These are present only when EL1 supports AArch32 */
5798 static const ARMCPRegInfo v8_aa32_el1_reginfo
[] = {
5799 { .name
= "FPEXC32_EL2", .state
= ARM_CP_STATE_AA64
,
5800 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 3, .opc2
= 0,
5802 .type
= ARM_CP_ALIAS
| ARM_CP_FPU
| ARM_CP_EL3_NO_EL2_KEEP
,
5803 .fieldoffset
= offsetof(CPUARMState
, vfp
.xregs
[ARM_VFP_FPEXC
]) },
5804 { .name
= "DACR32_EL2", .state
= ARM_CP_STATE_AA64
,
5805 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 0, .opc2
= 0,
5806 .access
= PL2_RW
, .resetvalue
= 0, .type
= ARM_CP_EL3_NO_EL2_KEEP
,
5807 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
5808 .fieldoffset
= offsetof(CPUARMState
, cp15
.dacr32_el2
) },
5809 { .name
= "IFSR32_EL2", .state
= ARM_CP_STATE_AA64
,
5810 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 0, .opc2
= 1,
5811 .access
= PL2_RW
, .resetvalue
= 0, .type
= ARM_CP_EL3_NO_EL2_KEEP
,
5812 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr32_el2
) },
5815 static void do_hcr_write(CPUARMState
*env
, uint64_t value
, uint64_t valid_mask
)
5817 ARMCPU
*cpu
= env_archcpu(env
);
5819 if (arm_feature(env
, ARM_FEATURE_V8
)) {
5820 valid_mask
|= MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */
5822 valid_mask
|= MAKE_64BIT_MASK(0, 28); /* ARMv7VE */
5825 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5826 valid_mask
&= ~HCR_HCD
;
5827 } else if (cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
5829 * Architecturally HCR.TSC is RES0 if EL3 is not implemented.
5830 * However, if we're using the SMC PSCI conduit then QEMU is
5831 * effectively acting like EL3 firmware and so the guest at
5832 * EL2 should retain the ability to prevent EL1 from being
5833 * able to make SMC calls into the ersatz firmware, so in
5834 * that case HCR.TSC should be read/write.
5836 valid_mask
&= ~HCR_TSC
;
5839 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5840 if (cpu_isar_feature(aa64_vh
, cpu
)) {
5841 valid_mask
|= HCR_E2H
;
5843 if (cpu_isar_feature(aa64_ras
, cpu
)) {
5844 valid_mask
|= HCR_TERR
| HCR_TEA
;
5846 if (cpu_isar_feature(aa64_lor
, cpu
)) {
5847 valid_mask
|= HCR_TLOR
;
5849 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
5850 valid_mask
|= HCR_API
| HCR_APK
;
5852 if (cpu_isar_feature(aa64_mte
, cpu
)) {
5853 valid_mask
|= HCR_ATA
| HCR_DCT
| HCR_TID5
;
5855 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
5856 valid_mask
|= HCR_ENSCXT
;
5858 if (cpu_isar_feature(aa64_fwb
, cpu
)) {
5859 valid_mask
|= HCR_FWB
;
5861 if (cpu_isar_feature(aa64_rme
, cpu
)) {
5862 valid_mask
|= HCR_GPF
;
5864 if (cpu_isar_feature(aa64_nv
, cpu
)) {
5865 valid_mask
|= HCR_NV
| HCR_NV1
| HCR_AT
;
5867 if (cpu_isar_feature(aa64_nv2
, cpu
)) {
5868 valid_mask
|= HCR_NV2
;
5872 if (cpu_isar_feature(any_evt
, cpu
)) {
5873 valid_mask
|= HCR_TTLBIS
| HCR_TTLBOS
| HCR_TICAB
| HCR_TOCU
| HCR_TID4
;
5874 } else if (cpu_isar_feature(any_half_evt
, cpu
)) {
5875 valid_mask
|= HCR_TICAB
| HCR_TOCU
| HCR_TID4
;
5878 /* Clear RES0 bits. */
5879 value
&= valid_mask
;
5882 * These bits change the MMU setup:
5883 * HCR_VM enables stage 2 translation
5884 * HCR_PTW forbids certain page-table setups
5885 * HCR_DC disables stage1 and enables stage2 translation
5886 * HCR_DCT enables tagging on (disabled) stage1 translation
5887 * HCR_FWB changes the interpretation of stage2 descriptor bits
5888 * HCR_NV and HCR_NV1 affect interpretation of descriptor bits
5890 if ((env
->cp15
.hcr_el2
^ value
) &
5891 (HCR_VM
| HCR_PTW
| HCR_DC
| HCR_DCT
| HCR_FWB
| HCR_NV
| HCR_NV1
)) {
5892 tlb_flush(CPU(cpu
));
5894 env
->cp15
.hcr_el2
= value
;
5897 * Updates to VI and VF require us to update the status of
5898 * virtual interrupts, which are the logical OR of these bits
5899 * and the state of the input lines from the GIC. (This requires
5900 * that we have the BQL, which is done by marking the
5901 * reginfo structs as ARM_CP_IO.)
5902 * Note that if a write to HCR pends a VIRQ or VFIQ it is never
5903 * possible for it to be taken immediately, because VIRQ and
5904 * VFIQ are masked unless running at EL0 or EL1, and HCR
5905 * can only be written at EL2.
5907 g_assert(bql_locked());
5908 arm_cpu_update_virq(cpu
);
5909 arm_cpu_update_vfiq(cpu
);
5910 arm_cpu_update_vserr(cpu
);
5913 static void hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
5915 do_hcr_write(env
, value
, 0);
5918 static void hcr_writehigh(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5921 /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */
5922 value
= deposit64(env
->cp15
.hcr_el2
, 32, 32, value
);
5923 do_hcr_write(env
, value
, MAKE_64BIT_MASK(0, 32));
5926 static void hcr_writelow(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5929 /* Handle HCR write, i.e. write to low half of HCR_EL2 */
5930 value
= deposit64(env
->cp15
.hcr_el2
, 0, 32, value
);
5931 do_hcr_write(env
, value
, MAKE_64BIT_MASK(32, 32));
5935 * Return the effective value of HCR_EL2, at the given security state.
5936 * Bits that are not included here:
5937 * RW (read from SCR_EL3.RW as needed)
5939 uint64_t arm_hcr_el2_eff_secstate(CPUARMState
*env
, ARMSecuritySpace space
)
5941 uint64_t ret
= env
->cp15
.hcr_el2
;
5943 assert(space
!= ARMSS_Root
);
5945 if (!arm_is_el2_enabled_secstate(env
, space
)) {
5947 * "This register has no effect if EL2 is not enabled in the
5948 * current Security state". This is ARMv8.4-SecEL2 speak for
5949 * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1).
5951 * Prior to that, the language was "In an implementation that
5952 * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
5953 * as if this field is 0 for all purposes other than a direct
5954 * read or write access of HCR_EL2". With lots of enumeration
5955 * on a per-field basis. In current QEMU, this is condition
5956 * is arm_is_secure_below_el3.
5958 * Since the v8.4 language applies to the entire register, and
5959 * appears to be backward compatible, use that.
5965 * For a cpu that supports both aarch64 and aarch32, we can set bits
5966 * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32.
5967 * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32.
5969 if (!arm_el_is_aa64(env
, 2)) {
5970 uint64_t aa32_valid
;
5973 * These bits are up-to-date as of ARMv8.6.
5974 * For HCR, it's easiest to list just the 2 bits that are invalid.
5975 * For HCR2, list those that are valid.
5977 aa32_valid
= MAKE_64BIT_MASK(0, 32) & ~(HCR_RW
| HCR_TDZ
);
5978 aa32_valid
|= (HCR_CD
| HCR_ID
| HCR_TERR
| HCR_TEA
| HCR_MIOCNCE
|
5979 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_TTLBIS
);
5983 if (ret
& HCR_TGE
) {
5984 /* These bits are up-to-date as of ARMv8.6. */
5985 if (ret
& HCR_E2H
) {
5986 ret
&= ~(HCR_VM
| HCR_FMO
| HCR_IMO
| HCR_AMO
|
5987 HCR_BSU_MASK
| HCR_DC
| HCR_TWI
| HCR_TWE
|
5988 HCR_TID0
| HCR_TID2
| HCR_TPCP
| HCR_TPU
|
5989 HCR_TDZ
| HCR_CD
| HCR_ID
| HCR_MIOCNCE
|
5990 HCR_TID4
| HCR_TICAB
| HCR_TOCU
| HCR_ENSCXT
|
5991 HCR_TTLBIS
| HCR_TTLBOS
| HCR_TID5
);
5993 ret
|= HCR_FMO
| HCR_IMO
| HCR_AMO
;
5995 ret
&= ~(HCR_SWIO
| HCR_PTW
| HCR_VF
| HCR_VI
| HCR_VSE
|
5996 HCR_FB
| HCR_TID1
| HCR_TID3
| HCR_TSC
| HCR_TACR
|
5997 HCR_TSW
| HCR_TTLB
| HCR_TVM
| HCR_HCD
| HCR_TRVM
|
6004 uint64_t arm_hcr_el2_eff(CPUARMState
*env
)
6006 if (arm_feature(env
, ARM_FEATURE_M
)) {
6009 return arm_hcr_el2_eff_secstate(env
, arm_security_space_below_el3(env
));
6013 * Corresponds to ARM pseudocode function ELIsInHost().
6015 bool el_is_in_host(CPUARMState
*env
, int el
)
6020 * Since we only care about E2H and TGE, we can skip arm_hcr_el2_eff().
6021 * Perform the simplest bit tests first, and validate EL2 afterward.
6024 return false; /* EL1 or EL3 */
6028 * Note that hcr_write() checks isar_feature_aa64_vh(),
6029 * aka HaveVirtHostExt(), in allowing HCR_E2H to be set.
6031 mask
= el
? HCR_E2H
: HCR_E2H
| HCR_TGE
;
6032 if ((env
->cp15
.hcr_el2
& mask
) != mask
) {
6036 /* TGE and/or E2H set: double check those bits are currently legal. */
6037 return arm_is_el2_enabled(env
) && arm_el_is_aa64(env
, 2);
6040 static void hcrx_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6043 uint64_t valid_mask
= 0;
6045 /* FEAT_MOPS adds MSCEn and MCE2 */
6046 if (cpu_isar_feature(aa64_mops
, env_archcpu(env
))) {
6047 valid_mask
|= HCRX_MSCEN
| HCRX_MCE2
;
6050 /* Clear RES0 bits. */
6051 env
->cp15
.hcrx_el2
= value
& valid_mask
;
6054 static CPAccessResult
access_hxen(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6057 if (arm_current_el(env
) == 2
6058 && arm_feature(env
, ARM_FEATURE_EL3
)
6059 && !(env
->cp15
.scr_el3
& SCR_HXEN
)) {
6060 return CP_ACCESS_TRAP_EL3
;
6062 return CP_ACCESS_OK
;
6065 static const ARMCPRegInfo hcrx_el2_reginfo
= {
6066 .name
= "HCRX_EL2", .state
= ARM_CP_STATE_AA64
,
6067 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 2,
6068 .access
= PL2_RW
, .writefn
= hcrx_write
, .accessfn
= access_hxen
,
6069 .nv2_redirect_offset
= 0xa0,
6070 .fieldoffset
= offsetof(CPUARMState
, cp15
.hcrx_el2
),
6073 /* Return the effective value of HCRX_EL2. */
6074 uint64_t arm_hcrx_el2_eff(CPUARMState
*env
)
6077 * The bits in this register behave as 0 for all purposes other than
6078 * direct reads of the register if SCR_EL3.HXEn is 0.
6079 * If EL2 is not enabled in the current security state, then the
6080 * bit may behave as if 0, or as if 1, depending on the bit.
6081 * For the moment, we treat the EL2-disabled case as taking
6082 * priority over the HXEn-disabled case. This is true for the only
6083 * bit for a feature which we implement where the answer is different
6084 * for the two cases (MSCEn for FEAT_MOPS).
6085 * This may need to be revisited for future bits.
6087 if (!arm_is_el2_enabled(env
)) {
6089 if (cpu_isar_feature(aa64_mops
, env_archcpu(env
))) {
6090 /* MSCEn behaves as 1 if EL2 is not enabled */
6095 if (arm_feature(env
, ARM_FEATURE_EL3
) && !(env
->cp15
.scr_el3
& SCR_HXEN
)) {
6098 return env
->cp15
.hcrx_el2
;
6101 static void cptr_el2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6105 * For A-profile AArch32 EL3, if NSACR.CP10
6106 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
6108 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
6109 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
6110 uint64_t mask
= R_HCPTR_TCP11_MASK
| R_HCPTR_TCP10_MASK
;
6111 value
= (value
& ~mask
) | (env
->cp15
.cptr_el
[2] & mask
);
6113 env
->cp15
.cptr_el
[2] = value
;
6116 static uint64_t cptr_el2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6119 * For A-profile AArch32 EL3, if NSACR.CP10
6120 * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1.
6122 uint64_t value
= env
->cp15
.cptr_el
[2];
6124 if (arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
6125 !arm_is_secure(env
) && !extract32(env
->cp15
.nsacr
, 10, 1)) {
6126 value
|= R_HCPTR_TCP11_MASK
| R_HCPTR_TCP10_MASK
;
6131 static const ARMCPRegInfo el2_cp_reginfo
[] = {
6132 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
6134 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
6135 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
6136 .nv2_redirect_offset
= 0x78,
6137 .writefn
= hcr_write
, .raw_writefn
= raw_write
},
6138 { .name
= "HCR", .state
= ARM_CP_STATE_AA32
,
6139 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
6140 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
6141 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
6142 .writefn
= hcr_writelow
},
6143 { .name
= "HACR_EL2", .state
= ARM_CP_STATE_BOTH
,
6144 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 7,
6145 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6146 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
6147 .type
= ARM_CP_ALIAS
| ARM_CP_NV2_REDIRECT
,
6148 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
6150 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
6151 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_BOTH
,
6152 .type
= ARM_CP_NV2_REDIRECT
,
6153 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
6154 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
6155 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_BOTH
,
6156 .type
= ARM_CP_NV2_REDIRECT
,
6157 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
6158 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
6159 { .name
= "HIFAR", .state
= ARM_CP_STATE_AA32
,
6160 .type
= ARM_CP_ALIAS
,
6161 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 2,
6163 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.far_el
[2]) },
6164 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
6165 .type
= ARM_CP_ALIAS
| ARM_CP_NV2_REDIRECT
,
6166 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
6168 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_HYP
]) },
6169 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_BOTH
,
6170 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
6171 .access
= PL2_RW
, .writefn
= vbar_write
,
6172 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
6174 { .name
= "SP_EL2", .state
= ARM_CP_STATE_AA64
,
6175 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 1, .opc2
= 0,
6176 .access
= PL3_RW
, .type
= ARM_CP_ALIAS
,
6177 .fieldoffset
= offsetof(CPUARMState
, sp_el
[2]) },
6178 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
6179 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
6180 .access
= PL2_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
6181 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[2]),
6182 .readfn
= cptr_el2_read
, .writefn
= cptr_el2_write
},
6183 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
6184 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
6185 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[2]),
6187 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
6188 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
6189 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
6190 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el
[2]) },
6191 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
6192 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
6193 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6195 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
6196 { .name
= "HAMAIR1", .state
= ARM_CP_STATE_AA32
,
6197 .cp
= 15, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
6198 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6200 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
6201 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
6202 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6204 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
6205 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
6206 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
6208 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
6209 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
6210 .access
= PL2_RW
, .writefn
= vmsa_tcr_el12_write
,
6211 .raw_writefn
= raw_write
,
6212 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[2]) },
6213 { .name
= "VTCR", .state
= ARM_CP_STATE_AA32
,
6214 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
6215 .type
= ARM_CP_ALIAS
,
6216 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
6217 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vtcr_el2
) },
6218 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_AA64
,
6219 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
6221 .nv2_redirect_offset
= 0x40,
6222 /* no .writefn needed as this can't cause an ASID change */
6223 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
6224 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
6225 .cp
= 15, .opc1
= 6, .crm
= 2,
6226 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
6227 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
6228 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
),
6229 .writefn
= vttbr_write
, .raw_writefn
= raw_write
},
6230 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
6231 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
6232 .access
= PL2_RW
, .writefn
= vttbr_write
, .raw_writefn
= raw_write
,
6233 .nv2_redirect_offset
= 0x20,
6234 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
) },
6235 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
6236 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
6237 .access
= PL2_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
6238 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[2]) },
6239 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
6240 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
6241 .access
= PL2_RW
, .resetvalue
= 0,
6242 .nv2_redirect_offset
= 0x90,
6243 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[2]) },
6244 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
6245 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
6246 .access
= PL2_RW
, .resetvalue
= 0,
6247 .writefn
= vmsa_tcr_ttbr_el2_write
, .raw_writefn
= raw_write
,
6248 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
6249 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
6250 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
6251 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
6252 { .name
= "TLBIALLNSNH",
6253 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
6254 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6255 .writefn
= tlbiall_nsnh_write
},
6256 { .name
= "TLBIALLNSNHIS",
6257 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
6258 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6259 .writefn
= tlbiall_nsnh_is_write
},
6260 { .name
= "TLBIALLH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
6261 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6262 .writefn
= tlbiall_hyp_write
},
6263 { .name
= "TLBIALLHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
6264 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6265 .writefn
= tlbiall_hyp_is_write
},
6266 { .name
= "TLBIMVAH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
6267 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6268 .writefn
= tlbimva_hyp_write
},
6269 { .name
= "TLBIMVAHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
6270 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
6271 .writefn
= tlbimva_hyp_is_write
},
6272 { .name
= "TLBI_ALLE2", .state
= ARM_CP_STATE_AA64
,
6273 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
6274 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6275 .writefn
= tlbi_aa64_alle2_write
},
6276 { .name
= "TLBI_VAE2", .state
= ARM_CP_STATE_AA64
,
6277 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
6278 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6279 .writefn
= tlbi_aa64_vae2_write
},
6280 { .name
= "TLBI_VALE2", .state
= ARM_CP_STATE_AA64
,
6281 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
6282 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6283 .writefn
= tlbi_aa64_vae2_write
},
6284 { .name
= "TLBI_ALLE2IS", .state
= ARM_CP_STATE_AA64
,
6285 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
6286 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6287 .writefn
= tlbi_aa64_alle2is_write
},
6288 { .name
= "TLBI_VAE2IS", .state
= ARM_CP_STATE_AA64
,
6289 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
6290 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6291 .writefn
= tlbi_aa64_vae2is_write
},
6292 { .name
= "TLBI_VALE2IS", .state
= ARM_CP_STATE_AA64
,
6293 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
6294 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
6295 .writefn
= tlbi_aa64_vae2is_write
},
6296 #ifndef CONFIG_USER_ONLY
6298 * Unlike the other EL2-related AT operations, these must
6299 * UNDEF from EL3 if EL2 is not implemented, which is why we
6300 * define them here rather than with the rest of the AT ops.
6302 { .name
= "AT_S1E2R", .state
= ARM_CP_STATE_AA64
,
6303 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
6304 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
6305 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
| ARM_CP_EL3_NO_EL2_UNDEF
,
6306 .writefn
= ats_write64
},
6307 { .name
= "AT_S1E2W", .state
= ARM_CP_STATE_AA64
,
6308 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
6309 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
6310 .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
| ARM_CP_EL3_NO_EL2_UNDEF
,
6311 .writefn
= ats_write64
},
6313 * The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
6314 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
6315 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
6316 * to behave as if SCR.NS was 1.
6318 { .name
= "ATS1HR", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
6320 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
6321 { .name
= "ATS1HW", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
6323 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
6324 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
6325 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
6327 * ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
6328 * reset values as IMPDEF. We choose to reset to 3 to comply with
6329 * both ARMv7 and ARMv8.
6331 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 3,
6332 .writefn
= gt_cnthctl_write
, .raw_writefn
= raw_write
,
6333 .fieldoffset
= offsetof(CPUARMState
, cp15
.cnthctl_el2
) },
6334 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
6335 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
6336 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 0,
6337 .writefn
= gt_cntvoff_write
,
6338 .nv2_redirect_offset
= 0x60,
6339 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
6340 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
6341 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
| ARM_CP_IO
,
6342 .writefn
= gt_cntvoff_write
,
6343 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
6344 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
6345 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
6346 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
6347 .type
= ARM_CP_IO
, .access
= PL2_RW
,
6348 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
6349 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
6350 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
6351 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_IO
,
6352 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
6353 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
6354 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
6355 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
6356 .resetfn
= gt_hyp_timer_reset
,
6357 .readfn
= gt_hyp_tval_read
, .writefn
= gt_hyp_tval_write
},
6358 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
6360 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
6362 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].ctl
),
6364 .writefn
= gt_hyp_ctl_write
, .raw_writefn
= raw_write
},
6366 { .name
= "HPFAR", .state
= ARM_CP_STATE_AA32
,
6367 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
6368 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
6369 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
6370 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_AA64
,
6371 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
6373 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
6374 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
6375 .cp
= 15, .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
6377 .nv2_redirect_offset
= 0x80,
6378 .fieldoffset
= offsetof(CPUARMState
, cp15
.hstr_el2
) },
6381 static const ARMCPRegInfo el2_v8_cp_reginfo
[] = {
6382 { .name
= "HCR2", .state
= ARM_CP_STATE_AA32
,
6383 .type
= ARM_CP_ALIAS
| ARM_CP_IO
,
6384 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
6386 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.hcr_el2
),
6387 .writefn
= hcr_writehigh
},
6390 static CPAccessResult
sel2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6393 if (arm_current_el(env
) == 3 || arm_is_secure_below_el3(env
)) {
6394 return CP_ACCESS_OK
;
6396 return CP_ACCESS_TRAP_UNCATEGORIZED
;
6399 static const ARMCPRegInfo el2_sec_cp_reginfo
[] = {
6400 { .name
= "VSTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
6401 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 6, .opc2
= 0,
6402 .access
= PL2_RW
, .accessfn
= sel2_access
,
6403 .nv2_redirect_offset
= 0x30,
6404 .fieldoffset
= offsetof(CPUARMState
, cp15
.vsttbr_el2
) },
6405 { .name
= "VSTCR_EL2", .state
= ARM_CP_STATE_AA64
,
6406 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 6, .opc2
= 2,
6407 .access
= PL2_RW
, .accessfn
= sel2_access
,
6408 .nv2_redirect_offset
= 0x48,
6409 .fieldoffset
= offsetof(CPUARMState
, cp15
.vstcr_el2
) },
6412 static CPAccessResult
nsacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6416 * The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
6417 * At Secure EL1 it traps to EL3 or EL2.
6419 if (arm_current_el(env
) == 3) {
6420 return CP_ACCESS_OK
;
6422 if (arm_is_secure_below_el3(env
)) {
6423 if (env
->cp15
.scr_el3
& SCR_EEL2
) {
6424 return CP_ACCESS_TRAP_EL2
;
6426 return CP_ACCESS_TRAP_EL3
;
6428 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
6430 return CP_ACCESS_OK
;
6432 return CP_ACCESS_TRAP_UNCATEGORIZED
;
6435 static const ARMCPRegInfo el3_cp_reginfo
[] = {
6436 { .name
= "SCR_EL3", .state
= ARM_CP_STATE_AA64
,
6437 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 0,
6438 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.scr_el3
),
6439 .resetfn
= scr_reset
, .writefn
= scr_write
, .raw_writefn
= raw_write
},
6440 { .name
= "SCR", .type
= ARM_CP_ALIAS
| ARM_CP_NEWEL
,
6441 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 0,
6442 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
6443 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.scr_el3
),
6444 .writefn
= scr_write
, .raw_writefn
= raw_write
},
6445 { .name
= "SDER32_EL3", .state
= ARM_CP_STATE_AA64
,
6446 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 1,
6447 .access
= PL3_RW
, .resetvalue
= 0,
6448 .fieldoffset
= offsetof(CPUARMState
, cp15
.sder
) },
6450 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 1,
6451 .access
= PL3_RW
, .resetvalue
= 0,
6452 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.sder
) },
6453 { .name
= "MVBAR", .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
6454 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
6455 .writefn
= vbar_write
, .resetvalue
= 0,
6456 .fieldoffset
= offsetof(CPUARMState
, cp15
.mvbar
) },
6457 { .name
= "TTBR0_EL3", .state
= ARM_CP_STATE_AA64
,
6458 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 0,
6459 .access
= PL3_RW
, .resetvalue
= 0,
6460 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[3]) },
6461 { .name
= "TCR_EL3", .state
= ARM_CP_STATE_AA64
,
6462 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 2,
6464 /* no .writefn needed as this can't cause an ASID change */
6466 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[3]) },
6467 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
6468 .type
= ARM_CP_ALIAS
,
6469 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
6471 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
6472 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
6473 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
6474 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
6475 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
6476 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
6477 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
6478 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
6479 .type
= ARM_CP_ALIAS
,
6480 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
6482 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_MON
]) },
6483 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
6484 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
6485 .access
= PL3_RW
, .writefn
= vbar_write
,
6486 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
6488 { .name
= "CPTR_EL3", .state
= ARM_CP_STATE_AA64
,
6489 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 2,
6490 .access
= PL3_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
6491 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[3]) },
6492 { .name
= "TPIDR_EL3", .state
= ARM_CP_STATE_AA64
,
6493 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 2,
6494 .access
= PL3_RW
, .resetvalue
= 0,
6495 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[3]) },
6496 { .name
= "AMAIR_EL3", .state
= ARM_CP_STATE_AA64
,
6497 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 3, .opc2
= 0,
6498 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6500 { .name
= "AFSR0_EL3", .state
= ARM_CP_STATE_BOTH
,
6501 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 0,
6502 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6504 { .name
= "AFSR1_EL3", .state
= ARM_CP_STATE_BOTH
,
6505 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 1,
6506 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
6508 { .name
= "TLBI_ALLE3IS", .state
= ARM_CP_STATE_AA64
,
6509 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 0,
6510 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6511 .writefn
= tlbi_aa64_alle3is_write
},
6512 { .name
= "TLBI_VAE3IS", .state
= ARM_CP_STATE_AA64
,
6513 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 1,
6514 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6515 .writefn
= tlbi_aa64_vae3is_write
},
6516 { .name
= "TLBI_VALE3IS", .state
= ARM_CP_STATE_AA64
,
6517 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 5,
6518 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6519 .writefn
= tlbi_aa64_vae3is_write
},
6520 { .name
= "TLBI_ALLE3", .state
= ARM_CP_STATE_AA64
,
6521 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 0,
6522 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6523 .writefn
= tlbi_aa64_alle3_write
},
6524 { .name
= "TLBI_VAE3", .state
= ARM_CP_STATE_AA64
,
6525 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 1,
6526 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6527 .writefn
= tlbi_aa64_vae3_write
},
6528 { .name
= "TLBI_VALE3", .state
= ARM_CP_STATE_AA64
,
6529 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 5,
6530 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
6531 .writefn
= tlbi_aa64_vae3_write
},
6534 #ifndef CONFIG_USER_ONLY
6536 static CPAccessResult
e2h_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6539 if (arm_current_el(env
) == 1) {
6540 /* This must be a FEAT_NV access */
6541 /* TODO: FEAT_ECV will need to check CNTHCTL_EL2 here */
6542 return CP_ACCESS_OK
;
6544 if (!(arm_hcr_el2_eff(env
) & HCR_E2H
)) {
6545 return CP_ACCESS_TRAP
;
6547 return CP_ACCESS_OK
;
6550 /* Test if system register redirection is to occur in the current state. */
6551 static bool redirect_for_e2h(CPUARMState
*env
)
6553 return arm_current_el(env
) == 2 && (arm_hcr_el2_eff(env
) & HCR_E2H
);
6556 static uint64_t el2_e2h_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6560 if (redirect_for_e2h(env
)) {
6561 /* Switch to the saved EL2 version of the register. */
6563 readfn
= ri
->readfn
;
6565 readfn
= ri
->orig_readfn
;
6567 if (readfn
== NULL
) {
6570 return readfn(env
, ri
);
6573 static void el2_e2h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6578 if (redirect_for_e2h(env
)) {
6579 /* Switch to the saved EL2 version of the register. */
6581 writefn
= ri
->writefn
;
6583 writefn
= ri
->orig_writefn
;
6585 if (writefn
== NULL
) {
6586 writefn
= raw_write
;
6588 writefn(env
, ri
, value
);
6591 static uint64_t el2_e2h_e12_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6593 /* Pass the EL1 register accessor its ri, not the EL12 alias ri */
6594 return ri
->orig_readfn(env
, ri
->opaque
);
6597 static void el2_e2h_e12_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6600 /* Pass the EL1 register accessor its ri, not the EL12 alias ri */
6601 return ri
->orig_writefn(env
, ri
->opaque
, value
);
6604 static CPAccessResult
el2_e2h_e12_access(CPUARMState
*env
,
6605 const ARMCPRegInfo
*ri
,
6608 if (arm_current_el(env
) == 1) {
6610 * This must be a FEAT_NV access (will either trap or redirect
6611 * to memory). None of the registers with _EL12 aliases want to
6612 * apply their trap controls for this kind of access, so don't
6613 * call the orig_accessfn or do the "UNDEF when E2H is 0" check.
6615 return CP_ACCESS_OK
;
6617 /* FOO_EL12 aliases only exist when E2H is 1; otherwise they UNDEF */
6618 if (!(arm_hcr_el2_eff(env
) & HCR_E2H
)) {
6619 return CP_ACCESS_TRAP_UNCATEGORIZED
;
6621 if (ri
->orig_accessfn
) {
6622 return ri
->orig_accessfn(env
, ri
->opaque
, isread
);
6624 return CP_ACCESS_OK
;
6627 static void define_arm_vh_e2h_redirects_aliases(ARMCPU
*cpu
)
6630 uint32_t src_key
, dst_key
, new_key
;
6631 const char *src_name
, *dst_name
, *new_name
;
6632 bool (*feature
)(const ARMISARegisters
*id
);
6635 #define K(op0, op1, crn, crm, op2) \
6636 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
6638 static const struct E2HAlias aliases
[] = {
6639 { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0),
6640 "SCTLR", "SCTLR_EL2", "SCTLR_EL12" },
6641 { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2),
6642 "CPACR", "CPTR_EL2", "CPACR_EL12" },
6643 { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0),
6644 "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" },
6645 { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1),
6646 "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" },
6647 { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2),
6648 "TCR_EL1", "TCR_EL2", "TCR_EL12" },
6649 { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0),
6650 "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" },
6651 { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1),
6652 "ELR_EL1", "ELR_EL2", "ELR_EL12" },
6653 { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0),
6654 "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" },
6655 { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1),
6656 "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" },
6657 { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0),
6658 "ESR_EL1", "ESR_EL2", "ESR_EL12" },
6659 { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0),
6660 "FAR_EL1", "FAR_EL2", "FAR_EL12" },
6661 { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0),
6662 "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" },
6663 { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0),
6664 "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" },
6665 { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0),
6666 "VBAR", "VBAR_EL2", "VBAR_EL12" },
6667 { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1),
6668 "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" },
6669 { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0),
6670 "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" },
6673 * Note that redirection of ZCR is mentioned in the description
6674 * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but
6675 * not in the summary table.
6677 { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0),
6678 "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve
},
6679 { K(3, 0, 1, 2, 6), K(3, 4, 1, 2, 6), K(3, 5, 1, 2, 6),
6680 "SMCR_EL1", "SMCR_EL2", "SMCR_EL12", isar_feature_aa64_sme
},
6682 { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0),
6683 "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte
},
6685 { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7),
6686 "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12",
6687 isar_feature_aa64_scxtnum
},
6689 /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
6690 /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
6696 for (i
= 0; i
< ARRAY_SIZE(aliases
); i
++) {
6697 const struct E2HAlias
*a
= &aliases
[i
];
6698 ARMCPRegInfo
*src_reg
, *dst_reg
, *new_reg
;
6701 if (a
->feature
&& !a
->feature(&cpu
->isar
)) {
6705 src_reg
= g_hash_table_lookup(cpu
->cp_regs
,
6706 (gpointer
)(uintptr_t)a
->src_key
);
6707 dst_reg
= g_hash_table_lookup(cpu
->cp_regs
,
6708 (gpointer
)(uintptr_t)a
->dst_key
);
6709 g_assert(src_reg
!= NULL
);
6710 g_assert(dst_reg
!= NULL
);
6712 /* Cross-compare names to detect typos in the keys. */
6713 g_assert(strcmp(src_reg
->name
, a
->src_name
) == 0);
6714 g_assert(strcmp(dst_reg
->name
, a
->dst_name
) == 0);
6716 /* None of the core system registers use opaque; we will. */
6717 g_assert(src_reg
->opaque
== NULL
);
6719 /* Create alias before redirection so we dup the right data. */
6720 new_reg
= g_memdup(src_reg
, sizeof(ARMCPRegInfo
));
6722 new_reg
->name
= a
->new_name
;
6723 new_reg
->type
|= ARM_CP_ALIAS
;
6724 /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */
6725 new_reg
->access
&= PL2_RW
| PL3_RW
;
6726 /* The new_reg op fields are as per new_key, not the target reg */
6727 new_reg
->crn
= (a
->new_key
& CP_REG_ARM64_SYSREG_CRN_MASK
)
6728 >> CP_REG_ARM64_SYSREG_CRN_SHIFT
;
6729 new_reg
->crm
= (a
->new_key
& CP_REG_ARM64_SYSREG_CRM_MASK
)
6730 >> CP_REG_ARM64_SYSREG_CRM_SHIFT
;
6731 new_reg
->opc0
= (a
->new_key
& CP_REG_ARM64_SYSREG_OP0_MASK
)
6732 >> CP_REG_ARM64_SYSREG_OP0_SHIFT
;
6733 new_reg
->opc1
= (a
->new_key
& CP_REG_ARM64_SYSREG_OP1_MASK
)
6734 >> CP_REG_ARM64_SYSREG_OP1_SHIFT
;
6735 new_reg
->opc2
= (a
->new_key
& CP_REG_ARM64_SYSREG_OP2_MASK
)
6736 >> CP_REG_ARM64_SYSREG_OP2_SHIFT
;
6737 new_reg
->opaque
= src_reg
;
6738 new_reg
->orig_readfn
= src_reg
->readfn
?: raw_read
;
6739 new_reg
->orig_writefn
= src_reg
->writefn
?: raw_write
;
6740 new_reg
->orig_accessfn
= src_reg
->accessfn
;
6741 if (!new_reg
->raw_readfn
) {
6742 new_reg
->raw_readfn
= raw_read
;
6744 if (!new_reg
->raw_writefn
) {
6745 new_reg
->raw_writefn
= raw_write
;
6747 new_reg
->readfn
= el2_e2h_e12_read
;
6748 new_reg
->writefn
= el2_e2h_e12_write
;
6749 new_reg
->accessfn
= el2_e2h_e12_access
;
6752 * If the _EL1 register is redirected to memory by FEAT_NV2,
6753 * then it shares the offset with the _EL12 register,
6754 * and which one is redirected depends on HCR_EL2.NV1.
6756 if (new_reg
->nv2_redirect_offset
) {
6757 assert(new_reg
->nv2_redirect_offset
& NV2_REDIR_NV1
);
6758 new_reg
->nv2_redirect_offset
&= ~NV2_REDIR_NV1
;
6759 new_reg
->nv2_redirect_offset
|= NV2_REDIR_NO_NV1
;
6762 ok
= g_hash_table_insert(cpu
->cp_regs
,
6763 (gpointer
)(uintptr_t)a
->new_key
, new_reg
);
6766 src_reg
->opaque
= dst_reg
;
6767 src_reg
->orig_readfn
= src_reg
->readfn
?: raw_read
;
6768 src_reg
->orig_writefn
= src_reg
->writefn
?: raw_write
;
6769 if (!src_reg
->raw_readfn
) {
6770 src_reg
->raw_readfn
= raw_read
;
6772 if (!src_reg
->raw_writefn
) {
6773 src_reg
->raw_writefn
= raw_write
;
6775 src_reg
->readfn
= el2_e2h_read
;
6776 src_reg
->writefn
= el2_e2h_write
;
6781 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6784 int cur_el
= arm_current_el(env
);
6787 uint64_t hcr
= arm_hcr_el2_eff(env
);
6790 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
6791 if (!(env
->cp15
.sctlr_el
[2] & SCTLR_UCT
)) {
6792 return CP_ACCESS_TRAP_EL2
;
6795 if (!(env
->cp15
.sctlr_el
[1] & SCTLR_UCT
)) {
6796 return CP_ACCESS_TRAP
;
6798 if (hcr
& HCR_TID2
) {
6799 return CP_ACCESS_TRAP_EL2
;
6802 } else if (hcr
& HCR_TID2
) {
6803 return CP_ACCESS_TRAP_EL2
;
6807 if (arm_current_el(env
) < 2 && arm_hcr_el2_eff(env
) & HCR_TID2
) {
6808 return CP_ACCESS_TRAP_EL2
;
6811 return CP_ACCESS_OK
;
6815 * Check for traps to RAS registers, which are controlled
6816 * by HCR_EL2.TERR and SCR_EL3.TERR.
6818 static CPAccessResult
access_terr(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
6821 int el
= arm_current_el(env
);
6823 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TERR
)) {
6824 return CP_ACCESS_TRAP_EL2
;
6826 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TERR
)) {
6827 return CP_ACCESS_TRAP_EL3
;
6829 return CP_ACCESS_OK
;
6832 static uint64_t disr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
6834 int el
= arm_current_el(env
);
6836 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_AMO
)) {
6837 return env
->cp15
.vdisr_el2
;
6839 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_EA
)) {
6840 return 0; /* RAZ/WI */
6842 return env
->cp15
.disr_el1
;
6845 static void disr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
6847 int el
= arm_current_el(env
);
6849 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_AMO
)) {
6850 env
->cp15
.vdisr_el2
= val
;
6853 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_EA
)) {
6854 return; /* RAZ/WI */
6856 env
->cp15
.disr_el1
= val
;
6860 * Minimal RAS implementation with no Error Records.
6861 * Which means that all of the Error Record registers:
6869 * ERXPFGCDN_EL1 (RASv1p1)
6870 * ERXPFGCTL_EL1 (RASv1p1)
6871 * ERXPFGF_EL1 (RASv1p1)
6875 * may generate UNDEFINED, which is the effect we get by not
6876 * listing them at all.
6878 * These registers have fine-grained trap bits, but UNDEF-to-EL1
6879 * is higher priority than FGT-to-EL2 so we do not need to list them
6880 * in order to check for an FGT.
6882 static const ARMCPRegInfo minimal_ras_reginfo
[] = {
6883 { .name
= "DISR_EL1", .state
= ARM_CP_STATE_BOTH
,
6884 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 1,
6885 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.disr_el1
),
6886 .readfn
= disr_read
, .writefn
= disr_write
, .raw_writefn
= raw_write
},
6887 { .name
= "ERRIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
6888 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 3, .opc2
= 0,
6889 .access
= PL1_R
, .accessfn
= access_terr
,
6890 .fgt
= FGT_ERRIDR_EL1
,
6891 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
6892 { .name
= "VDISR_EL2", .state
= ARM_CP_STATE_BOTH
,
6893 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 1, .opc2
= 1,
6894 .nv2_redirect_offset
= 0x500,
6895 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.vdisr_el2
) },
6896 { .name
= "VSESR_EL2", .state
= ARM_CP_STATE_BOTH
,
6897 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 3,
6898 .nv2_redirect_offset
= 0x508,
6899 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.vsesr_el2
) },
6903 * Return the exception level to which exceptions should be taken
6904 * via SVEAccessTrap. This excludes the check for whether the exception
6905 * should be routed through AArch64.AdvSIMDFPAccessTrap. That can easily
6906 * be found by testing 0 < fp_exception_el < sve_exception_el.
6908 * C.f. the ARM pseudocode function CheckSVEEnabled. Note that the
6909 * pseudocode does *not* separate out the FP trap checks, but has them
6910 * all in one function.
6912 int sve_exception_el(CPUARMState
*env
, int el
)
6914 #ifndef CONFIG_USER_ONLY
6915 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6916 switch (FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, ZEN
)) {
6928 if (el
<= 2 && arm_is_el2_enabled(env
)) {
6929 /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */
6930 if (env
->cp15
.hcr_el2
& HCR_E2H
) {
6931 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, ZEN
)) {
6933 if (el
!= 0 || !(env
->cp15
.hcr_el2
& HCR_TGE
)) {
6942 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TZ
)) {
6948 /* CPTR_EL3. Since EZ is negative we must check for EL3. */
6949 if (arm_feature(env
, ARM_FEATURE_EL3
)
6950 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, EZ
)) {
6958 * Return the exception level to which exceptions should be taken for SME.
6959 * C.f. the ARM pseudocode function CheckSMEAccess.
6961 int sme_exception_el(CPUARMState
*env
, int el
)
6963 #ifndef CONFIG_USER_ONLY
6964 if (el
<= 1 && !el_is_in_host(env
, el
)) {
6965 switch (FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, SMEN
)) {
6977 if (el
<= 2 && arm_is_el2_enabled(env
)) {
6978 /* CPTR_EL2 changes format with HCR_EL2.E2H (regardless of TGE). */
6979 if (env
->cp15
.hcr_el2
& HCR_E2H
) {
6980 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, SMEN
)) {
6982 if (el
!= 0 || !(env
->cp15
.hcr_el2
& HCR_TGE
)) {
6991 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TSM
)) {
6997 /* CPTR_EL3. Since ESM is negative we must check for EL3. */
6998 if (arm_feature(env
, ARM_FEATURE_EL3
)
6999 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, ESM
)) {
7007 * Given that SVE is enabled, return the vector length for EL.
7009 uint32_t sve_vqm1_for_el_sm(CPUARMState
*env
, int el
, bool sm
)
7011 ARMCPU
*cpu
= env_archcpu(env
);
7012 uint64_t *cr
= env
->vfp
.zcr_el
;
7013 uint32_t map
= cpu
->sve_vq
.map
;
7014 uint32_t len
= ARM_MAX_VQ
- 1;
7017 cr
= env
->vfp
.smcr_el
;
7018 map
= cpu
->sme_vq
.map
;
7021 if (el
<= 1 && !el_is_in_host(env
, el
)) {
7022 len
= MIN(len
, 0xf & (uint32_t)cr
[1]);
7024 if (el
<= 2 && arm_feature(env
, ARM_FEATURE_EL2
)) {
7025 len
= MIN(len
, 0xf & (uint32_t)cr
[2]);
7027 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
7028 len
= MIN(len
, 0xf & (uint32_t)cr
[3]);
7031 map
&= MAKE_64BIT_MASK(0, len
+ 1);
7033 return 31 - clz32(map
);
7036 /* Bit 0 is always set for Normal SVE -- not so for Streaming SVE. */
7038 return ctz32(cpu
->sme_vq
.map
);
7041 uint32_t sve_vqm1_for_el(CPUARMState
*env
, int el
)
7043 return sve_vqm1_for_el_sm(env
, el
, FIELD_EX64(env
->svcr
, SVCR
, SM
));
7046 static void zcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7049 int cur_el
= arm_current_el(env
);
7050 int old_len
= sve_vqm1_for_el(env
, cur_el
);
7053 /* Bits other than [3:0] are RAZ/WI. */
7054 QEMU_BUILD_BUG_ON(ARM_MAX_VQ
> 16);
7055 raw_write(env
, ri
, value
& 0xf);
7058 * Because we arrived here, we know both FP and SVE are enabled;
7059 * otherwise we would have trapped access to the ZCR_ELn register.
7061 new_len
= sve_vqm1_for_el(env
, cur_el
);
7062 if (new_len
< old_len
) {
7063 aarch64_sve_narrow_vq(env
, new_len
+ 1);
7067 static const ARMCPRegInfo zcr_reginfo
[] = {
7068 { .name
= "ZCR_EL1", .state
= ARM_CP_STATE_AA64
,
7069 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 0,
7070 .nv2_redirect_offset
= 0x1e0 | NV2_REDIR_NV1
,
7071 .access
= PL1_RW
, .type
= ARM_CP_SVE
,
7072 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[1]),
7073 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
7074 { .name
= "ZCR_EL2", .state
= ARM_CP_STATE_AA64
,
7075 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 0,
7076 .access
= PL2_RW
, .type
= ARM_CP_SVE
,
7077 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[2]),
7078 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
7079 { .name
= "ZCR_EL3", .state
= ARM_CP_STATE_AA64
,
7080 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 0,
7081 .access
= PL3_RW
, .type
= ARM_CP_SVE
,
7082 .fieldoffset
= offsetof(CPUARMState
, vfp
.zcr_el
[3]),
7083 .writefn
= zcr_write
, .raw_writefn
= raw_write
},
7086 #ifdef TARGET_AARCH64
7087 static CPAccessResult
access_tpidr2(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7090 int el
= arm_current_el(env
);
7093 uint64_t sctlr
= arm_sctlr(env
, el
);
7094 if (!(sctlr
& SCTLR_EnTP2
)) {
7095 return CP_ACCESS_TRAP
;
7098 /* TODO: FEAT_FGT */
7100 && arm_feature(env
, ARM_FEATURE_EL3
)
7101 && !(env
->cp15
.scr_el3
& SCR_ENTP2
)) {
7102 return CP_ACCESS_TRAP_EL3
;
7104 return CP_ACCESS_OK
;
7107 static CPAccessResult
access_smprimap(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7110 /* If EL1 this is a FEAT_NV access and CPTR_EL3.ESM doesn't apply */
7111 if (arm_current_el(env
) == 2
7112 && arm_feature(env
, ARM_FEATURE_EL3
)
7113 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, ESM
)) {
7114 return CP_ACCESS_TRAP_EL3
;
7116 return CP_ACCESS_OK
;
7119 static CPAccessResult
access_smpri(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7122 if (arm_current_el(env
) < 3
7123 && arm_feature(env
, ARM_FEATURE_EL3
)
7124 && !FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, ESM
)) {
7125 return CP_ACCESS_TRAP_EL3
;
7127 return CP_ACCESS_OK
;
7131 static void arm_reset_sve_state(CPUARMState
*env
)
7133 memset(env
->vfp
.zregs
, 0, sizeof(env
->vfp
.zregs
));
7134 /* Recall that FFR is stored as pregs[16]. */
7135 memset(env
->vfp
.pregs
, 0, sizeof(env
->vfp
.pregs
));
7136 vfp_set_fpcr(env
, 0x0800009f);
7139 void aarch64_set_svcr(CPUARMState
*env
, uint64_t new, uint64_t mask
)
7141 uint64_t change
= (env
->svcr
^ new) & mask
;
7146 env
->svcr
^= change
;
7148 if (change
& R_SVCR_SM_MASK
) {
7149 arm_reset_sve_state(env
);
7155 * SetPSTATE_ZA zeros on enable and disable. We can zero this only
7156 * on enable: while disabled, the storage is inaccessible and the
7157 * value does not matter. We're not saving the storage in vmstate
7158 * when disabled either.
7160 if (change
& new & R_SVCR_ZA_MASK
) {
7161 memset(env
->zarray
, 0, sizeof(env
->zarray
));
7164 if (tcg_enabled()) {
7165 arm_rebuild_hflags(env
);
7169 static void svcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7172 aarch64_set_svcr(env
, value
, -1);
7175 static void smcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7178 int cur_el
= arm_current_el(env
);
7179 int old_len
= sve_vqm1_for_el(env
, cur_el
);
7182 QEMU_BUILD_BUG_ON(ARM_MAX_VQ
> R_SMCR_LEN_MASK
+ 1);
7183 value
&= R_SMCR_LEN_MASK
| R_SMCR_FA64_MASK
;
7184 raw_write(env
, ri
, value
);
7187 * Note that it is CONSTRAINED UNPREDICTABLE what happens to ZA storage
7188 * when SVL is widened (old values kept, or zeros). Choose to keep the
7189 * current values for simplicity. But for QEMU internals, we must still
7190 * apply the narrower SVL to the Zregs and Pregs -- see the comment
7191 * above aarch64_sve_narrow_vq.
7193 new_len
= sve_vqm1_for_el(env
, cur_el
);
7194 if (new_len
< old_len
) {
7195 aarch64_sve_narrow_vq(env
, new_len
+ 1);
7199 static const ARMCPRegInfo sme_reginfo
[] = {
7200 { .name
= "TPIDR2_EL0", .state
= ARM_CP_STATE_AA64
,
7201 .opc0
= 3, .opc1
= 3, .crn
= 13, .crm
= 0, .opc2
= 5,
7202 .access
= PL0_RW
, .accessfn
= access_tpidr2
,
7203 .fgt
= FGT_NTPIDR2_EL0
,
7204 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr2_el0
) },
7205 { .name
= "SVCR", .state
= ARM_CP_STATE_AA64
,
7206 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 2,
7207 .access
= PL0_RW
, .type
= ARM_CP_SME
,
7208 .fieldoffset
= offsetof(CPUARMState
, svcr
),
7209 .writefn
= svcr_write
, .raw_writefn
= raw_write
},
7210 { .name
= "SMCR_EL1", .state
= ARM_CP_STATE_AA64
,
7211 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 6,
7212 .nv2_redirect_offset
= 0x1f0 | NV2_REDIR_NV1
,
7213 .access
= PL1_RW
, .type
= ARM_CP_SME
,
7214 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[1]),
7215 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
7216 { .name
= "SMCR_EL2", .state
= ARM_CP_STATE_AA64
,
7217 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 6,
7218 .access
= PL2_RW
, .type
= ARM_CP_SME
,
7219 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[2]),
7220 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
7221 { .name
= "SMCR_EL3", .state
= ARM_CP_STATE_AA64
,
7222 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 2, .opc2
= 6,
7223 .access
= PL3_RW
, .type
= ARM_CP_SME
,
7224 .fieldoffset
= offsetof(CPUARMState
, vfp
.smcr_el
[3]),
7225 .writefn
= smcr_write
, .raw_writefn
= raw_write
},
7226 { .name
= "SMIDR_EL1", .state
= ARM_CP_STATE_AA64
,
7227 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 6,
7228 .access
= PL1_R
, .accessfn
= access_aa64_tid1
,
7230 * IMPLEMENTOR = 0 (software)
7231 * REVISION = 0 (implementation defined)
7232 * SMPS = 0 (no streaming execution priority in QEMU)
7233 * AFFINITY = 0 (streaming sve mode not shared with other PEs)
7235 .type
= ARM_CP_CONST
, .resetvalue
= 0, },
7237 * Because SMIDR_EL1.SMPS is 0, SMPRI_EL1 and SMPRIMAP_EL2 are RES 0.
7239 { .name
= "SMPRI_EL1", .state
= ARM_CP_STATE_AA64
,
7240 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 2, .opc2
= 4,
7241 .access
= PL1_RW
, .accessfn
= access_smpri
,
7242 .fgt
= FGT_NSMPRI_EL1
,
7243 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7244 { .name
= "SMPRIMAP_EL2", .state
= ARM_CP_STATE_AA64
,
7245 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 2, .opc2
= 5,
7246 .nv2_redirect_offset
= 0x1f8,
7247 .access
= PL2_RW
, .accessfn
= access_smprimap
,
7248 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7251 static void tlbi_aa64_paall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7254 CPUState
*cs
= env_cpu(env
);
7259 static void gpccr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7262 /* L0GPTSZ is RO; other bits not mentioned are RES0. */
7263 uint64_t rw_mask
= R_GPCCR_PPS_MASK
| R_GPCCR_IRGN_MASK
|
7264 R_GPCCR_ORGN_MASK
| R_GPCCR_SH_MASK
| R_GPCCR_PGS_MASK
|
7265 R_GPCCR_GPC_MASK
| R_GPCCR_GPCP_MASK
;
7267 env
->cp15
.gpccr_el3
= (value
& rw_mask
) | (env
->cp15
.gpccr_el3
& ~rw_mask
);
7270 static void gpccr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7272 env
->cp15
.gpccr_el3
= FIELD_DP64(0, GPCCR
, L0GPTSZ
,
7273 env_archcpu(env
)->reset_l0gptsz
);
7276 static void tlbi_aa64_paallos_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7279 CPUState
*cs
= env_cpu(env
);
7281 tlb_flush_all_cpus_synced(cs
);
7284 static const ARMCPRegInfo rme_reginfo
[] = {
7285 { .name
= "GPCCR_EL3", .state
= ARM_CP_STATE_AA64
,
7286 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 1, .opc2
= 6,
7287 .access
= PL3_RW
, .writefn
= gpccr_write
, .resetfn
= gpccr_reset
,
7288 .fieldoffset
= offsetof(CPUARMState
, cp15
.gpccr_el3
) },
7289 { .name
= "GPTBR_EL3", .state
= ARM_CP_STATE_AA64
,
7290 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 1, .opc2
= 4,
7291 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.gptbr_el3
) },
7292 { .name
= "MFAR_EL3", .state
= ARM_CP_STATE_AA64
,
7293 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 5,
7294 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mfar_el3
) },
7295 { .name
= "TLBI_PAALL", .state
= ARM_CP_STATE_AA64
,
7296 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 4,
7297 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7298 .writefn
= tlbi_aa64_paall_write
},
7299 { .name
= "TLBI_PAALLOS", .state
= ARM_CP_STATE_AA64
,
7300 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 4,
7301 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7302 .writefn
= tlbi_aa64_paallos_write
},
7304 * QEMU does not have a way to invalidate by physical address, thus
7305 * invalidating a range of physical addresses is accomplished by
7306 * flushing all tlb entries in the outer shareable domain,
7307 * just like PAALLOS.
7309 { .name
= "TLBI_RPALOS", .state
= ARM_CP_STATE_AA64
,
7310 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 4, .opc2
= 7,
7311 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7312 .writefn
= tlbi_aa64_paallos_write
},
7313 { .name
= "TLBI_RPAOS", .state
= ARM_CP_STATE_AA64
,
7314 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 4, .opc2
= 3,
7315 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7316 .writefn
= tlbi_aa64_paallos_write
},
7317 { .name
= "DC_CIPAPA", .state
= ARM_CP_STATE_AA64
,
7318 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 14, .opc2
= 1,
7319 .access
= PL3_W
, .type
= ARM_CP_NOP
},
7322 static const ARMCPRegInfo rme_mte_reginfo
[] = {
7323 { .name
= "DC_CIGDPAPA", .state
= ARM_CP_STATE_AA64
,
7324 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 14, .opc2
= 5,
7325 .access
= PL3_W
, .type
= ARM_CP_NOP
},
7327 #endif /* TARGET_AARCH64 */
7329 static void define_pmu_regs(ARMCPU
*cpu
)
7332 * v7 performance monitor control register: same implementor
7333 * field as main ID register, and we implement four counters in
7334 * addition to the cycle count register.
7336 unsigned int i
, pmcrn
= pmu_num_counters(&cpu
->env
);
7337 ARMCPRegInfo pmcr
= {
7338 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
7340 .fgt
= FGT_PMCR_EL0
,
7341 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7342 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcr
),
7343 .accessfn
= pmreg_access
,
7344 .readfn
= pmcr_read
, .raw_readfn
= raw_read
,
7345 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
7347 ARMCPRegInfo pmcr64
= {
7348 .name
= "PMCR_EL0", .state
= ARM_CP_STATE_AA64
,
7349 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 0,
7350 .access
= PL0_RW
, .accessfn
= pmreg_access
,
7351 .fgt
= FGT_PMCR_EL0
,
7353 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
7354 .resetvalue
= cpu
->isar
.reset_pmcr_el0
,
7355 .readfn
= pmcr_read
, .raw_readfn
= raw_read
,
7356 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
7359 define_one_arm_cp_reg(cpu
, &pmcr
);
7360 define_one_arm_cp_reg(cpu
, &pmcr64
);
7361 for (i
= 0; i
< pmcrn
; i
++) {
7362 char *pmevcntr_name
= g_strdup_printf("PMEVCNTR%d", i
);
7363 char *pmevcntr_el0_name
= g_strdup_printf("PMEVCNTR%d_EL0", i
);
7364 char *pmevtyper_name
= g_strdup_printf("PMEVTYPER%d", i
);
7365 char *pmevtyper_el0_name
= g_strdup_printf("PMEVTYPER%d_EL0", i
);
7366 ARMCPRegInfo pmev_regs
[] = {
7367 { .name
= pmevcntr_name
, .cp
= 15, .crn
= 14,
7368 .crm
= 8 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
7369 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7370 .fgt
= FGT_PMEVCNTRN_EL0
,
7371 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
7372 .accessfn
= pmreg_access_xevcntr
},
7373 { .name
= pmevcntr_el0_name
, .state
= ARM_CP_STATE_AA64
,
7374 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 8 | (3 & (i
>> 3)),
7375 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access_xevcntr
,
7377 .fgt
= FGT_PMEVCNTRN_EL0
,
7378 .readfn
= pmevcntr_readfn
, .writefn
= pmevcntr_writefn
,
7379 .raw_readfn
= pmevcntr_rawread
,
7380 .raw_writefn
= pmevcntr_rawwrite
},
7381 { .name
= pmevtyper_name
, .cp
= 15, .crn
= 14,
7382 .crm
= 12 | (3 & (i
>> 3)), .opc1
= 0, .opc2
= i
& 7,
7383 .access
= PL0_RW
, .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
7384 .fgt
= FGT_PMEVTYPERN_EL0
,
7385 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
7386 .accessfn
= pmreg_access
},
7387 { .name
= pmevtyper_el0_name
, .state
= ARM_CP_STATE_AA64
,
7388 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 12 | (3 & (i
>> 3)),
7389 .opc2
= i
& 7, .access
= PL0_RW
, .accessfn
= pmreg_access
,
7390 .fgt
= FGT_PMEVTYPERN_EL0
,
7392 .readfn
= pmevtyper_readfn
, .writefn
= pmevtyper_writefn
,
7393 .raw_writefn
= pmevtyper_rawwrite
},
7395 define_arm_cp_regs(cpu
, pmev_regs
);
7396 g_free(pmevcntr_name
);
7397 g_free(pmevcntr_el0_name
);
7398 g_free(pmevtyper_name
);
7399 g_free(pmevtyper_el0_name
);
7401 if (cpu_isar_feature(aa32_pmuv3p1
, cpu
)) {
7402 ARMCPRegInfo v81_pmu_regs
[] = {
7403 { .name
= "PMCEID2", .state
= ARM_CP_STATE_AA32
,
7404 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 4,
7405 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7406 .fgt
= FGT_PMCEIDN_EL0
,
7407 .resetvalue
= extract64(cpu
->pmceid0
, 32, 32) },
7408 { .name
= "PMCEID3", .state
= ARM_CP_STATE_AA32
,
7409 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 5,
7410 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7411 .fgt
= FGT_PMCEIDN_EL0
,
7412 .resetvalue
= extract64(cpu
->pmceid1
, 32, 32) },
7414 define_arm_cp_regs(cpu
, v81_pmu_regs
);
7416 if (cpu_isar_feature(any_pmuv3p4
, cpu
)) {
7417 static const ARMCPRegInfo v84_pmmir
= {
7418 .name
= "PMMIR_EL1", .state
= ARM_CP_STATE_BOTH
,
7419 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 6,
7420 .access
= PL1_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
7421 .fgt
= FGT_PMMIR_EL1
,
7424 define_one_arm_cp_reg(cpu
, &v84_pmmir
);
7428 #ifndef CONFIG_USER_ONLY
7430 * We don't know until after realize whether there's a GICv3
7431 * attached, and that is what registers the gicv3 sysregs.
7432 * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
7435 static uint64_t id_pfr1_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7437 ARMCPU
*cpu
= env_archcpu(env
);
7438 uint64_t pfr1
= cpu
->isar
.id_pfr1
;
7440 if (env
->gicv3state
) {
7446 static uint64_t id_aa64pfr0_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7448 ARMCPU
*cpu
= env_archcpu(env
);
7449 uint64_t pfr0
= cpu
->isar
.id_aa64pfr0
;
7451 if (env
->gicv3state
) {
7459 * Shared logic between LORID and the rest of the LOR* registers.
7460 * Secure state exclusion has already been dealt with.
7462 static CPAccessResult
access_lor_ns(CPUARMState
*env
,
7463 const ARMCPRegInfo
*ri
, bool isread
)
7465 int el
= arm_current_el(env
);
7467 if (el
< 2 && (arm_hcr_el2_eff(env
) & HCR_TLOR
)) {
7468 return CP_ACCESS_TRAP_EL2
;
7470 if (el
< 3 && (env
->cp15
.scr_el3
& SCR_TLOR
)) {
7471 return CP_ACCESS_TRAP_EL3
;
7473 return CP_ACCESS_OK
;
7476 static CPAccessResult
access_lor_other(CPUARMState
*env
,
7477 const ARMCPRegInfo
*ri
, bool isread
)
7479 if (arm_is_secure_below_el3(env
)) {
7480 /* Access denied in secure mode. */
7481 return CP_ACCESS_TRAP
;
7483 return access_lor_ns(env
, ri
, isread
);
7487 * A trivial implementation of ARMv8.1-LOR leaves all of these
7488 * registers fixed at 0, which indicates that there are zero
7489 * supported Limited Ordering regions.
7491 static const ARMCPRegInfo lor_reginfo
[] = {
7492 { .name
= "LORSA_EL1", .state
= ARM_CP_STATE_AA64
,
7493 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 0,
7494 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7495 .fgt
= FGT_LORSA_EL1
,
7496 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7497 { .name
= "LOREA_EL1", .state
= ARM_CP_STATE_AA64
,
7498 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 1,
7499 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7500 .fgt
= FGT_LOREA_EL1
,
7501 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7502 { .name
= "LORN_EL1", .state
= ARM_CP_STATE_AA64
,
7503 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 2,
7504 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7505 .fgt
= FGT_LORN_EL1
,
7506 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7507 { .name
= "LORC_EL1", .state
= ARM_CP_STATE_AA64
,
7508 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 3,
7509 .access
= PL1_RW
, .accessfn
= access_lor_other
,
7510 .fgt
= FGT_LORC_EL1
,
7511 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7512 { .name
= "LORID_EL1", .state
= ARM_CP_STATE_AA64
,
7513 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 4, .opc2
= 7,
7514 .access
= PL1_R
, .accessfn
= access_lor_ns
,
7515 .fgt
= FGT_LORID_EL1
,
7516 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
7519 #ifdef TARGET_AARCH64
7520 static CPAccessResult
access_pauth(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7523 int el
= arm_current_el(env
);
7526 arm_is_el2_enabled(env
) &&
7527 !(arm_hcr_el2_eff(env
) & HCR_APK
)) {
7528 return CP_ACCESS_TRAP_EL2
;
7531 arm_feature(env
, ARM_FEATURE_EL3
) &&
7532 !(env
->cp15
.scr_el3
& SCR_APK
)) {
7533 return CP_ACCESS_TRAP_EL3
;
7535 return CP_ACCESS_OK
;
7538 static const ARMCPRegInfo pauth_reginfo
[] = {
7539 { .name
= "APDAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7540 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 0,
7541 .access
= PL1_RW
, .accessfn
= access_pauth
,
7543 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.lo
) },
7544 { .name
= "APDAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7545 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 1,
7546 .access
= PL1_RW
, .accessfn
= access_pauth
,
7548 .fieldoffset
= offsetof(CPUARMState
, keys
.apda
.hi
) },
7549 { .name
= "APDBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7550 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 2,
7551 .access
= PL1_RW
, .accessfn
= access_pauth
,
7553 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.lo
) },
7554 { .name
= "APDBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7555 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 2, .opc2
= 3,
7556 .access
= PL1_RW
, .accessfn
= access_pauth
,
7558 .fieldoffset
= offsetof(CPUARMState
, keys
.apdb
.hi
) },
7559 { .name
= "APGAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7560 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 0,
7561 .access
= PL1_RW
, .accessfn
= access_pauth
,
7563 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.lo
) },
7564 { .name
= "APGAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7565 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 3, .opc2
= 1,
7566 .access
= PL1_RW
, .accessfn
= access_pauth
,
7568 .fieldoffset
= offsetof(CPUARMState
, keys
.apga
.hi
) },
7569 { .name
= "APIAKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7570 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 0,
7571 .access
= PL1_RW
, .accessfn
= access_pauth
,
7573 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.lo
) },
7574 { .name
= "APIAKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7575 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 1,
7576 .access
= PL1_RW
, .accessfn
= access_pauth
,
7578 .fieldoffset
= offsetof(CPUARMState
, keys
.apia
.hi
) },
7579 { .name
= "APIBKEYLO_EL1", .state
= ARM_CP_STATE_AA64
,
7580 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 2,
7581 .access
= PL1_RW
, .accessfn
= access_pauth
,
7583 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.lo
) },
7584 { .name
= "APIBKEYHI_EL1", .state
= ARM_CP_STATE_AA64
,
7585 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 1, .opc2
= 3,
7586 .access
= PL1_RW
, .accessfn
= access_pauth
,
7588 .fieldoffset
= offsetof(CPUARMState
, keys
.apib
.hi
) },
7591 static const ARMCPRegInfo tlbirange_reginfo
[] = {
7592 { .name
= "TLBI_RVAE1IS", .state
= ARM_CP_STATE_AA64
,
7593 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 1,
7594 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7595 .fgt
= FGT_TLBIRVAE1IS
,
7596 .writefn
= tlbi_aa64_rvae1is_write
},
7597 { .name
= "TLBI_RVAAE1IS", .state
= ARM_CP_STATE_AA64
,
7598 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 3,
7599 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7600 .fgt
= FGT_TLBIRVAAE1IS
,
7601 .writefn
= tlbi_aa64_rvae1is_write
},
7602 { .name
= "TLBI_RVALE1IS", .state
= ARM_CP_STATE_AA64
,
7603 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 5,
7604 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7605 .fgt
= FGT_TLBIRVALE1IS
,
7606 .writefn
= tlbi_aa64_rvae1is_write
},
7607 { .name
= "TLBI_RVAALE1IS", .state
= ARM_CP_STATE_AA64
,
7608 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 2, .opc2
= 7,
7609 .access
= PL1_W
, .accessfn
= access_ttlbis
, .type
= ARM_CP_NO_RAW
,
7610 .fgt
= FGT_TLBIRVAALE1IS
,
7611 .writefn
= tlbi_aa64_rvae1is_write
},
7612 { .name
= "TLBI_RVAE1OS", .state
= ARM_CP_STATE_AA64
,
7613 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
7614 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7615 .fgt
= FGT_TLBIRVAE1OS
,
7616 .writefn
= tlbi_aa64_rvae1is_write
},
7617 { .name
= "TLBI_RVAAE1OS", .state
= ARM_CP_STATE_AA64
,
7618 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 3,
7619 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7620 .fgt
= FGT_TLBIRVAAE1OS
,
7621 .writefn
= tlbi_aa64_rvae1is_write
},
7622 { .name
= "TLBI_RVALE1OS", .state
= ARM_CP_STATE_AA64
,
7623 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 5,
7624 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7625 .fgt
= FGT_TLBIRVALE1OS
,
7626 .writefn
= tlbi_aa64_rvae1is_write
},
7627 { .name
= "TLBI_RVAALE1OS", .state
= ARM_CP_STATE_AA64
,
7628 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 7,
7629 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7630 .fgt
= FGT_TLBIRVAALE1OS
,
7631 .writefn
= tlbi_aa64_rvae1is_write
},
7632 { .name
= "TLBI_RVAE1", .state
= ARM_CP_STATE_AA64
,
7633 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
7634 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7635 .fgt
= FGT_TLBIRVAE1
,
7636 .writefn
= tlbi_aa64_rvae1_write
},
7637 { .name
= "TLBI_RVAAE1", .state
= ARM_CP_STATE_AA64
,
7638 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 3,
7639 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7640 .fgt
= FGT_TLBIRVAAE1
,
7641 .writefn
= tlbi_aa64_rvae1_write
},
7642 { .name
= "TLBI_RVALE1", .state
= ARM_CP_STATE_AA64
,
7643 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 5,
7644 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7645 .fgt
= FGT_TLBIRVALE1
,
7646 .writefn
= tlbi_aa64_rvae1_write
},
7647 { .name
= "TLBI_RVAALE1", .state
= ARM_CP_STATE_AA64
,
7648 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 7,
7649 .access
= PL1_W
, .accessfn
= access_ttlb
, .type
= ARM_CP_NO_RAW
,
7650 .fgt
= FGT_TLBIRVAALE1
,
7651 .writefn
= tlbi_aa64_rvae1_write
},
7652 { .name
= "TLBI_RIPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
7653 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 2,
7654 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7655 .writefn
= tlbi_aa64_ripas2e1is_write
},
7656 { .name
= "TLBI_RIPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
7657 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 6,
7658 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7659 .writefn
= tlbi_aa64_ripas2e1is_write
},
7660 { .name
= "TLBI_RVAE2IS", .state
= ARM_CP_STATE_AA64
,
7661 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 2, .opc2
= 1,
7662 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7663 .writefn
= tlbi_aa64_rvae2is_write
},
7664 { .name
= "TLBI_RVALE2IS", .state
= ARM_CP_STATE_AA64
,
7665 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 2, .opc2
= 5,
7666 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7667 .writefn
= tlbi_aa64_rvae2is_write
},
7668 { .name
= "TLBI_RIPAS2E1", .state
= ARM_CP_STATE_AA64
,
7669 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 2,
7670 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7671 .writefn
= tlbi_aa64_ripas2e1_write
},
7672 { .name
= "TLBI_RIPAS2LE1", .state
= ARM_CP_STATE_AA64
,
7673 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 6,
7674 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7675 .writefn
= tlbi_aa64_ripas2e1_write
},
7676 { .name
= "TLBI_RVAE2OS", .state
= ARM_CP_STATE_AA64
,
7677 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 5, .opc2
= 1,
7678 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7679 .writefn
= tlbi_aa64_rvae2is_write
},
7680 { .name
= "TLBI_RVALE2OS", .state
= ARM_CP_STATE_AA64
,
7681 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 5, .opc2
= 5,
7682 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7683 .writefn
= tlbi_aa64_rvae2is_write
},
7684 { .name
= "TLBI_RVAE2", .state
= ARM_CP_STATE_AA64
,
7685 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 6, .opc2
= 1,
7686 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7687 .writefn
= tlbi_aa64_rvae2_write
},
7688 { .name
= "TLBI_RVALE2", .state
= ARM_CP_STATE_AA64
,
7689 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 6, .opc2
= 5,
7690 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7691 .writefn
= tlbi_aa64_rvae2_write
},
7692 { .name
= "TLBI_RVAE3IS", .state
= ARM_CP_STATE_AA64
,
7693 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 2, .opc2
= 1,
7694 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7695 .writefn
= tlbi_aa64_rvae3is_write
},
7696 { .name
= "TLBI_RVALE3IS", .state
= ARM_CP_STATE_AA64
,
7697 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 2, .opc2
= 5,
7698 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7699 .writefn
= tlbi_aa64_rvae3is_write
},
7700 { .name
= "TLBI_RVAE3OS", .state
= ARM_CP_STATE_AA64
,
7701 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 5, .opc2
= 1,
7702 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7703 .writefn
= tlbi_aa64_rvae3is_write
},
7704 { .name
= "TLBI_RVALE3OS", .state
= ARM_CP_STATE_AA64
,
7705 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 5, .opc2
= 5,
7706 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7707 .writefn
= tlbi_aa64_rvae3is_write
},
7708 { .name
= "TLBI_RVAE3", .state
= ARM_CP_STATE_AA64
,
7709 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 6, .opc2
= 1,
7710 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7711 .writefn
= tlbi_aa64_rvae3_write
},
7712 { .name
= "TLBI_RVALE3", .state
= ARM_CP_STATE_AA64
,
7713 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 6, .opc2
= 5,
7714 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7715 .writefn
= tlbi_aa64_rvae3_write
},
7718 static const ARMCPRegInfo tlbios_reginfo
[] = {
7719 { .name
= "TLBI_VMALLE1OS", .state
= ARM_CP_STATE_AA64
,
7720 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 0,
7721 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7722 .fgt
= FGT_TLBIVMALLE1OS
,
7723 .writefn
= tlbi_aa64_vmalle1is_write
},
7724 { .name
= "TLBI_VAE1OS", .state
= ARM_CP_STATE_AA64
,
7725 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 1,
7726 .fgt
= FGT_TLBIVAE1OS
,
7727 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7728 .writefn
= tlbi_aa64_vae1is_write
},
7729 { .name
= "TLBI_ASIDE1OS", .state
= ARM_CP_STATE_AA64
,
7730 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 2,
7731 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7732 .fgt
= FGT_TLBIASIDE1OS
,
7733 .writefn
= tlbi_aa64_vmalle1is_write
},
7734 { .name
= "TLBI_VAAE1OS", .state
= ARM_CP_STATE_AA64
,
7735 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 3,
7736 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7737 .fgt
= FGT_TLBIVAAE1OS
,
7738 .writefn
= tlbi_aa64_vae1is_write
},
7739 { .name
= "TLBI_VALE1OS", .state
= ARM_CP_STATE_AA64
,
7740 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 5,
7741 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7742 .fgt
= FGT_TLBIVALE1OS
,
7743 .writefn
= tlbi_aa64_vae1is_write
},
7744 { .name
= "TLBI_VAALE1OS", .state
= ARM_CP_STATE_AA64
,
7745 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 1, .opc2
= 7,
7746 .access
= PL1_W
, .accessfn
= access_ttlbos
, .type
= ARM_CP_NO_RAW
,
7747 .fgt
= FGT_TLBIVAALE1OS
,
7748 .writefn
= tlbi_aa64_vae1is_write
},
7749 { .name
= "TLBI_ALLE2OS", .state
= ARM_CP_STATE_AA64
,
7750 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 0,
7751 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7752 .writefn
= tlbi_aa64_alle2is_write
},
7753 { .name
= "TLBI_VAE2OS", .state
= ARM_CP_STATE_AA64
,
7754 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 1,
7755 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7756 .writefn
= tlbi_aa64_vae2is_write
},
7757 { .name
= "TLBI_ALLE1OS", .state
= ARM_CP_STATE_AA64
,
7758 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 4,
7759 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7760 .writefn
= tlbi_aa64_alle1is_write
},
7761 { .name
= "TLBI_VALE2OS", .state
= ARM_CP_STATE_AA64
,
7762 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 5,
7763 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_EL3_NO_EL2_UNDEF
,
7764 .writefn
= tlbi_aa64_vae2is_write
},
7765 { .name
= "TLBI_VMALLS12E1OS", .state
= ARM_CP_STATE_AA64
,
7766 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 1, .opc2
= 6,
7767 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
7768 .writefn
= tlbi_aa64_alle1is_write
},
7769 { .name
= "TLBI_IPAS2E1OS", .state
= ARM_CP_STATE_AA64
,
7770 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 0,
7771 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7772 { .name
= "TLBI_RIPAS2E1OS", .state
= ARM_CP_STATE_AA64
,
7773 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 3,
7774 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7775 { .name
= "TLBI_IPAS2LE1OS", .state
= ARM_CP_STATE_AA64
,
7776 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 4,
7777 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7778 { .name
= "TLBI_RIPAS2LE1OS", .state
= ARM_CP_STATE_AA64
,
7779 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 7,
7780 .access
= PL2_W
, .type
= ARM_CP_NOP
},
7781 { .name
= "TLBI_ALLE3OS", .state
= ARM_CP_STATE_AA64
,
7782 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 0,
7783 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7784 .writefn
= tlbi_aa64_alle3is_write
},
7785 { .name
= "TLBI_VAE3OS", .state
= ARM_CP_STATE_AA64
,
7786 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 1,
7787 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7788 .writefn
= tlbi_aa64_vae3is_write
},
7789 { .name
= "TLBI_VALE3OS", .state
= ARM_CP_STATE_AA64
,
7790 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 1, .opc2
= 5,
7791 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
7792 .writefn
= tlbi_aa64_vae3is_write
},
7795 static uint64_t rndr_readfn(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7800 /* Success sets NZCV = 0000. */
7801 env
->NF
= env
->CF
= env
->VF
= 0, env
->ZF
= 1;
7803 if (qemu_guest_getrandom(&ret
, sizeof(ret
), &err
) < 0) {
7805 * ??? Failed, for unknown reasons in the crypto subsystem.
7806 * The best we can do is log the reason and return the
7807 * timed-out indication to the guest. There is no reason
7808 * we know to expect this failure to be transitory, so the
7809 * guest may well hang retrying the operation.
7811 qemu_log_mask(LOG_UNIMP
, "%s: Crypto failure: %s",
7812 ri
->name
, error_get_pretty(err
));
7815 env
->ZF
= 0; /* NZCF = 0100 */
7821 /* We do not support re-seeding, so the two registers operate the same. */
7822 static const ARMCPRegInfo rndr_reginfo
[] = {
7823 { .name
= "RNDR", .state
= ARM_CP_STATE_AA64
,
7824 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
7825 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 0,
7826 .access
= PL0_R
, .readfn
= rndr_readfn
},
7827 { .name
= "RNDRRS", .state
= ARM_CP_STATE_AA64
,
7828 .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
| ARM_CP_IO
,
7829 .opc0
= 3, .opc1
= 3, .crn
= 2, .crm
= 4, .opc2
= 1,
7830 .access
= PL0_R
, .readfn
= rndr_readfn
},
7833 static void dccvap_writefn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
,
7837 ARMCPU
*cpu
= env_archcpu(env
);
7838 /* CTR_EL0 System register -> DminLine, bits [19:16] */
7839 uint64_t dline_size
= 4 << ((cpu
->ctr
>> 16) & 0xF);
7840 uint64_t vaddr_in
= (uint64_t) value
;
7841 uint64_t vaddr
= vaddr_in
& ~(dline_size
- 1);
7843 int mem_idx
= cpu_mmu_index(env
, false);
7845 /* This won't be crossing page boundaries */
7846 haddr
= probe_read(env
, vaddr
, dline_size
, mem_idx
, GETPC());
7848 #ifndef CONFIG_USER_ONLY
7853 /* RCU lock is already being held */
7854 mr
= memory_region_from_host(haddr
, &offset
);
7857 memory_region_writeback(mr
, offset
, dline_size
);
7859 #endif /*CONFIG_USER_ONLY*/
7862 /* Handled by hardware accelerator. */
7863 g_assert_not_reached();
7864 #endif /* CONFIG_TCG */
7867 static const ARMCPRegInfo dcpop_reg
[] = {
7868 { .name
= "DC_CVAP", .state
= ARM_CP_STATE_AA64
,
7869 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 1,
7870 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
7872 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
7875 static const ARMCPRegInfo dcpodp_reg
[] = {
7876 { .name
= "DC_CVADP", .state
= ARM_CP_STATE_AA64
,
7877 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 1,
7878 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_SUPPRESS_TB_END
,
7880 .accessfn
= aa64_cacheop_poc_access
, .writefn
= dccvap_writefn
},
7883 static CPAccessResult
access_aa64_tid5(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7886 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID5
)) {
7887 return CP_ACCESS_TRAP_EL2
;
7890 return CP_ACCESS_OK
;
7893 static CPAccessResult
access_mte(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7896 int el
= arm_current_el(env
);
7897 if (el
< 2 && arm_is_el2_enabled(env
)) {
7898 uint64_t hcr
= arm_hcr_el2_eff(env
);
7899 if (!(hcr
& HCR_ATA
) && (!(hcr
& HCR_E2H
) || !(hcr
& HCR_TGE
))) {
7900 return CP_ACCESS_TRAP_EL2
;
7904 arm_feature(env
, ARM_FEATURE_EL3
) &&
7905 !(env
->cp15
.scr_el3
& SCR_ATA
)) {
7906 return CP_ACCESS_TRAP_EL3
;
7908 return CP_ACCESS_OK
;
7911 static CPAccessResult
access_tfsr_el1(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7914 CPAccessResult nv1
= access_nv1(env
, ri
, isread
);
7916 if (nv1
!= CP_ACCESS_OK
) {
7919 return access_mte(env
, ri
, isread
);
7922 static CPAccessResult
access_tfsr_el2(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
7926 * TFSR_EL2: similar to generic access_mte(), but we need to
7927 * account for FEAT_NV. At EL1 this must be a FEAT_NV access;
7928 * if NV2 is enabled then we will redirect this to TFSR_EL1
7929 * after doing the HCR and SCR ATA traps; otherwise this will
7930 * be a trap to EL2 and the HCR/SCR traps do not apply.
7932 int el
= arm_current_el(env
);
7934 if (el
== 1 && (arm_hcr_el2_eff(env
) & HCR_NV2
)) {
7935 return CP_ACCESS_OK
;
7937 if (el
< 2 && arm_is_el2_enabled(env
)) {
7938 uint64_t hcr
= arm_hcr_el2_eff(env
);
7939 if (!(hcr
& HCR_ATA
) && (!(hcr
& HCR_E2H
) || !(hcr
& HCR_TGE
))) {
7940 return CP_ACCESS_TRAP_EL2
;
7944 arm_feature(env
, ARM_FEATURE_EL3
) &&
7945 !(env
->cp15
.scr_el3
& SCR_ATA
)) {
7946 return CP_ACCESS_TRAP_EL3
;
7948 return CP_ACCESS_OK
;
7951 static uint64_t tco_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
7953 return env
->pstate
& PSTATE_TCO
;
7956 static void tco_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
7958 env
->pstate
= (env
->pstate
& ~PSTATE_TCO
) | (val
& PSTATE_TCO
);
7961 static const ARMCPRegInfo mte_reginfo
[] = {
7962 { .name
= "TFSRE0_EL1", .state
= ARM_CP_STATE_AA64
,
7963 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 1,
7964 .access
= PL1_RW
, .accessfn
= access_mte
,
7965 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[0]) },
7966 { .name
= "TFSR_EL1", .state
= ARM_CP_STATE_AA64
,
7967 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 6, .opc2
= 0,
7968 .access
= PL1_RW
, .accessfn
= access_tfsr_el1
,
7969 .nv2_redirect_offset
= 0x190 | NV2_REDIR_NV1
,
7970 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[1]) },
7971 { .name
= "TFSR_EL2", .state
= ARM_CP_STATE_AA64
,
7972 .type
= ARM_CP_NV2_REDIRECT
,
7973 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 6, .opc2
= 0,
7974 .access
= PL2_RW
, .accessfn
= access_tfsr_el2
,
7975 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[2]) },
7976 { .name
= "TFSR_EL3", .state
= ARM_CP_STATE_AA64
,
7977 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 6, .opc2
= 0,
7979 .fieldoffset
= offsetof(CPUARMState
, cp15
.tfsr_el
[3]) },
7980 { .name
= "RGSR_EL1", .state
= ARM_CP_STATE_AA64
,
7981 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 5,
7982 .access
= PL1_RW
, .accessfn
= access_mte
,
7983 .fieldoffset
= offsetof(CPUARMState
, cp15
.rgsr_el1
) },
7984 { .name
= "GCR_EL1", .state
= ARM_CP_STATE_AA64
,
7985 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 6,
7986 .access
= PL1_RW
, .accessfn
= access_mte
,
7987 .fieldoffset
= offsetof(CPUARMState
, cp15
.gcr_el1
) },
7988 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
7989 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
7990 .type
= ARM_CP_NO_RAW
,
7991 .access
= PL0_RW
, .readfn
= tco_read
, .writefn
= tco_write
},
7992 { .name
= "DC_IGVAC", .state
= ARM_CP_STATE_AA64
,
7993 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 3,
7994 .type
= ARM_CP_NOP
, .access
= PL1_W
,
7996 .accessfn
= aa64_cacheop_poc_access
},
7997 { .name
= "DC_IGSW", .state
= ARM_CP_STATE_AA64
,
7998 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 4,
8000 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
8001 { .name
= "DC_IGDVAC", .state
= ARM_CP_STATE_AA64
,
8002 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 5,
8003 .type
= ARM_CP_NOP
, .access
= PL1_W
,
8005 .accessfn
= aa64_cacheop_poc_access
},
8006 { .name
= "DC_IGDSW", .state
= ARM_CP_STATE_AA64
,
8007 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 6,
8009 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
8010 { .name
= "DC_CGSW", .state
= ARM_CP_STATE_AA64
,
8011 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 4,
8013 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
8014 { .name
= "DC_CGDSW", .state
= ARM_CP_STATE_AA64
,
8015 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 6,
8017 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
8018 { .name
= "DC_CIGSW", .state
= ARM_CP_STATE_AA64
,
8019 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 4,
8021 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
8022 { .name
= "DC_CIGDSW", .state
= ARM_CP_STATE_AA64
,
8023 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 6,
8025 .type
= ARM_CP_NOP
, .access
= PL1_W
, .accessfn
= access_tsw
},
8028 static const ARMCPRegInfo mte_tco_ro_reginfo
[] = {
8029 { .name
= "TCO", .state
= ARM_CP_STATE_AA64
,
8030 .opc0
= 3, .opc1
= 3, .crn
= 4, .crm
= 2, .opc2
= 7,
8031 .type
= ARM_CP_CONST
, .access
= PL0_RW
, },
8034 static const ARMCPRegInfo mte_el0_cacheop_reginfo
[] = {
8035 { .name
= "DC_CGVAC", .state
= ARM_CP_STATE_AA64
,
8036 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 3,
8037 .type
= ARM_CP_NOP
, .access
= PL0_W
,
8039 .accessfn
= aa64_cacheop_poc_access
},
8040 { .name
= "DC_CGDVAC", .state
= ARM_CP_STATE_AA64
,
8041 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 5,
8042 .type
= ARM_CP_NOP
, .access
= PL0_W
,
8044 .accessfn
= aa64_cacheop_poc_access
},
8045 { .name
= "DC_CGVAP", .state
= ARM_CP_STATE_AA64
,
8046 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 3,
8047 .type
= ARM_CP_NOP
, .access
= PL0_W
,
8049 .accessfn
= aa64_cacheop_poc_access
},
8050 { .name
= "DC_CGDVAP", .state
= ARM_CP_STATE_AA64
,
8051 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 12, .opc2
= 5,
8052 .type
= ARM_CP_NOP
, .access
= PL0_W
,
8054 .accessfn
= aa64_cacheop_poc_access
},
8055 { .name
= "DC_CGVADP", .state
= ARM_CP_STATE_AA64
,
8056 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 3,
8057 .type
= ARM_CP_NOP
, .access
= PL0_W
,
8059 .accessfn
= aa64_cacheop_poc_access
},
8060 { .name
= "DC_CGDVADP", .state
= ARM_CP_STATE_AA64
,
8061 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 13, .opc2
= 5,
8062 .type
= ARM_CP_NOP
, .access
= PL0_W
,
8064 .accessfn
= aa64_cacheop_poc_access
},
8065 { .name
= "DC_CIGVAC", .state
= ARM_CP_STATE_AA64
,
8066 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 3,
8067 .type
= ARM_CP_NOP
, .access
= PL0_W
,
8069 .accessfn
= aa64_cacheop_poc_access
},
8070 { .name
= "DC_CIGDVAC", .state
= ARM_CP_STATE_AA64
,
8071 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 5,
8072 .type
= ARM_CP_NOP
, .access
= PL0_W
,
8074 .accessfn
= aa64_cacheop_poc_access
},
8075 { .name
= "DC_GVA", .state
= ARM_CP_STATE_AA64
,
8076 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 3,
8077 .access
= PL0_W
, .type
= ARM_CP_DC_GVA
,
8078 #ifndef CONFIG_USER_ONLY
8079 /* Avoid overhead of an access check that always passes in user-mode */
8080 .accessfn
= aa64_zva_access
,
8084 { .name
= "DC_GZVA", .state
= ARM_CP_STATE_AA64
,
8085 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 4,
8086 .access
= PL0_W
, .type
= ARM_CP_DC_GZVA
,
8087 #ifndef CONFIG_USER_ONLY
8088 /* Avoid overhead of an access check that always passes in user-mode */
8089 .accessfn
= aa64_zva_access
,
8095 static CPAccessResult
access_scxtnum(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8098 uint64_t hcr
= arm_hcr_el2_eff(env
);
8099 int el
= arm_current_el(env
);
8101 if (el
== 0 && !((hcr
& HCR_E2H
) && (hcr
& HCR_TGE
))) {
8102 if (env
->cp15
.sctlr_el
[1] & SCTLR_TSCXT
) {
8103 if (hcr
& HCR_TGE
) {
8104 return CP_ACCESS_TRAP_EL2
;
8106 return CP_ACCESS_TRAP
;
8108 } else if (el
< 2 && (env
->cp15
.sctlr_el
[2] & SCTLR_TSCXT
)) {
8109 return CP_ACCESS_TRAP_EL2
;
8111 if (el
< 2 && arm_is_el2_enabled(env
) && !(hcr
& HCR_ENSCXT
)) {
8112 return CP_ACCESS_TRAP_EL2
;
8115 && arm_feature(env
, ARM_FEATURE_EL3
)
8116 && !(env
->cp15
.scr_el3
& SCR_ENSCXT
)) {
8117 return CP_ACCESS_TRAP_EL3
;
8119 return CP_ACCESS_OK
;
8122 static CPAccessResult
access_scxtnum_el1(CPUARMState
*env
,
8123 const ARMCPRegInfo
*ri
,
8126 CPAccessResult nv1
= access_nv1(env
, ri
, isread
);
8128 if (nv1
!= CP_ACCESS_OK
) {
8131 return access_scxtnum(env
, ri
, isread
);
8134 static const ARMCPRegInfo scxtnum_reginfo
[] = {
8135 { .name
= "SCXTNUM_EL0", .state
= ARM_CP_STATE_AA64
,
8136 .opc0
= 3, .opc1
= 3, .crn
= 13, .crm
= 0, .opc2
= 7,
8137 .access
= PL0_RW
, .accessfn
= access_scxtnum
,
8138 .fgt
= FGT_SCXTNUM_EL0
,
8139 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[0]) },
8140 { .name
= "SCXTNUM_EL1", .state
= ARM_CP_STATE_AA64
,
8141 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 7,
8142 .access
= PL1_RW
, .accessfn
= access_scxtnum_el1
,
8143 .fgt
= FGT_SCXTNUM_EL1
,
8144 .nv2_redirect_offset
= 0x188 | NV2_REDIR_NV1
,
8145 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[1]) },
8146 { .name
= "SCXTNUM_EL2", .state
= ARM_CP_STATE_AA64
,
8147 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 7,
8148 .access
= PL2_RW
, .accessfn
= access_scxtnum
,
8149 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[2]) },
8150 { .name
= "SCXTNUM_EL3", .state
= ARM_CP_STATE_AA64
,
8151 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 7,
8153 .fieldoffset
= offsetof(CPUARMState
, scxtnum_el
[3]) },
8156 static CPAccessResult
access_fgt(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8159 if (arm_current_el(env
) == 2 &&
8160 arm_feature(env
, ARM_FEATURE_EL3
) && !(env
->cp15
.scr_el3
& SCR_FGTEN
)) {
8161 return CP_ACCESS_TRAP_EL3
;
8163 return CP_ACCESS_OK
;
8166 static const ARMCPRegInfo fgt_reginfo
[] = {
8167 { .name
= "HFGRTR_EL2", .state
= ARM_CP_STATE_AA64
,
8168 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 4,
8169 .nv2_redirect_offset
= 0x1b8,
8170 .access
= PL2_RW
, .accessfn
= access_fgt
,
8171 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_read
[FGTREG_HFGRTR
]) },
8172 { .name
= "HFGWTR_EL2", .state
= ARM_CP_STATE_AA64
,
8173 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 5,
8174 .nv2_redirect_offset
= 0x1c0,
8175 .access
= PL2_RW
, .accessfn
= access_fgt
,
8176 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_write
[FGTREG_HFGWTR
]) },
8177 { .name
= "HDFGRTR_EL2", .state
= ARM_CP_STATE_AA64
,
8178 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 1, .opc2
= 4,
8179 .nv2_redirect_offset
= 0x1d0,
8180 .access
= PL2_RW
, .accessfn
= access_fgt
,
8181 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_read
[FGTREG_HDFGRTR
]) },
8182 { .name
= "HDFGWTR_EL2", .state
= ARM_CP_STATE_AA64
,
8183 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 1, .opc2
= 5,
8184 .nv2_redirect_offset
= 0x1d8,
8185 .access
= PL2_RW
, .accessfn
= access_fgt
,
8186 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_write
[FGTREG_HDFGWTR
]) },
8187 { .name
= "HFGITR_EL2", .state
= ARM_CP_STATE_AA64
,
8188 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 6,
8189 .nv2_redirect_offset
= 0x1c8,
8190 .access
= PL2_RW
, .accessfn
= access_fgt
,
8191 .fieldoffset
= offsetof(CPUARMState
, cp15
.fgt_exec
[FGTREG_HFGITR
]) },
8194 static void vncr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8198 * Clear the RES0 bottom 12 bits; this means at runtime we can guarantee
8199 * that VNCR_EL2 + offset is 64-bit aligned. We don't need to do anything
8200 * about the RESS bits at the top -- we choose the "generate an EL2
8201 * translation abort on use" CONSTRAINED UNPREDICTABLE option (i.e. let
8202 * the ptw.c code detect the resulting invalid address).
8204 env
->cp15
.vncr_el2
= value
& ~0xfffULL
;
8207 static const ARMCPRegInfo nv2_reginfo
[] = {
8208 { .name
= "VNCR_EL2", .state
= ARM_CP_STATE_AA64
,
8209 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 2, .opc2
= 0,
8211 .writefn
= vncr_write
,
8212 .nv2_redirect_offset
= 0xb0,
8213 .fieldoffset
= offsetof(CPUARMState
, cp15
.vncr_el2
) },
8216 #endif /* TARGET_AARCH64 */
8218 static CPAccessResult
access_predinv(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8221 int el
= arm_current_el(env
);
8224 uint64_t sctlr
= arm_sctlr(env
, el
);
8225 if (!(sctlr
& SCTLR_EnRCTX
)) {
8226 return CP_ACCESS_TRAP
;
8228 } else if (el
== 1) {
8229 uint64_t hcr
= arm_hcr_el2_eff(env
);
8231 return CP_ACCESS_TRAP_EL2
;
8234 return CP_ACCESS_OK
;
8237 static const ARMCPRegInfo predinv_reginfo
[] = {
8238 { .name
= "CFP_RCTX", .state
= ARM_CP_STATE_AA64
,
8239 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 4,
8241 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
8242 { .name
= "DVP_RCTX", .state
= ARM_CP_STATE_AA64
,
8243 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 5,
8245 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
8246 { .name
= "CPP_RCTX", .state
= ARM_CP_STATE_AA64
,
8247 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 3, .opc2
= 7,
8249 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
8251 * Note the AArch32 opcodes have a different OPC1.
8253 { .name
= "CFPRCTX", .state
= ARM_CP_STATE_AA32
,
8254 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 4,
8256 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
8257 { .name
= "DVPRCTX", .state
= ARM_CP_STATE_AA32
,
8258 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 5,
8260 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
8261 { .name
= "CPPRCTX", .state
= ARM_CP_STATE_AA32
,
8262 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 3, .opc2
= 7,
8264 .type
= ARM_CP_NOP
, .access
= PL0_W
, .accessfn
= access_predinv
},
8267 static uint64_t ccsidr2_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
8269 /* Read the high 32 bits of the current CCSIDR */
8270 return extract64(ccsidr_read(env
, ri
), 32, 32);
8273 static const ARMCPRegInfo ccsidr2_reginfo
[] = {
8274 { .name
= "CCSIDR2", .state
= ARM_CP_STATE_BOTH
,
8275 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 2,
8277 .accessfn
= access_tid4
,
8278 .readfn
= ccsidr2_read
, .type
= ARM_CP_NO_RAW
},
8281 static CPAccessResult
access_aa64_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8284 if ((arm_current_el(env
) < 2) && (arm_hcr_el2_eff(env
) & HCR_TID3
)) {
8285 return CP_ACCESS_TRAP_EL2
;
8288 return CP_ACCESS_OK
;
8291 static CPAccessResult
access_aa32_tid3(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8294 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8295 return access_aa64_tid3(env
, ri
, isread
);
8298 return CP_ACCESS_OK
;
8301 static CPAccessResult
access_jazelle(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
8304 if (arm_current_el(env
) == 1 && (arm_hcr_el2_eff(env
) & HCR_TID0
)) {
8305 return CP_ACCESS_TRAP_EL2
;
8308 return CP_ACCESS_OK
;
8311 static CPAccessResult
access_joscr_jmcr(CPUARMState
*env
,
8312 const ARMCPRegInfo
*ri
, bool isread
)
8315 * HSTR.TJDBX traps JOSCR and JMCR accesses, but it exists only
8316 * in v7A, not in v8A.
8318 if (!arm_feature(env
, ARM_FEATURE_V8
) &&
8319 arm_current_el(env
) < 2 && !arm_is_secure_below_el3(env
) &&
8320 (env
->cp15
.hstr_el2
& HSTR_TJDBX
)) {
8321 return CP_ACCESS_TRAP_EL2
;
8323 return CP_ACCESS_OK
;
8326 static const ARMCPRegInfo jazelle_regs
[] = {
8328 .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 7, .opc2
= 0,
8329 .access
= PL1_R
, .accessfn
= access_jazelle
,
8330 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8332 .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 7, .opc2
= 0,
8333 .accessfn
= access_joscr_jmcr
,
8334 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8336 .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 7, .opc2
= 0,
8337 .accessfn
= access_joscr_jmcr
,
8338 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8341 static const ARMCPRegInfo contextidr_el2
= {
8342 .name
= "CONTEXTIDR_EL2", .state
= ARM_CP_STATE_AA64
,
8343 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 1,
8345 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[2])
8348 static const ARMCPRegInfo vhe_reginfo
[] = {
8349 { .name
= "TTBR1_EL2", .state
= ARM_CP_STATE_AA64
,
8350 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 1,
8351 .access
= PL2_RW
, .writefn
= vmsa_tcr_ttbr_el2_write
,
8352 .raw_writefn
= raw_write
,
8353 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr1_el
[2]) },
8354 #ifndef CONFIG_USER_ONLY
8355 { .name
= "CNTHV_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
8356 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 2,
8358 offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].cval
),
8359 .type
= ARM_CP_IO
, .access
= PL2_RW
,
8360 .writefn
= gt_hv_cval_write
, .raw_writefn
= raw_write
},
8361 { .name
= "CNTHV_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
8362 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 0,
8363 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
8364 .resetfn
= gt_hv_timer_reset
,
8365 .readfn
= gt_hv_tval_read
, .writefn
= gt_hv_tval_write
},
8366 { .name
= "CNTHV_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
8368 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 3, .opc2
= 1,
8370 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYPVIRT
].ctl
),
8371 .writefn
= gt_hv_ctl_write
, .raw_writefn
= raw_write
},
8372 { .name
= "CNTP_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
8373 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 1,
8374 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
8375 .access
= PL2_RW
, .accessfn
= e2h_access
,
8376 .nv2_redirect_offset
= 0x180 | NV2_REDIR_NO_NV1
,
8377 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
8378 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
},
8379 { .name
= "CNTV_CTL_EL02", .state
= ARM_CP_STATE_AA64
,
8380 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 1,
8381 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
8382 .access
= PL2_RW
, .accessfn
= e2h_access
,
8383 .nv2_redirect_offset
= 0x170 | NV2_REDIR_NO_NV1
,
8384 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
8385 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
},
8386 { .name
= "CNTP_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
8387 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 0,
8388 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
8389 .access
= PL2_RW
, .accessfn
= e2h_access
,
8390 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
},
8391 { .name
= "CNTV_TVAL_EL02", .state
= ARM_CP_STATE_AA64
,
8392 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 0,
8393 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
| ARM_CP_ALIAS
,
8394 .access
= PL2_RW
, .accessfn
= e2h_access
,
8395 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
},
8396 { .name
= "CNTP_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
8397 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 2, .opc2
= 2,
8398 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
8399 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
8400 .nv2_redirect_offset
= 0x178 | NV2_REDIR_NO_NV1
,
8401 .access
= PL2_RW
, .accessfn
= e2h_access
,
8402 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
},
8403 { .name
= "CNTV_CVAL_EL02", .state
= ARM_CP_STATE_AA64
,
8404 .opc0
= 3, .opc1
= 5, .crn
= 14, .crm
= 3, .opc2
= 2,
8405 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
8406 .nv2_redirect_offset
= 0x168 | NV2_REDIR_NO_NV1
,
8407 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
8408 .access
= PL2_RW
, .accessfn
= e2h_access
,
8409 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
},
8413 #ifndef CONFIG_USER_ONLY
8414 static const ARMCPRegInfo ats1e1_reginfo
[] = {
8415 { .name
= "AT_S1E1RP", .state
= ARM_CP_STATE_AA64
,
8416 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
8417 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
8418 .fgt
= FGT_ATS1E1RP
,
8419 .accessfn
= at_s1e01_access
, .writefn
= ats_write64
},
8420 { .name
= "AT_S1E1WP", .state
= ARM_CP_STATE_AA64
,
8421 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
8422 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
8423 .fgt
= FGT_ATS1E1WP
,
8424 .accessfn
= at_s1e01_access
, .writefn
= ats_write64
},
8427 static const ARMCPRegInfo ats1cp_reginfo
[] = {
8428 { .name
= "ATS1CPRP",
8429 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 0,
8430 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
8431 .writefn
= ats_write
},
8432 { .name
= "ATS1CPWP",
8433 .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 9, .opc2
= 1,
8434 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
,
8435 .writefn
= ats_write
},
8440 * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and
8441 * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field
8442 * is non-zero, which is never for ARMv7, optionally in ARMv8
8443 * and mandatorily for ARMv8.2 and up.
8444 * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's
8445 * implementation is RAZ/WI we can ignore this detail, as we
8448 static const ARMCPRegInfo actlr2_hactlr2_reginfo
[] = {
8449 { .name
= "ACTLR2", .state
= ARM_CP_STATE_AA32
,
8450 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 3,
8451 .access
= PL1_RW
, .accessfn
= access_tacr
,
8452 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
8453 { .name
= "HACTLR2", .state
= ARM_CP_STATE_AA32
,
8454 .cp
= 15, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 3,
8455 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
8459 void register_cp_regs_for_features(ARMCPU
*cpu
)
8461 /* Register all the coprocessor registers based on feature bits */
8462 CPUARMState
*env
= &cpu
->env
;
8463 if (arm_feature(env
, ARM_FEATURE_M
)) {
8464 /* M profile has no coprocessor registers */
8468 define_arm_cp_regs(cpu
, cp_reginfo
);
8469 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
8471 * Must go early as it is full of wildcards that may be
8472 * overridden by later definitions.
8474 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
8477 if (arm_feature(env
, ARM_FEATURE_V6
)) {
8478 /* The ID registers all have impdef reset values */
8479 ARMCPRegInfo v6_idregs
[] = {
8480 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
8481 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
8482 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8483 .accessfn
= access_aa32_tid3
,
8484 .resetvalue
= cpu
->isar
.id_pfr0
},
8486 * ID_PFR1 is not a plain ARM_CP_CONST because we don't know
8487 * the value of the GIC field until after we define these regs.
8489 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
8490 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
8491 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
8492 .accessfn
= access_aa32_tid3
,
8493 #ifdef CONFIG_USER_ONLY
8494 .type
= ARM_CP_CONST
,
8495 .resetvalue
= cpu
->isar
.id_pfr1
,
8497 .type
= ARM_CP_NO_RAW
,
8498 .accessfn
= access_aa32_tid3
,
8499 .readfn
= id_pfr1_read
,
8500 .writefn
= arm_cp_write_ignore
8503 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
8504 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
8505 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8506 .accessfn
= access_aa32_tid3
,
8507 .resetvalue
= cpu
->isar
.id_dfr0
},
8508 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
8509 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
8510 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8511 .accessfn
= access_aa32_tid3
,
8512 .resetvalue
= cpu
->id_afr0
},
8513 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
8514 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
8515 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8516 .accessfn
= access_aa32_tid3
,
8517 .resetvalue
= cpu
->isar
.id_mmfr0
},
8518 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
8519 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
8520 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8521 .accessfn
= access_aa32_tid3
,
8522 .resetvalue
= cpu
->isar
.id_mmfr1
},
8523 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
8524 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
8525 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8526 .accessfn
= access_aa32_tid3
,
8527 .resetvalue
= cpu
->isar
.id_mmfr2
},
8528 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
8529 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
8530 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8531 .accessfn
= access_aa32_tid3
,
8532 .resetvalue
= cpu
->isar
.id_mmfr3
},
8533 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
8534 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
8535 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8536 .accessfn
= access_aa32_tid3
,
8537 .resetvalue
= cpu
->isar
.id_isar0
},
8538 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
8539 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
8540 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8541 .accessfn
= access_aa32_tid3
,
8542 .resetvalue
= cpu
->isar
.id_isar1
},
8543 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
8544 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
8545 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8546 .accessfn
= access_aa32_tid3
,
8547 .resetvalue
= cpu
->isar
.id_isar2
},
8548 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
8549 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
8550 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8551 .accessfn
= access_aa32_tid3
,
8552 .resetvalue
= cpu
->isar
.id_isar3
},
8553 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
8554 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
8555 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8556 .accessfn
= access_aa32_tid3
,
8557 .resetvalue
= cpu
->isar
.id_isar4
},
8558 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
8559 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
8560 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8561 .accessfn
= access_aa32_tid3
,
8562 .resetvalue
= cpu
->isar
.id_isar5
},
8563 { .name
= "ID_MMFR4", .state
= ARM_CP_STATE_BOTH
,
8564 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 6,
8565 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8566 .accessfn
= access_aa32_tid3
,
8567 .resetvalue
= cpu
->isar
.id_mmfr4
},
8568 { .name
= "ID_ISAR6", .state
= ARM_CP_STATE_BOTH
,
8569 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 7,
8570 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8571 .accessfn
= access_aa32_tid3
,
8572 .resetvalue
= cpu
->isar
.id_isar6
},
8574 define_arm_cp_regs(cpu
, v6_idregs
);
8575 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
8577 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
8579 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
8580 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
8582 if (arm_feature(env
, ARM_FEATURE_V7MP
) &&
8583 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
8584 define_arm_cp_regs(cpu
, v7mp_cp_reginfo
);
8586 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
8587 define_arm_cp_regs(cpu
, pmovsset_cp_reginfo
);
8589 if (arm_feature(env
, ARM_FEATURE_V7
)) {
8590 ARMCPRegInfo clidr
= {
8591 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
8592 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
8593 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8594 .accessfn
= access_tid4
,
8595 .fgt
= FGT_CLIDR_EL1
,
8596 .resetvalue
= cpu
->clidr
8598 define_one_arm_cp_reg(cpu
, &clidr
);
8599 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
8600 define_debug_regs(cpu
);
8601 define_pmu_regs(cpu
);
8603 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
8605 if (arm_feature(env
, ARM_FEATURE_V8
)) {
8607 * v8 ID registers, which all have impdef reset values.
8608 * Note that within the ID register ranges the unused slots
8609 * must all RAZ, not UNDEF; future architecture versions may
8610 * define new registers here.
8611 * ID registers which are AArch64 views of the AArch32 ID registers
8612 * which already existed in v6 and v7 are handled elsewhere,
8616 ARMCPRegInfo v8_idregs
[] = {
8618 * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system
8619 * emulation because we don't know the right value for the
8620 * GIC field until after we define these regs.
8622 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8623 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
8625 #ifdef CONFIG_USER_ONLY
8626 .type
= ARM_CP_CONST
,
8627 .resetvalue
= cpu
->isar
.id_aa64pfr0
8629 .type
= ARM_CP_NO_RAW
,
8630 .accessfn
= access_aa64_tid3
,
8631 .readfn
= id_aa64pfr0_read
,
8632 .writefn
= arm_cp_write_ignore
8635 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8636 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
8637 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8638 .accessfn
= access_aa64_tid3
,
8639 .resetvalue
= cpu
->isar
.id_aa64pfr1
},
8640 { .name
= "ID_AA64PFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8641 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 2,
8642 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8643 .accessfn
= access_aa64_tid3
,
8645 { .name
= "ID_AA64PFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8646 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 3,
8647 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8648 .accessfn
= access_aa64_tid3
,
8650 { .name
= "ID_AA64ZFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8651 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 4,
8652 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8653 .accessfn
= access_aa64_tid3
,
8654 .resetvalue
= cpu
->isar
.id_aa64zfr0
},
8655 { .name
= "ID_AA64SMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8656 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 5,
8657 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8658 .accessfn
= access_aa64_tid3
,
8659 .resetvalue
= cpu
->isar
.id_aa64smfr0
},
8660 { .name
= "ID_AA64PFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8661 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 6,
8662 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8663 .accessfn
= access_aa64_tid3
,
8665 { .name
= "ID_AA64PFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8666 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 7,
8667 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8668 .accessfn
= access_aa64_tid3
,
8670 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8671 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
8672 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8673 .accessfn
= access_aa64_tid3
,
8674 .resetvalue
= cpu
->isar
.id_aa64dfr0
},
8675 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8676 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
8677 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8678 .accessfn
= access_aa64_tid3
,
8679 .resetvalue
= cpu
->isar
.id_aa64dfr1
},
8680 { .name
= "ID_AA64DFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8681 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 2,
8682 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8683 .accessfn
= access_aa64_tid3
,
8685 { .name
= "ID_AA64DFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8686 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 3,
8687 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8688 .accessfn
= access_aa64_tid3
,
8690 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8691 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
8692 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8693 .accessfn
= access_aa64_tid3
,
8694 .resetvalue
= cpu
->id_aa64afr0
},
8695 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8696 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
8697 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8698 .accessfn
= access_aa64_tid3
,
8699 .resetvalue
= cpu
->id_aa64afr1
},
8700 { .name
= "ID_AA64AFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8701 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 6,
8702 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8703 .accessfn
= access_aa64_tid3
,
8705 { .name
= "ID_AA64AFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8706 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 7,
8707 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8708 .accessfn
= access_aa64_tid3
,
8710 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
8711 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
8712 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8713 .accessfn
= access_aa64_tid3
,
8714 .resetvalue
= cpu
->isar
.id_aa64isar0
},
8715 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
8716 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
8717 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8718 .accessfn
= access_aa64_tid3
,
8719 .resetvalue
= cpu
->isar
.id_aa64isar1
},
8720 { .name
= "ID_AA64ISAR2_EL1", .state
= ARM_CP_STATE_AA64
,
8721 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 2,
8722 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8723 .accessfn
= access_aa64_tid3
,
8724 .resetvalue
= cpu
->isar
.id_aa64isar2
},
8725 { .name
= "ID_AA64ISAR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8726 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 3,
8727 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8728 .accessfn
= access_aa64_tid3
,
8730 { .name
= "ID_AA64ISAR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8731 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 4,
8732 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8733 .accessfn
= access_aa64_tid3
,
8735 { .name
= "ID_AA64ISAR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8736 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 5,
8737 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8738 .accessfn
= access_aa64_tid3
,
8740 { .name
= "ID_AA64ISAR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8741 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 6,
8742 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8743 .accessfn
= access_aa64_tid3
,
8745 { .name
= "ID_AA64ISAR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8746 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 7,
8747 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8748 .accessfn
= access_aa64_tid3
,
8750 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8751 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
8752 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8753 .accessfn
= access_aa64_tid3
,
8754 .resetvalue
= cpu
->isar
.id_aa64mmfr0
},
8755 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8756 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
8757 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8758 .accessfn
= access_aa64_tid3
,
8759 .resetvalue
= cpu
->isar
.id_aa64mmfr1
},
8760 { .name
= "ID_AA64MMFR2_EL1", .state
= ARM_CP_STATE_AA64
,
8761 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 2,
8762 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8763 .accessfn
= access_aa64_tid3
,
8764 .resetvalue
= cpu
->isar
.id_aa64mmfr2
},
8765 { .name
= "ID_AA64MMFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8766 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 3,
8767 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8768 .accessfn
= access_aa64_tid3
,
8770 { .name
= "ID_AA64MMFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8771 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 4,
8772 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8773 .accessfn
= access_aa64_tid3
,
8775 { .name
= "ID_AA64MMFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8776 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 5,
8777 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8778 .accessfn
= access_aa64_tid3
,
8780 { .name
= "ID_AA64MMFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8781 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 6,
8782 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8783 .accessfn
= access_aa64_tid3
,
8785 { .name
= "ID_AA64MMFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
8786 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 7,
8787 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8788 .accessfn
= access_aa64_tid3
,
8790 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
8791 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
8792 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8793 .accessfn
= access_aa64_tid3
,
8794 .resetvalue
= cpu
->isar
.mvfr0
},
8795 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
8796 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
8797 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8798 .accessfn
= access_aa64_tid3
,
8799 .resetvalue
= cpu
->isar
.mvfr1
},
8800 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
8801 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
8802 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8803 .accessfn
= access_aa64_tid3
,
8804 .resetvalue
= cpu
->isar
.mvfr2
},
8806 * "0, c0, c3, {0,1,2}" are the encodings corresponding to
8807 * AArch64 MVFR[012]_EL1. Define the STATE_AA32 encoding
8808 * as RAZ, since it is in the "reserved for future ID
8809 * registers, RAZ" part of the AArch32 encoding space.
8811 { .name
= "RES_0_C0_C3_0", .state
= ARM_CP_STATE_AA32
,
8812 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
8813 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8814 .accessfn
= access_aa64_tid3
,
8816 { .name
= "RES_0_C0_C3_1", .state
= ARM_CP_STATE_AA32
,
8817 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
8818 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8819 .accessfn
= access_aa64_tid3
,
8821 { .name
= "RES_0_C0_C3_2", .state
= ARM_CP_STATE_AA32
,
8822 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
8823 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8824 .accessfn
= access_aa64_tid3
,
8827 * Other encodings in "0, c0, c3, ..." are STATE_BOTH because
8828 * they're also RAZ for AArch64, and in v8 are gradually
8829 * being filled with AArch64-view-of-AArch32-ID-register
8830 * for new ID registers.
8832 { .name
= "RES_0_C0_C3_3", .state
= ARM_CP_STATE_BOTH
,
8833 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 3,
8834 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8835 .accessfn
= access_aa64_tid3
,
8837 { .name
= "ID_PFR2", .state
= ARM_CP_STATE_BOTH
,
8838 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 4,
8839 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8840 .accessfn
= access_aa64_tid3
,
8841 .resetvalue
= cpu
->isar
.id_pfr2
},
8842 { .name
= "ID_DFR1", .state
= ARM_CP_STATE_BOTH
,
8843 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 5,
8844 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8845 .accessfn
= access_aa64_tid3
,
8846 .resetvalue
= cpu
->isar
.id_dfr1
},
8847 { .name
= "ID_MMFR5", .state
= ARM_CP_STATE_BOTH
,
8848 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 6,
8849 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8850 .accessfn
= access_aa64_tid3
,
8851 .resetvalue
= cpu
->isar
.id_mmfr5
},
8852 { .name
= "RES_0_C0_C3_7", .state
= ARM_CP_STATE_BOTH
,
8853 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 7,
8854 .access
= PL1_R
, .type
= ARM_CP_CONST
,
8855 .accessfn
= access_aa64_tid3
,
8857 { .name
= "PMCEID0", .state
= ARM_CP_STATE_AA32
,
8858 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 6,
8859 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8860 .fgt
= FGT_PMCEIDN_EL0
,
8861 .resetvalue
= extract64(cpu
->pmceid0
, 0, 32) },
8862 { .name
= "PMCEID0_EL0", .state
= ARM_CP_STATE_AA64
,
8863 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 6,
8864 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8865 .fgt
= FGT_PMCEIDN_EL0
,
8866 .resetvalue
= cpu
->pmceid0
},
8867 { .name
= "PMCEID1", .state
= ARM_CP_STATE_AA32
,
8868 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 7,
8869 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8870 .fgt
= FGT_PMCEIDN_EL0
,
8871 .resetvalue
= extract64(cpu
->pmceid1
, 0, 32) },
8872 { .name
= "PMCEID1_EL0", .state
= ARM_CP_STATE_AA64
,
8873 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 7,
8874 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
8875 .fgt
= FGT_PMCEIDN_EL0
,
8876 .resetvalue
= cpu
->pmceid1
},
8878 #ifdef CONFIG_USER_ONLY
8879 static const ARMCPRegUserSpaceInfo v8_user_idregs
[] = {
8880 { .name
= "ID_AA64PFR0_EL1",
8881 .exported_bits
= R_ID_AA64PFR0_FP_MASK
|
8882 R_ID_AA64PFR0_ADVSIMD_MASK
|
8883 R_ID_AA64PFR0_SVE_MASK
|
8884 R_ID_AA64PFR0_DIT_MASK
,
8885 .fixed_bits
= (0x1u
<< R_ID_AA64PFR0_EL0_SHIFT
) |
8886 (0x1u
<< R_ID_AA64PFR0_EL1_SHIFT
) },
8887 { .name
= "ID_AA64PFR1_EL1",
8888 .exported_bits
= R_ID_AA64PFR1_BT_MASK
|
8889 R_ID_AA64PFR1_SSBS_MASK
|
8890 R_ID_AA64PFR1_MTE_MASK
|
8891 R_ID_AA64PFR1_SME_MASK
},
8892 { .name
= "ID_AA64PFR*_EL1_RESERVED",
8894 { .name
= "ID_AA64ZFR0_EL1",
8895 .exported_bits
= R_ID_AA64ZFR0_SVEVER_MASK
|
8896 R_ID_AA64ZFR0_AES_MASK
|
8897 R_ID_AA64ZFR0_BITPERM_MASK
|
8898 R_ID_AA64ZFR0_BFLOAT16_MASK
|
8899 R_ID_AA64ZFR0_SHA3_MASK
|
8900 R_ID_AA64ZFR0_SM4_MASK
|
8901 R_ID_AA64ZFR0_I8MM_MASK
|
8902 R_ID_AA64ZFR0_F32MM_MASK
|
8903 R_ID_AA64ZFR0_F64MM_MASK
},
8904 { .name
= "ID_AA64SMFR0_EL1",
8905 .exported_bits
= R_ID_AA64SMFR0_F32F32_MASK
|
8906 R_ID_AA64SMFR0_BI32I32_MASK
|
8907 R_ID_AA64SMFR0_B16F32_MASK
|
8908 R_ID_AA64SMFR0_F16F32_MASK
|
8909 R_ID_AA64SMFR0_I8I32_MASK
|
8910 R_ID_AA64SMFR0_F16F16_MASK
|
8911 R_ID_AA64SMFR0_B16B16_MASK
|
8912 R_ID_AA64SMFR0_I16I32_MASK
|
8913 R_ID_AA64SMFR0_F64F64_MASK
|
8914 R_ID_AA64SMFR0_I16I64_MASK
|
8915 R_ID_AA64SMFR0_SMEVER_MASK
|
8916 R_ID_AA64SMFR0_FA64_MASK
},
8917 { .name
= "ID_AA64MMFR0_EL1",
8918 .exported_bits
= R_ID_AA64MMFR0_ECV_MASK
,
8919 .fixed_bits
= (0xfu
<< R_ID_AA64MMFR0_TGRAN64_SHIFT
) |
8920 (0xfu
<< R_ID_AA64MMFR0_TGRAN4_SHIFT
) },
8921 { .name
= "ID_AA64MMFR1_EL1",
8922 .exported_bits
= R_ID_AA64MMFR1_AFP_MASK
},
8923 { .name
= "ID_AA64MMFR2_EL1",
8924 .exported_bits
= R_ID_AA64MMFR2_AT_MASK
},
8925 { .name
= "ID_AA64MMFR*_EL1_RESERVED",
8927 { .name
= "ID_AA64DFR0_EL1",
8928 .fixed_bits
= (0x6u
<< R_ID_AA64DFR0_DEBUGVER_SHIFT
) },
8929 { .name
= "ID_AA64DFR1_EL1" },
8930 { .name
= "ID_AA64DFR*_EL1_RESERVED",
8932 { .name
= "ID_AA64AFR*",
8934 { .name
= "ID_AA64ISAR0_EL1",
8935 .exported_bits
= R_ID_AA64ISAR0_AES_MASK
|
8936 R_ID_AA64ISAR0_SHA1_MASK
|
8937 R_ID_AA64ISAR0_SHA2_MASK
|
8938 R_ID_AA64ISAR0_CRC32_MASK
|
8939 R_ID_AA64ISAR0_ATOMIC_MASK
|
8940 R_ID_AA64ISAR0_RDM_MASK
|
8941 R_ID_AA64ISAR0_SHA3_MASK
|
8942 R_ID_AA64ISAR0_SM3_MASK
|
8943 R_ID_AA64ISAR0_SM4_MASK
|
8944 R_ID_AA64ISAR0_DP_MASK
|
8945 R_ID_AA64ISAR0_FHM_MASK
|
8946 R_ID_AA64ISAR0_TS_MASK
|
8947 R_ID_AA64ISAR0_RNDR_MASK
},
8948 { .name
= "ID_AA64ISAR1_EL1",
8949 .exported_bits
= R_ID_AA64ISAR1_DPB_MASK
|
8950 R_ID_AA64ISAR1_APA_MASK
|
8951 R_ID_AA64ISAR1_API_MASK
|
8952 R_ID_AA64ISAR1_JSCVT_MASK
|
8953 R_ID_AA64ISAR1_FCMA_MASK
|
8954 R_ID_AA64ISAR1_LRCPC_MASK
|
8955 R_ID_AA64ISAR1_GPA_MASK
|
8956 R_ID_AA64ISAR1_GPI_MASK
|
8957 R_ID_AA64ISAR1_FRINTTS_MASK
|
8958 R_ID_AA64ISAR1_SB_MASK
|
8959 R_ID_AA64ISAR1_BF16_MASK
|
8960 R_ID_AA64ISAR1_DGH_MASK
|
8961 R_ID_AA64ISAR1_I8MM_MASK
},
8962 { .name
= "ID_AA64ISAR2_EL1",
8963 .exported_bits
= R_ID_AA64ISAR2_WFXT_MASK
|
8964 R_ID_AA64ISAR2_RPRES_MASK
|
8965 R_ID_AA64ISAR2_GPA3_MASK
|
8966 R_ID_AA64ISAR2_APA3_MASK
|
8967 R_ID_AA64ISAR2_MOPS_MASK
|
8968 R_ID_AA64ISAR2_BC_MASK
|
8969 R_ID_AA64ISAR2_RPRFM_MASK
|
8970 R_ID_AA64ISAR2_CSSC_MASK
},
8971 { .name
= "ID_AA64ISAR*_EL1_RESERVED",
8974 modify_arm_cp_regs(v8_idregs
, v8_user_idregs
);
8977 * RVBAR_EL1 and RMR_EL1 only implemented if EL1 is the highest EL.
8978 * TODO: For RMR, a write with bit 1 set should do something with
8979 * cpu_reset(). In the meantime, "the bit is strictly a request",
8980 * so we are in spec just ignoring writes.
8982 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
8983 !arm_feature(env
, ARM_FEATURE_EL2
)) {
8984 ARMCPRegInfo el1_reset_regs
[] = {
8985 { .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_BOTH
,
8986 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
8988 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
) },
8989 { .name
= "RMR_EL1", .state
= ARM_CP_STATE_BOTH
,
8990 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 2,
8991 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
8992 .resetvalue
= arm_feature(env
, ARM_FEATURE_AARCH64
) }
8994 define_arm_cp_regs(cpu
, el1_reset_regs
);
8996 define_arm_cp_regs(cpu
, v8_idregs
);
8997 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
8998 if (cpu_isar_feature(aa64_aa32_el1
, cpu
)) {
8999 define_arm_cp_regs(cpu
, v8_aa32_el1_reginfo
);
9002 for (i
= 4; i
< 16; i
++) {
9004 * Encodings in "0, c0, {c4-c7}, {0-7}" are RAZ for AArch32.
9005 * For pre-v8 cores there are RAZ patterns for these in
9006 * id_pre_v8_midr_cp_reginfo[]; for v8 we do that here.
9007 * v8 extends the "must RAZ" part of the ID register space
9008 * to also cover c0, 0, c{8-15}, {0-7}.
9009 * These are STATE_AA32 because in the AArch64 sysreg space
9010 * c4-c7 is where the AArch64 ID registers live (and we've
9011 * already defined those in v8_idregs[]), and c8-c15 are not
9012 * "must RAZ" for AArch64.
9014 g_autofree
char *name
= g_strdup_printf("RES_0_C0_C%d_X", i
);
9015 ARMCPRegInfo v8_aa32_raz_idregs
= {
9017 .state
= ARM_CP_STATE_AA32
,
9018 .cp
= 15, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= CP_ANY
,
9019 .access
= PL1_R
, .type
= ARM_CP_CONST
,
9020 .accessfn
= access_aa64_tid3
,
9022 define_one_arm_cp_reg(cpu
, &v8_aa32_raz_idregs
);
9027 * Register the base EL2 cpregs.
9028 * Pre v8, these registers are implemented only as part of the
9029 * Virtualization Extensions (EL2 present). Beginning with v8,
9030 * if EL2 is missing but EL3 is enabled, mostly these become
9031 * RES0 from EL3, with some specific exceptions.
9033 if (arm_feature(env
, ARM_FEATURE_EL2
)
9034 || (arm_feature(env
, ARM_FEATURE_EL3
)
9035 && arm_feature(env
, ARM_FEATURE_V8
))) {
9036 uint64_t vmpidr_def
= mpidr_read_val(env
);
9037 ARMCPRegInfo vpidr_regs
[] = {
9038 { .name
= "VPIDR", .state
= ARM_CP_STATE_AA32
,
9039 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
9040 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
9041 .resetvalue
= cpu
->midr
,
9042 .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_C_NZ
,
9043 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vpidr_el2
) },
9044 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
9045 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
9046 .access
= PL2_RW
, .resetvalue
= cpu
->midr
,
9047 .type
= ARM_CP_EL3_NO_EL2_C_NZ
,
9048 .nv2_redirect_offset
= 0x88,
9049 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
9050 { .name
= "VMPIDR", .state
= ARM_CP_STATE_AA32
,
9051 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
9052 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
9053 .resetvalue
= vmpidr_def
,
9054 .type
= ARM_CP_ALIAS
| ARM_CP_EL3_NO_EL2_C_NZ
,
9055 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vmpidr_el2
) },
9056 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
9057 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
9058 .access
= PL2_RW
, .resetvalue
= vmpidr_def
,
9059 .type
= ARM_CP_EL3_NO_EL2_C_NZ
,
9060 .nv2_redirect_offset
= 0x50,
9061 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
9064 * The only field of MDCR_EL2 that has a defined architectural reset
9065 * value is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
9067 ARMCPRegInfo mdcr_el2
= {
9068 .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
, .type
= ARM_CP_IO
,
9069 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
9070 .writefn
= mdcr_el2_write
,
9071 .access
= PL2_RW
, .resetvalue
= pmu_num_counters(env
),
9072 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el2
),
9074 define_one_arm_cp_reg(cpu
, &mdcr_el2
);
9075 define_arm_cp_regs(cpu
, vpidr_regs
);
9076 define_arm_cp_regs(cpu
, el2_cp_reginfo
);
9077 if (arm_feature(env
, ARM_FEATURE_V8
)) {
9078 define_arm_cp_regs(cpu
, el2_v8_cp_reginfo
);
9080 if (cpu_isar_feature(aa64_sel2
, cpu
)) {
9081 define_arm_cp_regs(cpu
, el2_sec_cp_reginfo
);
9084 * RVBAR_EL2 and RMR_EL2 only implemented if EL2 is the highest EL.
9085 * See commentary near RMR_EL1.
9087 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
9088 static const ARMCPRegInfo el2_reset_regs
[] = {
9089 { .name
= "RVBAR_EL2", .state
= ARM_CP_STATE_AA64
,
9090 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 1,
9092 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
) },
9093 { .name
= "RVBAR", .type
= ARM_CP_ALIAS
,
9094 .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
9096 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
) },
9097 { .name
= "RMR_EL2", .state
= ARM_CP_STATE_AA64
,
9098 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 2,
9099 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 1 },
9101 define_arm_cp_regs(cpu
, el2_reset_regs
);
9105 /* Register the base EL3 cpregs. */
9106 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
9107 define_arm_cp_regs(cpu
, el3_cp_reginfo
);
9108 ARMCPRegInfo el3_regs
[] = {
9109 { .name
= "RVBAR_EL3", .state
= ARM_CP_STATE_AA64
,
9110 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 1,
9112 .fieldoffset
= offsetof(CPUARMState
, cp15
.rvbar
), },
9113 { .name
= "RMR_EL3", .state
= ARM_CP_STATE_AA64
,
9114 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 2,
9115 .access
= PL3_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 1 },
9116 { .name
= "RMR", .state
= ARM_CP_STATE_AA32
,
9117 .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 2,
9118 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
9119 .resetvalue
= arm_feature(env
, ARM_FEATURE_AARCH64
) },
9120 { .name
= "SCTLR_EL3", .state
= ARM_CP_STATE_AA64
,
9121 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 0,
9123 .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
9124 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[3]),
9125 .resetvalue
= cpu
->reset_sctlr
},
9128 define_arm_cp_regs(cpu
, el3_regs
);
9131 * The behaviour of NSACR is sufficiently various that we don't
9132 * try to describe it in a single reginfo:
9133 * if EL3 is 64 bit, then trap to EL3 from S EL1,
9134 * reads as constant 0xc00 from NS EL1 and NS EL2
9135 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
9136 * if v7 without EL3, register doesn't exist
9137 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
9139 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
9140 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
9141 static const ARMCPRegInfo nsacr
= {
9142 .name
= "NSACR", .type
= ARM_CP_CONST
,
9143 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
9144 .access
= PL1_RW
, .accessfn
= nsacr_access
,
9147 define_one_arm_cp_reg(cpu
, &nsacr
);
9149 static const ARMCPRegInfo nsacr
= {
9151 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
9152 .access
= PL3_RW
| PL1_R
,
9154 .fieldoffset
= offsetof(CPUARMState
, cp15
.nsacr
)
9156 define_one_arm_cp_reg(cpu
, &nsacr
);
9159 if (arm_feature(env
, ARM_FEATURE_V8
)) {
9160 static const ARMCPRegInfo nsacr
= {
9161 .name
= "NSACR", .type
= ARM_CP_CONST
,
9162 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
9166 define_one_arm_cp_reg(cpu
, &nsacr
);
9170 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
9171 if (arm_feature(env
, ARM_FEATURE_V6
)) {
9172 /* PMSAv6 not implemented */
9173 assert(arm_feature(env
, ARM_FEATURE_V7
));
9174 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
9175 define_arm_cp_regs(cpu
, pmsav7_cp_reginfo
);
9177 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
9180 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
9181 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
9182 /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */
9183 if (cpu_isar_feature(aa32_hpd
, cpu
)) {
9184 define_one_arm_cp_reg(cpu
, &ttbcr2_reginfo
);
9187 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
9188 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
9190 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
9191 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
9193 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
9194 ARMCPRegInfo vapa_cp_reginfo
[] = {
9195 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
9196 .access
= PL1_RW
, .resetvalue
= 0,
9197 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.par_s
),
9198 offsetoflow32(CPUARMState
, cp15
.par_ns
) },
9199 .writefn
= par_write
},
9200 #ifndef CONFIG_USER_ONLY
9201 /* This underdecoding is safe because the reginfo is NO_RAW. */
9202 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
9203 .access
= PL1_W
, .accessfn
= ats_access
,
9204 .writefn
= ats_write
, .type
= ARM_CP_NO_RAW
| ARM_CP_RAISES_EXC
},
9209 * When LPAE exists this 32-bit PAR register is an alias of the
9210 * 64-bit AArch32 PAR register defined in lpae_cp_reginfo[]
9212 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
9213 vapa_cp_reginfo
[0].type
= ARM_CP_ALIAS
| ARM_CP_NO_GDB
;
9215 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
9217 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
9218 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
9220 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
9221 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
9223 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
9224 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
9226 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
9227 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
9229 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
9230 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
9232 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
9233 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
9235 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
9236 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
9238 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
9239 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
9241 if (cpu_isar_feature(aa32_jazelle
, cpu
)) {
9242 define_arm_cp_regs(cpu
, jazelle_regs
);
9245 * Slightly awkwardly, the OMAP and StrongARM cores need all of
9246 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
9247 * be read-only (ie write causes UNDEF exception).
9250 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
9252 * Pre-v8 MIDR space.
9253 * Note that the MIDR isn't a simple constant register because
9254 * of the TI925 behaviour where writes to another register can
9255 * cause the MIDR value to change.
9257 * Unimplemented registers in the c15 0 0 0 space default to
9258 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
9259 * and friends override accordingly.
9262 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
9263 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
9264 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
9265 .readfn
= midr_read
,
9266 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
9267 .type
= ARM_CP_OVERRIDE
},
9268 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
9270 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
9271 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9273 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
9274 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9276 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
9277 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9279 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
9280 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9282 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
9283 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9285 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
9286 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
9287 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
9288 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
, .resetvalue
= cpu
->midr
,
9289 .fgt
= FGT_MIDR_EL1
,
9290 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
9291 .readfn
= midr_read
},
9292 /* crn = 0 op1 = 0 crm = 0 op2 = 7 : AArch32 aliases of MIDR */
9293 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
9294 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 7,
9295 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
9296 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
9297 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
9299 .accessfn
= access_aa64_tid1
,
9300 .fgt
= FGT_REVIDR_EL1
,
9301 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->revidr
},
9303 ARMCPRegInfo id_v8_midr_alias_cp_reginfo
= {
9304 .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
| ARM_CP_NO_GDB
,
9305 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
9306 .access
= PL1_R
, .resetvalue
= cpu
->midr
9308 ARMCPRegInfo id_cp_reginfo
[] = {
9309 /* These are common to v8 and pre-v8 */
9311 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
9312 .access
= PL1_R
, .accessfn
= ctr_el0_access
,
9313 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
9314 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
9315 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
9316 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
9318 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
9319 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
9321 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
9323 .accessfn
= access_aa32_tid1
,
9324 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
9326 /* TLBTR is specific to VMSA */
9327 ARMCPRegInfo id_tlbtr_reginfo
= {
9329 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
9331 .accessfn
= access_aa32_tid1
,
9332 .type
= ARM_CP_CONST
, .resetvalue
= 0,
9334 /* MPUIR is specific to PMSA V6+ */
9335 ARMCPRegInfo id_mpuir_reginfo
= {
9337 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
9338 .access
= PL1_R
, .type
= ARM_CP_CONST
,
9339 .resetvalue
= cpu
->pmsav7_dregion
<< 8
9341 /* HMPUIR is specific to PMSA V8 */
9342 ARMCPRegInfo id_hmpuir_reginfo
= {
9344 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 4,
9345 .access
= PL2_R
, .type
= ARM_CP_CONST
,
9346 .resetvalue
= cpu
->pmsav8r_hdregion
9348 static const ARMCPRegInfo crn0_wi_reginfo
= {
9349 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
9350 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
9351 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
9353 #ifdef CONFIG_USER_ONLY
9354 static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo
[] = {
9355 { .name
= "MIDR_EL1",
9356 .exported_bits
= R_MIDR_EL1_REVISION_MASK
|
9357 R_MIDR_EL1_PARTNUM_MASK
|
9358 R_MIDR_EL1_ARCHITECTURE_MASK
|
9359 R_MIDR_EL1_VARIANT_MASK
|
9360 R_MIDR_EL1_IMPLEMENTER_MASK
},
9361 { .name
= "REVIDR_EL1" },
9363 modify_arm_cp_regs(id_v8_midr_cp_reginfo
, id_v8_user_midr_cp_reginfo
);
9365 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
9366 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
9369 * Register the blanket "writes ignored" value first to cover the
9370 * whole space. Then update the specific ID registers to allow write
9371 * access, so that they ignore writes rather than causing them to
9374 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
9375 for (i
= 0; i
< ARRAY_SIZE(id_pre_v8_midr_cp_reginfo
); ++i
) {
9376 id_pre_v8_midr_cp_reginfo
[i
].access
= PL1_RW
;
9378 for (i
= 0; i
< ARRAY_SIZE(id_cp_reginfo
); ++i
) {
9379 id_cp_reginfo
[i
].access
= PL1_RW
;
9381 id_mpuir_reginfo
.access
= PL1_RW
;
9382 id_tlbtr_reginfo
.access
= PL1_RW
;
9384 if (arm_feature(env
, ARM_FEATURE_V8
)) {
9385 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
9386 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
9387 define_one_arm_cp_reg(cpu
, &id_v8_midr_alias_cp_reginfo
);
9390 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
9392 define_arm_cp_regs(cpu
, id_cp_reginfo
);
9393 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
9394 define_one_arm_cp_reg(cpu
, &id_tlbtr_reginfo
);
9395 } else if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
9396 arm_feature(env
, ARM_FEATURE_V8
)) {
9400 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
9401 define_one_arm_cp_reg(cpu
, &id_hmpuir_reginfo
);
9402 define_arm_cp_regs(cpu
, pmsav8r_cp_reginfo
);
9404 /* Register alias is only valid for first 32 indexes */
9405 for (i
= 0; i
< MIN(cpu
->pmsav7_dregion
, 32); ++i
) {
9406 uint8_t crm
= 0b1000 | extract32(i
, 1, 3);
9407 uint8_t opc1
= extract32(i
, 4, 1);
9408 uint8_t opc2
= extract32(i
, 0, 1) << 2;
9410 tmp_string
= g_strdup_printf("PRBAR%u", i
);
9411 ARMCPRegInfo tmp_prbarn_reginfo
= {
9412 .name
= tmp_string
, .type
= ARM_CP_ALIAS
| ARM_CP_NO_RAW
,
9413 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
9414 .access
= PL1_RW
, .resetvalue
= 0,
9415 .accessfn
= access_tvm_trvm
,
9416 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
9418 define_one_arm_cp_reg(cpu
, &tmp_prbarn_reginfo
);
9421 opc2
= extract32(i
, 0, 1) << 2 | 0x1;
9422 tmp_string
= g_strdup_printf("PRLAR%u", i
);
9423 ARMCPRegInfo tmp_prlarn_reginfo
= {
9424 .name
= tmp_string
, .type
= ARM_CP_ALIAS
| ARM_CP_NO_RAW
,
9425 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
9426 .access
= PL1_RW
, .resetvalue
= 0,
9427 .accessfn
= access_tvm_trvm
,
9428 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
9430 define_one_arm_cp_reg(cpu
, &tmp_prlarn_reginfo
);
9434 /* Register alias is only valid for first 32 indexes */
9435 for (i
= 0; i
< MIN(cpu
->pmsav8r_hdregion
, 32); ++i
) {
9436 uint8_t crm
= 0b1000 | extract32(i
, 1, 3);
9437 uint8_t opc1
= 0b100 | extract32(i
, 4, 1);
9438 uint8_t opc2
= extract32(i
, 0, 1) << 2;
9440 tmp_string
= g_strdup_printf("HPRBAR%u", i
);
9441 ARMCPRegInfo tmp_hprbarn_reginfo
= {
9443 .type
= ARM_CP_NO_RAW
,
9444 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
9445 .access
= PL2_RW
, .resetvalue
= 0,
9446 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
9448 define_one_arm_cp_reg(cpu
, &tmp_hprbarn_reginfo
);
9451 opc2
= extract32(i
, 0, 1) << 2 | 0x1;
9452 tmp_string
= g_strdup_printf("HPRLAR%u", i
);
9453 ARMCPRegInfo tmp_hprlarn_reginfo
= {
9455 .type
= ARM_CP_NO_RAW
,
9456 .cp
= 15, .opc1
= opc1
, .crn
= 6, .crm
= crm
, .opc2
= opc2
,
9457 .access
= PL2_RW
, .resetvalue
= 0,
9458 .writefn
= pmsav8r_regn_write
, .readfn
= pmsav8r_regn_read
9460 define_one_arm_cp_reg(cpu
, &tmp_hprlarn_reginfo
);
9463 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
9464 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
9468 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
9469 ARMCPRegInfo mpidr_cp_reginfo
[] = {
9470 { .name
= "MPIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
9471 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
9472 .fgt
= FGT_MPIDR_EL1
,
9473 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_RAW
},
9475 #ifdef CONFIG_USER_ONLY
9476 static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo
[] = {
9477 { .name
= "MPIDR_EL1",
9478 .fixed_bits
= 0x0000000080000000 },
9480 modify_arm_cp_regs(mpidr_cp_reginfo
, mpidr_user_cp_reginfo
);
9482 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
9485 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
9486 ARMCPRegInfo auxcr_reginfo
[] = {
9487 { .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
9488 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
9489 .access
= PL1_RW
, .accessfn
= access_tacr
,
9490 .nv2_redirect_offset
= 0x118,
9491 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->reset_auxcr
},
9492 { .name
= "ACTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
9493 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 1,
9494 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
9496 { .name
= "ACTLR_EL3", .state
= ARM_CP_STATE_AA64
,
9497 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 1,
9498 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
9501 define_arm_cp_regs(cpu
, auxcr_reginfo
);
9502 if (cpu_isar_feature(aa32_ac2
, cpu
)) {
9503 define_arm_cp_regs(cpu
, actlr2_hactlr2_reginfo
);
9507 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
9509 * CBAR is IMPDEF, but common on Arm Cortex-A implementations.
9510 * There are two flavours:
9511 * (1) older 32-bit only cores have a simple 32-bit CBAR
9512 * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a
9513 * 32-bit register visible to AArch32 at a different encoding
9514 * to the "flavour 1" register and with the bits rearranged to
9515 * be able to squash a 64-bit address into the 32-bit view.
9516 * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but
9517 * in future if we support AArch32-only configs of some of the
9518 * AArch64 cores we might need to add a specific feature flag
9519 * to indicate cores with "flavour 2" CBAR.
9521 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
9522 /* 32 bit view is [31:18] 0...0 [43:32]. */
9523 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
9524 | extract64(cpu
->reset_cbar
, 32, 12);
9525 ARMCPRegInfo cbar_reginfo
[] = {
9527 .type
= ARM_CP_CONST
,
9528 .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 1, .opc2
= 0,
9529 .access
= PL1_R
, .resetvalue
= cbar32
},
9530 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
9531 .type
= ARM_CP_CONST
,
9532 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
9533 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
9535 /* We don't implement a r/w 64 bit CBAR currently */
9536 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
9537 define_arm_cp_regs(cpu
, cbar_reginfo
);
9539 ARMCPRegInfo cbar
= {
9541 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
9542 .access
= PL1_R
| PL3_W
, .resetvalue
= cpu
->reset_cbar
,
9543 .fieldoffset
= offsetof(CPUARMState
,
9544 cp15
.c15_config_base_address
)
9546 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
9547 cbar
.access
= PL1_R
;
9548 cbar
.fieldoffset
= 0;
9549 cbar
.type
= ARM_CP_CONST
;
9551 define_one_arm_cp_reg(cpu
, &cbar
);
9555 if (arm_feature(env
, ARM_FEATURE_VBAR
)) {
9556 static const ARMCPRegInfo vbar_cp_reginfo
[] = {
9557 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
9558 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
9559 .access
= PL1_RW
, .writefn
= vbar_write
,
9560 .accessfn
= access_nv1
,
9561 .fgt
= FGT_VBAR_EL1
,
9562 .nv2_redirect_offset
= 0x250 | NV2_REDIR_NV1
,
9563 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.vbar_s
),
9564 offsetof(CPUARMState
, cp15
.vbar_ns
) },
9567 define_arm_cp_regs(cpu
, vbar_cp_reginfo
);
9570 /* Generic registers whose values depend on the implementation */
9572 ARMCPRegInfo sctlr
= {
9573 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
9574 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
9575 .access
= PL1_RW
, .accessfn
= access_tvm_trvm
,
9576 .fgt
= FGT_SCTLR_EL1
,
9577 .nv2_redirect_offset
= 0x110 | NV2_REDIR_NV1
,
9578 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.sctlr_s
),
9579 offsetof(CPUARMState
, cp15
.sctlr_ns
) },
9580 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
9581 .raw_writefn
= raw_write
,
9583 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
9585 * Normally we would always end the TB on an SCTLR write, but Linux
9586 * arch/arm/mach-pxa/sleep.S expects two instructions following
9587 * an MMU enable to execute from cache. Imitate this behaviour.
9589 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
9591 define_one_arm_cp_reg(cpu
, &sctlr
);
9593 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
9594 arm_feature(env
, ARM_FEATURE_V8
)) {
9595 ARMCPRegInfo vsctlr
= {
9596 .name
= "VSCTLR", .state
= ARM_CP_STATE_AA32
,
9597 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
9598 .access
= PL2_RW
, .resetvalue
= 0x0,
9599 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.vsctlr
),
9601 define_one_arm_cp_reg(cpu
, &vsctlr
);
9605 if (cpu_isar_feature(aa64_lor
, cpu
)) {
9606 define_arm_cp_regs(cpu
, lor_reginfo
);
9608 if (cpu_isar_feature(aa64_pan
, cpu
)) {
9609 define_one_arm_cp_reg(cpu
, &pan_reginfo
);
9611 #ifndef CONFIG_USER_ONLY
9612 if (cpu_isar_feature(aa64_ats1e1
, cpu
)) {
9613 define_arm_cp_regs(cpu
, ats1e1_reginfo
);
9615 if (cpu_isar_feature(aa32_ats1e1
, cpu
)) {
9616 define_arm_cp_regs(cpu
, ats1cp_reginfo
);
9619 if (cpu_isar_feature(aa64_uao
, cpu
)) {
9620 define_one_arm_cp_reg(cpu
, &uao_reginfo
);
9623 if (cpu_isar_feature(aa64_dit
, cpu
)) {
9624 define_one_arm_cp_reg(cpu
, &dit_reginfo
);
9626 if (cpu_isar_feature(aa64_ssbs
, cpu
)) {
9627 define_one_arm_cp_reg(cpu
, &ssbs_reginfo
);
9629 if (cpu_isar_feature(any_ras
, cpu
)) {
9630 define_arm_cp_regs(cpu
, minimal_ras_reginfo
);
9633 if (cpu_isar_feature(aa64_vh
, cpu
) ||
9634 cpu_isar_feature(aa64_debugv8p2
, cpu
)) {
9635 define_one_arm_cp_reg(cpu
, &contextidr_el2
);
9637 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
9638 define_arm_cp_regs(cpu
, vhe_reginfo
);
9641 if (cpu_isar_feature(aa64_sve
, cpu
)) {
9642 define_arm_cp_regs(cpu
, zcr_reginfo
);
9645 if (cpu_isar_feature(aa64_hcx
, cpu
)) {
9646 define_one_arm_cp_reg(cpu
, &hcrx_el2_reginfo
);
9649 #ifdef TARGET_AARCH64
9650 if (cpu_isar_feature(aa64_sme
, cpu
)) {
9651 define_arm_cp_regs(cpu
, sme_reginfo
);
9653 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
9654 define_arm_cp_regs(cpu
, pauth_reginfo
);
9656 if (cpu_isar_feature(aa64_rndr
, cpu
)) {
9657 define_arm_cp_regs(cpu
, rndr_reginfo
);
9659 if (cpu_isar_feature(aa64_tlbirange
, cpu
)) {
9660 define_arm_cp_regs(cpu
, tlbirange_reginfo
);
9662 if (cpu_isar_feature(aa64_tlbios
, cpu
)) {
9663 define_arm_cp_regs(cpu
, tlbios_reginfo
);
9665 /* Data Cache clean instructions up to PoP */
9666 if (cpu_isar_feature(aa64_dcpop
, cpu
)) {
9667 define_one_arm_cp_reg(cpu
, dcpop_reg
);
9669 if (cpu_isar_feature(aa64_dcpodp
, cpu
)) {
9670 define_one_arm_cp_reg(cpu
, dcpodp_reg
);
9675 * If full MTE is enabled, add all of the system registers.
9676 * If only "instructions available at EL0" are enabled,
9677 * then define only a RAZ/WI version of PSTATE.TCO.
9679 if (cpu_isar_feature(aa64_mte
, cpu
)) {
9680 ARMCPRegInfo gmid_reginfo
= {
9681 .name
= "GMID_EL1", .state
= ARM_CP_STATE_AA64
,
9682 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 4,
9683 .access
= PL1_R
, .accessfn
= access_aa64_tid5
,
9684 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->gm_blocksize
,
9686 define_one_arm_cp_reg(cpu
, &gmid_reginfo
);
9687 define_arm_cp_regs(cpu
, mte_reginfo
);
9688 define_arm_cp_regs(cpu
, mte_el0_cacheop_reginfo
);
9689 } else if (cpu_isar_feature(aa64_mte_insn_reg
, cpu
)) {
9690 define_arm_cp_regs(cpu
, mte_tco_ro_reginfo
);
9691 define_arm_cp_regs(cpu
, mte_el0_cacheop_reginfo
);
9694 if (cpu_isar_feature(aa64_scxtnum
, cpu
)) {
9695 define_arm_cp_regs(cpu
, scxtnum_reginfo
);
9698 if (cpu_isar_feature(aa64_fgt
, cpu
)) {
9699 define_arm_cp_regs(cpu
, fgt_reginfo
);
9702 if (cpu_isar_feature(aa64_rme
, cpu
)) {
9703 define_arm_cp_regs(cpu
, rme_reginfo
);
9704 if (cpu_isar_feature(aa64_mte
, cpu
)) {
9705 define_arm_cp_regs(cpu
, rme_mte_reginfo
);
9709 if (cpu_isar_feature(aa64_nv2
, cpu
)) {
9710 define_arm_cp_regs(cpu
, nv2_reginfo
);
9714 if (cpu_isar_feature(any_predinv
, cpu
)) {
9715 define_arm_cp_regs(cpu
, predinv_reginfo
);
9718 if (cpu_isar_feature(any_ccidx
, cpu
)) {
9719 define_arm_cp_regs(cpu
, ccsidr2_reginfo
);
9722 #ifndef CONFIG_USER_ONLY
9724 * Register redirections and aliases must be done last,
9725 * after the registers from the other extensions have been defined.
9727 if (arm_feature(env
, ARM_FEATURE_EL2
) && cpu_isar_feature(aa64_vh
, cpu
)) {
9728 define_arm_vh_e2h_redirects_aliases(cpu
);
9734 * Private utility function for define_one_arm_cp_reg_with_opaque():
9735 * add a single reginfo struct to the hash table.
9737 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
9738 void *opaque
, CPState state
,
9739 CPSecureState secstate
,
9740 int crm
, int opc1
, int opc2
,
9743 CPUARMState
*env
= &cpu
->env
;
9746 bool is64
= r
->type
& ARM_CP_64BIT
;
9747 bool ns
= secstate
& ARM_CP_SECSTATE_NS
;
9753 case ARM_CP_STATE_AA32
:
9754 /* We assume it is a cp15 register if the .cp field is left unset. */
9755 if (cp
== 0 && r
->state
== ARM_CP_STATE_BOTH
) {
9758 key
= ENCODE_CP_REG(cp
, is64
, ns
, r
->crn
, crm
, opc1
, opc2
);
9760 case ARM_CP_STATE_AA64
:
9762 * To allow abbreviation of ARMCPRegInfo definitions, we treat
9763 * cp == 0 as equivalent to the value for "standard guest-visible
9764 * sysreg". STATE_BOTH definitions are also always "standard sysreg"
9765 * in their AArch64 view (the .cp value may be non-zero for the
9766 * benefit of the AArch32 view).
9768 if (cp
== 0 || r
->state
== ARM_CP_STATE_BOTH
) {
9769 cp
= CP_REG_ARM64_SYSREG_CP
;
9771 key
= ENCODE_AA64_CP_REG(cp
, r
->crn
, crm
, r
->opc0
, opc1
, opc2
);
9774 g_assert_not_reached();
9777 /* Overriding of an existing definition must be explicitly requested. */
9778 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
9779 const ARMCPRegInfo
*oldreg
= get_arm_cp_reginfo(cpu
->cp_regs
, key
);
9781 assert(oldreg
->type
& ARM_CP_OVERRIDE
);
9786 * Eliminate registers that are not present because the EL is missing.
9787 * Doing this here makes it easier to put all registers for a given
9788 * feature into the same ARMCPRegInfo array and define them all at once.
9791 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
9793 * An EL2 register without EL2 but with EL3 is (usually) RES0.
9794 * See rule RJFFP in section D1.1.3 of DDI0487H.a.
9796 int min_el
= ctz32(r
->access
) / 2;
9797 if (min_el
== 2 && !arm_feature(env
, ARM_FEATURE_EL2
)) {
9798 if (r
->type
& ARM_CP_EL3_NO_EL2_UNDEF
) {
9801 make_const
= !(r
->type
& ARM_CP_EL3_NO_EL2_KEEP
);
9804 CPAccessRights max_el
= (arm_feature(env
, ARM_FEATURE_EL2
)
9806 if ((r
->access
& max_el
) == 0) {
9811 /* Combine cpreg and name into one allocation. */
9812 name_len
= strlen(name
) + 1;
9813 r2
= g_malloc(sizeof(*r2
) + name_len
);
9815 r2
->name
= memcpy(r2
+ 1, name
, name_len
);
9818 * Update fields to match the instantiation, overwiting wildcards
9819 * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH.
9826 r2
->secure
= secstate
;
9828 r2
->opaque
= opaque
;
9832 /* This should not have been a very special register to begin. */
9833 int old_special
= r2
->type
& ARM_CP_SPECIAL_MASK
;
9834 assert(old_special
== 0 || old_special
== ARM_CP_NOP
);
9836 * Set the special function to CONST, retaining the other flags.
9837 * This is important for e.g. ARM_CP_SVE so that we still
9838 * take the SVE trap if CPTR_EL3.EZ == 0.
9840 r2
->type
= (r2
->type
& ~ARM_CP_SPECIAL_MASK
) | ARM_CP_CONST
;
9842 * Usually, these registers become RES0, but there are a few
9843 * special cases like VPIDR_EL2 which have a constant non-zero
9844 * value with writes ignored.
9846 if (!(r
->type
& ARM_CP_EL3_NO_EL2_C_NZ
)) {
9850 * ARM_CP_CONST has precedence, so removing the callbacks and
9851 * offsets are not strictly necessary, but it is potentially
9852 * less confusing to debug later.
9856 r2
->raw_readfn
= NULL
;
9857 r2
->raw_writefn
= NULL
;
9859 r2
->fieldoffset
= 0;
9860 r2
->bank_fieldoffsets
[0] = 0;
9861 r2
->bank_fieldoffsets
[1] = 0;
9863 bool isbanked
= r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1];
9867 * Register is banked (using both entries in array).
9868 * Overwriting fieldoffset as the array is only used to define
9869 * banked registers but later only fieldoffset is used.
9871 r2
->fieldoffset
= r
->bank_fieldoffsets
[ns
];
9873 if (state
== ARM_CP_STATE_AA32
) {
9876 * If the register is banked then we don't need to migrate or
9877 * reset the 32-bit instance in certain cases:
9879 * 1) If the register has both 32-bit and 64-bit instances
9880 * then we can count on the 64-bit instance taking care
9881 * of the non-secure bank.
9882 * 2) If ARMv8 is enabled then we can count on a 64-bit
9883 * version taking care of the secure bank. This requires
9884 * that separate 32 and 64-bit definitions are provided.
9886 if ((r
->state
== ARM_CP_STATE_BOTH
&& ns
) ||
9887 (arm_feature(env
, ARM_FEATURE_V8
) && !ns
)) {
9888 r2
->type
|= ARM_CP_ALIAS
;
9890 } else if ((secstate
!= r
->secure
) && !ns
) {
9892 * The register is not banked so we only want to allow
9893 * migration of the non-secure instance.
9895 r2
->type
|= ARM_CP_ALIAS
;
9898 if (HOST_BIG_ENDIAN
&&
9899 r
->state
== ARM_CP_STATE_BOTH
&& r2
->fieldoffset
) {
9900 r2
->fieldoffset
+= sizeof(uint32_t);
9906 * By convention, for wildcarded registers only the first
9907 * entry is used for migration; the others are marked as
9908 * ALIAS so we don't try to transfer the register
9909 * multiple times. Special registers (ie NOP/WFI) are
9910 * never migratable and not even raw-accessible.
9912 if (r2
->type
& ARM_CP_SPECIAL_MASK
) {
9913 r2
->type
|= ARM_CP_NO_RAW
;
9915 if (((r
->crm
== CP_ANY
) && crm
!= 0) ||
9916 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
9917 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
9918 r2
->type
|= ARM_CP_ALIAS
| ARM_CP_NO_GDB
;
9922 * Check that raw accesses are either forbidden or handled. Note that
9923 * we can't assert this earlier because the setup of fieldoffset for
9924 * banked registers has to be done first.
9926 if (!(r2
->type
& ARM_CP_NO_RAW
)) {
9927 assert(!raw_accessors_invalid(r2
));
9930 g_hash_table_insert(cpu
->cp_regs
, (gpointer
)(uintptr_t)key
, r2
);
9934 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
9935 const ARMCPRegInfo
*r
, void *opaque
)
9938 * Define implementations of coprocessor registers.
9939 * We store these in a hashtable because typically
9940 * there are less than 150 registers in a space which
9941 * is 16*16*16*8*8 = 262144 in size.
9942 * Wildcarding is supported for the crm, opc1 and opc2 fields.
9943 * If a register is defined twice then the second definition is
9944 * used, so this can be used to define some generic registers and
9945 * then override them with implementation specific variations.
9946 * At least one of the original and the second definition should
9947 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
9948 * against accidental use.
9950 * The state field defines whether the register is to be
9951 * visible in the AArch32 or AArch64 execution state. If the
9952 * state is set to ARM_CP_STATE_BOTH then we synthesise a
9953 * reginfo structure for the AArch32 view, which sees the lower
9954 * 32 bits of the 64 bit register.
9956 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
9957 * be wildcarded. AArch64 registers are always considered to be 64
9958 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
9959 * the register, if any.
9961 int crm
, opc1
, opc2
;
9962 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
9963 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
9964 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
9965 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
9966 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
9967 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
9970 /* 64 bit registers have only CRm and Opc1 fields */
9971 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
9972 /* op0 only exists in the AArch64 encodings */
9973 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
9974 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
9975 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
9977 * This API is only for Arm's system coprocessors (14 and 15) or
9978 * (M-profile or v7A-and-earlier only) for implementation defined
9979 * coprocessors in the range 0..7. Our decode assumes this, since
9980 * 8..13 can be used for other insns including VFP and Neon. See
9981 * valid_cp() in translate.c. Assert here that we haven't tried
9982 * to use an invalid coprocessor number.
9985 case ARM_CP_STATE_BOTH
:
9986 /* 0 has a special meaning, but otherwise the same rules as AA32. */
9991 case ARM_CP_STATE_AA32
:
9992 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) &&
9993 !arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
9994 assert(r
->cp
>= 14 && r
->cp
<= 15);
9996 assert(r
->cp
< 8 || (r
->cp
>= 14 && r
->cp
<= 15));
9999 case ARM_CP_STATE_AA64
:
10000 assert(r
->cp
== 0 || r
->cp
== CP_REG_ARM64_SYSREG_CP
);
10003 g_assert_not_reached();
10006 * The AArch64 pseudocode CheckSystemAccess() specifies that op1
10007 * encodes a minimum access level for the register. We roll this
10008 * runtime check into our general permission check code, so check
10009 * here that the reginfo's specified permissions are strict enough
10010 * to encompass the generic architectural permission check.
10012 if (r
->state
!= ARM_CP_STATE_AA32
) {
10013 CPAccessRights mask
;
10016 /* min_EL EL1, but some accessible to EL0 via kernel ABI */
10017 mask
= PL0U_R
| PL1_RW
;
10037 /* min_EL EL1, secure mode only (we don't check the latter) */
10041 /* broken reginfo with out-of-range opc1 */
10042 g_assert_not_reached();
10044 /* assert our permissions are not too lax (stricter is fine) */
10045 assert((r
->access
& ~mask
) == 0);
10049 * Check that the register definition has enough info to handle
10050 * reads and writes if they are permitted.
10052 if (!(r
->type
& (ARM_CP_SPECIAL_MASK
| ARM_CP_CONST
))) {
10053 if (r
->access
& PL3_R
) {
10054 assert((r
->fieldoffset
||
10055 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
10058 if (r
->access
& PL3_W
) {
10059 assert((r
->fieldoffset
||
10060 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
10065 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
10066 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
10067 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
10068 for (state
= ARM_CP_STATE_AA32
;
10069 state
<= ARM_CP_STATE_AA64
; state
++) {
10070 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
10073 if (state
== ARM_CP_STATE_AA32
) {
10075 * Under AArch32 CP registers can be common
10076 * (same for secure and non-secure world) or banked.
10080 switch (r
->secure
) {
10081 case ARM_CP_SECSTATE_S
:
10082 case ARM_CP_SECSTATE_NS
:
10083 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
10084 r
->secure
, crm
, opc1
, opc2
,
10087 case ARM_CP_SECSTATE_BOTH
:
10088 name
= g_strdup_printf("%s_S", r
->name
);
10089 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
10091 crm
, opc1
, opc2
, name
);
10093 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
10094 ARM_CP_SECSTATE_NS
,
10095 crm
, opc1
, opc2
, r
->name
);
10098 g_assert_not_reached();
10102 * AArch64 registers get mapped to non-secure instance
10105 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
10106 ARM_CP_SECSTATE_NS
,
10107 crm
, opc1
, opc2
, r
->name
);
10115 /* Define a whole list of registers */
10116 void define_arm_cp_regs_with_opaque_len(ARMCPU
*cpu
, const ARMCPRegInfo
*regs
,
10117 void *opaque
, size_t len
)
10120 for (i
= 0; i
< len
; ++i
) {
10121 define_one_arm_cp_reg_with_opaque(cpu
, regs
+ i
, opaque
);
10126 * Modify ARMCPRegInfo for access from userspace.
10128 * This is a data driven modification directed by
10129 * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as
10130 * user-space cannot alter any values and dynamic values pertaining to
10131 * execution state are hidden from user space view anyway.
10133 void modify_arm_cp_regs_with_len(ARMCPRegInfo
*regs
, size_t regs_len
,
10134 const ARMCPRegUserSpaceInfo
*mods
,
10137 for (size_t mi
= 0; mi
< mods_len
; ++mi
) {
10138 const ARMCPRegUserSpaceInfo
*m
= mods
+ mi
;
10139 GPatternSpec
*pat
= NULL
;
10142 pat
= g_pattern_spec_new(m
->name
);
10144 for (size_t ri
= 0; ri
< regs_len
; ++ri
) {
10145 ARMCPRegInfo
*r
= regs
+ ri
;
10147 if (pat
&& g_pattern_match_string(pat
, r
->name
)) {
10148 r
->type
= ARM_CP_CONST
;
10149 r
->access
= PL0U_R
;
10152 } else if (strcmp(r
->name
, m
->name
) == 0) {
10153 r
->type
= ARM_CP_CONST
;
10154 r
->access
= PL0U_R
;
10155 r
->resetvalue
&= m
->exported_bits
;
10156 r
->resetvalue
|= m
->fixed_bits
;
10161 g_pattern_spec_free(pat
);
10166 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
10168 return g_hash_table_lookup(cpregs
, (gpointer
)(uintptr_t)encoded_cp
);
10171 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
10174 /* Helper coprocessor write function for write-ignore registers */
10177 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
10179 /* Helper coprocessor write function for read-as-zero registers */
10183 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
10185 /* Helper coprocessor reset function for do-nothing-on-reset registers */
10188 static int bad_mode_switch(CPUARMState
*env
, int mode
, CPSRWriteType write_type
)
10191 * Return true if it is not valid for us to switch to
10192 * this CPU mode (ie all the UNPREDICTABLE cases in
10193 * the ARM ARM CPSRWriteByInstr pseudocode).
10196 /* Changes to or from Hyp via MSR and CPS are illegal. */
10197 if (write_type
== CPSRWriteByInstr
&&
10198 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_HYP
||
10199 mode
== ARM_CPU_MODE_HYP
)) {
10204 case ARM_CPU_MODE_USR
:
10206 case ARM_CPU_MODE_SYS
:
10207 case ARM_CPU_MODE_SVC
:
10208 case ARM_CPU_MODE_ABT
:
10209 case ARM_CPU_MODE_UND
:
10210 case ARM_CPU_MODE_IRQ
:
10211 case ARM_CPU_MODE_FIQ
:
10213 * Note that we don't implement the IMPDEF NSACR.RFR which in v7
10214 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
10217 * If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
10218 * and CPS are treated as illegal mode changes.
10220 if (write_type
== CPSRWriteByInstr
&&
10221 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
&&
10222 (arm_hcr_el2_eff(env
) & HCR_TGE
)) {
10226 case ARM_CPU_MODE_HYP
:
10227 return !arm_is_el2_enabled(env
) || arm_current_el(env
) < 2;
10228 case ARM_CPU_MODE_MON
:
10229 return arm_current_el(env
) < 3;
10235 uint32_t cpsr_read(CPUARMState
*env
)
10238 ZF
= (env
->ZF
== 0);
10239 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
10240 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
10241 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
10242 | ((env
->condexec_bits
& 0xfc) << 8)
10243 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
10246 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
,
10247 CPSRWriteType write_type
)
10249 uint32_t changed_daif
;
10250 bool rebuild_hflags
= (write_type
!= CPSRWriteRaw
) &&
10251 (mask
& (CPSR_M
| CPSR_E
| CPSR_IL
));
10253 if (mask
& CPSR_NZCV
) {
10254 env
->ZF
= (~val
) & CPSR_Z
;
10256 env
->CF
= (val
>> 29) & 1;
10257 env
->VF
= (val
<< 3) & 0x80000000;
10259 if (mask
& CPSR_Q
) {
10260 env
->QF
= ((val
& CPSR_Q
) != 0);
10262 if (mask
& CPSR_T
) {
10263 env
->thumb
= ((val
& CPSR_T
) != 0);
10265 if (mask
& CPSR_IT_0_1
) {
10266 env
->condexec_bits
&= ~3;
10267 env
->condexec_bits
|= (val
>> 25) & 3;
10269 if (mask
& CPSR_IT_2_7
) {
10270 env
->condexec_bits
&= 3;
10271 env
->condexec_bits
|= (val
>> 8) & 0xfc;
10273 if (mask
& CPSR_GE
) {
10274 env
->GE
= (val
>> 16) & 0xf;
10278 * In a V7 implementation that includes the security extensions but does
10279 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
10280 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
10281 * bits respectively.
10283 * In a V8 implementation, it is permitted for privileged software to
10284 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
10286 if (write_type
!= CPSRWriteRaw
&& !arm_feature(env
, ARM_FEATURE_V8
) &&
10287 arm_feature(env
, ARM_FEATURE_EL3
) &&
10288 !arm_feature(env
, ARM_FEATURE_EL2
) &&
10289 !arm_is_secure(env
)) {
10291 changed_daif
= (env
->daif
^ val
) & mask
;
10293 if (changed_daif
& CPSR_A
) {
10295 * Check to see if we are allowed to change the masking of async
10296 * abort exceptions from a non-secure state.
10298 if (!(env
->cp15
.scr_el3
& SCR_AW
)) {
10299 qemu_log_mask(LOG_GUEST_ERROR
,
10300 "Ignoring attempt to switch CPSR_A flag from "
10301 "non-secure world with SCR.AW bit clear\n");
10306 if (changed_daif
& CPSR_F
) {
10308 * Check to see if we are allowed to change the masking of FIQ
10309 * exceptions from a non-secure state.
10311 if (!(env
->cp15
.scr_el3
& SCR_FW
)) {
10312 qemu_log_mask(LOG_GUEST_ERROR
,
10313 "Ignoring attempt to switch CPSR_F flag from "
10314 "non-secure world with SCR.FW bit clear\n");
10319 * Check whether non-maskable FIQ (NMFI) support is enabled.
10320 * If this bit is set software is not allowed to mask
10321 * FIQs, but is allowed to set CPSR_F to 0.
10323 if ((A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_NMFI
) &&
10325 qemu_log_mask(LOG_GUEST_ERROR
,
10326 "Ignoring attempt to enable CPSR_F flag "
10327 "(non-maskable FIQ [NMFI] support enabled)\n");
10333 env
->daif
&= ~(CPSR_AIF
& mask
);
10334 env
->daif
|= val
& CPSR_AIF
& mask
;
10336 if (write_type
!= CPSRWriteRaw
&&
10337 ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
)) {
10338 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
) {
10340 * Note that we can only get here in USR mode if this is a
10341 * gdb stub write; for this case we follow the architectural
10342 * behaviour for guest writes in USR mode of ignoring an attempt
10343 * to switch mode. (Those are caught by translate.c for writes
10344 * triggered by guest instructions.)
10347 } else if (bad_mode_switch(env
, val
& CPSR_M
, write_type
)) {
10349 * Attempt to switch to an invalid mode: this is UNPREDICTABLE in
10350 * v7, and has defined behaviour in v8:
10351 * + leave CPSR.M untouched
10352 * + allow changes to the other CPSR fields
10354 * For user changes via the GDB stub, we don't set PSTATE.IL,
10355 * as this would be unnecessarily harsh for a user error.
10358 if (write_type
!= CPSRWriteByGDBStub
&&
10359 arm_feature(env
, ARM_FEATURE_V8
)) {
10363 qemu_log_mask(LOG_GUEST_ERROR
,
10364 "Illegal AArch32 mode switch attempt from %s to %s\n",
10365 aarch32_mode_name(env
->uncached_cpsr
),
10366 aarch32_mode_name(val
));
10368 qemu_log_mask(CPU_LOG_INT
, "%s %s to %s PC 0x%" PRIx32
"\n",
10369 write_type
== CPSRWriteExceptionReturn
?
10370 "Exception return from AArch32" :
10371 "AArch32 mode switch from",
10372 aarch32_mode_name(env
->uncached_cpsr
),
10373 aarch32_mode_name(val
), env
->regs
[15]);
10374 switch_mode(env
, val
& CPSR_M
);
10377 mask
&= ~CACHED_CPSR_BITS
;
10378 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
10379 if (tcg_enabled() && rebuild_hflags
) {
10380 arm_rebuild_hflags(env
);
10384 #ifdef CONFIG_USER_ONLY
10386 static void switch_mode(CPUARMState
*env
, int mode
)
10388 ARMCPU
*cpu
= env_archcpu(env
);
10390 if (mode
!= ARM_CPU_MODE_USR
) {
10391 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
10395 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
10396 uint32_t cur_el
, bool secure
)
10401 void aarch64_sync_64_to_32(CPUARMState
*env
)
10403 g_assert_not_reached();
10408 static void switch_mode(CPUARMState
*env
, int mode
)
10413 old_mode
= env
->uncached_cpsr
& CPSR_M
;
10414 if (mode
== old_mode
) {
10418 if (old_mode
== ARM_CPU_MODE_FIQ
) {
10419 memcpy(env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
10420 memcpy(env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
10421 } else if (mode
== ARM_CPU_MODE_FIQ
) {
10422 memcpy(env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
10423 memcpy(env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
10426 i
= bank_number(old_mode
);
10427 env
->banked_r13
[i
] = env
->regs
[13];
10428 env
->banked_spsr
[i
] = env
->spsr
;
10430 i
= bank_number(mode
);
10431 env
->regs
[13] = env
->banked_r13
[i
];
10432 env
->spsr
= env
->banked_spsr
[i
];
10434 env
->banked_r14
[r14_bank_number(old_mode
)] = env
->regs
[14];
10435 env
->regs
[14] = env
->banked_r14
[r14_bank_number(mode
)];
10439 * Physical Interrupt Target EL Lookup Table
10441 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
10443 * The below multi-dimensional table is used for looking up the target
10444 * exception level given numerous condition criteria. Specifically, the
10445 * target EL is based on SCR and HCR routing controls as well as the
10446 * currently executing EL and secure state.
10449 * target_el_table[2][2][2][2][2][4]
10450 * | | | | | +--- Current EL
10451 * | | | | +------ Non-secure(0)/Secure(1)
10452 * | | | +--------- HCR mask override
10453 * | | +------------ SCR exec state control
10454 * | +--------------- SCR mask override
10455 * +------------------ 32-bit(0)/64-bit(1) EL3
10457 * The table values are as such:
10459 * -1 = Cannot occur
10461 * The ARM ARM target EL table includes entries indicating that an "exception
10462 * is not taken". The two cases where this is applicable are:
10463 * 1) An exception is taken from EL3 but the SCR does not have the exception
10465 * 2) An exception is taken from EL2 but the HCR does not have the exception
10467 * In these two cases, the below table contain a target of EL1. This value is
10468 * returned as it is expected that the consumer of the table data will check
10469 * for "target EL >= current EL" to ensure the exception is not taken.
10473 * BIT IRQ IMO Non-secure Secure
10474 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
10476 static const int8_t target_el_table
[2][2][2][2][2][4] = {
10477 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
10478 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
10479 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
10480 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
10481 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
10482 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
10483 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
10484 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
10485 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
10486 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 2, 2, -1, 1 },},},
10487 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, 1, 1 },},
10488 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 2, 2, 2, 1 },},},},
10489 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
10490 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
10491 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},
10492 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, 3, 3 },},},},},
10496 * Determine the target EL for physical exceptions
10498 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
10499 uint32_t cur_el
, bool secure
)
10501 CPUARMState
*env
= cpu_env(cs
);
10506 /* Is the highest EL AArch64? */
10507 bool is64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
10510 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
10511 rw
= ((env
->cp15
.scr_el3
& SCR_RW
) == SCR_RW
);
10514 * Either EL2 is the highest EL (and so the EL2 register width
10515 * is given by is64); or there is no EL2 or EL3, in which case
10516 * the value of 'rw' does not affect the table lookup anyway.
10521 hcr_el2
= arm_hcr_el2_eff(env
);
10522 switch (excp_idx
) {
10524 scr
= ((env
->cp15
.scr_el3
& SCR_IRQ
) == SCR_IRQ
);
10525 hcr
= hcr_el2
& HCR_IMO
;
10528 scr
= ((env
->cp15
.scr_el3
& SCR_FIQ
) == SCR_FIQ
);
10529 hcr
= hcr_el2
& HCR_FMO
;
10532 scr
= ((env
->cp15
.scr_el3
& SCR_EA
) == SCR_EA
);
10533 hcr
= hcr_el2
& HCR_AMO
;
10538 * For these purposes, TGE and AMO/IMO/FMO both force the
10539 * interrupt to EL2. Fold TGE into the bit extracted above.
10541 hcr
|= (hcr_el2
& HCR_TGE
) != 0;
10543 /* Perform a table-lookup for the target EL given the current state */
10544 target_el
= target_el_table
[is64
][scr
][rw
][hcr
][secure
][cur_el
];
10546 assert(target_el
> 0);
10551 void arm_log_exception(CPUState
*cs
)
10553 int idx
= cs
->exception_index
;
10555 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
10556 const char *exc
= NULL
;
10557 static const char * const excnames
[] = {
10558 [EXCP_UDEF
] = "Undefined Instruction",
10559 [EXCP_SWI
] = "SVC",
10560 [EXCP_PREFETCH_ABORT
] = "Prefetch Abort",
10561 [EXCP_DATA_ABORT
] = "Data Abort",
10562 [EXCP_IRQ
] = "IRQ",
10563 [EXCP_FIQ
] = "FIQ",
10564 [EXCP_BKPT
] = "Breakpoint",
10565 [EXCP_EXCEPTION_EXIT
] = "QEMU v7M exception exit",
10566 [EXCP_KERNEL_TRAP
] = "QEMU intercept of kernel commpage",
10567 [EXCP_HVC
] = "Hypervisor Call",
10568 [EXCP_HYP_TRAP
] = "Hypervisor Trap",
10569 [EXCP_SMC
] = "Secure Monitor Call",
10570 [EXCP_VIRQ
] = "Virtual IRQ",
10571 [EXCP_VFIQ
] = "Virtual FIQ",
10572 [EXCP_SEMIHOST
] = "Semihosting call",
10573 [EXCP_NOCP
] = "v7M NOCP UsageFault",
10574 [EXCP_INVSTATE
] = "v7M INVSTATE UsageFault",
10575 [EXCP_STKOF
] = "v8M STKOF UsageFault",
10576 [EXCP_LAZYFP
] = "v7M exception during lazy FP stacking",
10577 [EXCP_LSERR
] = "v8M LSERR UsageFault",
10578 [EXCP_UNALIGNED
] = "v7M UNALIGNED UsageFault",
10579 [EXCP_DIVBYZERO
] = "v7M DIVBYZERO UsageFault",
10580 [EXCP_VSERR
] = "Virtual SERR",
10581 [EXCP_GPC
] = "Granule Protection Check",
10584 if (idx
>= 0 && idx
< ARRAY_SIZE(excnames
)) {
10585 exc
= excnames
[idx
];
10590 qemu_log_mask(CPU_LOG_INT
, "Taking exception %d [%s] on CPU %d\n",
10591 idx
, exc
, cs
->cpu_index
);
10596 * Function used to synchronize QEMU's AArch64 register set with AArch32
10597 * register set. This is necessary when switching between AArch32 and AArch64
10600 void aarch64_sync_32_to_64(CPUARMState
*env
)
10603 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
10605 /* We can blanket copy R[0:7] to X[0:7] */
10606 for (i
= 0; i
< 8; i
++) {
10607 env
->xregs
[i
] = env
->regs
[i
];
10611 * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
10612 * Otherwise, they come from the banked user regs.
10614 if (mode
== ARM_CPU_MODE_FIQ
) {
10615 for (i
= 8; i
< 13; i
++) {
10616 env
->xregs
[i
] = env
->usr_regs
[i
- 8];
10619 for (i
= 8; i
< 13; i
++) {
10620 env
->xregs
[i
] = env
->regs
[i
];
10625 * Registers x13-x23 are the various mode SP and FP registers. Registers
10626 * r13 and r14 are only copied if we are in that mode, otherwise we copy
10627 * from the mode banked register.
10629 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
10630 env
->xregs
[13] = env
->regs
[13];
10631 env
->xregs
[14] = env
->regs
[14];
10633 env
->xregs
[13] = env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)];
10634 /* HYP is an exception in that it is copied from r14 */
10635 if (mode
== ARM_CPU_MODE_HYP
) {
10636 env
->xregs
[14] = env
->regs
[14];
10638 env
->xregs
[14] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)];
10642 if (mode
== ARM_CPU_MODE_HYP
) {
10643 env
->xregs
[15] = env
->regs
[13];
10645 env
->xregs
[15] = env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)];
10648 if (mode
== ARM_CPU_MODE_IRQ
) {
10649 env
->xregs
[16] = env
->regs
[14];
10650 env
->xregs
[17] = env
->regs
[13];
10652 env
->xregs
[16] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)];
10653 env
->xregs
[17] = env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)];
10656 if (mode
== ARM_CPU_MODE_SVC
) {
10657 env
->xregs
[18] = env
->regs
[14];
10658 env
->xregs
[19] = env
->regs
[13];
10660 env
->xregs
[18] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)];
10661 env
->xregs
[19] = env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)];
10664 if (mode
== ARM_CPU_MODE_ABT
) {
10665 env
->xregs
[20] = env
->regs
[14];
10666 env
->xregs
[21] = env
->regs
[13];
10668 env
->xregs
[20] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)];
10669 env
->xregs
[21] = env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)];
10672 if (mode
== ARM_CPU_MODE_UND
) {
10673 env
->xregs
[22] = env
->regs
[14];
10674 env
->xregs
[23] = env
->regs
[13];
10676 env
->xregs
[22] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)];
10677 env
->xregs
[23] = env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)];
10681 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
10682 * mode, then we can copy from r8-r14. Otherwise, we copy from the
10683 * FIQ bank for r8-r14.
10685 if (mode
== ARM_CPU_MODE_FIQ
) {
10686 for (i
= 24; i
< 31; i
++) {
10687 env
->xregs
[i
] = env
->regs
[i
- 16]; /* X[24:30] <- R[8:14] */
10690 for (i
= 24; i
< 29; i
++) {
10691 env
->xregs
[i
] = env
->fiq_regs
[i
- 24];
10693 env
->xregs
[29] = env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)];
10694 env
->xregs
[30] = env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)];
10697 env
->pc
= env
->regs
[15];
10701 * Function used to synchronize QEMU's AArch32 register set with AArch64
10702 * register set. This is necessary when switching between AArch32 and AArch64
10705 void aarch64_sync_64_to_32(CPUARMState
*env
)
10708 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
10710 /* We can blanket copy X[0:7] to R[0:7] */
10711 for (i
= 0; i
< 8; i
++) {
10712 env
->regs
[i
] = env
->xregs
[i
];
10716 * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
10717 * Otherwise, we copy x8-x12 into the banked user regs.
10719 if (mode
== ARM_CPU_MODE_FIQ
) {
10720 for (i
= 8; i
< 13; i
++) {
10721 env
->usr_regs
[i
- 8] = env
->xregs
[i
];
10724 for (i
= 8; i
< 13; i
++) {
10725 env
->regs
[i
] = env
->xregs
[i
];
10730 * Registers r13 & r14 depend on the current mode.
10731 * If we are in a given mode, we copy the corresponding x registers to r13
10732 * and r14. Otherwise, we copy the x register to the banked r13 and r14
10735 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
10736 env
->regs
[13] = env
->xregs
[13];
10737 env
->regs
[14] = env
->xregs
[14];
10739 env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[13];
10742 * HYP is an exception in that it does not have its own banked r14 but
10743 * shares the USR r14
10745 if (mode
== ARM_CPU_MODE_HYP
) {
10746 env
->regs
[14] = env
->xregs
[14];
10748 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[14];
10752 if (mode
== ARM_CPU_MODE_HYP
) {
10753 env
->regs
[13] = env
->xregs
[15];
10755 env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)] = env
->xregs
[15];
10758 if (mode
== ARM_CPU_MODE_IRQ
) {
10759 env
->regs
[14] = env
->xregs
[16];
10760 env
->regs
[13] = env
->xregs
[17];
10762 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[16];
10763 env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[17];
10766 if (mode
== ARM_CPU_MODE_SVC
) {
10767 env
->regs
[14] = env
->xregs
[18];
10768 env
->regs
[13] = env
->xregs
[19];
10770 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[18];
10771 env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[19];
10774 if (mode
== ARM_CPU_MODE_ABT
) {
10775 env
->regs
[14] = env
->xregs
[20];
10776 env
->regs
[13] = env
->xregs
[21];
10778 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[20];
10779 env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[21];
10782 if (mode
== ARM_CPU_MODE_UND
) {
10783 env
->regs
[14] = env
->xregs
[22];
10784 env
->regs
[13] = env
->xregs
[23];
10786 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[22];
10787 env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[23];
10791 * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
10792 * mode, then we can copy to r8-r14. Otherwise, we copy to the
10793 * FIQ bank for r8-r14.
10795 if (mode
== ARM_CPU_MODE_FIQ
) {
10796 for (i
= 24; i
< 31; i
++) {
10797 env
->regs
[i
- 16] = env
->xregs
[i
]; /* X[24:30] -> R[8:14] */
10800 for (i
= 24; i
< 29; i
++) {
10801 env
->fiq_regs
[i
- 24] = env
->xregs
[i
];
10803 env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[29];
10804 env
->banked_r14
[r14_bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[30];
10807 env
->regs
[15] = env
->pc
;
10810 static void take_aarch32_exception(CPUARMState
*env
, int new_mode
,
10811 uint32_t mask
, uint32_t offset
,
10816 /* Change the CPU state so as to actually take the exception. */
10817 switch_mode(env
, new_mode
);
10820 * For exceptions taken to AArch32 we must clear the SS bit in both
10821 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
10823 env
->pstate
&= ~PSTATE_SS
;
10824 env
->spsr
= cpsr_read(env
);
10825 /* Clear IT bits. */
10826 env
->condexec_bits
= 0;
10827 /* Switch to the new mode, and to the correct instruction set. */
10828 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
10830 /* This must be after mode switching. */
10831 new_el
= arm_current_el(env
);
10833 /* Set new mode endianness */
10834 env
->uncached_cpsr
&= ~CPSR_E
;
10835 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_EE
) {
10836 env
->uncached_cpsr
|= CPSR_E
;
10838 /* J and IL must always be cleared for exception entry */
10839 env
->uncached_cpsr
&= ~(CPSR_IL
| CPSR_J
);
10842 if (cpu_isar_feature(aa32_ssbs
, env_archcpu(env
))) {
10843 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_DSSBS_32
) {
10844 env
->uncached_cpsr
|= CPSR_SSBS
;
10846 env
->uncached_cpsr
&= ~CPSR_SSBS
;
10850 if (new_mode
== ARM_CPU_MODE_HYP
) {
10851 env
->thumb
= (env
->cp15
.sctlr_el
[2] & SCTLR_TE
) != 0;
10852 env
->elr_el
[2] = env
->regs
[15];
10854 /* CPSR.PAN is normally preserved preserved unless... */
10855 if (cpu_isar_feature(aa32_pan
, env_archcpu(env
))) {
10858 if (!arm_is_secure_below_el3(env
)) {
10859 /* ... the target is EL3, from non-secure state. */
10860 env
->uncached_cpsr
&= ~CPSR_PAN
;
10863 /* ... the target is EL3, from secure state ... */
10866 /* ... the target is EL1 and SCTLR.SPAN is 0. */
10867 if (!(env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
)) {
10868 env
->uncached_cpsr
|= CPSR_PAN
;
10874 * this is a lie, as there was no c1_sys on V4T/V5, but who cares
10875 * and we should just guard the thumb mode on V4
10877 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
10879 (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_TE
) != 0;
10881 env
->regs
[14] = env
->regs
[15] + offset
;
10883 env
->regs
[15] = newpc
;
10885 if (tcg_enabled()) {
10886 arm_rebuild_hflags(env
);
10890 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState
*cs
)
10893 * Handle exception entry to Hyp mode; this is sufficiently
10894 * different to entry to other AArch32 modes that we handle it
10897 * The vector table entry used is always the 0x14 Hyp mode entry point,
10898 * unless this is an UNDEF/SVC/HVC/abort taken from Hyp to Hyp.
10899 * The offset applied to the preferred return address is always zero
10900 * (see DDI0487C.a section G1.12.3).
10901 * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values.
10903 uint32_t addr
, mask
;
10904 ARMCPU
*cpu
= ARM_CPU(cs
);
10905 CPUARMState
*env
= &cpu
->env
;
10907 switch (cs
->exception_index
) {
10915 /* Fall through to prefetch abort. */
10916 case EXCP_PREFETCH_ABORT
:
10917 env
->cp15
.ifar_s
= env
->exception
.vaddress
;
10918 qemu_log_mask(CPU_LOG_INT
, "...with HIFAR 0x%x\n",
10919 (uint32_t)env
->exception
.vaddress
);
10922 case EXCP_DATA_ABORT
:
10923 env
->cp15
.dfar_s
= env
->exception
.vaddress
;
10924 qemu_log_mask(CPU_LOG_INT
, "...with HDFAR 0x%x\n",
10925 (uint32_t)env
->exception
.vaddress
);
10937 case EXCP_HYP_TRAP
:
10941 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
10944 if (cs
->exception_index
!= EXCP_IRQ
&& cs
->exception_index
!= EXCP_FIQ
) {
10945 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
10947 * QEMU syndrome values are v8-style. v7 has the IL bit
10948 * UNK/SBZP for "field not valid" cases, where v8 uses RES1.
10949 * If this is a v7 CPU, squash the IL bit in those cases.
10951 if (cs
->exception_index
== EXCP_PREFETCH_ABORT
||
10952 (cs
->exception_index
== EXCP_DATA_ABORT
&&
10953 !(env
->exception
.syndrome
& ARM_EL_ISV
)) ||
10954 syn_get_ec(env
->exception
.syndrome
) == EC_UNCATEGORIZED
) {
10955 env
->exception
.syndrome
&= ~ARM_EL_IL
;
10958 env
->cp15
.esr_el
[2] = env
->exception
.syndrome
;
10961 if (arm_current_el(env
) != 2 && addr
< 0x14) {
10966 if (!(env
->cp15
.scr_el3
& SCR_EA
)) {
10969 if (!(env
->cp15
.scr_el3
& SCR_IRQ
)) {
10972 if (!(env
->cp15
.scr_el3
& SCR_FIQ
)) {
10976 addr
+= env
->cp15
.hvbar
;
10978 take_aarch32_exception(env
, ARM_CPU_MODE_HYP
, mask
, 0, addr
);
10981 static void arm_cpu_do_interrupt_aarch32(CPUState
*cs
)
10983 ARMCPU
*cpu
= ARM_CPU(cs
);
10984 CPUARMState
*env
= &cpu
->env
;
10991 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
10992 switch (syn_get_ec(env
->exception
.syndrome
)) {
10993 case EC_BREAKPOINT
:
10994 case EC_BREAKPOINT_SAME_EL
:
10997 case EC_WATCHPOINT
:
10998 case EC_WATCHPOINT_SAME_EL
:
11004 case EC_VECTORCATCH
:
11013 env
->cp15
.mdscr_el1
= deposit64(env
->cp15
.mdscr_el1
, 2, 4, moe
);
11016 if (env
->exception
.target_el
== 2) {
11017 arm_cpu_do_interrupt_aarch32_hyp(cs
);
11021 switch (cs
->exception_index
) {
11023 new_mode
= ARM_CPU_MODE_UND
;
11033 new_mode
= ARM_CPU_MODE_SVC
;
11036 /* The PC already points to the next instruction. */
11040 /* Fall through to prefetch abort. */
11041 case EXCP_PREFETCH_ABORT
:
11042 A32_BANKED_CURRENT_REG_SET(env
, ifsr
, env
->exception
.fsr
);
11043 A32_BANKED_CURRENT_REG_SET(env
, ifar
, env
->exception
.vaddress
);
11044 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
11045 env
->exception
.fsr
, (uint32_t)env
->exception
.vaddress
);
11046 new_mode
= ARM_CPU_MODE_ABT
;
11048 mask
= CPSR_A
| CPSR_I
;
11051 case EXCP_DATA_ABORT
:
11052 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
11053 A32_BANKED_CURRENT_REG_SET(env
, dfar
, env
->exception
.vaddress
);
11054 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
11055 env
->exception
.fsr
,
11056 (uint32_t)env
->exception
.vaddress
);
11057 new_mode
= ARM_CPU_MODE_ABT
;
11059 mask
= CPSR_A
| CPSR_I
;
11063 new_mode
= ARM_CPU_MODE_IRQ
;
11065 /* Disable IRQ and imprecise data aborts. */
11066 mask
= CPSR_A
| CPSR_I
;
11068 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
11069 /* IRQ routed to monitor mode */
11070 new_mode
= ARM_CPU_MODE_MON
;
11075 new_mode
= ARM_CPU_MODE_FIQ
;
11077 /* Disable FIQ, IRQ and imprecise data aborts. */
11078 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
11079 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
11080 /* FIQ routed to monitor mode */
11081 new_mode
= ARM_CPU_MODE_MON
;
11086 new_mode
= ARM_CPU_MODE_IRQ
;
11088 /* Disable IRQ and imprecise data aborts. */
11089 mask
= CPSR_A
| CPSR_I
;
11093 new_mode
= ARM_CPU_MODE_FIQ
;
11095 /* Disable FIQ, IRQ and imprecise data aborts. */
11096 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
11102 * Note that this is reported as a data abort, but the DFAR
11103 * has an UNKNOWN value. Construct the SError syndrome from
11104 * AET and ExT fields.
11106 ARMMMUFaultInfo fi
= { .type
= ARMFault_AsyncExternal
, };
11108 if (extended_addresses_enabled(env
)) {
11109 env
->exception
.fsr
= arm_fi_to_lfsc(&fi
);
11111 env
->exception
.fsr
= arm_fi_to_sfsc(&fi
);
11113 env
->exception
.fsr
|= env
->cp15
.vsesr_el2
& 0xd000;
11114 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
11115 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x\n",
11116 env
->exception
.fsr
);
11118 new_mode
= ARM_CPU_MODE_ABT
;
11120 mask
= CPSR_A
| CPSR_I
;
11125 new_mode
= ARM_CPU_MODE_MON
;
11127 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
11131 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
11132 return; /* Never happens. Keep compiler happy. */
11135 if (new_mode
== ARM_CPU_MODE_MON
) {
11136 addr
+= env
->cp15
.mvbar
;
11137 } else if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
11138 /* High vectors. When enabled, base address cannot be remapped. */
11139 addr
+= 0xffff0000;
11142 * ARM v7 architectures provide a vector base address register to remap
11143 * the interrupt vector table.
11144 * This register is only followed in non-monitor mode, and is banked.
11145 * Note: only bits 31:5 are valid.
11147 addr
+= A32_BANKED_CURRENT_REG_GET(env
, vbar
);
11150 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
11151 env
->cp15
.scr_el3
&= ~SCR_NS
;
11154 take_aarch32_exception(env
, new_mode
, mask
, offset
, addr
);
11157 static int aarch64_regnum(CPUARMState
*env
, int aarch32_reg
)
11160 * Return the register number of the AArch64 view of the AArch32
11161 * register @aarch32_reg. The CPUARMState CPSR is assumed to still
11162 * be that of the AArch32 mode the exception came from.
11164 int mode
= env
->uncached_cpsr
& CPSR_M
;
11166 switch (aarch32_reg
) {
11168 return aarch32_reg
;
11170 return mode
== ARM_CPU_MODE_FIQ
? aarch32_reg
+ 16 : aarch32_reg
;
11173 case ARM_CPU_MODE_USR
:
11174 case ARM_CPU_MODE_SYS
:
11176 case ARM_CPU_MODE_HYP
:
11178 case ARM_CPU_MODE_IRQ
:
11180 case ARM_CPU_MODE_SVC
:
11182 case ARM_CPU_MODE_ABT
:
11184 case ARM_CPU_MODE_UND
:
11186 case ARM_CPU_MODE_FIQ
:
11189 g_assert_not_reached();
11193 case ARM_CPU_MODE_USR
:
11194 case ARM_CPU_MODE_SYS
:
11195 case ARM_CPU_MODE_HYP
:
11197 case ARM_CPU_MODE_IRQ
:
11199 case ARM_CPU_MODE_SVC
:
11201 case ARM_CPU_MODE_ABT
:
11203 case ARM_CPU_MODE_UND
:
11205 case ARM_CPU_MODE_FIQ
:
11208 g_assert_not_reached();
11213 g_assert_not_reached();
11217 static uint32_t cpsr_read_for_spsr_elx(CPUARMState
*env
)
11219 uint32_t ret
= cpsr_read(env
);
11221 /* Move DIT to the correct location for SPSR_ELx */
11222 if (ret
& CPSR_DIT
) {
11226 /* Merge PSTATE.SS into SPSR_ELx */
11227 ret
|= env
->pstate
& PSTATE_SS
;
11232 static bool syndrome_is_sync_extabt(uint32_t syndrome
)
11234 /* Return true if this syndrome value is a synchronous external abort */
11235 switch (syn_get_ec(syndrome
)) {
11237 case EC_INSNABORT_SAME_EL
:
11239 case EC_DATAABORT_SAME_EL
:
11240 /* Look at fault status code for all the synchronous ext abort cases */
11241 switch (syndrome
& 0x3f) {
11257 /* Handle exception entry to a target EL which is using AArch64 */
11258 static void arm_cpu_do_interrupt_aarch64(CPUState
*cs
)
11260 ARMCPU
*cpu
= ARM_CPU(cs
);
11261 CPUARMState
*env
= &cpu
->env
;
11262 unsigned int new_el
= env
->exception
.target_el
;
11263 target_ulong addr
= env
->cp15
.vbar_el
[new_el
];
11264 unsigned int new_mode
= aarch64_pstate_mode(new_el
, true);
11265 unsigned int old_mode
;
11266 unsigned int cur_el
= arm_current_el(env
);
11269 if (tcg_enabled()) {
11271 * Note that new_el can never be 0. If cur_el is 0, then
11272 * el0_a64 is is_a64(), else el0_a64 is ignored.
11274 aarch64_sve_change_el(env
, cur_el
, new_el
, is_a64(env
));
11277 if (cur_el
< new_el
) {
11279 * Entry vector offset depends on whether the implemented EL
11280 * immediately lower than the target level is using AArch32 or AArch64
11287 is_aa64
= (env
->cp15
.scr_el3
& SCR_RW
) != 0;
11290 hcr
= arm_hcr_el2_eff(env
);
11291 if ((hcr
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
11292 is_aa64
= (hcr
& HCR_RW
) != 0;
11297 is_aa64
= is_a64(env
);
11300 g_assert_not_reached();
11308 } else if (pstate_read(env
) & PSTATE_SP
) {
11312 switch (cs
->exception_index
) {
11314 qemu_log_mask(CPU_LOG_INT
, "...with MFAR 0x%" PRIx64
"\n",
11315 env
->cp15
.mfar_el3
);
11317 case EXCP_PREFETCH_ABORT
:
11318 case EXCP_DATA_ABORT
:
11320 * FEAT_DoubleFault allows synchronous external aborts taken to EL3
11321 * to be taken to the SError vector entrypoint.
11323 if (new_el
== 3 && (env
->cp15
.scr_el3
& SCR_EASE
) &&
11324 syndrome_is_sync_extabt(env
->exception
.syndrome
)) {
11327 env
->cp15
.far_el
[new_el
] = env
->exception
.vaddress
;
11328 qemu_log_mask(CPU_LOG_INT
, "...with FAR 0x%" PRIx64
"\n",
11329 env
->cp15
.far_el
[new_el
]);
11335 case EXCP_HYP_TRAP
:
11337 switch (syn_get_ec(env
->exception
.syndrome
)) {
11338 case EC_ADVSIMDFPACCESSTRAP
:
11340 * QEMU internal FP/SIMD syndromes from AArch32 include the
11341 * TA and coproc fields which are only exposed if the exception
11342 * is taken to AArch32 Hyp mode. Mask them out to get a valid
11343 * AArch64 format syndrome.
11345 env
->exception
.syndrome
&= ~MAKE_64BIT_MASK(0, 20);
11347 case EC_CP14RTTRAP
:
11348 case EC_CP15RTTRAP
:
11349 case EC_CP14DTTRAP
:
11351 * For a trap on AArch32 MRC/MCR/LDC/STC the Rt field is currently
11352 * the raw register field from the insn; when taking this to
11353 * AArch64 we must convert it to the AArch64 view of the register
11354 * number. Notice that we read a 4-bit AArch32 register number and
11355 * write back a 5-bit AArch64 one.
11357 rt
= extract32(env
->exception
.syndrome
, 5, 4);
11358 rt
= aarch64_regnum(env
, rt
);
11359 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
11362 case EC_CP15RRTTRAP
:
11363 case EC_CP14RRTTRAP
:
11364 /* Similarly for MRRC/MCRR traps for Rt and Rt2 fields */
11365 rt
= extract32(env
->exception
.syndrome
, 5, 4);
11366 rt
= aarch64_regnum(env
, rt
);
11367 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
11369 rt
= extract32(env
->exception
.syndrome
, 10, 4);
11370 rt
= aarch64_regnum(env
, rt
);
11371 env
->exception
.syndrome
= deposit32(env
->exception
.syndrome
,
11375 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
11387 /* Construct the SError syndrome from IDS and ISS fields. */
11388 env
->exception
.syndrome
= syn_serror(env
->cp15
.vsesr_el2
& 0x1ffffff);
11389 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
11392 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
11396 old_mode
= pstate_read(env
);
11397 aarch64_save_sp(env
, arm_current_el(env
));
11398 env
->elr_el
[new_el
] = env
->pc
;
11400 if (cur_el
== 1 && new_el
== 1) {
11401 uint64_t hcr
= arm_hcr_el2_eff(env
);
11402 if ((hcr
& (HCR_NV
| HCR_NV1
| HCR_NV2
)) == HCR_NV
||
11403 (hcr
& (HCR_NV
| HCR_NV2
)) == (HCR_NV
| HCR_NV2
)) {
11405 * FEAT_NV, FEAT_NV2 may need to report EL2 in the SPSR
11406 * by setting M[3:2] to 0b10.
11407 * If NV2 is disabled, change SPSR when NV,NV1 == 1,0 (I_ZJRNN)
11408 * If NV2 is enabled, change SPSR when NV is 1 (I_DBTLM)
11410 old_mode
= deposit32(old_mode
, 2, 2, 2);
11414 old_mode
= cpsr_read_for_spsr_elx(env
);
11415 env
->elr_el
[new_el
] = env
->regs
[15];
11417 aarch64_sync_32_to_64(env
);
11419 env
->condexec_bits
= 0;
11421 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = old_mode
;
11423 qemu_log_mask(CPU_LOG_INT
, "...with SPSR 0x%x\n", old_mode
);
11424 qemu_log_mask(CPU_LOG_INT
, "...with ELR 0x%" PRIx64
"\n",
11425 env
->elr_el
[new_el
]);
11427 if (cpu_isar_feature(aa64_pan
, cpu
)) {
11428 /* The value of PSTATE.PAN is normally preserved, except when ... */
11429 new_mode
|= old_mode
& PSTATE_PAN
;
11432 /* ... the target is EL2 with HCR_EL2.{E2H,TGE} == '11' ... */
11433 if ((arm_hcr_el2_eff(env
) & (HCR_E2H
| HCR_TGE
))
11434 != (HCR_E2H
| HCR_TGE
)) {
11439 /* ... the target is EL1 ... */
11440 /* ... and SCTLR_ELx.SPAN == 0, then set to 1. */
11441 if ((env
->cp15
.sctlr_el
[new_el
] & SCTLR_SPAN
) == 0) {
11442 new_mode
|= PSTATE_PAN
;
11447 if (cpu_isar_feature(aa64_mte
, cpu
)) {
11448 new_mode
|= PSTATE_TCO
;
11451 if (cpu_isar_feature(aa64_ssbs
, cpu
)) {
11452 if (env
->cp15
.sctlr_el
[new_el
] & SCTLR_DSSBS_64
) {
11453 new_mode
|= PSTATE_SSBS
;
11455 new_mode
&= ~PSTATE_SSBS
;
11459 pstate_write(env
, PSTATE_DAIF
| new_mode
);
11460 env
->aarch64
= true;
11461 aarch64_restore_sp(env
, new_el
);
11463 if (tcg_enabled()) {
11464 helper_rebuild_hflags_a64(env
, new_el
);
11469 qemu_log_mask(CPU_LOG_INT
, "...to EL%d PC 0x%" PRIx64
" PSTATE 0x%x\n",
11470 new_el
, env
->pc
, pstate_read(env
));
11474 * Do semihosting call and set the appropriate return value. All the
11475 * permission and validity checks have been done at translate time.
11477 * We only see semihosting exceptions in TCG only as they are not
11478 * trapped to the hypervisor in KVM.
11481 static void tcg_handle_semihosting(CPUState
*cs
)
11483 ARMCPU
*cpu
= ARM_CPU(cs
);
11484 CPUARMState
*env
= &cpu
->env
;
11487 qemu_log_mask(CPU_LOG_INT
,
11488 "...handling as semihosting call 0x%" PRIx64
"\n",
11490 do_common_semihosting(cs
);
11493 qemu_log_mask(CPU_LOG_INT
,
11494 "...handling as semihosting call 0x%x\n",
11496 do_common_semihosting(cs
);
11497 env
->regs
[15] += env
->thumb
? 2 : 4;
11503 * Handle a CPU exception for A and R profile CPUs.
11504 * Do any appropriate logging, handle PSCI calls, and then hand off
11505 * to the AArch64-entry or AArch32-entry function depending on the
11506 * target exception level's register width.
11508 * Note: this is used for both TCG (as the do_interrupt tcg op),
11509 * and KVM to re-inject guest debug exceptions, and to
11510 * inject a Synchronous-External-Abort.
11512 void arm_cpu_do_interrupt(CPUState
*cs
)
11514 ARMCPU
*cpu
= ARM_CPU(cs
);
11515 CPUARMState
*env
= &cpu
->env
;
11516 unsigned int new_el
= env
->exception
.target_el
;
11518 assert(!arm_feature(env
, ARM_FEATURE_M
));
11520 arm_log_exception(cs
);
11521 qemu_log_mask(CPU_LOG_INT
, "...from EL%d to EL%d\n", arm_current_el(env
),
11523 if (qemu_loglevel_mask(CPU_LOG_INT
)
11524 && !excp_is_internal(cs
->exception_index
)) {
11525 qemu_log_mask(CPU_LOG_INT
, "...with ESR 0x%x/0x%" PRIx32
"\n",
11526 syn_get_ec(env
->exception
.syndrome
),
11527 env
->exception
.syndrome
);
11530 if (tcg_enabled() && arm_is_psci_call(cpu
, cs
->exception_index
)) {
11531 arm_handle_psci_call(cpu
);
11532 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
11537 * Semihosting semantics depend on the register width of the code
11538 * that caused the exception, not the target exception level, so
11539 * must be handled here.
11542 if (cs
->exception_index
== EXCP_SEMIHOST
) {
11543 tcg_handle_semihosting(cs
);
11549 * Hooks may change global state so BQL should be held, also the
11550 * BQL needs to be held for any modification of
11551 * cs->interrupt_request.
11553 g_assert(bql_locked());
11555 arm_call_pre_el_change_hook(cpu
);
11557 assert(!excp_is_internal(cs
->exception_index
));
11558 if (arm_el_is_aa64(env
, new_el
)) {
11559 arm_cpu_do_interrupt_aarch64(cs
);
11561 arm_cpu_do_interrupt_aarch32(cs
);
11564 arm_call_el_change_hook(cpu
);
11566 if (!kvm_enabled()) {
11567 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
11570 #endif /* !CONFIG_USER_ONLY */
11572 uint64_t arm_sctlr(CPUARMState
*env
, int el
)
11574 /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */
11576 ARMMMUIdx mmu_idx
= arm_mmu_idx_el(env
, 0);
11577 el
= mmu_idx
== ARMMMUIdx_E20_0
? 2 : 1;
11579 return env
->cp15
.sctlr_el
[el
];
11582 int aa64_va_parameter_tbi(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11584 if (regime_has_2_ranges(mmu_idx
)) {
11585 return extract64(tcr
, 37, 2);
11586 } else if (regime_is_stage2(mmu_idx
)) {
11587 return 0; /* VTCR_EL2 */
11589 /* Replicate the single TBI bit so we always have 2 bits. */
11590 return extract32(tcr
, 20, 1) * 3;
11594 int aa64_va_parameter_tbid(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11596 if (regime_has_2_ranges(mmu_idx
)) {
11597 return extract64(tcr
, 51, 2);
11598 } else if (regime_is_stage2(mmu_idx
)) {
11599 return 0; /* VTCR_EL2 */
11601 /* Replicate the single TBID bit so we always have 2 bits. */
11602 return extract32(tcr
, 29, 1) * 3;
11606 int aa64_va_parameter_tcma(uint64_t tcr
, ARMMMUIdx mmu_idx
)
11608 if (regime_has_2_ranges(mmu_idx
)) {
11609 return extract64(tcr
, 57, 2);
11611 /* Replicate the single TCMA bit so we always have 2 bits. */
11612 return extract32(tcr
, 30, 1) * 3;
11616 static ARMGranuleSize
tg0_to_gran_size(int tg
)
11626 return GranInvalid
;
11630 static ARMGranuleSize
tg1_to_gran_size(int tg
)
11640 return GranInvalid
;
11644 static inline bool have4k(ARMCPU
*cpu
, bool stage2
)
11646 return stage2
? cpu_isar_feature(aa64_tgran4_2
, cpu
)
11647 : cpu_isar_feature(aa64_tgran4
, cpu
);
11650 static inline bool have16k(ARMCPU
*cpu
, bool stage2
)
11652 return stage2
? cpu_isar_feature(aa64_tgran16_2
, cpu
)
11653 : cpu_isar_feature(aa64_tgran16
, cpu
);
11656 static inline bool have64k(ARMCPU
*cpu
, bool stage2
)
11658 return stage2
? cpu_isar_feature(aa64_tgran64_2
, cpu
)
11659 : cpu_isar_feature(aa64_tgran64
, cpu
);
11662 static ARMGranuleSize
sanitize_gran_size(ARMCPU
*cpu
, ARMGranuleSize gran
,
11667 if (have4k(cpu
, stage2
)) {
11672 if (have16k(cpu
, stage2
)) {
11677 if (have64k(cpu
, stage2
)) {
11685 * If the guest selects a granule size that isn't implemented,
11686 * the architecture requires that we behave as if it selected one
11687 * that is (with an IMPDEF choice of which one to pick). We choose
11688 * to implement the smallest supported granule size.
11690 if (have4k(cpu
, stage2
)) {
11693 if (have16k(cpu
, stage2
)) {
11696 assert(have64k(cpu
, stage2
));
11700 ARMVAParameters
aa64_va_parameters(CPUARMState
*env
, uint64_t va
,
11701 ARMMMUIdx mmu_idx
, bool data
,
11704 uint64_t tcr
= regime_tcr(env
, mmu_idx
);
11705 bool epd
, hpd
, tsz_oob
, ds
, ha
, hd
;
11706 int select
, tsz
, tbi
, max_tsz
, min_tsz
, ps
, sh
;
11707 ARMGranuleSize gran
;
11708 ARMCPU
*cpu
= env_archcpu(env
);
11709 bool stage2
= regime_is_stage2(mmu_idx
);
11711 if (!regime_has_2_ranges(mmu_idx
)) {
11713 tsz
= extract32(tcr
, 0, 6);
11714 gran
= tg0_to_gran_size(extract32(tcr
, 14, 2));
11719 hpd
= extract32(tcr
, 24, 1);
11722 sh
= extract32(tcr
, 12, 2);
11723 ps
= extract32(tcr
, 16, 3);
11724 ha
= extract32(tcr
, 21, 1) && cpu_isar_feature(aa64_hafs
, cpu
);
11725 hd
= extract32(tcr
, 22, 1) && cpu_isar_feature(aa64_hdbs
, cpu
);
11726 ds
= extract64(tcr
, 32, 1);
11731 * Bit 55 is always between the two regions, and is canonical for
11732 * determining if address tagging is enabled.
11734 select
= extract64(va
, 55, 1);
11736 tsz
= extract32(tcr
, 0, 6);
11737 gran
= tg0_to_gran_size(extract32(tcr
, 14, 2));
11738 epd
= extract32(tcr
, 7, 1);
11739 sh
= extract32(tcr
, 12, 2);
11740 hpd
= extract64(tcr
, 41, 1);
11741 e0pd
= extract64(tcr
, 55, 1);
11743 tsz
= extract32(tcr
, 16, 6);
11744 gran
= tg1_to_gran_size(extract32(tcr
, 30, 2));
11745 epd
= extract32(tcr
, 23, 1);
11746 sh
= extract32(tcr
, 28, 2);
11747 hpd
= extract64(tcr
, 42, 1);
11748 e0pd
= extract64(tcr
, 56, 1);
11750 ps
= extract64(tcr
, 32, 3);
11751 ha
= extract64(tcr
, 39, 1) && cpu_isar_feature(aa64_hafs
, cpu
);
11752 hd
= extract64(tcr
, 40, 1) && cpu_isar_feature(aa64_hdbs
, cpu
);
11753 ds
= extract64(tcr
, 59, 1);
11755 if (e0pd
&& cpu_isar_feature(aa64_e0pd
, cpu
) &&
11756 regime_is_user(env
, mmu_idx
)) {
11761 gran
= sanitize_gran_size(cpu
, gran
, stage2
);
11763 if (cpu_isar_feature(aa64_st
, cpu
)) {
11764 max_tsz
= 48 - (gran
== Gran64K
);
11770 * DS is RES0 unless FEAT_LPA2 is supported for the given page size;
11771 * adjust the effective value of DS, as documented.
11774 if (gran
== Gran64K
) {
11775 if (cpu_isar_feature(aa64_lva
, cpu
)) {
11780 if (regime_is_stage2(mmu_idx
)) {
11781 if (gran
== Gran16K
) {
11782 ds
= cpu_isar_feature(aa64_tgran16_2_lpa2
, cpu
);
11784 ds
= cpu_isar_feature(aa64_tgran4_2_lpa2
, cpu
);
11787 if (gran
== Gran16K
) {
11788 ds
= cpu_isar_feature(aa64_tgran16_lpa2
, cpu
);
11790 ds
= cpu_isar_feature(aa64_tgran4_lpa2
, cpu
);
11798 if (stage2
&& el1_is_aa32
) {
11800 * For AArch32 EL1 the min txsz (and thus max IPA size) requirements
11801 * are loosened: a configured IPA of 40 bits is permitted even if
11802 * the implemented PA is less than that (and so a 40 bit IPA would
11803 * fault for an AArch64 EL1). See R_DTLMN.
11805 min_tsz
= MIN(min_tsz
, 24);
11808 if (tsz
> max_tsz
) {
11811 } else if (tsz
< min_tsz
) {
11818 /* Present TBI as a composite with TBID. */
11819 tbi
= aa64_va_parameter_tbi(tcr
, mmu_idx
);
11821 tbi
&= ~aa64_va_parameter_tbid(tcr
, mmu_idx
);
11823 tbi
= (tbi
>> select
) & 1;
11825 return (ARMVAParameters
) {
11833 .tsz_oob
= tsz_oob
,
11842 * Note that signed overflow is undefined in C. The following routines are
11843 * careful to use unsigned types where modulo arithmetic is required.
11844 * Failure to do so _will_ break on newer gcc.
11847 /* Signed saturating arithmetic. */
11849 /* Perform 16-bit signed saturating addition. */
11850 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
11855 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
11865 /* Perform 8-bit signed saturating addition. */
11866 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
11871 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
11881 /* Perform 16-bit signed saturating subtraction. */
11882 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
11887 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
11897 /* Perform 8-bit signed saturating subtraction. */
11898 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
11903 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
11913 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
11914 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
11915 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
11916 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
11919 #include "op_addsub.h"
11921 /* Unsigned saturating arithmetic. */
11922 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
11932 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
11941 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
11951 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
11960 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
11961 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
11962 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
11963 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
11966 #include "op_addsub.h"
11968 /* Signed modulo arithmetic. */
11969 #define SARITH16(a, b, n, op) do { \
11971 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
11972 RESULT(sum, n, 16); \
11974 ge |= 3 << (n * 2); \
11977 #define SARITH8(a, b, n, op) do { \
11979 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
11980 RESULT(sum, n, 8); \
11986 #define ADD16(a, b, n) SARITH16(a, b, n, +)
11987 #define SUB16(a, b, n) SARITH16(a, b, n, -)
11988 #define ADD8(a, b, n) SARITH8(a, b, n, +)
11989 #define SUB8(a, b, n) SARITH8(a, b, n, -)
11993 #include "op_addsub.h"
11995 /* Unsigned modulo arithmetic. */
11996 #define ADD16(a, b, n) do { \
11998 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
11999 RESULT(sum, n, 16); \
12000 if ((sum >> 16) == 1) \
12001 ge |= 3 << (n * 2); \
12004 #define ADD8(a, b, n) do { \
12006 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
12007 RESULT(sum, n, 8); \
12008 if ((sum >> 8) == 1) \
12012 #define SUB16(a, b, n) do { \
12014 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
12015 RESULT(sum, n, 16); \
12016 if ((sum >> 16) == 0) \
12017 ge |= 3 << (n * 2); \
12020 #define SUB8(a, b, n) do { \
12022 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
12023 RESULT(sum, n, 8); \
12024 if ((sum >> 8) == 0) \
12031 #include "op_addsub.h"
12033 /* Halved signed arithmetic. */
12034 #define ADD16(a, b, n) \
12035 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
12036 #define SUB16(a, b, n) \
12037 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
12038 #define ADD8(a, b, n) \
12039 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
12040 #define SUB8(a, b, n) \
12041 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
12044 #include "op_addsub.h"
12046 /* Halved unsigned arithmetic. */
12047 #define ADD16(a, b, n) \
12048 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
12049 #define SUB16(a, b, n) \
12050 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
12051 #define ADD8(a, b, n) \
12052 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
12053 #define SUB8(a, b, n) \
12054 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
12057 #include "op_addsub.h"
12059 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
12068 /* Unsigned sum of absolute byte differences. */
12069 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
12072 sum
= do_usad(a
, b
);
12073 sum
+= do_usad(a
>> 8, b
>> 8);
12074 sum
+= do_usad(a
>> 16, b
>> 16);
12075 sum
+= do_usad(a
>> 24, b
>> 24);
12079 /* For ARMv6 SEL instruction. */
12080 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
12095 mask
|= 0xff000000;
12097 return (a
& mask
) | (b
& ~mask
);
12102 * The upper bytes of val (above the number specified by 'bytes') must have
12103 * been zeroed out by the caller.
12105 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
12109 stl_le_p(buf
, val
);
12111 /* zlib crc32 converts the accumulator and output to one's complement. */
12112 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
12115 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
12119 stl_le_p(buf
, val
);
12121 /* Linux crc32c converts the output to one's complement. */
12122 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;
12126 * Return the exception level to which FP-disabled exceptions should
12127 * be taken, or 0 if FP is enabled.
12129 int fp_exception_el(CPUARMState
*env
, int cur_el
)
12131 #ifndef CONFIG_USER_ONLY
12135 * CPACR and the CPTR registers don't exist before v6, so FP is
12136 * always accessible
12138 if (!arm_feature(env
, ARM_FEATURE_V6
)) {
12142 if (arm_feature(env
, ARM_FEATURE_M
)) {
12143 /* CPACR can cause a NOCP UsageFault taken to current security state */
12144 if (!v7m_cpacr_pass(env
, env
->v7m
.secure
, cur_el
!= 0)) {
12148 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) && !env
->v7m
.secure
) {
12149 if (!extract32(env
->v7m
.nsacr
, 10, 1)) {
12150 /* FP insns cause a NOCP UsageFault taken to Secure */
12158 hcr_el2
= arm_hcr_el2_eff(env
);
12161 * The CPACR controls traps to EL1, or PL1 if we're 32 bit:
12162 * 0, 2 : trap EL0 and EL1/PL1 accesses
12163 * 1 : trap only EL0 accesses
12164 * 3 : trap no accesses
12165 * This register is ignored if E2H+TGE are both set.
12167 if ((hcr_el2
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
12168 int fpen
= FIELD_EX64(env
->cp15
.cpacr_el1
, CPACR_EL1
, FPEN
);
12178 /* Trap from Secure PL0 or PL1 to Secure PL1. */
12179 if (!arm_el_is_aa64(env
, 3)
12180 && (cur_el
== 3 || arm_is_secure_below_el3(env
))) {
12191 * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode
12192 * to control non-secure access to the FPU. It doesn't have any
12193 * effect if EL3 is AArch64 or if EL3 doesn't exist at all.
12195 if ((arm_feature(env
, ARM_FEATURE_EL3
) && !arm_el_is_aa64(env
, 3) &&
12196 cur_el
<= 2 && !arm_is_secure_below_el3(env
))) {
12197 if (!extract32(env
->cp15
.nsacr
, 10, 1)) {
12198 /* FP insns act as UNDEF */
12199 return cur_el
== 2 ? 2 : 1;
12204 * CPTR_EL2 is present in v7VE or v8, and changes format
12205 * with HCR_EL2.E2H (regardless of TGE).
12208 if (hcr_el2
& HCR_E2H
) {
12209 switch (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, FPEN
)) {
12211 if (cur_el
!= 0 || !(hcr_el2
& HCR_TGE
)) {
12219 } else if (arm_is_el2_enabled(env
)) {
12220 if (FIELD_EX64(env
->cp15
.cptr_el
[2], CPTR_EL2
, TFP
)) {
12226 /* CPTR_EL3 : present in v8 */
12227 if (FIELD_EX64(env
->cp15
.cptr_el
[3], CPTR_EL3
, TFP
)) {
12228 /* Trap all FP ops to EL3 */
12235 /* Return the exception level we're running at if this is our mmu_idx */
12236 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx
)
12238 if (mmu_idx
& ARM_MMU_IDX_M
) {
12239 return mmu_idx
& ARM_MMU_IDX_M_PRIV
;
12243 case ARMMMUIdx_E10_0
:
12244 case ARMMMUIdx_E20_0
:
12246 case ARMMMUIdx_E10_1
:
12247 case ARMMMUIdx_E10_1_PAN
:
12250 case ARMMMUIdx_E20_2
:
12251 case ARMMMUIdx_E20_2_PAN
:
12256 g_assert_not_reached();
12261 ARMMMUIdx
arm_v7m_mmu_idx_for_secstate(CPUARMState
*env
, bool secstate
)
12263 g_assert_not_reached();
12267 ARMMMUIdx
arm_mmu_idx_el(CPUARMState
*env
, int el
)
12272 if (arm_feature(env
, ARM_FEATURE_M
)) {
12273 return arm_v7m_mmu_idx_for_secstate(env
, env
->v7m
.secure
);
12276 /* See ARM pseudo-function ELIsInHost. */
12279 hcr
= arm_hcr_el2_eff(env
);
12280 if ((hcr
& (HCR_E2H
| HCR_TGE
)) == (HCR_E2H
| HCR_TGE
)) {
12281 idx
= ARMMMUIdx_E20_0
;
12283 idx
= ARMMMUIdx_E10_0
;
12287 if (arm_pan_enabled(env
)) {
12288 idx
= ARMMMUIdx_E10_1_PAN
;
12290 idx
= ARMMMUIdx_E10_1
;
12294 /* Note that TGE does not apply at EL2. */
12295 if (arm_hcr_el2_eff(env
) & HCR_E2H
) {
12296 if (arm_pan_enabled(env
)) {
12297 idx
= ARMMMUIdx_E20_2_PAN
;
12299 idx
= ARMMMUIdx_E20_2
;
12302 idx
= ARMMMUIdx_E2
;
12306 return ARMMMUIdx_E3
;
12308 g_assert_not_reached();
12314 ARMMMUIdx
arm_mmu_idx(CPUARMState
*env
)
12316 return arm_mmu_idx_el(env
, arm_current_el(env
));
12319 static bool mve_no_pred(CPUARMState
*env
)
12322 * Return true if there is definitely no predication of MVE
12323 * instructions by VPR or LTPSIZE. (Returning false even if there
12324 * isn't any predication is OK; generated code will just be
12326 * If the CPU does not implement MVE then this TB flag is always 0.
12328 * NOTE: if you change this logic, the "recalculate s->mve_no_pred"
12329 * logic in gen_update_fp_context() needs to be updated to match.
12331 * We do not include the effect of the ECI bits here -- they are
12332 * tracked in other TB flags. This simplifies the logic for
12333 * "when did we emit code that changes the MVE_NO_PRED TB flag
12334 * and thus need to end the TB?".
12336 if (cpu_isar_feature(aa32_mve
, env_archcpu(env
))) {
12339 if (env
->v7m
.vpr
) {
12342 if (env
->v7m
.ltpsize
< 4) {
12348 void cpu_get_tb_cpu_state(CPUARMState
*env
, vaddr
*pc
,
12349 uint64_t *cs_base
, uint32_t *pflags
)
12351 CPUARMTBFlags flags
;
12353 assert_hflags_rebuild_correctly(env
);
12354 flags
= env
->hflags
;
12356 if (EX_TBFLAG_ANY(flags
, AARCH64_STATE
)) {
12358 if (cpu_isar_feature(aa64_bti
, env_archcpu(env
))) {
12359 DP_TBFLAG_A64(flags
, BTYPE
, env
->btype
);
12362 *pc
= env
->regs
[15];
12364 if (arm_feature(env
, ARM_FEATURE_M
)) {
12365 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
12366 FIELD_EX32(env
->v7m
.fpccr
[M_REG_S
], V7M_FPCCR
, S
)
12367 != env
->v7m
.secure
) {
12368 DP_TBFLAG_M32(flags
, FPCCR_S_WRONG
, 1);
12371 if ((env
->v7m
.fpccr
[env
->v7m
.secure
] & R_V7M_FPCCR_ASPEN_MASK
) &&
12372 (!(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_FPCA_MASK
) ||
12373 (env
->v7m
.secure
&&
12374 !(env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
)))) {
12376 * ASPEN is set, but FPCA/SFPA indicate that there is no
12377 * active FP context; we must create a new FP context before
12378 * executing any FP insn.
12380 DP_TBFLAG_M32(flags
, NEW_FP_CTXT_NEEDED
, 1);
12383 bool is_secure
= env
->v7m
.fpccr
[M_REG_S
] & R_V7M_FPCCR_S_MASK
;
12384 if (env
->v7m
.fpccr
[is_secure
] & R_V7M_FPCCR_LSPACT_MASK
) {
12385 DP_TBFLAG_M32(flags
, LSPACT
, 1);
12388 if (mve_no_pred(env
)) {
12389 DP_TBFLAG_M32(flags
, MVE_NO_PRED
, 1);
12393 * Note that XSCALE_CPAR shares bits with VECSTRIDE.
12394 * Note that VECLEN+VECSTRIDE are RES0 for M-profile.
12396 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
12397 DP_TBFLAG_A32(flags
, XSCALE_CPAR
, env
->cp15
.c15_cpar
);
12399 DP_TBFLAG_A32(flags
, VECLEN
, env
->vfp
.vec_len
);
12400 DP_TBFLAG_A32(flags
, VECSTRIDE
, env
->vfp
.vec_stride
);
12402 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)) {
12403 DP_TBFLAG_A32(flags
, VFPEN
, 1);
12407 DP_TBFLAG_AM32(flags
, THUMB
, env
->thumb
);
12408 DP_TBFLAG_AM32(flags
, CONDEXEC
, env
->condexec_bits
);
12412 * The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
12413 * states defined in the ARM ARM for software singlestep:
12414 * SS_ACTIVE PSTATE.SS State
12415 * 0 x Inactive (the TB flag for SS is always 0)
12416 * 1 0 Active-pending
12417 * 1 1 Active-not-pending
12418 * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB.
12420 if (EX_TBFLAG_ANY(flags
, SS_ACTIVE
) && (env
->pstate
& PSTATE_SS
)) {
12421 DP_TBFLAG_ANY(flags
, PSTATE__SS
, 1);
12424 *pflags
= flags
.flags
;
12425 *cs_base
= flags
.flags2
;
12428 #ifdef TARGET_AARCH64
12430 * The manual says that when SVE is enabled and VQ is widened the
12431 * implementation is allowed to zero the previously inaccessible
12432 * portion of the registers. The corollary to that is that when
12433 * SVE is enabled and VQ is narrowed we are also allowed to zero
12434 * the now inaccessible portion of the registers.
12436 * The intent of this is that no predicate bit beyond VQ is ever set.
12437 * Which means that some operations on predicate registers themselves
12438 * may operate on full uint64_t or even unrolled across the maximum
12439 * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally
12440 * may well be cheaper than conditionals to restrict the operation
12441 * to the relevant portion of a uint16_t[16].
12443 void aarch64_sve_narrow_vq(CPUARMState
*env
, unsigned vq
)
12448 assert(vq
>= 1 && vq
<= ARM_MAX_VQ
);
12449 assert(vq
<= env_archcpu(env
)->sve_max_vq
);
12451 /* Zap the high bits of the zregs. */
12452 for (i
= 0; i
< 32; i
++) {
12453 memset(&env
->vfp
.zregs
[i
].d
[2 * vq
], 0, 16 * (ARM_MAX_VQ
- vq
));
12456 /* Zap the high bits of the pregs and ffr. */
12459 pmask
= ~(-1ULL << (16 * (vq
& 3)));
12461 for (j
= vq
/ 4; j
< ARM_MAX_VQ
/ 4; j
++) {
12462 for (i
= 0; i
< 17; ++i
) {
12463 env
->vfp
.pregs
[i
].p
[j
] &= pmask
;
12469 static uint32_t sve_vqm1_for_el_sm_ena(CPUARMState
*env
, int el
, bool sm
)
12474 exc_el
= sme_exception_el(env
, el
);
12476 exc_el
= sve_exception_el(env
, el
);
12479 return 0; /* disabled */
12481 return sve_vqm1_for_el_sm(env
, el
, sm
);
12485 * Notice a change in SVE vector size when changing EL.
12487 void aarch64_sve_change_el(CPUARMState
*env
, int old_el
,
12488 int new_el
, bool el0_a64
)
12490 ARMCPU
*cpu
= env_archcpu(env
);
12491 int old_len
, new_len
;
12492 bool old_a64
, new_a64
, sm
;
12494 /* Nothing to do if no SVE. */
12495 if (!cpu_isar_feature(aa64_sve
, cpu
)) {
12499 /* Nothing to do if FP is disabled in either EL. */
12500 if (fp_exception_el(env
, old_el
) || fp_exception_el(env
, new_el
)) {
12504 old_a64
= old_el
? arm_el_is_aa64(env
, old_el
) : el0_a64
;
12505 new_a64
= new_el
? arm_el_is_aa64(env
, new_el
) : el0_a64
;
12508 * Both AArch64.TakeException and AArch64.ExceptionReturn
12509 * invoke ResetSVEState when taking an exception from, or
12510 * returning to, AArch32 state when PSTATE.SM is enabled.
12512 sm
= FIELD_EX64(env
->svcr
, SVCR
, SM
);
12513 if (old_a64
!= new_a64
&& sm
) {
12514 arm_reset_sve_state(env
);
12519 * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
12520 * at ELx, or not available because the EL is in AArch32 state, then
12521 * for all purposes other than a direct read, the ZCR_ELx.LEN field
12522 * has an effective value of 0".
12524 * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0).
12525 * If we ignore aa32 state, we would fail to see the vq4->vq0 transition
12526 * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that
12527 * we already have the correct register contents when encountering the
12528 * vq0->vq0 transition between EL0->EL1.
12530 old_len
= new_len
= 0;
12532 old_len
= sve_vqm1_for_el_sm_ena(env
, old_el
, sm
);
12535 new_len
= sve_vqm1_for_el_sm_ena(env
, new_el
, sm
);
12538 /* When changing vector length, clear inaccessible state. */
12539 if (new_len
< old_len
) {
12540 aarch64_sve_narrow_vq(env
, new_len
+ 1);
12545 #ifndef CONFIG_USER_ONLY
12546 ARMSecuritySpace
arm_security_space(CPUARMState
*env
)
12548 if (arm_feature(env
, ARM_FEATURE_M
)) {
12549 return arm_secure_to_space(env
->v7m
.secure
);
12553 * If EL3 is not supported then the secure state is implementation
12554 * defined, in which case QEMU defaults to non-secure.
12556 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
12557 return ARMSS_NonSecure
;
12560 /* Check for AArch64 EL3 or AArch32 Mon. */
12562 if (extract32(env
->pstate
, 2, 2) == 3) {
12563 if (cpu_isar_feature(aa64_rme
, env_archcpu(env
))) {
12566 return ARMSS_Secure
;
12570 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
12571 return ARMSS_Secure
;
12575 return arm_security_space_below_el3(env
);
12578 ARMSecuritySpace
arm_security_space_below_el3(CPUARMState
*env
)
12580 assert(!arm_feature(env
, ARM_FEATURE_M
));
12583 * If EL3 is not supported then the secure state is implementation
12584 * defined, in which case QEMU defaults to non-secure.
12586 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
12587 return ARMSS_NonSecure
;
12591 * Note NSE cannot be set without RME, and NSE & !NS is Reserved.
12592 * Ignoring NSE when !NS retains consistency without having to
12593 * modify other predicates.
12595 if (!(env
->cp15
.scr_el3
& SCR_NS
)) {
12596 return ARMSS_Secure
;
12597 } else if (env
->cp15
.scr_el3
& SCR_NSE
) {
12598 return ARMSS_Realm
;
12600 return ARMSS_NonSecure
;
12603 #endif /* !CONFIG_USER_ONLY */