2 * ARM implementation of KVM hooks, 64 bit specific code
4 * Copyright Mian-M. Hamayun 2013, Virtual Open Systems
5 * Copyright Alex Bennée 2014, Linaro
7 * This work is licensed under the terms of the GNU GPL, version 2 or later.
8 * See the COPYING file in the top-level directory.
12 #include "qemu/osdep.h"
13 #include <sys/ioctl.h>
14 #include <sys/ptrace.h>
16 #include <linux/elf.h>
17 #include <linux/kvm.h>
19 #include "qemu-common.h"
21 #include "qemu/timer.h"
22 #include "qemu/error-report.h"
23 #include "qemu/host-utils.h"
24 #include "qemu/main-loop.h"
25 #include "exec/gdbstub.h"
26 #include "sysemu/kvm.h"
27 #include "sysemu/kvm_int.h"
29 #include "internals.h"
31 static bool have_guest_debug
;
34 * Although the ARM implementation of hardware assisted debugging
35 * allows for different breakpoints per-core, the current GDB
36 * interface treats them as a global pool of registers (which seems to
37 * be the case for x86, ppc and s390). As a result we store one copy
38 * of registers which is used for all active cores.
40 * Write access is serialised by virtue of the GDB protocol which
41 * updates things. Read access (i.e. when the values are copied to the
42 * vCPU) is also gated by GDB's run control.
44 * This is not unreasonable as most of the time debugging kernels you
45 * never know which core will eventually execute your function.
53 /* The watchpoint registers can cover more area than the requested
54 * watchpoint so we need to store the additional information
55 * somewhere. We also need to supply a CPUWatchpoint to the GDB stub
56 * when the watchpoint is hit.
61 CPUWatchpoint details
;
64 /* Maximum and current break/watch point counts */
65 int max_hw_bps
, max_hw_wps
;
66 GArray
*hw_breakpoints
, *hw_watchpoints
;
68 #define cur_hw_wps (hw_watchpoints->len)
69 #define cur_hw_bps (hw_breakpoints->len)
70 #define get_hw_bp(i) (&g_array_index(hw_breakpoints, HWBreakpoint, i))
71 #define get_hw_wp(i) (&g_array_index(hw_watchpoints, HWWatchpoint, i))
74 * kvm_arm_init_debug() - check for guest debug capabilities
77 * kvm_check_extension returns the number of debug registers we have
78 * or 0 if we have none.
81 static void kvm_arm_init_debug(CPUState
*cs
)
83 have_guest_debug
= kvm_check_extension(cs
->kvm_state
,
84 KVM_CAP_SET_GUEST_DEBUG
);
86 max_hw_wps
= kvm_check_extension(cs
->kvm_state
, KVM_CAP_GUEST_DEBUG_HW_WPS
);
87 hw_watchpoints
= g_array_sized_new(true, true,
88 sizeof(HWWatchpoint
), max_hw_wps
);
90 max_hw_bps
= kvm_check_extension(cs
->kvm_state
, KVM_CAP_GUEST_DEBUG_HW_BPS
);
91 hw_breakpoints
= g_array_sized_new(true, true,
92 sizeof(HWBreakpoint
), max_hw_bps
);
97 * insert_hw_breakpoint()
98 * @addr: address of breakpoint
100 * See ARM ARM D2.9.1 for details but here we are only going to create
101 * simple un-linked breakpoints (i.e. we don't chain breakpoints
102 * together to match address and context or vmid). The hardware is
103 * capable of fancier matching but that will require exposing that
104 * fanciness to GDB's interface
106 * DBGBCR<n>_EL1, Debug Breakpoint Control Registers
108 * 31 24 23 20 19 16 15 14 13 12 9 8 5 4 3 2 1 0
109 * +------+------+-------+-----+----+------+-----+------+-----+---+
110 * | RES0 | BT | LBN | SSC | HMC| RES0 | BAS | RES0 | PMC | E |
111 * +------+------+-------+-----+----+------+-----+------+-----+---+
113 * BT: Breakpoint type (0 = unlinked address match)
114 * LBN: Linked BP number (0 = unused)
115 * SSC/HMC/PMC: Security, Higher and Priv access control (Table D-12)
116 * BAS: Byte Address Select (RES1 for AArch64)
119 * DBGBVR<n>_EL1, Debug Breakpoint Value Registers
121 * 63 53 52 49 48 2 1 0
122 * +------+-----------+----------+-----+
123 * | RESS | VA[52:49] | VA[48:2] | 0 0 |
124 * +------+-----------+----------+-----+
126 * Depending on the addressing mode bits the top bits of the register
127 * are a sign extension of the highest applicable VA bit. Some
128 * versions of GDB don't do it correctly so we ensure they are correct
129 * here so future PC comparisons will work properly.
132 static int insert_hw_breakpoint(target_ulong addr
)
135 .bcr
= 0x1, /* BCR E=1, enable */
136 .bvr
= sextract64(addr
, 0, 53)
139 if (cur_hw_bps
>= max_hw_bps
) {
143 brk
.bcr
= deposit32(brk
.bcr
, 1, 2, 0x3); /* PMC = 11 */
144 brk
.bcr
= deposit32(brk
.bcr
, 5, 4, 0xf); /* BAS = RES1 */
146 g_array_append_val(hw_breakpoints
, brk
);
152 * delete_hw_breakpoint()
153 * @pc: address of breakpoint
155 * Delete a breakpoint and shuffle any above down
158 static int delete_hw_breakpoint(target_ulong pc
)
161 for (i
= 0; i
< hw_breakpoints
->len
; i
++) {
162 HWBreakpoint
*brk
= get_hw_bp(i
);
163 if (brk
->bvr
== pc
) {
164 g_array_remove_index(hw_breakpoints
, i
);
172 * insert_hw_watchpoint()
173 * @addr: address of watch point
175 * @type: type of watch point
177 * See ARM ARM D2.10. As with the breakpoints we can do some advanced
178 * stuff if we want to. The watch points can be linked with the break
179 * points above to make them context aware. However for simplicity
180 * currently we only deal with simple read/write watch points.
182 * D7.3.11 DBGWCR<n>_EL1, Debug Watchpoint Control Registers
184 * 31 29 28 24 23 21 20 19 16 15 14 13 12 5 4 3 2 1 0
185 * +------+-------+------+----+-----+-----+-----+-----+-----+-----+---+
186 * | RES0 | MASK | RES0 | WT | LBN | SSC | HMC | BAS | LSC | PAC | E |
187 * +------+-------+------+----+-----+-----+-----+-----+-----+-----+---+
189 * MASK: num bits addr mask (0=none,01/10=res,11=3 bits (8 bytes))
190 * WT: 0 - unlinked, 1 - linked (not currently used)
191 * LBN: Linked BP number (not currently used)
192 * SSC/HMC/PAC: Security, Higher and Priv access control (Table D2-11)
193 * BAS: Byte Address Select
194 * LSC: Load/Store control (01: load, 10: store, 11: both)
197 * The bottom 2 bits of the value register are masked. Therefore to
198 * break on any sizes smaller than an unaligned word you need to set
199 * MASK=0, BAS=bit per byte in question. For larger regions (^2) you
200 * need to ensure you mask the address as required and set BAS=0xff
203 static int insert_hw_watchpoint(target_ulong addr
,
204 target_ulong len
, int type
)
207 .wcr
= 1, /* E=1, enable */
208 .wvr
= addr
& (~0x7ULL
),
209 .details
= { .vaddr
= addr
, .len
= len
}
212 if (cur_hw_wps
>= max_hw_wps
) {
217 * HMC=0 SSC=0 PAC=3 will hit EL0 or EL1, any security state,
218 * valid whether EL3 is implemented or not
220 wp
.wcr
= deposit32(wp
.wcr
, 1, 2, 3);
223 case GDB_WATCHPOINT_READ
:
224 wp
.wcr
= deposit32(wp
.wcr
, 3, 2, 1);
225 wp
.details
.flags
= BP_MEM_READ
;
227 case GDB_WATCHPOINT_WRITE
:
228 wp
.wcr
= deposit32(wp
.wcr
, 3, 2, 2);
229 wp
.details
.flags
= BP_MEM_WRITE
;
231 case GDB_WATCHPOINT_ACCESS
:
232 wp
.wcr
= deposit32(wp
.wcr
, 3, 2, 3);
233 wp
.details
.flags
= BP_MEM_ACCESS
;
236 g_assert_not_reached();
240 /* we align the address and set the bits in BAS */
241 int off
= addr
& 0x7;
242 int bas
= (1 << len
) - 1;
244 wp
.wcr
= deposit32(wp
.wcr
, 5 + off
, 8 - off
, bas
);
246 /* For ranges above 8 bytes we need to be a power of 2 */
247 if (is_power_of_2(len
)) {
248 int bits
= ctz64(len
);
250 wp
.wvr
&= ~((1 << bits
) - 1);
251 wp
.wcr
= deposit32(wp
.wcr
, 24, 4, bits
);
252 wp
.wcr
= deposit32(wp
.wcr
, 5, 8, 0xff);
258 g_array_append_val(hw_watchpoints
, wp
);
263 static bool check_watchpoint_in_range(int i
, target_ulong addr
)
265 HWWatchpoint
*wp
= get_hw_wp(i
);
266 uint64_t addr_top
, addr_bottom
= wp
->wvr
;
267 int bas
= extract32(wp
->wcr
, 5, 8);
268 int mask
= extract32(wp
->wcr
, 24, 4);
271 addr_top
= addr_bottom
+ (1 << mask
);
273 /* BAS must be contiguous but can offset against the base
274 * address in DBGWVR */
275 addr_bottom
= addr_bottom
+ ctz32(bas
);
276 addr_top
= addr_bottom
+ clo32(bas
);
279 if (addr
>= addr_bottom
&& addr
<= addr_top
) {
287 * delete_hw_watchpoint()
288 * @addr: address of breakpoint
290 * Delete a breakpoint and shuffle any above down
293 static int delete_hw_watchpoint(target_ulong addr
,
294 target_ulong len
, int type
)
297 for (i
= 0; i
< cur_hw_wps
; i
++) {
298 if (check_watchpoint_in_range(i
, addr
)) {
299 g_array_remove_index(hw_watchpoints
, i
);
307 int kvm_arch_insert_hw_breakpoint(target_ulong addr
,
308 target_ulong len
, int type
)
311 case GDB_BREAKPOINT_HW
:
312 return insert_hw_breakpoint(addr
);
314 case GDB_WATCHPOINT_READ
:
315 case GDB_WATCHPOINT_WRITE
:
316 case GDB_WATCHPOINT_ACCESS
:
317 return insert_hw_watchpoint(addr
, len
, type
);
323 int kvm_arch_remove_hw_breakpoint(target_ulong addr
,
324 target_ulong len
, int type
)
327 case GDB_BREAKPOINT_HW
:
328 return delete_hw_breakpoint(addr
);
330 case GDB_WATCHPOINT_READ
:
331 case GDB_WATCHPOINT_WRITE
:
332 case GDB_WATCHPOINT_ACCESS
:
333 return delete_hw_watchpoint(addr
, len
, type
);
340 void kvm_arch_remove_all_hw_breakpoints(void)
342 if (cur_hw_wps
> 0) {
343 g_array_remove_range(hw_watchpoints
, 0, cur_hw_wps
);
345 if (cur_hw_bps
> 0) {
346 g_array_remove_range(hw_breakpoints
, 0, cur_hw_bps
);
350 void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch
*ptr
)
353 memset(ptr
, 0, sizeof(struct kvm_guest_debug_arch
));
355 for (i
= 0; i
< max_hw_wps
; i
++) {
356 HWWatchpoint
*wp
= get_hw_wp(i
);
357 ptr
->dbg_wcr
[i
] = wp
->wcr
;
358 ptr
->dbg_wvr
[i
] = wp
->wvr
;
360 for (i
= 0; i
< max_hw_bps
; i
++) {
361 HWBreakpoint
*bp
= get_hw_bp(i
);
362 ptr
->dbg_bcr
[i
] = bp
->bcr
;
363 ptr
->dbg_bvr
[i
] = bp
->bvr
;
367 bool kvm_arm_hw_debug_active(CPUState
*cs
)
369 return ((cur_hw_wps
> 0) || (cur_hw_bps
> 0));
372 static bool find_hw_breakpoint(CPUState
*cpu
, target_ulong pc
)
376 for (i
= 0; i
< cur_hw_bps
; i
++) {
377 HWBreakpoint
*bp
= get_hw_bp(i
);
385 static CPUWatchpoint
*find_hw_watchpoint(CPUState
*cpu
, target_ulong addr
)
389 for (i
= 0; i
< cur_hw_wps
; i
++) {
390 if (check_watchpoint_in_range(i
, addr
)) {
391 return &get_hw_wp(i
)->details
;
397 static bool kvm_arm_pmu_set_attr(CPUState
*cs
, struct kvm_device_attr
*attr
)
401 err
= kvm_vcpu_ioctl(cs
, KVM_HAS_DEVICE_ATTR
, attr
);
403 error_report("PMU: KVM_HAS_DEVICE_ATTR: %s", strerror(-err
));
407 err
= kvm_vcpu_ioctl(cs
, KVM_SET_DEVICE_ATTR
, attr
);
409 error_report("PMU: KVM_SET_DEVICE_ATTR: %s", strerror(-err
));
416 void kvm_arm_pmu_init(CPUState
*cs
)
418 struct kvm_device_attr attr
= {
419 .group
= KVM_ARM_VCPU_PMU_V3_CTRL
,
420 .attr
= KVM_ARM_VCPU_PMU_V3_INIT
,
423 if (!ARM_CPU(cs
)->has_pmu
) {
426 if (!kvm_arm_pmu_set_attr(cs
, &attr
)) {
427 error_report("failed to init PMU");
432 void kvm_arm_pmu_set_irq(CPUState
*cs
, int irq
)
434 struct kvm_device_attr attr
= {
435 .group
= KVM_ARM_VCPU_PMU_V3_CTRL
,
436 .addr
= (intptr_t)&irq
,
437 .attr
= KVM_ARM_VCPU_PMU_V3_IRQ
,
440 if (!ARM_CPU(cs
)->has_pmu
) {
443 if (!kvm_arm_pmu_set_attr(cs
, &attr
)) {
444 error_report("failed to set irq for PMU");
449 static inline void set_feature(uint64_t *features
, int feature
)
451 *features
|= 1ULL << feature
;
454 static inline void unset_feature(uint64_t *features
, int feature
)
456 *features
&= ~(1ULL << feature
);
459 static int read_sys_reg32(int fd
, uint32_t *pret
, uint64_t id
)
462 struct kvm_one_reg idreg
= { .id
= id
, .addr
= (uintptr_t)&ret
};
465 assert((id
& KVM_REG_SIZE_MASK
) == KVM_REG_SIZE_U64
);
466 err
= ioctl(fd
, KVM_GET_ONE_REG
, &idreg
);
474 static int read_sys_reg64(int fd
, uint64_t *pret
, uint64_t id
)
476 struct kvm_one_reg idreg
= { .id
= id
, .addr
= (uintptr_t)pret
};
478 assert((id
& KVM_REG_SIZE_MASK
) == KVM_REG_SIZE_U64
);
479 return ioctl(fd
, KVM_GET_ONE_REG
, &idreg
);
482 bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures
*ahcf
)
484 /* Identify the feature bits corresponding to the host CPU, and
485 * fill out the ARMHostCPUClass fields accordingly. To do this
486 * we have to create a scratch VM, create a single CPU inside it,
487 * and then query that CPU for the relevant ID registers.
491 uint64_t features
= 0;
495 /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
496 * we know these will only support creating one kind of guest CPU,
497 * which is its preferred CPU type. Fortunately these old kernels
498 * support only a very limited number of CPUs.
500 static const uint32_t cpus_to_try
[] = {
501 KVM_ARM_TARGET_AEM_V8
,
502 KVM_ARM_TARGET_FOUNDATION_V8
,
503 KVM_ARM_TARGET_CORTEX_A57
,
504 QEMU_KVM_ARM_TARGET_NONE
507 * target = -1 informs kvm_arm_create_scratch_host_vcpu()
508 * to use the preferred target
510 struct kvm_vcpu_init init
= { .target
= -1, };
512 if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try
, fdarray
, &init
)) {
516 ahcf
->target
= init
.target
;
517 ahcf
->dtb_compatible
= "arm,arm-v8";
519 err
= read_sys_reg64(fdarray
[2], &ahcf
->isar
.id_aa64pfr0
,
520 ARM64_SYS_REG(3, 0, 0, 4, 0));
521 if (unlikely(err
< 0)) {
523 * Before v4.15, the kernel only exposed a limited number of system
524 * registers, not including any of the interesting AArch64 ID regs.
525 * For the most part we could leave these fields as zero with minimal
526 * effect, since this does not affect the values seen by the guest.
528 * However, it could cause problems down the line for QEMU,
529 * so provide a minimal v8.0 default.
531 * ??? Could read MIDR and use knowledge from cpu64.c.
532 * ??? Could map a page of memory into our temp guest and
533 * run the tiniest of hand-crafted kernels to extract
534 * the values seen by the guest.
535 * ??? Either of these sounds like too much effort just
536 * to work around running a modern host kernel.
538 ahcf
->isar
.id_aa64pfr0
= 0x00000011; /* EL1&0, AArch64 only */
541 err
|= read_sys_reg64(fdarray
[2], &ahcf
->isar
.id_aa64pfr1
,
542 ARM64_SYS_REG(3, 0, 0, 4, 1));
543 err
|= read_sys_reg64(fdarray
[2], &ahcf
->isar
.id_aa64isar0
,
544 ARM64_SYS_REG(3, 0, 0, 6, 0));
545 err
|= read_sys_reg64(fdarray
[2], &ahcf
->isar
.id_aa64isar1
,
546 ARM64_SYS_REG(3, 0, 0, 6, 1));
547 err
|= read_sys_reg64(fdarray
[2], &ahcf
->isar
.id_aa64mmfr0
,
548 ARM64_SYS_REG(3, 0, 0, 7, 0));
549 err
|= read_sys_reg64(fdarray
[2], &ahcf
->isar
.id_aa64mmfr1
,
550 ARM64_SYS_REG(3, 0, 0, 7, 1));
553 * Note that if AArch32 support is not present in the host,
554 * the AArch32 sysregs are present to be read, but will
555 * return UNKNOWN values. This is neither better nor worse
556 * than skipping the reads and leaving 0, as we must avoid
557 * considering the values in every case.
559 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_isar0
,
560 ARM64_SYS_REG(3, 0, 0, 2, 0));
561 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_isar1
,
562 ARM64_SYS_REG(3, 0, 0, 2, 1));
563 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_isar2
,
564 ARM64_SYS_REG(3, 0, 0, 2, 2));
565 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_isar3
,
566 ARM64_SYS_REG(3, 0, 0, 2, 3));
567 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_isar4
,
568 ARM64_SYS_REG(3, 0, 0, 2, 4));
569 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_isar5
,
570 ARM64_SYS_REG(3, 0, 0, 2, 5));
571 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.id_isar6
,
572 ARM64_SYS_REG(3, 0, 0, 2, 7));
574 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.mvfr0
,
575 ARM64_SYS_REG(3, 0, 0, 3, 0));
576 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.mvfr1
,
577 ARM64_SYS_REG(3, 0, 0, 3, 1));
578 err
|= read_sys_reg32(fdarray
[2], &ahcf
->isar
.mvfr2
,
579 ARM64_SYS_REG(3, 0, 0, 3, 2));
582 sve_supported
= ioctl(fdarray
[0], KVM_CHECK_EXTENSION
, KVM_CAP_ARM_SVE
) > 0;
584 kvm_arm_destroy_scratch_host_vcpu(fdarray
);
590 /* Add feature bits that can't appear until after VCPU init. */
592 t
= ahcf
->isar
.id_aa64pfr0
;
593 t
= FIELD_DP64(t
, ID_AA64PFR0
, SVE
, 1);
594 ahcf
->isar
.id_aa64pfr0
= t
;
598 * We can assume any KVM supporting CPU is at least a v8
599 * with VFPv4+Neon; this in turn implies most of the other
602 set_feature(&features
, ARM_FEATURE_V8
);
603 set_feature(&features
, ARM_FEATURE_VFP4
);
604 set_feature(&features
, ARM_FEATURE_NEON
);
605 set_feature(&features
, ARM_FEATURE_AARCH64
);
606 set_feature(&features
, ARM_FEATURE_PMU
);
608 ahcf
->features
= features
;
613 bool kvm_arm_aarch32_supported(CPUState
*cpu
)
615 KVMState
*s
= KVM_STATE(current_accel());
617 return kvm_check_extension(s
, KVM_CAP_ARM_EL1_32BIT
);
620 bool kvm_arm_sve_supported(CPUState
*cpu
)
622 KVMState
*s
= KVM_STATE(current_accel());
624 return kvm_check_extension(s
, KVM_CAP_ARM_SVE
);
627 QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN
!= 1);
629 void kvm_arm_sve_get_vls(CPUState
*cs
, unsigned long *map
)
631 /* Only call this function if kvm_arm_sve_supported() returns true. */
632 static uint64_t vls
[KVM_ARM64_SVE_VLS_WORDS
];
637 bitmap_clear(map
, 0, ARM_MAX_VQ
);
640 * KVM ensures all host CPUs support the same set of vector lengths.
641 * So we only need to create the scratch VCPUs once and then cache
645 struct kvm_vcpu_init init
= {
647 .features
[0] = (1 << KVM_ARM_VCPU_SVE
),
649 struct kvm_one_reg reg
= {
650 .id
= KVM_REG_ARM64_SVE_VLS
,
651 .addr
= (uint64_t)&vls
[0],
657 if (!kvm_arm_create_scratch_host_vcpu(NULL
, fdarray
, &init
)) {
658 error_report("failed to create scratch VCPU with SVE enabled");
661 ret
= ioctl(fdarray
[2], KVM_GET_ONE_REG
, ®
);
662 kvm_arm_destroy_scratch_host_vcpu(fdarray
);
664 error_report("failed to get KVM_REG_ARM64_SVE_VLS: %s",
669 for (i
= KVM_ARM64_SVE_VLS_WORDS
- 1; i
>= 0; --i
) {
671 vq
= 64 - clz64(vls
[i
]) + i
* 64;
675 if (vq
> ARM_MAX_VQ
) {
676 warn_report("KVM supports vector lengths larger than "
681 for (i
= 0; i
< KVM_ARM64_SVE_VLS_WORDS
; ++i
) {
685 for (j
= 1; j
<= 64; ++j
) {
687 if (vq
> ARM_MAX_VQ
) {
690 if (vls
[i
] & (1UL << (j
- 1))) {
691 set_bit(vq
- 1, map
);
697 static int kvm_arm_sve_set_vls(CPUState
*cs
)
699 uint64_t vls
[KVM_ARM64_SVE_VLS_WORDS
] = {0};
700 struct kvm_one_reg reg
= {
701 .id
= KVM_REG_ARM64_SVE_VLS
,
702 .addr
= (uint64_t)&vls
[0],
704 ARMCPU
*cpu
= ARM_CPU(cs
);
708 assert(cpu
->sve_max_vq
<= KVM_ARM64_SVE_VQ_MAX
);
710 for (vq
= 1; vq
<= cpu
->sve_max_vq
; ++vq
) {
711 if (test_bit(vq
- 1, cpu
->sve_vq_map
)) {
718 return kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
721 #define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5
723 int kvm_arch_init_vcpu(CPUState
*cs
)
727 ARMCPU
*cpu
= ARM_CPU(cs
);
728 CPUARMState
*env
= &cpu
->env
;
730 if (cpu
->kvm_target
== QEMU_KVM_ARM_TARGET_NONE
||
731 !object_dynamic_cast(OBJECT(cpu
), TYPE_AARCH64_CPU
)) {
732 error_report("KVM is not supported for this guest CPU type");
736 /* Determine init features for this CPU */
737 memset(cpu
->kvm_init_features
, 0, sizeof(cpu
->kvm_init_features
));
738 if (cpu
->start_powered_off
) {
739 cpu
->kvm_init_features
[0] |= 1 << KVM_ARM_VCPU_POWER_OFF
;
741 if (kvm_check_extension(cs
->kvm_state
, KVM_CAP_ARM_PSCI_0_2
)) {
742 cpu
->psci_version
= 2;
743 cpu
->kvm_init_features
[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2
;
745 if (!arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
746 cpu
->kvm_init_features
[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT
;
748 if (!kvm_check_extension(cs
->kvm_state
, KVM_CAP_ARM_PMU_V3
)) {
749 cpu
->has_pmu
= false;
752 cpu
->kvm_init_features
[0] |= 1 << KVM_ARM_VCPU_PMU_V3
;
754 unset_feature(&env
->features
, ARM_FEATURE_PMU
);
756 if (cpu_isar_feature(aa64_sve
, cpu
)) {
757 assert(kvm_arm_sve_supported(cs
));
758 cpu
->kvm_init_features
[0] |= 1 << KVM_ARM_VCPU_SVE
;
761 /* Do KVM_ARM_VCPU_INIT ioctl */
762 ret
= kvm_arm_vcpu_init(cs
);
767 if (cpu_isar_feature(aa64_sve
, cpu
)) {
768 ret
= kvm_arm_sve_set_vls(cs
);
772 ret
= kvm_arm_vcpu_finalize(cs
, KVM_ARM_VCPU_SVE
);
779 * When KVM is in use, PSCI is emulated in-kernel and not by qemu.
780 * Currently KVM has its own idea about MPIDR assignment, so we
781 * override our defaults with what we get from KVM.
783 ret
= kvm_get_one_reg(cs
, ARM64_SYS_REG(ARM_CPU_ID_MPIDR
), &mpidr
);
787 cpu
->mp_affinity
= mpidr
& ARM64_AFFINITY_MASK
;
789 kvm_arm_init_debug(cs
);
791 /* Check whether user space can specify guest syndrome value */
792 kvm_arm_init_serror_injection(cs
);
794 return kvm_arm_init_cpreg_list(cpu
);
797 int kvm_arch_destroy_vcpu(CPUState
*cs
)
802 bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx
)
804 /* Return true if the regidx is a register we should synchronize
805 * via the cpreg_tuples array (ie is not a core or sve reg that
806 * we sync by hand in kvm_arch_get/put_registers())
808 switch (regidx
& KVM_REG_ARM_COPROC_MASK
) {
809 case KVM_REG_ARM_CORE
:
810 case KVM_REG_ARM64_SVE
:
817 typedef struct CPRegStateLevel
{
822 /* All system registers not listed in the following table are assumed to be
823 * of the level KVM_PUT_RUNTIME_STATE. If a register should be written less
824 * often, you must add it to this table with a state of either
825 * KVM_PUT_RESET_STATE or KVM_PUT_FULL_STATE.
827 static const CPRegStateLevel non_runtime_cpregs
[] = {
828 { KVM_REG_ARM_TIMER_CNT
, KVM_PUT_FULL_STATE
},
831 int kvm_arm_cpreg_level(uint64_t regidx
)
835 for (i
= 0; i
< ARRAY_SIZE(non_runtime_cpregs
); i
++) {
836 const CPRegStateLevel
*l
= &non_runtime_cpregs
[i
];
837 if (l
->regidx
== regidx
) {
842 return KVM_PUT_RUNTIME_STATE
;
845 #define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
846 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
848 #define AARCH64_SIMD_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U128 | \
849 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
851 #define AARCH64_SIMD_CTRL_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U32 | \
852 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
854 static int kvm_arch_put_fpsimd(CPUState
*cs
)
856 CPUARMState
*env
= &ARM_CPU(cs
)->env
;
857 struct kvm_one_reg reg
;
860 for (i
= 0; i
< 32; i
++) {
861 uint64_t *q
= aa64_vfp_qreg(env
, i
);
862 #ifdef HOST_WORDS_BIGENDIAN
863 uint64_t fp_val
[2] = { q
[1], q
[0] };
864 reg
.addr
= (uintptr_t)fp_val
;
866 reg
.addr
= (uintptr_t)q
;
868 reg
.id
= AARCH64_SIMD_CORE_REG(fp_regs
.vregs
[i
]);
869 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
879 * KVM SVE registers come in slices where ZREGs have a slice size of 2048 bits
880 * and PREGS and the FFR have a slice size of 256 bits. However we simply hard
881 * code the slice index to zero for now as it's unlikely we'll need more than
882 * one slice for quite some time.
884 static int kvm_arch_put_sve(CPUState
*cs
)
886 ARMCPU
*cpu
= ARM_CPU(cs
);
887 CPUARMState
*env
= &cpu
->env
;
888 uint64_t tmp
[ARM_MAX_VQ
* 2];
890 struct kvm_one_reg reg
;
893 for (n
= 0; n
< KVM_ARM64_SVE_NUM_ZREGS
; ++n
) {
894 r
= sve_bswap64(tmp
, &env
->vfp
.zregs
[n
].d
[0], cpu
->sve_max_vq
* 2);
895 reg
.addr
= (uintptr_t)r
;
896 reg
.id
= KVM_REG_ARM64_SVE_ZREG(n
, 0);
897 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
903 for (n
= 0; n
< KVM_ARM64_SVE_NUM_PREGS
; ++n
) {
904 r
= sve_bswap64(tmp
, r
= &env
->vfp
.pregs
[n
].p
[0],
905 DIV_ROUND_UP(cpu
->sve_max_vq
* 2, 8));
906 reg
.addr
= (uintptr_t)r
;
907 reg
.id
= KVM_REG_ARM64_SVE_PREG(n
, 0);
908 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
914 r
= sve_bswap64(tmp
, &env
->vfp
.pregs
[FFR_PRED_NUM
].p
[0],
915 DIV_ROUND_UP(cpu
->sve_max_vq
* 2, 8));
916 reg
.addr
= (uintptr_t)r
;
917 reg
.id
= KVM_REG_ARM64_SVE_FFR(0);
918 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
926 int kvm_arch_put_registers(CPUState
*cs
, int level
)
928 struct kvm_one_reg reg
;
934 ARMCPU
*cpu
= ARM_CPU(cs
);
935 CPUARMState
*env
= &cpu
->env
;
937 /* If we are in AArch32 mode then we need to copy the AArch32 regs to the
938 * AArch64 registers before pushing them out to 64-bit KVM.
941 aarch64_sync_32_to_64(env
);
944 for (i
= 0; i
< 31; i
++) {
945 reg
.id
= AARCH64_CORE_REG(regs
.regs
[i
]);
946 reg
.addr
= (uintptr_t) &env
->xregs
[i
];
947 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
953 /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the
954 * QEMU side we keep the current SP in xregs[31] as well.
956 aarch64_save_sp(env
, 1);
958 reg
.id
= AARCH64_CORE_REG(regs
.sp
);
959 reg
.addr
= (uintptr_t) &env
->sp_el
[0];
960 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
965 reg
.id
= AARCH64_CORE_REG(sp_el1
);
966 reg
.addr
= (uintptr_t) &env
->sp_el
[1];
967 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
972 /* Note that KVM thinks pstate is 64 bit but we use a uint32_t */
974 val
= pstate_read(env
);
976 val
= cpsr_read(env
);
978 reg
.id
= AARCH64_CORE_REG(regs
.pstate
);
979 reg
.addr
= (uintptr_t) &val
;
980 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
985 reg
.id
= AARCH64_CORE_REG(regs
.pc
);
986 reg
.addr
= (uintptr_t) &env
->pc
;
987 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
992 reg
.id
= AARCH64_CORE_REG(elr_el1
);
993 reg
.addr
= (uintptr_t) &env
->elr_el
[1];
994 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
999 /* Saved Program State Registers
1001 * Before we restore from the banked_spsr[] array we need to
1002 * ensure that any modifications to env->spsr are correctly
1003 * reflected in the banks.
1005 el
= arm_current_el(env
);
1006 if (el
> 0 && !is_a64(env
)) {
1007 i
= bank_number(env
->uncached_cpsr
& CPSR_M
);
1008 env
->banked_spsr
[i
] = env
->spsr
;
1011 /* KVM 0-4 map to QEMU banks 1-5 */
1012 for (i
= 0; i
< KVM_NR_SPSR
; i
++) {
1013 reg
.id
= AARCH64_CORE_REG(spsr
[i
]);
1014 reg
.addr
= (uintptr_t) &env
->banked_spsr
[i
+ 1];
1015 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
1021 if (cpu_isar_feature(aa64_sve
, cpu
)) {
1022 ret
= kvm_arch_put_sve(cs
);
1024 ret
= kvm_arch_put_fpsimd(cs
);
1030 reg
.addr
= (uintptr_t)(&fpr
);
1031 fpr
= vfp_get_fpsr(env
);
1032 reg
.id
= AARCH64_SIMD_CTRL_REG(fp_regs
.fpsr
);
1033 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
1038 reg
.addr
= (uintptr_t)(&fpr
);
1039 fpr
= vfp_get_fpcr(env
);
1040 reg
.id
= AARCH64_SIMD_CTRL_REG(fp_regs
.fpcr
);
1041 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
1046 ret
= kvm_put_vcpu_events(cpu
);
1051 write_cpustate_to_list(cpu
, true);
1053 if (!write_list_to_kvmstate(cpu
, level
)) {
1057 kvm_arm_sync_mpstate_to_kvm(cpu
);
1062 static int kvm_arch_get_fpsimd(CPUState
*cs
)
1064 CPUARMState
*env
= &ARM_CPU(cs
)->env
;
1065 struct kvm_one_reg reg
;
1068 for (i
= 0; i
< 32; i
++) {
1069 uint64_t *q
= aa64_vfp_qreg(env
, i
);
1070 reg
.id
= AARCH64_SIMD_CORE_REG(fp_regs
.vregs
[i
]);
1071 reg
.addr
= (uintptr_t)q
;
1072 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
1076 #ifdef HOST_WORDS_BIGENDIAN
1078 t
= q
[0], q
[0] = q
[1], q
[1] = t
;
1087 * KVM SVE registers come in slices where ZREGs have a slice size of 2048 bits
1088 * and PREGS and the FFR have a slice size of 256 bits. However we simply hard
1089 * code the slice index to zero for now as it's unlikely we'll need more than
1090 * one slice for quite some time.
1092 static int kvm_arch_get_sve(CPUState
*cs
)
1094 ARMCPU
*cpu
= ARM_CPU(cs
);
1095 CPUARMState
*env
= &cpu
->env
;
1096 struct kvm_one_reg reg
;
1100 for (n
= 0; n
< KVM_ARM64_SVE_NUM_ZREGS
; ++n
) {
1101 r
= &env
->vfp
.zregs
[n
].d
[0];
1102 reg
.addr
= (uintptr_t)r
;
1103 reg
.id
= KVM_REG_ARM64_SVE_ZREG(n
, 0);
1104 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
1108 sve_bswap64(r
, r
, cpu
->sve_max_vq
* 2);
1111 for (n
= 0; n
< KVM_ARM64_SVE_NUM_PREGS
; ++n
) {
1112 r
= &env
->vfp
.pregs
[n
].p
[0];
1113 reg
.addr
= (uintptr_t)r
;
1114 reg
.id
= KVM_REG_ARM64_SVE_PREG(n
, 0);
1115 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
1119 sve_bswap64(r
, r
, DIV_ROUND_UP(cpu
->sve_max_vq
* 2, 8));
1122 r
= &env
->vfp
.pregs
[FFR_PRED_NUM
].p
[0];
1123 reg
.addr
= (uintptr_t)r
;
1124 reg
.id
= KVM_REG_ARM64_SVE_FFR(0);
1125 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
1129 sve_bswap64(r
, r
, DIV_ROUND_UP(cpu
->sve_max_vq
* 2, 8));
1134 int kvm_arch_get_registers(CPUState
*cs
)
1136 struct kvm_one_reg reg
;
1142 ARMCPU
*cpu
= ARM_CPU(cs
);
1143 CPUARMState
*env
= &cpu
->env
;
1145 for (i
= 0; i
< 31; i
++) {
1146 reg
.id
= AARCH64_CORE_REG(regs
.regs
[i
]);
1147 reg
.addr
= (uintptr_t) &env
->xregs
[i
];
1148 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
1154 reg
.id
= AARCH64_CORE_REG(regs
.sp
);
1155 reg
.addr
= (uintptr_t) &env
->sp_el
[0];
1156 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
1161 reg
.id
= AARCH64_CORE_REG(sp_el1
);
1162 reg
.addr
= (uintptr_t) &env
->sp_el
[1];
1163 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
1168 reg
.id
= AARCH64_CORE_REG(regs
.pstate
);
1169 reg
.addr
= (uintptr_t) &val
;
1170 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
1175 env
->aarch64
= ((val
& PSTATE_nRW
) == 0);
1177 pstate_write(env
, val
);
1179 cpsr_write(env
, val
, 0xffffffff, CPSRWriteRaw
);
1182 /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the
1183 * QEMU side we keep the current SP in xregs[31] as well.
1185 aarch64_restore_sp(env
, 1);
1187 reg
.id
= AARCH64_CORE_REG(regs
.pc
);
1188 reg
.addr
= (uintptr_t) &env
->pc
;
1189 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
1194 /* If we are in AArch32 mode then we need to sync the AArch32 regs with the
1195 * incoming AArch64 regs received from 64-bit KVM.
1196 * We must perform this after all of the registers have been acquired from
1200 aarch64_sync_64_to_32(env
);
1203 reg
.id
= AARCH64_CORE_REG(elr_el1
);
1204 reg
.addr
= (uintptr_t) &env
->elr_el
[1];
1205 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
1210 /* Fetch the SPSR registers
1212 * KVM SPSRs 0-4 map to QEMU banks 1-5
1214 for (i
= 0; i
< KVM_NR_SPSR
; i
++) {
1215 reg
.id
= AARCH64_CORE_REG(spsr
[i
]);
1216 reg
.addr
= (uintptr_t) &env
->banked_spsr
[i
+ 1];
1217 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
1223 el
= arm_current_el(env
);
1224 if (el
> 0 && !is_a64(env
)) {
1225 i
= bank_number(env
->uncached_cpsr
& CPSR_M
);
1226 env
->spsr
= env
->banked_spsr
[i
];
1229 if (cpu_isar_feature(aa64_sve
, cpu
)) {
1230 ret
= kvm_arch_get_sve(cs
);
1232 ret
= kvm_arch_get_fpsimd(cs
);
1238 reg
.addr
= (uintptr_t)(&fpr
);
1239 reg
.id
= AARCH64_SIMD_CTRL_REG(fp_regs
.fpsr
);
1240 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
1244 vfp_set_fpsr(env
, fpr
);
1246 reg
.addr
= (uintptr_t)(&fpr
);
1247 reg
.id
= AARCH64_SIMD_CTRL_REG(fp_regs
.fpcr
);
1248 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
1252 vfp_set_fpcr(env
, fpr
);
1254 ret
= kvm_get_vcpu_events(cpu
);
1259 if (!write_kvmstate_to_list(cpu
)) {
1262 /* Note that it's OK to have registers which aren't in CPUState,
1263 * so we can ignore a failure return here.
1265 write_list_to_cpustate(cpu
);
1267 kvm_arm_sync_mpstate_to_qemu(cpu
);
1269 /* TODO: other registers */
1273 /* C6.6.29 BRK instruction */
1274 static const uint32_t brk_insn
= 0xd4200000;
1276 int kvm_arch_insert_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
1278 if (have_guest_debug
) {
1279 if (cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 4, 0) ||
1280 cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&brk_insn
, 4, 1)) {
1285 error_report("guest debug not supported on this kernel");
1290 int kvm_arch_remove_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
1292 static uint32_t brk
;
1294 if (have_guest_debug
) {
1295 if (cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&brk
, 4, 0) ||
1297 cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 4, 1)) {
1302 error_report("guest debug not supported on this kernel");
1307 /* See v8 ARM ARM D7.2.27 ESR_ELx, Exception Syndrome Register
1309 * To minimise translating between kernel and user-space the kernel
1310 * ABI just provides user-space with the full exception syndrome
1311 * register value to be decoded in QEMU.
1314 bool kvm_arm_handle_debug(CPUState
*cs
, struct kvm_debug_exit_arch
*debug_exit
)
1316 int hsr_ec
= syn_get_ec(debug_exit
->hsr
);
1317 ARMCPU
*cpu
= ARM_CPU(cs
);
1318 CPUClass
*cc
= CPU_GET_CLASS(cs
);
1319 CPUARMState
*env
= &cpu
->env
;
1321 /* Ensure PC is synchronised */
1322 kvm_cpu_synchronize_state(cs
);
1325 case EC_SOFTWARESTEP
:
1326 if (cs
->singlestep_enabled
) {
1330 * The kernel should have suppressed the guest's ability to
1331 * single step at this point so something has gone wrong.
1333 error_report("%s: guest single-step while debugging unsupported"
1334 " (%"PRIx64
", %"PRIx32
")",
1335 __func__
, env
->pc
, debug_exit
->hsr
);
1340 if (kvm_find_sw_breakpoint(cs
, env
->pc
)) {
1345 if (find_hw_breakpoint(cs
, env
->pc
)) {
1351 CPUWatchpoint
*wp
= find_hw_watchpoint(cs
, debug_exit
->far
);
1353 cs
->watchpoint_hit
= wp
;
1359 error_report("%s: unhandled debug exit (%"PRIx32
", %"PRIx64
")",
1360 __func__
, debug_exit
->hsr
, env
->pc
);
1363 /* If we are not handling the debug exception it must belong to
1364 * the guest. Let's re-use the existing TCG interrupt code to set
1365 * everything up properly.
1367 cs
->exception_index
= EXCP_BKPT
;
1368 env
->exception
.syndrome
= debug_exit
->hsr
;
1369 env
->exception
.vaddress
= debug_exit
->far
;
1370 env
->exception
.target_el
= 1;
1371 qemu_mutex_lock_iothread();
1372 cc
->do_interrupt(cs
);
1373 qemu_mutex_unlock_iothread();