4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
26 #include "translate.h"
27 #include "internals.h"
28 #include "qemu/host-utils.h"
30 #include "exec/semihost.h"
31 #include "exec/gen-icount.h"
33 #include "exec/helper-proto.h"
34 #include "exec/helper-gen.h"
37 #include "trace-tcg.h"
39 static TCGv_i64 cpu_X
[32];
40 static TCGv_i64 cpu_pc
;
42 /* Load/store exclusive handling */
43 static TCGv_i64 cpu_exclusive_high
;
44 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
);
46 static const char *regnames
[] = {
47 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
48 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
49 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
50 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
54 A64_SHIFT_TYPE_LSL
= 0,
55 A64_SHIFT_TYPE_LSR
= 1,
56 A64_SHIFT_TYPE_ASR
= 2,
57 A64_SHIFT_TYPE_ROR
= 3
60 /* Table based decoder typedefs - used when the relevant bits for decode
61 * are too awkwardly scattered across the instruction (eg SIMD).
63 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
65 typedef struct AArch64DecodeTable
{
68 AArch64DecodeFn
*disas_fn
;
71 /* Function prototype for gen_ functions for calling Neon helpers */
72 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
73 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
74 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
75 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
76 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
77 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
78 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
79 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
80 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
81 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
82 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
83 typedef void CryptoTwoOpEnvFn(TCGv_ptr
, TCGv_i32
, TCGv_i32
);
84 typedef void CryptoThreeOpEnvFn(TCGv_ptr
, TCGv_i32
, TCGv_i32
, TCGv_i32
);
86 /* initialize TCG globals. */
87 void a64_translate_init(void)
91 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
92 offsetof(CPUARMState
, pc
),
94 for (i
= 0; i
< 32; i
++) {
95 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
96 offsetof(CPUARMState
, xregs
[i
]),
100 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
101 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
104 static inline ARMMMUIdx
get_a64_user_mem_index(DisasContext
*s
)
106 /* Return the mmu_idx to use for A64 "unprivileged load/store" insns:
107 * if EL1, access as if EL0; otherwise access at current EL
109 switch (s
->mmu_idx
) {
110 case ARMMMUIdx_S12NSE1
:
111 return ARMMMUIdx_S12NSE0
;
112 case ARMMMUIdx_S1SE1
:
113 return ARMMMUIdx_S1SE0
;
115 g_assert_not_reached();
121 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
122 fprintf_function cpu_fprintf
, int flags
)
124 ARMCPU
*cpu
= ARM_CPU(cs
);
125 CPUARMState
*env
= &cpu
->env
;
126 uint32_t psr
= pstate_read(env
);
128 int el
= arm_current_el(env
);
129 const char *ns_status
;
131 cpu_fprintf(f
, "PC=%016"PRIx64
" SP=%016"PRIx64
"\n",
132 env
->pc
, env
->xregs
[31]);
133 for (i
= 0; i
< 31; i
++) {
134 cpu_fprintf(f
, "X%02d=%016"PRIx64
, i
, env
->xregs
[i
]);
136 cpu_fprintf(f
, "\n");
142 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
143 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
148 cpu_fprintf(f
, "\nPSTATE=%08x %c%c%c%c %sEL%d%c\n",
150 psr
& PSTATE_N
? 'N' : '-',
151 psr
& PSTATE_Z
? 'Z' : '-',
152 psr
& PSTATE_C
? 'C' : '-',
153 psr
& PSTATE_V
? 'V' : '-',
156 psr
& PSTATE_SP
? 'h' : 't');
158 if (flags
& CPU_DUMP_FPU
) {
160 for (i
= 0; i
< numvfpregs
; i
+= 2) {
161 uint64_t vlo
= float64_val(env
->vfp
.regs
[i
* 2]);
162 uint64_t vhi
= float64_val(env
->vfp
.regs
[(i
* 2) + 1]);
163 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
" ",
165 vlo
= float64_val(env
->vfp
.regs
[(i
+ 1) * 2]);
166 vhi
= float64_val(env
->vfp
.regs
[((i
+ 1) * 2) + 1]);
167 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
"\n",
170 cpu_fprintf(f
, "FPCR: %08x FPSR: %08x\n",
171 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
175 void gen_a64_set_pc_im(uint64_t val
)
177 tcg_gen_movi_i64(cpu_pc
, val
);
180 /* Load the PC from a generic TCG variable.
182 * If address tagging is enabled via the TCR TBI bits, then loading
183 * an address into the PC will clear out any tag in the it:
184 * + for EL2 and EL3 there is only one TBI bit, and if it is set
185 * then the address is zero-extended, clearing bits [63:56]
186 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
187 * and TBI1 controls addressses with bit 55 == 1.
188 * If the appropriate TBI bit is set for the address then
189 * the address is sign-extended from bit 55 into bits [63:56]
191 * We can avoid doing this for relative-branches, because the
192 * PC + offset can never overflow into the tag bits (assuming
193 * that virtual addresses are less than 56 bits wide, as they
194 * are currently), but we must handle it for branch-to-register.
196 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
199 if (s
->current_el
<= 1) {
200 /* Test if NEITHER or BOTH TBI values are set. If so, no need to
201 * examine bit 55 of address, can just generate code.
202 * If mixed, then test via generated code
204 if (s
->tbi0
&& s
->tbi1
) {
205 TCGv_i64 tmp_reg
= tcg_temp_new_i64();
206 /* Both bits set, sign extension from bit 55 into [63:56] will
209 tcg_gen_shli_i64(tmp_reg
, src
, 8);
210 tcg_gen_sari_i64(cpu_pc
, tmp_reg
, 8);
211 tcg_temp_free_i64(tmp_reg
);
212 } else if (!s
->tbi0
&& !s
->tbi1
) {
213 /* Neither bit set, just load it as-is */
214 tcg_gen_mov_i64(cpu_pc
, src
);
216 TCGv_i64 tcg_tmpval
= tcg_temp_new_i64();
217 TCGv_i64 tcg_bit55
= tcg_temp_new_i64();
218 TCGv_i64 tcg_zero
= tcg_const_i64(0);
220 tcg_gen_andi_i64(tcg_bit55
, src
, (1ull << 55));
223 /* tbi0==1, tbi1==0, so 0-fill upper byte if bit 55 = 0 */
224 tcg_gen_andi_i64(tcg_tmpval
, src
,
225 0x00FFFFFFFFFFFFFFull
);
226 tcg_gen_movcond_i64(TCG_COND_EQ
, cpu_pc
, tcg_bit55
, tcg_zero
,
229 /* tbi0==0, tbi1==1, so 1-fill upper byte if bit 55 = 1 */
230 tcg_gen_ori_i64(tcg_tmpval
, src
,
231 0xFF00000000000000ull
);
232 tcg_gen_movcond_i64(TCG_COND_NE
, cpu_pc
, tcg_bit55
, tcg_zero
,
235 tcg_temp_free_i64(tcg_zero
);
236 tcg_temp_free_i64(tcg_bit55
);
237 tcg_temp_free_i64(tcg_tmpval
);
239 } else { /* EL > 1 */
241 /* Force tag byte to all zero */
242 tcg_gen_andi_i64(cpu_pc
, src
, 0x00FFFFFFFFFFFFFFull
);
244 /* Load unmodified address */
245 tcg_gen_mov_i64(cpu_pc
, src
);
250 typedef struct DisasCompare64
{
255 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
259 arm_test_cc(&c32
, cc
);
261 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
262 * properly. The NE/EQ comparisons are also fine with this choice. */
263 c64
->cond
= c32
.cond
;
264 c64
->value
= tcg_temp_new_i64();
265 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
270 static void a64_free_cc(DisasCompare64
*c64
)
272 tcg_temp_free_i64(c64
->value
);
275 static void gen_exception_internal(int excp
)
277 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
279 assert(excp_is_internal(excp
));
280 gen_helper_exception_internal(cpu_env
, tcg_excp
);
281 tcg_temp_free_i32(tcg_excp
);
284 static void gen_exception(int excp
, uint32_t syndrome
, uint32_t target_el
)
286 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
287 TCGv_i32 tcg_syn
= tcg_const_i32(syndrome
);
288 TCGv_i32 tcg_el
= tcg_const_i32(target_el
);
290 gen_helper_exception_with_syndrome(cpu_env
, tcg_excp
,
292 tcg_temp_free_i32(tcg_el
);
293 tcg_temp_free_i32(tcg_syn
);
294 tcg_temp_free_i32(tcg_excp
);
297 static void gen_exception_internal_insn(DisasContext
*s
, int offset
, int excp
)
299 gen_a64_set_pc_im(s
->pc
- offset
);
300 gen_exception_internal(excp
);
301 s
->is_jmp
= DISAS_EXC
;
304 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
,
305 uint32_t syndrome
, uint32_t target_el
)
307 gen_a64_set_pc_im(s
->pc
- offset
);
308 gen_exception(excp
, syndrome
, target_el
);
309 s
->is_jmp
= DISAS_EXC
;
312 static void gen_ss_advance(DisasContext
*s
)
314 /* If the singlestep state is Active-not-pending, advance to
319 gen_helper_clear_pstate_ss(cpu_env
);
323 static void gen_step_complete_exception(DisasContext
*s
)
325 /* We just completed step of an insn. Move from Active-not-pending
326 * to Active-pending, and then also take the swstep exception.
327 * This corresponds to making the (IMPDEF) choice to prioritize
328 * swstep exceptions over asynchronous exceptions taken to an exception
329 * level where debug is disabled. This choice has the advantage that
330 * we do not need to maintain internal state corresponding to the
331 * ISV/EX syndrome bits between completion of the step and generation
332 * of the exception, and our syndrome information is always correct.
335 gen_exception(EXCP_UDEF
, syn_swstep(s
->ss_same_el
, 1, s
->is_ldex
),
336 default_exception_el(s
));
337 s
->is_jmp
= DISAS_EXC
;
340 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
342 /* No direct tb linking with singlestep (either QEMU's or the ARM
343 * debug architecture kind) or deterministic io
345 if (s
->singlestep_enabled
|| s
->ss_active
|| (s
->tb
->cflags
& CF_LAST_IO
)) {
349 #ifndef CONFIG_USER_ONLY
350 /* Only link tbs from inside the same guest page */
351 if ((s
->tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
359 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
361 TranslationBlock
*tb
;
364 if (use_goto_tb(s
, n
, dest
)) {
366 gen_a64_set_pc_im(dest
);
367 tcg_gen_exit_tb((intptr_t)tb
+ n
);
368 s
->is_jmp
= DISAS_TB_JUMP
;
370 gen_a64_set_pc_im(dest
);
372 gen_step_complete_exception(s
);
373 } else if (s
->singlestep_enabled
) {
374 gen_exception_internal(EXCP_DEBUG
);
377 s
->is_jmp
= DISAS_TB_JUMP
;
382 static void unallocated_encoding(DisasContext
*s
)
384 /* Unallocated and reserved encodings are uncategorized */
385 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(),
386 default_exception_el(s
));
389 #define unsupported_encoding(s, insn) \
391 qemu_log_mask(LOG_UNIMP, \
392 "%s:%d: unsupported instruction encoding 0x%08x " \
393 "at pc=%016" PRIx64 "\n", \
394 __FILE__, __LINE__, insn, s->pc - 4); \
395 unallocated_encoding(s); \
398 static void init_tmp_a64_array(DisasContext
*s
)
400 #ifdef CONFIG_DEBUG_TCG
402 for (i
= 0; i
< ARRAY_SIZE(s
->tmp_a64
); i
++) {
403 TCGV_UNUSED_I64(s
->tmp_a64
[i
]);
406 s
->tmp_a64_count
= 0;
409 static void free_tmp_a64(DisasContext
*s
)
412 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
413 tcg_temp_free_i64(s
->tmp_a64
[i
]);
415 init_tmp_a64_array(s
);
418 static TCGv_i64
new_tmp_a64(DisasContext
*s
)
420 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
421 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
424 static TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
426 TCGv_i64 t
= new_tmp_a64(s
);
427 tcg_gen_movi_i64(t
, 0);
432 * Register access functions
434 * These functions are used for directly accessing a register in where
435 * changes to the final register value are likely to be made. If you
436 * need to use a register for temporary calculation (e.g. index type
437 * operations) use the read_* form.
439 * B1.2.1 Register mappings
441 * In instruction register encoding 31 can refer to ZR (zero register) or
442 * the SP (stack pointer) depending on context. In QEMU's case we map SP
443 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
444 * This is the point of the _sp forms.
446 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
449 return new_tmp_a64_zero(s
);
455 /* register access for when 31 == SP */
456 static TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
461 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
462 * representing the register contents. This TCGv is an auto-freed
463 * temporary so it need not be explicitly freed, and may be modified.
465 static TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
467 TCGv_i64 v
= new_tmp_a64(s
);
470 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
472 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
475 tcg_gen_movi_i64(v
, 0);
480 static TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
482 TCGv_i64 v
= new_tmp_a64(s
);
484 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
486 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
491 /* We should have at some point before trying to access an FP register
492 * done the necessary access check, so assert that
493 * (a) we did the check and
494 * (b) we didn't then just plough ahead anyway if it failed.
495 * Print the instruction pattern in the abort message so we can figure
496 * out what we need to fix if a user encounters this problem in the wild.
498 static inline void assert_fp_access_checked(DisasContext
*s
)
500 #ifdef CONFIG_DEBUG_TCG
501 if (unlikely(!s
->fp_access_checked
|| s
->fp_excp_el
)) {
502 fprintf(stderr
, "target-arm: FP access check missing for "
503 "instruction 0x%08x\n", s
->insn
);
509 /* Return the offset into CPUARMState of an element of specified
510 * size, 'element' places in from the least significant end of
511 * the FP/vector register Qn.
513 static inline int vec_reg_offset(DisasContext
*s
, int regno
,
514 int element
, TCGMemOp size
)
517 #ifdef HOST_WORDS_BIGENDIAN
518 /* This is complicated slightly because vfp.regs[2n] is
519 * still the low half and vfp.regs[2n+1] the high half
520 * of the 128 bit vector, even on big endian systems.
521 * Calculate the offset assuming a fully bigendian 128 bits,
522 * then XOR to account for the order of the two 64 bit halves.
524 offs
+= (16 - ((element
+ 1) * (1 << size
)));
527 offs
+= element
* (1 << size
);
529 offs
+= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
530 assert_fp_access_checked(s
);
534 /* Return the offset into CPUARMState of a slice (from
535 * the least significant end) of FP register Qn (ie
537 * (Note that this is not the same mapping as for A32; see cpu.h)
539 static inline int fp_reg_offset(DisasContext
*s
, int regno
, TCGMemOp size
)
541 int offs
= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
542 #ifdef HOST_WORDS_BIGENDIAN
543 offs
+= (8 - (1 << size
));
545 assert_fp_access_checked(s
);
549 /* Offset of the high half of the 128 bit vector Qn */
550 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
552 assert_fp_access_checked(s
);
553 return offsetof(CPUARMState
, vfp
.regs
[regno
* 2 + 1]);
556 /* Convenience accessors for reading and writing single and double
557 * FP registers. Writing clears the upper parts of the associated
558 * 128 bit vector register, as required by the architecture.
559 * Note that unlike the GP register accessors, the values returned
560 * by the read functions must be manually freed.
562 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
564 TCGv_i64 v
= tcg_temp_new_i64();
566 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
570 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
572 TCGv_i32 v
= tcg_temp_new_i32();
574 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
578 static void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
580 TCGv_i64 tcg_zero
= tcg_const_i64(0);
582 tcg_gen_st_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
583 tcg_gen_st_i64(tcg_zero
, cpu_env
, fp_reg_hi_offset(s
, reg
));
584 tcg_temp_free_i64(tcg_zero
);
587 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
589 TCGv_i64 tmp
= tcg_temp_new_i64();
591 tcg_gen_extu_i32_i64(tmp
, v
);
592 write_fp_dreg(s
, reg
, tmp
);
593 tcg_temp_free_i64(tmp
);
596 static TCGv_ptr
get_fpstatus_ptr(void)
598 TCGv_ptr statusptr
= tcg_temp_new_ptr();
601 /* In A64 all instructions (both FP and Neon) use the FPCR;
602 * there is no equivalent of the A32 Neon "standard FPSCR value"
603 * and all operations use vfp.fp_status.
605 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
606 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
610 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
611 * than the 32 bit equivalent.
613 static inline void gen_set_NZ64(TCGv_i64 result
)
615 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
616 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
619 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
620 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
623 gen_set_NZ64(result
);
625 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
626 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
628 tcg_gen_movi_i32(cpu_CF
, 0);
629 tcg_gen_movi_i32(cpu_VF
, 0);
632 /* dest = T0 + T1; compute C, N, V and Z flags */
633 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
636 TCGv_i64 result
, flag
, tmp
;
637 result
= tcg_temp_new_i64();
638 flag
= tcg_temp_new_i64();
639 tmp
= tcg_temp_new_i64();
641 tcg_gen_movi_i64(tmp
, 0);
642 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
644 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
646 gen_set_NZ64(result
);
648 tcg_gen_xor_i64(flag
, result
, t0
);
649 tcg_gen_xor_i64(tmp
, t0
, t1
);
650 tcg_gen_andc_i64(flag
, flag
, tmp
);
651 tcg_temp_free_i64(tmp
);
652 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
654 tcg_gen_mov_i64(dest
, result
);
655 tcg_temp_free_i64(result
);
656 tcg_temp_free_i64(flag
);
658 /* 32 bit arithmetic */
659 TCGv_i32 t0_32
= tcg_temp_new_i32();
660 TCGv_i32 t1_32
= tcg_temp_new_i32();
661 TCGv_i32 tmp
= tcg_temp_new_i32();
663 tcg_gen_movi_i32(tmp
, 0);
664 tcg_gen_extrl_i64_i32(t0_32
, t0
);
665 tcg_gen_extrl_i64_i32(t1_32
, t1
);
666 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
667 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
668 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
669 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
670 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
671 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
673 tcg_temp_free_i32(tmp
);
674 tcg_temp_free_i32(t0_32
);
675 tcg_temp_free_i32(t1_32
);
679 /* dest = T0 - T1; compute C, N, V and Z flags */
680 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
683 /* 64 bit arithmetic */
684 TCGv_i64 result
, flag
, tmp
;
686 result
= tcg_temp_new_i64();
687 flag
= tcg_temp_new_i64();
688 tcg_gen_sub_i64(result
, t0
, t1
);
690 gen_set_NZ64(result
);
692 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
693 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
695 tcg_gen_xor_i64(flag
, result
, t0
);
696 tmp
= tcg_temp_new_i64();
697 tcg_gen_xor_i64(tmp
, t0
, t1
);
698 tcg_gen_and_i64(flag
, flag
, tmp
);
699 tcg_temp_free_i64(tmp
);
700 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
701 tcg_gen_mov_i64(dest
, result
);
702 tcg_temp_free_i64(flag
);
703 tcg_temp_free_i64(result
);
705 /* 32 bit arithmetic */
706 TCGv_i32 t0_32
= tcg_temp_new_i32();
707 TCGv_i32 t1_32
= tcg_temp_new_i32();
710 tcg_gen_extrl_i64_i32(t0_32
, t0
);
711 tcg_gen_extrl_i64_i32(t1_32
, t1
);
712 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
713 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
714 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
715 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
716 tmp
= tcg_temp_new_i32();
717 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
718 tcg_temp_free_i32(t0_32
);
719 tcg_temp_free_i32(t1_32
);
720 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
721 tcg_temp_free_i32(tmp
);
722 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
726 /* dest = T0 + T1 + CF; do not compute flags. */
727 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
729 TCGv_i64 flag
= tcg_temp_new_i64();
730 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
731 tcg_gen_add_i64(dest
, t0
, t1
);
732 tcg_gen_add_i64(dest
, dest
, flag
);
733 tcg_temp_free_i64(flag
);
736 tcg_gen_ext32u_i64(dest
, dest
);
740 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
741 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
744 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
745 result
= tcg_temp_new_i64();
746 cf_64
= tcg_temp_new_i64();
747 vf_64
= tcg_temp_new_i64();
748 tmp
= tcg_const_i64(0);
750 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
751 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
752 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
753 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
754 gen_set_NZ64(result
);
756 tcg_gen_xor_i64(vf_64
, result
, t0
);
757 tcg_gen_xor_i64(tmp
, t0
, t1
);
758 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
759 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
761 tcg_gen_mov_i64(dest
, result
);
763 tcg_temp_free_i64(tmp
);
764 tcg_temp_free_i64(vf_64
);
765 tcg_temp_free_i64(cf_64
);
766 tcg_temp_free_i64(result
);
768 TCGv_i32 t0_32
, t1_32
, tmp
;
769 t0_32
= tcg_temp_new_i32();
770 t1_32
= tcg_temp_new_i32();
771 tmp
= tcg_const_i32(0);
773 tcg_gen_extrl_i64_i32(t0_32
, t0
);
774 tcg_gen_extrl_i64_i32(t1_32
, t1
);
775 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
776 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
778 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
779 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
780 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
781 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
782 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
784 tcg_temp_free_i32(tmp
);
785 tcg_temp_free_i32(t1_32
);
786 tcg_temp_free_i32(t0_32
);
791 * Load/Store generators
795 * Store from GPR register to memory.
797 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
798 TCGv_i64 tcg_addr
, int size
, int memidx
,
800 unsigned int iss_srt
,
801 bool iss_sf
, bool iss_ar
)
804 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, s
->be_data
+ size
);
809 syn
= syn_data_abort_with_iss(0,
815 0, 0, 0, 0, 0, false);
816 disas_set_insn_syndrome(s
, syn
);
820 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
821 TCGv_i64 tcg_addr
, int size
,
823 unsigned int iss_srt
,
824 bool iss_sf
, bool iss_ar
)
826 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
),
827 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
831 * Load from memory to GPR register
833 static void do_gpr_ld_memidx(DisasContext
*s
,
834 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
835 int size
, bool is_signed
,
836 bool extend
, int memidx
,
837 bool iss_valid
, unsigned int iss_srt
,
838 bool iss_sf
, bool iss_ar
)
840 TCGMemOp memop
= s
->be_data
+ size
;
848 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
850 if (extend
&& is_signed
) {
852 tcg_gen_ext32u_i64(dest
, dest
);
858 syn
= syn_data_abort_with_iss(0,
864 0, 0, 0, 0, 0, false);
865 disas_set_insn_syndrome(s
, syn
);
869 static void do_gpr_ld(DisasContext
*s
,
870 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
871 int size
, bool is_signed
, bool extend
,
872 bool iss_valid
, unsigned int iss_srt
,
873 bool iss_sf
, bool iss_ar
)
875 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
877 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
881 * Store from FP register to memory
883 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
885 /* This writes the bottom N bits of a 128 bit wide vector to memory */
886 TCGv_i64 tmp
= tcg_temp_new_i64();
887 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
889 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
),
892 bool be
= s
->be_data
== MO_BE
;
893 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
895 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
896 tcg_gen_qemu_st_i64(tmp
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
898 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
899 tcg_gen_qemu_st_i64(tmp
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
901 tcg_temp_free_i64(tcg_hiaddr
);
904 tcg_temp_free_i64(tmp
);
908 * Load from memory to FP register
910 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
912 /* This always zero-extends and writes to a full 128 bit wide vector */
913 TCGv_i64 tmplo
= tcg_temp_new_i64();
917 TCGMemOp memop
= s
->be_data
+ size
;
918 tmphi
= tcg_const_i64(0);
919 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
921 bool be
= s
->be_data
== MO_BE
;
924 tmphi
= tcg_temp_new_i64();
925 tcg_hiaddr
= tcg_temp_new_i64();
927 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
928 tcg_gen_qemu_ld_i64(tmplo
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
930 tcg_gen_qemu_ld_i64(tmphi
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
932 tcg_temp_free_i64(tcg_hiaddr
);
935 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
936 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
938 tcg_temp_free_i64(tmplo
);
939 tcg_temp_free_i64(tmphi
);
943 * Vector load/store helpers.
945 * The principal difference between this and a FP load is that we don't
946 * zero extend as we are filling a partial chunk of the vector register.
947 * These functions don't support 128 bit loads/stores, which would be
948 * normal load/store operations.
950 * The _i32 versions are useful when operating on 32 bit quantities
951 * (eg for floating point single or using Neon helper functions).
954 /* Get value of an element within a vector register */
955 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
956 int element
, TCGMemOp memop
)
958 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
961 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
964 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
967 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
970 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
973 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
976 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
980 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
983 g_assert_not_reached();
987 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
988 int element
, TCGMemOp memop
)
990 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
993 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
996 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
999 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1002 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1006 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1009 g_assert_not_reached();
1013 /* Set value of an element within a vector register */
1014 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1015 int element
, TCGMemOp memop
)
1017 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1020 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1023 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1026 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1029 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1032 g_assert_not_reached();
1036 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1037 int destidx
, int element
, TCGMemOp memop
)
1039 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1042 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1045 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1048 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1051 g_assert_not_reached();
1055 /* Clear the high 64 bits of a 128 bit vector (in general non-quad
1056 * vector ops all need to do this).
1058 static void clear_vec_high(DisasContext
*s
, int rd
)
1060 TCGv_i64 tcg_zero
= tcg_const_i64(0);
1062 write_vec_element(s
, tcg_zero
, rd
, 1, MO_64
);
1063 tcg_temp_free_i64(tcg_zero
);
1066 /* Store from vector register to memory */
1067 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1068 TCGv_i64 tcg_addr
, int size
)
1070 TCGMemOp memop
= s
->be_data
+ size
;
1071 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1073 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
1074 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
1076 tcg_temp_free_i64(tcg_tmp
);
1079 /* Load from memory to vector register */
1080 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1081 TCGv_i64 tcg_addr
, int size
)
1083 TCGMemOp memop
= s
->be_data
+ size
;
1084 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1086 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
1087 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
1089 tcg_temp_free_i64(tcg_tmp
);
1092 /* Check that FP/Neon access is enabled. If it is, return
1093 * true. If not, emit code to generate an appropriate exception,
1094 * and return false; the caller should not emit any code for
1095 * the instruction. Note that this check must happen after all
1096 * unallocated-encoding checks (otherwise the syndrome information
1097 * for the resulting exception will be incorrect).
1099 static inline bool fp_access_check(DisasContext
*s
)
1101 assert(!s
->fp_access_checked
);
1102 s
->fp_access_checked
= true;
1104 if (!s
->fp_excp_el
) {
1108 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_fp_access_trap(1, 0xe, false),
1114 * This utility function is for doing register extension with an
1115 * optional shift. You will likely want to pass a temporary for the
1116 * destination register. See DecodeRegExtend() in the ARM ARM.
1118 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1119 int option
, unsigned int shift
)
1121 int extsize
= extract32(option
, 0, 2);
1122 bool is_signed
= extract32(option
, 2, 1);
1127 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1130 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1133 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1136 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1142 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1145 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1148 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1151 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1157 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1161 static inline void gen_check_sp_alignment(DisasContext
*s
)
1163 /* The AArch64 architecture mandates that (if enabled via PSTATE
1164 * or SCTLR bits) there is a check that SP is 16-aligned on every
1165 * SP-relative load or store (with an exception generated if it is not).
1166 * In line with general QEMU practice regarding misaligned accesses,
1167 * we omit these checks for the sake of guest program performance.
1168 * This function is provided as a hook so we can more easily add these
1169 * checks in future (possibly as a "favour catching guest program bugs
1170 * over speed" user selectable option).
1175 * This provides a simple table based table lookup decoder. It is
1176 * intended to be used when the relevant bits for decode are too
1177 * awkwardly placed and switch/if based logic would be confusing and
1178 * deeply nested. Since it's a linear search through the table, tables
1179 * should be kept small.
1181 * It returns the first handler where insn & mask == pattern, or
1182 * NULL if there is no match.
1183 * The table is terminated by an empty mask (i.e. 0)
1185 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1188 const AArch64DecodeTable
*tptr
= table
;
1190 while (tptr
->mask
) {
1191 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1192 return tptr
->disas_fn
;
1200 * the instruction disassembly implemented here matches
1201 * the instruction encoding classifications in chapter 3 (C3)
1202 * of the ARM Architecture Reference Manual (DDI0487A_a)
1205 /* C3.2.7 Unconditional branch (immediate)
1207 * +----+-----------+-------------------------------------+
1208 * | op | 0 0 1 0 1 | imm26 |
1209 * +----+-----------+-------------------------------------+
1211 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1213 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
1215 if (insn
& (1U << 31)) {
1216 /* C5.6.26 BL Branch with link */
1217 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1220 /* C5.6.20 B Branch / C5.6.26 BL Branch with link */
1221 gen_goto_tb(s
, 0, addr
);
1224 /* C3.2.1 Compare & branch (immediate)
1225 * 31 30 25 24 23 5 4 0
1226 * +----+-------------+----+---------------------+--------+
1227 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1228 * +----+-------------+----+---------------------+--------+
1230 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1232 unsigned int sf
, op
, rt
;
1234 TCGLabel
*label_match
;
1237 sf
= extract32(insn
, 31, 1);
1238 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1239 rt
= extract32(insn
, 0, 5);
1240 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1242 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1243 label_match
= gen_new_label();
1245 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1246 tcg_cmp
, 0, label_match
);
1248 gen_goto_tb(s
, 0, s
->pc
);
1249 gen_set_label(label_match
);
1250 gen_goto_tb(s
, 1, addr
);
1253 /* C3.2.5 Test & branch (immediate)
1254 * 31 30 25 24 23 19 18 5 4 0
1255 * +----+-------------+----+-------+-------------+------+
1256 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1257 * +----+-------------+----+-------+-------------+------+
1259 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1261 unsigned int bit_pos
, op
, rt
;
1263 TCGLabel
*label_match
;
1266 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1267 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1268 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
1269 rt
= extract32(insn
, 0, 5);
1271 tcg_cmp
= tcg_temp_new_i64();
1272 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1273 label_match
= gen_new_label();
1274 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1275 tcg_cmp
, 0, label_match
);
1276 tcg_temp_free_i64(tcg_cmp
);
1277 gen_goto_tb(s
, 0, s
->pc
);
1278 gen_set_label(label_match
);
1279 gen_goto_tb(s
, 1, addr
);
1282 /* C3.2.2 / C5.6.19 Conditional branch (immediate)
1283 * 31 25 24 23 5 4 3 0
1284 * +---------------+----+---------------------+----+------+
1285 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1286 * +---------------+----+---------------------+----+------+
1288 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1293 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1294 unallocated_encoding(s
);
1297 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1298 cond
= extract32(insn
, 0, 4);
1301 /* genuinely conditional branches */
1302 TCGLabel
*label_match
= gen_new_label();
1303 arm_gen_test_cc(cond
, label_match
);
1304 gen_goto_tb(s
, 0, s
->pc
);
1305 gen_set_label(label_match
);
1306 gen_goto_tb(s
, 1, addr
);
1308 /* 0xe and 0xf are both "always" conditions */
1309 gen_goto_tb(s
, 0, addr
);
1314 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1315 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1317 unsigned int selector
= crm
<< 3 | op2
;
1320 unallocated_encoding(s
);
1328 s
->is_jmp
= DISAS_WFI
;
1331 if (!parallel_cpus
) {
1332 s
->is_jmp
= DISAS_YIELD
;
1336 if (!parallel_cpus
) {
1337 s
->is_jmp
= DISAS_WFE
;
1342 /* we treat all as NOP at least for now */
1345 /* default specified as NOP equivalent */
1350 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1352 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1355 /* CLREX, DSB, DMB, ISB */
1356 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1357 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1362 unallocated_encoding(s
);
1373 case 1: /* MBReqTypes_Reads */
1374 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1376 case 2: /* MBReqTypes_Writes */
1377 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1379 default: /* MBReqTypes_All */
1380 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1386 /* We need to break the TB after this insn to execute
1387 * a self-modified code correctly and also to take
1388 * any pending interrupts immediately.
1390 s
->is_jmp
= DISAS_UPDATE
;
1393 unallocated_encoding(s
);
1398 /* C5.6.130 MSR (immediate) - move immediate to processor state field */
1399 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1400 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1402 int op
= op1
<< 3 | op2
;
1404 case 0x05: /* SPSel */
1405 if (s
->current_el
== 0) {
1406 unallocated_encoding(s
);
1410 case 0x1e: /* DAIFSet */
1411 case 0x1f: /* DAIFClear */
1413 TCGv_i32 tcg_imm
= tcg_const_i32(crm
);
1414 TCGv_i32 tcg_op
= tcg_const_i32(op
);
1415 gen_a64_set_pc_im(s
->pc
- 4);
1416 gen_helper_msr_i_pstate(cpu_env
, tcg_op
, tcg_imm
);
1417 tcg_temp_free_i32(tcg_imm
);
1418 tcg_temp_free_i32(tcg_op
);
1419 s
->is_jmp
= DISAS_UPDATE
;
1423 unallocated_encoding(s
);
1428 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1430 TCGv_i32 tmp
= tcg_temp_new_i32();
1431 TCGv_i32 nzcv
= tcg_temp_new_i32();
1433 /* build bit 31, N */
1434 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1435 /* build bit 30, Z */
1436 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1437 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1438 /* build bit 29, C */
1439 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1440 /* build bit 28, V */
1441 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1442 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1443 /* generate result */
1444 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1446 tcg_temp_free_i32(nzcv
);
1447 tcg_temp_free_i32(tmp
);
1450 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1453 TCGv_i32 nzcv
= tcg_temp_new_i32();
1455 /* take NZCV from R[t] */
1456 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1459 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1461 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1462 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1464 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1465 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1467 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1468 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1469 tcg_temp_free_i32(nzcv
);
1472 /* C5.6.129 MRS - move from system register
1473 * C5.6.131 MSR (register) - move to system register
1476 * These are all essentially the same insn in 'read' and 'write'
1477 * versions, with varying op0 fields.
1479 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1480 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1481 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1483 const ARMCPRegInfo
*ri
;
1486 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1487 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1488 crn
, crm
, op0
, op1
, op2
));
1491 /* Unknown register; this might be a guest error or a QEMU
1492 * unimplemented feature.
1494 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1495 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1496 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1497 unallocated_encoding(s
);
1501 /* Check access permissions */
1502 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1503 unallocated_encoding(s
);
1508 /* Emit code to perform further access permissions checks at
1509 * runtime; this may result in an exception.
1512 TCGv_i32 tcg_syn
, tcg_isread
;
1515 gen_a64_set_pc_im(s
->pc
- 4);
1516 tmpptr
= tcg_const_ptr(ri
);
1517 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1518 tcg_syn
= tcg_const_i32(syndrome
);
1519 tcg_isread
= tcg_const_i32(isread
);
1520 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1521 tcg_temp_free_ptr(tmpptr
);
1522 tcg_temp_free_i32(tcg_syn
);
1523 tcg_temp_free_i32(tcg_isread
);
1526 /* Handle special cases first */
1527 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1531 tcg_rt
= cpu_reg(s
, rt
);
1533 gen_get_nzcv(tcg_rt
);
1535 gen_set_nzcv(tcg_rt
);
1538 case ARM_CP_CURRENTEL
:
1539 /* Reads as current EL value from pstate, which is
1540 * guaranteed to be constant by the tb flags.
1542 tcg_rt
= cpu_reg(s
, rt
);
1543 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1546 /* Writes clear the aligned block of memory which rt points into. */
1547 tcg_rt
= cpu_reg(s
, rt
);
1548 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1554 if ((s
->tb
->cflags
& CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1558 tcg_rt
= cpu_reg(s
, rt
);
1561 if (ri
->type
& ARM_CP_CONST
) {
1562 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1563 } else if (ri
->readfn
) {
1565 tmpptr
= tcg_const_ptr(ri
);
1566 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1567 tcg_temp_free_ptr(tmpptr
);
1569 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1572 if (ri
->type
& ARM_CP_CONST
) {
1573 /* If not forbidden by access permissions, treat as WI */
1575 } else if (ri
->writefn
) {
1577 tmpptr
= tcg_const_ptr(ri
);
1578 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1579 tcg_temp_free_ptr(tmpptr
);
1581 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1585 if ((s
->tb
->cflags
& CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1586 /* I/O operations must end the TB here (whether read or write) */
1588 s
->is_jmp
= DISAS_UPDATE
;
1589 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1590 /* We default to ending the TB on a coprocessor register write,
1591 * but allow this to be suppressed by the register definition
1592 * (usually only necessary to work around guest bugs).
1594 s
->is_jmp
= DISAS_UPDATE
;
1599 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1600 * +---------------------+---+-----+-----+-------+-------+-----+------+
1601 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1602 * +---------------------+---+-----+-----+-------+-------+-----+------+
1604 static void disas_system(DisasContext
*s
, uint32_t insn
)
1606 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1607 l
= extract32(insn
, 21, 1);
1608 op0
= extract32(insn
, 19, 2);
1609 op1
= extract32(insn
, 16, 3);
1610 crn
= extract32(insn
, 12, 4);
1611 crm
= extract32(insn
, 8, 4);
1612 op2
= extract32(insn
, 5, 3);
1613 rt
= extract32(insn
, 0, 5);
1616 if (l
|| rt
!= 31) {
1617 unallocated_encoding(s
);
1621 case 2: /* C5.6.68 HINT */
1622 handle_hint(s
, insn
, op1
, op2
, crm
);
1624 case 3: /* CLREX, DSB, DMB, ISB */
1625 handle_sync(s
, insn
, op1
, op2
, crm
);
1627 case 4: /* C5.6.130 MSR (immediate) */
1628 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1631 unallocated_encoding(s
);
1636 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1639 /* C3.2.3 Exception generation
1641 * 31 24 23 21 20 5 4 2 1 0
1642 * +-----------------+-----+------------------------+-----+----+
1643 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1644 * +-----------------------+------------------------+----------+
1646 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1648 int opc
= extract32(insn
, 21, 3);
1649 int op2_ll
= extract32(insn
, 0, 5);
1650 int imm16
= extract32(insn
, 5, 16);
1655 /* For SVC, HVC and SMC we advance the single-step state
1656 * machine before taking the exception. This is architecturally
1657 * mandated, to ensure that single-stepping a system call
1658 * instruction works properly.
1663 gen_exception_insn(s
, 0, EXCP_SWI
, syn_aa64_svc(imm16
),
1664 default_exception_el(s
));
1667 if (s
->current_el
== 0) {
1668 unallocated_encoding(s
);
1671 /* The pre HVC helper handles cases when HVC gets trapped
1672 * as an undefined insn by runtime configuration.
1674 gen_a64_set_pc_im(s
->pc
- 4);
1675 gen_helper_pre_hvc(cpu_env
);
1677 gen_exception_insn(s
, 0, EXCP_HVC
, syn_aa64_hvc(imm16
), 2);
1680 if (s
->current_el
== 0) {
1681 unallocated_encoding(s
);
1684 gen_a64_set_pc_im(s
->pc
- 4);
1685 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
1686 gen_helper_pre_smc(cpu_env
, tmp
);
1687 tcg_temp_free_i32(tmp
);
1689 gen_exception_insn(s
, 0, EXCP_SMC
, syn_aa64_smc(imm16
), 3);
1692 unallocated_encoding(s
);
1698 unallocated_encoding(s
);
1702 gen_exception_insn(s
, 4, EXCP_BKPT
, syn_aa64_bkpt(imm16
),
1703 default_exception_el(s
));
1707 unallocated_encoding(s
);
1710 /* HLT. This has two purposes.
1711 * Architecturally, it is an external halting debug instruction.
1712 * Since QEMU doesn't implement external debug, we treat this as
1713 * it is required for halting debug disabled: it will UNDEF.
1714 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
1716 if (semihosting_enabled() && imm16
== 0xf000) {
1717 #ifndef CONFIG_USER_ONLY
1718 /* In system mode, don't allow userspace access to semihosting,
1719 * to provide some semblance of security (and for consistency
1720 * with our 32-bit semihosting).
1722 if (s
->current_el
== 0) {
1723 unsupported_encoding(s
, insn
);
1727 gen_exception_internal_insn(s
, 0, EXCP_SEMIHOST
);
1729 unsupported_encoding(s
, insn
);
1733 if (op2_ll
< 1 || op2_ll
> 3) {
1734 unallocated_encoding(s
);
1737 /* DCPS1, DCPS2, DCPS3 */
1738 unsupported_encoding(s
, insn
);
1741 unallocated_encoding(s
);
1746 /* C3.2.7 Unconditional branch (register)
1747 * 31 25 24 21 20 16 15 10 9 5 4 0
1748 * +---------------+-------+-------+-------+------+-------+
1749 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1750 * +---------------+-------+-------+-------+------+-------+
1752 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
1754 unsigned int opc
, op2
, op3
, rn
, op4
;
1756 opc
= extract32(insn
, 21, 4);
1757 op2
= extract32(insn
, 16, 5);
1758 op3
= extract32(insn
, 10, 6);
1759 rn
= extract32(insn
, 5, 5);
1760 op4
= extract32(insn
, 0, 5);
1762 if (op4
!= 0x0 || op3
!= 0x0 || op2
!= 0x1f) {
1763 unallocated_encoding(s
);
1771 gen_a64_set_pc(s
, cpu_reg(s
, rn
));
1772 /* BLR also needs to load return address */
1774 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1778 if (s
->current_el
== 0) {
1779 unallocated_encoding(s
);
1782 gen_helper_exception_return(cpu_env
);
1783 s
->is_jmp
= DISAS_JUMP
;
1787 unallocated_encoding(s
);
1789 unsupported_encoding(s
, insn
);
1793 unallocated_encoding(s
);
1797 s
->is_jmp
= DISAS_JUMP
;
1800 /* C3.2 Branches, exception generating and system instructions */
1801 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
1803 switch (extract32(insn
, 25, 7)) {
1804 case 0x0a: case 0x0b:
1805 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
1806 disas_uncond_b_imm(s
, insn
);
1808 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
1809 disas_comp_b_imm(s
, insn
);
1811 case 0x1b: case 0x5b: /* Test & branch (immediate) */
1812 disas_test_b_imm(s
, insn
);
1814 case 0x2a: /* Conditional branch (immediate) */
1815 disas_cond_b_imm(s
, insn
);
1817 case 0x6a: /* Exception generation / System */
1818 if (insn
& (1 << 24)) {
1819 disas_system(s
, insn
);
1824 case 0x6b: /* Unconditional branch (register) */
1825 disas_uncond_b_reg(s
, insn
);
1828 unallocated_encoding(s
);
1834 * Load/Store exclusive instructions are implemented by remembering
1835 * the value/address loaded, and seeing if these are the same
1836 * when the store is performed. This is not actually the architecturally
1837 * mandated semantics, but it works for typical guest code sequences
1838 * and avoids having to monitor regular stores.
1840 * The store exclusive uses the atomic cmpxchg primitives to avoid
1841 * races in multi-threaded linux-user and when MTTCG softmmu is
1844 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
1845 TCGv_i64 addr
, int size
, bool is_pair
)
1847 TCGv_i64 tmp
= tcg_temp_new_i64();
1848 TCGMemOp memop
= s
->be_data
+ size
;
1850 g_assert(size
<= 3);
1851 tcg_gen_qemu_ld_i64(tmp
, addr
, get_mem_index(s
), memop
);
1854 TCGv_i64 addr2
= tcg_temp_new_i64();
1855 TCGv_i64 hitmp
= tcg_temp_new_i64();
1857 g_assert(size
>= 2);
1858 tcg_gen_addi_i64(addr2
, addr
, 1 << size
);
1859 tcg_gen_qemu_ld_i64(hitmp
, addr2
, get_mem_index(s
), memop
);
1860 tcg_temp_free_i64(addr2
);
1861 tcg_gen_mov_i64(cpu_exclusive_high
, hitmp
);
1862 tcg_gen_mov_i64(cpu_reg(s
, rt2
), hitmp
);
1863 tcg_temp_free_i64(hitmp
);
1866 tcg_gen_mov_i64(cpu_exclusive_val
, tmp
);
1867 tcg_gen_mov_i64(cpu_reg(s
, rt
), tmp
);
1869 tcg_temp_free_i64(tmp
);
1870 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
1873 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1874 TCGv_i64 inaddr
, int size
, int is_pair
)
1876 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
1877 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
1880 * [addr + datasize] = {Rt2};
1886 * env->exclusive_addr = -1;
1888 TCGLabel
*fail_label
= gen_new_label();
1889 TCGLabel
*done_label
= gen_new_label();
1890 TCGv_i64 addr
= tcg_temp_local_new_i64();
1893 /* Copy input into a local temp so it is not trashed when the
1894 * basic block ends at the branch insn.
1896 tcg_gen_mov_i64(addr
, inaddr
);
1897 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
1899 tmp
= tcg_temp_new_i64();
1902 TCGv_i64 val
= tcg_temp_new_i64();
1903 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
1904 tcg_gen_concat32_i64(val
, cpu_exclusive_val
, cpu_exclusive_high
);
1905 tcg_gen_atomic_cmpxchg_i64(tmp
, addr
, val
, tmp
,
1907 size
| MO_ALIGN
| s
->be_data
);
1908 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, val
);
1909 tcg_temp_free_i64(val
);
1910 } else if (s
->be_data
== MO_LE
) {
1911 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, addr
, cpu_reg(s
, rt
),
1914 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, addr
, cpu_reg(s
, rt
),
1918 TCGv_i64 val
= cpu_reg(s
, rt
);
1919 tcg_gen_atomic_cmpxchg_i64(tmp
, addr
, cpu_exclusive_val
, val
,
1921 size
| MO_ALIGN
| s
->be_data
);
1922 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
1925 tcg_temp_free_i64(addr
);
1927 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
1928 tcg_temp_free_i64(tmp
);
1929 tcg_gen_br(done_label
);
1931 gen_set_label(fail_label
);
1932 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
1933 gen_set_label(done_label
);
1934 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1937 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
1938 * from the ARMv8 specs for LDR (Shared decode for all encodings).
1940 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
1942 int opc0
= extract32(opc
, 0, 1);
1946 regsize
= opc0
? 32 : 64;
1948 regsize
= size
== 3 ? 64 : 32;
1950 return regsize
== 64;
1953 /* C3.3.6 Load/store exclusive
1955 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
1956 * +-----+-------------+----+---+----+------+----+-------+------+------+
1957 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
1958 * +-----+-------------+----+---+----+------+----+-------+------+------+
1960 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
1961 * L: 0 -> store, 1 -> load
1962 * o2: 0 -> exclusive, 1 -> not
1963 * o1: 0 -> single register, 1 -> register pair
1964 * o0: 1 -> load-acquire/store-release, 0 -> not
1966 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
1968 int rt
= extract32(insn
, 0, 5);
1969 int rn
= extract32(insn
, 5, 5);
1970 int rt2
= extract32(insn
, 10, 5);
1971 int is_lasr
= extract32(insn
, 15, 1);
1972 int rs
= extract32(insn
, 16, 5);
1973 int is_pair
= extract32(insn
, 21, 1);
1974 int is_store
= !extract32(insn
, 22, 1);
1975 int is_excl
= !extract32(insn
, 23, 1);
1976 int size
= extract32(insn
, 30, 2);
1979 if ((!is_excl
&& !is_pair
&& !is_lasr
) ||
1980 (!is_excl
&& is_pair
) ||
1981 (is_pair
&& size
< 2)) {
1982 unallocated_encoding(s
);
1987 gen_check_sp_alignment(s
);
1989 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
1991 /* Note that since TCG is single threaded load-acquire/store-release
1992 * semantics require no extra if (is_lasr) { ... } handling.
1998 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, is_pair
);
2000 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2004 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2006 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, is_pair
);
2009 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2010 bool iss_sf
= disas_ldst_compute_iss_sf(size
, false, 0);
2012 /* Generate ISS for non-exclusive accesses including LASR. */
2015 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2017 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2018 true, rt
, iss_sf
, is_lasr
);
2020 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, false, false,
2021 true, rt
, iss_sf
, is_lasr
);
2023 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2030 * C3.3.5 Load register (literal)
2032 * 31 30 29 27 26 25 24 23 5 4 0
2033 * +-----+-------+---+-----+-------------------+-------+
2034 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2035 * +-----+-------+---+-----+-------------------+-------+
2037 * V: 1 -> vector (simd/fp)
2038 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2039 * 10-> 32 bit signed, 11 -> prefetch
2040 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2042 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2044 int rt
= extract32(insn
, 0, 5);
2045 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2046 bool is_vector
= extract32(insn
, 26, 1);
2047 int opc
= extract32(insn
, 30, 2);
2048 bool is_signed
= false;
2050 TCGv_i64 tcg_rt
, tcg_addr
;
2054 unallocated_encoding(s
);
2058 if (!fp_access_check(s
)) {
2063 /* PRFM (literal) : prefetch */
2066 size
= 2 + extract32(opc
, 0, 1);
2067 is_signed
= extract32(opc
, 1, 1);
2070 tcg_rt
= cpu_reg(s
, rt
);
2072 tcg_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
2074 do_fp_ld(s
, rt
, tcg_addr
, size
);
2076 /* Only unsigned 32bit loads target 32bit registers. */
2077 bool iss_sf
= opc
!= 0;
2079 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false,
2080 true, rt
, iss_sf
, false);
2082 tcg_temp_free_i64(tcg_addr
);
2086 * C5.6.80 LDNP (Load Pair - non-temporal hint)
2087 * C5.6.81 LDP (Load Pair - non vector)
2088 * C5.6.82 LDPSW (Load Pair Signed Word - non vector)
2089 * C5.6.176 STNP (Store Pair - non-temporal hint)
2090 * C5.6.177 STP (Store Pair - non vector)
2091 * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
2092 * C6.3.165 LDP (Load Pair of SIMD&FP)
2093 * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
2094 * C6.3.284 STP (Store Pair of SIMD&FP)
2096 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2097 * +-----+-------+---+---+-------+---+-----------------------------+
2098 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2099 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2101 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2103 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2104 * V: 0 -> GPR, 1 -> Vector
2105 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2106 * 10 -> signed offset, 11 -> pre-index
2107 * L: 0 -> Store 1 -> Load
2109 * Rt, Rt2 = GPR or SIMD registers to be stored
2110 * Rn = general purpose register containing address
2111 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2113 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2115 int rt
= extract32(insn
, 0, 5);
2116 int rn
= extract32(insn
, 5, 5);
2117 int rt2
= extract32(insn
, 10, 5);
2118 uint64_t offset
= sextract64(insn
, 15, 7);
2119 int index
= extract32(insn
, 23, 2);
2120 bool is_vector
= extract32(insn
, 26, 1);
2121 bool is_load
= extract32(insn
, 22, 1);
2122 int opc
= extract32(insn
, 30, 2);
2124 bool is_signed
= false;
2125 bool postindex
= false;
2128 TCGv_i64 tcg_addr
; /* calculated address */
2132 unallocated_encoding(s
);
2139 size
= 2 + extract32(opc
, 1, 1);
2140 is_signed
= extract32(opc
, 0, 1);
2141 if (!is_load
&& is_signed
) {
2142 unallocated_encoding(s
);
2148 case 1: /* post-index */
2153 /* signed offset with "non-temporal" hint. Since we don't emulate
2154 * caches we don't care about hints to the cache system about
2155 * data access patterns, and handle this identically to plain
2159 /* There is no non-temporal-hint version of LDPSW */
2160 unallocated_encoding(s
);
2165 case 2: /* signed offset, rn not updated */
2168 case 3: /* pre-index */
2174 if (is_vector
&& !fp_access_check(s
)) {
2181 gen_check_sp_alignment(s
);
2184 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2187 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2192 do_fp_ld(s
, rt
, tcg_addr
, size
);
2194 do_fp_st(s
, rt
, tcg_addr
, size
);
2196 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2198 do_fp_ld(s
, rt2
, tcg_addr
, size
);
2200 do_fp_st(s
, rt2
, tcg_addr
, size
);
2203 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2204 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2207 TCGv_i64 tmp
= tcg_temp_new_i64();
2209 /* Do not modify tcg_rt before recognizing any exception
2210 * from the second load.
2212 do_gpr_ld(s
, tmp
, tcg_addr
, size
, is_signed
, false,
2213 false, 0, false, false);
2214 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2215 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, is_signed
, false,
2216 false, 0, false, false);
2218 tcg_gen_mov_i64(tcg_rt
, tmp
);
2219 tcg_temp_free_i64(tmp
);
2221 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2222 false, 0, false, false);
2223 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2224 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
,
2225 false, 0, false, false);
2231 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
- (1 << size
));
2233 tcg_gen_subi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2235 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), tcg_addr
);
2240 * C3.3.8 Load/store (immediate post-indexed)
2241 * C3.3.9 Load/store (immediate pre-indexed)
2242 * C3.3.12 Load/store (unscaled immediate)
2244 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2245 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2246 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2247 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2249 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2251 * V = 0 -> non-vector
2252 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2253 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2255 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
2261 int rn
= extract32(insn
, 5, 5);
2262 int imm9
= sextract32(insn
, 12, 9);
2263 int idx
= extract32(insn
, 10, 2);
2264 bool is_signed
= false;
2265 bool is_store
= false;
2266 bool is_extended
= false;
2267 bool is_unpriv
= (idx
== 2);
2268 bool iss_valid
= !is_vector
;
2275 size
|= (opc
& 2) << 1;
2276 if (size
> 4 || is_unpriv
) {
2277 unallocated_encoding(s
);
2280 is_store
= ((opc
& 1) == 0);
2281 if (!fp_access_check(s
)) {
2285 if (size
== 3 && opc
== 2) {
2286 /* PRFM - prefetch */
2288 unallocated_encoding(s
);
2293 if (opc
== 3 && size
> 1) {
2294 unallocated_encoding(s
);
2297 is_store
= (opc
== 0);
2298 is_signed
= extract32(opc
, 1, 1);
2299 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2319 gen_check_sp_alignment(s
);
2321 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2324 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2329 do_fp_st(s
, rt
, tcg_addr
, size
);
2331 do_fp_ld(s
, rt
, tcg_addr
, size
);
2334 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2335 int memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
2336 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2339 do_gpr_st_memidx(s
, tcg_rt
, tcg_addr
, size
, memidx
,
2340 iss_valid
, rt
, iss_sf
, false);
2342 do_gpr_ld_memidx(s
, tcg_rt
, tcg_addr
, size
,
2343 is_signed
, is_extended
, memidx
,
2344 iss_valid
, rt
, iss_sf
, false);
2349 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2351 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2353 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2358 * C3.3.10 Load/store (register offset)
2360 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2361 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2362 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2363 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2366 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2367 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2369 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2370 * opc<0>: 0 -> store, 1 -> load
2371 * V: 1 -> vector/simd
2372 * opt: extend encoding (see DecodeRegExtend)
2373 * S: if S=1 then scale (essentially index by sizeof(size))
2374 * Rt: register to transfer into/out of
2375 * Rn: address register or SP for base
2376 * Rm: offset register or ZR for offset
2378 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
2384 int rn
= extract32(insn
, 5, 5);
2385 int shift
= extract32(insn
, 12, 1);
2386 int rm
= extract32(insn
, 16, 5);
2387 int opt
= extract32(insn
, 13, 3);
2388 bool is_signed
= false;
2389 bool is_store
= false;
2390 bool is_extended
= false;
2395 if (extract32(opt
, 1, 1) == 0) {
2396 unallocated_encoding(s
);
2401 size
|= (opc
& 2) << 1;
2403 unallocated_encoding(s
);
2406 is_store
= !extract32(opc
, 0, 1);
2407 if (!fp_access_check(s
)) {
2411 if (size
== 3 && opc
== 2) {
2412 /* PRFM - prefetch */
2415 if (opc
== 3 && size
> 1) {
2416 unallocated_encoding(s
);
2419 is_store
= (opc
== 0);
2420 is_signed
= extract32(opc
, 1, 1);
2421 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2425 gen_check_sp_alignment(s
);
2427 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2429 tcg_rm
= read_cpu_reg(s
, rm
, 1);
2430 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
2432 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_rm
);
2436 do_fp_st(s
, rt
, tcg_addr
, size
);
2438 do_fp_ld(s
, rt
, tcg_addr
, size
);
2441 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2442 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2444 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2445 true, rt
, iss_sf
, false);
2447 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
,
2448 is_signed
, is_extended
,
2449 true, rt
, iss_sf
, false);
2455 * C3.3.13 Load/store (unsigned immediate)
2457 * 31 30 29 27 26 25 24 23 22 21 10 9 5
2458 * +----+-------+---+-----+-----+------------+-------+------+
2459 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
2460 * +----+-------+---+-----+-----+------------+-------+------+
2463 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2464 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2466 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2467 * opc<0>: 0 -> store, 1 -> load
2468 * Rn: base address register (inc SP)
2469 * Rt: target register
2471 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
2477 int rn
= extract32(insn
, 5, 5);
2478 unsigned int imm12
= extract32(insn
, 10, 12);
2479 unsigned int offset
;
2484 bool is_signed
= false;
2485 bool is_extended
= false;
2488 size
|= (opc
& 2) << 1;
2490 unallocated_encoding(s
);
2493 is_store
= !extract32(opc
, 0, 1);
2494 if (!fp_access_check(s
)) {
2498 if (size
== 3 && opc
== 2) {
2499 /* PRFM - prefetch */
2502 if (opc
== 3 && size
> 1) {
2503 unallocated_encoding(s
);
2506 is_store
= (opc
== 0);
2507 is_signed
= extract32(opc
, 1, 1);
2508 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2512 gen_check_sp_alignment(s
);
2514 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2515 offset
= imm12
<< size
;
2516 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2520 do_fp_st(s
, rt
, tcg_addr
, size
);
2522 do_fp_ld(s
, rt
, tcg_addr
, size
);
2525 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2526 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2528 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2529 true, rt
, iss_sf
, false);
2531 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
,
2532 true, rt
, iss_sf
, false);
2537 /* Load/store register (all forms) */
2538 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
2540 int rt
= extract32(insn
, 0, 5);
2541 int opc
= extract32(insn
, 22, 2);
2542 bool is_vector
= extract32(insn
, 26, 1);
2543 int size
= extract32(insn
, 30, 2);
2545 switch (extract32(insn
, 24, 2)) {
2547 if (extract32(insn
, 21, 1) == 1 && extract32(insn
, 10, 2) == 2) {
2548 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
2550 /* Load/store register (unscaled immediate)
2551 * Load/store immediate pre/post-indexed
2552 * Load/store register unprivileged
2554 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
2558 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
2561 unallocated_encoding(s
);
2566 /* C3.3.1 AdvSIMD load/store multiple structures
2568 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
2569 * +---+---+---------------+---+-------------+--------+------+------+------+
2570 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
2571 * +---+---+---------------+---+-------------+--------+------+------+------+
2573 * C3.3.2 AdvSIMD load/store multiple structures (post-indexed)
2575 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
2576 * +---+---+---------------+---+---+---------+--------+------+------+------+
2577 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
2578 * +---+---+---------------+---+---+---------+--------+------+------+------+
2580 * Rt: first (or only) SIMD&FP register to be transferred
2581 * Rn: base address or SP
2582 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2584 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
2586 int rt
= extract32(insn
, 0, 5);
2587 int rn
= extract32(insn
, 5, 5);
2588 int size
= extract32(insn
, 10, 2);
2589 int opcode
= extract32(insn
, 12, 4);
2590 bool is_store
= !extract32(insn
, 22, 1);
2591 bool is_postidx
= extract32(insn
, 23, 1);
2592 bool is_q
= extract32(insn
, 30, 1);
2593 TCGv_i64 tcg_addr
, tcg_rn
;
2595 int ebytes
= 1 << size
;
2596 int elements
= (is_q
? 128 : 64) / (8 << size
);
2597 int rpt
; /* num iterations */
2598 int selem
; /* structure elements */
2601 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
2602 unallocated_encoding(s
);
2606 /* From the shared decode logic */
2637 unallocated_encoding(s
);
2641 if (size
== 3 && !is_q
&& selem
!= 1) {
2643 unallocated_encoding(s
);
2647 if (!fp_access_check(s
)) {
2652 gen_check_sp_alignment(s
);
2655 tcg_rn
= cpu_reg_sp(s
, rn
);
2656 tcg_addr
= tcg_temp_new_i64();
2657 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2659 for (r
= 0; r
< rpt
; r
++) {
2661 for (e
= 0; e
< elements
; e
++) {
2662 int tt
= (rt
+ r
) % 32;
2664 for (xs
= 0; xs
< selem
; xs
++) {
2666 do_vec_st(s
, tt
, e
, tcg_addr
, size
);
2668 do_vec_ld(s
, tt
, e
, tcg_addr
, size
);
2670 /* For non-quad operations, setting a slice of the low
2671 * 64 bits of the register clears the high 64 bits (in
2672 * the ARM ARM pseudocode this is implicit in the fact
2673 * that 'rval' is a 64 bit wide variable). We optimize
2674 * by noticing that we only need to do this the first
2675 * time we touch a register.
2677 if (!is_q
&& e
== 0 && (r
== 0 || xs
== selem
- 1)) {
2678 clear_vec_high(s
, tt
);
2681 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2688 int rm
= extract32(insn
, 16, 5);
2690 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2692 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2695 tcg_temp_free_i64(tcg_addr
);
2698 /* C3.3.3 AdvSIMD load/store single structure
2700 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2701 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2702 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
2703 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2705 * C3.3.4 AdvSIMD load/store single structure (post-indexed)
2707 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2708 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2709 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
2710 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2712 * Rt: first (or only) SIMD&FP register to be transferred
2713 * Rn: base address or SP
2714 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2715 * index = encoded in Q:S:size dependent on size
2717 * lane_size = encoded in R, opc
2718 * transfer width = encoded in opc, S, size
2720 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
2722 int rt
= extract32(insn
, 0, 5);
2723 int rn
= extract32(insn
, 5, 5);
2724 int size
= extract32(insn
, 10, 2);
2725 int S
= extract32(insn
, 12, 1);
2726 int opc
= extract32(insn
, 13, 3);
2727 int R
= extract32(insn
, 21, 1);
2728 int is_load
= extract32(insn
, 22, 1);
2729 int is_postidx
= extract32(insn
, 23, 1);
2730 int is_q
= extract32(insn
, 30, 1);
2732 int scale
= extract32(opc
, 1, 2);
2733 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
2734 bool replicate
= false;
2735 int index
= is_q
<< 3 | S
<< 2 | size
;
2737 TCGv_i64 tcg_addr
, tcg_rn
;
2741 if (!is_load
|| S
) {
2742 unallocated_encoding(s
);
2751 if (extract32(size
, 0, 1)) {
2752 unallocated_encoding(s
);
2758 if (extract32(size
, 1, 1)) {
2759 unallocated_encoding(s
);
2762 if (!extract32(size
, 0, 1)) {
2766 unallocated_encoding(s
);
2774 g_assert_not_reached();
2777 if (!fp_access_check(s
)) {
2781 ebytes
= 1 << scale
;
2784 gen_check_sp_alignment(s
);
2787 tcg_rn
= cpu_reg_sp(s
, rn
);
2788 tcg_addr
= tcg_temp_new_i64();
2789 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2791 for (xs
= 0; xs
< selem
; xs
++) {
2793 /* Load and replicate to all elements */
2795 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
2797 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
,
2798 get_mem_index(s
), s
->be_data
+ scale
);
2801 mulconst
= 0x0101010101010101ULL
;
2804 mulconst
= 0x0001000100010001ULL
;
2807 mulconst
= 0x0000000100000001ULL
;
2813 g_assert_not_reached();
2816 tcg_gen_muli_i64(tcg_tmp
, tcg_tmp
, mulconst
);
2818 write_vec_element(s
, tcg_tmp
, rt
, 0, MO_64
);
2820 write_vec_element(s
, tcg_tmp
, rt
, 1, MO_64
);
2822 clear_vec_high(s
, rt
);
2824 tcg_temp_free_i64(tcg_tmp
);
2826 /* Load/store one element per register */
2828 do_vec_ld(s
, rt
, index
, tcg_addr
, scale
);
2830 do_vec_st(s
, rt
, index
, tcg_addr
, scale
);
2833 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2838 int rm
= extract32(insn
, 16, 5);
2840 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2842 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2845 tcg_temp_free_i64(tcg_addr
);
2848 /* C3.3 Loads and stores */
2849 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
2851 switch (extract32(insn
, 24, 6)) {
2852 case 0x08: /* Load/store exclusive */
2853 disas_ldst_excl(s
, insn
);
2855 case 0x18: case 0x1c: /* Load register (literal) */
2856 disas_ld_lit(s
, insn
);
2858 case 0x28: case 0x29:
2859 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
2860 disas_ldst_pair(s
, insn
);
2862 case 0x38: case 0x39:
2863 case 0x3c: case 0x3d: /* Load/store register (all forms) */
2864 disas_ldst_reg(s
, insn
);
2866 case 0x0c: /* AdvSIMD load/store multiple structures */
2867 disas_ldst_multiple_struct(s
, insn
);
2869 case 0x0d: /* AdvSIMD load/store single structure */
2870 disas_ldst_single_struct(s
, insn
);
2873 unallocated_encoding(s
);
2878 /* C3.4.6 PC-rel. addressing
2879 * 31 30 29 28 24 23 5 4 0
2880 * +----+-------+-----------+-------------------+------+
2881 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
2882 * +----+-------+-----------+-------------------+------+
2884 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
2886 unsigned int page
, rd
;
2890 page
= extract32(insn
, 31, 1);
2891 /* SignExtend(immhi:immlo) -> offset */
2892 offset
= sextract64(insn
, 5, 19);
2893 offset
= offset
<< 2 | extract32(insn
, 29, 2);
2894 rd
= extract32(insn
, 0, 5);
2898 /* ADRP (page based) */
2903 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
2907 * C3.4.1 Add/subtract (immediate)
2909 * 31 30 29 28 24 23 22 21 10 9 5 4 0
2910 * +--+--+--+-----------+-----+-------------+-----+-----+
2911 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
2912 * +--+--+--+-----------+-----+-------------+-----+-----+
2914 * sf: 0 -> 32bit, 1 -> 64bit
2915 * op: 0 -> add , 1 -> sub
2917 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
2919 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
2921 int rd
= extract32(insn
, 0, 5);
2922 int rn
= extract32(insn
, 5, 5);
2923 uint64_t imm
= extract32(insn
, 10, 12);
2924 int shift
= extract32(insn
, 22, 2);
2925 bool setflags
= extract32(insn
, 29, 1);
2926 bool sub_op
= extract32(insn
, 30, 1);
2927 bool is_64bit
= extract32(insn
, 31, 1);
2929 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2930 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
2931 TCGv_i64 tcg_result
;
2940 unallocated_encoding(s
);
2944 tcg_result
= tcg_temp_new_i64();
2947 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
2949 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
2952 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
2954 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2956 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2958 tcg_temp_free_i64(tcg_imm
);
2962 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
2964 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
2967 tcg_temp_free_i64(tcg_result
);
2970 /* The input should be a value in the bottom e bits (with higher
2971 * bits zero); returns that value replicated into every element
2972 * of size e in a 64 bit integer.
2974 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
2984 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
2985 static inline uint64_t bitmask64(unsigned int length
)
2987 assert(length
> 0 && length
<= 64);
2988 return ~0ULL >> (64 - length
);
2991 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
2992 * only require the wmask. Returns false if the imms/immr/immn are a reserved
2993 * value (ie should cause a guest UNDEF exception), and true if they are
2994 * valid, in which case the decoded bit pattern is written to result.
2996 static bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
2997 unsigned int imms
, unsigned int immr
)
3000 unsigned e
, levels
, s
, r
;
3003 assert(immn
< 2 && imms
< 64 && immr
< 64);
3005 /* The bit patterns we create here are 64 bit patterns which
3006 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
3007 * 64 bits each. Each element contains the same value: a run
3008 * of between 1 and e-1 non-zero bits, rotated within the
3009 * element by between 0 and e-1 bits.
3011 * The element size and run length are encoded into immn (1 bit)
3012 * and imms (6 bits) as follows:
3013 * 64 bit elements: immn = 1, imms = <length of run - 1>
3014 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
3015 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
3016 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
3017 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
3018 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
3019 * Notice that immn = 0, imms = 11111x is the only combination
3020 * not covered by one of the above options; this is reserved.
3021 * Further, <length of run - 1> all-ones is a reserved pattern.
3023 * In all cases the rotation is by immr % e (and immr is 6 bits).
3026 /* First determine the element size */
3027 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
3029 /* This is the immn == 0, imms == 0x11111x case */
3039 /* <length of run - 1> mustn't be all-ones. */
3043 /* Create the value of one element: s+1 set bits rotated
3044 * by r within the element (which is e bits wide)...
3046 mask
= bitmask64(s
+ 1);
3048 mask
= (mask
>> r
) | (mask
<< (e
- r
));
3049 mask
&= bitmask64(e
);
3051 /* ...then replicate the element over the whole 64 bit value */
3052 mask
= bitfield_replicate(mask
, e
);
3057 /* C3.4.4 Logical (immediate)
3058 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3059 * +----+-----+-------------+---+------+------+------+------+
3060 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
3061 * +----+-----+-------------+---+------+------+------+------+
3063 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
3065 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
3066 TCGv_i64 tcg_rd
, tcg_rn
;
3068 bool is_and
= false;
3070 sf
= extract32(insn
, 31, 1);
3071 opc
= extract32(insn
, 29, 2);
3072 is_n
= extract32(insn
, 22, 1);
3073 immr
= extract32(insn
, 16, 6);
3074 imms
= extract32(insn
, 10, 6);
3075 rn
= extract32(insn
, 5, 5);
3076 rd
= extract32(insn
, 0, 5);
3079 unallocated_encoding(s
);
3083 if (opc
== 0x3) { /* ANDS */
3084 tcg_rd
= cpu_reg(s
, rd
);
3086 tcg_rd
= cpu_reg_sp(s
, rd
);
3088 tcg_rn
= cpu_reg(s
, rn
);
3090 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
3091 /* some immediate field values are reserved */
3092 unallocated_encoding(s
);
3097 wmask
&= 0xffffffff;
3101 case 0x3: /* ANDS */
3103 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
3107 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
3110 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
3113 assert(FALSE
); /* must handle all above */
3117 if (!sf
&& !is_and
) {
3118 /* zero extend final result; we know we can skip this for AND
3119 * since the immediate had the high 32 bits clear.
3121 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3124 if (opc
== 3) { /* ANDS */
3125 gen_logic_CC(sf
, tcg_rd
);
3130 * C3.4.5 Move wide (immediate)
3132 * 31 30 29 28 23 22 21 20 5 4 0
3133 * +--+-----+-------------+-----+----------------+------+
3134 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
3135 * +--+-----+-------------+-----+----------------+------+
3137 * sf: 0 -> 32 bit, 1 -> 64 bit
3138 * opc: 00 -> N, 10 -> Z, 11 -> K
3139 * hw: shift/16 (0,16, and sf only 32, 48)
3141 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
3143 int rd
= extract32(insn
, 0, 5);
3144 uint64_t imm
= extract32(insn
, 5, 16);
3145 int sf
= extract32(insn
, 31, 1);
3146 int opc
= extract32(insn
, 29, 2);
3147 int pos
= extract32(insn
, 21, 2) << 4;
3148 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3151 if (!sf
&& (pos
>= 32)) {
3152 unallocated_encoding(s
);
3166 tcg_gen_movi_i64(tcg_rd
, imm
);
3169 tcg_imm
= tcg_const_i64(imm
);
3170 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
3171 tcg_temp_free_i64(tcg_imm
);
3173 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3177 unallocated_encoding(s
);
3183 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3184 * +----+-----+-------------+---+------+------+------+------+
3185 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
3186 * +----+-----+-------------+---+------+------+------+------+
3188 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
3190 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
3191 TCGv_i64 tcg_rd
, tcg_tmp
;
3193 sf
= extract32(insn
, 31, 1);
3194 opc
= extract32(insn
, 29, 2);
3195 n
= extract32(insn
, 22, 1);
3196 ri
= extract32(insn
, 16, 6);
3197 si
= extract32(insn
, 10, 6);
3198 rn
= extract32(insn
, 5, 5);
3199 rd
= extract32(insn
, 0, 5);
3200 bitsize
= sf
? 64 : 32;
3202 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
3203 unallocated_encoding(s
);
3207 tcg_rd
= cpu_reg(s
, rd
);
3209 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
3210 to be smaller than bitsize, we'll never reference data outside the
3211 low 32-bits anyway. */
3212 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
3214 /* Recognize simple(r) extractions. */
3216 /* Wd<s-r:0> = Wn<s:r> */
3217 len
= (si
- ri
) + 1;
3218 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
3219 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3221 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
3222 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3225 /* opc == 1, BXFIL fall through to deposit */
3226 tcg_gen_extract_i64(tcg_tmp
, tcg_tmp
, ri
, len
);
3229 /* Handle the ri > si case with a deposit
3230 * Wd<32+s-r,32-r> = Wn<s:0>
3233 pos
= (bitsize
- ri
) & (bitsize
- 1);
3236 if (opc
== 0 && len
< ri
) {
3237 /* SBFM: sign extend the destination field from len to fill
3238 the balance of the word. Let the deposit below insert all
3239 of those sign bits. */
3240 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
3244 if (opc
== 1) { /* BFM, BXFIL */
3245 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
3247 /* SBFM or UBFM: We start with zero, and we haven't modified
3248 any bits outside bitsize, therefore the zero-extension
3249 below is unneeded. */
3250 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
3255 if (!sf
) { /* zero extend final result */
3256 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3261 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
3262 * +----+------+-------------+---+----+------+--------+------+------+
3263 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
3264 * +----+------+-------------+---+----+------+--------+------+------+
3266 static void disas_extract(DisasContext
*s
, uint32_t insn
)
3268 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
3270 sf
= extract32(insn
, 31, 1);
3271 n
= extract32(insn
, 22, 1);
3272 rm
= extract32(insn
, 16, 5);
3273 imm
= extract32(insn
, 10, 6);
3274 rn
= extract32(insn
, 5, 5);
3275 rd
= extract32(insn
, 0, 5);
3276 op21
= extract32(insn
, 29, 2);
3277 op0
= extract32(insn
, 21, 1);
3278 bitsize
= sf
? 64 : 32;
3280 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
3281 unallocated_encoding(s
);
3283 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
3285 tcg_rd
= cpu_reg(s
, rd
);
3287 if (unlikely(imm
== 0)) {
3288 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
3289 * so an extract from bit 0 is a special case.
3292 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
3294 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
3296 } else if (rm
== rn
) { /* ROR */
3297 tcg_rm
= cpu_reg(s
, rm
);
3299 tcg_gen_rotri_i64(tcg_rd
, tcg_rm
, imm
);
3301 TCGv_i32 tmp
= tcg_temp_new_i32();
3302 tcg_gen_extrl_i64_i32(tmp
, tcg_rm
);
3303 tcg_gen_rotri_i32(tmp
, tmp
, imm
);
3304 tcg_gen_extu_i32_i64(tcg_rd
, tmp
);
3305 tcg_temp_free_i32(tmp
);
3308 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3309 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3310 tcg_gen_shri_i64(tcg_rm
, tcg_rm
, imm
);
3311 tcg_gen_shli_i64(tcg_rn
, tcg_rn
, bitsize
- imm
);
3312 tcg_gen_or_i64(tcg_rd
, tcg_rm
, tcg_rn
);
3314 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3320 /* C3.4 Data processing - immediate */
3321 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
3323 switch (extract32(insn
, 23, 6)) {
3324 case 0x20: case 0x21: /* PC-rel. addressing */
3325 disas_pc_rel_adr(s
, insn
);
3327 case 0x22: case 0x23: /* Add/subtract (immediate) */
3328 disas_add_sub_imm(s
, insn
);
3330 case 0x24: /* Logical (immediate) */
3331 disas_logic_imm(s
, insn
);
3333 case 0x25: /* Move wide (immediate) */
3334 disas_movw_imm(s
, insn
);
3336 case 0x26: /* Bitfield */
3337 disas_bitfield(s
, insn
);
3339 case 0x27: /* Extract */
3340 disas_extract(s
, insn
);
3343 unallocated_encoding(s
);
3348 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
3349 * Note that it is the caller's responsibility to ensure that the
3350 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
3351 * mandated semantics for out of range shifts.
3353 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3354 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
3356 switch (shift_type
) {
3357 case A64_SHIFT_TYPE_LSL
:
3358 tcg_gen_shl_i64(dst
, src
, shift_amount
);
3360 case A64_SHIFT_TYPE_LSR
:
3361 tcg_gen_shr_i64(dst
, src
, shift_amount
);
3363 case A64_SHIFT_TYPE_ASR
:
3365 tcg_gen_ext32s_i64(dst
, src
);
3367 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
3369 case A64_SHIFT_TYPE_ROR
:
3371 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
3374 t0
= tcg_temp_new_i32();
3375 t1
= tcg_temp_new_i32();
3376 tcg_gen_extrl_i64_i32(t0
, src
);
3377 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
3378 tcg_gen_rotr_i32(t0
, t0
, t1
);
3379 tcg_gen_extu_i32_i64(dst
, t0
);
3380 tcg_temp_free_i32(t0
);
3381 tcg_temp_free_i32(t1
);
3385 assert(FALSE
); /* all shift types should be handled */
3389 if (!sf
) { /* zero extend final result */
3390 tcg_gen_ext32u_i64(dst
, dst
);
3394 /* Shift a TCGv src by immediate, put result in dst.
3395 * The shift amount must be in range (this should always be true as the
3396 * relevant instructions will UNDEF on bad shift immediates).
3398 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3399 enum a64_shift_type shift_type
, unsigned int shift_i
)
3401 assert(shift_i
< (sf
? 64 : 32));
3404 tcg_gen_mov_i64(dst
, src
);
3406 TCGv_i64 shift_const
;
3408 shift_const
= tcg_const_i64(shift_i
);
3409 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
3410 tcg_temp_free_i64(shift_const
);
3414 /* C3.5.10 Logical (shifted register)
3415 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3416 * +----+-----+-----------+-------+---+------+--------+------+------+
3417 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
3418 * +----+-----+-----------+-------+---+------+--------+------+------+
3420 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
3422 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
3423 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
3425 sf
= extract32(insn
, 31, 1);
3426 opc
= extract32(insn
, 29, 2);
3427 shift_type
= extract32(insn
, 22, 2);
3428 invert
= extract32(insn
, 21, 1);
3429 rm
= extract32(insn
, 16, 5);
3430 shift_amount
= extract32(insn
, 10, 6);
3431 rn
= extract32(insn
, 5, 5);
3432 rd
= extract32(insn
, 0, 5);
3434 if (!sf
&& (shift_amount
& (1 << 5))) {
3435 unallocated_encoding(s
);
3439 tcg_rd
= cpu_reg(s
, rd
);
3441 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
3442 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
3443 * register-register MOV and MVN, so it is worth special casing.
3445 tcg_rm
= cpu_reg(s
, rm
);
3447 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
3449 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3453 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
3455 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
3461 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3464 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
3467 tcg_rn
= cpu_reg(s
, rn
);
3469 switch (opc
| (invert
<< 2)) {
3472 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3475 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3478 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3482 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3485 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3488 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3496 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3500 gen_logic_CC(sf
, tcg_rd
);
3505 * C3.5.1 Add/subtract (extended register)
3507 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
3508 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3509 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
3510 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3512 * sf: 0 -> 32bit, 1 -> 64bit
3513 * op: 0 -> add , 1 -> sub
3516 * option: extension type (see DecodeRegExtend)
3517 * imm3: optional shift to Rm
3519 * Rd = Rn + LSL(extend(Rm), amount)
3521 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
3523 int rd
= extract32(insn
, 0, 5);
3524 int rn
= extract32(insn
, 5, 5);
3525 int imm3
= extract32(insn
, 10, 3);
3526 int option
= extract32(insn
, 13, 3);
3527 int rm
= extract32(insn
, 16, 5);
3528 bool setflags
= extract32(insn
, 29, 1);
3529 bool sub_op
= extract32(insn
, 30, 1);
3530 bool sf
= extract32(insn
, 31, 1);
3532 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
3534 TCGv_i64 tcg_result
;
3537 unallocated_encoding(s
);
3541 /* non-flag setting ops may use SP */
3543 tcg_rd
= cpu_reg_sp(s
, rd
);
3545 tcg_rd
= cpu_reg(s
, rd
);
3547 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
3549 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3550 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
3552 tcg_result
= tcg_temp_new_i64();
3556 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3558 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3562 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3564 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3569 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3571 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3574 tcg_temp_free_i64(tcg_result
);
3578 * C3.5.2 Add/subtract (shifted register)
3580 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3581 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3582 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
3583 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3585 * sf: 0 -> 32bit, 1 -> 64bit
3586 * op: 0 -> add , 1 -> sub
3588 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
3589 * imm6: Shift amount to apply to Rm before the add/sub
3591 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
3593 int rd
= extract32(insn
, 0, 5);
3594 int rn
= extract32(insn
, 5, 5);
3595 int imm6
= extract32(insn
, 10, 6);
3596 int rm
= extract32(insn
, 16, 5);
3597 int shift_type
= extract32(insn
, 22, 2);
3598 bool setflags
= extract32(insn
, 29, 1);
3599 bool sub_op
= extract32(insn
, 30, 1);
3600 bool sf
= extract32(insn
, 31, 1);
3602 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3603 TCGv_i64 tcg_rn
, tcg_rm
;
3604 TCGv_i64 tcg_result
;
3606 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
3607 unallocated_encoding(s
);
3611 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3612 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3614 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
3616 tcg_result
= tcg_temp_new_i64();
3620 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3622 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3626 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3628 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3633 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3635 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3638 tcg_temp_free_i64(tcg_result
);
3641 /* C3.5.9 Data-processing (3 source)
3643 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
3644 +--+------+-----------+------+------+----+------+------+------+
3645 |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
3646 +--+------+-----------+------+------+----+------+------+------+
3649 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
3651 int rd
= extract32(insn
, 0, 5);
3652 int rn
= extract32(insn
, 5, 5);
3653 int ra
= extract32(insn
, 10, 5);
3654 int rm
= extract32(insn
, 16, 5);
3655 int op_id
= (extract32(insn
, 29, 3) << 4) |
3656 (extract32(insn
, 21, 3) << 1) |
3657 extract32(insn
, 15, 1);
3658 bool sf
= extract32(insn
, 31, 1);
3659 bool is_sub
= extract32(op_id
, 0, 1);
3660 bool is_high
= extract32(op_id
, 2, 1);
3661 bool is_signed
= false;
3666 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
3668 case 0x42: /* SMADDL */
3669 case 0x43: /* SMSUBL */
3670 case 0x44: /* SMULH */
3673 case 0x0: /* MADD (32bit) */
3674 case 0x1: /* MSUB (32bit) */
3675 case 0x40: /* MADD (64bit) */
3676 case 0x41: /* MSUB (64bit) */
3677 case 0x4a: /* UMADDL */
3678 case 0x4b: /* UMSUBL */
3679 case 0x4c: /* UMULH */
3682 unallocated_encoding(s
);
3687 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
3688 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3689 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
3690 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
3693 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3695 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3698 tcg_temp_free_i64(low_bits
);
3702 tcg_op1
= tcg_temp_new_i64();
3703 tcg_op2
= tcg_temp_new_i64();
3704 tcg_tmp
= tcg_temp_new_i64();
3707 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
3708 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
3711 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
3712 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
3714 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
3715 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
3719 if (ra
== 31 && !is_sub
) {
3720 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
3721 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
3723 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
3725 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3727 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3732 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
3735 tcg_temp_free_i64(tcg_op1
);
3736 tcg_temp_free_i64(tcg_op2
);
3737 tcg_temp_free_i64(tcg_tmp
);
3740 /* C3.5.3 - Add/subtract (with carry)
3741 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
3742 * +--+--+--+------------------------+------+---------+------+-----+
3743 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
3744 * +--+--+--+------------------------+------+---------+------+-----+
3748 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
3750 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
3751 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
3753 if (extract32(insn
, 10, 6) != 0) {
3754 unallocated_encoding(s
);
3758 sf
= extract32(insn
, 31, 1);
3759 op
= extract32(insn
, 30, 1);
3760 setflags
= extract32(insn
, 29, 1);
3761 rm
= extract32(insn
, 16, 5);
3762 rn
= extract32(insn
, 5, 5);
3763 rd
= extract32(insn
, 0, 5);
3765 tcg_rd
= cpu_reg(s
, rd
);
3766 tcg_rn
= cpu_reg(s
, rn
);
3769 tcg_y
= new_tmp_a64(s
);
3770 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
3772 tcg_y
= cpu_reg(s
, rm
);
3776 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3778 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3782 /* C3.5.4 - C3.5.5 Conditional compare (immediate / register)
3783 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
3784 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3785 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
3786 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3789 static void disas_cc(DisasContext
*s
, uint32_t insn
)
3791 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
3792 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
3793 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
3796 if (!extract32(insn
, 29, 1)) {
3797 unallocated_encoding(s
);
3800 if (insn
& (1 << 10 | 1 << 4)) {
3801 unallocated_encoding(s
);
3804 sf
= extract32(insn
, 31, 1);
3805 op
= extract32(insn
, 30, 1);
3806 is_imm
= extract32(insn
, 11, 1);
3807 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
3808 cond
= extract32(insn
, 12, 4);
3809 rn
= extract32(insn
, 5, 5);
3810 nzcv
= extract32(insn
, 0, 4);
3812 /* Set T0 = !COND. */
3813 tcg_t0
= tcg_temp_new_i32();
3814 arm_test_cc(&c
, cond
);
3815 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
3818 /* Load the arguments for the new comparison. */
3820 tcg_y
= new_tmp_a64(s
);
3821 tcg_gen_movi_i64(tcg_y
, y
);
3823 tcg_y
= cpu_reg(s
, y
);
3825 tcg_rn
= cpu_reg(s
, rn
);
3827 /* Set the flags for the new comparison. */
3828 tcg_tmp
= tcg_temp_new_i64();
3830 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3832 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3834 tcg_temp_free_i64(tcg_tmp
);
3836 /* If COND was false, force the flags to #nzcv. Compute two masks
3837 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
3838 * For tcg hosts that support ANDC, we can make do with just T1.
3839 * In either case, allow the tcg optimizer to delete any unused mask.
3841 tcg_t1
= tcg_temp_new_i32();
3842 tcg_t2
= tcg_temp_new_i32();
3843 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
3844 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
3846 if (nzcv
& 8) { /* N */
3847 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
3849 if (TCG_TARGET_HAS_andc_i32
) {
3850 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
3852 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
3855 if (nzcv
& 4) { /* Z */
3856 if (TCG_TARGET_HAS_andc_i32
) {
3857 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
3859 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
3862 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
3864 if (nzcv
& 2) { /* C */
3865 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
3867 if (TCG_TARGET_HAS_andc_i32
) {
3868 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
3870 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
3873 if (nzcv
& 1) { /* V */
3874 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
3876 if (TCG_TARGET_HAS_andc_i32
) {
3877 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
3879 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
3882 tcg_temp_free_i32(tcg_t0
);
3883 tcg_temp_free_i32(tcg_t1
);
3884 tcg_temp_free_i32(tcg_t2
);
3887 /* C3.5.6 Conditional select
3888 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
3889 * +----+----+---+-----------------+------+------+-----+------+------+
3890 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
3891 * +----+----+---+-----------------+------+------+-----+------+------+
3893 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
3895 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
3896 TCGv_i64 tcg_rd
, zero
;
3899 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
3900 /* S == 1 or op2<1> == 1 */
3901 unallocated_encoding(s
);
3904 sf
= extract32(insn
, 31, 1);
3905 else_inv
= extract32(insn
, 30, 1);
3906 rm
= extract32(insn
, 16, 5);
3907 cond
= extract32(insn
, 12, 4);
3908 else_inc
= extract32(insn
, 10, 1);
3909 rn
= extract32(insn
, 5, 5);
3910 rd
= extract32(insn
, 0, 5);
3912 tcg_rd
= cpu_reg(s
, rd
);
3914 a64_test_cc(&c
, cond
);
3915 zero
= tcg_const_i64(0);
3917 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
3919 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
3921 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
3924 TCGv_i64 t_true
= cpu_reg(s
, rn
);
3925 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
3926 if (else_inv
&& else_inc
) {
3927 tcg_gen_neg_i64(t_false
, t_false
);
3928 } else if (else_inv
) {
3929 tcg_gen_not_i64(t_false
, t_false
);
3930 } else if (else_inc
) {
3931 tcg_gen_addi_i64(t_false
, t_false
, 1);
3933 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
3936 tcg_temp_free_i64(zero
);
3940 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3944 static void handle_clz(DisasContext
*s
, unsigned int sf
,
3945 unsigned int rn
, unsigned int rd
)
3947 TCGv_i64 tcg_rd
, tcg_rn
;
3948 tcg_rd
= cpu_reg(s
, rd
);
3949 tcg_rn
= cpu_reg(s
, rn
);
3952 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
3954 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3955 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
3956 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
3957 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3958 tcg_temp_free_i32(tcg_tmp32
);
3962 static void handle_cls(DisasContext
*s
, unsigned int sf
,
3963 unsigned int rn
, unsigned int rd
)
3965 TCGv_i64 tcg_rd
, tcg_rn
;
3966 tcg_rd
= cpu_reg(s
, rd
);
3967 tcg_rn
= cpu_reg(s
, rn
);
3970 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
3972 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3973 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
3974 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
3975 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3976 tcg_temp_free_i32(tcg_tmp32
);
3980 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
3981 unsigned int rn
, unsigned int rd
)
3983 TCGv_i64 tcg_rd
, tcg_rn
;
3984 tcg_rd
= cpu_reg(s
, rd
);
3985 tcg_rn
= cpu_reg(s
, rn
);
3988 gen_helper_rbit64(tcg_rd
, tcg_rn
);
3990 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3991 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
3992 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
3993 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3994 tcg_temp_free_i32(tcg_tmp32
);
3998 /* C5.6.149 REV with sf==1, opcode==3 ("REV64") */
3999 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
4000 unsigned int rn
, unsigned int rd
)
4003 unallocated_encoding(s
);
4006 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
4009 /* C5.6.149 REV with sf==0, opcode==2
4010 * C5.6.151 REV32 (sf==1, opcode==2)
4012 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
4013 unsigned int rn
, unsigned int rd
)
4015 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4018 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4019 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4021 /* bswap32_i64 requires zero high word */
4022 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
4023 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
4024 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
4025 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
4026 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4028 tcg_temp_free_i64(tcg_tmp
);
4030 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
4031 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
4035 /* C5.6.150 REV16 (opcode==1) */
4036 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
4037 unsigned int rn
, unsigned int rd
)
4039 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4040 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4041 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4043 tcg_gen_andi_i64(tcg_tmp
, tcg_rn
, 0xffff);
4044 tcg_gen_bswap16_i64(tcg_rd
, tcg_tmp
);
4046 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 16);
4047 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
4048 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
4049 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 16, 16);
4052 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
4053 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
4054 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
4055 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 32, 16);
4057 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 48);
4058 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
4059 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 48, 16);
4062 tcg_temp_free_i64(tcg_tmp
);
4065 /* C3.5.7 Data-processing (1 source)
4066 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4067 * +----+---+---+-----------------+---------+--------+------+------+
4068 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
4069 * +----+---+---+-----------------+---------+--------+------+------+
4071 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
4073 unsigned int sf
, opcode
, rn
, rd
;
4075 if (extract32(insn
, 29, 1) || extract32(insn
, 16, 5)) {
4076 unallocated_encoding(s
);
4080 sf
= extract32(insn
, 31, 1);
4081 opcode
= extract32(insn
, 10, 6);
4082 rn
= extract32(insn
, 5, 5);
4083 rd
= extract32(insn
, 0, 5);
4087 handle_rbit(s
, sf
, rn
, rd
);
4090 handle_rev16(s
, sf
, rn
, rd
);
4093 handle_rev32(s
, sf
, rn
, rd
);
4096 handle_rev64(s
, sf
, rn
, rd
);
4099 handle_clz(s
, sf
, rn
, rd
);
4102 handle_cls(s
, sf
, rn
, rd
);
4107 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
4108 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4110 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
4111 tcg_rd
= cpu_reg(s
, rd
);
4113 if (!sf
&& is_signed
) {
4114 tcg_n
= new_tmp_a64(s
);
4115 tcg_m
= new_tmp_a64(s
);
4116 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
4117 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
4119 tcg_n
= read_cpu_reg(s
, rn
, sf
);
4120 tcg_m
= read_cpu_reg(s
, rm
, sf
);
4124 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
4126 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
4129 if (!sf
) { /* zero extend final result */
4130 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4134 /* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */
4135 static void handle_shift_reg(DisasContext
*s
,
4136 enum a64_shift_type shift_type
, unsigned int sf
,
4137 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4139 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
4140 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4141 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4143 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
4144 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
4145 tcg_temp_free_i64(tcg_shift
);
4148 /* CRC32[BHWX], CRC32C[BHWX] */
4149 static void handle_crc32(DisasContext
*s
,
4150 unsigned int sf
, unsigned int sz
, bool crc32c
,
4151 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4153 TCGv_i64 tcg_acc
, tcg_val
;
4156 if (!arm_dc_feature(s
, ARM_FEATURE_CRC
)
4157 || (sf
== 1 && sz
!= 3)
4158 || (sf
== 0 && sz
== 3)) {
4159 unallocated_encoding(s
);
4164 tcg_val
= cpu_reg(s
, rm
);
4178 g_assert_not_reached();
4180 tcg_val
= new_tmp_a64(s
);
4181 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
4184 tcg_acc
= cpu_reg(s
, rn
);
4185 tcg_bytes
= tcg_const_i32(1 << sz
);
4188 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4190 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4193 tcg_temp_free_i32(tcg_bytes
);
4196 /* C3.5.8 Data-processing (2 source)
4197 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4198 * +----+---+---+-----------------+------+--------+------+------+
4199 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
4200 * +----+---+---+-----------------+------+--------+------+------+
4202 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
4204 unsigned int sf
, rm
, opcode
, rn
, rd
;
4205 sf
= extract32(insn
, 31, 1);
4206 rm
= extract32(insn
, 16, 5);
4207 opcode
= extract32(insn
, 10, 6);
4208 rn
= extract32(insn
, 5, 5);
4209 rd
= extract32(insn
, 0, 5);
4211 if (extract32(insn
, 29, 1)) {
4212 unallocated_encoding(s
);
4218 handle_div(s
, false, sf
, rm
, rn
, rd
);
4221 handle_div(s
, true, sf
, rm
, rn
, rd
);
4224 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
4227 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
4230 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
4233 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
4242 case 23: /* CRC32 */
4244 int sz
= extract32(opcode
, 0, 2);
4245 bool crc32c
= extract32(opcode
, 2, 1);
4246 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
4250 unallocated_encoding(s
);
4255 /* C3.5 Data processing - register */
4256 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
4258 switch (extract32(insn
, 24, 5)) {
4259 case 0x0a: /* Logical (shifted register) */
4260 disas_logic_reg(s
, insn
);
4262 case 0x0b: /* Add/subtract */
4263 if (insn
& (1 << 21)) { /* (extended register) */
4264 disas_add_sub_ext_reg(s
, insn
);
4266 disas_add_sub_reg(s
, insn
);
4269 case 0x1b: /* Data-processing (3 source) */
4270 disas_data_proc_3src(s
, insn
);
4273 switch (extract32(insn
, 21, 3)) {
4274 case 0x0: /* Add/subtract (with carry) */
4275 disas_adc_sbc(s
, insn
);
4277 case 0x2: /* Conditional compare */
4278 disas_cc(s
, insn
); /* both imm and reg forms */
4280 case 0x4: /* Conditional select */
4281 disas_cond_select(s
, insn
);
4283 case 0x6: /* Data-processing */
4284 if (insn
& (1 << 30)) { /* (1 source) */
4285 disas_data_proc_1src(s
, insn
);
4286 } else { /* (2 source) */
4287 disas_data_proc_2src(s
, insn
);
4291 unallocated_encoding(s
);
4296 unallocated_encoding(s
);
4301 static void handle_fp_compare(DisasContext
*s
, bool is_double
,
4302 unsigned int rn
, unsigned int rm
,
4303 bool cmp_with_zero
, bool signal_all_nans
)
4305 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
4306 TCGv_ptr fpst
= get_fpstatus_ptr();
4309 TCGv_i64 tcg_vn
, tcg_vm
;
4311 tcg_vn
= read_fp_dreg(s
, rn
);
4312 if (cmp_with_zero
) {
4313 tcg_vm
= tcg_const_i64(0);
4315 tcg_vm
= read_fp_dreg(s
, rm
);
4317 if (signal_all_nans
) {
4318 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4320 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4322 tcg_temp_free_i64(tcg_vn
);
4323 tcg_temp_free_i64(tcg_vm
);
4325 TCGv_i32 tcg_vn
, tcg_vm
;
4327 tcg_vn
= read_fp_sreg(s
, rn
);
4328 if (cmp_with_zero
) {
4329 tcg_vm
= tcg_const_i32(0);
4331 tcg_vm
= read_fp_sreg(s
, rm
);
4333 if (signal_all_nans
) {
4334 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4336 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4338 tcg_temp_free_i32(tcg_vn
);
4339 tcg_temp_free_i32(tcg_vm
);
4342 tcg_temp_free_ptr(fpst
);
4344 gen_set_nzcv(tcg_flags
);
4346 tcg_temp_free_i64(tcg_flags
);
4349 /* C3.6.22 Floating point compare
4350 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
4351 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4352 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
4353 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4355 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
4357 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
4359 mos
= extract32(insn
, 29, 3);
4360 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4361 rm
= extract32(insn
, 16, 5);
4362 op
= extract32(insn
, 14, 2);
4363 rn
= extract32(insn
, 5, 5);
4364 opc
= extract32(insn
, 3, 2);
4365 op2r
= extract32(insn
, 0, 3);
4367 if (mos
|| op
|| op2r
|| type
> 1) {
4368 unallocated_encoding(s
);
4372 if (!fp_access_check(s
)) {
4376 handle_fp_compare(s
, type
, rn
, rm
, opc
& 1, opc
& 2);
4379 /* C3.6.23 Floating point conditional compare
4380 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4381 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4382 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
4383 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4385 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
4387 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
4389 TCGLabel
*label_continue
= NULL
;
4391 mos
= extract32(insn
, 29, 3);
4392 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4393 rm
= extract32(insn
, 16, 5);
4394 cond
= extract32(insn
, 12, 4);
4395 rn
= extract32(insn
, 5, 5);
4396 op
= extract32(insn
, 4, 1);
4397 nzcv
= extract32(insn
, 0, 4);
4399 if (mos
|| type
> 1) {
4400 unallocated_encoding(s
);
4404 if (!fp_access_check(s
)) {
4408 if (cond
< 0x0e) { /* not always */
4409 TCGLabel
*label_match
= gen_new_label();
4410 label_continue
= gen_new_label();
4411 arm_gen_test_cc(cond
, label_match
);
4413 tcg_flags
= tcg_const_i64(nzcv
<< 28);
4414 gen_set_nzcv(tcg_flags
);
4415 tcg_temp_free_i64(tcg_flags
);
4416 tcg_gen_br(label_continue
);
4417 gen_set_label(label_match
);
4420 handle_fp_compare(s
, type
, rn
, rm
, false, op
);
4423 gen_set_label(label_continue
);
4427 /* C3.6.24 Floating point conditional select
4428 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4429 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4430 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
4431 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4433 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
4435 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
4436 TCGv_i64 t_true
, t_false
, t_zero
;
4439 mos
= extract32(insn
, 29, 3);
4440 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4441 rm
= extract32(insn
, 16, 5);
4442 cond
= extract32(insn
, 12, 4);
4443 rn
= extract32(insn
, 5, 5);
4444 rd
= extract32(insn
, 0, 5);
4446 if (mos
|| type
> 1) {
4447 unallocated_encoding(s
);
4451 if (!fp_access_check(s
)) {
4455 /* Zero extend sreg inputs to 64 bits now. */
4456 t_true
= tcg_temp_new_i64();
4457 t_false
= tcg_temp_new_i64();
4458 read_vec_element(s
, t_true
, rn
, 0, type
? MO_64
: MO_32
);
4459 read_vec_element(s
, t_false
, rm
, 0, type
? MO_64
: MO_32
);
4461 a64_test_cc(&c
, cond
);
4462 t_zero
= tcg_const_i64(0);
4463 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
4464 tcg_temp_free_i64(t_zero
);
4465 tcg_temp_free_i64(t_false
);
4468 /* Note that sregs write back zeros to the high bits,
4469 and we've already done the zero-extension. */
4470 write_fp_dreg(s
, rd
, t_true
);
4471 tcg_temp_free_i64(t_true
);
4474 /* C3.6.25 Floating-point data-processing (1 source) - single precision */
4475 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
4481 fpst
= get_fpstatus_ptr();
4482 tcg_op
= read_fp_sreg(s
, rn
);
4483 tcg_res
= tcg_temp_new_i32();
4486 case 0x0: /* FMOV */
4487 tcg_gen_mov_i32(tcg_res
, tcg_op
);
4489 case 0x1: /* FABS */
4490 gen_helper_vfp_abss(tcg_res
, tcg_op
);
4492 case 0x2: /* FNEG */
4493 gen_helper_vfp_negs(tcg_res
, tcg_op
);
4495 case 0x3: /* FSQRT */
4496 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
4498 case 0x8: /* FRINTN */
4499 case 0x9: /* FRINTP */
4500 case 0xa: /* FRINTM */
4501 case 0xb: /* FRINTZ */
4502 case 0xc: /* FRINTA */
4504 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4506 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4507 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4509 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4510 tcg_temp_free_i32(tcg_rmode
);
4513 case 0xe: /* FRINTX */
4514 gen_helper_rints_exact(tcg_res
, tcg_op
, fpst
);
4516 case 0xf: /* FRINTI */
4517 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4523 write_fp_sreg(s
, rd
, tcg_res
);
4525 tcg_temp_free_ptr(fpst
);
4526 tcg_temp_free_i32(tcg_op
);
4527 tcg_temp_free_i32(tcg_res
);
4530 /* C3.6.25 Floating-point data-processing (1 source) - double precision */
4531 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
4537 fpst
= get_fpstatus_ptr();
4538 tcg_op
= read_fp_dreg(s
, rn
);
4539 tcg_res
= tcg_temp_new_i64();
4542 case 0x0: /* FMOV */
4543 tcg_gen_mov_i64(tcg_res
, tcg_op
);
4545 case 0x1: /* FABS */
4546 gen_helper_vfp_absd(tcg_res
, tcg_op
);
4548 case 0x2: /* FNEG */
4549 gen_helper_vfp_negd(tcg_res
, tcg_op
);
4551 case 0x3: /* FSQRT */
4552 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
4554 case 0x8: /* FRINTN */
4555 case 0x9: /* FRINTP */
4556 case 0xa: /* FRINTM */
4557 case 0xb: /* FRINTZ */
4558 case 0xc: /* FRINTA */
4560 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4562 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4563 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4565 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4566 tcg_temp_free_i32(tcg_rmode
);
4569 case 0xe: /* FRINTX */
4570 gen_helper_rintd_exact(tcg_res
, tcg_op
, fpst
);
4572 case 0xf: /* FRINTI */
4573 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4579 write_fp_dreg(s
, rd
, tcg_res
);
4581 tcg_temp_free_ptr(fpst
);
4582 tcg_temp_free_i64(tcg_op
);
4583 tcg_temp_free_i64(tcg_res
);
4586 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
4587 int rd
, int rn
, int dtype
, int ntype
)
4592 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4594 /* Single to double */
4595 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4596 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
4597 write_fp_dreg(s
, rd
, tcg_rd
);
4598 tcg_temp_free_i64(tcg_rd
);
4600 /* Single to half */
4601 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4602 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4603 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4604 write_fp_sreg(s
, rd
, tcg_rd
);
4605 tcg_temp_free_i32(tcg_rd
);
4607 tcg_temp_free_i32(tcg_rn
);
4612 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
4613 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4615 /* Double to single */
4616 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
4618 /* Double to half */
4619 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4620 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4622 write_fp_sreg(s
, rd
, tcg_rd
);
4623 tcg_temp_free_i32(tcg_rd
);
4624 tcg_temp_free_i64(tcg_rn
);
4629 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4630 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
4632 /* Half to single */
4633 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4634 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, cpu_env
);
4635 write_fp_sreg(s
, rd
, tcg_rd
);
4636 tcg_temp_free_i32(tcg_rd
);
4638 /* Half to double */
4639 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4640 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, cpu_env
);
4641 write_fp_dreg(s
, rd
, tcg_rd
);
4642 tcg_temp_free_i64(tcg_rd
);
4644 tcg_temp_free_i32(tcg_rn
);
4652 /* C3.6.25 Floating point data-processing (1 source)
4653 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
4654 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4655 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
4656 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4658 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
4660 int type
= extract32(insn
, 22, 2);
4661 int opcode
= extract32(insn
, 15, 6);
4662 int rn
= extract32(insn
, 5, 5);
4663 int rd
= extract32(insn
, 0, 5);
4666 case 0x4: case 0x5: case 0x7:
4668 /* FCVT between half, single and double precision */
4669 int dtype
= extract32(opcode
, 0, 2);
4670 if (type
== 2 || dtype
== type
) {
4671 unallocated_encoding(s
);
4674 if (!fp_access_check(s
)) {
4678 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
4684 /* 32-to-32 and 64-to-64 ops */
4687 if (!fp_access_check(s
)) {
4691 handle_fp_1src_single(s
, opcode
, rd
, rn
);
4694 if (!fp_access_check(s
)) {
4698 handle_fp_1src_double(s
, opcode
, rd
, rn
);
4701 unallocated_encoding(s
);
4705 unallocated_encoding(s
);
4710 /* C3.6.26 Floating-point data-processing (2 source) - single precision */
4711 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
4712 int rd
, int rn
, int rm
)
4719 tcg_res
= tcg_temp_new_i32();
4720 fpst
= get_fpstatus_ptr();
4721 tcg_op1
= read_fp_sreg(s
, rn
);
4722 tcg_op2
= read_fp_sreg(s
, rm
);
4725 case 0x0: /* FMUL */
4726 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4728 case 0x1: /* FDIV */
4729 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4731 case 0x2: /* FADD */
4732 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4734 case 0x3: /* FSUB */
4735 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4737 case 0x4: /* FMAX */
4738 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4740 case 0x5: /* FMIN */
4741 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4743 case 0x6: /* FMAXNM */
4744 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4746 case 0x7: /* FMINNM */
4747 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4749 case 0x8: /* FNMUL */
4750 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4751 gen_helper_vfp_negs(tcg_res
, tcg_res
);
4755 write_fp_sreg(s
, rd
, tcg_res
);
4757 tcg_temp_free_ptr(fpst
);
4758 tcg_temp_free_i32(tcg_op1
);
4759 tcg_temp_free_i32(tcg_op2
);
4760 tcg_temp_free_i32(tcg_res
);
4763 /* C3.6.26 Floating-point data-processing (2 source) - double precision */
4764 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
4765 int rd
, int rn
, int rm
)
4772 tcg_res
= tcg_temp_new_i64();
4773 fpst
= get_fpstatus_ptr();
4774 tcg_op1
= read_fp_dreg(s
, rn
);
4775 tcg_op2
= read_fp_dreg(s
, rm
);
4778 case 0x0: /* FMUL */
4779 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4781 case 0x1: /* FDIV */
4782 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4784 case 0x2: /* FADD */
4785 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4787 case 0x3: /* FSUB */
4788 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4790 case 0x4: /* FMAX */
4791 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4793 case 0x5: /* FMIN */
4794 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4796 case 0x6: /* FMAXNM */
4797 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4799 case 0x7: /* FMINNM */
4800 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4802 case 0x8: /* FNMUL */
4803 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4804 gen_helper_vfp_negd(tcg_res
, tcg_res
);
4808 write_fp_dreg(s
, rd
, tcg_res
);
4810 tcg_temp_free_ptr(fpst
);
4811 tcg_temp_free_i64(tcg_op1
);
4812 tcg_temp_free_i64(tcg_op2
);
4813 tcg_temp_free_i64(tcg_res
);
4816 /* C3.6.26 Floating point data-processing (2 source)
4817 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4818 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4819 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
4820 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4822 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
4824 int type
= extract32(insn
, 22, 2);
4825 int rd
= extract32(insn
, 0, 5);
4826 int rn
= extract32(insn
, 5, 5);
4827 int rm
= extract32(insn
, 16, 5);
4828 int opcode
= extract32(insn
, 12, 4);
4831 unallocated_encoding(s
);
4837 if (!fp_access_check(s
)) {
4840 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
4843 if (!fp_access_check(s
)) {
4846 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
4849 unallocated_encoding(s
);
4853 /* C3.6.27 Floating-point data-processing (3 source) - single precision */
4854 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
4855 int rd
, int rn
, int rm
, int ra
)
4857 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
4858 TCGv_i32 tcg_res
= tcg_temp_new_i32();
4859 TCGv_ptr fpst
= get_fpstatus_ptr();
4861 tcg_op1
= read_fp_sreg(s
, rn
);
4862 tcg_op2
= read_fp_sreg(s
, rm
);
4863 tcg_op3
= read_fp_sreg(s
, ra
);
4865 /* These are fused multiply-add, and must be done as one
4866 * floating point operation with no rounding between the
4867 * multiplication and addition steps.
4868 * NB that doing the negations here as separate steps is
4869 * correct : an input NaN should come out with its sign bit
4870 * flipped if it is a negated-input.
4873 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
4877 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
4880 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4882 write_fp_sreg(s
, rd
, tcg_res
);
4884 tcg_temp_free_ptr(fpst
);
4885 tcg_temp_free_i32(tcg_op1
);
4886 tcg_temp_free_i32(tcg_op2
);
4887 tcg_temp_free_i32(tcg_op3
);
4888 tcg_temp_free_i32(tcg_res
);
4891 /* C3.6.27 Floating-point data-processing (3 source) - double precision */
4892 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
4893 int rd
, int rn
, int rm
, int ra
)
4895 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
4896 TCGv_i64 tcg_res
= tcg_temp_new_i64();
4897 TCGv_ptr fpst
= get_fpstatus_ptr();
4899 tcg_op1
= read_fp_dreg(s
, rn
);
4900 tcg_op2
= read_fp_dreg(s
, rm
);
4901 tcg_op3
= read_fp_dreg(s
, ra
);
4903 /* These are fused multiply-add, and must be done as one
4904 * floating point operation with no rounding between the
4905 * multiplication and addition steps.
4906 * NB that doing the negations here as separate steps is
4907 * correct : an input NaN should come out with its sign bit
4908 * flipped if it is a negated-input.
4911 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
4915 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
4918 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4920 write_fp_dreg(s
, rd
, tcg_res
);
4922 tcg_temp_free_ptr(fpst
);
4923 tcg_temp_free_i64(tcg_op1
);
4924 tcg_temp_free_i64(tcg_op2
);
4925 tcg_temp_free_i64(tcg_op3
);
4926 tcg_temp_free_i64(tcg_res
);
4929 /* C3.6.27 Floating point data-processing (3 source)
4930 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
4931 * +---+---+---+-----------+------+----+------+----+------+------+------+
4932 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
4933 * +---+---+---+-----------+------+----+------+----+------+------+------+
4935 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
4937 int type
= extract32(insn
, 22, 2);
4938 int rd
= extract32(insn
, 0, 5);
4939 int rn
= extract32(insn
, 5, 5);
4940 int ra
= extract32(insn
, 10, 5);
4941 int rm
= extract32(insn
, 16, 5);
4942 bool o0
= extract32(insn
, 15, 1);
4943 bool o1
= extract32(insn
, 21, 1);
4947 if (!fp_access_check(s
)) {
4950 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4953 if (!fp_access_check(s
)) {
4956 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4959 unallocated_encoding(s
);
4963 /* C3.6.28 Floating point immediate
4964 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
4965 * +---+---+---+-----------+------+---+------------+-------+------+------+
4966 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
4967 * +---+---+---+-----------+------+---+------------+-------+------+------+
4969 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
4971 int rd
= extract32(insn
, 0, 5);
4972 int imm8
= extract32(insn
, 13, 8);
4973 int is_double
= extract32(insn
, 22, 2);
4977 if (is_double
> 1) {
4978 unallocated_encoding(s
);
4982 if (!fp_access_check(s
)) {
4986 /* The imm8 encodes the sign bit, enough bits to represent
4987 * an exponent in the range 01....1xx to 10....0xx,
4988 * and the most significant 4 bits of the mantissa; see
4989 * VFPExpandImm() in the v8 ARM ARM.
4992 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
4993 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
4994 extract32(imm8
, 0, 6);
4997 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
4998 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
4999 (extract32(imm8
, 0, 6) << 3);
5003 tcg_res
= tcg_const_i64(imm
);
5004 write_fp_dreg(s
, rd
, tcg_res
);
5005 tcg_temp_free_i64(tcg_res
);
5008 /* Handle floating point <=> fixed point conversions. Note that we can
5009 * also deal with fp <=> integer conversions as a special case (scale == 64)
5010 * OPTME: consider handling that special case specially or at least skipping
5011 * the call to scalbn in the helpers for zero shifts.
5013 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
5014 bool itof
, int rmode
, int scale
, int sf
, int type
)
5016 bool is_signed
= !(opcode
& 1);
5017 bool is_double
= type
;
5018 TCGv_ptr tcg_fpstatus
;
5021 tcg_fpstatus
= get_fpstatus_ptr();
5023 tcg_shift
= tcg_const_i32(64 - scale
);
5026 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
5028 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
5031 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
5033 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
5036 tcg_int
= tcg_extend
;
5040 TCGv_i64 tcg_double
= tcg_temp_new_i64();
5042 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
5043 tcg_shift
, tcg_fpstatus
);
5045 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
5046 tcg_shift
, tcg_fpstatus
);
5048 write_fp_dreg(s
, rd
, tcg_double
);
5049 tcg_temp_free_i64(tcg_double
);
5051 TCGv_i32 tcg_single
= tcg_temp_new_i32();
5053 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
5054 tcg_shift
, tcg_fpstatus
);
5056 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
5057 tcg_shift
, tcg_fpstatus
);
5059 write_fp_sreg(s
, rd
, tcg_single
);
5060 tcg_temp_free_i32(tcg_single
);
5063 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
5066 if (extract32(opcode
, 2, 1)) {
5067 /* There are too many rounding modes to all fit into rmode,
5068 * so FCVTA[US] is a special case.
5070 rmode
= FPROUNDING_TIEAWAY
;
5073 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
5075 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
5078 TCGv_i64 tcg_double
= read_fp_dreg(s
, rn
);
5081 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
5082 tcg_shift
, tcg_fpstatus
);
5084 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
5085 tcg_shift
, tcg_fpstatus
);
5089 gen_helper_vfp_tould(tcg_int
, tcg_double
,
5090 tcg_shift
, tcg_fpstatus
);
5092 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
5093 tcg_shift
, tcg_fpstatus
);
5096 tcg_temp_free_i64(tcg_double
);
5098 TCGv_i32 tcg_single
= read_fp_sreg(s
, rn
);
5101 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
5102 tcg_shift
, tcg_fpstatus
);
5104 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
5105 tcg_shift
, tcg_fpstatus
);
5108 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
5110 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
5111 tcg_shift
, tcg_fpstatus
);
5113 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
5114 tcg_shift
, tcg_fpstatus
);
5116 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
5117 tcg_temp_free_i32(tcg_dest
);
5119 tcg_temp_free_i32(tcg_single
);
5122 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
5123 tcg_temp_free_i32(tcg_rmode
);
5126 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
5130 tcg_temp_free_ptr(tcg_fpstatus
);
5131 tcg_temp_free_i32(tcg_shift
);
5134 /* C3.6.29 Floating point <-> fixed point conversions
5135 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
5136 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
5137 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
5138 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
5140 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
5142 int rd
= extract32(insn
, 0, 5);
5143 int rn
= extract32(insn
, 5, 5);
5144 int scale
= extract32(insn
, 10, 6);
5145 int opcode
= extract32(insn
, 16, 3);
5146 int rmode
= extract32(insn
, 19, 2);
5147 int type
= extract32(insn
, 22, 2);
5148 bool sbit
= extract32(insn
, 29, 1);
5149 bool sf
= extract32(insn
, 31, 1);
5152 if (sbit
|| (type
> 1)
5153 || (!sf
&& scale
< 32)) {
5154 unallocated_encoding(s
);
5158 switch ((rmode
<< 3) | opcode
) {
5159 case 0x2: /* SCVTF */
5160 case 0x3: /* UCVTF */
5163 case 0x18: /* FCVTZS */
5164 case 0x19: /* FCVTZU */
5168 unallocated_encoding(s
);
5172 if (!fp_access_check(s
)) {
5176 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
5179 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
5181 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
5182 * without conversion.
5186 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
5192 TCGv_i64 tmp
= tcg_temp_new_i64();
5193 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
5194 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
5195 tcg_gen_movi_i64(tmp
, 0);
5196 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5197 tcg_temp_free_i64(tmp
);
5203 TCGv_i64 tmp
= tcg_const_i64(0);
5204 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
5205 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5206 tcg_temp_free_i64(tmp
);
5210 /* 64 bit to top half. */
5211 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5215 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5220 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
5224 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
5227 /* 64 bits from top half */
5228 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
5234 /* C3.6.30 Floating point <-> integer conversions
5235 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
5236 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
5237 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
5238 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
5240 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
5242 int rd
= extract32(insn
, 0, 5);
5243 int rn
= extract32(insn
, 5, 5);
5244 int opcode
= extract32(insn
, 16, 3);
5245 int rmode
= extract32(insn
, 19, 2);
5246 int type
= extract32(insn
, 22, 2);
5247 bool sbit
= extract32(insn
, 29, 1);
5248 bool sf
= extract32(insn
, 31, 1);
5251 unallocated_encoding(s
);
5257 bool itof
= opcode
& 1;
5260 unallocated_encoding(s
);
5264 switch (sf
<< 3 | type
<< 1 | rmode
) {
5265 case 0x0: /* 32 bit */
5266 case 0xa: /* 64 bit */
5267 case 0xd: /* 64 bit to top half of quad */
5270 /* all other sf/type/rmode combinations are invalid */
5271 unallocated_encoding(s
);
5275 if (!fp_access_check(s
)) {
5278 handle_fmov(s
, rd
, rn
, type
, itof
);
5280 /* actual FP conversions */
5281 bool itof
= extract32(opcode
, 1, 1);
5283 if (type
> 1 || (rmode
!= 0 && opcode
> 1)) {
5284 unallocated_encoding(s
);
5288 if (!fp_access_check(s
)) {
5291 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
5295 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
5296 * 31 30 29 28 25 24 0
5297 * +---+---+---+---------+-----------------------------+
5298 * | | 0 | | 1 1 1 1 | |
5299 * +---+---+---+---------+-----------------------------+
5301 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
5303 if (extract32(insn
, 24, 1)) {
5304 /* Floating point data-processing (3 source) */
5305 disas_fp_3src(s
, insn
);
5306 } else if (extract32(insn
, 21, 1) == 0) {
5307 /* Floating point to fixed point conversions */
5308 disas_fp_fixed_conv(s
, insn
);
5310 switch (extract32(insn
, 10, 2)) {
5312 /* Floating point conditional compare */
5313 disas_fp_ccomp(s
, insn
);
5316 /* Floating point data-processing (2 source) */
5317 disas_fp_2src(s
, insn
);
5320 /* Floating point conditional select */
5321 disas_fp_csel(s
, insn
);
5324 switch (ctz32(extract32(insn
, 12, 4))) {
5325 case 0: /* [15:12] == xxx1 */
5326 /* Floating point immediate */
5327 disas_fp_imm(s
, insn
);
5329 case 1: /* [15:12] == xx10 */
5330 /* Floating point compare */
5331 disas_fp_compare(s
, insn
);
5333 case 2: /* [15:12] == x100 */
5334 /* Floating point data-processing (1 source) */
5335 disas_fp_1src(s
, insn
);
5337 case 3: /* [15:12] == 1000 */
5338 unallocated_encoding(s
);
5340 default: /* [15:12] == 0000 */
5341 /* Floating point <-> integer conversions */
5342 disas_fp_int_conv(s
, insn
);
5350 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
5353 /* Extract 64 bits from the middle of two concatenated 64 bit
5354 * vector register slices left:right. The extracted bits start
5355 * at 'pos' bits into the right (least significant) side.
5356 * We return the result in tcg_right, and guarantee not to
5359 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
5360 assert(pos
> 0 && pos
< 64);
5362 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
5363 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
5364 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
5366 tcg_temp_free_i64(tcg_tmp
);
5370 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
5371 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5372 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
5373 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5375 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
5377 int is_q
= extract32(insn
, 30, 1);
5378 int op2
= extract32(insn
, 22, 2);
5379 int imm4
= extract32(insn
, 11, 4);
5380 int rm
= extract32(insn
, 16, 5);
5381 int rn
= extract32(insn
, 5, 5);
5382 int rd
= extract32(insn
, 0, 5);
5383 int pos
= imm4
<< 3;
5384 TCGv_i64 tcg_resl
, tcg_resh
;
5386 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
5387 unallocated_encoding(s
);
5391 if (!fp_access_check(s
)) {
5395 tcg_resh
= tcg_temp_new_i64();
5396 tcg_resl
= tcg_temp_new_i64();
5398 /* Vd gets bits starting at pos bits into Vm:Vn. This is
5399 * either extracting 128 bits from a 128:128 concatenation, or
5400 * extracting 64 bits from a 64:64 concatenation.
5403 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
5405 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
5406 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
5408 tcg_gen_movi_i64(tcg_resh
, 0);
5415 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
5416 EltPosns
*elt
= eltposns
;
5423 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
5425 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
5428 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
5429 tcg_hh
= tcg_temp_new_i64();
5430 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
5431 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
5432 tcg_temp_free_i64(tcg_hh
);
5436 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5437 tcg_temp_free_i64(tcg_resl
);
5438 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5439 tcg_temp_free_i64(tcg_resh
);
5443 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
5444 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5445 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
5446 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5448 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
5450 int op2
= extract32(insn
, 22, 2);
5451 int is_q
= extract32(insn
, 30, 1);
5452 int rm
= extract32(insn
, 16, 5);
5453 int rn
= extract32(insn
, 5, 5);
5454 int rd
= extract32(insn
, 0, 5);
5455 int is_tblx
= extract32(insn
, 12, 1);
5456 int len
= extract32(insn
, 13, 2);
5457 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
5458 TCGv_i32 tcg_regno
, tcg_numregs
;
5461 unallocated_encoding(s
);
5465 if (!fp_access_check(s
)) {
5469 /* This does a table lookup: for every byte element in the input
5470 * we index into a table formed from up to four vector registers,
5471 * and then the output is the result of the lookups. Our helper
5472 * function does the lookup operation for a single 64 bit part of
5475 tcg_resl
= tcg_temp_new_i64();
5476 tcg_resh
= tcg_temp_new_i64();
5479 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5481 tcg_gen_movi_i64(tcg_resl
, 0);
5483 if (is_tblx
&& is_q
) {
5484 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5486 tcg_gen_movi_i64(tcg_resh
, 0);
5489 tcg_idx
= tcg_temp_new_i64();
5490 tcg_regno
= tcg_const_i32(rn
);
5491 tcg_numregs
= tcg_const_i32(len
+ 1);
5492 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
5493 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
5494 tcg_regno
, tcg_numregs
);
5496 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
5497 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
5498 tcg_regno
, tcg_numregs
);
5500 tcg_temp_free_i64(tcg_idx
);
5501 tcg_temp_free_i32(tcg_regno
);
5502 tcg_temp_free_i32(tcg_numregs
);
5504 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5505 tcg_temp_free_i64(tcg_resl
);
5506 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5507 tcg_temp_free_i64(tcg_resh
);
5510 /* C3.6.3 ZIP/UZP/TRN
5511 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
5512 * +---+---+-------------+------+---+------+---+------------------+------+
5513 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
5514 * +---+---+-------------+------+---+------+---+------------------+------+
5516 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
5518 int rd
= extract32(insn
, 0, 5);
5519 int rn
= extract32(insn
, 5, 5);
5520 int rm
= extract32(insn
, 16, 5);
5521 int size
= extract32(insn
, 22, 2);
5522 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
5523 * bit 2 indicates 1 vs 2 variant of the insn.
5525 int opcode
= extract32(insn
, 12, 2);
5526 bool part
= extract32(insn
, 14, 1);
5527 bool is_q
= extract32(insn
, 30, 1);
5528 int esize
= 8 << size
;
5530 int datasize
= is_q
? 128 : 64;
5531 int elements
= datasize
/ esize
;
5532 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
5534 if (opcode
== 0 || (size
== 3 && !is_q
)) {
5535 unallocated_encoding(s
);
5539 if (!fp_access_check(s
)) {
5543 tcg_resl
= tcg_const_i64(0);
5544 tcg_resh
= tcg_const_i64(0);
5545 tcg_res
= tcg_temp_new_i64();
5547 for (i
= 0; i
< elements
; i
++) {
5549 case 1: /* UZP1/2 */
5551 int midpoint
= elements
/ 2;
5553 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
5555 read_vec_element(s
, tcg_res
, rm
,
5556 2 * (i
- midpoint
) + part
, size
);
5560 case 2: /* TRN1/2 */
5562 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
5564 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
5567 case 3: /* ZIP1/2 */
5569 int base
= part
* elements
/ 2;
5571 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
5573 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
5578 g_assert_not_reached();
5583 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
5584 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
5586 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
5587 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
5591 tcg_temp_free_i64(tcg_res
);
5593 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5594 tcg_temp_free_i64(tcg_resl
);
5595 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5596 tcg_temp_free_i64(tcg_resh
);
5599 static void do_minmaxop(DisasContext
*s
, TCGv_i32 tcg_elt1
, TCGv_i32 tcg_elt2
,
5600 int opc
, bool is_min
, TCGv_ptr fpst
)
5602 /* Helper function for disas_simd_across_lanes: do a single precision
5603 * min/max operation on the specified two inputs,
5604 * and return the result in tcg_elt1.
5608 gen_helper_vfp_minnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5610 gen_helper_vfp_maxnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5615 gen_helper_vfp_mins(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5617 gen_helper_vfp_maxs(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5622 /* C3.6.4 AdvSIMD across lanes
5623 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
5624 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5625 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
5626 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5628 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
5630 int rd
= extract32(insn
, 0, 5);
5631 int rn
= extract32(insn
, 5, 5);
5632 int size
= extract32(insn
, 22, 2);
5633 int opcode
= extract32(insn
, 12, 5);
5634 bool is_q
= extract32(insn
, 30, 1);
5635 bool is_u
= extract32(insn
, 29, 1);
5637 bool is_min
= false;
5641 TCGv_i64 tcg_res
, tcg_elt
;
5644 case 0x1b: /* ADDV */
5646 unallocated_encoding(s
);
5650 case 0x3: /* SADDLV, UADDLV */
5651 case 0xa: /* SMAXV, UMAXV */
5652 case 0x1a: /* SMINV, UMINV */
5653 if (size
== 3 || (size
== 2 && !is_q
)) {
5654 unallocated_encoding(s
);
5658 case 0xc: /* FMAXNMV, FMINNMV */
5659 case 0xf: /* FMAXV, FMINV */
5660 if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
5661 unallocated_encoding(s
);
5664 /* Bit 1 of size field encodes min vs max, and actual size is always
5665 * 32 bits: adjust the size variable so following code can rely on it
5667 is_min
= extract32(size
, 1, 1);
5672 unallocated_encoding(s
);
5676 if (!fp_access_check(s
)) {
5681 elements
= (is_q
? 128 : 64) / esize
;
5683 tcg_res
= tcg_temp_new_i64();
5684 tcg_elt
= tcg_temp_new_i64();
5686 /* These instructions operate across all lanes of a vector
5687 * to produce a single result. We can guarantee that a 64
5688 * bit intermediate is sufficient:
5689 * + for [US]ADDLV the maximum element size is 32 bits, and
5690 * the result type is 64 bits
5691 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
5692 * same as the element size, which is 32 bits at most
5693 * For the integer operations we can choose to work at 64
5694 * or 32 bits and truncate at the end; for simplicity
5695 * we use 64 bits always. The floating point
5696 * ops do require 32 bit intermediates, though.
5699 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
5701 for (i
= 1; i
< elements
; i
++) {
5702 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
5705 case 0x03: /* SADDLV / UADDLV */
5706 case 0x1b: /* ADDV */
5707 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
5709 case 0x0a: /* SMAXV / UMAXV */
5710 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
5712 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5714 case 0x1a: /* SMINV / UMINV */
5715 tcg_gen_movcond_i64(is_u
? TCG_COND_LEU
: TCG_COND_LE
,
5717 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5721 g_assert_not_reached();
5726 /* Floating point ops which work on 32 bit (single) intermediates.
5727 * Note that correct NaN propagation requires that we do these
5728 * operations in exactly the order specified by the pseudocode.
5730 TCGv_i32 tcg_elt1
= tcg_temp_new_i32();
5731 TCGv_i32 tcg_elt2
= tcg_temp_new_i32();
5732 TCGv_i32 tcg_elt3
= tcg_temp_new_i32();
5733 TCGv_ptr fpst
= get_fpstatus_ptr();
5735 assert(esize
== 32);
5736 assert(elements
== 4);
5738 read_vec_element(s
, tcg_elt
, rn
, 0, MO_32
);
5739 tcg_gen_extrl_i64_i32(tcg_elt1
, tcg_elt
);
5740 read_vec_element(s
, tcg_elt
, rn
, 1, MO_32
);
5741 tcg_gen_extrl_i64_i32(tcg_elt2
, tcg_elt
);
5743 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5745 read_vec_element(s
, tcg_elt
, rn
, 2, MO_32
);
5746 tcg_gen_extrl_i64_i32(tcg_elt2
, tcg_elt
);
5747 read_vec_element(s
, tcg_elt
, rn
, 3, MO_32
);
5748 tcg_gen_extrl_i64_i32(tcg_elt3
, tcg_elt
);
5750 do_minmaxop(s
, tcg_elt2
, tcg_elt3
, opcode
, is_min
, fpst
);
5752 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5754 tcg_gen_extu_i32_i64(tcg_res
, tcg_elt1
);
5755 tcg_temp_free_i32(tcg_elt1
);
5756 tcg_temp_free_i32(tcg_elt2
);
5757 tcg_temp_free_i32(tcg_elt3
);
5758 tcg_temp_free_ptr(fpst
);
5761 tcg_temp_free_i64(tcg_elt
);
5763 /* Now truncate the result to the width required for the final output */
5764 if (opcode
== 0x03) {
5765 /* SADDLV, UADDLV: result is 2*esize */
5771 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
5774 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
5777 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
5782 g_assert_not_reached();
5785 write_fp_dreg(s
, rd
, tcg_res
);
5786 tcg_temp_free_i64(tcg_res
);
5789 /* C6.3.31 DUP (Element, Vector)
5791 * 31 30 29 21 20 16 15 10 9 5 4 0
5792 * +---+---+-------------------+--------+-------------+------+------+
5793 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5794 * +---+---+-------------------+--------+-------------+------+------+
5796 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5798 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
5801 int size
= ctz32(imm5
);
5802 int esize
= 8 << size
;
5803 int elements
= (is_q
? 128 : 64) / esize
;
5807 if (size
> 3 || (size
== 3 && !is_q
)) {
5808 unallocated_encoding(s
);
5812 if (!fp_access_check(s
)) {
5816 index
= imm5
>> (size
+ 1);
5818 tmp
= tcg_temp_new_i64();
5819 read_vec_element(s
, tmp
, rn
, index
, size
);
5821 for (i
= 0; i
< elements
; i
++) {
5822 write_vec_element(s
, tmp
, rd
, i
, size
);
5826 clear_vec_high(s
, rd
);
5829 tcg_temp_free_i64(tmp
);
5832 /* C6.3.31 DUP (element, scalar)
5833 * 31 21 20 16 15 10 9 5 4 0
5834 * +-----------------------+--------+-------------+------+------+
5835 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5836 * +-----------------------+--------+-------------+------+------+
5838 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
5841 int size
= ctz32(imm5
);
5846 unallocated_encoding(s
);
5850 if (!fp_access_check(s
)) {
5854 index
= imm5
>> (size
+ 1);
5856 /* This instruction just extracts the specified element and
5857 * zero-extends it into the bottom of the destination register.
5859 tmp
= tcg_temp_new_i64();
5860 read_vec_element(s
, tmp
, rn
, index
, size
);
5861 write_fp_dreg(s
, rd
, tmp
);
5862 tcg_temp_free_i64(tmp
);
5865 /* C6.3.32 DUP (General)
5867 * 31 30 29 21 20 16 15 10 9 5 4 0
5868 * +---+---+-------------------+--------+-------------+------+------+
5869 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
5870 * +---+---+-------------------+--------+-------------+------+------+
5872 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5874 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
5877 int size
= ctz32(imm5
);
5878 int esize
= 8 << size
;
5879 int elements
= (is_q
? 128 : 64)/esize
;
5882 if (size
> 3 || ((size
== 3) && !is_q
)) {
5883 unallocated_encoding(s
);
5887 if (!fp_access_check(s
)) {
5891 for (i
= 0; i
< elements
; i
++) {
5892 write_vec_element(s
, cpu_reg(s
, rn
), rd
, i
, size
);
5895 clear_vec_high(s
, rd
);
5899 /* C6.3.150 INS (Element)
5901 * 31 21 20 16 15 14 11 10 9 5 4 0
5902 * +-----------------------+--------+------------+---+------+------+
5903 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5904 * +-----------------------+--------+------------+---+------+------+
5906 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5907 * index: encoded in imm5<4:size+1>
5909 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
5912 int size
= ctz32(imm5
);
5913 int src_index
, dst_index
;
5917 unallocated_encoding(s
);
5921 if (!fp_access_check(s
)) {
5925 dst_index
= extract32(imm5
, 1+size
, 5);
5926 src_index
= extract32(imm4
, size
, 4);
5928 tmp
= tcg_temp_new_i64();
5930 read_vec_element(s
, tmp
, rn
, src_index
, size
);
5931 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
5933 tcg_temp_free_i64(tmp
);
5937 /* C6.3.151 INS (General)
5939 * 31 21 20 16 15 10 9 5 4 0
5940 * +-----------------------+--------+-------------+------+------+
5941 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
5942 * +-----------------------+--------+-------------+------+------+
5944 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5945 * index: encoded in imm5<4:size+1>
5947 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
5949 int size
= ctz32(imm5
);
5953 unallocated_encoding(s
);
5957 if (!fp_access_check(s
)) {
5961 idx
= extract32(imm5
, 1 + size
, 4 - size
);
5962 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
5966 * C6.3.321 UMOV (General)
5967 * C6.3.237 SMOV (General)
5969 * 31 30 29 21 20 16 15 12 10 9 5 4 0
5970 * +---+---+-------------------+--------+-------------+------+------+
5971 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
5972 * +---+---+-------------------+--------+-------------+------+------+
5974 * U: unsigned when set
5975 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5977 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
5978 int rn
, int rd
, int imm5
)
5980 int size
= ctz32(imm5
);
5984 /* Check for UnallocatedEncodings */
5986 if (size
> 2 || (size
== 2 && !is_q
)) {
5987 unallocated_encoding(s
);
5992 || (size
< 3 && is_q
)
5993 || (size
== 3 && !is_q
)) {
5994 unallocated_encoding(s
);
5999 if (!fp_access_check(s
)) {
6003 element
= extract32(imm5
, 1+size
, 4);
6005 tcg_rd
= cpu_reg(s
, rd
);
6006 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
6007 if (is_signed
&& !is_q
) {
6008 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
6012 /* C3.6.5 AdvSIMD copy
6013 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
6014 * +---+---+----+-----------------+------+---+------+---+------+------+
6015 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6016 * +---+---+----+-----------------+------+---+------+---+------+------+
6018 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
6020 int rd
= extract32(insn
, 0, 5);
6021 int rn
= extract32(insn
, 5, 5);
6022 int imm4
= extract32(insn
, 11, 4);
6023 int op
= extract32(insn
, 29, 1);
6024 int is_q
= extract32(insn
, 30, 1);
6025 int imm5
= extract32(insn
, 16, 5);
6030 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
6032 unallocated_encoding(s
);
6037 /* DUP (element - vector) */
6038 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
6042 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
6047 handle_simd_insg(s
, rd
, rn
, imm5
);
6049 unallocated_encoding(s
);
6054 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
6055 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
6058 unallocated_encoding(s
);
6064 /* C3.6.6 AdvSIMD modified immediate
6065 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
6066 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
6067 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
6068 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
6070 * There are a number of operations that can be carried out here:
6071 * MOVI - move (shifted) imm into register
6072 * MVNI - move inverted (shifted) imm into register
6073 * ORR - bitwise OR of (shifted) imm with register
6074 * BIC - bitwise clear of (shifted) imm with register
6076 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
6078 int rd
= extract32(insn
, 0, 5);
6079 int cmode
= extract32(insn
, 12, 4);
6080 int cmode_3_1
= extract32(cmode
, 1, 3);
6081 int cmode_0
= extract32(cmode
, 0, 1);
6082 int o2
= extract32(insn
, 11, 1);
6083 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
6084 bool is_neg
= extract32(insn
, 29, 1);
6085 bool is_q
= extract32(insn
, 30, 1);
6087 TCGv_i64 tcg_rd
, tcg_imm
;
6090 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
6091 unallocated_encoding(s
);
6095 if (!fp_access_check(s
)) {
6099 /* See AdvSIMDExpandImm() in ARM ARM */
6100 switch (cmode_3_1
) {
6101 case 0: /* Replicate(Zeros(24):imm8, 2) */
6102 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
6103 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
6104 case 3: /* Replicate(imm8:Zeros(24), 2) */
6106 int shift
= cmode_3_1
* 8;
6107 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
6110 case 4: /* Replicate(Zeros(8):imm8, 4) */
6111 case 5: /* Replicate(imm8:Zeros(8), 4) */
6113 int shift
= (cmode_3_1
& 0x1) * 8;
6114 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
6119 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
6120 imm
= (abcdefgh
<< 16) | 0xffff;
6122 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
6123 imm
= (abcdefgh
<< 8) | 0xff;
6125 imm
= bitfield_replicate(imm
, 32);
6128 if (!cmode_0
&& !is_neg
) {
6129 imm
= bitfield_replicate(abcdefgh
, 8);
6130 } else if (!cmode_0
&& is_neg
) {
6133 for (i
= 0; i
< 8; i
++) {
6134 if ((abcdefgh
) & (1 << i
)) {
6135 imm
|= 0xffULL
<< (i
* 8);
6138 } else if (cmode_0
) {
6140 imm
= (abcdefgh
& 0x3f) << 48;
6141 if (abcdefgh
& 0x80) {
6142 imm
|= 0x8000000000000000ULL
;
6144 if (abcdefgh
& 0x40) {
6145 imm
|= 0x3fc0000000000000ULL
;
6147 imm
|= 0x4000000000000000ULL
;
6150 imm
= (abcdefgh
& 0x3f) << 19;
6151 if (abcdefgh
& 0x80) {
6154 if (abcdefgh
& 0x40) {
6165 if (cmode_3_1
!= 7 && is_neg
) {
6169 tcg_imm
= tcg_const_i64(imm
);
6170 tcg_rd
= new_tmp_a64(s
);
6172 for (i
= 0; i
< 2; i
++) {
6173 int foffs
= i
? fp_reg_hi_offset(s
, rd
) : fp_reg_offset(s
, rd
, MO_64
);
6175 if (i
== 1 && !is_q
) {
6176 /* non-quad ops clear high half of vector */
6177 tcg_gen_movi_i64(tcg_rd
, 0);
6178 } else if ((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9) {
6179 tcg_gen_ld_i64(tcg_rd
, cpu_env
, foffs
);
6182 tcg_gen_and_i64(tcg_rd
, tcg_rd
, tcg_imm
);
6185 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_imm
);
6189 tcg_gen_mov_i64(tcg_rd
, tcg_imm
);
6191 tcg_gen_st_i64(tcg_rd
, cpu_env
, foffs
);
6194 tcg_temp_free_i64(tcg_imm
);
6197 /* C3.6.7 AdvSIMD scalar copy
6198 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
6199 * +-----+----+-----------------+------+---+------+---+------+------+
6200 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6201 * +-----+----+-----------------+------+---+------+---+------+------+
6203 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
6205 int rd
= extract32(insn
, 0, 5);
6206 int rn
= extract32(insn
, 5, 5);
6207 int imm4
= extract32(insn
, 11, 4);
6208 int imm5
= extract32(insn
, 16, 5);
6209 int op
= extract32(insn
, 29, 1);
6211 if (op
!= 0 || imm4
!= 0) {
6212 unallocated_encoding(s
);
6216 /* DUP (element, scalar) */
6217 handle_simd_dupes(s
, rd
, rn
, imm5
);
6220 /* C3.6.8 AdvSIMD scalar pairwise
6221 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
6222 * +-----+---+-----------+------+-----------+--------+-----+------+------+
6223 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
6224 * +-----+---+-----------+------+-----------+--------+-----+------+------+
6226 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
6228 int u
= extract32(insn
, 29, 1);
6229 int size
= extract32(insn
, 22, 2);
6230 int opcode
= extract32(insn
, 12, 5);
6231 int rn
= extract32(insn
, 5, 5);
6232 int rd
= extract32(insn
, 0, 5);
6235 /* For some ops (the FP ones), size[1] is part of the encoding.
6236 * For ADDP strictly it is not but size[1] is always 1 for valid
6239 opcode
|= (extract32(size
, 1, 1) << 5);
6242 case 0x3b: /* ADDP */
6243 if (u
|| size
!= 3) {
6244 unallocated_encoding(s
);
6247 if (!fp_access_check(s
)) {
6251 TCGV_UNUSED_PTR(fpst
);
6253 case 0xc: /* FMAXNMP */
6254 case 0xd: /* FADDP */
6255 case 0xf: /* FMAXP */
6256 case 0x2c: /* FMINNMP */
6257 case 0x2f: /* FMINP */
6258 /* FP op, size[0] is 32 or 64 bit */
6260 unallocated_encoding(s
);
6263 if (!fp_access_check(s
)) {
6267 size
= extract32(size
, 0, 1) ? 3 : 2;
6268 fpst
= get_fpstatus_ptr();
6271 unallocated_encoding(s
);
6276 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
6277 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
6278 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6280 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
6281 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
6284 case 0x3b: /* ADDP */
6285 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
6287 case 0xc: /* FMAXNMP */
6288 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6290 case 0xd: /* FADDP */
6291 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6293 case 0xf: /* FMAXP */
6294 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6296 case 0x2c: /* FMINNMP */
6297 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6299 case 0x2f: /* FMINP */
6300 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6303 g_assert_not_reached();
6306 write_fp_dreg(s
, rd
, tcg_res
);
6308 tcg_temp_free_i64(tcg_op1
);
6309 tcg_temp_free_i64(tcg_op2
);
6310 tcg_temp_free_i64(tcg_res
);
6312 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
6313 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
6314 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6316 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_32
);
6317 read_vec_element_i32(s
, tcg_op2
, rn
, 1, MO_32
);
6320 case 0xc: /* FMAXNMP */
6321 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6323 case 0xd: /* FADDP */
6324 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6326 case 0xf: /* FMAXP */
6327 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6329 case 0x2c: /* FMINNMP */
6330 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6332 case 0x2f: /* FMINP */
6333 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6336 g_assert_not_reached();
6339 write_fp_sreg(s
, rd
, tcg_res
);
6341 tcg_temp_free_i32(tcg_op1
);
6342 tcg_temp_free_i32(tcg_op2
);
6343 tcg_temp_free_i32(tcg_res
);
6346 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
6347 tcg_temp_free_ptr(fpst
);
6352 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
6354 * This code is handles the common shifting code and is used by both
6355 * the vector and scalar code.
6357 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6358 TCGv_i64 tcg_rnd
, bool accumulate
,
6359 bool is_u
, int size
, int shift
)
6361 bool extended_result
= false;
6362 bool round
= !TCGV_IS_UNUSED_I64(tcg_rnd
);
6364 TCGv_i64 tcg_src_hi
;
6366 if (round
&& size
== 3) {
6367 extended_result
= true;
6368 ext_lshift
= 64 - shift
;
6369 tcg_src_hi
= tcg_temp_new_i64();
6370 } else if (shift
== 64) {
6371 if (!accumulate
&& is_u
) {
6372 /* result is zero */
6373 tcg_gen_movi_i64(tcg_res
, 0);
6378 /* Deal with the rounding step */
6380 if (extended_result
) {
6381 TCGv_i64 tcg_zero
= tcg_const_i64(0);
6383 /* take care of sign extending tcg_res */
6384 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
6385 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
6386 tcg_src
, tcg_src_hi
,
6389 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
6393 tcg_temp_free_i64(tcg_zero
);
6395 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
6399 /* Now do the shift right */
6400 if (round
&& extended_result
) {
6401 /* extended case, >64 bit precision required */
6402 if (ext_lshift
== 0) {
6403 /* special case, only high bits matter */
6404 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
6406 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6407 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
6408 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
6413 /* essentially shifting in 64 zeros */
6414 tcg_gen_movi_i64(tcg_src
, 0);
6416 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6420 /* effectively extending the sign-bit */
6421 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
6423 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
6429 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
6431 tcg_gen_mov_i64(tcg_res
, tcg_src
);
6434 if (extended_result
) {
6435 tcg_temp_free_i64(tcg_src_hi
);
6439 /* Common SHL/SLI - Shift left with an optional insert */
6440 static void handle_shli_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6441 bool insert
, int shift
)
6443 if (insert
) { /* SLI */
6444 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, shift
, 64 - shift
);
6446 tcg_gen_shli_i64(tcg_res
, tcg_src
, shift
);
6450 /* SRI: shift right with insert */
6451 static void handle_shri_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6452 int size
, int shift
)
6454 int esize
= 8 << size
;
6456 /* shift count same as element size is valid but does nothing;
6457 * special case to avoid potential shift by 64.
6459 if (shift
!= esize
) {
6460 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6461 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, 0, esize
- shift
);
6465 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
6466 static void handle_scalar_simd_shri(DisasContext
*s
,
6467 bool is_u
, int immh
, int immb
,
6468 int opcode
, int rn
, int rd
)
6471 int immhb
= immh
<< 3 | immb
;
6472 int shift
= 2 * (8 << size
) - immhb
;
6473 bool accumulate
= false;
6475 bool insert
= false;
6480 if (!extract32(immh
, 3, 1)) {
6481 unallocated_encoding(s
);
6485 if (!fp_access_check(s
)) {
6490 case 0x02: /* SSRA / USRA (accumulate) */
6493 case 0x04: /* SRSHR / URSHR (rounding) */
6496 case 0x06: /* SRSRA / URSRA (accum + rounding) */
6497 accumulate
= round
= true;
6499 case 0x08: /* SRI */
6505 uint64_t round_const
= 1ULL << (shift
- 1);
6506 tcg_round
= tcg_const_i64(round_const
);
6508 TCGV_UNUSED_I64(tcg_round
);
6511 tcg_rn
= read_fp_dreg(s
, rn
);
6512 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6515 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
6517 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6518 accumulate
, is_u
, size
, shift
);
6521 write_fp_dreg(s
, rd
, tcg_rd
);
6523 tcg_temp_free_i64(tcg_rn
);
6524 tcg_temp_free_i64(tcg_rd
);
6526 tcg_temp_free_i64(tcg_round
);
6530 /* SHL/SLI - Scalar shift left */
6531 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
6532 int immh
, int immb
, int opcode
,
6535 int size
= 32 - clz32(immh
) - 1;
6536 int immhb
= immh
<< 3 | immb
;
6537 int shift
= immhb
- (8 << size
);
6538 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
6539 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
6541 if (!extract32(immh
, 3, 1)) {
6542 unallocated_encoding(s
);
6546 if (!fp_access_check(s
)) {
6550 tcg_rn
= read_fp_dreg(s
, rn
);
6551 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6553 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
6555 write_fp_dreg(s
, rd
, tcg_rd
);
6557 tcg_temp_free_i64(tcg_rn
);
6558 tcg_temp_free_i64(tcg_rd
);
6561 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
6562 * (signed/unsigned) narrowing */
6563 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
6564 bool is_u_shift
, bool is_u_narrow
,
6565 int immh
, int immb
, int opcode
,
6568 int immhb
= immh
<< 3 | immb
;
6569 int size
= 32 - clz32(immh
) - 1;
6570 int esize
= 8 << size
;
6571 int shift
= (2 * esize
) - immhb
;
6572 int elements
= is_scalar
? 1 : (64 / esize
);
6573 bool round
= extract32(opcode
, 0, 1);
6574 TCGMemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
6575 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
6576 TCGv_i32 tcg_rd_narrowed
;
6579 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
6580 { gen_helper_neon_narrow_sat_s8
,
6581 gen_helper_neon_unarrow_sat8
},
6582 { gen_helper_neon_narrow_sat_s16
,
6583 gen_helper_neon_unarrow_sat16
},
6584 { gen_helper_neon_narrow_sat_s32
,
6585 gen_helper_neon_unarrow_sat32
},
6588 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
6589 gen_helper_neon_narrow_sat_u8
,
6590 gen_helper_neon_narrow_sat_u16
,
6591 gen_helper_neon_narrow_sat_u32
,
6594 NeonGenNarrowEnvFn
*narrowfn
;
6600 if (extract32(immh
, 3, 1)) {
6601 unallocated_encoding(s
);
6605 if (!fp_access_check(s
)) {
6610 narrowfn
= unsigned_narrow_fns
[size
];
6612 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
6615 tcg_rn
= tcg_temp_new_i64();
6616 tcg_rd
= tcg_temp_new_i64();
6617 tcg_rd_narrowed
= tcg_temp_new_i32();
6618 tcg_final
= tcg_const_i64(0);
6621 uint64_t round_const
= 1ULL << (shift
- 1);
6622 tcg_round
= tcg_const_i64(round_const
);
6624 TCGV_UNUSED_I64(tcg_round
);
6627 for (i
= 0; i
< elements
; i
++) {
6628 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
6629 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6630 false, is_u_shift
, size
+1, shift
);
6631 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
6632 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
6633 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
6637 clear_vec_high(s
, rd
);
6638 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
6640 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
6644 tcg_temp_free_i64(tcg_round
);
6646 tcg_temp_free_i64(tcg_rn
);
6647 tcg_temp_free_i64(tcg_rd
);
6648 tcg_temp_free_i32(tcg_rd_narrowed
);
6649 tcg_temp_free_i64(tcg_final
);
6653 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
6654 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
6655 bool src_unsigned
, bool dst_unsigned
,
6656 int immh
, int immb
, int rn
, int rd
)
6658 int immhb
= immh
<< 3 | immb
;
6659 int size
= 32 - clz32(immh
) - 1;
6660 int shift
= immhb
- (8 << size
);
6664 assert(!(scalar
&& is_q
));
6667 if (!is_q
&& extract32(immh
, 3, 1)) {
6668 unallocated_encoding(s
);
6672 /* Since we use the variable-shift helpers we must
6673 * replicate the shift count into each element of
6674 * the tcg_shift value.
6678 shift
|= shift
<< 8;
6681 shift
|= shift
<< 16;
6687 g_assert_not_reached();
6691 if (!fp_access_check(s
)) {
6696 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
6697 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
6698 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
6699 { NULL
, gen_helper_neon_qshl_u64
},
6701 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
6702 int maxpass
= is_q
? 2 : 1;
6704 for (pass
= 0; pass
< maxpass
; pass
++) {
6705 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6707 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6708 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6709 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6711 tcg_temp_free_i64(tcg_op
);
6713 tcg_temp_free_i64(tcg_shift
);
6716 clear_vec_high(s
, rd
);
6719 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
6720 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
6722 { gen_helper_neon_qshl_s8
,
6723 gen_helper_neon_qshl_s16
,
6724 gen_helper_neon_qshl_s32
},
6725 { gen_helper_neon_qshlu_s8
,
6726 gen_helper_neon_qshlu_s16
,
6727 gen_helper_neon_qshlu_s32
}
6729 { NULL
, NULL
, NULL
},
6730 { gen_helper_neon_qshl_u8
,
6731 gen_helper_neon_qshl_u16
,
6732 gen_helper_neon_qshl_u32
}
6735 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
6736 TCGMemOp memop
= scalar
? size
: MO_32
;
6737 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
6739 for (pass
= 0; pass
< maxpass
; pass
++) {
6740 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6742 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
6743 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6747 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
6750 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
6755 g_assert_not_reached();
6757 write_fp_sreg(s
, rd
, tcg_op
);
6759 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6762 tcg_temp_free_i32(tcg_op
);
6764 tcg_temp_free_i32(tcg_shift
);
6766 if (!is_q
&& !scalar
) {
6767 clear_vec_high(s
, rd
);
6772 /* Common vector code for handling integer to FP conversion */
6773 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
6774 int elements
, int is_signed
,
6775 int fracbits
, int size
)
6777 bool is_double
= size
== 3 ? true : false;
6778 TCGv_ptr tcg_fpst
= get_fpstatus_ptr();
6779 TCGv_i32 tcg_shift
= tcg_const_i32(fracbits
);
6780 TCGv_i64 tcg_int
= tcg_temp_new_i64();
6781 TCGMemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
6784 for (pass
= 0; pass
< elements
; pass
++) {
6785 read_vec_element(s
, tcg_int
, rn
, pass
, mop
);
6788 TCGv_i64 tcg_double
= tcg_temp_new_i64();
6790 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6791 tcg_shift
, tcg_fpst
);
6793 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6794 tcg_shift
, tcg_fpst
);
6796 if (elements
== 1) {
6797 write_fp_dreg(s
, rd
, tcg_double
);
6799 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
6801 tcg_temp_free_i64(tcg_double
);
6803 TCGv_i32 tcg_single
= tcg_temp_new_i32();
6805 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6806 tcg_shift
, tcg_fpst
);
6808 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6809 tcg_shift
, tcg_fpst
);
6811 if (elements
== 1) {
6812 write_fp_sreg(s
, rd
, tcg_single
);
6814 write_vec_element_i32(s
, tcg_single
, rd
, pass
, MO_32
);
6816 tcg_temp_free_i32(tcg_single
);
6820 if (!is_double
&& elements
== 2) {
6821 clear_vec_high(s
, rd
);
6824 tcg_temp_free_i64(tcg_int
);
6825 tcg_temp_free_ptr(tcg_fpst
);
6826 tcg_temp_free_i32(tcg_shift
);
6829 /* UCVTF/SCVTF - Integer to FP conversion */
6830 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
6831 bool is_q
, bool is_u
,
6832 int immh
, int immb
, int opcode
,
6835 bool is_double
= extract32(immh
, 3, 1);
6836 int size
= is_double
? MO_64
: MO_32
;
6838 int immhb
= immh
<< 3 | immb
;
6839 int fracbits
= (is_double
? 128 : 64) - immhb
;
6841 if (!extract32(immh
, 2, 2)) {
6842 unallocated_encoding(s
);
6849 elements
= is_double
? 2 : is_q
? 4 : 2;
6850 if (is_double
&& !is_q
) {
6851 unallocated_encoding(s
);
6856 if (!fp_access_check(s
)) {
6860 /* immh == 0 would be a failure of the decode logic */
6863 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
6866 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
6867 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
6868 bool is_q
, bool is_u
,
6869 int immh
, int immb
, int rn
, int rd
)
6871 bool is_double
= extract32(immh
, 3, 1);
6872 int immhb
= immh
<< 3 | immb
;
6873 int fracbits
= (is_double
? 128 : 64) - immhb
;
6875 TCGv_ptr tcg_fpstatus
;
6876 TCGv_i32 tcg_rmode
, tcg_shift
;
6878 if (!extract32(immh
, 2, 2)) {
6879 unallocated_encoding(s
);
6883 if (!is_scalar
&& !is_q
&& is_double
) {
6884 unallocated_encoding(s
);
6888 if (!fp_access_check(s
)) {
6892 assert(!(is_scalar
&& is_q
));
6894 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
6895 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6896 tcg_fpstatus
= get_fpstatus_ptr();
6897 tcg_shift
= tcg_const_i32(fracbits
);
6900 int maxpass
= is_scalar
? 1 : 2;
6902 for (pass
= 0; pass
< maxpass
; pass
++) {
6903 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6905 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6907 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6909 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6911 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6912 tcg_temp_free_i64(tcg_op
);
6915 clear_vec_high(s
, rd
);
6918 int maxpass
= is_scalar
? 1 : is_q
? 4 : 2;
6919 for (pass
= 0; pass
< maxpass
; pass
++) {
6920 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6922 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
6924 gen_helper_vfp_touls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6926 gen_helper_vfp_tosls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6929 write_fp_sreg(s
, rd
, tcg_op
);
6931 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6933 tcg_temp_free_i32(tcg_op
);
6935 if (!is_q
&& !is_scalar
) {
6936 clear_vec_high(s
, rd
);
6940 tcg_temp_free_ptr(tcg_fpstatus
);
6941 tcg_temp_free_i32(tcg_shift
);
6942 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6943 tcg_temp_free_i32(tcg_rmode
);
6946 /* C3.6.9 AdvSIMD scalar shift by immediate
6947 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
6948 * +-----+---+-------------+------+------+--------+---+------+------+
6949 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
6950 * +-----+---+-------------+------+------+--------+---+------+------+
6952 * This is the scalar version so it works on a fixed sized registers
6954 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
6956 int rd
= extract32(insn
, 0, 5);
6957 int rn
= extract32(insn
, 5, 5);
6958 int opcode
= extract32(insn
, 11, 5);
6959 int immb
= extract32(insn
, 16, 3);
6960 int immh
= extract32(insn
, 19, 4);
6961 bool is_u
= extract32(insn
, 29, 1);
6964 unallocated_encoding(s
);
6969 case 0x08: /* SRI */
6971 unallocated_encoding(s
);
6975 case 0x00: /* SSHR / USHR */
6976 case 0x02: /* SSRA / USRA */
6977 case 0x04: /* SRSHR / URSHR */
6978 case 0x06: /* SRSRA / URSRA */
6979 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6981 case 0x0a: /* SHL / SLI */
6982 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6984 case 0x1c: /* SCVTF, UCVTF */
6985 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
6988 case 0x10: /* SQSHRUN, SQSHRUN2 */
6989 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
6991 unallocated_encoding(s
);
6994 handle_vec_simd_sqshrn(s
, true, false, false, true,
6995 immh
, immb
, opcode
, rn
, rd
);
6997 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
6998 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
6999 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
7000 immh
, immb
, opcode
, rn
, rd
);
7002 case 0xc: /* SQSHLU */
7004 unallocated_encoding(s
);
7007 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
7009 case 0xe: /* SQSHL, UQSHL */
7010 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
7012 case 0x1f: /* FCVTZS, FCVTZU */
7013 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
7016 unallocated_encoding(s
);
7021 /* C3.6.10 AdvSIMD scalar three different
7022 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
7023 * +-----+---+-----------+------+---+------+--------+-----+------+------+
7024 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
7025 * +-----+---+-----------+------+---+------+--------+-----+------+------+
7027 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
7029 bool is_u
= extract32(insn
, 29, 1);
7030 int size
= extract32(insn
, 22, 2);
7031 int opcode
= extract32(insn
, 12, 4);
7032 int rm
= extract32(insn
, 16, 5);
7033 int rn
= extract32(insn
, 5, 5);
7034 int rd
= extract32(insn
, 0, 5);
7037 unallocated_encoding(s
);
7042 case 0x9: /* SQDMLAL, SQDMLAL2 */
7043 case 0xb: /* SQDMLSL, SQDMLSL2 */
7044 case 0xd: /* SQDMULL, SQDMULL2 */
7045 if (size
== 0 || size
== 3) {
7046 unallocated_encoding(s
);
7051 unallocated_encoding(s
);
7055 if (!fp_access_check(s
)) {
7060 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7061 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7062 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7064 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
7065 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
7067 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
7068 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
7071 case 0xd: /* SQDMULL, SQDMULL2 */
7073 case 0xb: /* SQDMLSL, SQDMLSL2 */
7074 tcg_gen_neg_i64(tcg_res
, tcg_res
);
7076 case 0x9: /* SQDMLAL, SQDMLAL2 */
7077 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
7078 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
7082 g_assert_not_reached();
7085 write_fp_dreg(s
, rd
, tcg_res
);
7087 tcg_temp_free_i64(tcg_op1
);
7088 tcg_temp_free_i64(tcg_op2
);
7089 tcg_temp_free_i64(tcg_res
);
7091 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7092 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7093 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7095 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_16
);
7096 read_vec_element_i32(s
, tcg_op2
, rm
, 0, MO_16
);
7098 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
7099 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
7102 case 0xd: /* SQDMULL, SQDMULL2 */
7104 case 0xb: /* SQDMLSL, SQDMLSL2 */
7105 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
7107 case 0x9: /* SQDMLAL, SQDMLAL2 */
7109 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
7110 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
7111 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
7113 tcg_temp_free_i64(tcg_op3
);
7117 g_assert_not_reached();
7120 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7121 write_fp_dreg(s
, rd
, tcg_res
);
7123 tcg_temp_free_i32(tcg_op1
);
7124 tcg_temp_free_i32(tcg_op2
);
7125 tcg_temp_free_i64(tcg_res
);
7129 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
7130 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
7132 /* Handle 64x64->64 opcodes which are shared between the scalar
7133 * and vector 3-same groups. We cover every opcode where size == 3
7134 * is valid in either the three-reg-same (integer, not pairwise)
7135 * or scalar-three-reg-same groups. (Some opcodes are not yet
7141 case 0x1: /* SQADD */
7143 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7145 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7148 case 0x5: /* SQSUB */
7150 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7152 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7155 case 0x6: /* CMGT, CMHI */
7156 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
7157 * We implement this using setcond (test) and then negating.
7159 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
7161 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
7162 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7164 case 0x7: /* CMGE, CMHS */
7165 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
7167 case 0x11: /* CMTST, CMEQ */
7172 /* CMTST : test is "if (X & Y != 0)". */
7173 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7174 tcg_gen_setcondi_i64(TCG_COND_NE
, tcg_rd
, tcg_rd
, 0);
7175 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7177 case 0x8: /* SSHL, USHL */
7179 gen_helper_neon_shl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
7181 gen_helper_neon_shl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
7184 case 0x9: /* SQSHL, UQSHL */
7186 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7188 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7191 case 0xa: /* SRSHL, URSHL */
7193 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
7195 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
7198 case 0xb: /* SQRSHL, UQRSHL */
7200 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7202 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
7205 case 0x10: /* ADD, SUB */
7207 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7209 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
7213 g_assert_not_reached();
7217 /* Handle the 3-same-operands float operations; shared by the scalar
7218 * and vector encodings. The caller must filter out any encodings
7219 * not allocated for the encoding it is dealing with.
7221 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
7222 int fpopcode
, int rd
, int rn
, int rm
)
7225 TCGv_ptr fpst
= get_fpstatus_ptr();
7227 for (pass
= 0; pass
< elements
; pass
++) {
7230 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7231 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7232 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7234 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
7235 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
7238 case 0x39: /* FMLS */
7239 /* As usual for ARM, separate negation for fused multiply-add */
7240 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
7242 case 0x19: /* FMLA */
7243 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7244 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
7247 case 0x18: /* FMAXNM */
7248 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7250 case 0x1a: /* FADD */
7251 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7253 case 0x1b: /* FMULX */
7254 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7256 case 0x1c: /* FCMEQ */
7257 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7259 case 0x1e: /* FMAX */
7260 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7262 case 0x1f: /* FRECPS */
7263 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7265 case 0x38: /* FMINNM */
7266 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7268 case 0x3a: /* FSUB */
7269 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7271 case 0x3e: /* FMIN */
7272 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7274 case 0x3f: /* FRSQRTS */
7275 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7277 case 0x5b: /* FMUL */
7278 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7280 case 0x5c: /* FCMGE */
7281 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7283 case 0x5d: /* FACGE */
7284 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7286 case 0x5f: /* FDIV */
7287 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7289 case 0x7a: /* FABD */
7290 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7291 gen_helper_vfp_absd(tcg_res
, tcg_res
);
7293 case 0x7c: /* FCMGT */
7294 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7296 case 0x7d: /* FACGT */
7297 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7300 g_assert_not_reached();
7303 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7305 tcg_temp_free_i64(tcg_res
);
7306 tcg_temp_free_i64(tcg_op1
);
7307 tcg_temp_free_i64(tcg_op2
);
7310 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7311 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7312 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7314 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
7315 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
7318 case 0x39: /* FMLS */
7319 /* As usual for ARM, separate negation for fused multiply-add */
7320 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
7322 case 0x19: /* FMLA */
7323 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7324 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
7327 case 0x1a: /* FADD */
7328 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7330 case 0x1b: /* FMULX */
7331 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7333 case 0x1c: /* FCMEQ */
7334 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7336 case 0x1e: /* FMAX */
7337 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7339 case 0x1f: /* FRECPS */
7340 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7342 case 0x18: /* FMAXNM */
7343 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7345 case 0x38: /* FMINNM */
7346 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7348 case 0x3a: /* FSUB */
7349 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7351 case 0x3e: /* FMIN */
7352 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7354 case 0x3f: /* FRSQRTS */
7355 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7357 case 0x5b: /* FMUL */
7358 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7360 case 0x5c: /* FCMGE */
7361 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7363 case 0x5d: /* FACGE */
7364 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7366 case 0x5f: /* FDIV */
7367 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7369 case 0x7a: /* FABD */
7370 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7371 gen_helper_vfp_abss(tcg_res
, tcg_res
);
7373 case 0x7c: /* FCMGT */
7374 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7376 case 0x7d: /* FACGT */
7377 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7380 g_assert_not_reached();
7383 if (elements
== 1) {
7384 /* scalar single so clear high part */
7385 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
7387 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
7388 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
7389 tcg_temp_free_i64(tcg_tmp
);
7391 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7394 tcg_temp_free_i32(tcg_res
);
7395 tcg_temp_free_i32(tcg_op1
);
7396 tcg_temp_free_i32(tcg_op2
);
7400 tcg_temp_free_ptr(fpst
);
7402 if ((elements
<< size
) < 4) {
7403 /* scalar, or non-quad vector op */
7404 clear_vec_high(s
, rd
);
7408 /* C3.6.11 AdvSIMD scalar three same
7409 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
7410 * +-----+---+-----------+------+---+------+--------+---+------+------+
7411 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
7412 * +-----+---+-----------+------+---+------+--------+---+------+------+
7414 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
7416 int rd
= extract32(insn
, 0, 5);
7417 int rn
= extract32(insn
, 5, 5);
7418 int opcode
= extract32(insn
, 11, 5);
7419 int rm
= extract32(insn
, 16, 5);
7420 int size
= extract32(insn
, 22, 2);
7421 bool u
= extract32(insn
, 29, 1);
7424 if (opcode
>= 0x18) {
7425 /* Floating point: U, size[1] and opcode indicate operation */
7426 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
7428 case 0x1b: /* FMULX */
7429 case 0x1f: /* FRECPS */
7430 case 0x3f: /* FRSQRTS */
7431 case 0x5d: /* FACGE */
7432 case 0x7d: /* FACGT */
7433 case 0x1c: /* FCMEQ */
7434 case 0x5c: /* FCMGE */
7435 case 0x7c: /* FCMGT */
7436 case 0x7a: /* FABD */
7439 unallocated_encoding(s
);
7443 if (!fp_access_check(s
)) {
7447 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
7452 case 0x1: /* SQADD, UQADD */
7453 case 0x5: /* SQSUB, UQSUB */
7454 case 0x9: /* SQSHL, UQSHL */
7455 case 0xb: /* SQRSHL, UQRSHL */
7457 case 0x8: /* SSHL, USHL */
7458 case 0xa: /* SRSHL, URSHL */
7459 case 0x6: /* CMGT, CMHI */
7460 case 0x7: /* CMGE, CMHS */
7461 case 0x11: /* CMTST, CMEQ */
7462 case 0x10: /* ADD, SUB (vector) */
7464 unallocated_encoding(s
);
7468 case 0x16: /* SQDMULH, SQRDMULH (vector) */
7469 if (size
!= 1 && size
!= 2) {
7470 unallocated_encoding(s
);
7475 unallocated_encoding(s
);
7479 if (!fp_access_check(s
)) {
7483 tcg_rd
= tcg_temp_new_i64();
7486 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
7487 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
7489 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
7490 tcg_temp_free_i64(tcg_rn
);
7491 tcg_temp_free_i64(tcg_rm
);
7493 /* Do a single operation on the lowest element in the vector.
7494 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
7495 * no side effects for all these operations.
7496 * OPTME: special-purpose helpers would avoid doing some
7497 * unnecessary work in the helper for the 8 and 16 bit cases.
7499 NeonGenTwoOpEnvFn
*genenvfn
;
7500 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
7501 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
7502 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
7504 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
7505 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
7508 case 0x1: /* SQADD, UQADD */
7510 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7511 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
7512 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
7513 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
7515 genenvfn
= fns
[size
][u
];
7518 case 0x5: /* SQSUB, UQSUB */
7520 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7521 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
7522 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
7523 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
7525 genenvfn
= fns
[size
][u
];
7528 case 0x9: /* SQSHL, UQSHL */
7530 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7531 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
7532 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
7533 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
7535 genenvfn
= fns
[size
][u
];
7538 case 0xb: /* SQRSHL, UQRSHL */
7540 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7541 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
7542 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
7543 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
7545 genenvfn
= fns
[size
][u
];
7548 case 0x16: /* SQDMULH, SQRDMULH */
7550 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
7551 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
7552 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
7554 assert(size
== 1 || size
== 2);
7555 genenvfn
= fns
[size
- 1][u
];
7559 g_assert_not_reached();
7562 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
7563 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
7564 tcg_temp_free_i32(tcg_rd32
);
7565 tcg_temp_free_i32(tcg_rn
);
7566 tcg_temp_free_i32(tcg_rm
);
7569 write_fp_dreg(s
, rd
, tcg_rd
);
7571 tcg_temp_free_i64(tcg_rd
);
7574 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
7575 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
7576 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
7578 /* Handle 64->64 opcodes which are shared between the scalar and
7579 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
7580 * is valid in either group and also the double-precision fp ops.
7581 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
7587 case 0x4: /* CLS, CLZ */
7589 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
7591 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
7595 /* This opcode is shared with CNT and RBIT but we have earlier
7596 * enforced that size == 3 if and only if this is the NOT insn.
7598 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
7600 case 0x7: /* SQABS, SQNEG */
7602 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
7604 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
7607 case 0xa: /* CMLT */
7608 /* 64 bit integer comparison against zero, result is
7609 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
7614 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
7615 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7617 case 0x8: /* CMGT, CMGE */
7618 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
7620 case 0x9: /* CMEQ, CMLE */
7621 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
7623 case 0xb: /* ABS, NEG */
7625 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7627 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7628 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7629 tcg_gen_movcond_i64(TCG_COND_GT
, tcg_rd
, tcg_rn
, tcg_zero
,
7631 tcg_temp_free_i64(tcg_zero
);
7634 case 0x2f: /* FABS */
7635 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
7637 case 0x6f: /* FNEG */
7638 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
7640 case 0x7f: /* FSQRT */
7641 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
7643 case 0x1a: /* FCVTNS */
7644 case 0x1b: /* FCVTMS */
7645 case 0x1c: /* FCVTAS */
7646 case 0x3a: /* FCVTPS */
7647 case 0x3b: /* FCVTZS */
7649 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7650 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7651 tcg_temp_free_i32(tcg_shift
);
7654 case 0x5a: /* FCVTNU */
7655 case 0x5b: /* FCVTMU */
7656 case 0x5c: /* FCVTAU */
7657 case 0x7a: /* FCVTPU */
7658 case 0x7b: /* FCVTZU */
7660 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7661 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7662 tcg_temp_free_i32(tcg_shift
);
7665 case 0x18: /* FRINTN */
7666 case 0x19: /* FRINTM */
7667 case 0x38: /* FRINTP */
7668 case 0x39: /* FRINTZ */
7669 case 0x58: /* FRINTA */
7670 case 0x79: /* FRINTI */
7671 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7673 case 0x59: /* FRINTX */
7674 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7677 g_assert_not_reached();
7681 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
7682 bool is_scalar
, bool is_u
, bool is_q
,
7683 int size
, int rn
, int rd
)
7685 bool is_double
= (size
== 3);
7688 if (!fp_access_check(s
)) {
7692 fpst
= get_fpstatus_ptr();
7695 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7696 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7697 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7698 NeonGenTwoDoubleOPFn
*genfn
;
7703 case 0x2e: /* FCMLT (zero) */
7706 case 0x2c: /* FCMGT (zero) */
7707 genfn
= gen_helper_neon_cgt_f64
;
7709 case 0x2d: /* FCMEQ (zero) */
7710 genfn
= gen_helper_neon_ceq_f64
;
7712 case 0x6d: /* FCMLE (zero) */
7715 case 0x6c: /* FCMGE (zero) */
7716 genfn
= gen_helper_neon_cge_f64
;
7719 g_assert_not_reached();
7722 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7723 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7725 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7727 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7729 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7732 clear_vec_high(s
, rd
);
7735 tcg_temp_free_i64(tcg_res
);
7736 tcg_temp_free_i64(tcg_zero
);
7737 tcg_temp_free_i64(tcg_op
);
7739 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7740 TCGv_i32 tcg_zero
= tcg_const_i32(0);
7741 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7742 NeonGenTwoSingleOPFn
*genfn
;
7744 int pass
, maxpasses
;
7747 case 0x2e: /* FCMLT (zero) */
7750 case 0x2c: /* FCMGT (zero) */
7751 genfn
= gen_helper_neon_cgt_f32
;
7753 case 0x2d: /* FCMEQ (zero) */
7754 genfn
= gen_helper_neon_ceq_f32
;
7756 case 0x6d: /* FCMLE (zero) */
7759 case 0x6c: /* FCMGE (zero) */
7760 genfn
= gen_helper_neon_cge_f32
;
7763 g_assert_not_reached();
7769 maxpasses
= is_q
? 4 : 2;
7772 for (pass
= 0; pass
< maxpasses
; pass
++) {
7773 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7775 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7777 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7780 write_fp_sreg(s
, rd
, tcg_res
);
7782 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7785 tcg_temp_free_i32(tcg_res
);
7786 tcg_temp_free_i32(tcg_zero
);
7787 tcg_temp_free_i32(tcg_op
);
7788 if (!is_q
&& !is_scalar
) {
7789 clear_vec_high(s
, rd
);
7793 tcg_temp_free_ptr(fpst
);
7796 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
7797 bool is_scalar
, bool is_u
, bool is_q
,
7798 int size
, int rn
, int rd
)
7800 bool is_double
= (size
== 3);
7801 TCGv_ptr fpst
= get_fpstatus_ptr();
7804 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7805 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7808 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7809 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7811 case 0x3d: /* FRECPE */
7812 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
7814 case 0x3f: /* FRECPX */
7815 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
7817 case 0x7d: /* FRSQRTE */
7818 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
7821 g_assert_not_reached();
7823 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7826 clear_vec_high(s
, rd
);
7829 tcg_temp_free_i64(tcg_res
);
7830 tcg_temp_free_i64(tcg_op
);
7832 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7833 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7834 int pass
, maxpasses
;
7839 maxpasses
= is_q
? 4 : 2;
7842 for (pass
= 0; pass
< maxpasses
; pass
++) {
7843 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7846 case 0x3c: /* URECPE */
7847 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
7849 case 0x3d: /* FRECPE */
7850 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
7852 case 0x3f: /* FRECPX */
7853 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
7855 case 0x7d: /* FRSQRTE */
7856 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
7859 g_assert_not_reached();
7863 write_fp_sreg(s
, rd
, tcg_res
);
7865 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7868 tcg_temp_free_i32(tcg_res
);
7869 tcg_temp_free_i32(tcg_op
);
7870 if (!is_q
&& !is_scalar
) {
7871 clear_vec_high(s
, rd
);
7874 tcg_temp_free_ptr(fpst
);
7877 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
7878 int opcode
, bool u
, bool is_q
,
7879 int size
, int rn
, int rd
)
7881 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
7882 * in the source becomes a size element in the destination).
7885 TCGv_i32 tcg_res
[2];
7886 int destelt
= is_q
? 2 : 0;
7887 int passes
= scalar
? 1 : 2;
7890 tcg_res
[1] = tcg_const_i32(0);
7893 for (pass
= 0; pass
< passes
; pass
++) {
7894 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7895 NeonGenNarrowFn
*genfn
= NULL
;
7896 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
7899 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
7901 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7903 tcg_res
[pass
] = tcg_temp_new_i32();
7906 case 0x12: /* XTN, SQXTUN */
7908 static NeonGenNarrowFn
* const xtnfns
[3] = {
7909 gen_helper_neon_narrow_u8
,
7910 gen_helper_neon_narrow_u16
,
7911 tcg_gen_extrl_i64_i32
,
7913 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
7914 gen_helper_neon_unarrow_sat8
,
7915 gen_helper_neon_unarrow_sat16
,
7916 gen_helper_neon_unarrow_sat32
,
7919 genenvfn
= sqxtunfns
[size
];
7921 genfn
= xtnfns
[size
];
7925 case 0x14: /* SQXTN, UQXTN */
7927 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
7928 { gen_helper_neon_narrow_sat_s8
,
7929 gen_helper_neon_narrow_sat_u8
},
7930 { gen_helper_neon_narrow_sat_s16
,
7931 gen_helper_neon_narrow_sat_u16
},
7932 { gen_helper_neon_narrow_sat_s32
,
7933 gen_helper_neon_narrow_sat_u32
},
7935 genenvfn
= fns
[size
][u
];
7938 case 0x16: /* FCVTN, FCVTN2 */
7939 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
7941 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
7943 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
7944 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
7945 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
7946 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, cpu_env
);
7947 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, cpu_env
);
7948 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
7949 tcg_temp_free_i32(tcg_lo
);
7950 tcg_temp_free_i32(tcg_hi
);
7953 case 0x56: /* FCVTXN, FCVTXN2 */
7954 /* 64 bit to 32 bit float conversion
7955 * with von Neumann rounding (round to odd)
7958 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
7961 g_assert_not_reached();
7965 genfn(tcg_res
[pass
], tcg_op
);
7966 } else if (genenvfn
) {
7967 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
7970 tcg_temp_free_i64(tcg_op
);
7973 for (pass
= 0; pass
< 2; pass
++) {
7974 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
7975 tcg_temp_free_i32(tcg_res
[pass
]);
7978 clear_vec_high(s
, rd
);
7982 /* Remaining saturating accumulating ops */
7983 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
7984 bool is_q
, int size
, int rn
, int rd
)
7986 bool is_double
= (size
== 3);
7989 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
7990 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
7993 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7994 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
7995 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
7997 if (is_u
) { /* USQADD */
7998 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7999 } else { /* SUQADD */
8000 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8002 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
8005 clear_vec_high(s
, rd
);
8008 tcg_temp_free_i64(tcg_rd
);
8009 tcg_temp_free_i64(tcg_rn
);
8011 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
8012 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
8013 int pass
, maxpasses
;
8018 maxpasses
= is_q
? 4 : 2;
8021 for (pass
= 0; pass
< maxpasses
; pass
++) {
8023 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
8024 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
8026 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
8027 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
8030 if (is_u
) { /* USQADD */
8033 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8036 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8039 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8042 g_assert_not_reached();
8044 } else { /* SUQADD */
8047 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8050 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8053 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
8056 g_assert_not_reached();
8061 TCGv_i64 tcg_zero
= tcg_const_i64(0);
8062 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
8063 tcg_temp_free_i64(tcg_zero
);
8065 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
8069 clear_vec_high(s
, rd
);
8072 tcg_temp_free_i32(tcg_rd
);
8073 tcg_temp_free_i32(tcg_rn
);
8077 /* C3.6.12 AdvSIMD scalar two reg misc
8078 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
8079 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8080 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
8081 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8083 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
8085 int rd
= extract32(insn
, 0, 5);
8086 int rn
= extract32(insn
, 5, 5);
8087 int opcode
= extract32(insn
, 12, 5);
8088 int size
= extract32(insn
, 22, 2);
8089 bool u
= extract32(insn
, 29, 1);
8090 bool is_fcvt
= false;
8093 TCGv_ptr tcg_fpstatus
;
8096 case 0x3: /* USQADD / SUQADD*/
8097 if (!fp_access_check(s
)) {
8100 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
8102 case 0x7: /* SQABS / SQNEG */
8104 case 0xa: /* CMLT */
8106 unallocated_encoding(s
);
8110 case 0x8: /* CMGT, CMGE */
8111 case 0x9: /* CMEQ, CMLE */
8112 case 0xb: /* ABS, NEG */
8114 unallocated_encoding(s
);
8118 case 0x12: /* SQXTUN */
8120 unallocated_encoding(s
);
8124 case 0x14: /* SQXTN, UQXTN */
8126 unallocated_encoding(s
);
8129 if (!fp_access_check(s
)) {
8132 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
8137 /* Floating point: U, size[1] and opcode indicate operation;
8138 * size[0] indicates single or double precision.
8140 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
8141 size
= extract32(size
, 0, 1) ? 3 : 2;
8143 case 0x2c: /* FCMGT (zero) */
8144 case 0x2d: /* FCMEQ (zero) */
8145 case 0x2e: /* FCMLT (zero) */
8146 case 0x6c: /* FCMGE (zero) */
8147 case 0x6d: /* FCMLE (zero) */
8148 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
8150 case 0x1d: /* SCVTF */
8151 case 0x5d: /* UCVTF */
8153 bool is_signed
= (opcode
== 0x1d);
8154 if (!fp_access_check(s
)) {
8157 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
8160 case 0x3d: /* FRECPE */
8161 case 0x3f: /* FRECPX */
8162 case 0x7d: /* FRSQRTE */
8163 if (!fp_access_check(s
)) {
8166 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
8168 case 0x1a: /* FCVTNS */
8169 case 0x1b: /* FCVTMS */
8170 case 0x3a: /* FCVTPS */
8171 case 0x3b: /* FCVTZS */
8172 case 0x5a: /* FCVTNU */
8173 case 0x5b: /* FCVTMU */
8174 case 0x7a: /* FCVTPU */
8175 case 0x7b: /* FCVTZU */
8177 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
8179 case 0x1c: /* FCVTAS */
8180 case 0x5c: /* FCVTAU */
8181 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
8183 rmode
= FPROUNDING_TIEAWAY
;
8185 case 0x56: /* FCVTXN, FCVTXN2 */
8187 unallocated_encoding(s
);
8190 if (!fp_access_check(s
)) {
8193 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
8196 unallocated_encoding(s
);
8201 unallocated_encoding(s
);
8205 if (!fp_access_check(s
)) {
8210 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
8211 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
8212 tcg_fpstatus
= get_fpstatus_ptr();
8214 TCGV_UNUSED_I32(tcg_rmode
);
8215 TCGV_UNUSED_PTR(tcg_fpstatus
);
8219 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
8220 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
8222 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
8223 write_fp_dreg(s
, rd
, tcg_rd
);
8224 tcg_temp_free_i64(tcg_rd
);
8225 tcg_temp_free_i64(tcg_rn
);
8227 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
8228 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
8230 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
8233 case 0x7: /* SQABS, SQNEG */
8235 NeonGenOneOpEnvFn
*genfn
;
8236 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
8237 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
8238 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
8239 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
8241 genfn
= fns
[size
][u
];
8242 genfn(tcg_rd
, cpu_env
, tcg_rn
);
8245 case 0x1a: /* FCVTNS */
8246 case 0x1b: /* FCVTMS */
8247 case 0x1c: /* FCVTAS */
8248 case 0x3a: /* FCVTPS */
8249 case 0x3b: /* FCVTZS */
8251 TCGv_i32 tcg_shift
= tcg_const_i32(0);
8252 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
8253 tcg_temp_free_i32(tcg_shift
);
8256 case 0x5a: /* FCVTNU */
8257 case 0x5b: /* FCVTMU */
8258 case 0x5c: /* FCVTAU */
8259 case 0x7a: /* FCVTPU */
8260 case 0x7b: /* FCVTZU */
8262 TCGv_i32 tcg_shift
= tcg_const_i32(0);
8263 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
8264 tcg_temp_free_i32(tcg_shift
);
8268 g_assert_not_reached();
8271 write_fp_sreg(s
, rd
, tcg_rd
);
8272 tcg_temp_free_i32(tcg_rd
);
8273 tcg_temp_free_i32(tcg_rn
);
8277 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
8278 tcg_temp_free_i32(tcg_rmode
);
8279 tcg_temp_free_ptr(tcg_fpstatus
);
8283 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
8284 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
8285 int immh
, int immb
, int opcode
, int rn
, int rd
)
8287 int size
= 32 - clz32(immh
) - 1;
8288 int immhb
= immh
<< 3 | immb
;
8289 int shift
= 2 * (8 << size
) - immhb
;
8290 bool accumulate
= false;
8292 bool insert
= false;
8293 int dsize
= is_q
? 128 : 64;
8294 int esize
= 8 << size
;
8295 int elements
= dsize
/esize
;
8296 TCGMemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
8297 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8298 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8302 if (extract32(immh
, 3, 1) && !is_q
) {
8303 unallocated_encoding(s
);
8307 if (size
> 3 && !is_q
) {
8308 unallocated_encoding(s
);
8312 if (!fp_access_check(s
)) {
8317 case 0x02: /* SSRA / USRA (accumulate) */
8320 case 0x04: /* SRSHR / URSHR (rounding) */
8323 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8324 accumulate
= round
= true;
8326 case 0x08: /* SRI */
8332 uint64_t round_const
= 1ULL << (shift
- 1);
8333 tcg_round
= tcg_const_i64(round_const
);
8335 TCGV_UNUSED_I64(tcg_round
);
8338 for (i
= 0; i
< elements
; i
++) {
8339 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
8340 if (accumulate
|| insert
) {
8341 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
8345 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
8347 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8348 accumulate
, is_u
, size
, shift
);
8351 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
8355 clear_vec_high(s
, rd
);
8359 tcg_temp_free_i64(tcg_round
);
8363 /* SHL/SLI - Vector shift left */
8364 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
8365 int immh
, int immb
, int opcode
, int rn
, int rd
)
8367 int size
= 32 - clz32(immh
) - 1;
8368 int immhb
= immh
<< 3 | immb
;
8369 int shift
= immhb
- (8 << size
);
8370 int dsize
= is_q
? 128 : 64;
8371 int esize
= 8 << size
;
8372 int elements
= dsize
/esize
;
8373 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8374 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8377 if (extract32(immh
, 3, 1) && !is_q
) {
8378 unallocated_encoding(s
);
8382 if (size
> 3 && !is_q
) {
8383 unallocated_encoding(s
);
8387 if (!fp_access_check(s
)) {
8391 for (i
= 0; i
< elements
; i
++) {
8392 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
8394 read_vec_element(s
, tcg_rd
, rd
, i
, size
);
8397 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
8399 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
8403 clear_vec_high(s
, rd
);
8407 /* USHLL/SHLL - Vector shift left with widening */
8408 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
8409 int immh
, int immb
, int opcode
, int rn
, int rd
)
8411 int size
= 32 - clz32(immh
) - 1;
8412 int immhb
= immh
<< 3 | immb
;
8413 int shift
= immhb
- (8 << size
);
8415 int esize
= 8 << size
;
8416 int elements
= dsize
/esize
;
8417 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8418 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8422 unallocated_encoding(s
);
8426 if (!fp_access_check(s
)) {
8430 /* For the LL variants the store is larger than the load,
8431 * so if rd == rn we would overwrite parts of our input.
8432 * So load everything right now and use shifts in the main loop.
8434 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
8436 for (i
= 0; i
< elements
; i
++) {
8437 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
8438 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
8439 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
8440 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
8444 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
8445 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
8446 int immh
, int immb
, int opcode
, int rn
, int rd
)
8448 int immhb
= immh
<< 3 | immb
;
8449 int size
= 32 - clz32(immh
) - 1;
8451 int esize
= 8 << size
;
8452 int elements
= dsize
/esize
;
8453 int shift
= (2 * esize
) - immhb
;
8454 bool round
= extract32(opcode
, 0, 1);
8455 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
8459 if (extract32(immh
, 3, 1)) {
8460 unallocated_encoding(s
);
8464 if (!fp_access_check(s
)) {
8468 tcg_rn
= tcg_temp_new_i64();
8469 tcg_rd
= tcg_temp_new_i64();
8470 tcg_final
= tcg_temp_new_i64();
8471 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
8474 uint64_t round_const
= 1ULL << (shift
- 1);
8475 tcg_round
= tcg_const_i64(round_const
);
8477 TCGV_UNUSED_I64(tcg_round
);
8480 for (i
= 0; i
< elements
; i
++) {
8481 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
8482 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8483 false, true, size
+1, shift
);
8485 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8489 clear_vec_high(s
, rd
);
8490 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8492 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8496 tcg_temp_free_i64(tcg_round
);
8498 tcg_temp_free_i64(tcg_rn
);
8499 tcg_temp_free_i64(tcg_rd
);
8500 tcg_temp_free_i64(tcg_final
);
8505 /* C3.6.14 AdvSIMD shift by immediate
8506 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8507 * +---+---+---+-------------+------+------+--------+---+------+------+
8508 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8509 * +---+---+---+-------------+------+------+--------+---+------+------+
8511 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
8513 int rd
= extract32(insn
, 0, 5);
8514 int rn
= extract32(insn
, 5, 5);
8515 int opcode
= extract32(insn
, 11, 5);
8516 int immb
= extract32(insn
, 16, 3);
8517 int immh
= extract32(insn
, 19, 4);
8518 bool is_u
= extract32(insn
, 29, 1);
8519 bool is_q
= extract32(insn
, 30, 1);
8522 case 0x08: /* SRI */
8524 unallocated_encoding(s
);
8528 case 0x00: /* SSHR / USHR */
8529 case 0x02: /* SSRA / USRA (accumulate) */
8530 case 0x04: /* SRSHR / URSHR (rounding) */
8531 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8532 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8534 case 0x0a: /* SHL / SLI */
8535 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8537 case 0x10: /* SHRN */
8538 case 0x11: /* RSHRN / SQRSHRUN */
8540 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
8543 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
8546 case 0x12: /* SQSHRN / UQSHRN */
8547 case 0x13: /* SQRSHRN / UQRSHRN */
8548 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
8551 case 0x14: /* SSHLL / USHLL */
8552 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8554 case 0x1c: /* SCVTF / UCVTF */
8555 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
8558 case 0xc: /* SQSHLU */
8560 unallocated_encoding(s
);
8563 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
8565 case 0xe: /* SQSHL, UQSHL */
8566 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
8568 case 0x1f: /* FCVTZS/ FCVTZU */
8569 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
8572 unallocated_encoding(s
);
8577 /* Generate code to do a "long" addition or subtraction, ie one done in
8578 * TCGv_i64 on vector lanes twice the width specified by size.
8580 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
8581 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
8583 static NeonGenTwo64OpFn
* const fns
[3][2] = {
8584 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
8585 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
8586 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
8588 NeonGenTwo64OpFn
*genfn
;
8591 genfn
= fns
[size
][is_sub
];
8592 genfn(tcg_res
, tcg_op1
, tcg_op2
);
8595 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
8596 int opcode
, int rd
, int rn
, int rm
)
8598 /* 3-reg-different widening insns: 64 x 64 -> 128 */
8599 TCGv_i64 tcg_res
[2];
8602 tcg_res
[0] = tcg_temp_new_i64();
8603 tcg_res
[1] = tcg_temp_new_i64();
8605 /* Does this op do an adding accumulate, a subtracting accumulate,
8606 * or no accumulate at all?
8624 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8625 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8628 /* size == 2 means two 32x32->64 operations; this is worth special
8629 * casing because we can generally handle it inline.
8632 for (pass
= 0; pass
< 2; pass
++) {
8633 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8634 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8635 TCGv_i64 tcg_passres
;
8636 TCGMemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
8638 int elt
= pass
+ is_q
* 2;
8640 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
8641 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
8644 tcg_passres
= tcg_res
[pass
];
8646 tcg_passres
= tcg_temp_new_i64();
8650 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8651 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8653 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8654 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8656 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8657 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8659 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
8660 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
8662 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
8663 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
8664 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
8666 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
8667 tcg_temp_free_i64(tcg_tmp1
);
8668 tcg_temp_free_i64(tcg_tmp2
);
8671 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8672 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8673 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8674 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8676 case 9: /* SQDMLAL, SQDMLAL2 */
8677 case 11: /* SQDMLSL, SQDMLSL2 */
8678 case 13: /* SQDMULL, SQDMULL2 */
8679 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8680 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
8681 tcg_passres
, tcg_passres
);
8684 g_assert_not_reached();
8687 if (opcode
== 9 || opcode
== 11) {
8688 /* saturating accumulate ops */
8690 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
8692 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
8693 tcg_res
[pass
], tcg_passres
);
8694 } else if (accop
> 0) {
8695 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8696 } else if (accop
< 0) {
8697 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8701 tcg_temp_free_i64(tcg_passres
);
8704 tcg_temp_free_i64(tcg_op1
);
8705 tcg_temp_free_i64(tcg_op2
);
8708 /* size 0 or 1, generally helper functions */
8709 for (pass
= 0; pass
< 2; pass
++) {
8710 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8711 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8712 TCGv_i64 tcg_passres
;
8713 int elt
= pass
+ is_q
* 2;
8715 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
8716 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
8719 tcg_passres
= tcg_res
[pass
];
8721 tcg_passres
= tcg_temp_new_i64();
8725 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8726 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8728 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
8729 static NeonGenWidenFn
* const widenfns
[2][2] = {
8730 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8731 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8733 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8735 widenfn(tcg_op2_64
, tcg_op2
);
8736 widenfn(tcg_passres
, tcg_op1
);
8737 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
8738 tcg_passres
, tcg_op2_64
);
8739 tcg_temp_free_i64(tcg_op2_64
);
8742 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8743 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8746 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8748 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8752 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
8754 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
8758 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8759 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8760 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8763 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
8765 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
8769 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8771 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8775 case 9: /* SQDMLAL, SQDMLAL2 */
8776 case 11: /* SQDMLSL, SQDMLSL2 */
8777 case 13: /* SQDMULL, SQDMULL2 */
8779 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8780 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
8781 tcg_passres
, tcg_passres
);
8783 case 14: /* PMULL */
8785 gen_helper_neon_mull_p8(tcg_passres
, tcg_op1
, tcg_op2
);
8788 g_assert_not_reached();
8790 tcg_temp_free_i32(tcg_op1
);
8791 tcg_temp_free_i32(tcg_op2
);
8794 if (opcode
== 9 || opcode
== 11) {
8795 /* saturating accumulate ops */
8797 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
8799 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
8803 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
8804 tcg_res
[pass
], tcg_passres
);
8806 tcg_temp_free_i64(tcg_passres
);
8811 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8812 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8813 tcg_temp_free_i64(tcg_res
[0]);
8814 tcg_temp_free_i64(tcg_res
[1]);
8817 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
8818 int opcode
, int rd
, int rn
, int rm
)
8820 TCGv_i64 tcg_res
[2];
8821 int part
= is_q
? 2 : 0;
8824 for (pass
= 0; pass
< 2; pass
++) {
8825 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8826 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8827 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
8828 static NeonGenWidenFn
* const widenfns
[3][2] = {
8829 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8830 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8831 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
8833 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8835 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8836 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
8837 widenfn(tcg_op2_wide
, tcg_op2
);
8838 tcg_temp_free_i32(tcg_op2
);
8839 tcg_res
[pass
] = tcg_temp_new_i64();
8840 gen_neon_addl(size
, (opcode
== 3),
8841 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
8842 tcg_temp_free_i64(tcg_op1
);
8843 tcg_temp_free_i64(tcg_op2_wide
);
8846 for (pass
= 0; pass
< 2; pass
++) {
8847 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8848 tcg_temp_free_i64(tcg_res
[pass
]);
8852 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
8854 tcg_gen_addi_i64(in
, in
, 1U << 31);
8855 tcg_gen_extrh_i64_i32(res
, in
);
8858 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
8859 int opcode
, int rd
, int rn
, int rm
)
8861 TCGv_i32 tcg_res
[2];
8862 int part
= is_q
? 2 : 0;
8865 for (pass
= 0; pass
< 2; pass
++) {
8866 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8867 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8868 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
8869 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
8870 { gen_helper_neon_narrow_high_u8
,
8871 gen_helper_neon_narrow_round_high_u8
},
8872 { gen_helper_neon_narrow_high_u16
,
8873 gen_helper_neon_narrow_round_high_u16
},
8874 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
8876 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
8878 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8879 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8881 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
8883 tcg_temp_free_i64(tcg_op1
);
8884 tcg_temp_free_i64(tcg_op2
);
8886 tcg_res
[pass
] = tcg_temp_new_i32();
8887 gennarrow(tcg_res
[pass
], tcg_wideres
);
8888 tcg_temp_free_i64(tcg_wideres
);
8891 for (pass
= 0; pass
< 2; pass
++) {
8892 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
8893 tcg_temp_free_i32(tcg_res
[pass
]);
8896 clear_vec_high(s
, rd
);
8900 static void handle_pmull_64(DisasContext
*s
, int is_q
, int rd
, int rn
, int rm
)
8902 /* PMULL of 64 x 64 -> 128 is an odd special case because it
8903 * is the only three-reg-diff instruction which produces a
8904 * 128-bit wide result from a single operation. However since
8905 * it's possible to calculate the two halves more or less
8906 * separately we just use two helper calls.
8908 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8909 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8910 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8912 read_vec_element(s
, tcg_op1
, rn
, is_q
, MO_64
);
8913 read_vec_element(s
, tcg_op2
, rm
, is_q
, MO_64
);
8914 gen_helper_neon_pmull_64_lo(tcg_res
, tcg_op1
, tcg_op2
);
8915 write_vec_element(s
, tcg_res
, rd
, 0, MO_64
);
8916 gen_helper_neon_pmull_64_hi(tcg_res
, tcg_op1
, tcg_op2
);
8917 write_vec_element(s
, tcg_res
, rd
, 1, MO_64
);
8919 tcg_temp_free_i64(tcg_op1
);
8920 tcg_temp_free_i64(tcg_op2
);
8921 tcg_temp_free_i64(tcg_res
);
8924 /* C3.6.15 AdvSIMD three different
8925 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8926 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8927 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8928 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8930 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8932 /* Instructions in this group fall into three basic classes
8933 * (in each case with the operation working on each element in
8934 * the input vectors):
8935 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
8937 * (2) wide 64 x 128 -> 128
8938 * (3) narrowing 128 x 128 -> 64
8939 * Here we do initial decode, catch unallocated cases and
8940 * dispatch to separate functions for each class.
8942 int is_q
= extract32(insn
, 30, 1);
8943 int is_u
= extract32(insn
, 29, 1);
8944 int size
= extract32(insn
, 22, 2);
8945 int opcode
= extract32(insn
, 12, 4);
8946 int rm
= extract32(insn
, 16, 5);
8947 int rn
= extract32(insn
, 5, 5);
8948 int rd
= extract32(insn
, 0, 5);
8951 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
8952 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
8953 /* 64 x 128 -> 128 */
8955 unallocated_encoding(s
);
8958 if (!fp_access_check(s
)) {
8961 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8963 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
8964 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
8965 /* 128 x 128 -> 64 */
8967 unallocated_encoding(s
);
8970 if (!fp_access_check(s
)) {
8973 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8975 case 14: /* PMULL, PMULL2 */
8976 if (is_u
|| size
== 1 || size
== 2) {
8977 unallocated_encoding(s
);
8981 if (!arm_dc_feature(s
, ARM_FEATURE_V8_PMULL
)) {
8982 unallocated_encoding(s
);
8985 if (!fp_access_check(s
)) {
8988 handle_pmull_64(s
, is_q
, rd
, rn
, rm
);
8992 case 9: /* SQDMLAL, SQDMLAL2 */
8993 case 11: /* SQDMLSL, SQDMLSL2 */
8994 case 13: /* SQDMULL, SQDMULL2 */
8995 if (is_u
|| size
== 0) {
8996 unallocated_encoding(s
);
9000 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
9001 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
9002 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
9003 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
9004 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
9005 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
9006 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
9007 /* 64 x 64 -> 128 */
9009 unallocated_encoding(s
);
9013 if (!fp_access_check(s
)) {
9017 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
9020 /* opcode 15 not allocated */
9021 unallocated_encoding(s
);
9026 /* Logic op (opcode == 3) subgroup of C3.6.16. */
9027 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
9029 int rd
= extract32(insn
, 0, 5);
9030 int rn
= extract32(insn
, 5, 5);
9031 int rm
= extract32(insn
, 16, 5);
9032 int size
= extract32(insn
, 22, 2);
9033 bool is_u
= extract32(insn
, 29, 1);
9034 bool is_q
= extract32(insn
, 30, 1);
9035 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
9038 if (!fp_access_check(s
)) {
9042 tcg_op1
= tcg_temp_new_i64();
9043 tcg_op2
= tcg_temp_new_i64();
9044 tcg_res
[0] = tcg_temp_new_i64();
9045 tcg_res
[1] = tcg_temp_new_i64();
9047 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
9048 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9049 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9054 tcg_gen_and_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9057 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9060 tcg_gen_or_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9063 tcg_gen_orc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9068 /* B* ops need res loaded to operate on */
9069 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9074 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9076 case 1: /* BSL bitwise select */
9077 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_op2
);
9078 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
9079 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op1
);
9081 case 2: /* BIT, bitwise insert if true */
9082 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
9083 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_op2
);
9084 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9086 case 3: /* BIF, bitwise insert if false */
9087 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
9088 tcg_gen_andc_i64(tcg_op1
, tcg_op1
, tcg_op2
);
9089 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9095 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
9097 tcg_gen_movi_i64(tcg_res
[1], 0);
9099 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
9101 tcg_temp_free_i64(tcg_op1
);
9102 tcg_temp_free_i64(tcg_op2
);
9103 tcg_temp_free_i64(tcg_res
[0]);
9104 tcg_temp_free_i64(tcg_res
[1]);
9107 /* Helper functions for 32 bit comparisons */
9108 static void gen_max_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9110 tcg_gen_movcond_i32(TCG_COND_GE
, res
, op1
, op2
, op1
, op2
);
9113 static void gen_max_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9115 tcg_gen_movcond_i32(TCG_COND_GEU
, res
, op1
, op2
, op1
, op2
);
9118 static void gen_min_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9120 tcg_gen_movcond_i32(TCG_COND_LE
, res
, op1
, op2
, op1
, op2
);
9123 static void gen_min_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
9125 tcg_gen_movcond_i32(TCG_COND_LEU
, res
, op1
, op2
, op1
, op2
);
9128 /* Pairwise op subgroup of C3.6.16.
9130 * This is called directly or via the handle_3same_float for float pairwise
9131 * operations where the opcode and size are calculated differently.
9133 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
9134 int size
, int rn
, int rm
, int rd
)
9139 /* Floating point operations need fpst */
9140 if (opcode
>= 0x58) {
9141 fpst
= get_fpstatus_ptr();
9143 TCGV_UNUSED_PTR(fpst
);
9146 if (!fp_access_check(s
)) {
9150 /* These operations work on the concatenated rm:rn, with each pair of
9151 * adjacent elements being operated on to produce an element in the result.
9154 TCGv_i64 tcg_res
[2];
9156 for (pass
= 0; pass
< 2; pass
++) {
9157 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9158 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9159 int passreg
= (pass
== 0) ? rn
: rm
;
9161 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
9162 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
9163 tcg_res
[pass
] = tcg_temp_new_i64();
9166 case 0x17: /* ADDP */
9167 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9169 case 0x58: /* FMAXNMP */
9170 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9172 case 0x5a: /* FADDP */
9173 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9175 case 0x5e: /* FMAXP */
9176 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9178 case 0x78: /* FMINNMP */
9179 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9181 case 0x7e: /* FMINP */
9182 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9185 g_assert_not_reached();
9188 tcg_temp_free_i64(tcg_op1
);
9189 tcg_temp_free_i64(tcg_op2
);
9192 for (pass
= 0; pass
< 2; pass
++) {
9193 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9194 tcg_temp_free_i64(tcg_res
[pass
]);
9197 int maxpass
= is_q
? 4 : 2;
9198 TCGv_i32 tcg_res
[4];
9200 for (pass
= 0; pass
< maxpass
; pass
++) {
9201 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9202 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9203 NeonGenTwoOpFn
*genfn
= NULL
;
9204 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
9205 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
9207 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
9208 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
9209 tcg_res
[pass
] = tcg_temp_new_i32();
9212 case 0x17: /* ADDP */
9214 static NeonGenTwoOpFn
* const fns
[3] = {
9215 gen_helper_neon_padd_u8
,
9216 gen_helper_neon_padd_u16
,
9222 case 0x14: /* SMAXP, UMAXP */
9224 static NeonGenTwoOpFn
* const fns
[3][2] = {
9225 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
9226 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
9227 { gen_max_s32
, gen_max_u32
},
9229 genfn
= fns
[size
][u
];
9232 case 0x15: /* SMINP, UMINP */
9234 static NeonGenTwoOpFn
* const fns
[3][2] = {
9235 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
9236 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
9237 { gen_min_s32
, gen_min_u32
},
9239 genfn
= fns
[size
][u
];
9242 /* The FP operations are all on single floats (32 bit) */
9243 case 0x58: /* FMAXNMP */
9244 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9246 case 0x5a: /* FADDP */
9247 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9249 case 0x5e: /* FMAXP */
9250 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9252 case 0x78: /* FMINNMP */
9253 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9255 case 0x7e: /* FMINP */
9256 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
9259 g_assert_not_reached();
9262 /* FP ops called directly, otherwise call now */
9264 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9267 tcg_temp_free_i32(tcg_op1
);
9268 tcg_temp_free_i32(tcg_op2
);
9271 for (pass
= 0; pass
< maxpass
; pass
++) {
9272 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
9273 tcg_temp_free_i32(tcg_res
[pass
]);
9276 clear_vec_high(s
, rd
);
9280 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
9281 tcg_temp_free_ptr(fpst
);
9285 /* Floating point op subgroup of C3.6.16. */
9286 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
9288 /* For floating point ops, the U, size[1] and opcode bits
9289 * together indicate the operation. size[0] indicates single
9292 int fpopcode
= extract32(insn
, 11, 5)
9293 | (extract32(insn
, 23, 1) << 5)
9294 | (extract32(insn
, 29, 1) << 6);
9295 int is_q
= extract32(insn
, 30, 1);
9296 int size
= extract32(insn
, 22, 1);
9297 int rm
= extract32(insn
, 16, 5);
9298 int rn
= extract32(insn
, 5, 5);
9299 int rd
= extract32(insn
, 0, 5);
9301 int datasize
= is_q
? 128 : 64;
9302 int esize
= 32 << size
;
9303 int elements
= datasize
/ esize
;
9305 if (size
== 1 && !is_q
) {
9306 unallocated_encoding(s
);
9311 case 0x58: /* FMAXNMP */
9312 case 0x5a: /* FADDP */
9313 case 0x5e: /* FMAXP */
9314 case 0x78: /* FMINNMP */
9315 case 0x7e: /* FMINP */
9316 if (size
&& !is_q
) {
9317 unallocated_encoding(s
);
9320 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
9323 case 0x1b: /* FMULX */
9324 case 0x1f: /* FRECPS */
9325 case 0x3f: /* FRSQRTS */
9326 case 0x5d: /* FACGE */
9327 case 0x7d: /* FACGT */
9328 case 0x19: /* FMLA */
9329 case 0x39: /* FMLS */
9330 case 0x18: /* FMAXNM */
9331 case 0x1a: /* FADD */
9332 case 0x1c: /* FCMEQ */
9333 case 0x1e: /* FMAX */
9334 case 0x38: /* FMINNM */
9335 case 0x3a: /* FSUB */
9336 case 0x3e: /* FMIN */
9337 case 0x5b: /* FMUL */
9338 case 0x5c: /* FCMGE */
9339 case 0x5f: /* FDIV */
9340 case 0x7a: /* FABD */
9341 case 0x7c: /* FCMGT */
9342 if (!fp_access_check(s
)) {
9346 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
9349 unallocated_encoding(s
);
9354 /* Integer op subgroup of C3.6.16. */
9355 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
9357 int is_q
= extract32(insn
, 30, 1);
9358 int u
= extract32(insn
, 29, 1);
9359 int size
= extract32(insn
, 22, 2);
9360 int opcode
= extract32(insn
, 11, 5);
9361 int rm
= extract32(insn
, 16, 5);
9362 int rn
= extract32(insn
, 5, 5);
9363 int rd
= extract32(insn
, 0, 5);
9367 case 0x13: /* MUL, PMUL */
9368 if (u
&& size
!= 0) {
9369 unallocated_encoding(s
);
9373 case 0x0: /* SHADD, UHADD */
9374 case 0x2: /* SRHADD, URHADD */
9375 case 0x4: /* SHSUB, UHSUB */
9376 case 0xc: /* SMAX, UMAX */
9377 case 0xd: /* SMIN, UMIN */
9378 case 0xe: /* SABD, UABD */
9379 case 0xf: /* SABA, UABA */
9380 case 0x12: /* MLA, MLS */
9382 unallocated_encoding(s
);
9386 case 0x16: /* SQDMULH, SQRDMULH */
9387 if (size
== 0 || size
== 3) {
9388 unallocated_encoding(s
);
9393 if (size
== 3 && !is_q
) {
9394 unallocated_encoding(s
);
9400 if (!fp_access_check(s
)) {
9406 for (pass
= 0; pass
< 2; pass
++) {
9407 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9408 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9409 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9411 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9412 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9414 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
9416 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9418 tcg_temp_free_i64(tcg_res
);
9419 tcg_temp_free_i64(tcg_op1
);
9420 tcg_temp_free_i64(tcg_op2
);
9423 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
9424 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9425 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9426 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9427 NeonGenTwoOpFn
*genfn
= NULL
;
9428 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
9430 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
9431 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
9434 case 0x0: /* SHADD, UHADD */
9436 static NeonGenTwoOpFn
* const fns
[3][2] = {
9437 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
9438 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
9439 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
9441 genfn
= fns
[size
][u
];
9444 case 0x1: /* SQADD, UQADD */
9446 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9447 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9448 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9449 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9451 genenvfn
= fns
[size
][u
];
9454 case 0x2: /* SRHADD, URHADD */
9456 static NeonGenTwoOpFn
* const fns
[3][2] = {
9457 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
9458 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
9459 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
9461 genfn
= fns
[size
][u
];
9464 case 0x4: /* SHSUB, UHSUB */
9466 static NeonGenTwoOpFn
* const fns
[3][2] = {
9467 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
9468 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
9469 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
9471 genfn
= fns
[size
][u
];
9474 case 0x5: /* SQSUB, UQSUB */
9476 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9477 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9478 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9479 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9481 genenvfn
= fns
[size
][u
];
9484 case 0x6: /* CMGT, CMHI */
9486 static NeonGenTwoOpFn
* const fns
[3][2] = {
9487 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_u8
},
9488 { gen_helper_neon_cgt_s16
, gen_helper_neon_cgt_u16
},
9489 { gen_helper_neon_cgt_s32
, gen_helper_neon_cgt_u32
},
9491 genfn
= fns
[size
][u
];
9494 case 0x7: /* CMGE, CMHS */
9496 static NeonGenTwoOpFn
* const fns
[3][2] = {
9497 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_u8
},
9498 { gen_helper_neon_cge_s16
, gen_helper_neon_cge_u16
},
9499 { gen_helper_neon_cge_s32
, gen_helper_neon_cge_u32
},
9501 genfn
= fns
[size
][u
];
9504 case 0x8: /* SSHL, USHL */
9506 static NeonGenTwoOpFn
* const fns
[3][2] = {
9507 { gen_helper_neon_shl_s8
, gen_helper_neon_shl_u8
},
9508 { gen_helper_neon_shl_s16
, gen_helper_neon_shl_u16
},
9509 { gen_helper_neon_shl_s32
, gen_helper_neon_shl_u32
},
9511 genfn
= fns
[size
][u
];
9514 case 0x9: /* SQSHL, UQSHL */
9516 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9517 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9518 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9519 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9521 genenvfn
= fns
[size
][u
];
9524 case 0xa: /* SRSHL, URSHL */
9526 static NeonGenTwoOpFn
* const fns
[3][2] = {
9527 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
9528 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
9529 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
9531 genfn
= fns
[size
][u
];
9534 case 0xb: /* SQRSHL, UQRSHL */
9536 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9537 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9538 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9539 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9541 genenvfn
= fns
[size
][u
];
9544 case 0xc: /* SMAX, UMAX */
9546 static NeonGenTwoOpFn
* const fns
[3][2] = {
9547 { gen_helper_neon_max_s8
, gen_helper_neon_max_u8
},
9548 { gen_helper_neon_max_s16
, gen_helper_neon_max_u16
},
9549 { gen_max_s32
, gen_max_u32
},
9551 genfn
= fns
[size
][u
];
9555 case 0xd: /* SMIN, UMIN */
9557 static NeonGenTwoOpFn
* const fns
[3][2] = {
9558 { gen_helper_neon_min_s8
, gen_helper_neon_min_u8
},
9559 { gen_helper_neon_min_s16
, gen_helper_neon_min_u16
},
9560 { gen_min_s32
, gen_min_u32
},
9562 genfn
= fns
[size
][u
];
9565 case 0xe: /* SABD, UABD */
9566 case 0xf: /* SABA, UABA */
9568 static NeonGenTwoOpFn
* const fns
[3][2] = {
9569 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
9570 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
9571 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
9573 genfn
= fns
[size
][u
];
9576 case 0x10: /* ADD, SUB */
9578 static NeonGenTwoOpFn
* const fns
[3][2] = {
9579 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9580 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9581 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9583 genfn
= fns
[size
][u
];
9586 case 0x11: /* CMTST, CMEQ */
9588 static NeonGenTwoOpFn
* const fns
[3][2] = {
9589 { gen_helper_neon_tst_u8
, gen_helper_neon_ceq_u8
},
9590 { gen_helper_neon_tst_u16
, gen_helper_neon_ceq_u16
},
9591 { gen_helper_neon_tst_u32
, gen_helper_neon_ceq_u32
},
9593 genfn
= fns
[size
][u
];
9596 case 0x13: /* MUL, PMUL */
9600 genfn
= gen_helper_neon_mul_p8
;
9603 /* fall through : MUL */
9604 case 0x12: /* MLA, MLS */
9606 static NeonGenTwoOpFn
* const fns
[3] = {
9607 gen_helper_neon_mul_u8
,
9608 gen_helper_neon_mul_u16
,
9614 case 0x16: /* SQDMULH, SQRDMULH */
9616 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9617 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9618 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9620 assert(size
== 1 || size
== 2);
9621 genenvfn
= fns
[size
- 1][u
];
9625 g_assert_not_reached();
9629 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
9631 genfn(tcg_res
, tcg_op1
, tcg_op2
);
9634 if (opcode
== 0xf || opcode
== 0x12) {
9635 /* SABA, UABA, MLA, MLS: accumulating ops */
9636 static NeonGenTwoOpFn
* const fns
[3][2] = {
9637 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9638 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9639 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9641 bool is_sub
= (opcode
== 0x12 && u
); /* MLS */
9643 genfn
= fns
[size
][is_sub
];
9644 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
9645 genfn(tcg_res
, tcg_op1
, tcg_res
);
9648 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9650 tcg_temp_free_i32(tcg_res
);
9651 tcg_temp_free_i32(tcg_op1
);
9652 tcg_temp_free_i32(tcg_op2
);
9657 clear_vec_high(s
, rd
);
9661 /* C3.6.16 AdvSIMD three same
9662 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9663 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9664 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9665 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9667 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
9669 int opcode
= extract32(insn
, 11, 5);
9672 case 0x3: /* logic ops */
9673 disas_simd_3same_logic(s
, insn
);
9675 case 0x17: /* ADDP */
9676 case 0x14: /* SMAXP, UMAXP */
9677 case 0x15: /* SMINP, UMINP */
9679 /* Pairwise operations */
9680 int is_q
= extract32(insn
, 30, 1);
9681 int u
= extract32(insn
, 29, 1);
9682 int size
= extract32(insn
, 22, 2);
9683 int rm
= extract32(insn
, 16, 5);
9684 int rn
= extract32(insn
, 5, 5);
9685 int rd
= extract32(insn
, 0, 5);
9686 if (opcode
== 0x17) {
9687 if (u
|| (size
== 3 && !is_q
)) {
9688 unallocated_encoding(s
);
9693 unallocated_encoding(s
);
9697 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
9701 /* floating point ops, sz[1] and U are part of opcode */
9702 disas_simd_3same_float(s
, insn
);
9705 disas_simd_3same_int(s
, insn
);
9710 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
9711 int size
, int rn
, int rd
)
9713 /* Handle 2-reg-misc ops which are widening (so each size element
9714 * in the source becomes a 2*size element in the destination.
9715 * The only instruction like this is FCVTL.
9720 /* 32 -> 64 bit fp conversion */
9721 TCGv_i64 tcg_res
[2];
9722 int srcelt
= is_q
? 2 : 0;
9724 for (pass
= 0; pass
< 2; pass
++) {
9725 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9726 tcg_res
[pass
] = tcg_temp_new_i64();
9728 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
9729 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
9730 tcg_temp_free_i32(tcg_op
);
9732 for (pass
= 0; pass
< 2; pass
++) {
9733 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9734 tcg_temp_free_i64(tcg_res
[pass
]);
9737 /* 16 -> 32 bit fp conversion */
9738 int srcelt
= is_q
? 4 : 0;
9739 TCGv_i32 tcg_res
[4];
9741 for (pass
= 0; pass
< 4; pass
++) {
9742 tcg_res
[pass
] = tcg_temp_new_i32();
9744 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
9745 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
9748 for (pass
= 0; pass
< 4; pass
++) {
9749 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
9750 tcg_temp_free_i32(tcg_res
[pass
]);
9755 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
9756 bool is_q
, int size
, int rn
, int rd
)
9758 int op
= (opcode
<< 1) | u
;
9759 int opsz
= op
+ size
;
9760 int grp_size
= 3 - opsz
;
9761 int dsize
= is_q
? 128 : 64;
9765 unallocated_encoding(s
);
9769 if (!fp_access_check(s
)) {
9774 /* Special case bytes, use bswap op on each group of elements */
9775 int groups
= dsize
/ (8 << grp_size
);
9777 for (i
= 0; i
< groups
; i
++) {
9778 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9780 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
9783 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
9786 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
9789 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
9792 g_assert_not_reached();
9794 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
9795 tcg_temp_free_i64(tcg_tmp
);
9798 clear_vec_high(s
, rd
);
9801 int revmask
= (1 << grp_size
) - 1;
9802 int esize
= 8 << size
;
9803 int elements
= dsize
/ esize
;
9804 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9805 TCGv_i64 tcg_rd
= tcg_const_i64(0);
9806 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
9808 for (i
= 0; i
< elements
; i
++) {
9809 int e_rev
= (i
& 0xf) ^ revmask
;
9810 int off
= e_rev
* esize
;
9811 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
9813 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
9814 tcg_rn
, off
- 64, esize
);
9816 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
9819 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
9820 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
9822 tcg_temp_free_i64(tcg_rd_hi
);
9823 tcg_temp_free_i64(tcg_rd
);
9824 tcg_temp_free_i64(tcg_rn
);
9828 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
9829 bool is_q
, int size
, int rn
, int rd
)
9831 /* Implement the pairwise operations from 2-misc:
9832 * SADDLP, UADDLP, SADALP, UADALP.
9833 * These all add pairs of elements in the input to produce a
9834 * double-width result element in the output (possibly accumulating).
9836 bool accum
= (opcode
== 0x6);
9837 int maxpass
= is_q
? 2 : 1;
9839 TCGv_i64 tcg_res
[2];
9842 /* 32 + 32 -> 64 op */
9843 TCGMemOp memop
= size
+ (u
? 0 : MO_SIGN
);
9845 for (pass
= 0; pass
< maxpass
; pass
++) {
9846 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9847 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9849 tcg_res
[pass
] = tcg_temp_new_i64();
9851 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
9852 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
9853 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9855 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
9856 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9859 tcg_temp_free_i64(tcg_op1
);
9860 tcg_temp_free_i64(tcg_op2
);
9863 for (pass
= 0; pass
< maxpass
; pass
++) {
9864 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9865 NeonGenOneOpFn
*genfn
;
9866 static NeonGenOneOpFn
* const fns
[2][2] = {
9867 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
9868 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
9871 genfn
= fns
[size
][u
];
9873 tcg_res
[pass
] = tcg_temp_new_i64();
9875 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9876 genfn(tcg_res
[pass
], tcg_op
);
9879 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
9881 gen_helper_neon_addl_u16(tcg_res
[pass
],
9882 tcg_res
[pass
], tcg_op
);
9884 gen_helper_neon_addl_u32(tcg_res
[pass
],
9885 tcg_res
[pass
], tcg_op
);
9888 tcg_temp_free_i64(tcg_op
);
9892 tcg_res
[1] = tcg_const_i64(0);
9894 for (pass
= 0; pass
< 2; pass
++) {
9895 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9896 tcg_temp_free_i64(tcg_res
[pass
]);
9900 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
9902 /* Implement SHLL and SHLL2 */
9904 int part
= is_q
? 2 : 0;
9905 TCGv_i64 tcg_res
[2];
9907 for (pass
= 0; pass
< 2; pass
++) {
9908 static NeonGenWidenFn
* const widenfns
[3] = {
9909 gen_helper_neon_widen_u8
,
9910 gen_helper_neon_widen_u16
,
9911 tcg_gen_extu_i32_i64
,
9913 NeonGenWidenFn
*widenfn
= widenfns
[size
];
9914 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9916 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
9917 tcg_res
[pass
] = tcg_temp_new_i64();
9918 widenfn(tcg_res
[pass
], tcg_op
);
9919 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
9921 tcg_temp_free_i32(tcg_op
);
9924 for (pass
= 0; pass
< 2; pass
++) {
9925 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9926 tcg_temp_free_i64(tcg_res
[pass
]);
9930 /* C3.6.17 AdvSIMD two reg misc
9931 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9932 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9933 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9934 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9936 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9938 int size
= extract32(insn
, 22, 2);
9939 int opcode
= extract32(insn
, 12, 5);
9940 bool u
= extract32(insn
, 29, 1);
9941 bool is_q
= extract32(insn
, 30, 1);
9942 int rn
= extract32(insn
, 5, 5);
9943 int rd
= extract32(insn
, 0, 5);
9944 bool need_fpstatus
= false;
9945 bool need_rmode
= false;
9948 TCGv_ptr tcg_fpstatus
;
9951 case 0x0: /* REV64, REV32 */
9952 case 0x1: /* REV16 */
9953 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
9955 case 0x5: /* CNT, NOT, RBIT */
9956 if (u
&& size
== 0) {
9957 /* NOT: adjust size so we can use the 64-bits-at-a-time loop. */
9960 } else if (u
&& size
== 1) {
9963 } else if (!u
&& size
== 0) {
9967 unallocated_encoding(s
);
9969 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
9970 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
9972 unallocated_encoding(s
);
9975 if (!fp_access_check(s
)) {
9979 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
9981 case 0x4: /* CLS, CLZ */
9983 unallocated_encoding(s
);
9987 case 0x2: /* SADDLP, UADDLP */
9988 case 0x6: /* SADALP, UADALP */
9990 unallocated_encoding(s
);
9993 if (!fp_access_check(s
)) {
9996 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
9998 case 0x13: /* SHLL, SHLL2 */
9999 if (u
== 0 || size
== 3) {
10000 unallocated_encoding(s
);
10003 if (!fp_access_check(s
)) {
10006 handle_shll(s
, is_q
, size
, rn
, rd
);
10008 case 0xa: /* CMLT */
10010 unallocated_encoding(s
);
10014 case 0x8: /* CMGT, CMGE */
10015 case 0x9: /* CMEQ, CMLE */
10016 case 0xb: /* ABS, NEG */
10017 if (size
== 3 && !is_q
) {
10018 unallocated_encoding(s
);
10022 case 0x3: /* SUQADD, USQADD */
10023 if (size
== 3 && !is_q
) {
10024 unallocated_encoding(s
);
10027 if (!fp_access_check(s
)) {
10030 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
10032 case 0x7: /* SQABS, SQNEG */
10033 if (size
== 3 && !is_q
) {
10034 unallocated_encoding(s
);
10039 case 0x16 ... 0x1d:
10042 /* Floating point: U, size[1] and opcode indicate operation;
10043 * size[0] indicates single or double precision.
10045 int is_double
= extract32(size
, 0, 1);
10046 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
10047 size
= is_double
? 3 : 2;
10049 case 0x2f: /* FABS */
10050 case 0x6f: /* FNEG */
10051 if (size
== 3 && !is_q
) {
10052 unallocated_encoding(s
);
10056 case 0x1d: /* SCVTF */
10057 case 0x5d: /* UCVTF */
10059 bool is_signed
= (opcode
== 0x1d) ? true : false;
10060 int elements
= is_double
? 2 : is_q
? 4 : 2;
10061 if (is_double
&& !is_q
) {
10062 unallocated_encoding(s
);
10065 if (!fp_access_check(s
)) {
10068 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
10071 case 0x2c: /* FCMGT (zero) */
10072 case 0x2d: /* FCMEQ (zero) */
10073 case 0x2e: /* FCMLT (zero) */
10074 case 0x6c: /* FCMGE (zero) */
10075 case 0x6d: /* FCMLE (zero) */
10076 if (size
== 3 && !is_q
) {
10077 unallocated_encoding(s
);
10080 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
10082 case 0x7f: /* FSQRT */
10083 if (size
== 3 && !is_q
) {
10084 unallocated_encoding(s
);
10088 case 0x1a: /* FCVTNS */
10089 case 0x1b: /* FCVTMS */
10090 case 0x3a: /* FCVTPS */
10091 case 0x3b: /* FCVTZS */
10092 case 0x5a: /* FCVTNU */
10093 case 0x5b: /* FCVTMU */
10094 case 0x7a: /* FCVTPU */
10095 case 0x7b: /* FCVTZU */
10096 need_fpstatus
= true;
10098 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10099 if (size
== 3 && !is_q
) {
10100 unallocated_encoding(s
);
10104 case 0x5c: /* FCVTAU */
10105 case 0x1c: /* FCVTAS */
10106 need_fpstatus
= true;
10108 rmode
= FPROUNDING_TIEAWAY
;
10109 if (size
== 3 && !is_q
) {
10110 unallocated_encoding(s
);
10114 case 0x3c: /* URECPE */
10116 unallocated_encoding(s
);
10120 case 0x3d: /* FRECPE */
10121 case 0x7d: /* FRSQRTE */
10122 if (size
== 3 && !is_q
) {
10123 unallocated_encoding(s
);
10126 if (!fp_access_check(s
)) {
10129 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
10131 case 0x56: /* FCVTXN, FCVTXN2 */
10133 unallocated_encoding(s
);
10137 case 0x16: /* FCVTN, FCVTN2 */
10138 /* handle_2misc_narrow does a 2*size -> size operation, but these
10139 * instructions encode the source size rather than dest size.
10141 if (!fp_access_check(s
)) {
10144 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
10146 case 0x17: /* FCVTL, FCVTL2 */
10147 if (!fp_access_check(s
)) {
10150 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
10152 case 0x18: /* FRINTN */
10153 case 0x19: /* FRINTM */
10154 case 0x38: /* FRINTP */
10155 case 0x39: /* FRINTZ */
10157 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10159 case 0x59: /* FRINTX */
10160 case 0x79: /* FRINTI */
10161 need_fpstatus
= true;
10162 if (size
== 3 && !is_q
) {
10163 unallocated_encoding(s
);
10167 case 0x58: /* FRINTA */
10169 rmode
= FPROUNDING_TIEAWAY
;
10170 need_fpstatus
= true;
10171 if (size
== 3 && !is_q
) {
10172 unallocated_encoding(s
);
10176 case 0x7c: /* URSQRTE */
10178 unallocated_encoding(s
);
10181 need_fpstatus
= true;
10184 unallocated_encoding(s
);
10190 unallocated_encoding(s
);
10194 if (!fp_access_check(s
)) {
10198 if (need_fpstatus
) {
10199 tcg_fpstatus
= get_fpstatus_ptr();
10201 TCGV_UNUSED_PTR(tcg_fpstatus
);
10204 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
10205 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
10207 TCGV_UNUSED_I32(tcg_rmode
);
10211 /* All 64-bit element operations can be shared with scalar 2misc */
10214 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
10215 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10216 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10218 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10220 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
10221 tcg_rmode
, tcg_fpstatus
);
10223 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10225 tcg_temp_free_i64(tcg_res
);
10226 tcg_temp_free_i64(tcg_op
);
10231 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
10232 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10233 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10236 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
10239 /* Special cases for 32 bit elements */
10241 case 0xa: /* CMLT */
10242 /* 32 bit integer comparison against zero, result is
10243 * test ? (2^32 - 1) : 0. We implement via setcond(test)
10246 cond
= TCG_COND_LT
;
10248 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
10249 tcg_gen_neg_i32(tcg_res
, tcg_res
);
10251 case 0x8: /* CMGT, CMGE */
10252 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
10254 case 0x9: /* CMEQ, CMLE */
10255 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
10257 case 0x4: /* CLS */
10259 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
10261 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
10264 case 0x7: /* SQABS, SQNEG */
10266 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
10268 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
10271 case 0xb: /* ABS, NEG */
10273 tcg_gen_neg_i32(tcg_res
, tcg_op
);
10275 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10276 tcg_gen_neg_i32(tcg_res
, tcg_op
);
10277 tcg_gen_movcond_i32(TCG_COND_GT
, tcg_res
, tcg_op
,
10278 tcg_zero
, tcg_op
, tcg_res
);
10279 tcg_temp_free_i32(tcg_zero
);
10282 case 0x2f: /* FABS */
10283 gen_helper_vfp_abss(tcg_res
, tcg_op
);
10285 case 0x6f: /* FNEG */
10286 gen_helper_vfp_negs(tcg_res
, tcg_op
);
10288 case 0x7f: /* FSQRT */
10289 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
10291 case 0x1a: /* FCVTNS */
10292 case 0x1b: /* FCVTMS */
10293 case 0x1c: /* FCVTAS */
10294 case 0x3a: /* FCVTPS */
10295 case 0x3b: /* FCVTZS */
10297 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10298 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
10299 tcg_shift
, tcg_fpstatus
);
10300 tcg_temp_free_i32(tcg_shift
);
10303 case 0x5a: /* FCVTNU */
10304 case 0x5b: /* FCVTMU */
10305 case 0x5c: /* FCVTAU */
10306 case 0x7a: /* FCVTPU */
10307 case 0x7b: /* FCVTZU */
10309 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10310 gen_helper_vfp_touls(tcg_res
, tcg_op
,
10311 tcg_shift
, tcg_fpstatus
);
10312 tcg_temp_free_i32(tcg_shift
);
10315 case 0x18: /* FRINTN */
10316 case 0x19: /* FRINTM */
10317 case 0x38: /* FRINTP */
10318 case 0x39: /* FRINTZ */
10319 case 0x58: /* FRINTA */
10320 case 0x79: /* FRINTI */
10321 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
10323 case 0x59: /* FRINTX */
10324 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
10326 case 0x7c: /* URSQRTE */
10327 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
10330 g_assert_not_reached();
10333 /* Use helpers for 8 and 16 bit elements */
10335 case 0x5: /* CNT, RBIT */
10336 /* For these two insns size is part of the opcode specifier
10337 * (handled earlier); they always operate on byte elements.
10340 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
10342 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
10345 case 0x7: /* SQABS, SQNEG */
10347 NeonGenOneOpEnvFn
*genfn
;
10348 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
10349 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
10350 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10352 genfn
= fns
[size
][u
];
10353 genfn(tcg_res
, cpu_env
, tcg_op
);
10356 case 0x8: /* CMGT, CMGE */
10357 case 0x9: /* CMEQ, CMLE */
10358 case 0xa: /* CMLT */
10360 static NeonGenTwoOpFn
* const fns
[3][2] = {
10361 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
10362 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
10363 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
10365 NeonGenTwoOpFn
*genfn
;
10368 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10370 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
10371 comp
= (opcode
- 0x8) * 2 + u
;
10372 /* ...but LE, LT are implemented as reverse GE, GT */
10373 reverse
= (comp
> 2);
10377 genfn
= fns
[comp
][size
];
10379 genfn(tcg_res
, tcg_zero
, tcg_op
);
10381 genfn(tcg_res
, tcg_op
, tcg_zero
);
10383 tcg_temp_free_i32(tcg_zero
);
10386 case 0xb: /* ABS, NEG */
10388 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10390 gen_helper_neon_sub_u16(tcg_res
, tcg_zero
, tcg_op
);
10392 gen_helper_neon_sub_u8(tcg_res
, tcg_zero
, tcg_op
);
10394 tcg_temp_free_i32(tcg_zero
);
10397 gen_helper_neon_abs_s16(tcg_res
, tcg_op
);
10399 gen_helper_neon_abs_s8(tcg_res
, tcg_op
);
10403 case 0x4: /* CLS, CLZ */
10406 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
10408 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
10412 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
10414 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
10419 g_assert_not_reached();
10423 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10425 tcg_temp_free_i32(tcg_res
);
10426 tcg_temp_free_i32(tcg_op
);
10430 clear_vec_high(s
, rd
);
10434 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
10435 tcg_temp_free_i32(tcg_rmode
);
10437 if (need_fpstatus
) {
10438 tcg_temp_free_ptr(tcg_fpstatus
);
10442 /* C3.6.13 AdvSIMD scalar x indexed element
10443 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10444 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10445 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10446 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10447 * C3.6.18 AdvSIMD vector x indexed element
10448 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10449 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10450 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10451 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10453 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
10455 /* This encoding has two kinds of instruction:
10456 * normal, where we perform elt x idxelt => elt for each
10457 * element in the vector
10458 * long, where we perform elt x idxelt and generate a result of
10459 * double the width of the input element
10460 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
10462 bool is_scalar
= extract32(insn
, 28, 1);
10463 bool is_q
= extract32(insn
, 30, 1);
10464 bool u
= extract32(insn
, 29, 1);
10465 int size
= extract32(insn
, 22, 2);
10466 int l
= extract32(insn
, 21, 1);
10467 int m
= extract32(insn
, 20, 1);
10468 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
10469 int rm
= extract32(insn
, 16, 4);
10470 int opcode
= extract32(insn
, 12, 4);
10471 int h
= extract32(insn
, 11, 1);
10472 int rn
= extract32(insn
, 5, 5);
10473 int rd
= extract32(insn
, 0, 5);
10474 bool is_long
= false;
10475 bool is_fp
= false;
10480 case 0x0: /* MLA */
10481 case 0x4: /* MLS */
10482 if (!u
|| is_scalar
) {
10483 unallocated_encoding(s
);
10487 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10488 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10489 case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */
10491 unallocated_encoding(s
);
10496 case 0x3: /* SQDMLAL, SQDMLAL2 */
10497 case 0x7: /* SQDMLSL, SQDMLSL2 */
10498 case 0xb: /* SQDMULL, SQDMULL2 */
10501 case 0xc: /* SQDMULH */
10502 case 0xd: /* SQRDMULH */
10504 unallocated_encoding(s
);
10508 case 0x8: /* MUL */
10509 if (u
|| is_scalar
) {
10510 unallocated_encoding(s
);
10514 case 0x1: /* FMLA */
10515 case 0x5: /* FMLS */
10517 unallocated_encoding(s
);
10521 case 0x9: /* FMUL, FMULX */
10522 if (!extract32(size
, 1, 1)) {
10523 unallocated_encoding(s
);
10529 unallocated_encoding(s
);
10534 /* low bit of size indicates single/double */
10535 size
= extract32(size
, 0, 1) ? 3 : 2;
10537 index
= h
<< 1 | l
;
10540 unallocated_encoding(s
);
10549 index
= h
<< 2 | l
<< 1 | m
;
10552 index
= h
<< 1 | l
;
10556 unallocated_encoding(s
);
10561 if (!fp_access_check(s
)) {
10566 fpst
= get_fpstatus_ptr();
10568 TCGV_UNUSED_PTR(fpst
);
10572 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10575 assert(is_fp
&& is_q
&& !is_long
);
10577 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
10579 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10580 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10581 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10583 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10586 case 0x5: /* FMLS */
10587 /* As usual for ARM, separate negation for fused multiply-add */
10588 gen_helper_vfp_negd(tcg_op
, tcg_op
);
10590 case 0x1: /* FMLA */
10591 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10592 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10594 case 0x9: /* FMUL, FMULX */
10596 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10598 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10602 g_assert_not_reached();
10605 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10606 tcg_temp_free_i64(tcg_op
);
10607 tcg_temp_free_i64(tcg_res
);
10611 clear_vec_high(s
, rd
);
10614 tcg_temp_free_i64(tcg_idx
);
10615 } else if (!is_long
) {
10616 /* 32 bit floating point, or 16 or 32 bit integer.
10617 * For the 16 bit scalar case we use the usual Neon helpers and
10618 * rely on the fact that 0 op 0 == 0 with no side effects.
10620 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10621 int pass
, maxpasses
;
10626 maxpasses
= is_q
? 4 : 2;
10629 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10631 if (size
== 1 && !is_scalar
) {
10632 /* The simplest way to handle the 16x16 indexed ops is to duplicate
10633 * the index into both halves of the 32 bit tcg_idx and then use
10634 * the usual Neon helpers.
10636 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10639 for (pass
= 0; pass
< maxpasses
; pass
++) {
10640 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10641 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10643 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
10646 case 0x0: /* MLA */
10647 case 0x4: /* MLS */
10648 case 0x8: /* MUL */
10650 static NeonGenTwoOpFn
* const fns
[2][2] = {
10651 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
10652 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
10654 NeonGenTwoOpFn
*genfn
;
10655 bool is_sub
= opcode
== 0x4;
10658 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
10660 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
10662 if (opcode
== 0x8) {
10665 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
10666 genfn
= fns
[size
- 1][is_sub
];
10667 genfn(tcg_res
, tcg_op
, tcg_res
);
10670 case 0x5: /* FMLS */
10671 /* As usual for ARM, separate negation for fused multiply-add */
10672 gen_helper_vfp_negs(tcg_op
, tcg_op
);
10674 case 0x1: /* FMLA */
10675 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10676 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10678 case 0x9: /* FMUL, FMULX */
10680 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10682 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10685 case 0xc: /* SQDMULH */
10687 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
10690 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
10694 case 0xd: /* SQRDMULH */
10696 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
10699 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
10704 g_assert_not_reached();
10708 write_fp_sreg(s
, rd
, tcg_res
);
10710 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10713 tcg_temp_free_i32(tcg_op
);
10714 tcg_temp_free_i32(tcg_res
);
10717 tcg_temp_free_i32(tcg_idx
);
10720 clear_vec_high(s
, rd
);
10723 /* long ops: 16x16->32 or 32x32->64 */
10724 TCGv_i64 tcg_res
[2];
10726 bool satop
= extract32(opcode
, 0, 1);
10727 TCGMemOp memop
= MO_32
;
10734 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10736 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
10738 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10739 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10740 TCGv_i64 tcg_passres
;
10746 passelt
= pass
+ (is_q
* 2);
10749 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
10751 tcg_res
[pass
] = tcg_temp_new_i64();
10753 if (opcode
== 0xa || opcode
== 0xb) {
10754 /* Non-accumulating ops */
10755 tcg_passres
= tcg_res
[pass
];
10757 tcg_passres
= tcg_temp_new_i64();
10760 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
10761 tcg_temp_free_i64(tcg_op
);
10764 /* saturating, doubling */
10765 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10766 tcg_passres
, tcg_passres
);
10769 if (opcode
== 0xa || opcode
== 0xb) {
10773 /* Accumulating op: handle accumulate step */
10774 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10777 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10778 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10780 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10781 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10783 case 0x7: /* SQDMLSL, SQDMLSL2 */
10784 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10786 case 0x3: /* SQDMLAL, SQDMLAL2 */
10787 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10792 g_assert_not_reached();
10794 tcg_temp_free_i64(tcg_passres
);
10796 tcg_temp_free_i64(tcg_idx
);
10799 clear_vec_high(s
, rd
);
10802 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10805 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10808 /* The simplest way to handle the 16x16 indexed ops is to
10809 * duplicate the index into both halves of the 32 bit tcg_idx
10810 * and then use the usual Neon helpers.
10812 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10815 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10816 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10817 TCGv_i64 tcg_passres
;
10820 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
10822 read_vec_element_i32(s
, tcg_op
, rn
,
10823 pass
+ (is_q
* 2), MO_32
);
10826 tcg_res
[pass
] = tcg_temp_new_i64();
10828 if (opcode
== 0xa || opcode
== 0xb) {
10829 /* Non-accumulating ops */
10830 tcg_passres
= tcg_res
[pass
];
10832 tcg_passres
= tcg_temp_new_i64();
10835 if (memop
& MO_SIGN
) {
10836 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
10838 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
10841 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10842 tcg_passres
, tcg_passres
);
10844 tcg_temp_free_i32(tcg_op
);
10846 if (opcode
== 0xa || opcode
== 0xb) {
10850 /* Accumulating op: handle accumulate step */
10851 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10854 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10855 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
10858 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10859 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
10862 case 0x7: /* SQDMLSL, SQDMLSL2 */
10863 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10865 case 0x3: /* SQDMLAL, SQDMLAL2 */
10866 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10871 g_assert_not_reached();
10873 tcg_temp_free_i64(tcg_passres
);
10875 tcg_temp_free_i32(tcg_idx
);
10878 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
10883 tcg_res
[1] = tcg_const_i64(0);
10886 for (pass
= 0; pass
< 2; pass
++) {
10887 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10888 tcg_temp_free_i64(tcg_res
[pass
]);
10892 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
10893 tcg_temp_free_ptr(fpst
);
10897 /* C3.6.19 Crypto AES
10898 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
10899 * +-----------------+------+-----------+--------+-----+------+------+
10900 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
10901 * +-----------------+------+-----------+--------+-----+------+------+
10903 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
10905 int size
= extract32(insn
, 22, 2);
10906 int opcode
= extract32(insn
, 12, 5);
10907 int rn
= extract32(insn
, 5, 5);
10908 int rd
= extract32(insn
, 0, 5);
10910 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
, tcg_decrypt
;
10911 CryptoThreeOpEnvFn
*genfn
;
10913 if (!arm_dc_feature(s
, ARM_FEATURE_V8_AES
)
10915 unallocated_encoding(s
);
10920 case 0x4: /* AESE */
10922 genfn
= gen_helper_crypto_aese
;
10924 case 0x6: /* AESMC */
10926 genfn
= gen_helper_crypto_aesmc
;
10928 case 0x5: /* AESD */
10930 genfn
= gen_helper_crypto_aese
;
10932 case 0x7: /* AESIMC */
10934 genfn
= gen_helper_crypto_aesmc
;
10937 unallocated_encoding(s
);
10941 if (!fp_access_check(s
)) {
10945 /* Note that we convert the Vx register indexes into the
10946 * index within the vfp.regs[] array, so we can share the
10947 * helper with the AArch32 instructions.
10949 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
10950 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
10951 tcg_decrypt
= tcg_const_i32(decrypt
);
10953 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
, tcg_decrypt
);
10955 tcg_temp_free_i32(tcg_rd_regno
);
10956 tcg_temp_free_i32(tcg_rn_regno
);
10957 tcg_temp_free_i32(tcg_decrypt
);
10960 /* C3.6.20 Crypto three-reg SHA
10961 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
10962 * +-----------------+------+---+------+---+--------+-----+------+------+
10963 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
10964 * +-----------------+------+---+------+---+--------+-----+------+------+
10966 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
10968 int size
= extract32(insn
, 22, 2);
10969 int opcode
= extract32(insn
, 12, 3);
10970 int rm
= extract32(insn
, 16, 5);
10971 int rn
= extract32(insn
, 5, 5);
10972 int rd
= extract32(insn
, 0, 5);
10973 CryptoThreeOpEnvFn
*genfn
;
10974 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
, tcg_rm_regno
;
10975 int feature
= ARM_FEATURE_V8_SHA256
;
10978 unallocated_encoding(s
);
10983 case 0: /* SHA1C */
10984 case 1: /* SHA1P */
10985 case 2: /* SHA1M */
10986 case 3: /* SHA1SU0 */
10988 feature
= ARM_FEATURE_V8_SHA1
;
10990 case 4: /* SHA256H */
10991 genfn
= gen_helper_crypto_sha256h
;
10993 case 5: /* SHA256H2 */
10994 genfn
= gen_helper_crypto_sha256h2
;
10996 case 6: /* SHA256SU1 */
10997 genfn
= gen_helper_crypto_sha256su1
;
11000 unallocated_encoding(s
);
11004 if (!arm_dc_feature(s
, feature
)) {
11005 unallocated_encoding(s
);
11009 if (!fp_access_check(s
)) {
11013 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
11014 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
11015 tcg_rm_regno
= tcg_const_i32(rm
<< 1);
11018 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
, tcg_rm_regno
);
11020 TCGv_i32 tcg_opcode
= tcg_const_i32(opcode
);
11022 gen_helper_crypto_sha1_3reg(cpu_env
, tcg_rd_regno
,
11023 tcg_rn_regno
, tcg_rm_regno
, tcg_opcode
);
11024 tcg_temp_free_i32(tcg_opcode
);
11027 tcg_temp_free_i32(tcg_rd_regno
);
11028 tcg_temp_free_i32(tcg_rn_regno
);
11029 tcg_temp_free_i32(tcg_rm_regno
);
11032 /* C3.6.21 Crypto two-reg SHA
11033 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
11034 * +-----------------+------+-----------+--------+-----+------+------+
11035 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
11036 * +-----------------+------+-----------+--------+-----+------+------+
11038 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
11040 int size
= extract32(insn
, 22, 2);
11041 int opcode
= extract32(insn
, 12, 5);
11042 int rn
= extract32(insn
, 5, 5);
11043 int rd
= extract32(insn
, 0, 5);
11044 CryptoTwoOpEnvFn
*genfn
;
11046 TCGv_i32 tcg_rd_regno
, tcg_rn_regno
;
11049 unallocated_encoding(s
);
11054 case 0: /* SHA1H */
11055 feature
= ARM_FEATURE_V8_SHA1
;
11056 genfn
= gen_helper_crypto_sha1h
;
11058 case 1: /* SHA1SU1 */
11059 feature
= ARM_FEATURE_V8_SHA1
;
11060 genfn
= gen_helper_crypto_sha1su1
;
11062 case 2: /* SHA256SU0 */
11063 feature
= ARM_FEATURE_V8_SHA256
;
11064 genfn
= gen_helper_crypto_sha256su0
;
11067 unallocated_encoding(s
);
11071 if (!arm_dc_feature(s
, feature
)) {
11072 unallocated_encoding(s
);
11076 if (!fp_access_check(s
)) {
11080 tcg_rd_regno
= tcg_const_i32(rd
<< 1);
11081 tcg_rn_regno
= tcg_const_i32(rn
<< 1);
11083 genfn(cpu_env
, tcg_rd_regno
, tcg_rn_regno
);
11085 tcg_temp_free_i32(tcg_rd_regno
);
11086 tcg_temp_free_i32(tcg_rn_regno
);
11089 /* C3.6 Data processing - SIMD, inc Crypto
11091 * As the decode gets a little complex we are using a table based
11092 * approach for this part of the decode.
11094 static const AArch64DecodeTable data_proc_simd
[] = {
11095 /* pattern , mask , fn */
11096 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
11097 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
11098 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
11099 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
11100 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
11101 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
11102 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
11103 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
11104 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
11105 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
11106 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
11107 { 0x2e000000, 0xbf208400, disas_simd_ext
},
11108 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
11109 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
11110 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
11111 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
11112 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
11113 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
11114 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
11115 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
11116 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
11117 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
11118 { 0x00000000, 0x00000000, NULL
}
11121 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
11123 /* Note that this is called with all non-FP cases from
11124 * table C3-6 so it must UNDEF for entries not specifically
11125 * allocated to instructions in that table.
11127 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
11131 unallocated_encoding(s
);
11135 /* C3.6 Data processing - SIMD and floating point */
11136 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
11138 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
11139 disas_data_proc_fp(s
, insn
);
11141 /* SIMD, including crypto */
11142 disas_data_proc_simd(s
, insn
);
11146 /* C3.1 A64 instruction index by encoding */
11147 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
11151 insn
= arm_ldl_code(env
, s
->pc
, s
->sctlr_b
);
11155 s
->fp_access_checked
= false;
11157 switch (extract32(insn
, 25, 4)) {
11158 case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */
11159 unallocated_encoding(s
);
11161 case 0x8: case 0x9: /* Data processing - immediate */
11162 disas_data_proc_imm(s
, insn
);
11164 case 0xa: case 0xb: /* Branch, exception generation and system insns */
11165 disas_b_exc_sys(s
, insn
);
11170 case 0xe: /* Loads and stores */
11171 disas_ldst(s
, insn
);
11174 case 0xd: /* Data processing - register */
11175 disas_data_proc_reg(s
, insn
);
11178 case 0xf: /* Data processing - SIMD and floating point */
11179 disas_data_proc_simd_fp(s
, insn
);
11182 assert(FALSE
); /* all 15 cases should be handled above */
11186 /* if we allocated any temporaries, free them here */
11190 void gen_intermediate_code_a64(ARMCPU
*cpu
, TranslationBlock
*tb
)
11192 CPUState
*cs
= CPU(cpu
);
11193 CPUARMState
*env
= &cpu
->env
;
11194 DisasContext dc1
, *dc
= &dc1
;
11195 target_ulong pc_start
;
11196 target_ulong next_page_start
;
11204 dc
->is_jmp
= DISAS_NEXT
;
11206 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
11210 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
11211 * there is no secure EL1, so we route exceptions to EL3.
11213 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
11214 !arm_el_is_aa64(env
, 3);
11217 dc
->be_data
= ARM_TBFLAG_BE_DATA(tb
->flags
) ? MO_BE
: MO_LE
;
11218 dc
->condexec_mask
= 0;
11219 dc
->condexec_cond
= 0;
11220 dc
->mmu_idx
= ARM_TBFLAG_MMUIDX(tb
->flags
);
11221 dc
->tbi0
= ARM_TBFLAG_TBI0(tb
->flags
);
11222 dc
->tbi1
= ARM_TBFLAG_TBI1(tb
->flags
);
11223 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
11224 #if !defined(CONFIG_USER_ONLY)
11225 dc
->user
= (dc
->current_el
== 0);
11227 dc
->fp_excp_el
= ARM_TBFLAG_FPEXC_EL(tb
->flags
);
11229 dc
->vec_stride
= 0;
11230 dc
->cp_regs
= cpu
->cp_regs
;
11231 dc
->features
= env
->features
;
11233 /* Single step state. The code-generation logic here is:
11235 * generate code with no special handling for single-stepping (except
11236 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
11237 * this happens anyway because those changes are all system register or
11239 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
11240 * emit code for one insn
11241 * emit code to clear PSTATE.SS
11242 * emit code to generate software step exception for completed step
11243 * end TB (as usual for having generated an exception)
11244 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
11245 * emit code to generate a software step exception
11248 dc
->ss_active
= ARM_TBFLAG_SS_ACTIVE(tb
->flags
);
11249 dc
->pstate_ss
= ARM_TBFLAG_PSTATE_SS(tb
->flags
);
11250 dc
->is_ldex
= false;
11251 dc
->ss_same_el
= (arm_debug_target_el(env
) == dc
->current_el
);
11253 init_tmp_a64_array(dc
);
11255 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
11257 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
11258 if (max_insns
== 0) {
11259 max_insns
= CF_COUNT_MASK
;
11261 if (max_insns
> TCG_MAX_INSNS
) {
11262 max_insns
= TCG_MAX_INSNS
;
11267 tcg_clear_temp_count();
11270 dc
->insn_start_idx
= tcg_op_buf_count();
11271 tcg_gen_insn_start(dc
->pc
, 0, 0);
11274 if (unlikely(!QTAILQ_EMPTY(&cs
->breakpoints
))) {
11276 QTAILQ_FOREACH(bp
, &cs
->breakpoints
, entry
) {
11277 if (bp
->pc
== dc
->pc
) {
11278 if (bp
->flags
& BP_CPU
) {
11279 gen_a64_set_pc_im(dc
->pc
);
11280 gen_helper_check_breakpoints(cpu_env
);
11281 /* End the TB early; it likely won't be executed */
11282 dc
->is_jmp
= DISAS_UPDATE
;
11284 gen_exception_internal_insn(dc
, 0, EXCP_DEBUG
);
11285 /* The address covered by the breakpoint must be
11286 included in [tb->pc, tb->pc + tb->size) in order
11287 to for it to be properly cleared -- thus we
11288 increment the PC here so that the logic setting
11289 tb->size below does the right thing. */
11291 goto done_generating
;
11298 if (num_insns
== max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
11302 if (dc
->ss_active
&& !dc
->pstate_ss
) {
11303 /* Singlestep state is Active-pending.
11304 * If we're in this state at the start of a TB then either
11305 * a) we just took an exception to an EL which is being debugged
11306 * and this is the first insn in the exception handler
11307 * b) debug exceptions were masked and we just unmasked them
11308 * without changing EL (eg by clearing PSTATE.D)
11309 * In either case we're going to take a swstep exception in the
11310 * "did not step an insn" case, and so the syndrome ISV and EX
11311 * bits should be zero.
11313 assert(num_insns
== 1);
11314 gen_exception(EXCP_UDEF
, syn_swstep(dc
->ss_same_el
, 0, 0),
11315 default_exception_el(dc
));
11316 dc
->is_jmp
= DISAS_EXC
;
11320 disas_a64_insn(env
, dc
);
11322 if (tcg_check_temp_count()) {
11323 fprintf(stderr
, "TCG temporary leak before "TARGET_FMT_lx
"\n",
11327 /* Translation stops when a conditional branch is encountered.
11328 * Otherwise the subsequent code could get translated several times.
11329 * Also stop translation when a page boundary is reached. This
11330 * ensures prefetch aborts occur at the right place.
11332 } while (!dc
->is_jmp
&& !tcg_op_buf_full() &&
11333 !cs
->singlestep_enabled
&&
11336 dc
->pc
< next_page_start
&&
11337 num_insns
< max_insns
);
11339 if (tb
->cflags
& CF_LAST_IO
) {
11343 if (unlikely(cs
->singlestep_enabled
|| dc
->ss_active
)
11344 && dc
->is_jmp
!= DISAS_EXC
) {
11345 /* Note that this means single stepping WFI doesn't halt the CPU.
11346 * For conditional branch insns this is harmless unreachable code as
11347 * gen_goto_tb() has already handled emitting the debug exception
11348 * (and thus a tb-jump is not possible when singlestepping).
11350 assert(dc
->is_jmp
!= DISAS_TB_JUMP
);
11351 if (dc
->is_jmp
!= DISAS_JUMP
) {
11352 gen_a64_set_pc_im(dc
->pc
);
11354 if (cs
->singlestep_enabled
) {
11355 gen_exception_internal(EXCP_DEBUG
);
11357 gen_step_complete_exception(dc
);
11360 switch (dc
->is_jmp
) {
11362 gen_goto_tb(dc
, 1, dc
->pc
);
11366 gen_a64_set_pc_im(dc
->pc
);
11369 /* indicate that the hash table must be used to find the next TB */
11370 tcg_gen_exit_tb(0);
11372 case DISAS_TB_JUMP
:
11377 gen_a64_set_pc_im(dc
->pc
);
11378 gen_helper_wfe(cpu_env
);
11381 gen_a64_set_pc_im(dc
->pc
);
11382 gen_helper_yield(cpu_env
);
11385 /* This is a special case because we don't want to just halt the CPU
11386 * if trying to debug across a WFI.
11388 gen_a64_set_pc_im(dc
->pc
);
11389 gen_helper_wfi(cpu_env
);
11390 /* The helper doesn't necessarily throw an exception, but we
11391 * must go back to the main loop to check for interrupts anyway.
11393 tcg_gen_exit_tb(0);
11399 gen_tb_end(tb
, num_insns
);
11402 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
) &&
11403 qemu_log_in_addr_range(pc_start
)) {
11405 qemu_log("----------------\n");
11406 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
11407 log_target_disas(cs
, pc_start
, dc
->pc
- pc_start
,
11408 4 | (bswap_code(dc
->sctlr_b
) ? 2 : 0));
11413 tb
->size
= dc
->pc
- pc_start
;
11414 tb
->icount
= num_insns
;