2 * ARM VFP floating-point operations
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
23 #include "exec/helper-proto.h"
24 #include "fpu/softfloat.h"
25 #include "internals.h"
28 /* VFP support. We follow the convention used for VFP instructions:
29 Single precision routines have a "s" suffix, double precision a
32 /* Convert host exception flags to vfp form. */
33 static inline int vfp_exceptbits_from_host(int host_bits
)
37 if (host_bits
& float_flag_invalid
)
39 if (host_bits
& float_flag_divbyzero
)
41 if (host_bits
& float_flag_overflow
)
43 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
))
45 if (host_bits
& float_flag_inexact
)
47 if (host_bits
& float_flag_input_denormal
)
52 uint32_t HELPER(vfp_get_fpscr
)(CPUARMState
*env
)
56 fpscr
= env
->vfp
.xregs
[ARM_VFP_FPSCR
]
57 | (env
->vfp
.vec_len
<< 16)
58 | (env
->vfp
.vec_stride
<< 20);
60 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
61 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
62 /* FZ16 does not generate an input denormal exception. */
63 i
|= (get_float_exception_flags(&env
->vfp
.fp_status_f16
)
64 & ~float_flag_input_denormal
);
65 fpscr
|= vfp_exceptbits_from_host(i
);
67 i
= env
->vfp
.qc
[0] | env
->vfp
.qc
[1] | env
->vfp
.qc
[2] | env
->vfp
.qc
[3];
68 fpscr
|= i
? FPCR_QC
: 0;
73 uint32_t vfp_get_fpscr(CPUARMState
*env
)
75 return HELPER(vfp_get_fpscr
)(env
);
78 /* Convert vfp exception flags to target form. */
79 static inline int vfp_exceptbits_to_host(int target_bits
)
84 host_bits
|= float_flag_invalid
;
86 host_bits
|= float_flag_divbyzero
;
88 host_bits
|= float_flag_overflow
;
90 host_bits
|= float_flag_underflow
;
91 if (target_bits
& 0x10)
92 host_bits
|= float_flag_inexact
;
93 if (target_bits
& 0x80)
94 host_bits
|= float_flag_input_denormal
;
98 void HELPER(vfp_set_fpscr
)(CPUARMState
*env
, uint32_t val
)
101 uint32_t changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
103 /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
104 if (!cpu_isar_feature(aa64_fp16
, arm_env_get_cpu(env
))) {
108 if (arm_feature(env
, ARM_FEATURE_M
)) {
110 * M profile FPSCR is RES0 for the QC, STRIDE, FZ16, LEN bits
111 * and also for the trapped-exception-handling bits IxE.
117 * We don't implement trapped exception handling, so the
118 * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!)
120 * If we exclude the exception flags, IOC|DZC|OFC|UFC|IXC|IDC
121 * (which are stored in fp_status), and the other RES0 bits
122 * in between, then we clear all of the low 16 bits.
124 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = val
& 0xf7c80000;
125 env
->vfp
.vec_len
= (val
>> 16) & 7;
126 env
->vfp
.vec_stride
= (val
>> 20) & 3;
129 * The bit we set within fpscr_q is arbitrary; the register as a
130 * whole being zero/non-zero is what counts.
132 env
->vfp
.qc
[0] = val
& FPCR_QC
;
138 if (changed
& (3 << 22)) {
141 case FPROUNDING_TIEEVEN
:
142 i
= float_round_nearest_even
;
144 case FPROUNDING_POSINF
:
147 case FPROUNDING_NEGINF
:
148 i
= float_round_down
;
150 case FPROUNDING_ZERO
:
151 i
= float_round_to_zero
;
154 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
155 set_float_rounding_mode(i
, &env
->vfp
.fp_status_f16
);
157 if (changed
& FPCR_FZ16
) {
158 bool ftz_enabled
= val
& FPCR_FZ16
;
159 set_flush_to_zero(ftz_enabled
, &env
->vfp
.fp_status_f16
);
160 set_flush_inputs_to_zero(ftz_enabled
, &env
->vfp
.fp_status_f16
);
162 if (changed
& FPCR_FZ
) {
163 bool ftz_enabled
= val
& FPCR_FZ
;
164 set_flush_to_zero(ftz_enabled
, &env
->vfp
.fp_status
);
165 set_flush_inputs_to_zero(ftz_enabled
, &env
->vfp
.fp_status
);
167 if (changed
& FPCR_DN
) {
168 bool dnan_enabled
= val
& FPCR_DN
;
169 set_default_nan_mode(dnan_enabled
, &env
->vfp
.fp_status
);
170 set_default_nan_mode(dnan_enabled
, &env
->vfp
.fp_status_f16
);
173 /* The exception flags are ORed together when we read fpscr so we
174 * only need to preserve the current state in one of our
175 * float_status values.
177 i
= vfp_exceptbits_to_host(val
);
178 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
179 set_float_exception_flags(0, &env
->vfp
.fp_status_f16
);
180 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
183 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
)
185 HELPER(vfp_set_fpscr
)(env
, val
);
188 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
190 #define VFP_BINOP(name) \
191 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
193 float_status *fpst = fpstp; \
194 return float32_ ## name(a, b, fpst); \
196 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
198 float_status *fpst = fpstp; \
199 return float64_ ## name(a, b, fpst); \
211 float32
VFP_HELPER(neg
, s
)(float32 a
)
213 return float32_chs(a
);
216 float64
VFP_HELPER(neg
, d
)(float64 a
)
218 return float64_chs(a
);
221 float32
VFP_HELPER(abs
, s
)(float32 a
)
223 return float32_abs(a
);
226 float64
VFP_HELPER(abs
, d
)(float64 a
)
228 return float64_abs(a
);
231 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUARMState
*env
)
233 return float32_sqrt(a
, &env
->vfp
.fp_status
);
236 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUARMState
*env
)
238 return float64_sqrt(a
, &env
->vfp
.fp_status
);
241 static void softfloat_to_vfp_compare(CPUARMState
*env
, int cmp
)
245 case float_relation_equal
:
248 case float_relation_less
:
251 case float_relation_greater
:
254 case float_relation_unordered
:
258 g_assert_not_reached();
260 env
->vfp
.xregs
[ARM_VFP_FPSCR
] =
261 deposit32(env
->vfp
.xregs
[ARM_VFP_FPSCR
], 28, 4, flags
);
264 /* XXX: check quiet/signaling case */
265 #define DO_VFP_cmp(p, type) \
266 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
268 softfloat_to_vfp_compare(env, \
269 type ## _compare_quiet(a, b, &env->vfp.fp_status)); \
271 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
273 softfloat_to_vfp_compare(env, \
274 type ## _compare(a, b, &env->vfp.fp_status)); \
276 DO_VFP_cmp(s
, float32
)
277 DO_VFP_cmp(d
, float64
)
280 /* Integer to float and float to integer conversions */
282 #define CONV_ITOF(name, ftype, fsz, sign) \
283 ftype HELPER(name)(uint32_t x, void *fpstp) \
285 float_status *fpst = fpstp; \
286 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
289 #define CONV_FTOI(name, ftype, fsz, sign, round) \
290 sign##int32_t HELPER(name)(ftype x, void *fpstp) \
292 float_status *fpst = fpstp; \
293 if (float##fsz##_is_any_nan(x)) { \
294 float_raise(float_flag_invalid, fpst); \
297 return float##fsz##_to_##sign##int32##round(x, fpst); \
300 #define FLOAT_CONVS(name, p, ftype, fsz, sign) \
301 CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign) \
302 CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \
303 CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero)
305 FLOAT_CONVS(si
, h
, uint32_t, 16, )
306 FLOAT_CONVS(si
, s
, float32
, 32, )
307 FLOAT_CONVS(si
, d
, float64
, 64, )
308 FLOAT_CONVS(ui
, h
, uint32_t, 16, u
)
309 FLOAT_CONVS(ui
, s
, float32
, 32, u
)
310 FLOAT_CONVS(ui
, d
, float64
, 64, u
)
316 /* floating point conversion */
317 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUARMState
*env
)
319 return float32_to_float64(x
, &env
->vfp
.fp_status
);
322 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUARMState
*env
)
324 return float64_to_float32(x
, &env
->vfp
.fp_status
);
327 /* VFP3 fixed point conversion. */
328 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
329 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
331 { return itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); }
333 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ROUND, suff) \
334 uint##isz##_t HELPER(vfp_to##name##p##suff)(float##fsz x, uint32_t shift, \
337 if (unlikely(float##fsz##_is_any_nan(x))) { \
338 float_raise(float_flag_invalid, fpst); \
341 return float##fsz##_to_##itype##_scalbn(x, ROUND, shift, fpst); \
344 #define VFP_CONV_FIX(name, p, fsz, isz, itype) \
345 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
346 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, \
347 float_round_to_zero, _round_to_zero) \
348 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, \
349 get_float_rounding_mode(fpst), )
351 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \
352 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
353 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, \
354 get_float_rounding_mode(fpst), )
356 VFP_CONV_FIX(sh
, d
, 64, 64, int16
)
357 VFP_CONV_FIX(sl
, d
, 64, 64, int32
)
358 VFP_CONV_FIX_A64(sq
, d
, 64, 64, int64
)
359 VFP_CONV_FIX(uh
, d
, 64, 64, uint16
)
360 VFP_CONV_FIX(ul
, d
, 64, 64, uint32
)
361 VFP_CONV_FIX_A64(uq
, d
, 64, 64, uint64
)
362 VFP_CONV_FIX(sh
, s
, 32, 32, int16
)
363 VFP_CONV_FIX(sl
, s
, 32, 32, int32
)
364 VFP_CONV_FIX_A64(sq
, s
, 32, 64, int64
)
365 VFP_CONV_FIX(uh
, s
, 32, 32, uint16
)
366 VFP_CONV_FIX(ul
, s
, 32, 32, uint32
)
367 VFP_CONV_FIX_A64(uq
, s
, 32, 64, uint64
)
370 #undef VFP_CONV_FIX_FLOAT
371 #undef VFP_CONV_FLOAT_FIX_ROUND
372 #undef VFP_CONV_FIX_A64
374 uint32_t HELPER(vfp_sltoh
)(uint32_t x
, uint32_t shift
, void *fpst
)
376 return int32_to_float16_scalbn(x
, -shift
, fpst
);
379 uint32_t HELPER(vfp_ultoh
)(uint32_t x
, uint32_t shift
, void *fpst
)
381 return uint32_to_float16_scalbn(x
, -shift
, fpst
);
384 uint32_t HELPER(vfp_sqtoh
)(uint64_t x
, uint32_t shift
, void *fpst
)
386 return int64_to_float16_scalbn(x
, -shift
, fpst
);
389 uint32_t HELPER(vfp_uqtoh
)(uint64_t x
, uint32_t shift
, void *fpst
)
391 return uint64_to_float16_scalbn(x
, -shift
, fpst
);
394 uint32_t HELPER(vfp_toshh
)(uint32_t x
, uint32_t shift
, void *fpst
)
396 if (unlikely(float16_is_any_nan(x
))) {
397 float_raise(float_flag_invalid
, fpst
);
400 return float16_to_int16_scalbn(x
, get_float_rounding_mode(fpst
),
404 uint32_t HELPER(vfp_touhh
)(uint32_t x
, uint32_t shift
, void *fpst
)
406 if (unlikely(float16_is_any_nan(x
))) {
407 float_raise(float_flag_invalid
, fpst
);
410 return float16_to_uint16_scalbn(x
, get_float_rounding_mode(fpst
),
414 uint32_t HELPER(vfp_toslh
)(uint32_t x
, uint32_t shift
, void *fpst
)
416 if (unlikely(float16_is_any_nan(x
))) {
417 float_raise(float_flag_invalid
, fpst
);
420 return float16_to_int32_scalbn(x
, get_float_rounding_mode(fpst
),
424 uint32_t HELPER(vfp_toulh
)(uint32_t x
, uint32_t shift
, void *fpst
)
426 if (unlikely(float16_is_any_nan(x
))) {
427 float_raise(float_flag_invalid
, fpst
);
430 return float16_to_uint32_scalbn(x
, get_float_rounding_mode(fpst
),
434 uint64_t HELPER(vfp_tosqh
)(uint32_t x
, uint32_t shift
, void *fpst
)
436 if (unlikely(float16_is_any_nan(x
))) {
437 float_raise(float_flag_invalid
, fpst
);
440 return float16_to_int64_scalbn(x
, get_float_rounding_mode(fpst
),
444 uint64_t HELPER(vfp_touqh
)(uint32_t x
, uint32_t shift
, void *fpst
)
446 if (unlikely(float16_is_any_nan(x
))) {
447 float_raise(float_flag_invalid
, fpst
);
450 return float16_to_uint64_scalbn(x
, get_float_rounding_mode(fpst
),
454 /* Set the current fp rounding mode and return the old one.
455 * The argument is a softfloat float_round_ value.
457 uint32_t HELPER(set_rmode
)(uint32_t rmode
, void *fpstp
)
459 float_status
*fp_status
= fpstp
;
461 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
462 set_float_rounding_mode(rmode
, fp_status
);
467 /* Set the current fp rounding mode in the standard fp status and return
468 * the old one. This is for NEON instructions that need to change the
469 * rounding mode but wish to use the standard FPSCR values for everything
470 * else. Always set the rounding mode back to the correct value after
472 * The argument is a softfloat float_round_ value.
474 uint32_t HELPER(set_neon_rmode
)(uint32_t rmode
, CPUARMState
*env
)
476 float_status
*fp_status
= &env
->vfp
.standard_fp_status
;
478 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
479 set_float_rounding_mode(rmode
, fp_status
);
484 /* Half precision conversions. */
485 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, void *fpstp
, uint32_t ahp_mode
)
487 /* Squash FZ16 to 0 for the duration of conversion. In this case,
488 * it would affect flushing input denormals.
490 float_status
*fpst
= fpstp
;
491 flag save
= get_flush_inputs_to_zero(fpst
);
492 set_flush_inputs_to_zero(false, fpst
);
493 float32 r
= float16_to_float32(a
, !ahp_mode
, fpst
);
494 set_flush_inputs_to_zero(save
, fpst
);
498 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, void *fpstp
, uint32_t ahp_mode
)
500 /* Squash FZ16 to 0 for the duration of conversion. In this case,
501 * it would affect flushing output denormals.
503 float_status
*fpst
= fpstp
;
504 flag save
= get_flush_to_zero(fpst
);
505 set_flush_to_zero(false, fpst
);
506 float16 r
= float32_to_float16(a
, !ahp_mode
, fpst
);
507 set_flush_to_zero(save
, fpst
);
511 float64
HELPER(vfp_fcvt_f16_to_f64
)(uint32_t a
, void *fpstp
, uint32_t ahp_mode
)
513 /* Squash FZ16 to 0 for the duration of conversion. In this case,
514 * it would affect flushing input denormals.
516 float_status
*fpst
= fpstp
;
517 flag save
= get_flush_inputs_to_zero(fpst
);
518 set_flush_inputs_to_zero(false, fpst
);
519 float64 r
= float16_to_float64(a
, !ahp_mode
, fpst
);
520 set_flush_inputs_to_zero(save
, fpst
);
524 uint32_t HELPER(vfp_fcvt_f64_to_f16
)(float64 a
, void *fpstp
, uint32_t ahp_mode
)
526 /* Squash FZ16 to 0 for the duration of conversion. In this case,
527 * it would affect flushing output denormals.
529 float_status
*fpst
= fpstp
;
530 flag save
= get_flush_to_zero(fpst
);
531 set_flush_to_zero(false, fpst
);
532 float16 r
= float64_to_float16(a
, !ahp_mode
, fpst
);
533 set_flush_to_zero(save
, fpst
);
537 #define float32_two make_float32(0x40000000)
538 #define float32_three make_float32(0x40400000)
539 #define float32_one_point_five make_float32(0x3fc00000)
541 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
543 float_status
*s
= &env
->vfp
.standard_fp_status
;
544 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
545 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
546 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
547 float_raise(float_flag_input_denormal
, s
);
551 return float32_sub(float32_two
, float32_mul(a
, b
, s
), s
);
554 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
556 float_status
*s
= &env
->vfp
.standard_fp_status
;
558 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
559 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
560 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
561 float_raise(float_flag_input_denormal
, s
);
563 return float32_one_point_five
;
565 product
= float32_mul(a
, b
, s
);
566 return float32_div(float32_sub(float32_three
, product
, s
), float32_two
, s
);
571 /* Constants 256 and 512 are used in some helpers; we avoid relying on
572 * int->float conversions at run-time. */
573 #define float64_256 make_float64(0x4070000000000000LL)
574 #define float64_512 make_float64(0x4080000000000000LL)
575 #define float16_maxnorm make_float16(0x7bff)
576 #define float32_maxnorm make_float32(0x7f7fffff)
577 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
579 /* Reciprocal functions
581 * The algorithm that must be used to calculate the estimate
582 * is specified by the ARM ARM, see FPRecipEstimate()/RecipEstimate
585 /* See RecipEstimate()
587 * input is a 9 bit fixed point number
588 * input range 256 .. 511 for a number from 0.5 <= x < 1.0.
589 * result range 256 .. 511 for a number from 1.0 to 511/256.
592 static int recip_estimate(int input
)
595 assert(256 <= input
&& input
< 512);
599 assert(256 <= r
&& r
< 512);
604 * Common wrapper to call recip_estimate
606 * The parameters are exponent and 64 bit fraction (without implicit
607 * bit) where the binary point is nominally at bit 52. Returns a
608 * float64 which can then be rounded to the appropriate size by the
612 static uint64_t call_recip_estimate(int *exp
, int exp_off
, uint64_t frac
)
614 uint32_t scaled
, estimate
;
615 uint64_t result_frac
;
618 /* Handle sub-normals */
620 if (extract64(frac
, 51, 1) == 0) {
628 /* scaled = UInt('1':fraction<51:44>) */
629 scaled
= deposit32(1 << 8, 0, 8, extract64(frac
, 44, 8));
630 estimate
= recip_estimate(scaled
);
632 result_exp
= exp_off
- *exp
;
633 result_frac
= deposit64(0, 44, 8, estimate
);
634 if (result_exp
== 0) {
635 result_frac
= deposit64(result_frac
>> 1, 51, 1, 1);
636 } else if (result_exp
== -1) {
637 result_frac
= deposit64(result_frac
>> 2, 50, 2, 1);
646 static bool round_to_inf(float_status
*fpst
, bool sign_bit
)
648 switch (fpst
->float_rounding_mode
) {
649 case float_round_nearest_even
: /* Round to Nearest */
651 case float_round_up
: /* Round to +Inf */
653 case float_round_down
: /* Round to -Inf */
655 case float_round_to_zero
: /* Round to Zero */
659 g_assert_not_reached();
662 uint32_t HELPER(recpe_f16
)(uint32_t input
, void *fpstp
)
664 float_status
*fpst
= fpstp
;
665 float16 f16
= float16_squash_input_denormal(input
, fpst
);
666 uint32_t f16_val
= float16_val(f16
);
667 uint32_t f16_sign
= float16_is_neg(f16
);
668 int f16_exp
= extract32(f16_val
, 10, 5);
669 uint32_t f16_frac
= extract32(f16_val
, 0, 10);
672 if (float16_is_any_nan(f16
)) {
674 if (float16_is_signaling_nan(f16
, fpst
)) {
675 float_raise(float_flag_invalid
, fpst
);
676 nan
= float16_silence_nan(f16
, fpst
);
678 if (fpst
->default_nan_mode
) {
679 nan
= float16_default_nan(fpst
);
682 } else if (float16_is_infinity(f16
)) {
683 return float16_set_sign(float16_zero
, float16_is_neg(f16
));
684 } else if (float16_is_zero(f16
)) {
685 float_raise(float_flag_divbyzero
, fpst
);
686 return float16_set_sign(float16_infinity
, float16_is_neg(f16
));
687 } else if (float16_abs(f16
) < (1 << 8)) {
688 /* Abs(value) < 2.0^-16 */
689 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
690 if (round_to_inf(fpst
, f16_sign
)) {
691 return float16_set_sign(float16_infinity
, f16_sign
);
693 return float16_set_sign(float16_maxnorm
, f16_sign
);
695 } else if (f16_exp
>= 29 && fpst
->flush_to_zero
) {
696 float_raise(float_flag_underflow
, fpst
);
697 return float16_set_sign(float16_zero
, float16_is_neg(f16
));
700 f64_frac
= call_recip_estimate(&f16_exp
, 29,
701 ((uint64_t) f16_frac
) << (52 - 10));
703 /* result = sign : result_exp<4:0> : fraction<51:42> */
704 f16_val
= deposit32(0, 15, 1, f16_sign
);
705 f16_val
= deposit32(f16_val
, 10, 5, f16_exp
);
706 f16_val
= deposit32(f16_val
, 0, 10, extract64(f64_frac
, 52 - 10, 10));
707 return make_float16(f16_val
);
710 float32
HELPER(recpe_f32
)(float32 input
, void *fpstp
)
712 float_status
*fpst
= fpstp
;
713 float32 f32
= float32_squash_input_denormal(input
, fpst
);
714 uint32_t f32_val
= float32_val(f32
);
715 bool f32_sign
= float32_is_neg(f32
);
716 int f32_exp
= extract32(f32_val
, 23, 8);
717 uint32_t f32_frac
= extract32(f32_val
, 0, 23);
720 if (float32_is_any_nan(f32
)) {
722 if (float32_is_signaling_nan(f32
, fpst
)) {
723 float_raise(float_flag_invalid
, fpst
);
724 nan
= float32_silence_nan(f32
, fpst
);
726 if (fpst
->default_nan_mode
) {
727 nan
= float32_default_nan(fpst
);
730 } else if (float32_is_infinity(f32
)) {
731 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
732 } else if (float32_is_zero(f32
)) {
733 float_raise(float_flag_divbyzero
, fpst
);
734 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
735 } else if (float32_abs(f32
) < (1ULL << 21)) {
736 /* Abs(value) < 2.0^-128 */
737 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
738 if (round_to_inf(fpst
, f32_sign
)) {
739 return float32_set_sign(float32_infinity
, f32_sign
);
741 return float32_set_sign(float32_maxnorm
, f32_sign
);
743 } else if (f32_exp
>= 253 && fpst
->flush_to_zero
) {
744 float_raise(float_flag_underflow
, fpst
);
745 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
748 f64_frac
= call_recip_estimate(&f32_exp
, 253,
749 ((uint64_t) f32_frac
) << (52 - 23));
751 /* result = sign : result_exp<7:0> : fraction<51:29> */
752 f32_val
= deposit32(0, 31, 1, f32_sign
);
753 f32_val
= deposit32(f32_val
, 23, 8, f32_exp
);
754 f32_val
= deposit32(f32_val
, 0, 23, extract64(f64_frac
, 52 - 23, 23));
755 return make_float32(f32_val
);
758 float64
HELPER(recpe_f64
)(float64 input
, void *fpstp
)
760 float_status
*fpst
= fpstp
;
761 float64 f64
= float64_squash_input_denormal(input
, fpst
);
762 uint64_t f64_val
= float64_val(f64
);
763 bool f64_sign
= float64_is_neg(f64
);
764 int f64_exp
= extract64(f64_val
, 52, 11);
765 uint64_t f64_frac
= extract64(f64_val
, 0, 52);
767 /* Deal with any special cases */
768 if (float64_is_any_nan(f64
)) {
770 if (float64_is_signaling_nan(f64
, fpst
)) {
771 float_raise(float_flag_invalid
, fpst
);
772 nan
= float64_silence_nan(f64
, fpst
);
774 if (fpst
->default_nan_mode
) {
775 nan
= float64_default_nan(fpst
);
778 } else if (float64_is_infinity(f64
)) {
779 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
780 } else if (float64_is_zero(f64
)) {
781 float_raise(float_flag_divbyzero
, fpst
);
782 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
783 } else if ((f64_val
& ~(1ULL << 63)) < (1ULL << 50)) {
784 /* Abs(value) < 2.0^-1024 */
785 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
786 if (round_to_inf(fpst
, f64_sign
)) {
787 return float64_set_sign(float64_infinity
, f64_sign
);
789 return float64_set_sign(float64_maxnorm
, f64_sign
);
791 } else if (f64_exp
>= 2045 && fpst
->flush_to_zero
) {
792 float_raise(float_flag_underflow
, fpst
);
793 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
796 f64_frac
= call_recip_estimate(&f64_exp
, 2045, f64_frac
);
798 /* result = sign : result_exp<10:0> : fraction<51:0>; */
799 f64_val
= deposit64(0, 63, 1, f64_sign
);
800 f64_val
= deposit64(f64_val
, 52, 11, f64_exp
);
801 f64_val
= deposit64(f64_val
, 0, 52, f64_frac
);
802 return make_float64(f64_val
);
805 /* The algorithm that must be used to calculate the estimate
806 * is specified by the ARM ARM.
809 static int do_recip_sqrt_estimate(int a
)
813 assert(128 <= a
&& a
< 512);
821 while (a
* (b
+ 1) * (b
+ 1) < (1 << 28)) {
824 estimate
= (b
+ 1) / 2;
825 assert(256 <= estimate
&& estimate
< 512);
831 static uint64_t recip_sqrt_estimate(int *exp
, int exp_off
, uint64_t frac
)
837 while (extract64(frac
, 51, 1) == 0) {
841 frac
= extract64(frac
, 0, 51) << 1;
845 /* scaled = UInt('01':fraction<51:45>) */
846 scaled
= deposit32(1 << 7, 0, 7, extract64(frac
, 45, 7));
848 /* scaled = UInt('1':fraction<51:44>) */
849 scaled
= deposit32(1 << 8, 0, 8, extract64(frac
, 44, 8));
851 estimate
= do_recip_sqrt_estimate(scaled
);
853 *exp
= (exp_off
- *exp
) / 2;
854 return extract64(estimate
, 0, 8) << 44;
857 uint32_t HELPER(rsqrte_f16
)(uint32_t input
, void *fpstp
)
859 float_status
*s
= fpstp
;
860 float16 f16
= float16_squash_input_denormal(input
, s
);
861 uint16_t val
= float16_val(f16
);
862 bool f16_sign
= float16_is_neg(f16
);
863 int f16_exp
= extract32(val
, 10, 5);
864 uint16_t f16_frac
= extract32(val
, 0, 10);
867 if (float16_is_any_nan(f16
)) {
869 if (float16_is_signaling_nan(f16
, s
)) {
870 float_raise(float_flag_invalid
, s
);
871 nan
= float16_silence_nan(f16
, s
);
873 if (s
->default_nan_mode
) {
874 nan
= float16_default_nan(s
);
877 } else if (float16_is_zero(f16
)) {
878 float_raise(float_flag_divbyzero
, s
);
879 return float16_set_sign(float16_infinity
, f16_sign
);
880 } else if (f16_sign
) {
881 float_raise(float_flag_invalid
, s
);
882 return float16_default_nan(s
);
883 } else if (float16_is_infinity(f16
)) {
887 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
888 * preserving the parity of the exponent. */
890 f64_frac
= ((uint64_t) f16_frac
) << (52 - 10);
892 f64_frac
= recip_sqrt_estimate(&f16_exp
, 44, f64_frac
);
894 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(2) */
895 val
= deposit32(0, 15, 1, f16_sign
);
896 val
= deposit32(val
, 10, 5, f16_exp
);
897 val
= deposit32(val
, 2, 8, extract64(f64_frac
, 52 - 8, 8));
898 return make_float16(val
);
901 float32
HELPER(rsqrte_f32
)(float32 input
, void *fpstp
)
903 float_status
*s
= fpstp
;
904 float32 f32
= float32_squash_input_denormal(input
, s
);
905 uint32_t val
= float32_val(f32
);
906 uint32_t f32_sign
= float32_is_neg(f32
);
907 int f32_exp
= extract32(val
, 23, 8);
908 uint32_t f32_frac
= extract32(val
, 0, 23);
911 if (float32_is_any_nan(f32
)) {
913 if (float32_is_signaling_nan(f32
, s
)) {
914 float_raise(float_flag_invalid
, s
);
915 nan
= float32_silence_nan(f32
, s
);
917 if (s
->default_nan_mode
) {
918 nan
= float32_default_nan(s
);
921 } else if (float32_is_zero(f32
)) {
922 float_raise(float_flag_divbyzero
, s
);
923 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
924 } else if (float32_is_neg(f32
)) {
925 float_raise(float_flag_invalid
, s
);
926 return float32_default_nan(s
);
927 } else if (float32_is_infinity(f32
)) {
931 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
932 * preserving the parity of the exponent. */
934 f64_frac
= ((uint64_t) f32_frac
) << 29;
936 f64_frac
= recip_sqrt_estimate(&f32_exp
, 380, f64_frac
);
938 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(15) */
939 val
= deposit32(0, 31, 1, f32_sign
);
940 val
= deposit32(val
, 23, 8, f32_exp
);
941 val
= deposit32(val
, 15, 8, extract64(f64_frac
, 52 - 8, 8));
942 return make_float32(val
);
945 float64
HELPER(rsqrte_f64
)(float64 input
, void *fpstp
)
947 float_status
*s
= fpstp
;
948 float64 f64
= float64_squash_input_denormal(input
, s
);
949 uint64_t val
= float64_val(f64
);
950 bool f64_sign
= float64_is_neg(f64
);
951 int f64_exp
= extract64(val
, 52, 11);
952 uint64_t f64_frac
= extract64(val
, 0, 52);
954 if (float64_is_any_nan(f64
)) {
956 if (float64_is_signaling_nan(f64
, s
)) {
957 float_raise(float_flag_invalid
, s
);
958 nan
= float64_silence_nan(f64
, s
);
960 if (s
->default_nan_mode
) {
961 nan
= float64_default_nan(s
);
964 } else if (float64_is_zero(f64
)) {
965 float_raise(float_flag_divbyzero
, s
);
966 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
967 } else if (float64_is_neg(f64
)) {
968 float_raise(float_flag_invalid
, s
);
969 return float64_default_nan(s
);
970 } else if (float64_is_infinity(f64
)) {
974 f64_frac
= recip_sqrt_estimate(&f64_exp
, 3068, f64_frac
);
976 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(44) */
977 val
= deposit64(0, 61, 1, f64_sign
);
978 val
= deposit64(val
, 52, 11, f64_exp
);
979 val
= deposit64(val
, 44, 8, extract64(f64_frac
, 52 - 8, 8));
980 return make_float64(val
);
983 uint32_t HELPER(recpe_u32
)(uint32_t a
, void *fpstp
)
985 /* float_status *s = fpstp; */
988 if ((a
& 0x80000000) == 0) {
992 input
= extract32(a
, 23, 9);
993 estimate
= recip_estimate(input
);
995 return deposit32(0, (32 - 9), 9, estimate
);
998 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, void *fpstp
)
1002 if ((a
& 0xc0000000) == 0) {
1006 estimate
= do_recip_sqrt_estimate(extract32(a
, 23, 9));
1008 return deposit32(0, 23, 9, estimate
);
1011 /* VFPv4 fused multiply-accumulate */
1012 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
1014 float_status
*fpst
= fpstp
;
1015 return float32_muladd(a
, b
, c
, 0, fpst
);
1018 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
1020 float_status
*fpst
= fpstp
;
1021 return float64_muladd(a
, b
, c
, 0, fpst
);
1024 /* ARMv8 round to integral */
1025 float32
HELPER(rints_exact
)(float32 x
, void *fp_status
)
1027 return float32_round_to_int(x
, fp_status
);
1030 float64
HELPER(rintd_exact
)(float64 x
, void *fp_status
)
1032 return float64_round_to_int(x
, fp_status
);
1035 float32
HELPER(rints
)(float32 x
, void *fp_status
)
1037 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
1040 ret
= float32_round_to_int(x
, fp_status
);
1042 /* Suppress any inexact exceptions the conversion produced */
1043 if (!(old_flags
& float_flag_inexact
)) {
1044 new_flags
= get_float_exception_flags(fp_status
);
1045 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
1051 float64
HELPER(rintd
)(float64 x
, void *fp_status
)
1053 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
1056 ret
= float64_round_to_int(x
, fp_status
);
1058 new_flags
= get_float_exception_flags(fp_status
);
1060 /* Suppress any inexact exceptions the conversion produced */
1061 if (!(old_flags
& float_flag_inexact
)) {
1062 new_flags
= get_float_exception_flags(fp_status
);
1063 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
1069 /* Convert ARM rounding mode to softfloat */
1070 int arm_rmode_to_sf(int rmode
)
1073 case FPROUNDING_TIEAWAY
:
1074 rmode
= float_round_ties_away
;
1076 case FPROUNDING_ODD
:
1077 /* FIXME: add support for TIEAWAY and ODD */
1078 qemu_log_mask(LOG_UNIMP
, "arm: unimplemented rounding mode: %d\n",
1080 /* fall through for now */
1081 case FPROUNDING_TIEEVEN
:
1083 rmode
= float_round_nearest_even
;
1085 case FPROUNDING_POSINF
:
1086 rmode
= float_round_up
;
1088 case FPROUNDING_NEGINF
:
1089 rmode
= float_round_down
;
1091 case FPROUNDING_ZERO
:
1092 rmode
= float_round_to_zero
;
1099 * Implement float64 to int32_t conversion without saturation;
1100 * the result is supplied modulo 2^32.
1102 uint64_t HELPER(fjcvtzs
)(float64 value
, void *vstatus
)
1104 float_status
*status
= vstatus
;
1107 uint32_t inexact
= 1; /* !Z */
1109 sign
= extract64(value
, 63, 1);
1110 exp
= extract64(value
, 52, 11);
1111 frac
= extract64(value
, 0, 52);
1114 /* While not inexact for IEEE FP, -0.0 is inexact for JavaScript. */
1117 if (status
->flush_inputs_to_zero
) {
1118 float_raise(float_flag_input_denormal
, status
);
1120 float_raise(float_flag_inexact
, status
);
1125 } else if (exp
== 0x7ff) {
1126 /* This operation raises Invalid for both NaN and overflow (Inf). */
1127 float_raise(float_flag_invalid
, status
);
1130 int true_exp
= exp
- 1023;
1131 int shift
= true_exp
- 52;
1133 /* Restore implicit bit. */
1136 /* Shift the fraction into place. */
1138 /* The number is so large we must shift the fraction left. */
1140 /* The fraction is shifted out entirely. */
1145 } else if (shift
> -64) {
1146 /* Normal case -- shift right and notice if bits shift out. */
1147 inexact
= (frac
<< (64 + shift
)) != 0;
1150 /* The fraction is shifted out entirely. */
1154 /* Notice overflow or inexact exceptions. */
1155 if (true_exp
> 31 || frac
> (sign
? 0x80000000ull
: 0x7fffffff)) {
1156 /* Overflow, for which this operation raises invalid. */
1157 float_raise(float_flag_invalid
, status
);
1159 } else if (inexact
) {
1160 float_raise(float_flag_inexact
, status
);
1163 /* Honor the sign. */
1169 /* Pack the result and the env->ZF representation of Z together. */
1170 return deposit64(frac
, 32, 32, inexact
);
1173 uint32_t HELPER(vjcvt
)(float64 value
, CPUARMState
*env
)
1175 uint64_t pair
= HELPER(fjcvtzs
)(value
, &env
->vfp
.fp_status
);
1176 uint32_t result
= pair
;
1177 uint32_t z
= (pair
>> 32) == 0;
1179 /* Store Z, clear NCV, in FPSCR.NZCV. */
1180 env
->vfp
.xregs
[ARM_VFP_FPSCR
]
1181 = (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & ~CPSR_NZCV
) | (z
* CPSR_Z
);
1186 /* Round a float32 to an integer that fits in int32_t or int64_t. */
1187 static float32
frint_s(float32 f
, float_status
*fpst
, int intsize
)
1189 int old_flags
= get_float_exception_flags(fpst
);
1190 uint32_t exp
= extract32(f
, 23, 8);
1192 if (unlikely(exp
== 0xff)) {
1197 /* Round and re-extract the exponent. */
1198 f
= float32_round_to_int(f
, fpst
);
1199 exp
= extract32(f
, 23, 8);
1201 /* Validate the range of the result. */
1202 if (exp
< 126 + intsize
) {
1203 /* abs(F) <= INT{N}_MAX */
1206 if (exp
== 126 + intsize
) {
1207 uint32_t sign
= extract32(f
, 31, 1);
1208 uint32_t frac
= extract32(f
, 0, 23);
1209 if (sign
&& frac
== 0) {
1210 /* F == INT{N}_MIN */
1217 * Raise Invalid and return INT{N}_MIN as a float. Revert any
1218 * inexact exception float32_round_to_int may have raised.
1220 set_float_exception_flags(old_flags
| float_flag_invalid
, fpst
);
1221 return (0x100u
+ 126u + intsize
) << 23;
1224 float32
HELPER(frint32_s
)(float32 f
, void *fpst
)
1226 return frint_s(f
, fpst
, 32);
1229 float32
HELPER(frint64_s
)(float32 f
, void *fpst
)
1231 return frint_s(f
, fpst
, 64);
1234 /* Round a float64 to an integer that fits in int32_t or int64_t. */
1235 static float64
frint_d(float64 f
, float_status
*fpst
, int intsize
)
1237 int old_flags
= get_float_exception_flags(fpst
);
1238 uint32_t exp
= extract64(f
, 52, 11);
1240 if (unlikely(exp
== 0x7ff)) {
1245 /* Round and re-extract the exponent. */
1246 f
= float64_round_to_int(f
, fpst
);
1247 exp
= extract64(f
, 52, 11);
1249 /* Validate the range of the result. */
1250 if (exp
< 1022 + intsize
) {
1251 /* abs(F) <= INT{N}_MAX */
1254 if (exp
== 1022 + intsize
) {
1255 uint64_t sign
= extract64(f
, 63, 1);
1256 uint64_t frac
= extract64(f
, 0, 52);
1257 if (sign
&& frac
== 0) {
1258 /* F == INT{N}_MIN */
1265 * Raise Invalid and return INT{N}_MIN as a float. Revert any
1266 * inexact exception float64_round_to_int may have raised.
1268 set_float_exception_flags(old_flags
| float_flag_invalid
, fpst
);
1269 return (uint64_t)(0x800 + 1022 + intsize
) << 52;
1272 float64
HELPER(frint32_d
)(float64 f
, void *fpst
)
1274 return frint_d(f
, fpst
, 32);
1277 float64
HELPER(frint64_d
)(float64 f
, void *fpst
)
1279 return frint_d(f
, fpst
, 64);