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i386: Make unversioned CPU models be aliases
[mirror_qemu.git] / target / i386 / cpu.c
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/units.h"
22 #include "qemu/cutils.h"
23 #include "qemu/bitops.h"
24 #include "qemu/qemu-print.h"
25
26 #include "cpu.h"
27 #include "exec/exec-all.h"
28 #include "sysemu/kvm.h"
29 #include "sysemu/hvf.h"
30 #include "sysemu/cpus.h"
31 #include "kvm_i386.h"
32 #include "sev_i386.h"
33
34 #include "qemu/error-report.h"
35 #include "qemu/module.h"
36 #include "qemu/option.h"
37 #include "qemu/config-file.h"
38 #include "qapi/error.h"
39 #include "qapi/qapi-visit-machine.h"
40 #include "qapi/qapi-visit-run-state.h"
41 #include "qapi/qmp/qdict.h"
42 #include "qapi/qmp/qerror.h"
43 #include "qapi/visitor.h"
44 #include "qom/qom-qobject.h"
45 #include "sysemu/arch_init.h"
46 #include "qapi/qapi-commands-machine-target.h"
47
48 #include "standard-headers/asm-x86/kvm_para.h"
49
50 #include "sysemu/sysemu.h"
51 #include "sysemu/tcg.h"
52 #include "hw/qdev-properties.h"
53 #include "hw/i386/topology.h"
54 #ifndef CONFIG_USER_ONLY
55 #include "exec/address-spaces.h"
56 #include "hw/hw.h"
57 #include "hw/xen/xen.h"
58 #include "hw/i386/apic_internal.h"
59 #include "hw/boards.h"
60 #endif
61
62 #include "disas/capstone.h"
63
64 /* Helpers for building CPUID[2] descriptors: */
65
66 struct CPUID2CacheDescriptorInfo {
67 enum CacheType type;
68 int level;
69 int size;
70 int line_size;
71 int associativity;
72 };
73
74 /*
75 * Known CPUID 2 cache descriptors.
76 * From Intel SDM Volume 2A, CPUID instruction
77 */
78 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
79 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB,
80 .associativity = 4, .line_size = 32, },
81 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB,
82 .associativity = 4, .line_size = 32, },
83 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
84 .associativity = 4, .line_size = 64, },
85 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
86 .associativity = 2, .line_size = 32, },
87 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
88 .associativity = 4, .line_size = 32, },
89 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
90 .associativity = 4, .line_size = 64, },
91 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB,
92 .associativity = 6, .line_size = 64, },
93 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
94 .associativity = 2, .line_size = 64, },
95 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
96 .associativity = 8, .line_size = 64, },
97 /* lines per sector is not supported cpuid2_cache_descriptor(),
98 * so descriptors 0x22, 0x23 are not included
99 */
100 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
101 .associativity = 16, .line_size = 64, },
102 /* lines per sector is not supported cpuid2_cache_descriptor(),
103 * so descriptors 0x25, 0x20 are not included
104 */
105 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
106 .associativity = 8, .line_size = 64, },
107 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
108 .associativity = 8, .line_size = 64, },
109 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
110 .associativity = 4, .line_size = 32, },
111 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
112 .associativity = 4, .line_size = 32, },
113 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
114 .associativity = 4, .line_size = 32, },
115 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
116 .associativity = 4, .line_size = 32, },
117 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
118 .associativity = 4, .line_size = 32, },
119 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
120 .associativity = 4, .line_size = 64, },
121 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
122 .associativity = 8, .line_size = 64, },
123 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
124 .associativity = 12, .line_size = 64, },
125 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
126 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
127 .associativity = 12, .line_size = 64, },
128 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
129 .associativity = 16, .line_size = 64, },
130 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
131 .associativity = 12, .line_size = 64, },
132 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
133 .associativity = 16, .line_size = 64, },
134 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
135 .associativity = 24, .line_size = 64, },
136 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
137 .associativity = 8, .line_size = 64, },
138 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
139 .associativity = 4, .line_size = 64, },
140 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
141 .associativity = 4, .line_size = 64, },
142 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
143 .associativity = 4, .line_size = 64, },
144 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
145 .associativity = 4, .line_size = 64, },
146 /* lines per sector is not supported cpuid2_cache_descriptor(),
147 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
148 */
149 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
150 .associativity = 8, .line_size = 64, },
151 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
152 .associativity = 2, .line_size = 64, },
153 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
154 .associativity = 8, .line_size = 64, },
155 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
156 .associativity = 8, .line_size = 32, },
157 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
158 .associativity = 8, .line_size = 32, },
159 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
160 .associativity = 8, .line_size = 32, },
161 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
162 .associativity = 8, .line_size = 32, },
163 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
164 .associativity = 4, .line_size = 64, },
165 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
166 .associativity = 8, .line_size = 64, },
167 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
168 .associativity = 4, .line_size = 64, },
169 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
170 .associativity = 4, .line_size = 64, },
171 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
172 .associativity = 4, .line_size = 64, },
173 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
174 .associativity = 8, .line_size = 64, },
175 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
176 .associativity = 8, .line_size = 64, },
177 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
178 .associativity = 8, .line_size = 64, },
179 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
180 .associativity = 12, .line_size = 64, },
181 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
182 .associativity = 12, .line_size = 64, },
183 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
184 .associativity = 12, .line_size = 64, },
185 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
186 .associativity = 16, .line_size = 64, },
187 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
188 .associativity = 16, .line_size = 64, },
189 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
190 .associativity = 16, .line_size = 64, },
191 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
192 .associativity = 24, .line_size = 64, },
193 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
194 .associativity = 24, .line_size = 64, },
195 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
196 .associativity = 24, .line_size = 64, },
197 };
198
199 /*
200 * "CPUID leaf 2 does not report cache descriptor information,
201 * use CPUID leaf 4 to query cache parameters"
202 */
203 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
204
205 /*
206 * Return a CPUID 2 cache descriptor for a given cache.
207 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
208 */
209 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
210 {
211 int i;
212
213 assert(cache->size > 0);
214 assert(cache->level > 0);
215 assert(cache->line_size > 0);
216 assert(cache->associativity > 0);
217 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
218 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
219 if (d->level == cache->level && d->type == cache->type &&
220 d->size == cache->size && d->line_size == cache->line_size &&
221 d->associativity == cache->associativity) {
222 return i;
223 }
224 }
225
226 return CACHE_DESCRIPTOR_UNAVAILABLE;
227 }
228
229 /* CPUID Leaf 4 constants: */
230
231 /* EAX: */
232 #define CACHE_TYPE_D 1
233 #define CACHE_TYPE_I 2
234 #define CACHE_TYPE_UNIFIED 3
235
236 #define CACHE_LEVEL(l) (l << 5)
237
238 #define CACHE_SELF_INIT_LEVEL (1 << 8)
239
240 /* EDX: */
241 #define CACHE_NO_INVD_SHARING (1 << 0)
242 #define CACHE_INCLUSIVE (1 << 1)
243 #define CACHE_COMPLEX_IDX (1 << 2)
244
245 /* Encode CacheType for CPUID[4].EAX */
246 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
247 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
248 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
249 0 /* Invalid value */)
250
251
252 /* Encode cache info for CPUID[4] */
253 static void encode_cache_cpuid4(CPUCacheInfo *cache,
254 int num_apic_ids, int num_cores,
255 uint32_t *eax, uint32_t *ebx,
256 uint32_t *ecx, uint32_t *edx)
257 {
258 assert(cache->size == cache->line_size * cache->associativity *
259 cache->partitions * cache->sets);
260
261 assert(num_apic_ids > 0);
262 *eax = CACHE_TYPE(cache->type) |
263 CACHE_LEVEL(cache->level) |
264 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
265 ((num_cores - 1) << 26) |
266 ((num_apic_ids - 1) << 14);
267
268 assert(cache->line_size > 0);
269 assert(cache->partitions > 0);
270 assert(cache->associativity > 0);
271 /* We don't implement fully-associative caches */
272 assert(cache->associativity < cache->sets);
273 *ebx = (cache->line_size - 1) |
274 ((cache->partitions - 1) << 12) |
275 ((cache->associativity - 1) << 22);
276
277 assert(cache->sets > 0);
278 *ecx = cache->sets - 1;
279
280 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
281 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
282 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
283 }
284
285 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
286 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
287 {
288 assert(cache->size % 1024 == 0);
289 assert(cache->lines_per_tag > 0);
290 assert(cache->associativity > 0);
291 assert(cache->line_size > 0);
292 return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
293 (cache->lines_per_tag << 8) | (cache->line_size);
294 }
295
296 #define ASSOC_FULL 0xFF
297
298 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
299 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
300 a == 2 ? 0x2 : \
301 a == 4 ? 0x4 : \
302 a == 8 ? 0x6 : \
303 a == 16 ? 0x8 : \
304 a == 32 ? 0xA : \
305 a == 48 ? 0xB : \
306 a == 64 ? 0xC : \
307 a == 96 ? 0xD : \
308 a == 128 ? 0xE : \
309 a == ASSOC_FULL ? 0xF : \
310 0 /* invalid value */)
311
312 /*
313 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
314 * @l3 can be NULL.
315 */
316 static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
317 CPUCacheInfo *l3,
318 uint32_t *ecx, uint32_t *edx)
319 {
320 assert(l2->size % 1024 == 0);
321 assert(l2->associativity > 0);
322 assert(l2->lines_per_tag > 0);
323 assert(l2->line_size > 0);
324 *ecx = ((l2->size / 1024) << 16) |
325 (AMD_ENC_ASSOC(l2->associativity) << 12) |
326 (l2->lines_per_tag << 8) | (l2->line_size);
327
328 if (l3) {
329 assert(l3->size % (512 * 1024) == 0);
330 assert(l3->associativity > 0);
331 assert(l3->lines_per_tag > 0);
332 assert(l3->line_size > 0);
333 *edx = ((l3->size / (512 * 1024)) << 18) |
334 (AMD_ENC_ASSOC(l3->associativity) << 12) |
335 (l3->lines_per_tag << 8) | (l3->line_size);
336 } else {
337 *edx = 0;
338 }
339 }
340
341 /*
342 * Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E
343 * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3.
344 * Define the constants to build the cpu topology. Right now, TOPOEXT
345 * feature is enabled only on EPYC. So, these constants are based on
346 * EPYC supported configurations. We may need to handle the cases if
347 * these values change in future.
348 */
349 /* Maximum core complexes in a node */
350 #define MAX_CCX 2
351 /* Maximum cores in a core complex */
352 #define MAX_CORES_IN_CCX 4
353 /* Maximum cores in a node */
354 #define MAX_CORES_IN_NODE 8
355 /* Maximum nodes in a socket */
356 #define MAX_NODES_PER_SOCKET 4
357
358 /*
359 * Figure out the number of nodes required to build this config.
360 * Max cores in a node is 8
361 */
362 static int nodes_in_socket(int nr_cores)
363 {
364 int nodes;
365
366 nodes = DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE);
367
368 /* Hardware does not support config with 3 nodes, return 4 in that case */
369 return (nodes == 3) ? 4 : nodes;
370 }
371
372 /*
373 * Decide the number of cores in a core complex with the given nr_cores using
374 * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and
375 * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible
376 * L3 cache is shared across all cores in a core complex. So, this will also
377 * tell us how many cores are sharing the L3 cache.
378 */
379 static int cores_in_core_complex(int nr_cores)
380 {
381 int nodes;
382
383 /* Check if we can fit all the cores in one core complex */
384 if (nr_cores <= MAX_CORES_IN_CCX) {
385 return nr_cores;
386 }
387 /* Get the number of nodes required to build this config */
388 nodes = nodes_in_socket(nr_cores);
389
390 /*
391 * Divide the cores accros all the core complexes
392 * Return rounded up value
393 */
394 return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX);
395 }
396
397 /* Encode cache info for CPUID[8000001D] */
398 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs,
399 uint32_t *eax, uint32_t *ebx,
400 uint32_t *ecx, uint32_t *edx)
401 {
402 uint32_t l3_cores;
403 assert(cache->size == cache->line_size * cache->associativity *
404 cache->partitions * cache->sets);
405
406 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
407 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
408
409 /* L3 is shared among multiple cores */
410 if (cache->level == 3) {
411 l3_cores = cores_in_core_complex(cs->nr_cores);
412 *eax |= ((l3_cores * cs->nr_threads) - 1) << 14;
413 } else {
414 *eax |= ((cs->nr_threads - 1) << 14);
415 }
416
417 assert(cache->line_size > 0);
418 assert(cache->partitions > 0);
419 assert(cache->associativity > 0);
420 /* We don't implement fully-associative caches */
421 assert(cache->associativity < cache->sets);
422 *ebx = (cache->line_size - 1) |
423 ((cache->partitions - 1) << 12) |
424 ((cache->associativity - 1) << 22);
425
426 assert(cache->sets > 0);
427 *ecx = cache->sets - 1;
428
429 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
430 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
431 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
432 }
433
434 /* Data structure to hold the configuration info for a given core index */
435 struct core_topology {
436 /* core complex id of the current core index */
437 int ccx_id;
438 /*
439 * Adjusted core index for this core in the topology
440 * This can be 0,1,2,3 with max 4 cores in a core complex
441 */
442 int core_id;
443 /* Node id for this core index */
444 int node_id;
445 /* Number of nodes in this config */
446 int num_nodes;
447 };
448
449 /*
450 * Build the configuration closely match the EPYC hardware. Using the EPYC
451 * hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE)
452 * right now. This could change in future.
453 * nr_cores : Total number of cores in the config
454 * core_id : Core index of the current CPU
455 * topo : Data structure to hold all the config info for this core index
456 */
457 static void build_core_topology(int nr_cores, int core_id,
458 struct core_topology *topo)
459 {
460 int nodes, cores_in_ccx;
461
462 /* First get the number of nodes required */
463 nodes = nodes_in_socket(nr_cores);
464
465 cores_in_ccx = cores_in_core_complex(nr_cores);
466
467 topo->node_id = core_id / (cores_in_ccx * MAX_CCX);
468 topo->ccx_id = (core_id % (cores_in_ccx * MAX_CCX)) / cores_in_ccx;
469 topo->core_id = core_id % cores_in_ccx;
470 topo->num_nodes = nodes;
471 }
472
473 /* Encode cache info for CPUID[8000001E] */
474 static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu,
475 uint32_t *eax, uint32_t *ebx,
476 uint32_t *ecx, uint32_t *edx)
477 {
478 struct core_topology topo = {0};
479 unsigned long nodes;
480 int shift;
481
482 build_core_topology(cs->nr_cores, cpu->core_id, &topo);
483 *eax = cpu->apic_id;
484 /*
485 * CPUID_Fn8000001E_EBX
486 * 31:16 Reserved
487 * 15:8 Threads per core (The number of threads per core is
488 * Threads per core + 1)
489 * 7:0 Core id (see bit decoding below)
490 * SMT:
491 * 4:3 node id
492 * 2 Core complex id
493 * 1:0 Core id
494 * Non SMT:
495 * 5:4 node id
496 * 3 Core complex id
497 * 1:0 Core id
498 */
499 if (cs->nr_threads - 1) {
500 *ebx = ((cs->nr_threads - 1) << 8) | (topo.node_id << 3) |
501 (topo.ccx_id << 2) | topo.core_id;
502 } else {
503 *ebx = (topo.node_id << 4) | (topo.ccx_id << 3) | topo.core_id;
504 }
505 /*
506 * CPUID_Fn8000001E_ECX
507 * 31:11 Reserved
508 * 10:8 Nodes per processor (Nodes per processor is number of nodes + 1)
509 * 7:0 Node id (see bit decoding below)
510 * 2 Socket id
511 * 1:0 Node id
512 */
513 if (topo.num_nodes <= 4) {
514 *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << 2) |
515 topo.node_id;
516 } else {
517 /*
518 * Node id fix up. Actual hardware supports up to 4 nodes. But with
519 * more than 32 cores, we may end up with more than 4 nodes.
520 * Node id is a combination of socket id and node id. Only requirement
521 * here is that this number should be unique accross the system.
522 * Shift the socket id to accommodate more nodes. We dont expect both
523 * socket id and node id to be big number at the same time. This is not
524 * an ideal config but we need to to support it. Max nodes we can have
525 * is 32 (255/8) with 8 cores per node and 255 max cores. We only need
526 * 5 bits for nodes. Find the left most set bit to represent the total
527 * number of nodes. find_last_bit returns last set bit(0 based). Left
528 * shift(+1) the socket id to represent all the nodes.
529 */
530 nodes = topo.num_nodes - 1;
531 shift = find_last_bit(&nodes, 8);
532 *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << (shift + 1)) |
533 topo.node_id;
534 }
535 *edx = 0;
536 }
537
538 /*
539 * Definitions of the hardcoded cache entries we expose:
540 * These are legacy cache values. If there is a need to change any
541 * of these values please use builtin_x86_defs
542 */
543
544 /* L1 data cache: */
545 static CPUCacheInfo legacy_l1d_cache = {
546 .type = DATA_CACHE,
547 .level = 1,
548 .size = 32 * KiB,
549 .self_init = 1,
550 .line_size = 64,
551 .associativity = 8,
552 .sets = 64,
553 .partitions = 1,
554 .no_invd_sharing = true,
555 };
556
557 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
558 static CPUCacheInfo legacy_l1d_cache_amd = {
559 .type = DATA_CACHE,
560 .level = 1,
561 .size = 64 * KiB,
562 .self_init = 1,
563 .line_size = 64,
564 .associativity = 2,
565 .sets = 512,
566 .partitions = 1,
567 .lines_per_tag = 1,
568 .no_invd_sharing = true,
569 };
570
571 /* L1 instruction cache: */
572 static CPUCacheInfo legacy_l1i_cache = {
573 .type = INSTRUCTION_CACHE,
574 .level = 1,
575 .size = 32 * KiB,
576 .self_init = 1,
577 .line_size = 64,
578 .associativity = 8,
579 .sets = 64,
580 .partitions = 1,
581 .no_invd_sharing = true,
582 };
583
584 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
585 static CPUCacheInfo legacy_l1i_cache_amd = {
586 .type = INSTRUCTION_CACHE,
587 .level = 1,
588 .size = 64 * KiB,
589 .self_init = 1,
590 .line_size = 64,
591 .associativity = 2,
592 .sets = 512,
593 .partitions = 1,
594 .lines_per_tag = 1,
595 .no_invd_sharing = true,
596 };
597
598 /* Level 2 unified cache: */
599 static CPUCacheInfo legacy_l2_cache = {
600 .type = UNIFIED_CACHE,
601 .level = 2,
602 .size = 4 * MiB,
603 .self_init = 1,
604 .line_size = 64,
605 .associativity = 16,
606 .sets = 4096,
607 .partitions = 1,
608 .no_invd_sharing = true,
609 };
610
611 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
612 static CPUCacheInfo legacy_l2_cache_cpuid2 = {
613 .type = UNIFIED_CACHE,
614 .level = 2,
615 .size = 2 * MiB,
616 .line_size = 64,
617 .associativity = 8,
618 };
619
620
621 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
622 static CPUCacheInfo legacy_l2_cache_amd = {
623 .type = UNIFIED_CACHE,
624 .level = 2,
625 .size = 512 * KiB,
626 .line_size = 64,
627 .lines_per_tag = 1,
628 .associativity = 16,
629 .sets = 512,
630 .partitions = 1,
631 };
632
633 /* Level 3 unified cache: */
634 static CPUCacheInfo legacy_l3_cache = {
635 .type = UNIFIED_CACHE,
636 .level = 3,
637 .size = 16 * MiB,
638 .line_size = 64,
639 .associativity = 16,
640 .sets = 16384,
641 .partitions = 1,
642 .lines_per_tag = 1,
643 .self_init = true,
644 .inclusive = true,
645 .complex_indexing = true,
646 };
647
648 /* TLB definitions: */
649
650 #define L1_DTLB_2M_ASSOC 1
651 #define L1_DTLB_2M_ENTRIES 255
652 #define L1_DTLB_4K_ASSOC 1
653 #define L1_DTLB_4K_ENTRIES 255
654
655 #define L1_ITLB_2M_ASSOC 1
656 #define L1_ITLB_2M_ENTRIES 255
657 #define L1_ITLB_4K_ASSOC 1
658 #define L1_ITLB_4K_ENTRIES 255
659
660 #define L2_DTLB_2M_ASSOC 0 /* disabled */
661 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
662 #define L2_DTLB_4K_ASSOC 4
663 #define L2_DTLB_4K_ENTRIES 512
664
665 #define L2_ITLB_2M_ASSOC 0 /* disabled */
666 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
667 #define L2_ITLB_4K_ASSOC 4
668 #define L2_ITLB_4K_ENTRIES 512
669
670 /* CPUID Leaf 0x14 constants: */
671 #define INTEL_PT_MAX_SUBLEAF 0x1
672 /*
673 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
674 * MSR can be accessed;
675 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
676 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
677 * of Intel PT MSRs across warm reset;
678 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
679 */
680 #define INTEL_PT_MINIMAL_EBX 0xf
681 /*
682 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
683 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
684 * accessed;
685 * bit[01]: ToPA tables can hold any number of output entries, up to the
686 * maximum allowed by the MaskOrTableOffset field of
687 * IA32_RTIT_OUTPUT_MASK_PTRS;
688 * bit[02]: Support Single-Range Output scheme;
689 */
690 #define INTEL_PT_MINIMAL_ECX 0x7
691 /* generated packets which contain IP payloads have LIP values */
692 #define INTEL_PT_IP_LIP (1 << 31)
693 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
694 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
695 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
696 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
697 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
698
699 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
700 uint32_t vendor2, uint32_t vendor3)
701 {
702 int i;
703 for (i = 0; i < 4; i++) {
704 dst[i] = vendor1 >> (8 * i);
705 dst[i + 4] = vendor2 >> (8 * i);
706 dst[i + 8] = vendor3 >> (8 * i);
707 }
708 dst[CPUID_VENDOR_SZ] = '\0';
709 }
710
711 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
712 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
713 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
714 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
715 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
716 CPUID_PSE36 | CPUID_FXSR)
717 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
718 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
719 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
720 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
721 CPUID_PAE | CPUID_SEP | CPUID_APIC)
722
723 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
724 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
725 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
726 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
727 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
728 /* partly implemented:
729 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
730 /* missing:
731 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
732 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
733 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
734 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
735 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
736 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \
737 CPUID_EXT_RDRAND)
738 /* missing:
739 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
740 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
741 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
742 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
743 CPUID_EXT_F16C */
744
745 #ifdef TARGET_X86_64
746 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
747 #else
748 #define TCG_EXT2_X86_64_FEATURES 0
749 #endif
750
751 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
752 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
753 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
754 TCG_EXT2_X86_64_FEATURES)
755 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
756 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
757 #define TCG_EXT4_FEATURES 0
758 #define TCG_SVM_FEATURES CPUID_SVM_NPT
759 #define TCG_KVM_FEATURES 0
760 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
761 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
762 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
763 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
764 CPUID_7_0_EBX_ERMS)
765 /* missing:
766 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
767 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
768 CPUID_7_0_EBX_RDSEED */
769 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \
770 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
771 CPUID_7_0_ECX_LA57)
772 #define TCG_7_0_EDX_FEATURES 0
773 #define TCG_APM_FEATURES 0
774 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
775 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
776 /* missing:
777 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
778
779 typedef enum FeatureWordType {
780 CPUID_FEATURE_WORD,
781 MSR_FEATURE_WORD,
782 } FeatureWordType;
783
784 typedef struct FeatureWordInfo {
785 FeatureWordType type;
786 /* feature flags names are taken from "Intel Processor Identification and
787 * the CPUID Instruction" and AMD's "CPUID Specification".
788 * In cases of disagreement between feature naming conventions,
789 * aliases may be added.
790 */
791 const char *feat_names[32];
792 union {
793 /* If type==CPUID_FEATURE_WORD */
794 struct {
795 uint32_t eax; /* Input EAX for CPUID */
796 bool needs_ecx; /* CPUID instruction uses ECX as input */
797 uint32_t ecx; /* Input ECX value for CPUID */
798 int reg; /* output register (R_* constant) */
799 } cpuid;
800 /* If type==MSR_FEATURE_WORD */
801 struct {
802 uint32_t index;
803 struct { /*CPUID that enumerate this MSR*/
804 FeatureWord cpuid_class;
805 uint32_t cpuid_flag;
806 } cpuid_dep;
807 } msr;
808 };
809 uint32_t tcg_features; /* Feature flags supported by TCG */
810 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
811 uint32_t migratable_flags; /* Feature flags known to be migratable */
812 /* Features that shouldn't be auto-enabled by "-cpu host" */
813 uint32_t no_autoenable_flags;
814 } FeatureWordInfo;
815
816 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
817 [FEAT_1_EDX] = {
818 .type = CPUID_FEATURE_WORD,
819 .feat_names = {
820 "fpu", "vme", "de", "pse",
821 "tsc", "msr", "pae", "mce",
822 "cx8", "apic", NULL, "sep",
823 "mtrr", "pge", "mca", "cmov",
824 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
825 NULL, "ds" /* Intel dts */, "acpi", "mmx",
826 "fxsr", "sse", "sse2", "ss",
827 "ht" /* Intel htt */, "tm", "ia64", "pbe",
828 },
829 .cpuid = {.eax = 1, .reg = R_EDX, },
830 .tcg_features = TCG_FEATURES,
831 },
832 [FEAT_1_ECX] = {
833 .type = CPUID_FEATURE_WORD,
834 .feat_names = {
835 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
836 "ds-cpl", "vmx", "smx", "est",
837 "tm2", "ssse3", "cid", NULL,
838 "fma", "cx16", "xtpr", "pdcm",
839 NULL, "pcid", "dca", "sse4.1",
840 "sse4.2", "x2apic", "movbe", "popcnt",
841 "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
842 "avx", "f16c", "rdrand", "hypervisor",
843 },
844 .cpuid = { .eax = 1, .reg = R_ECX, },
845 .tcg_features = TCG_EXT_FEATURES,
846 },
847 /* Feature names that are already defined on feature_name[] but
848 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
849 * names on feat_names below. They are copied automatically
850 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
851 */
852 [FEAT_8000_0001_EDX] = {
853 .type = CPUID_FEATURE_WORD,
854 .feat_names = {
855 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
856 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
857 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
858 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
859 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
860 "nx", NULL, "mmxext", NULL /* mmx */,
861 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
862 NULL, "lm", "3dnowext", "3dnow",
863 },
864 .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
865 .tcg_features = TCG_EXT2_FEATURES,
866 },
867 [FEAT_8000_0001_ECX] = {
868 .type = CPUID_FEATURE_WORD,
869 .feat_names = {
870 "lahf-lm", "cmp-legacy", "svm", "extapic",
871 "cr8legacy", "abm", "sse4a", "misalignsse",
872 "3dnowprefetch", "osvw", "ibs", "xop",
873 "skinit", "wdt", NULL, "lwp",
874 "fma4", "tce", NULL, "nodeid-msr",
875 NULL, "tbm", "topoext", "perfctr-core",
876 "perfctr-nb", NULL, NULL, NULL,
877 NULL, NULL, NULL, NULL,
878 },
879 .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
880 .tcg_features = TCG_EXT3_FEATURES,
881 /*
882 * TOPOEXT is always allowed but can't be enabled blindly by
883 * "-cpu host", as it requires consistent cache topology info
884 * to be provided so it doesn't confuse guests.
885 */
886 .no_autoenable_flags = CPUID_EXT3_TOPOEXT,
887 },
888 [FEAT_C000_0001_EDX] = {
889 .type = CPUID_FEATURE_WORD,
890 .feat_names = {
891 NULL, NULL, "xstore", "xstore-en",
892 NULL, NULL, "xcrypt", "xcrypt-en",
893 "ace2", "ace2-en", "phe", "phe-en",
894 "pmm", "pmm-en", NULL, NULL,
895 NULL, NULL, NULL, NULL,
896 NULL, NULL, NULL, NULL,
897 NULL, NULL, NULL, NULL,
898 NULL, NULL, NULL, NULL,
899 },
900 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
901 .tcg_features = TCG_EXT4_FEATURES,
902 },
903 [FEAT_KVM] = {
904 .type = CPUID_FEATURE_WORD,
905 .feat_names = {
906 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
907 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
908 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
909 NULL, NULL, NULL, NULL,
910 NULL, NULL, NULL, NULL,
911 NULL, NULL, NULL, NULL,
912 "kvmclock-stable-bit", NULL, NULL, NULL,
913 NULL, NULL, NULL, NULL,
914 },
915 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
916 .tcg_features = TCG_KVM_FEATURES,
917 },
918 [FEAT_KVM_HINTS] = {
919 .type = CPUID_FEATURE_WORD,
920 .feat_names = {
921 "kvm-hint-dedicated", NULL, NULL, NULL,
922 NULL, NULL, NULL, NULL,
923 NULL, NULL, NULL, NULL,
924 NULL, NULL, NULL, NULL,
925 NULL, NULL, NULL, NULL,
926 NULL, NULL, NULL, NULL,
927 NULL, NULL, NULL, NULL,
928 NULL, NULL, NULL, NULL,
929 },
930 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
931 .tcg_features = TCG_KVM_FEATURES,
932 /*
933 * KVM hints aren't auto-enabled by -cpu host, they need to be
934 * explicitly enabled in the command-line.
935 */
936 .no_autoenable_flags = ~0U,
937 },
938 /*
939 * .feat_names are commented out for Hyper-V enlightenments because we
940 * don't want to have two different ways for enabling them on QEMU command
941 * line. Some features (e.g. "hyperv_time", "hyperv_vapic", ...) require
942 * enabling several feature bits simultaneously, exposing these bits
943 * individually may just confuse guests.
944 */
945 [FEAT_HYPERV_EAX] = {
946 .type = CPUID_FEATURE_WORD,
947 .feat_names = {
948 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
949 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
950 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
951 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
952 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
953 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
954 NULL /* hv_msr_debug_access */, NULL /* hv_msr_reenlightenment_access */,
955 NULL, NULL,
956 NULL, NULL, NULL, NULL,
957 NULL, NULL, NULL, NULL,
958 NULL, NULL, NULL, NULL,
959 NULL, NULL, NULL, NULL,
960 },
961 .cpuid = { .eax = 0x40000003, .reg = R_EAX, },
962 },
963 [FEAT_HYPERV_EBX] = {
964 .type = CPUID_FEATURE_WORD,
965 .feat_names = {
966 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
967 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
968 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
969 NULL /* hv_create_port */, NULL /* hv_connect_port */,
970 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
971 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
972 NULL, NULL,
973 NULL, NULL, NULL, NULL,
974 NULL, NULL, NULL, NULL,
975 NULL, NULL, NULL, NULL,
976 NULL, NULL, NULL, NULL,
977 },
978 .cpuid = { .eax = 0x40000003, .reg = R_EBX, },
979 },
980 [FEAT_HYPERV_EDX] = {
981 .type = CPUID_FEATURE_WORD,
982 .feat_names = {
983 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
984 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
985 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
986 NULL, NULL,
987 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
988 NULL, NULL, NULL, NULL,
989 NULL, NULL, NULL, NULL,
990 NULL, NULL, NULL, NULL,
991 NULL, NULL, NULL, NULL,
992 NULL, NULL, NULL, NULL,
993 },
994 .cpuid = { .eax = 0x40000003, .reg = R_EDX, },
995 },
996 [FEAT_HV_RECOMM_EAX] = {
997 .type = CPUID_FEATURE_WORD,
998 .feat_names = {
999 NULL /* hv_recommend_pv_as_switch */,
1000 NULL /* hv_recommend_pv_tlbflush_local */,
1001 NULL /* hv_recommend_pv_tlbflush_remote */,
1002 NULL /* hv_recommend_msr_apic_access */,
1003 NULL /* hv_recommend_msr_reset */,
1004 NULL /* hv_recommend_relaxed_timing */,
1005 NULL /* hv_recommend_dma_remapping */,
1006 NULL /* hv_recommend_int_remapping */,
1007 NULL /* hv_recommend_x2apic_msrs */,
1008 NULL /* hv_recommend_autoeoi_deprecation */,
1009 NULL /* hv_recommend_pv_ipi */,
1010 NULL /* hv_recommend_ex_hypercalls */,
1011 NULL /* hv_hypervisor_is_nested */,
1012 NULL /* hv_recommend_int_mbec */,
1013 NULL /* hv_recommend_evmcs */,
1014 NULL,
1015 NULL, NULL, NULL, NULL,
1016 NULL, NULL, NULL, NULL,
1017 NULL, NULL, NULL, NULL,
1018 NULL, NULL, NULL, NULL,
1019 },
1020 .cpuid = { .eax = 0x40000004, .reg = R_EAX, },
1021 },
1022 [FEAT_HV_NESTED_EAX] = {
1023 .type = CPUID_FEATURE_WORD,
1024 .cpuid = { .eax = 0x4000000A, .reg = R_EAX, },
1025 },
1026 [FEAT_SVM] = {
1027 .type = CPUID_FEATURE_WORD,
1028 .feat_names = {
1029 "npt", "lbrv", "svm-lock", "nrip-save",
1030 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
1031 NULL, NULL, "pause-filter", NULL,
1032 "pfthreshold", NULL, NULL, NULL,
1033 NULL, NULL, NULL, NULL,
1034 NULL, NULL, NULL, NULL,
1035 NULL, NULL, NULL, NULL,
1036 NULL, NULL, NULL, NULL,
1037 },
1038 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
1039 .tcg_features = TCG_SVM_FEATURES,
1040 },
1041 [FEAT_7_0_EBX] = {
1042 .type = CPUID_FEATURE_WORD,
1043 .feat_names = {
1044 "fsgsbase", "tsc-adjust", NULL, "bmi1",
1045 "hle", "avx2", NULL, "smep",
1046 "bmi2", "erms", "invpcid", "rtm",
1047 NULL, NULL, "mpx", NULL,
1048 "avx512f", "avx512dq", "rdseed", "adx",
1049 "smap", "avx512ifma", "pcommit", "clflushopt",
1050 "clwb", "intel-pt", "avx512pf", "avx512er",
1051 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
1052 },
1053 .cpuid = {
1054 .eax = 7,
1055 .needs_ecx = true, .ecx = 0,
1056 .reg = R_EBX,
1057 },
1058 .tcg_features = TCG_7_0_EBX_FEATURES,
1059 },
1060 [FEAT_7_0_ECX] = {
1061 .type = CPUID_FEATURE_WORD,
1062 .feat_names = {
1063 NULL, "avx512vbmi", "umip", "pku",
1064 NULL /* ospke */, NULL, "avx512vbmi2", NULL,
1065 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
1066 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
1067 "la57", NULL, NULL, NULL,
1068 NULL, NULL, "rdpid", NULL,
1069 NULL, "cldemote", NULL, "movdiri",
1070 "movdir64b", NULL, NULL, NULL,
1071 },
1072 .cpuid = {
1073 .eax = 7,
1074 .needs_ecx = true, .ecx = 0,
1075 .reg = R_ECX,
1076 },
1077 .tcg_features = TCG_7_0_ECX_FEATURES,
1078 },
1079 [FEAT_7_0_EDX] = {
1080 .type = CPUID_FEATURE_WORD,
1081 .feat_names = {
1082 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
1083 NULL, NULL, NULL, NULL,
1084 NULL, NULL, "md-clear", NULL,
1085 NULL, NULL, NULL, NULL,
1086 NULL, NULL, NULL, NULL,
1087 NULL, NULL, NULL, NULL,
1088 NULL, NULL, "spec-ctrl", "stibp",
1089 NULL, "arch-capabilities", "core-capability", "ssbd",
1090 },
1091 .cpuid = {
1092 .eax = 7,
1093 .needs_ecx = true, .ecx = 0,
1094 .reg = R_EDX,
1095 },
1096 .tcg_features = TCG_7_0_EDX_FEATURES,
1097 },
1098 [FEAT_8000_0007_EDX] = {
1099 .type = CPUID_FEATURE_WORD,
1100 .feat_names = {
1101 NULL, NULL, NULL, NULL,
1102 NULL, NULL, NULL, NULL,
1103 "invtsc", NULL, NULL, NULL,
1104 NULL, NULL, NULL, NULL,
1105 NULL, NULL, NULL, NULL,
1106 NULL, NULL, NULL, NULL,
1107 NULL, NULL, NULL, NULL,
1108 NULL, NULL, NULL, NULL,
1109 },
1110 .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
1111 .tcg_features = TCG_APM_FEATURES,
1112 .unmigratable_flags = CPUID_APM_INVTSC,
1113 },
1114 [FEAT_8000_0008_EBX] = {
1115 .type = CPUID_FEATURE_WORD,
1116 .feat_names = {
1117 NULL, NULL, NULL, NULL,
1118 NULL, NULL, NULL, NULL,
1119 NULL, "wbnoinvd", NULL, NULL,
1120 "ibpb", NULL, NULL, NULL,
1121 NULL, NULL, NULL, NULL,
1122 NULL, NULL, NULL, NULL,
1123 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
1124 NULL, NULL, NULL, NULL,
1125 },
1126 .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
1127 .tcg_features = 0,
1128 .unmigratable_flags = 0,
1129 },
1130 [FEAT_XSAVE] = {
1131 .type = CPUID_FEATURE_WORD,
1132 .feat_names = {
1133 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
1134 NULL, NULL, NULL, NULL,
1135 NULL, NULL, NULL, NULL,
1136 NULL, NULL, NULL, NULL,
1137 NULL, NULL, NULL, NULL,
1138 NULL, NULL, NULL, NULL,
1139 NULL, NULL, NULL, NULL,
1140 NULL, NULL, NULL, NULL,
1141 },
1142 .cpuid = {
1143 .eax = 0xd,
1144 .needs_ecx = true, .ecx = 1,
1145 .reg = R_EAX,
1146 },
1147 .tcg_features = TCG_XSAVE_FEATURES,
1148 },
1149 [FEAT_6_EAX] = {
1150 .type = CPUID_FEATURE_WORD,
1151 .feat_names = {
1152 NULL, NULL, "arat", NULL,
1153 NULL, NULL, NULL, NULL,
1154 NULL, NULL, NULL, NULL,
1155 NULL, NULL, NULL, NULL,
1156 NULL, NULL, NULL, NULL,
1157 NULL, NULL, NULL, NULL,
1158 NULL, NULL, NULL, NULL,
1159 NULL, NULL, NULL, NULL,
1160 },
1161 .cpuid = { .eax = 6, .reg = R_EAX, },
1162 .tcg_features = TCG_6_EAX_FEATURES,
1163 },
1164 [FEAT_XSAVE_COMP_LO] = {
1165 .type = CPUID_FEATURE_WORD,
1166 .cpuid = {
1167 .eax = 0xD,
1168 .needs_ecx = true, .ecx = 0,
1169 .reg = R_EAX,
1170 },
1171 .tcg_features = ~0U,
1172 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
1173 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
1174 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
1175 XSTATE_PKRU_MASK,
1176 },
1177 [FEAT_XSAVE_COMP_HI] = {
1178 .type = CPUID_FEATURE_WORD,
1179 .cpuid = {
1180 .eax = 0xD,
1181 .needs_ecx = true, .ecx = 0,
1182 .reg = R_EDX,
1183 },
1184 .tcg_features = ~0U,
1185 },
1186 /*Below are MSR exposed features*/
1187 [FEAT_ARCH_CAPABILITIES] = {
1188 .type = MSR_FEATURE_WORD,
1189 .feat_names = {
1190 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
1191 "ssb-no", "mds-no", NULL, NULL,
1192 NULL, NULL, NULL, NULL,
1193 NULL, NULL, NULL, NULL,
1194 NULL, NULL, NULL, NULL,
1195 NULL, NULL, NULL, NULL,
1196 NULL, NULL, NULL, NULL,
1197 NULL, NULL, NULL, NULL,
1198 },
1199 .msr = {
1200 .index = MSR_IA32_ARCH_CAPABILITIES,
1201 .cpuid_dep = {
1202 FEAT_7_0_EDX,
1203 CPUID_7_0_EDX_ARCH_CAPABILITIES
1204 }
1205 },
1206 },
1207 [FEAT_CORE_CAPABILITY] = {
1208 .type = MSR_FEATURE_WORD,
1209 .feat_names = {
1210 NULL, NULL, NULL, NULL,
1211 NULL, "split-lock-detect", NULL, NULL,
1212 NULL, NULL, NULL, NULL,
1213 NULL, NULL, NULL, NULL,
1214 NULL, NULL, NULL, NULL,
1215 NULL, NULL, NULL, NULL,
1216 NULL, NULL, NULL, NULL,
1217 NULL, NULL, NULL, NULL,
1218 },
1219 .msr = {
1220 .index = MSR_IA32_CORE_CAPABILITY,
1221 .cpuid_dep = {
1222 FEAT_7_0_EDX,
1223 CPUID_7_0_EDX_CORE_CAPABILITY,
1224 },
1225 },
1226 },
1227 };
1228
1229 typedef struct X86RegisterInfo32 {
1230 /* Name of register */
1231 const char *name;
1232 /* QAPI enum value register */
1233 X86CPURegister32 qapi_enum;
1234 } X86RegisterInfo32;
1235
1236 #define REGISTER(reg) \
1237 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
1238 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
1239 REGISTER(EAX),
1240 REGISTER(ECX),
1241 REGISTER(EDX),
1242 REGISTER(EBX),
1243 REGISTER(ESP),
1244 REGISTER(EBP),
1245 REGISTER(ESI),
1246 REGISTER(EDI),
1247 };
1248 #undef REGISTER
1249
1250 typedef struct ExtSaveArea {
1251 uint32_t feature, bits;
1252 uint32_t offset, size;
1253 } ExtSaveArea;
1254
1255 static const ExtSaveArea x86_ext_save_areas[] = {
1256 [XSTATE_FP_BIT] = {
1257 /* x87 FP state component is always enabled if XSAVE is supported */
1258 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1259 /* x87 state is in the legacy region of the XSAVE area */
1260 .offset = 0,
1261 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1262 },
1263 [XSTATE_SSE_BIT] = {
1264 /* SSE state component is always enabled if XSAVE is supported */
1265 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1266 /* SSE state is in the legacy region of the XSAVE area */
1267 .offset = 0,
1268 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1269 },
1270 [XSTATE_YMM_BIT] =
1271 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
1272 .offset = offsetof(X86XSaveArea, avx_state),
1273 .size = sizeof(XSaveAVX) },
1274 [XSTATE_BNDREGS_BIT] =
1275 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
1276 .offset = offsetof(X86XSaveArea, bndreg_state),
1277 .size = sizeof(XSaveBNDREG) },
1278 [XSTATE_BNDCSR_BIT] =
1279 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
1280 .offset = offsetof(X86XSaveArea, bndcsr_state),
1281 .size = sizeof(XSaveBNDCSR) },
1282 [XSTATE_OPMASK_BIT] =
1283 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1284 .offset = offsetof(X86XSaveArea, opmask_state),
1285 .size = sizeof(XSaveOpmask) },
1286 [XSTATE_ZMM_Hi256_BIT] =
1287 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1288 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
1289 .size = sizeof(XSaveZMM_Hi256) },
1290 [XSTATE_Hi16_ZMM_BIT] =
1291 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1292 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
1293 .size = sizeof(XSaveHi16_ZMM) },
1294 [XSTATE_PKRU_BIT] =
1295 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
1296 .offset = offsetof(X86XSaveArea, pkru_state),
1297 .size = sizeof(XSavePKRU) },
1298 };
1299
1300 static uint32_t xsave_area_size(uint64_t mask)
1301 {
1302 int i;
1303 uint64_t ret = 0;
1304
1305 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1306 const ExtSaveArea *esa = &x86_ext_save_areas[i];
1307 if ((mask >> i) & 1) {
1308 ret = MAX(ret, esa->offset + esa->size);
1309 }
1310 }
1311 return ret;
1312 }
1313
1314 static inline bool accel_uses_host_cpuid(void)
1315 {
1316 return kvm_enabled() || hvf_enabled();
1317 }
1318
1319 static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
1320 {
1321 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
1322 cpu->env.features[FEAT_XSAVE_COMP_LO];
1323 }
1324
1325 const char *get_register_name_32(unsigned int reg)
1326 {
1327 if (reg >= CPU_NB_REGS32) {
1328 return NULL;
1329 }
1330 return x86_reg_info_32[reg].name;
1331 }
1332
1333 /*
1334 * Returns the set of feature flags that are supported and migratable by
1335 * QEMU, for a given FeatureWord.
1336 */
1337 static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
1338 {
1339 FeatureWordInfo *wi = &feature_word_info[w];
1340 uint32_t r = 0;
1341 int i;
1342
1343 for (i = 0; i < 32; i++) {
1344 uint32_t f = 1U << i;
1345
1346 /* If the feature name is known, it is implicitly considered migratable,
1347 * unless it is explicitly set in unmigratable_flags */
1348 if ((wi->migratable_flags & f) ||
1349 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1350 r |= f;
1351 }
1352 }
1353 return r;
1354 }
1355
1356 void host_cpuid(uint32_t function, uint32_t count,
1357 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
1358 {
1359 uint32_t vec[4];
1360
1361 #ifdef __x86_64__
1362 asm volatile("cpuid"
1363 : "=a"(vec[0]), "=b"(vec[1]),
1364 "=c"(vec[2]), "=d"(vec[3])
1365 : "0"(function), "c"(count) : "cc");
1366 #elif defined(__i386__)
1367 asm volatile("pusha \n\t"
1368 "cpuid \n\t"
1369 "mov %%eax, 0(%2) \n\t"
1370 "mov %%ebx, 4(%2) \n\t"
1371 "mov %%ecx, 8(%2) \n\t"
1372 "mov %%edx, 12(%2) \n\t"
1373 "popa"
1374 : : "a"(function), "c"(count), "S"(vec)
1375 : "memory", "cc");
1376 #else
1377 abort();
1378 #endif
1379
1380 if (eax)
1381 *eax = vec[0];
1382 if (ebx)
1383 *ebx = vec[1];
1384 if (ecx)
1385 *ecx = vec[2];
1386 if (edx)
1387 *edx = vec[3];
1388 }
1389
1390 void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
1391 {
1392 uint32_t eax, ebx, ecx, edx;
1393
1394 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1395 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
1396
1397 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1398 if (family) {
1399 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1400 }
1401 if (model) {
1402 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1403 }
1404 if (stepping) {
1405 *stepping = eax & 0x0F;
1406 }
1407 }
1408
1409 /* CPU class name definitions: */
1410
1411 /* Return type name for a given CPU model name
1412 * Caller is responsible for freeing the returned string.
1413 */
1414 static char *x86_cpu_type_name(const char *model_name)
1415 {
1416 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1417 }
1418
1419 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1420 {
1421 ObjectClass *oc;
1422 char *typename = x86_cpu_type_name(cpu_model);
1423 oc = object_class_by_name(typename);
1424 g_free(typename);
1425 return oc;
1426 }
1427
1428 static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1429 {
1430 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1431 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
1432 return g_strndup(class_name,
1433 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
1434 }
1435
1436 typedef struct PropValue {
1437 const char *prop, *value;
1438 } PropValue;
1439
1440 typedef struct X86CPUVersionDefinition {
1441 X86CPUVersion version;
1442 const char *alias;
1443 PropValue *props;
1444 } X86CPUVersionDefinition;
1445
1446 /* Base definition for a CPU model */
1447 typedef struct X86CPUDefinition {
1448 const char *name;
1449 uint32_t level;
1450 uint32_t xlevel;
1451 /* vendor is zero-terminated, 12 character ASCII string */
1452 char vendor[CPUID_VENDOR_SZ + 1];
1453 int family;
1454 int model;
1455 int stepping;
1456 FeatureWordArray features;
1457 const char *model_id;
1458 CPUCaches *cache_info;
1459 /*
1460 * Definitions for alternative versions of CPU model.
1461 * List is terminated by item with version == 0.
1462 * If NULL, version 1 will be registered automatically.
1463 */
1464 const X86CPUVersionDefinition *versions;
1465 } X86CPUDefinition;
1466
1467 /* Reference to a specific CPU model version */
1468 struct X86CPUModel {
1469 /* Base CPU definition */
1470 X86CPUDefinition *cpudef;
1471 /* CPU model version */
1472 X86CPUVersion version;
1473 /*
1474 * If true, this is an alias CPU model.
1475 * This matters only for "-cpu help" and query-cpu-definitions
1476 */
1477 bool is_alias;
1478 };
1479
1480 /* Get full model name for CPU version */
1481 static char *x86_cpu_versioned_model_name(X86CPUDefinition *cpudef,
1482 X86CPUVersion version)
1483 {
1484 assert(version > 0);
1485 return g_strdup_printf("%s-v%d", cpudef->name, (int)version);
1486 }
1487
1488 static const X86CPUVersionDefinition *x86_cpu_def_get_versions(X86CPUDefinition *def)
1489 {
1490 /* When X86CPUDefinition::versions is NULL, we register only v1 */
1491 static const X86CPUVersionDefinition default_version_list[] = {
1492 { 1 },
1493 { /* end of list */ }
1494 };
1495
1496 return def->versions ?: default_version_list;
1497 }
1498
1499 static CPUCaches epyc_cache_info = {
1500 .l1d_cache = &(CPUCacheInfo) {
1501 .type = DATA_CACHE,
1502 .level = 1,
1503 .size = 32 * KiB,
1504 .line_size = 64,
1505 .associativity = 8,
1506 .partitions = 1,
1507 .sets = 64,
1508 .lines_per_tag = 1,
1509 .self_init = 1,
1510 .no_invd_sharing = true,
1511 },
1512 .l1i_cache = &(CPUCacheInfo) {
1513 .type = INSTRUCTION_CACHE,
1514 .level = 1,
1515 .size = 64 * KiB,
1516 .line_size = 64,
1517 .associativity = 4,
1518 .partitions = 1,
1519 .sets = 256,
1520 .lines_per_tag = 1,
1521 .self_init = 1,
1522 .no_invd_sharing = true,
1523 },
1524 .l2_cache = &(CPUCacheInfo) {
1525 .type = UNIFIED_CACHE,
1526 .level = 2,
1527 .size = 512 * KiB,
1528 .line_size = 64,
1529 .associativity = 8,
1530 .partitions = 1,
1531 .sets = 1024,
1532 .lines_per_tag = 1,
1533 },
1534 .l3_cache = &(CPUCacheInfo) {
1535 .type = UNIFIED_CACHE,
1536 .level = 3,
1537 .size = 8 * MiB,
1538 .line_size = 64,
1539 .associativity = 16,
1540 .partitions = 1,
1541 .sets = 8192,
1542 .lines_per_tag = 1,
1543 .self_init = true,
1544 .inclusive = true,
1545 .complex_indexing = true,
1546 },
1547 };
1548
1549 static X86CPUDefinition builtin_x86_defs[] = {
1550 {
1551 .name = "qemu64",
1552 .level = 0xd,
1553 .vendor = CPUID_VENDOR_AMD,
1554 .family = 6,
1555 .model = 6,
1556 .stepping = 3,
1557 .features[FEAT_1_EDX] =
1558 PPRO_FEATURES |
1559 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1560 CPUID_PSE36,
1561 .features[FEAT_1_ECX] =
1562 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
1563 .features[FEAT_8000_0001_EDX] =
1564 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1565 .features[FEAT_8000_0001_ECX] =
1566 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
1567 .xlevel = 0x8000000A,
1568 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1569 },
1570 {
1571 .name = "phenom",
1572 .level = 5,
1573 .vendor = CPUID_VENDOR_AMD,
1574 .family = 16,
1575 .model = 2,
1576 .stepping = 3,
1577 /* Missing: CPUID_HT */
1578 .features[FEAT_1_EDX] =
1579 PPRO_FEATURES |
1580 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1581 CPUID_PSE36 | CPUID_VME,
1582 .features[FEAT_1_ECX] =
1583 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
1584 CPUID_EXT_POPCNT,
1585 .features[FEAT_8000_0001_EDX] =
1586 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
1587 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
1588 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
1589 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1590 CPUID_EXT3_CR8LEG,
1591 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1592 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
1593 .features[FEAT_8000_0001_ECX] =
1594 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
1595 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
1596 /* Missing: CPUID_SVM_LBRV */
1597 .features[FEAT_SVM] =
1598 CPUID_SVM_NPT,
1599 .xlevel = 0x8000001A,
1600 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
1601 },
1602 {
1603 .name = "core2duo",
1604 .level = 10,
1605 .vendor = CPUID_VENDOR_INTEL,
1606 .family = 6,
1607 .model = 15,
1608 .stepping = 11,
1609 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1610 .features[FEAT_1_EDX] =
1611 PPRO_FEATURES |
1612 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1613 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
1614 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
1615 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
1616 .features[FEAT_1_ECX] =
1617 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
1618 CPUID_EXT_CX16,
1619 .features[FEAT_8000_0001_EDX] =
1620 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1621 .features[FEAT_8000_0001_ECX] =
1622 CPUID_EXT3_LAHF_LM,
1623 .xlevel = 0x80000008,
1624 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
1625 },
1626 {
1627 .name = "kvm64",
1628 .level = 0xd,
1629 .vendor = CPUID_VENDOR_INTEL,
1630 .family = 15,
1631 .model = 6,
1632 .stepping = 1,
1633 /* Missing: CPUID_HT */
1634 .features[FEAT_1_EDX] =
1635 PPRO_FEATURES | CPUID_VME |
1636 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1637 CPUID_PSE36,
1638 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
1639 .features[FEAT_1_ECX] =
1640 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
1641 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
1642 .features[FEAT_8000_0001_EDX] =
1643 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1644 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1645 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
1646 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1647 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
1648 .features[FEAT_8000_0001_ECX] =
1649 0,
1650 .xlevel = 0x80000008,
1651 .model_id = "Common KVM processor"
1652 },
1653 {
1654 .name = "qemu32",
1655 .level = 4,
1656 .vendor = CPUID_VENDOR_INTEL,
1657 .family = 6,
1658 .model = 6,
1659 .stepping = 3,
1660 .features[FEAT_1_EDX] =
1661 PPRO_FEATURES,
1662 .features[FEAT_1_ECX] =
1663 CPUID_EXT_SSE3,
1664 .xlevel = 0x80000004,
1665 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1666 },
1667 {
1668 .name = "kvm32",
1669 .level = 5,
1670 .vendor = CPUID_VENDOR_INTEL,
1671 .family = 15,
1672 .model = 6,
1673 .stepping = 1,
1674 .features[FEAT_1_EDX] =
1675 PPRO_FEATURES | CPUID_VME |
1676 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
1677 .features[FEAT_1_ECX] =
1678 CPUID_EXT_SSE3,
1679 .features[FEAT_8000_0001_ECX] =
1680 0,
1681 .xlevel = 0x80000008,
1682 .model_id = "Common 32-bit KVM processor"
1683 },
1684 {
1685 .name = "coreduo",
1686 .level = 10,
1687 .vendor = CPUID_VENDOR_INTEL,
1688 .family = 6,
1689 .model = 14,
1690 .stepping = 8,
1691 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1692 .features[FEAT_1_EDX] =
1693 PPRO_FEATURES | CPUID_VME |
1694 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
1695 CPUID_SS,
1696 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
1697 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
1698 .features[FEAT_1_ECX] =
1699 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
1700 .features[FEAT_8000_0001_EDX] =
1701 CPUID_EXT2_NX,
1702 .xlevel = 0x80000008,
1703 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
1704 },
1705 {
1706 .name = "486",
1707 .level = 1,
1708 .vendor = CPUID_VENDOR_INTEL,
1709 .family = 4,
1710 .model = 8,
1711 .stepping = 0,
1712 .features[FEAT_1_EDX] =
1713 I486_FEATURES,
1714 .xlevel = 0,
1715 .model_id = "",
1716 },
1717 {
1718 .name = "pentium",
1719 .level = 1,
1720 .vendor = CPUID_VENDOR_INTEL,
1721 .family = 5,
1722 .model = 4,
1723 .stepping = 3,
1724 .features[FEAT_1_EDX] =
1725 PENTIUM_FEATURES,
1726 .xlevel = 0,
1727 .model_id = "",
1728 },
1729 {
1730 .name = "pentium2",
1731 .level = 2,
1732 .vendor = CPUID_VENDOR_INTEL,
1733 .family = 6,
1734 .model = 5,
1735 .stepping = 2,
1736 .features[FEAT_1_EDX] =
1737 PENTIUM2_FEATURES,
1738 .xlevel = 0,
1739 .model_id = "",
1740 },
1741 {
1742 .name = "pentium3",
1743 .level = 3,
1744 .vendor = CPUID_VENDOR_INTEL,
1745 .family = 6,
1746 .model = 7,
1747 .stepping = 3,
1748 .features[FEAT_1_EDX] =
1749 PENTIUM3_FEATURES,
1750 .xlevel = 0,
1751 .model_id = "",
1752 },
1753 {
1754 .name = "athlon",
1755 .level = 2,
1756 .vendor = CPUID_VENDOR_AMD,
1757 .family = 6,
1758 .model = 2,
1759 .stepping = 3,
1760 .features[FEAT_1_EDX] =
1761 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
1762 CPUID_MCA,
1763 .features[FEAT_8000_0001_EDX] =
1764 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
1765 .xlevel = 0x80000008,
1766 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1767 },
1768 {
1769 .name = "n270",
1770 .level = 10,
1771 .vendor = CPUID_VENDOR_INTEL,
1772 .family = 6,
1773 .model = 28,
1774 .stepping = 2,
1775 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1776 .features[FEAT_1_EDX] =
1777 PPRO_FEATURES |
1778 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
1779 CPUID_ACPI | CPUID_SS,
1780 /* Some CPUs got no CPUID_SEP */
1781 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
1782 * CPUID_EXT_XTPR */
1783 .features[FEAT_1_ECX] =
1784 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
1785 CPUID_EXT_MOVBE,
1786 .features[FEAT_8000_0001_EDX] =
1787 CPUID_EXT2_NX,
1788 .features[FEAT_8000_0001_ECX] =
1789 CPUID_EXT3_LAHF_LM,
1790 .xlevel = 0x80000008,
1791 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
1792 },
1793 {
1794 .name = "Conroe",
1795 .level = 10,
1796 .vendor = CPUID_VENDOR_INTEL,
1797 .family = 6,
1798 .model = 15,
1799 .stepping = 3,
1800 .features[FEAT_1_EDX] =
1801 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1802 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1803 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1804 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1805 CPUID_DE | CPUID_FP87,
1806 .features[FEAT_1_ECX] =
1807 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
1808 .features[FEAT_8000_0001_EDX] =
1809 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
1810 .features[FEAT_8000_0001_ECX] =
1811 CPUID_EXT3_LAHF_LM,
1812 .xlevel = 0x80000008,
1813 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
1814 },
1815 {
1816 .name = "Penryn",
1817 .level = 10,
1818 .vendor = CPUID_VENDOR_INTEL,
1819 .family = 6,
1820 .model = 23,
1821 .stepping = 3,
1822 .features[FEAT_1_EDX] =
1823 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1824 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1825 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1826 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1827 CPUID_DE | CPUID_FP87,
1828 .features[FEAT_1_ECX] =
1829 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1830 CPUID_EXT_SSE3,
1831 .features[FEAT_8000_0001_EDX] =
1832 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
1833 .features[FEAT_8000_0001_ECX] =
1834 CPUID_EXT3_LAHF_LM,
1835 .xlevel = 0x80000008,
1836 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1837 },
1838 {
1839 .name = "Nehalem",
1840 .level = 11,
1841 .vendor = CPUID_VENDOR_INTEL,
1842 .family = 6,
1843 .model = 26,
1844 .stepping = 3,
1845 .features[FEAT_1_EDX] =
1846 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1847 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1848 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1849 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1850 CPUID_DE | CPUID_FP87,
1851 .features[FEAT_1_ECX] =
1852 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1853 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
1854 .features[FEAT_8000_0001_EDX] =
1855 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1856 .features[FEAT_8000_0001_ECX] =
1857 CPUID_EXT3_LAHF_LM,
1858 .xlevel = 0x80000008,
1859 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1860 .versions = (X86CPUVersionDefinition[]) {
1861 { .version = 1 },
1862 {
1863 .version = 2,
1864 .alias = "Nehalem-IBRS",
1865 .props = (PropValue[]) {
1866 { "spec-ctrl", "on" },
1867 { "model-id",
1868 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" },
1869 { /* end of list */ }
1870 }
1871 },
1872 { /* end of list */ }
1873 }
1874 },
1875 {
1876 .name = "Westmere",
1877 .level = 11,
1878 .vendor = CPUID_VENDOR_INTEL,
1879 .family = 6,
1880 .model = 44,
1881 .stepping = 1,
1882 .features[FEAT_1_EDX] =
1883 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1884 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1885 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1886 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1887 CPUID_DE | CPUID_FP87,
1888 .features[FEAT_1_ECX] =
1889 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1890 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1891 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1892 .features[FEAT_8000_0001_EDX] =
1893 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1894 .features[FEAT_8000_0001_ECX] =
1895 CPUID_EXT3_LAHF_LM,
1896 .features[FEAT_6_EAX] =
1897 CPUID_6_EAX_ARAT,
1898 .xlevel = 0x80000008,
1899 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1900 .versions = (X86CPUVersionDefinition[]) {
1901 { .version = 1 },
1902 {
1903 .version = 2,
1904 .alias = "Westmere-IBRS",
1905 .props = (PropValue[]) {
1906 { "spec-ctrl", "on" },
1907 { "model-id",
1908 "Westmere E56xx/L56xx/X56xx (IBRS update)" },
1909 { /* end of list */ }
1910 }
1911 },
1912 { /* end of list */ }
1913 }
1914 },
1915 {
1916 .name = "SandyBridge",
1917 .level = 0xd,
1918 .vendor = CPUID_VENDOR_INTEL,
1919 .family = 6,
1920 .model = 42,
1921 .stepping = 1,
1922 .features[FEAT_1_EDX] =
1923 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1924 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1925 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1926 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1927 CPUID_DE | CPUID_FP87,
1928 .features[FEAT_1_ECX] =
1929 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1930 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1931 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1932 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1933 CPUID_EXT_SSE3,
1934 .features[FEAT_8000_0001_EDX] =
1935 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1936 CPUID_EXT2_SYSCALL,
1937 .features[FEAT_8000_0001_ECX] =
1938 CPUID_EXT3_LAHF_LM,
1939 .features[FEAT_XSAVE] =
1940 CPUID_XSAVE_XSAVEOPT,
1941 .features[FEAT_6_EAX] =
1942 CPUID_6_EAX_ARAT,
1943 .xlevel = 0x80000008,
1944 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1945 .versions = (X86CPUVersionDefinition[]) {
1946 { .version = 1 },
1947 {
1948 .version = 2,
1949 .alias = "SandyBridge-IBRS",
1950 .props = (PropValue[]) {
1951 { "spec-ctrl", "on" },
1952 { "model-id",
1953 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" },
1954 { /* end of list */ }
1955 }
1956 },
1957 { /* end of list */ }
1958 }
1959 },
1960 {
1961 .name = "IvyBridge",
1962 .level = 0xd,
1963 .vendor = CPUID_VENDOR_INTEL,
1964 .family = 6,
1965 .model = 58,
1966 .stepping = 9,
1967 .features[FEAT_1_EDX] =
1968 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1969 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1970 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1971 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1972 CPUID_DE | CPUID_FP87,
1973 .features[FEAT_1_ECX] =
1974 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1975 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1976 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1977 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1978 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1979 .features[FEAT_7_0_EBX] =
1980 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1981 CPUID_7_0_EBX_ERMS,
1982 .features[FEAT_8000_0001_EDX] =
1983 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1984 CPUID_EXT2_SYSCALL,
1985 .features[FEAT_8000_0001_ECX] =
1986 CPUID_EXT3_LAHF_LM,
1987 .features[FEAT_XSAVE] =
1988 CPUID_XSAVE_XSAVEOPT,
1989 .features[FEAT_6_EAX] =
1990 CPUID_6_EAX_ARAT,
1991 .xlevel = 0x80000008,
1992 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1993 .versions = (X86CPUVersionDefinition[]) {
1994 { .version = 1 },
1995 {
1996 .version = 2,
1997 .alias = "IvyBridge-IBRS",
1998 .props = (PropValue[]) {
1999 { "spec-ctrl", "on" },
2000 { "model-id",
2001 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
2002 { /* end of list */ }
2003 }
2004 },
2005 { /* end of list */ }
2006 }
2007 },
2008 {
2009 .name = "Haswell",
2010 .level = 0xd,
2011 .vendor = CPUID_VENDOR_INTEL,
2012 .family = 6,
2013 .model = 60,
2014 .stepping = 4,
2015 .features[FEAT_1_EDX] =
2016 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2017 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2018 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2019 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2020 CPUID_DE | CPUID_FP87,
2021 .features[FEAT_1_ECX] =
2022 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2023 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2024 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2025 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2026 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2027 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2028 .features[FEAT_8000_0001_EDX] =
2029 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2030 CPUID_EXT2_SYSCALL,
2031 .features[FEAT_8000_0001_ECX] =
2032 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2033 .features[FEAT_7_0_EBX] =
2034 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2035 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2036 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2037 CPUID_7_0_EBX_RTM,
2038 .features[FEAT_XSAVE] =
2039 CPUID_XSAVE_XSAVEOPT,
2040 .features[FEAT_6_EAX] =
2041 CPUID_6_EAX_ARAT,
2042 .xlevel = 0x80000008,
2043 .model_id = "Intel Core Processor (Haswell)",
2044 .versions = (X86CPUVersionDefinition[]) {
2045 { .version = 1 },
2046 {
2047 .version = 2,
2048 .alias = "Haswell-noTSX",
2049 .props = (PropValue[]) {
2050 { "hle", "off" },
2051 { "rtm", "off" },
2052 { "stepping", "1" },
2053 { "model-id", "Intel Core Processor (Haswell, no TSX)", },
2054 { /* end of list */ }
2055 },
2056 },
2057 {
2058 .version = 3,
2059 .alias = "Haswell-IBRS",
2060 .props = (PropValue[]) {
2061 /* Restore TSX features removed by -v2 above */
2062 { "hle", "on" },
2063 { "rtm", "on" },
2064 /*
2065 * Haswell and Haswell-IBRS had stepping=4 in
2066 * QEMU 4.0 and older
2067 */
2068 { "stepping", "4" },
2069 { "spec-ctrl", "on" },
2070 { "model-id",
2071 "Intel Core Processor (Haswell, IBRS)" },
2072 { /* end of list */ }
2073 }
2074 },
2075 {
2076 .version = 4,
2077 .alias = "Haswell-noTSX-IBRS",
2078 .props = (PropValue[]) {
2079 { "hle", "off" },
2080 { "rtm", "off" },
2081 /* spec-ctrl was already enabled by -v3 above */
2082 { "stepping", "1" },
2083 { "model-id",
2084 "Intel Core Processor (Haswell, no TSX, IBRS)" },
2085 { /* end of list */ }
2086 }
2087 },
2088 { /* end of list */ }
2089 }
2090 },
2091 {
2092 .name = "Broadwell",
2093 .level = 0xd,
2094 .vendor = CPUID_VENDOR_INTEL,
2095 .family = 6,
2096 .model = 61,
2097 .stepping = 2,
2098 .features[FEAT_1_EDX] =
2099 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2100 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2101 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2102 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2103 CPUID_DE | CPUID_FP87,
2104 .features[FEAT_1_ECX] =
2105 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2106 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2107 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2108 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2109 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2110 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2111 .features[FEAT_8000_0001_EDX] =
2112 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2113 CPUID_EXT2_SYSCALL,
2114 .features[FEAT_8000_0001_ECX] =
2115 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2116 .features[FEAT_7_0_EBX] =
2117 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2118 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2119 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2120 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2121 CPUID_7_0_EBX_SMAP,
2122 .features[FEAT_XSAVE] =
2123 CPUID_XSAVE_XSAVEOPT,
2124 .features[FEAT_6_EAX] =
2125 CPUID_6_EAX_ARAT,
2126 .xlevel = 0x80000008,
2127 .model_id = "Intel Core Processor (Broadwell)",
2128 .versions = (X86CPUVersionDefinition[]) {
2129 { .version = 1 },
2130 {
2131 .version = 2,
2132 .alias = "Broadwell-noTSX",
2133 .props = (PropValue[]) {
2134 { "hle", "off" },
2135 { "rtm", "off" },
2136 { "model-id", "Intel Core Processor (Broadwell, no TSX)", },
2137 { /* end of list */ }
2138 },
2139 },
2140 {
2141 .version = 3,
2142 .alias = "Broadwell-IBRS",
2143 .props = (PropValue[]) {
2144 /* Restore TSX features removed by -v2 above */
2145 { "hle", "on" },
2146 { "rtm", "on" },
2147 { "spec-ctrl", "on" },
2148 { "model-id",
2149 "Intel Core Processor (Broadwell, IBRS)" },
2150 { /* end of list */ }
2151 }
2152 },
2153 {
2154 .version = 4,
2155 .alias = "Broadwell-noTSX-IBRS",
2156 .props = (PropValue[]) {
2157 { "hle", "off" },
2158 { "rtm", "off" },
2159 /* spec-ctrl was already enabled by -v3 above */
2160 { "model-id",
2161 "Intel Core Processor (Broadwell, no TSX, IBRS)" },
2162 { /* end of list */ }
2163 }
2164 },
2165 { /* end of list */ }
2166 }
2167 },
2168 {
2169 .name = "Skylake-Client",
2170 .level = 0xd,
2171 .vendor = CPUID_VENDOR_INTEL,
2172 .family = 6,
2173 .model = 94,
2174 .stepping = 3,
2175 .features[FEAT_1_EDX] =
2176 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2177 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2178 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2179 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2180 CPUID_DE | CPUID_FP87,
2181 .features[FEAT_1_ECX] =
2182 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2183 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2184 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2185 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2186 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2187 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2188 .features[FEAT_8000_0001_EDX] =
2189 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2190 CPUID_EXT2_SYSCALL,
2191 .features[FEAT_8000_0001_ECX] =
2192 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2193 .features[FEAT_7_0_EBX] =
2194 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2195 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2196 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2197 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2198 CPUID_7_0_EBX_SMAP,
2199 /* Missing: XSAVES (not supported by some Linux versions,
2200 * including v4.1 to v4.12).
2201 * KVM doesn't yet expose any XSAVES state save component,
2202 * and the only one defined in Skylake (processor tracing)
2203 * probably will block migration anyway.
2204 */
2205 .features[FEAT_XSAVE] =
2206 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2207 CPUID_XSAVE_XGETBV1,
2208 .features[FEAT_6_EAX] =
2209 CPUID_6_EAX_ARAT,
2210 .xlevel = 0x80000008,
2211 .model_id = "Intel Core Processor (Skylake)",
2212 .versions = (X86CPUVersionDefinition[]) {
2213 { .version = 1 },
2214 {
2215 .version = 2,
2216 .alias = "Skylake-Client-IBRS",
2217 .props = (PropValue[]) {
2218 { "spec-ctrl", "on" },
2219 { "model-id",
2220 "Intel Core Processor (Skylake, IBRS)" },
2221 { /* end of list */ }
2222 }
2223 },
2224 { /* end of list */ }
2225 }
2226 },
2227 {
2228 .name = "Skylake-Server",
2229 .level = 0xd,
2230 .vendor = CPUID_VENDOR_INTEL,
2231 .family = 6,
2232 .model = 85,
2233 .stepping = 4,
2234 .features[FEAT_1_EDX] =
2235 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2236 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2237 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2238 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2239 CPUID_DE | CPUID_FP87,
2240 .features[FEAT_1_ECX] =
2241 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2242 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2243 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2244 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2245 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2246 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2247 .features[FEAT_8000_0001_EDX] =
2248 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2249 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2250 .features[FEAT_8000_0001_ECX] =
2251 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2252 .features[FEAT_7_0_EBX] =
2253 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2254 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2255 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2256 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2257 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
2258 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2259 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2260 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
2261 .features[FEAT_7_0_ECX] =
2262 CPUID_7_0_ECX_PKU,
2263 /* Missing: XSAVES (not supported by some Linux versions,
2264 * including v4.1 to v4.12).
2265 * KVM doesn't yet expose any XSAVES state save component,
2266 * and the only one defined in Skylake (processor tracing)
2267 * probably will block migration anyway.
2268 */
2269 .features[FEAT_XSAVE] =
2270 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2271 CPUID_XSAVE_XGETBV1,
2272 .features[FEAT_6_EAX] =
2273 CPUID_6_EAX_ARAT,
2274 .xlevel = 0x80000008,
2275 .model_id = "Intel Xeon Processor (Skylake)",
2276 .versions = (X86CPUVersionDefinition[]) {
2277 { .version = 1 },
2278 {
2279 .version = 2,
2280 .alias = "Skylake-Server-IBRS",
2281 .props = (PropValue[]) {
2282 /* clflushopt was not added to Skylake-Server-IBRS */
2283 /* TODO: add -v3 including clflushopt */
2284 { "clflushopt", "off" },
2285 { "spec-ctrl", "on" },
2286 { "model-id",
2287 "Intel Xeon Processor (Skylake, IBRS)" },
2288 { /* end of list */ }
2289 }
2290 },
2291 { /* end of list */ }
2292 }
2293 },
2294 {
2295 .name = "Cascadelake-Server",
2296 .level = 0xd,
2297 .vendor = CPUID_VENDOR_INTEL,
2298 .family = 6,
2299 .model = 85,
2300 .stepping = 6,
2301 .features[FEAT_1_EDX] =
2302 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2303 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2304 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2305 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2306 CPUID_DE | CPUID_FP87,
2307 .features[FEAT_1_ECX] =
2308 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2309 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2310 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2311 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2312 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2313 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2314 .features[FEAT_8000_0001_EDX] =
2315 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2316 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2317 .features[FEAT_8000_0001_ECX] =
2318 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2319 .features[FEAT_7_0_EBX] =
2320 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2321 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2322 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2323 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2324 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
2325 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2326 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2327 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
2328 .features[FEAT_7_0_ECX] =
2329 CPUID_7_0_ECX_PKU |
2330 CPUID_7_0_ECX_AVX512VNNI,
2331 .features[FEAT_7_0_EDX] =
2332 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
2333 /* Missing: XSAVES (not supported by some Linux versions,
2334 * including v4.1 to v4.12).
2335 * KVM doesn't yet expose any XSAVES state save component,
2336 * and the only one defined in Skylake (processor tracing)
2337 * probably will block migration anyway.
2338 */
2339 .features[FEAT_XSAVE] =
2340 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2341 CPUID_XSAVE_XGETBV1,
2342 .features[FEAT_6_EAX] =
2343 CPUID_6_EAX_ARAT,
2344 .xlevel = 0x80000008,
2345 .model_id = "Intel Xeon Processor (Cascadelake)",
2346 },
2347 {
2348 .name = "Icelake-Client",
2349 .level = 0xd,
2350 .vendor = CPUID_VENDOR_INTEL,
2351 .family = 6,
2352 .model = 126,
2353 .stepping = 0,
2354 .features[FEAT_1_EDX] =
2355 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2356 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2357 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2358 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2359 CPUID_DE | CPUID_FP87,
2360 .features[FEAT_1_ECX] =
2361 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2362 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2363 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2364 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2365 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2366 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2367 .features[FEAT_8000_0001_EDX] =
2368 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2369 CPUID_EXT2_SYSCALL,
2370 .features[FEAT_8000_0001_ECX] =
2371 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2372 .features[FEAT_8000_0008_EBX] =
2373 CPUID_8000_0008_EBX_WBNOINVD,
2374 .features[FEAT_7_0_EBX] =
2375 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2376 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2377 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2378 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2379 CPUID_7_0_EBX_SMAP,
2380 .features[FEAT_7_0_ECX] =
2381 CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
2382 CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
2383 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
2384 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
2385 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
2386 .features[FEAT_7_0_EDX] =
2387 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
2388 /* Missing: XSAVES (not supported by some Linux versions,
2389 * including v4.1 to v4.12).
2390 * KVM doesn't yet expose any XSAVES state save component,
2391 * and the only one defined in Skylake (processor tracing)
2392 * probably will block migration anyway.
2393 */
2394 .features[FEAT_XSAVE] =
2395 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2396 CPUID_XSAVE_XGETBV1,
2397 .features[FEAT_6_EAX] =
2398 CPUID_6_EAX_ARAT,
2399 .xlevel = 0x80000008,
2400 .model_id = "Intel Core Processor (Icelake)",
2401 },
2402 {
2403 .name = "Icelake-Server",
2404 .level = 0xd,
2405 .vendor = CPUID_VENDOR_INTEL,
2406 .family = 6,
2407 .model = 134,
2408 .stepping = 0,
2409 .features[FEAT_1_EDX] =
2410 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2411 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2412 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2413 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2414 CPUID_DE | CPUID_FP87,
2415 .features[FEAT_1_ECX] =
2416 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2417 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2418 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2419 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2420 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2421 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2422 .features[FEAT_8000_0001_EDX] =
2423 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2424 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2425 .features[FEAT_8000_0001_ECX] =
2426 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2427 .features[FEAT_8000_0008_EBX] =
2428 CPUID_8000_0008_EBX_WBNOINVD,
2429 .features[FEAT_7_0_EBX] =
2430 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2431 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2432 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2433 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2434 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
2435 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2436 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2437 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
2438 .features[FEAT_7_0_ECX] =
2439 CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
2440 CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
2441 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
2442 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
2443 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,
2444 .features[FEAT_7_0_EDX] =
2445 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
2446 /* Missing: XSAVES (not supported by some Linux versions,
2447 * including v4.1 to v4.12).
2448 * KVM doesn't yet expose any XSAVES state save component,
2449 * and the only one defined in Skylake (processor tracing)
2450 * probably will block migration anyway.
2451 */
2452 .features[FEAT_XSAVE] =
2453 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2454 CPUID_XSAVE_XGETBV1,
2455 .features[FEAT_6_EAX] =
2456 CPUID_6_EAX_ARAT,
2457 .xlevel = 0x80000008,
2458 .model_id = "Intel Xeon Processor (Icelake)",
2459 },
2460 {
2461 .name = "SnowRidge-Server",
2462 .level = 27,
2463 .vendor = CPUID_VENDOR_INTEL,
2464 .family = 6,
2465 .model = 134,
2466 .stepping = 1,
2467 .features[FEAT_1_EDX] =
2468 /* missing: CPUID_PN CPUID_IA64 */
2469 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
2470 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE |
2471 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE |
2472 CPUID_CX8 | CPUID_APIC | CPUID_SEP |
2473 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
2474 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH |
2475 CPUID_MMX |
2476 CPUID_FXSR | CPUID_SSE | CPUID_SSE2,
2477 .features[FEAT_1_ECX] =
2478 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
2479 CPUID_EXT_VMX |
2480 CPUID_EXT_SSSE3 |
2481 CPUID_EXT_CX16 |
2482 CPUID_EXT_SSE41 |
2483 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
2484 CPUID_EXT_POPCNT |
2485 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE |
2486 CPUID_EXT_RDRAND,
2487 .features[FEAT_8000_0001_EDX] =
2488 CPUID_EXT2_SYSCALL |
2489 CPUID_EXT2_NX |
2490 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2491 CPUID_EXT2_LM,
2492 .features[FEAT_8000_0001_ECX] =
2493 CPUID_EXT3_LAHF_LM |
2494 CPUID_EXT3_3DNOWPREFETCH,
2495 .features[FEAT_7_0_EBX] =
2496 CPUID_7_0_EBX_FSGSBASE |
2497 CPUID_7_0_EBX_SMEP |
2498 CPUID_7_0_EBX_ERMS |
2499 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */
2500 CPUID_7_0_EBX_RDSEED |
2501 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
2502 CPUID_7_0_EBX_CLWB |
2503 CPUID_7_0_EBX_SHA_NI,
2504 .features[FEAT_7_0_ECX] =
2505 CPUID_7_0_ECX_UMIP |
2506 /* missing bit 5 */
2507 CPUID_7_0_ECX_GFNI |
2508 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE |
2509 CPUID_7_0_ECX_MOVDIR64B,
2510 .features[FEAT_7_0_EDX] =
2511 CPUID_7_0_EDX_SPEC_CTRL |
2512 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD |
2513 CPUID_7_0_EDX_CORE_CAPABILITY,
2514 .features[FEAT_CORE_CAPABILITY] =
2515 MSR_CORE_CAP_SPLIT_LOCK_DETECT,
2516 /*
2517 * Missing: XSAVES (not supported by some Linux versions,
2518 * including v4.1 to v4.12).
2519 * KVM doesn't yet expose any XSAVES state save component,
2520 * and the only one defined in Skylake (processor tracing)
2521 * probably will block migration anyway.
2522 */
2523 .features[FEAT_XSAVE] =
2524 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2525 CPUID_XSAVE_XGETBV1,
2526 .features[FEAT_6_EAX] =
2527 CPUID_6_EAX_ARAT,
2528 .xlevel = 0x80000008,
2529 .model_id = "Intel Atom Processor (SnowRidge)",
2530 },
2531 {
2532 .name = "KnightsMill",
2533 .level = 0xd,
2534 .vendor = CPUID_VENDOR_INTEL,
2535 .family = 6,
2536 .model = 133,
2537 .stepping = 0,
2538 .features[FEAT_1_EDX] =
2539 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR |
2540 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
2541 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
2542 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
2543 CPUID_PSE | CPUID_DE | CPUID_FP87,
2544 .features[FEAT_1_ECX] =
2545 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2546 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2547 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2548 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2549 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2550 CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2551 .features[FEAT_8000_0001_EDX] =
2552 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2553 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2554 .features[FEAT_8000_0001_ECX] =
2555 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2556 .features[FEAT_7_0_EBX] =
2557 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2558 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
2559 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F |
2560 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF |
2561 CPUID_7_0_EBX_AVX512ER,
2562 .features[FEAT_7_0_ECX] =
2563 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
2564 .features[FEAT_7_0_EDX] =
2565 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS,
2566 .features[FEAT_XSAVE] =
2567 CPUID_XSAVE_XSAVEOPT,
2568 .features[FEAT_6_EAX] =
2569 CPUID_6_EAX_ARAT,
2570 .xlevel = 0x80000008,
2571 .model_id = "Intel Xeon Phi Processor (Knights Mill)",
2572 },
2573 {
2574 .name = "Opteron_G1",
2575 .level = 5,
2576 .vendor = CPUID_VENDOR_AMD,
2577 .family = 15,
2578 .model = 6,
2579 .stepping = 1,
2580 .features[FEAT_1_EDX] =
2581 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2582 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2583 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2584 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2585 CPUID_DE | CPUID_FP87,
2586 .features[FEAT_1_ECX] =
2587 CPUID_EXT_SSE3,
2588 .features[FEAT_8000_0001_EDX] =
2589 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2590 .xlevel = 0x80000008,
2591 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
2592 },
2593 {
2594 .name = "Opteron_G2",
2595 .level = 5,
2596 .vendor = CPUID_VENDOR_AMD,
2597 .family = 15,
2598 .model = 6,
2599 .stepping = 1,
2600 .features[FEAT_1_EDX] =
2601 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2602 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2603 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2604 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2605 CPUID_DE | CPUID_FP87,
2606 .features[FEAT_1_ECX] =
2607 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
2608 .features[FEAT_8000_0001_EDX] =
2609 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2610 .features[FEAT_8000_0001_ECX] =
2611 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
2612 .xlevel = 0x80000008,
2613 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
2614 },
2615 {
2616 .name = "Opteron_G3",
2617 .level = 5,
2618 .vendor = CPUID_VENDOR_AMD,
2619 .family = 16,
2620 .model = 2,
2621 .stepping = 3,
2622 .features[FEAT_1_EDX] =
2623 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2624 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2625 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2626 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2627 CPUID_DE | CPUID_FP87,
2628 .features[FEAT_1_ECX] =
2629 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
2630 CPUID_EXT_SSE3,
2631 .features[FEAT_8000_0001_EDX] =
2632 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL |
2633 CPUID_EXT2_RDTSCP,
2634 .features[FEAT_8000_0001_ECX] =
2635 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
2636 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
2637 .xlevel = 0x80000008,
2638 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
2639 },
2640 {
2641 .name = "Opteron_G4",
2642 .level = 0xd,
2643 .vendor = CPUID_VENDOR_AMD,
2644 .family = 21,
2645 .model = 1,
2646 .stepping = 2,
2647 .features[FEAT_1_EDX] =
2648 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2649 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2650 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2651 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2652 CPUID_DE | CPUID_FP87,
2653 .features[FEAT_1_ECX] =
2654 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2655 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2656 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2657 CPUID_EXT_SSE3,
2658 .features[FEAT_8000_0001_EDX] =
2659 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
2660 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
2661 .features[FEAT_8000_0001_ECX] =
2662 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
2663 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
2664 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
2665 CPUID_EXT3_LAHF_LM,
2666 .features[FEAT_SVM] =
2667 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
2668 /* no xsaveopt! */
2669 .xlevel = 0x8000001A,
2670 .model_id = "AMD Opteron 62xx class CPU",
2671 },
2672 {
2673 .name = "Opteron_G5",
2674 .level = 0xd,
2675 .vendor = CPUID_VENDOR_AMD,
2676 .family = 21,
2677 .model = 2,
2678 .stepping = 0,
2679 .features[FEAT_1_EDX] =
2680 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2681 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2682 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2683 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2684 CPUID_DE | CPUID_FP87,
2685 .features[FEAT_1_ECX] =
2686 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
2687 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
2688 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
2689 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2690 .features[FEAT_8000_0001_EDX] =
2691 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
2692 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
2693 .features[FEAT_8000_0001_ECX] =
2694 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
2695 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
2696 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
2697 CPUID_EXT3_LAHF_LM,
2698 .features[FEAT_SVM] =
2699 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
2700 /* no xsaveopt! */
2701 .xlevel = 0x8000001A,
2702 .model_id = "AMD Opteron 63xx class CPU",
2703 },
2704 {
2705 .name = "EPYC",
2706 .level = 0xd,
2707 .vendor = CPUID_VENDOR_AMD,
2708 .family = 23,
2709 .model = 1,
2710 .stepping = 2,
2711 .features[FEAT_1_EDX] =
2712 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2713 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2714 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2715 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2716 CPUID_VME | CPUID_FP87,
2717 .features[FEAT_1_ECX] =
2718 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2719 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
2720 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2721 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2722 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2723 .features[FEAT_8000_0001_EDX] =
2724 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2725 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2726 CPUID_EXT2_SYSCALL,
2727 .features[FEAT_8000_0001_ECX] =
2728 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2729 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
2730 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
2731 CPUID_EXT3_TOPOEXT,
2732 .features[FEAT_7_0_EBX] =
2733 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2734 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2735 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
2736 CPUID_7_0_EBX_SHA_NI,
2737 /* Missing: XSAVES (not supported by some Linux versions,
2738 * including v4.1 to v4.12).
2739 * KVM doesn't yet expose any XSAVES state save component.
2740 */
2741 .features[FEAT_XSAVE] =
2742 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2743 CPUID_XSAVE_XGETBV1,
2744 .features[FEAT_6_EAX] =
2745 CPUID_6_EAX_ARAT,
2746 .features[FEAT_SVM] =
2747 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
2748 .xlevel = 0x8000001E,
2749 .model_id = "AMD EPYC Processor",
2750 .cache_info = &epyc_cache_info,
2751 .versions = (X86CPUVersionDefinition[]) {
2752 { .version = 1 },
2753 {
2754 .version = 2,
2755 .alias = "EPYC-IBPB",
2756 .props = (PropValue[]) {
2757 { "ibpb", "on" },
2758 { "model-id",
2759 "AMD EPYC Processor (with IBPB)" },
2760 { /* end of list */ }
2761 }
2762 },
2763 { /* end of list */ }
2764 }
2765 },
2766 {
2767 .name = "Dhyana",
2768 .level = 0xd,
2769 .vendor = CPUID_VENDOR_HYGON,
2770 .family = 24,
2771 .model = 0,
2772 .stepping = 1,
2773 .features[FEAT_1_EDX] =
2774 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2775 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2776 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2777 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2778 CPUID_VME | CPUID_FP87,
2779 .features[FEAT_1_ECX] =
2780 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2781 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT |
2782 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2783 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2784 CPUID_EXT_MONITOR | CPUID_EXT_SSE3,
2785 .features[FEAT_8000_0001_EDX] =
2786 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2787 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2788 CPUID_EXT2_SYSCALL,
2789 .features[FEAT_8000_0001_ECX] =
2790 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2791 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
2792 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
2793 CPUID_EXT3_TOPOEXT,
2794 .features[FEAT_8000_0008_EBX] =
2795 CPUID_8000_0008_EBX_IBPB,
2796 .features[FEAT_7_0_EBX] =
2797 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2798 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2799 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT,
2800 /*
2801 * Missing: XSAVES (not supported by some Linux versions,
2802 * including v4.1 to v4.12).
2803 * KVM doesn't yet expose any XSAVES state save component.
2804 */
2805 .features[FEAT_XSAVE] =
2806 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2807 CPUID_XSAVE_XGETBV1,
2808 .features[FEAT_6_EAX] =
2809 CPUID_6_EAX_ARAT,
2810 .features[FEAT_SVM] =
2811 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
2812 .xlevel = 0x8000001E,
2813 .model_id = "Hygon Dhyana Processor",
2814 .cache_info = &epyc_cache_info,
2815 },
2816 };
2817
2818 /* KVM-specific features that are automatically added/removed
2819 * from all CPU models when KVM is enabled.
2820 */
2821 static PropValue kvm_default_props[] = {
2822 { "kvmclock", "on" },
2823 { "kvm-nopiodelay", "on" },
2824 { "kvm-asyncpf", "on" },
2825 { "kvm-steal-time", "on" },
2826 { "kvm-pv-eoi", "on" },
2827 { "kvmclock-stable-bit", "on" },
2828 { "x2apic", "on" },
2829 { "acpi", "off" },
2830 { "monitor", "off" },
2831 { "svm", "off" },
2832 { NULL, NULL },
2833 };
2834
2835 /* TCG-specific defaults that override all CPU models when using TCG
2836 */
2837 static PropValue tcg_default_props[] = {
2838 { "vme", "off" },
2839 { NULL, NULL },
2840 };
2841
2842
2843 X86CPUVersion default_cpu_version = CPU_VERSION_LATEST;
2844
2845 void x86_cpu_set_default_version(X86CPUVersion version)
2846 {
2847 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */
2848 assert(version != CPU_VERSION_AUTO);
2849 default_cpu_version = version;
2850 }
2851
2852 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model)
2853 {
2854 int v = 0;
2855 const X86CPUVersionDefinition *vdef =
2856 x86_cpu_def_get_versions(model->cpudef);
2857 while (vdef->version) {
2858 v = vdef->version;
2859 vdef++;
2860 }
2861 return v;
2862 }
2863
2864 /* Return the actual version being used for a specific CPU model */
2865 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model)
2866 {
2867 X86CPUVersion v = model->version;
2868 if (v == CPU_VERSION_AUTO) {
2869 v = default_cpu_version;
2870 }
2871 if (v == CPU_VERSION_LATEST) {
2872 return x86_cpu_model_last_version(model);
2873 }
2874 return v;
2875 }
2876
2877 void x86_cpu_change_kvm_default(const char *prop, const char *value)
2878 {
2879 PropValue *pv;
2880 for (pv = kvm_default_props; pv->prop; pv++) {
2881 if (!strcmp(pv->prop, prop)) {
2882 pv->value = value;
2883 break;
2884 }
2885 }
2886
2887 /* It is valid to call this function only for properties that
2888 * are already present in the kvm_default_props table.
2889 */
2890 assert(pv->prop);
2891 }
2892
2893 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2894 bool migratable_only);
2895
2896 static bool lmce_supported(void)
2897 {
2898 uint64_t mce_cap = 0;
2899
2900 #ifdef CONFIG_KVM
2901 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
2902 return false;
2903 }
2904 #endif
2905
2906 return !!(mce_cap & MCG_LMCE_P);
2907 }
2908
2909 #define CPUID_MODEL_ID_SZ 48
2910
2911 /**
2912 * cpu_x86_fill_model_id:
2913 * Get CPUID model ID string from host CPU.
2914 *
2915 * @str should have at least CPUID_MODEL_ID_SZ bytes
2916 *
2917 * The function does NOT add a null terminator to the string
2918 * automatically.
2919 */
2920 static int cpu_x86_fill_model_id(char *str)
2921 {
2922 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
2923 int i;
2924
2925 for (i = 0; i < 3; i++) {
2926 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
2927 memcpy(str + i * 16 + 0, &eax, 4);
2928 memcpy(str + i * 16 + 4, &ebx, 4);
2929 memcpy(str + i * 16 + 8, &ecx, 4);
2930 memcpy(str + i * 16 + 12, &edx, 4);
2931 }
2932 return 0;
2933 }
2934
2935 static Property max_x86_cpu_properties[] = {
2936 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
2937 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
2938 DEFINE_PROP_END_OF_LIST()
2939 };
2940
2941 static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
2942 {
2943 DeviceClass *dc = DEVICE_CLASS(oc);
2944 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2945
2946 xcc->ordering = 9;
2947
2948 xcc->model_description =
2949 "Enables all features supported by the accelerator in the current host";
2950
2951 dc->props = max_x86_cpu_properties;
2952 }
2953
2954 static void max_x86_cpu_initfn(Object *obj)
2955 {
2956 X86CPU *cpu = X86_CPU(obj);
2957 CPUX86State *env = &cpu->env;
2958 KVMState *s = kvm_state;
2959
2960 /* We can't fill the features array here because we don't know yet if
2961 * "migratable" is true or false.
2962 */
2963 cpu->max_features = true;
2964
2965 if (accel_uses_host_cpuid()) {
2966 char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
2967 char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
2968 int family, model, stepping;
2969
2970 host_vendor_fms(vendor, &family, &model, &stepping);
2971 cpu_x86_fill_model_id(model_id);
2972
2973 object_property_set_str(OBJECT(cpu), vendor, "vendor", &error_abort);
2974 object_property_set_int(OBJECT(cpu), family, "family", &error_abort);
2975 object_property_set_int(OBJECT(cpu), model, "model", &error_abort);
2976 object_property_set_int(OBJECT(cpu), stepping, "stepping",
2977 &error_abort);
2978 object_property_set_str(OBJECT(cpu), model_id, "model-id",
2979 &error_abort);
2980
2981 if (kvm_enabled()) {
2982 env->cpuid_min_level =
2983 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
2984 env->cpuid_min_xlevel =
2985 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
2986 env->cpuid_min_xlevel2 =
2987 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
2988 } else {
2989 env->cpuid_min_level =
2990 hvf_get_supported_cpuid(0x0, 0, R_EAX);
2991 env->cpuid_min_xlevel =
2992 hvf_get_supported_cpuid(0x80000000, 0, R_EAX);
2993 env->cpuid_min_xlevel2 =
2994 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX);
2995 }
2996
2997 if (lmce_supported()) {
2998 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
2999 }
3000 } else {
3001 object_property_set_str(OBJECT(cpu), CPUID_VENDOR_AMD,
3002 "vendor", &error_abort);
3003 object_property_set_int(OBJECT(cpu), 6, "family", &error_abort);
3004 object_property_set_int(OBJECT(cpu), 6, "model", &error_abort);
3005 object_property_set_int(OBJECT(cpu), 3, "stepping", &error_abort);
3006 object_property_set_str(OBJECT(cpu),
3007 "QEMU TCG CPU version " QEMU_HW_VERSION,
3008 "model-id", &error_abort);
3009 }
3010
3011 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
3012 }
3013
3014 static const TypeInfo max_x86_cpu_type_info = {
3015 .name = X86_CPU_TYPE_NAME("max"),
3016 .parent = TYPE_X86_CPU,
3017 .instance_init = max_x86_cpu_initfn,
3018 .class_init = max_x86_cpu_class_init,
3019 };
3020
3021 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
3022 static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
3023 {
3024 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3025
3026 xcc->host_cpuid_required = true;
3027 xcc->ordering = 8;
3028
3029 #if defined(CONFIG_KVM)
3030 xcc->model_description =
3031 "KVM processor with all supported host features ";
3032 #elif defined(CONFIG_HVF)
3033 xcc->model_description =
3034 "HVF processor with all supported host features ";
3035 #endif
3036 }
3037
3038 static const TypeInfo host_x86_cpu_type_info = {
3039 .name = X86_CPU_TYPE_NAME("host"),
3040 .parent = X86_CPU_TYPE_NAME("max"),
3041 .class_init = host_x86_cpu_class_init,
3042 };
3043
3044 #endif
3045
3046 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
3047 {
3048 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
3049
3050 switch (f->type) {
3051 case CPUID_FEATURE_WORD:
3052 {
3053 const char *reg = get_register_name_32(f->cpuid.reg);
3054 assert(reg);
3055 return g_strdup_printf("CPUID.%02XH:%s",
3056 f->cpuid.eax, reg);
3057 }
3058 case MSR_FEATURE_WORD:
3059 return g_strdup_printf("MSR(%02XH)",
3060 f->msr.index);
3061 }
3062
3063 return NULL;
3064 }
3065
3066 static void report_unavailable_features(FeatureWord w, uint32_t mask)
3067 {
3068 FeatureWordInfo *f = &feature_word_info[w];
3069 int i;
3070 char *feat_word_str;
3071
3072 for (i = 0; i < 32; ++i) {
3073 if ((1UL << i) & mask) {
3074 feat_word_str = feature_word_description(f, i);
3075 warn_report("%s doesn't support requested feature: %s%s%s [bit %d]",
3076 accel_uses_host_cpuid() ? "host" : "TCG",
3077 feat_word_str,
3078 f->feat_names[i] ? "." : "",
3079 f->feat_names[i] ? f->feat_names[i] : "", i);
3080 g_free(feat_word_str);
3081 }
3082 }
3083 }
3084
3085 static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
3086 const char *name, void *opaque,
3087 Error **errp)
3088 {
3089 X86CPU *cpu = X86_CPU(obj);
3090 CPUX86State *env = &cpu->env;
3091 int64_t value;
3092
3093 value = (env->cpuid_version >> 8) & 0xf;
3094 if (value == 0xf) {
3095 value += (env->cpuid_version >> 20) & 0xff;
3096 }
3097 visit_type_int(v, name, &value, errp);
3098 }
3099
3100 static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
3101 const char *name, void *opaque,
3102 Error **errp)
3103 {
3104 X86CPU *cpu = X86_CPU(obj);
3105 CPUX86State *env = &cpu->env;
3106 const int64_t min = 0;
3107 const int64_t max = 0xff + 0xf;
3108 Error *local_err = NULL;
3109 int64_t value;
3110
3111 visit_type_int(v, name, &value, &local_err);
3112 if (local_err) {
3113 error_propagate(errp, local_err);
3114 return;
3115 }
3116 if (value < min || value > max) {
3117 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3118 name ? name : "null", value, min, max);
3119 return;
3120 }
3121
3122 env->cpuid_version &= ~0xff00f00;
3123 if (value > 0x0f) {
3124 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
3125 } else {
3126 env->cpuid_version |= value << 8;
3127 }
3128 }
3129
3130 static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
3131 const char *name, void *opaque,
3132 Error **errp)
3133 {
3134 X86CPU *cpu = X86_CPU(obj);
3135 CPUX86State *env = &cpu->env;
3136 int64_t value;
3137
3138 value = (env->cpuid_version >> 4) & 0xf;
3139 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
3140 visit_type_int(v, name, &value, errp);
3141 }
3142
3143 static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
3144 const char *name, void *opaque,
3145 Error **errp)
3146 {
3147 X86CPU *cpu = X86_CPU(obj);
3148 CPUX86State *env = &cpu->env;
3149 const int64_t min = 0;
3150 const int64_t max = 0xff;
3151 Error *local_err = NULL;
3152 int64_t value;
3153
3154 visit_type_int(v, name, &value, &local_err);
3155 if (local_err) {
3156 error_propagate(errp, local_err);
3157 return;
3158 }
3159 if (value < min || value > max) {
3160 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3161 name ? name : "null", value, min, max);
3162 return;
3163 }
3164
3165 env->cpuid_version &= ~0xf00f0;
3166 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
3167 }
3168
3169 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
3170 const char *name, void *opaque,
3171 Error **errp)
3172 {
3173 X86CPU *cpu = X86_CPU(obj);
3174 CPUX86State *env = &cpu->env;
3175 int64_t value;
3176
3177 value = env->cpuid_version & 0xf;
3178 visit_type_int(v, name, &value, errp);
3179 }
3180
3181 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
3182 const char *name, void *opaque,
3183 Error **errp)
3184 {
3185 X86CPU *cpu = X86_CPU(obj);
3186 CPUX86State *env = &cpu->env;
3187 const int64_t min = 0;
3188 const int64_t max = 0xf;
3189 Error *local_err = NULL;
3190 int64_t value;
3191
3192 visit_type_int(v, name, &value, &local_err);
3193 if (local_err) {
3194 error_propagate(errp, local_err);
3195 return;
3196 }
3197 if (value < min || value > max) {
3198 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3199 name ? name : "null", value, min, max);
3200 return;
3201 }
3202
3203 env->cpuid_version &= ~0xf;
3204 env->cpuid_version |= value & 0xf;
3205 }
3206
3207 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
3208 {
3209 X86CPU *cpu = X86_CPU(obj);
3210 CPUX86State *env = &cpu->env;
3211 char *value;
3212
3213 value = g_malloc(CPUID_VENDOR_SZ + 1);
3214 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
3215 env->cpuid_vendor3);
3216 return value;
3217 }
3218
3219 static void x86_cpuid_set_vendor(Object *obj, const char *value,
3220 Error **errp)
3221 {
3222 X86CPU *cpu = X86_CPU(obj);
3223 CPUX86State *env = &cpu->env;
3224 int i;
3225
3226 if (strlen(value) != CPUID_VENDOR_SZ) {
3227 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
3228 return;
3229 }
3230
3231 env->cpuid_vendor1 = 0;
3232 env->cpuid_vendor2 = 0;
3233 env->cpuid_vendor3 = 0;
3234 for (i = 0; i < 4; i++) {
3235 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
3236 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
3237 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
3238 }
3239 }
3240
3241 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
3242 {
3243 X86CPU *cpu = X86_CPU(obj);
3244 CPUX86State *env = &cpu->env;
3245 char *value;
3246 int i;
3247
3248 value = g_malloc(48 + 1);
3249 for (i = 0; i < 48; i++) {
3250 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
3251 }
3252 value[48] = '\0';
3253 return value;
3254 }
3255
3256 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
3257 Error **errp)
3258 {
3259 X86CPU *cpu = X86_CPU(obj);
3260 CPUX86State *env = &cpu->env;
3261 int c, len, i;
3262
3263 if (model_id == NULL) {
3264 model_id = "";
3265 }
3266 len = strlen(model_id);
3267 memset(env->cpuid_model, 0, 48);
3268 for (i = 0; i < 48; i++) {
3269 if (i >= len) {
3270 c = '\0';
3271 } else {
3272 c = (uint8_t)model_id[i];
3273 }
3274 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
3275 }
3276 }
3277
3278 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
3279 void *opaque, Error **errp)
3280 {
3281 X86CPU *cpu = X86_CPU(obj);
3282 int64_t value;
3283
3284 value = cpu->env.tsc_khz * 1000;
3285 visit_type_int(v, name, &value, errp);
3286 }
3287
3288 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
3289 void *opaque, Error **errp)
3290 {
3291 X86CPU *cpu = X86_CPU(obj);
3292 const int64_t min = 0;
3293 const int64_t max = INT64_MAX;
3294 Error *local_err = NULL;
3295 int64_t value;
3296
3297 visit_type_int(v, name, &value, &local_err);
3298 if (local_err) {
3299 error_propagate(errp, local_err);
3300 return;
3301 }
3302 if (value < min || value > max) {
3303 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3304 name ? name : "null", value, min, max);
3305 return;
3306 }
3307
3308 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
3309 }
3310
3311 /* Generic getter for "feature-words" and "filtered-features" properties */
3312 static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
3313 const char *name, void *opaque,
3314 Error **errp)
3315 {
3316 uint32_t *array = (uint32_t *)opaque;
3317 FeatureWord w;
3318 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
3319 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
3320 X86CPUFeatureWordInfoList *list = NULL;
3321
3322 for (w = 0; w < FEATURE_WORDS; w++) {
3323 FeatureWordInfo *wi = &feature_word_info[w];
3324 /*
3325 * We didn't have MSR features when "feature-words" was
3326 * introduced. Therefore skipped other type entries.
3327 */
3328 if (wi->type != CPUID_FEATURE_WORD) {
3329 continue;
3330 }
3331 X86CPUFeatureWordInfo *qwi = &word_infos[w];
3332 qwi->cpuid_input_eax = wi->cpuid.eax;
3333 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx;
3334 qwi->cpuid_input_ecx = wi->cpuid.ecx;
3335 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum;
3336 qwi->features = array[w];
3337
3338 /* List will be in reverse order, but order shouldn't matter */
3339 list_entries[w].next = list;
3340 list_entries[w].value = &word_infos[w];
3341 list = &list_entries[w];
3342 }
3343
3344 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
3345 }
3346
3347 /* Convert all '_' in a feature string option name to '-', to make feature
3348 * name conform to QOM property naming rule, which uses '-' instead of '_'.
3349 */
3350 static inline void feat2prop(char *s)
3351 {
3352 while ((s = strchr(s, '_'))) {
3353 *s = '-';
3354 }
3355 }
3356
3357 /* Return the feature property name for a feature flag bit */
3358 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
3359 {
3360 /* XSAVE components are automatically enabled by other features,
3361 * so return the original feature name instead
3362 */
3363 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
3364 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
3365
3366 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
3367 x86_ext_save_areas[comp].bits) {
3368 w = x86_ext_save_areas[comp].feature;
3369 bitnr = ctz32(x86_ext_save_areas[comp].bits);
3370 }
3371 }
3372
3373 assert(bitnr < 32);
3374 assert(w < FEATURE_WORDS);
3375 return feature_word_info[w].feat_names[bitnr];
3376 }
3377
3378 /* Compatibily hack to maintain legacy +-feat semantic,
3379 * where +-feat overwrites any feature set by
3380 * feat=on|feat even if the later is parsed after +-feat
3381 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
3382 */
3383 static GList *plus_features, *minus_features;
3384
3385 static gint compare_string(gconstpointer a, gconstpointer b)
3386 {
3387 return g_strcmp0(a, b);
3388 }
3389
3390 /* Parse "+feature,-feature,feature=foo" CPU feature string
3391 */
3392 static void x86_cpu_parse_featurestr(const char *typename, char *features,
3393 Error **errp)
3394 {
3395 char *featurestr; /* Single 'key=value" string being parsed */
3396 static bool cpu_globals_initialized;
3397 bool ambiguous = false;
3398
3399 if (cpu_globals_initialized) {
3400 return;
3401 }
3402 cpu_globals_initialized = true;
3403
3404 if (!features) {
3405 return;
3406 }
3407
3408 for (featurestr = strtok(features, ",");
3409 featurestr;
3410 featurestr = strtok(NULL, ",")) {
3411 const char *name;
3412 const char *val = NULL;
3413 char *eq = NULL;
3414 char num[32];
3415 GlobalProperty *prop;
3416
3417 /* Compatibility syntax: */
3418 if (featurestr[0] == '+') {
3419 plus_features = g_list_append(plus_features,
3420 g_strdup(featurestr + 1));
3421 continue;
3422 } else if (featurestr[0] == '-') {
3423 minus_features = g_list_append(minus_features,
3424 g_strdup(featurestr + 1));
3425 continue;
3426 }
3427
3428 eq = strchr(featurestr, '=');
3429 if (eq) {
3430 *eq++ = 0;
3431 val = eq;
3432 } else {
3433 val = "on";
3434 }
3435
3436 feat2prop(featurestr);
3437 name = featurestr;
3438
3439 if (g_list_find_custom(plus_features, name, compare_string)) {
3440 warn_report("Ambiguous CPU model string. "
3441 "Don't mix both \"+%s\" and \"%s=%s\"",
3442 name, name, val);
3443 ambiguous = true;
3444 }
3445 if (g_list_find_custom(minus_features, name, compare_string)) {
3446 warn_report("Ambiguous CPU model string. "
3447 "Don't mix both \"-%s\" and \"%s=%s\"",
3448 name, name, val);
3449 ambiguous = true;
3450 }
3451
3452 /* Special case: */
3453 if (!strcmp(name, "tsc-freq")) {
3454 int ret;
3455 uint64_t tsc_freq;
3456
3457 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
3458 if (ret < 0 || tsc_freq > INT64_MAX) {
3459 error_setg(errp, "bad numerical value %s", val);
3460 return;
3461 }
3462 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
3463 val = num;
3464 name = "tsc-frequency";
3465 }
3466
3467 prop = g_new0(typeof(*prop), 1);
3468 prop->driver = typename;
3469 prop->property = g_strdup(name);
3470 prop->value = g_strdup(val);
3471 qdev_prop_register_global(prop);
3472 }
3473
3474 if (ambiguous) {
3475 warn_report("Compatibility of ambiguous CPU model "
3476 "strings won't be kept on future QEMU versions");
3477 }
3478 }
3479
3480 static void x86_cpu_expand_features(X86CPU *cpu, Error **errp);
3481 static int x86_cpu_filter_features(X86CPU *cpu);
3482
3483 /* Build a list with the name of all features on a feature word array */
3484 static void x86_cpu_list_feature_names(FeatureWordArray features,
3485 strList **feat_names)
3486 {
3487 FeatureWord w;
3488 strList **next = feat_names;
3489
3490 for (w = 0; w < FEATURE_WORDS; w++) {
3491 uint32_t filtered = features[w];
3492 int i;
3493 for (i = 0; i < 32; i++) {
3494 if (filtered & (1UL << i)) {
3495 strList *new = g_new0(strList, 1);
3496 new->value = g_strdup(x86_cpu_feature_name(w, i));
3497 *next = new;
3498 next = &new->next;
3499 }
3500 }
3501 }
3502 }
3503
3504 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v,
3505 const char *name, void *opaque,
3506 Error **errp)
3507 {
3508 X86CPU *xc = X86_CPU(obj);
3509 strList *result = NULL;
3510
3511 x86_cpu_list_feature_names(xc->filtered_features, &result);
3512 visit_type_strList(v, "unavailable-features", &result, errp);
3513 }
3514
3515 /* Check for missing features that may prevent the CPU class from
3516 * running using the current machine and accelerator.
3517 */
3518 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
3519 strList **missing_feats)
3520 {
3521 X86CPU *xc;
3522 Error *err = NULL;
3523 strList **next = missing_feats;
3524
3525 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
3526 strList *new = g_new0(strList, 1);
3527 new->value = g_strdup("kvm");
3528 *missing_feats = new;
3529 return;
3530 }
3531
3532 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
3533
3534 x86_cpu_expand_features(xc, &err);
3535 if (err) {
3536 /* Errors at x86_cpu_expand_features should never happen,
3537 * but in case it does, just report the model as not
3538 * runnable at all using the "type" property.
3539 */
3540 strList *new = g_new0(strList, 1);
3541 new->value = g_strdup("type");
3542 *next = new;
3543 next = &new->next;
3544 }
3545
3546 x86_cpu_filter_features(xc);
3547
3548 x86_cpu_list_feature_names(xc->filtered_features, next);
3549
3550 object_unref(OBJECT(xc));
3551 }
3552
3553 /* Print all cpuid feature names in featureset
3554 */
3555 static void listflags(GList *features)
3556 {
3557 size_t len = 0;
3558 GList *tmp;
3559
3560 for (tmp = features; tmp; tmp = tmp->next) {
3561 const char *name = tmp->data;
3562 if ((len + strlen(name) + 1) >= 75) {
3563 qemu_printf("\n");
3564 len = 0;
3565 }
3566 qemu_printf("%s%s", len == 0 ? " " : " ", name);
3567 len += strlen(name) + 1;
3568 }
3569 qemu_printf("\n");
3570 }
3571
3572 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
3573 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
3574 {
3575 ObjectClass *class_a = (ObjectClass *)a;
3576 ObjectClass *class_b = (ObjectClass *)b;
3577 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
3578 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
3579 char *name_a, *name_b;
3580 int ret;
3581
3582 if (cc_a->ordering != cc_b->ordering) {
3583 ret = cc_a->ordering - cc_b->ordering;
3584 } else {
3585 name_a = x86_cpu_class_get_model_name(cc_a);
3586 name_b = x86_cpu_class_get_model_name(cc_b);
3587 ret = strcmp(name_a, name_b);
3588 g_free(name_a);
3589 g_free(name_b);
3590 }
3591 return ret;
3592 }
3593
3594 static GSList *get_sorted_cpu_model_list(void)
3595 {
3596 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
3597 list = g_slist_sort(list, x86_cpu_list_compare);
3598 return list;
3599 }
3600
3601 static char *x86_cpu_class_get_model_id(X86CPUClass *xc)
3602 {
3603 Object *obj = object_new(object_class_get_name(OBJECT_CLASS(xc)));
3604 char *r = object_property_get_str(obj, "model-id", &error_abort);
3605 object_unref(obj);
3606 return r;
3607 }
3608
3609 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc)
3610 {
3611 X86CPUVersion version;
3612
3613 if (!cc->model || !cc->model->is_alias) {
3614 return NULL;
3615 }
3616 version = x86_cpu_model_resolve_version(cc->model);
3617 if (version <= 0) {
3618 return NULL;
3619 }
3620 return x86_cpu_versioned_model_name(cc->model->cpudef, version);
3621 }
3622
3623 static void x86_cpu_list_entry(gpointer data, gpointer user_data)
3624 {
3625 ObjectClass *oc = data;
3626 X86CPUClass *cc = X86_CPU_CLASS(oc);
3627 char *name = x86_cpu_class_get_model_name(cc);
3628 char *desc = g_strdup(cc->model_description);
3629 char *alias_of = x86_cpu_class_get_alias_of(cc);
3630
3631 if (!desc && alias_of) {
3632 if (cc->model && cc->model->version == CPU_VERSION_AUTO) {
3633 desc = g_strdup("(alias configured by machine type)");
3634 } else {
3635 desc = g_strdup_printf("(alias of %s)", alias_of);
3636 }
3637 }
3638 if (!desc) {
3639 desc = x86_cpu_class_get_model_id(cc);
3640 }
3641
3642 qemu_printf("x86 %-20s %-48s\n", name, desc);
3643 g_free(name);
3644 g_free(desc);
3645 g_free(alias_of);
3646 }
3647
3648 /* list available CPU models and flags */
3649 void x86_cpu_list(void)
3650 {
3651 int i, j;
3652 GSList *list;
3653 GList *names = NULL;
3654
3655 qemu_printf("Available CPUs:\n");
3656 list = get_sorted_cpu_model_list();
3657 g_slist_foreach(list, x86_cpu_list_entry, NULL);
3658 g_slist_free(list);
3659
3660 names = NULL;
3661 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
3662 FeatureWordInfo *fw = &feature_word_info[i];
3663 for (j = 0; j < 32; j++) {
3664 if (fw->feat_names[j]) {
3665 names = g_list_append(names, (gpointer)fw->feat_names[j]);
3666 }
3667 }
3668 }
3669
3670 names = g_list_sort(names, (GCompareFunc)strcmp);
3671
3672 qemu_printf("\nRecognized CPUID flags:\n");
3673 listflags(names);
3674 qemu_printf("\n");
3675 g_list_free(names);
3676 }
3677
3678 static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
3679 {
3680 ObjectClass *oc = data;
3681 X86CPUClass *cc = X86_CPU_CLASS(oc);
3682 CpuDefinitionInfoList **cpu_list = user_data;
3683 CpuDefinitionInfoList *entry;
3684 CpuDefinitionInfo *info;
3685
3686 info = g_malloc0(sizeof(*info));
3687 info->name = x86_cpu_class_get_model_name(cc);
3688 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
3689 info->has_unavailable_features = true;
3690 info->q_typename = g_strdup(object_class_get_name(oc));
3691 info->migration_safe = cc->migration_safe;
3692 info->has_migration_safe = true;
3693 info->q_static = cc->static_model;
3694 /*
3695 * Old machine types won't report aliases, so that alias translation
3696 * doesn't break compatibility with previous QEMU versions.
3697 */
3698 if (default_cpu_version != CPU_VERSION_LEGACY) {
3699 info->alias_of = x86_cpu_class_get_alias_of(cc);
3700 info->has_alias_of = !!info->alias_of;
3701 }
3702
3703 entry = g_malloc0(sizeof(*entry));
3704 entry->value = info;
3705 entry->next = *cpu_list;
3706 *cpu_list = entry;
3707 }
3708
3709 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
3710 {
3711 CpuDefinitionInfoList *cpu_list = NULL;
3712 GSList *list = get_sorted_cpu_model_list();
3713 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
3714 g_slist_free(list);
3715 return cpu_list;
3716 }
3717
3718 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
3719 bool migratable_only)
3720 {
3721 FeatureWordInfo *wi = &feature_word_info[w];
3722 uint32_t r = 0;
3723
3724 if (kvm_enabled()) {
3725 switch (wi->type) {
3726 case CPUID_FEATURE_WORD:
3727 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax,
3728 wi->cpuid.ecx,
3729 wi->cpuid.reg);
3730 break;
3731 case MSR_FEATURE_WORD:
3732 r = kvm_arch_get_supported_msr_feature(kvm_state,
3733 wi->msr.index);
3734 break;
3735 }
3736 } else if (hvf_enabled()) {
3737 if (wi->type != CPUID_FEATURE_WORD) {
3738 return 0;
3739 }
3740 r = hvf_get_supported_cpuid(wi->cpuid.eax,
3741 wi->cpuid.ecx,
3742 wi->cpuid.reg);
3743 } else if (tcg_enabled()) {
3744 r = wi->tcg_features;
3745 } else {
3746 return ~0;
3747 }
3748 if (migratable_only) {
3749 r &= x86_cpu_get_migratable_flags(w);
3750 }
3751 return r;
3752 }
3753
3754 static void x86_cpu_report_filtered_features(X86CPU *cpu)
3755 {
3756 FeatureWord w;
3757
3758 for (w = 0; w < FEATURE_WORDS; w++) {
3759 report_unavailable_features(w, cpu->filtered_features[w]);
3760 }
3761 }
3762
3763 static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
3764 {
3765 PropValue *pv;
3766 for (pv = props; pv->prop; pv++) {
3767 if (!pv->value) {
3768 continue;
3769 }
3770 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
3771 &error_abort);
3772 }
3773 }
3774
3775 /* Apply properties for the CPU model version specified in model */
3776 static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model)
3777 {
3778 const X86CPUVersionDefinition *vdef;
3779 X86CPUVersion version = x86_cpu_model_resolve_version(model);
3780
3781 if (version == CPU_VERSION_LEGACY) {
3782 return;
3783 }
3784
3785 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) {
3786 PropValue *p;
3787
3788 for (p = vdef->props; p && p->prop; p++) {
3789 object_property_parse(OBJECT(cpu), p->value, p->prop,
3790 &error_abort);
3791 }
3792
3793 if (vdef->version == version) {
3794 break;
3795 }
3796 }
3797
3798 /*
3799 * If we reached the end of the list, version number was invalid
3800 */
3801 assert(vdef->version == version);
3802 }
3803
3804 /* Load data from X86CPUDefinition into a X86CPU object
3805 */
3806 static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model, Error **errp)
3807 {
3808 X86CPUDefinition *def = model->cpudef;
3809 CPUX86State *env = &cpu->env;
3810 const char *vendor;
3811 char host_vendor[CPUID_VENDOR_SZ + 1];
3812 FeatureWord w;
3813
3814 /*NOTE: any property set by this function should be returned by
3815 * x86_cpu_static_props(), so static expansion of
3816 * query-cpu-model-expansion is always complete.
3817 */
3818
3819 /* CPU models only set _minimum_ values for level/xlevel: */
3820 object_property_set_uint(OBJECT(cpu), def->level, "min-level", errp);
3821 object_property_set_uint(OBJECT(cpu), def->xlevel, "min-xlevel", errp);
3822
3823 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
3824 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
3825 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
3826 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
3827 for (w = 0; w < FEATURE_WORDS; w++) {
3828 env->features[w] = def->features[w];
3829 }
3830
3831 /* legacy-cache defaults to 'off' if CPU model provides cache info */
3832 cpu->legacy_cache = !def->cache_info;
3833
3834 /* Special cases not set in the X86CPUDefinition structs: */
3835 /* TODO: in-kernel irqchip for hvf */
3836 if (kvm_enabled()) {
3837 if (!kvm_irqchip_in_kernel()) {
3838 x86_cpu_change_kvm_default("x2apic", "off");
3839 }
3840
3841 x86_cpu_apply_props(cpu, kvm_default_props);
3842 } else if (tcg_enabled()) {
3843 x86_cpu_apply_props(cpu, tcg_default_props);
3844 }
3845
3846 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
3847
3848 /* sysenter isn't supported in compatibility mode on AMD,
3849 * syscall isn't supported in compatibility mode on Intel.
3850 * Normally we advertise the actual CPU vendor, but you can
3851 * override this using the 'vendor' property if you want to use
3852 * KVM's sysenter/syscall emulation in compatibility mode and
3853 * when doing cross vendor migration
3854 */
3855 vendor = def->vendor;
3856 if (accel_uses_host_cpuid()) {
3857 uint32_t ebx = 0, ecx = 0, edx = 0;
3858 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
3859 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
3860 vendor = host_vendor;
3861 }
3862
3863 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
3864
3865 x86_cpu_apply_version_props(cpu, model);
3866 }
3867
3868 #ifndef CONFIG_USER_ONLY
3869 /* Return a QDict containing keys for all properties that can be included
3870 * in static expansion of CPU models. All properties set by x86_cpu_load_model()
3871 * must be included in the dictionary.
3872 */
3873 static QDict *x86_cpu_static_props(void)
3874 {
3875 FeatureWord w;
3876 int i;
3877 static const char *props[] = {
3878 "min-level",
3879 "min-xlevel",
3880 "family",
3881 "model",
3882 "stepping",
3883 "model-id",
3884 "vendor",
3885 "lmce",
3886 NULL,
3887 };
3888 static QDict *d;
3889
3890 if (d) {
3891 return d;
3892 }
3893
3894 d = qdict_new();
3895 for (i = 0; props[i]; i++) {
3896 qdict_put_null(d, props[i]);
3897 }
3898
3899 for (w = 0; w < FEATURE_WORDS; w++) {
3900 FeatureWordInfo *fi = &feature_word_info[w];
3901 int bit;
3902 for (bit = 0; bit < 32; bit++) {
3903 if (!fi->feat_names[bit]) {
3904 continue;
3905 }
3906 qdict_put_null(d, fi->feat_names[bit]);
3907 }
3908 }
3909
3910 return d;
3911 }
3912
3913 /* Add an entry to @props dict, with the value for property. */
3914 static void x86_cpu_expand_prop(X86CPU *cpu, QDict *props, const char *prop)
3915 {
3916 QObject *value = object_property_get_qobject(OBJECT(cpu), prop,
3917 &error_abort);
3918
3919 qdict_put_obj(props, prop, value);
3920 }
3921
3922 /* Convert CPU model data from X86CPU object to a property dictionary
3923 * that can recreate exactly the same CPU model.
3924 */
3925 static void x86_cpu_to_dict(X86CPU *cpu, QDict *props)
3926 {
3927 QDict *sprops = x86_cpu_static_props();
3928 const QDictEntry *e;
3929
3930 for (e = qdict_first(sprops); e; e = qdict_next(sprops, e)) {
3931 const char *prop = qdict_entry_key(e);
3932 x86_cpu_expand_prop(cpu, props, prop);
3933 }
3934 }
3935
3936 /* Convert CPU model data from X86CPU object to a property dictionary
3937 * that can recreate exactly the same CPU model, including every
3938 * writeable QOM property.
3939 */
3940 static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props)
3941 {
3942 ObjectPropertyIterator iter;
3943 ObjectProperty *prop;
3944
3945 object_property_iter_init(&iter, OBJECT(cpu));
3946 while ((prop = object_property_iter_next(&iter))) {
3947 /* skip read-only or write-only properties */
3948 if (!prop->get || !prop->set) {
3949 continue;
3950 }
3951
3952 /* "hotplugged" is the only property that is configurable
3953 * on the command-line but will be set differently on CPUs
3954 * created using "-cpu ... -smp ..." and by CPUs created
3955 * on the fly by x86_cpu_from_model() for querying. Skip it.
3956 */
3957 if (!strcmp(prop->name, "hotplugged")) {
3958 continue;
3959 }
3960 x86_cpu_expand_prop(cpu, props, prop->name);
3961 }
3962 }
3963
3964 static void object_apply_props(Object *obj, QDict *props, Error **errp)
3965 {
3966 const QDictEntry *prop;
3967 Error *err = NULL;
3968
3969 for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) {
3970 object_property_set_qobject(obj, qdict_entry_value(prop),
3971 qdict_entry_key(prop), &err);
3972 if (err) {
3973 break;
3974 }
3975 }
3976
3977 error_propagate(errp, err);
3978 }
3979
3980 /* Create X86CPU object according to model+props specification */
3981 static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp)
3982 {
3983 X86CPU *xc = NULL;
3984 X86CPUClass *xcc;
3985 Error *err = NULL;
3986
3987 xcc = X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU, model));
3988 if (xcc == NULL) {
3989 error_setg(&err, "CPU model '%s' not found", model);
3990 goto out;
3991 }
3992
3993 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
3994 if (props) {
3995 object_apply_props(OBJECT(xc), props, &err);
3996 if (err) {
3997 goto out;
3998 }
3999 }
4000
4001 x86_cpu_expand_features(xc, &err);
4002 if (err) {
4003 goto out;
4004 }
4005
4006 out:
4007 if (err) {
4008 error_propagate(errp, err);
4009 object_unref(OBJECT(xc));
4010 xc = NULL;
4011 }
4012 return xc;
4013 }
4014
4015 CpuModelExpansionInfo *
4016 qmp_query_cpu_model_expansion(CpuModelExpansionType type,
4017 CpuModelInfo *model,
4018 Error **errp)
4019 {
4020 X86CPU *xc = NULL;
4021 Error *err = NULL;
4022 CpuModelExpansionInfo *ret = g_new0(CpuModelExpansionInfo, 1);
4023 QDict *props = NULL;
4024 const char *base_name;
4025
4026 xc = x86_cpu_from_model(model->name,
4027 model->has_props ?
4028 qobject_to(QDict, model->props) :
4029 NULL, &err);
4030 if (err) {
4031 goto out;
4032 }
4033
4034 props = qdict_new();
4035 ret->model = g_new0(CpuModelInfo, 1);
4036 ret->model->props = QOBJECT(props);
4037 ret->model->has_props = true;
4038
4039 switch (type) {
4040 case CPU_MODEL_EXPANSION_TYPE_STATIC:
4041 /* Static expansion will be based on "base" only */
4042 base_name = "base";
4043 x86_cpu_to_dict(xc, props);
4044 break;
4045 case CPU_MODEL_EXPANSION_TYPE_FULL:
4046 /* As we don't return every single property, full expansion needs
4047 * to keep the original model name+props, and add extra
4048 * properties on top of that.
4049 */
4050 base_name = model->name;
4051 x86_cpu_to_dict_full(xc, props);
4052 break;
4053 default:
4054 error_setg(&err, "Unsupported expansion type");
4055 goto out;
4056 }
4057
4058 x86_cpu_to_dict(xc, props);
4059
4060 ret->model->name = g_strdup(base_name);
4061
4062 out:
4063 object_unref(OBJECT(xc));
4064 if (err) {
4065 error_propagate(errp, err);
4066 qapi_free_CpuModelExpansionInfo(ret);
4067 ret = NULL;
4068 }
4069 return ret;
4070 }
4071 #endif /* !CONFIG_USER_ONLY */
4072
4073 static gchar *x86_gdb_arch_name(CPUState *cs)
4074 {
4075 #ifdef TARGET_X86_64
4076 return g_strdup("i386:x86-64");
4077 #else
4078 return g_strdup("i386");
4079 #endif
4080 }
4081
4082 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
4083 {
4084 X86CPUModel *model = data;
4085 X86CPUClass *xcc = X86_CPU_CLASS(oc);
4086
4087 xcc->model = model;
4088 xcc->migration_safe = true;
4089 }
4090
4091 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model)
4092 {
4093 char *typename = x86_cpu_type_name(name);
4094 TypeInfo ti = {
4095 .name = typename,
4096 .parent = TYPE_X86_CPU,
4097 .class_init = x86_cpu_cpudef_class_init,
4098 .class_data = model,
4099 };
4100
4101 type_register(&ti);
4102 g_free(typename);
4103 }
4104
4105 static void x86_register_cpudef_types(X86CPUDefinition *def)
4106 {
4107 X86CPUModel *m;
4108 const X86CPUVersionDefinition *vdef;
4109 char *name;
4110
4111 /* AMD aliases are handled at runtime based on CPUID vendor, so
4112 * they shouldn't be set on the CPU model table.
4113 */
4114 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
4115 /* catch mistakes instead of silently truncating model_id when too long */
4116 assert(def->model_id && strlen(def->model_id) <= 48);
4117
4118 /* Unversioned model: */
4119 m = g_new0(X86CPUModel, 1);
4120 m->cpudef = def;
4121 m->version = CPU_VERSION_AUTO;
4122 m->is_alias = true;
4123 x86_register_cpu_model_type(def->name, m);
4124
4125 /* Versioned models: */
4126
4127 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) {
4128 X86CPUModel *m = g_new0(X86CPUModel, 1);
4129 m->cpudef = def;
4130 m->version = vdef->version;
4131 name = x86_cpu_versioned_model_name(def, vdef->version);
4132 x86_register_cpu_model_type(name, m);
4133 g_free(name);
4134
4135 if (vdef->alias) {
4136 X86CPUModel *am = g_new0(X86CPUModel, 1);
4137 am->cpudef = def;
4138 am->version = vdef->version;
4139 am->is_alias = true;
4140 x86_register_cpu_model_type(vdef->alias, am);
4141 }
4142 }
4143
4144 }
4145
4146 #if !defined(CONFIG_USER_ONLY)
4147
4148 void cpu_clear_apic_feature(CPUX86State *env)
4149 {
4150 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
4151 }
4152
4153 #endif /* !CONFIG_USER_ONLY */
4154
4155 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
4156 uint32_t *eax, uint32_t *ebx,
4157 uint32_t *ecx, uint32_t *edx)
4158 {
4159 X86CPU *cpu = env_archcpu(env);
4160 CPUState *cs = env_cpu(env);
4161 uint32_t die_offset;
4162 uint32_t limit;
4163 uint32_t signature[3];
4164
4165 /* Calculate & apply limits for different index ranges */
4166 if (index >= 0xC0000000) {
4167 limit = env->cpuid_xlevel2;
4168 } else if (index >= 0x80000000) {
4169 limit = env->cpuid_xlevel;
4170 } else if (index >= 0x40000000) {
4171 limit = 0x40000001;
4172 } else {
4173 limit = env->cpuid_level;
4174 }
4175
4176 if (index > limit) {
4177 /* Intel documentation states that invalid EAX input will
4178 * return the same information as EAX=cpuid_level
4179 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
4180 */
4181 index = env->cpuid_level;
4182 }
4183
4184 switch(index) {
4185 case 0:
4186 *eax = env->cpuid_level;
4187 *ebx = env->cpuid_vendor1;
4188 *edx = env->cpuid_vendor2;
4189 *ecx = env->cpuid_vendor3;
4190 break;
4191 case 1:
4192 *eax = env->cpuid_version;
4193 *ebx = (cpu->apic_id << 24) |
4194 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
4195 *ecx = env->features[FEAT_1_ECX];
4196 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
4197 *ecx |= CPUID_EXT_OSXSAVE;
4198 }
4199 *edx = env->features[FEAT_1_EDX];
4200 if (cs->nr_cores * cs->nr_threads > 1) {
4201 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
4202 *edx |= CPUID_HT;
4203 }
4204 break;
4205 case 2:
4206 /* cache info: needed for Pentium Pro compatibility */
4207 if (cpu->cache_info_passthrough) {
4208 host_cpuid(index, 0, eax, ebx, ecx, edx);
4209 break;
4210 }
4211 *eax = 1; /* Number of CPUID[EAX=2] calls required */
4212 *ebx = 0;
4213 if (!cpu->enable_l3_cache) {
4214 *ecx = 0;
4215 } else {
4216 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
4217 }
4218 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) |
4219 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) |
4220 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache));
4221 break;
4222 case 4:
4223 /* cache info: needed for Core compatibility */
4224 if (cpu->cache_info_passthrough) {
4225 host_cpuid(index, count, eax, ebx, ecx, edx);
4226 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
4227 *eax &= ~0xFC000000;
4228 if ((*eax & 31) && cs->nr_cores > 1) {
4229 *eax |= (cs->nr_cores - 1) << 26;
4230 }
4231 } else {
4232 *eax = 0;
4233 switch (count) {
4234 case 0: /* L1 dcache info */
4235 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
4236 1, cs->nr_cores,
4237 eax, ebx, ecx, edx);
4238 break;
4239 case 1: /* L1 icache info */
4240 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
4241 1, cs->nr_cores,
4242 eax, ebx, ecx, edx);
4243 break;
4244 case 2: /* L2 cache info */
4245 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache,
4246 cs->nr_threads, cs->nr_cores,
4247 eax, ebx, ecx, edx);
4248 break;
4249 case 3: /* L3 cache info */
4250 die_offset = apicid_die_offset(env->nr_dies,
4251 cs->nr_cores, cs->nr_threads);
4252 if (cpu->enable_l3_cache) {
4253 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
4254 (1 << die_offset), cs->nr_cores,
4255 eax, ebx, ecx, edx);
4256 break;
4257 }
4258 /* fall through */
4259 default: /* end of info */
4260 *eax = *ebx = *ecx = *edx = 0;
4261 break;
4262 }
4263 }
4264 break;
4265 case 5:
4266 /* MONITOR/MWAIT Leaf */
4267 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */
4268 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */
4269 *ecx = cpu->mwait.ecx; /* flags */
4270 *edx = cpu->mwait.edx; /* mwait substates */
4271 break;
4272 case 6:
4273 /* Thermal and Power Leaf */
4274 *eax = env->features[FEAT_6_EAX];
4275 *ebx = 0;
4276 *ecx = 0;
4277 *edx = 0;
4278 break;
4279 case 7:
4280 /* Structured Extended Feature Flags Enumeration Leaf */
4281 if (count == 0) {
4282 *eax = 0; /* Maximum ECX value for sub-leaves */
4283 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
4284 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
4285 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
4286 *ecx |= CPUID_7_0_ECX_OSPKE;
4287 }
4288 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
4289 } else {
4290 *eax = 0;
4291 *ebx = 0;
4292 *ecx = 0;
4293 *edx = 0;
4294 }
4295 break;
4296 case 9:
4297 /* Direct Cache Access Information Leaf */
4298 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
4299 *ebx = 0;
4300 *ecx = 0;
4301 *edx = 0;
4302 break;
4303 case 0xA:
4304 /* Architectural Performance Monitoring Leaf */
4305 if (kvm_enabled() && cpu->enable_pmu) {
4306 KVMState *s = cs->kvm_state;
4307
4308 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
4309 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
4310 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
4311 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
4312 } else if (hvf_enabled() && cpu->enable_pmu) {
4313 *eax = hvf_get_supported_cpuid(0xA, count, R_EAX);
4314 *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX);
4315 *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX);
4316 *edx = hvf_get_supported_cpuid(0xA, count, R_EDX);
4317 } else {
4318 *eax = 0;
4319 *ebx = 0;
4320 *ecx = 0;
4321 *edx = 0;
4322 }
4323 break;
4324 case 0xB:
4325 /* Extended Topology Enumeration Leaf */
4326 if (!cpu->enable_cpuid_0xb) {
4327 *eax = *ebx = *ecx = *edx = 0;
4328 break;
4329 }
4330
4331 *ecx = count & 0xff;
4332 *edx = cpu->apic_id;
4333
4334 switch (count) {
4335 case 0:
4336 *eax = apicid_core_offset(env->nr_dies,
4337 cs->nr_cores, cs->nr_threads);
4338 *ebx = cs->nr_threads;
4339 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
4340 break;
4341 case 1:
4342 *eax = apicid_pkg_offset(env->nr_dies,
4343 cs->nr_cores, cs->nr_threads);
4344 *ebx = cs->nr_cores * cs->nr_threads;
4345 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
4346 break;
4347 default:
4348 *eax = 0;
4349 *ebx = 0;
4350 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
4351 }
4352
4353 assert(!(*eax & ~0x1f));
4354 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
4355 break;
4356 case 0x1F:
4357 /* V2 Extended Topology Enumeration Leaf */
4358 if (env->nr_dies < 2) {
4359 *eax = *ebx = *ecx = *edx = 0;
4360 break;
4361 }
4362
4363 *ecx = count & 0xff;
4364 *edx = cpu->apic_id;
4365 switch (count) {
4366 case 0:
4367 *eax = apicid_core_offset(env->nr_dies, cs->nr_cores,
4368 cs->nr_threads);
4369 *ebx = cs->nr_threads;
4370 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
4371 break;
4372 case 1:
4373 *eax = apicid_die_offset(env->nr_dies, cs->nr_cores,
4374 cs->nr_threads);
4375 *ebx = cs->nr_cores * cs->nr_threads;
4376 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
4377 break;
4378 case 2:
4379 *eax = apicid_pkg_offset(env->nr_dies, cs->nr_cores,
4380 cs->nr_threads);
4381 *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads;
4382 *ecx |= CPUID_TOPOLOGY_LEVEL_DIE;
4383 break;
4384 default:
4385 *eax = 0;
4386 *ebx = 0;
4387 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
4388 }
4389 assert(!(*eax & ~0x1f));
4390 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
4391 break;
4392 case 0xD: {
4393 /* Processor Extended State */
4394 *eax = 0;
4395 *ebx = 0;
4396 *ecx = 0;
4397 *edx = 0;
4398 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
4399 break;
4400 }
4401
4402 if (count == 0) {
4403 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
4404 *eax = env->features[FEAT_XSAVE_COMP_LO];
4405 *edx = env->features[FEAT_XSAVE_COMP_HI];
4406 *ebx = xsave_area_size(env->xcr0);
4407 } else if (count == 1) {
4408 *eax = env->features[FEAT_XSAVE];
4409 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
4410 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
4411 const ExtSaveArea *esa = &x86_ext_save_areas[count];
4412 *eax = esa->size;
4413 *ebx = esa->offset;
4414 }
4415 }
4416 break;
4417 }
4418 case 0x14: {
4419 /* Intel Processor Trace Enumeration */
4420 *eax = 0;
4421 *ebx = 0;
4422 *ecx = 0;
4423 *edx = 0;
4424 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
4425 !kvm_enabled()) {
4426 break;
4427 }
4428
4429 if (count == 0) {
4430 *eax = INTEL_PT_MAX_SUBLEAF;
4431 *ebx = INTEL_PT_MINIMAL_EBX;
4432 *ecx = INTEL_PT_MINIMAL_ECX;
4433 } else if (count == 1) {
4434 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
4435 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
4436 }
4437 break;
4438 }
4439 case 0x40000000:
4440 /*
4441 * CPUID code in kvm_arch_init_vcpu() ignores stuff
4442 * set here, but we restrict to TCG none the less.
4443 */
4444 if (tcg_enabled() && cpu->expose_tcg) {
4445 memcpy(signature, "TCGTCGTCGTCG", 12);
4446 *eax = 0x40000001;
4447 *ebx = signature[0];
4448 *ecx = signature[1];
4449 *edx = signature[2];
4450 } else {
4451 *eax = 0;
4452 *ebx = 0;
4453 *ecx = 0;
4454 *edx = 0;
4455 }
4456 break;
4457 case 0x40000001:
4458 *eax = 0;
4459 *ebx = 0;
4460 *ecx = 0;
4461 *edx = 0;
4462 break;
4463 case 0x80000000:
4464 *eax = env->cpuid_xlevel;
4465 *ebx = env->cpuid_vendor1;
4466 *edx = env->cpuid_vendor2;
4467 *ecx = env->cpuid_vendor3;
4468 break;
4469 case 0x80000001:
4470 *eax = env->cpuid_version;
4471 *ebx = 0;
4472 *ecx = env->features[FEAT_8000_0001_ECX];
4473 *edx = env->features[FEAT_8000_0001_EDX];
4474
4475 /* The Linux kernel checks for the CMPLegacy bit and
4476 * discards multiple thread information if it is set.
4477 * So don't set it here for Intel to make Linux guests happy.
4478 */
4479 if (cs->nr_cores * cs->nr_threads > 1) {
4480 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
4481 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
4482 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
4483 *ecx |= 1 << 1; /* CmpLegacy bit */
4484 }
4485 }
4486 break;
4487 case 0x80000002:
4488 case 0x80000003:
4489 case 0x80000004:
4490 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
4491 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
4492 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
4493 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
4494 break;
4495 case 0x80000005:
4496 /* cache info (L1 cache) */
4497 if (cpu->cache_info_passthrough) {
4498 host_cpuid(index, 0, eax, ebx, ecx, edx);
4499 break;
4500 }
4501 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
4502 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
4503 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
4504 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
4505 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache);
4506 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache);
4507 break;
4508 case 0x80000006:
4509 /* cache info (L2 cache) */
4510 if (cpu->cache_info_passthrough) {
4511 host_cpuid(index, 0, eax, ebx, ecx, edx);
4512 break;
4513 }
4514 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
4515 (L2_DTLB_2M_ENTRIES << 16) | \
4516 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
4517 (L2_ITLB_2M_ENTRIES);
4518 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
4519 (L2_DTLB_4K_ENTRIES << 16) | \
4520 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
4521 (L2_ITLB_4K_ENTRIES);
4522 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
4523 cpu->enable_l3_cache ?
4524 env->cache_info_amd.l3_cache : NULL,
4525 ecx, edx);
4526 break;
4527 case 0x80000007:
4528 *eax = 0;
4529 *ebx = 0;
4530 *ecx = 0;
4531 *edx = env->features[FEAT_8000_0007_EDX];
4532 break;
4533 case 0x80000008:
4534 /* virtual & phys address size in low 2 bytes. */
4535 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
4536 /* 64 bit processor */
4537 *eax = cpu->phys_bits; /* configurable physical bits */
4538 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
4539 *eax |= 0x00003900; /* 57 bits virtual */
4540 } else {
4541 *eax |= 0x00003000; /* 48 bits virtual */
4542 }
4543 } else {
4544 *eax = cpu->phys_bits;
4545 }
4546 *ebx = env->features[FEAT_8000_0008_EBX];
4547 *ecx = 0;
4548 *edx = 0;
4549 if (cs->nr_cores * cs->nr_threads > 1) {
4550 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
4551 }
4552 break;
4553 case 0x8000000A:
4554 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
4555 *eax = 0x00000001; /* SVM Revision */
4556 *ebx = 0x00000010; /* nr of ASIDs */
4557 *ecx = 0;
4558 *edx = env->features[FEAT_SVM]; /* optional features */
4559 } else {
4560 *eax = 0;
4561 *ebx = 0;
4562 *ecx = 0;
4563 *edx = 0;
4564 }
4565 break;
4566 case 0x8000001D:
4567 *eax = 0;
4568 if (cpu->cache_info_passthrough) {
4569 host_cpuid(index, count, eax, ebx, ecx, edx);
4570 break;
4571 }
4572 switch (count) {
4573 case 0: /* L1 dcache info */
4574 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs,
4575 eax, ebx, ecx, edx);
4576 break;
4577 case 1: /* L1 icache info */
4578 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, cs,
4579 eax, ebx, ecx, edx);
4580 break;
4581 case 2: /* L2 cache info */
4582 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, cs,
4583 eax, ebx, ecx, edx);
4584 break;
4585 case 3: /* L3 cache info */
4586 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, cs,
4587 eax, ebx, ecx, edx);
4588 break;
4589 default: /* end of info */
4590 *eax = *ebx = *ecx = *edx = 0;
4591 break;
4592 }
4593 break;
4594 case 0x8000001E:
4595 assert(cpu->core_id <= 255);
4596 encode_topo_cpuid8000001e(cs, cpu,
4597 eax, ebx, ecx, edx);
4598 break;
4599 case 0xC0000000:
4600 *eax = env->cpuid_xlevel2;
4601 *ebx = 0;
4602 *ecx = 0;
4603 *edx = 0;
4604 break;
4605 case 0xC0000001:
4606 /* Support for VIA CPU's CPUID instruction */
4607 *eax = env->cpuid_version;
4608 *ebx = 0;
4609 *ecx = 0;
4610 *edx = env->features[FEAT_C000_0001_EDX];
4611 break;
4612 case 0xC0000002:
4613 case 0xC0000003:
4614 case 0xC0000004:
4615 /* Reserved for the future, and now filled with zero */
4616 *eax = 0;
4617 *ebx = 0;
4618 *ecx = 0;
4619 *edx = 0;
4620 break;
4621 case 0x8000001F:
4622 *eax = sev_enabled() ? 0x2 : 0;
4623 *ebx = sev_get_cbit_position();
4624 *ebx |= sev_get_reduced_phys_bits() << 6;
4625 *ecx = 0;
4626 *edx = 0;
4627 break;
4628 default:
4629 /* reserved values: zero */
4630 *eax = 0;
4631 *ebx = 0;
4632 *ecx = 0;
4633 *edx = 0;
4634 break;
4635 }
4636 }
4637
4638 /* CPUClass::reset() */
4639 static void x86_cpu_reset(CPUState *s)
4640 {
4641 X86CPU *cpu = X86_CPU(s);
4642 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
4643 CPUX86State *env = &cpu->env;
4644 target_ulong cr4;
4645 uint64_t xcr0;
4646 int i;
4647
4648 xcc->parent_reset(s);
4649
4650 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
4651
4652 env->old_exception = -1;
4653
4654 /* init to reset state */
4655
4656 env->hflags2 |= HF2_GIF_MASK;
4657
4658 cpu_x86_update_cr0(env, 0x60000010);
4659 env->a20_mask = ~0x0;
4660 env->smbase = 0x30000;
4661 env->msr_smi_count = 0;
4662
4663 env->idt.limit = 0xffff;
4664 env->gdt.limit = 0xffff;
4665 env->ldt.limit = 0xffff;
4666 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
4667 env->tr.limit = 0xffff;
4668 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
4669
4670 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
4671 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
4672 DESC_R_MASK | DESC_A_MASK);
4673 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
4674 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4675 DESC_A_MASK);
4676 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
4677 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4678 DESC_A_MASK);
4679 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
4680 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4681 DESC_A_MASK);
4682 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
4683 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4684 DESC_A_MASK);
4685 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
4686 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4687 DESC_A_MASK);
4688
4689 env->eip = 0xfff0;
4690 env->regs[R_EDX] = env->cpuid_version;
4691
4692 env->eflags = 0x2;
4693
4694 /* FPU init */
4695 for (i = 0; i < 8; i++) {
4696 env->fptags[i] = 1;
4697 }
4698 cpu_set_fpuc(env, 0x37f);
4699
4700 env->mxcsr = 0x1f80;
4701 /* All units are in INIT state. */
4702 env->xstate_bv = 0;
4703
4704 env->pat = 0x0007040600070406ULL;
4705 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
4706 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) {
4707 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT;
4708 }
4709
4710 memset(env->dr, 0, sizeof(env->dr));
4711 env->dr[6] = DR6_FIXED_1;
4712 env->dr[7] = DR7_FIXED_1;
4713 cpu_breakpoint_remove_all(s, BP_CPU);
4714 cpu_watchpoint_remove_all(s, BP_CPU);
4715
4716 cr4 = 0;
4717 xcr0 = XSTATE_FP_MASK;
4718
4719 #ifdef CONFIG_USER_ONLY
4720 /* Enable all the features for user-mode. */
4721 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
4722 xcr0 |= XSTATE_SSE_MASK;
4723 }
4724 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
4725 const ExtSaveArea *esa = &x86_ext_save_areas[i];
4726 if (env->features[esa->feature] & esa->bits) {
4727 xcr0 |= 1ull << i;
4728 }
4729 }
4730
4731 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
4732 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
4733 }
4734 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
4735 cr4 |= CR4_FSGSBASE_MASK;
4736 }
4737 #endif
4738
4739 env->xcr0 = xcr0;
4740 cpu_x86_update_cr4(env, cr4);
4741
4742 /*
4743 * SDM 11.11.5 requires:
4744 * - IA32_MTRR_DEF_TYPE MSR.E = 0
4745 * - IA32_MTRR_PHYSMASKn.V = 0
4746 * All other bits are undefined. For simplification, zero it all.
4747 */
4748 env->mtrr_deftype = 0;
4749 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
4750 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
4751
4752 env->interrupt_injected = -1;
4753 env->exception_nr = -1;
4754 env->exception_pending = 0;
4755 env->exception_injected = 0;
4756 env->exception_has_payload = false;
4757 env->exception_payload = 0;
4758 env->nmi_injected = false;
4759 #if !defined(CONFIG_USER_ONLY)
4760 /* We hard-wire the BSP to the first CPU. */
4761 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
4762
4763 s->halted = !cpu_is_bsp(cpu);
4764
4765 if (kvm_enabled()) {
4766 kvm_arch_reset_vcpu(cpu);
4767 }
4768 else if (hvf_enabled()) {
4769 hvf_reset_vcpu(s);
4770 }
4771 #endif
4772 }
4773
4774 #ifndef CONFIG_USER_ONLY
4775 bool cpu_is_bsp(X86CPU *cpu)
4776 {
4777 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
4778 }
4779
4780 /* TODO: remove me, when reset over QOM tree is implemented */
4781 static void x86_cpu_machine_reset_cb(void *opaque)
4782 {
4783 X86CPU *cpu = opaque;
4784 cpu_reset(CPU(cpu));
4785 }
4786 #endif
4787
4788 static void mce_init(X86CPU *cpu)
4789 {
4790 CPUX86State *cenv = &cpu->env;
4791 unsigned int bank;
4792
4793 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
4794 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
4795 (CPUID_MCE | CPUID_MCA)) {
4796 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
4797 (cpu->enable_lmce ? MCG_LMCE_P : 0);
4798 cenv->mcg_ctl = ~(uint64_t)0;
4799 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
4800 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
4801 }
4802 }
4803 }
4804
4805 #ifndef CONFIG_USER_ONLY
4806 APICCommonClass *apic_get_class(void)
4807 {
4808 const char *apic_type = "apic";
4809
4810 /* TODO: in-kernel irqchip for hvf */
4811 if (kvm_apic_in_kernel()) {
4812 apic_type = "kvm-apic";
4813 } else if (xen_enabled()) {
4814 apic_type = "xen-apic";
4815 }
4816
4817 return APIC_COMMON_CLASS(object_class_by_name(apic_type));
4818 }
4819
4820 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
4821 {
4822 APICCommonState *apic;
4823 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
4824
4825 cpu->apic_state = DEVICE(object_new(object_class_get_name(apic_class)));
4826
4827 object_property_add_child(OBJECT(cpu), "lapic",
4828 OBJECT(cpu->apic_state), &error_abort);
4829 object_unref(OBJECT(cpu->apic_state));
4830
4831 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
4832 /* TODO: convert to link<> */
4833 apic = APIC_COMMON(cpu->apic_state);
4834 apic->cpu = cpu;
4835 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
4836 }
4837
4838 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
4839 {
4840 APICCommonState *apic;
4841 static bool apic_mmio_map_once;
4842
4843 if (cpu->apic_state == NULL) {
4844 return;
4845 }
4846 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
4847 errp);
4848
4849 /* Map APIC MMIO area */
4850 apic = APIC_COMMON(cpu->apic_state);
4851 if (!apic_mmio_map_once) {
4852 memory_region_add_subregion_overlap(get_system_memory(),
4853 apic->apicbase &
4854 MSR_IA32_APICBASE_BASE,
4855 &apic->io_memory,
4856 0x1000);
4857 apic_mmio_map_once = true;
4858 }
4859 }
4860
4861 static void x86_cpu_machine_done(Notifier *n, void *unused)
4862 {
4863 X86CPU *cpu = container_of(n, X86CPU, machine_done);
4864 MemoryRegion *smram =
4865 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
4866
4867 if (smram) {
4868 cpu->smram = g_new(MemoryRegion, 1);
4869 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
4870 smram, 0, 1ull << 32);
4871 memory_region_set_enabled(cpu->smram, true);
4872 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
4873 }
4874 }
4875 #else
4876 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
4877 {
4878 }
4879 #endif
4880
4881 /* Note: Only safe for use on x86(-64) hosts */
4882 static uint32_t x86_host_phys_bits(void)
4883 {
4884 uint32_t eax;
4885 uint32_t host_phys_bits;
4886
4887 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
4888 if (eax >= 0x80000008) {
4889 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
4890 /* Note: According to AMD doc 25481 rev 2.34 they have a field
4891 * at 23:16 that can specify a maximum physical address bits for
4892 * the guest that can override this value; but I've not seen
4893 * anything with that set.
4894 */
4895 host_phys_bits = eax & 0xff;
4896 } else {
4897 /* It's an odd 64 bit machine that doesn't have the leaf for
4898 * physical address bits; fall back to 36 that's most older
4899 * Intel.
4900 */
4901 host_phys_bits = 36;
4902 }
4903
4904 return host_phys_bits;
4905 }
4906
4907 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
4908 {
4909 if (*min < value) {
4910 *min = value;
4911 }
4912 }
4913
4914 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
4915 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
4916 {
4917 CPUX86State *env = &cpu->env;
4918 FeatureWordInfo *fi = &feature_word_info[w];
4919 uint32_t eax = fi->cpuid.eax;
4920 uint32_t region = eax & 0xF0000000;
4921
4922 assert(feature_word_info[w].type == CPUID_FEATURE_WORD);
4923 if (!env->features[w]) {
4924 return;
4925 }
4926
4927 switch (region) {
4928 case 0x00000000:
4929 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
4930 break;
4931 case 0x80000000:
4932 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
4933 break;
4934 case 0xC0000000:
4935 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
4936 break;
4937 }
4938 }
4939
4940 /* Calculate XSAVE components based on the configured CPU feature flags */
4941 static void x86_cpu_enable_xsave_components(X86CPU *cpu)
4942 {
4943 CPUX86State *env = &cpu->env;
4944 int i;
4945 uint64_t mask;
4946
4947 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
4948 return;
4949 }
4950
4951 mask = 0;
4952 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
4953 const ExtSaveArea *esa = &x86_ext_save_areas[i];
4954 if (env->features[esa->feature] & esa->bits) {
4955 mask |= (1ULL << i);
4956 }
4957 }
4958
4959 env->features[FEAT_XSAVE_COMP_LO] = mask;
4960 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
4961 }
4962
4963 /***** Steps involved on loading and filtering CPUID data
4964 *
4965 * When initializing and realizing a CPU object, the steps
4966 * involved in setting up CPUID data are:
4967 *
4968 * 1) Loading CPU model definition (X86CPUDefinition). This is
4969 * implemented by x86_cpu_load_model() and should be completely
4970 * transparent, as it is done automatically by instance_init.
4971 * No code should need to look at X86CPUDefinition structs
4972 * outside instance_init.
4973 *
4974 * 2) CPU expansion. This is done by realize before CPUID
4975 * filtering, and will make sure host/accelerator data is
4976 * loaded for CPU models that depend on host capabilities
4977 * (e.g. "host"). Done by x86_cpu_expand_features().
4978 *
4979 * 3) CPUID filtering. This initializes extra data related to
4980 * CPUID, and checks if the host supports all capabilities
4981 * required by the CPU. Runnability of a CPU model is
4982 * determined at this step. Done by x86_cpu_filter_features().
4983 *
4984 * Some operations don't require all steps to be performed.
4985 * More precisely:
4986 *
4987 * - CPU instance creation (instance_init) will run only CPU
4988 * model loading. CPU expansion can't run at instance_init-time
4989 * because host/accelerator data may be not available yet.
4990 * - CPU realization will perform both CPU model expansion and CPUID
4991 * filtering, and return an error in case one of them fails.
4992 * - query-cpu-definitions needs to run all 3 steps. It needs
4993 * to run CPUID filtering, as the 'unavailable-features'
4994 * field is set based on the filtering results.
4995 * - The query-cpu-model-expansion QMP command only needs to run
4996 * CPU model loading and CPU expansion. It should not filter
4997 * any CPUID data based on host capabilities.
4998 */
4999
5000 /* Expand CPU configuration data, based on configured features
5001 * and host/accelerator capabilities when appropriate.
5002 */
5003 static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
5004 {
5005 CPUX86State *env = &cpu->env;
5006 FeatureWord w;
5007 GList *l;
5008 Error *local_err = NULL;
5009
5010 /*TODO: Now cpu->max_features doesn't overwrite features
5011 * set using QOM properties, and we can convert
5012 * plus_features & minus_features to global properties
5013 * inside x86_cpu_parse_featurestr() too.
5014 */
5015 if (cpu->max_features) {
5016 for (w = 0; w < FEATURE_WORDS; w++) {
5017 /* Override only features that weren't set explicitly
5018 * by the user.
5019 */
5020 env->features[w] |=
5021 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
5022 ~env->user_features[w] & \
5023 ~feature_word_info[w].no_autoenable_flags;
5024 }
5025 }
5026
5027 for (l = plus_features; l; l = l->next) {
5028 const char *prop = l->data;
5029 object_property_set_bool(OBJECT(cpu), true, prop, &local_err);
5030 if (local_err) {
5031 goto out;
5032 }
5033 }
5034
5035 for (l = minus_features; l; l = l->next) {
5036 const char *prop = l->data;
5037 object_property_set_bool(OBJECT(cpu), false, prop, &local_err);
5038 if (local_err) {
5039 goto out;
5040 }
5041 }
5042
5043 if (!kvm_enabled() || !cpu->expose_kvm) {
5044 env->features[FEAT_KVM] = 0;
5045 }
5046
5047 x86_cpu_enable_xsave_components(cpu);
5048
5049 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
5050 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
5051 if (cpu->full_cpuid_auto_level) {
5052 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
5053 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
5054 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
5055 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
5056 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
5057 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
5058 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
5059 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
5060 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
5061 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
5062 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
5063
5064 /* Intel Processor Trace requires CPUID[0x14] */
5065 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
5066 kvm_enabled() && cpu->intel_pt_auto_level) {
5067 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14);
5068 }
5069
5070 /* CPU topology with multi-dies support requires CPUID[0x1F] */
5071 if (env->nr_dies > 1) {
5072 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F);
5073 }
5074
5075 /* SVM requires CPUID[0x8000000A] */
5076 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
5077 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
5078 }
5079
5080 /* SEV requires CPUID[0x8000001F] */
5081 if (sev_enabled()) {
5082 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
5083 }
5084 }
5085
5086 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
5087 if (env->cpuid_level == UINT32_MAX) {
5088 env->cpuid_level = env->cpuid_min_level;
5089 }
5090 if (env->cpuid_xlevel == UINT32_MAX) {
5091 env->cpuid_xlevel = env->cpuid_min_xlevel;
5092 }
5093 if (env->cpuid_xlevel2 == UINT32_MAX) {
5094 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
5095 }
5096
5097 out:
5098 if (local_err != NULL) {
5099 error_propagate(errp, local_err);
5100 }
5101 }
5102
5103 /*
5104 * Finishes initialization of CPUID data, filters CPU feature
5105 * words based on host availability of each feature.
5106 *
5107 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
5108 */
5109 static int x86_cpu_filter_features(X86CPU *cpu)
5110 {
5111 CPUX86State *env = &cpu->env;
5112 FeatureWord w;
5113 int rv = 0;
5114
5115 for (w = 0; w < FEATURE_WORDS; w++) {
5116 uint32_t host_feat =
5117 x86_cpu_get_supported_feature_word(w, false);
5118 uint32_t requested_features = env->features[w];
5119 uint32_t available_features = requested_features & host_feat;
5120 if (!cpu->force_features) {
5121 env->features[w] = available_features;
5122 }
5123 cpu->filtered_features[w] = requested_features & ~available_features;
5124 if (cpu->filtered_features[w]) {
5125 rv = 1;
5126 }
5127 }
5128
5129 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
5130 kvm_enabled()) {
5131 KVMState *s = CPU(cpu)->kvm_state;
5132 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
5133 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
5134 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
5135 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
5136 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX);
5137
5138 if (!eax_0 ||
5139 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
5140 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
5141 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) ||
5142 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) <
5143 INTEL_PT_ADDR_RANGES_NUM) ||
5144 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
5145 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) ||
5146 (ecx_0 & INTEL_PT_IP_LIP)) {
5147 /*
5148 * Processor Trace capabilities aren't configurable, so if the
5149 * host can't emulate the capabilities we report on
5150 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
5151 */
5152 env->features[FEAT_7_0_EBX] &= ~CPUID_7_0_EBX_INTEL_PT;
5153 cpu->filtered_features[FEAT_7_0_EBX] |= CPUID_7_0_EBX_INTEL_PT;
5154 rv = 1;
5155 }
5156 }
5157
5158 return rv;
5159 }
5160
5161 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
5162 {
5163 CPUState *cs = CPU(dev);
5164 X86CPU *cpu = X86_CPU(dev);
5165 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
5166 CPUX86State *env = &cpu->env;
5167 Error *local_err = NULL;
5168 static bool ht_warned;
5169
5170 if (xcc->host_cpuid_required) {
5171 if (!accel_uses_host_cpuid()) {
5172 char *name = x86_cpu_class_get_model_name(xcc);
5173 error_setg(&local_err, "CPU model '%s' requires KVM", name);
5174 g_free(name);
5175 goto out;
5176 }
5177
5178 if (enable_cpu_pm) {
5179 host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx,
5180 &cpu->mwait.ecx, &cpu->mwait.edx);
5181 env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR;
5182 }
5183 }
5184
5185 /* mwait extended info: needed for Core compatibility */
5186 /* We always wake on interrupt even if host does not have the capability */
5187 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
5188
5189 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
5190 error_setg(errp, "apic-id property was not initialized properly");
5191 return;
5192 }
5193
5194 x86_cpu_expand_features(cpu, &local_err);
5195 if (local_err) {
5196 goto out;
5197 }
5198
5199 if (x86_cpu_filter_features(cpu) &&
5200 (cpu->check_cpuid || cpu->enforce_cpuid)) {
5201 x86_cpu_report_filtered_features(cpu);
5202 if (cpu->enforce_cpuid) {
5203 error_setg(&local_err,
5204 accel_uses_host_cpuid() ?
5205 "Host doesn't support requested features" :
5206 "TCG doesn't support requested features");
5207 goto out;
5208 }
5209 }
5210
5211 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
5212 * CPUID[1].EDX.
5213 */
5214 if (IS_AMD_CPU(env)) {
5215 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
5216 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
5217 & CPUID_EXT2_AMD_ALIASES);
5218 }
5219
5220 /* For 64bit systems think about the number of physical bits to present.
5221 * ideally this should be the same as the host; anything other than matching
5222 * the host can cause incorrect guest behaviour.
5223 * QEMU used to pick the magic value of 40 bits that corresponds to
5224 * consumer AMD devices but nothing else.
5225 */
5226 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
5227 if (accel_uses_host_cpuid()) {
5228 uint32_t host_phys_bits = x86_host_phys_bits();
5229 static bool warned;
5230
5231 /* Print a warning if the user set it to a value that's not the
5232 * host value.
5233 */
5234 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
5235 !warned) {
5236 warn_report("Host physical bits (%u)"
5237 " does not match phys-bits property (%u)",
5238 host_phys_bits, cpu->phys_bits);
5239 warned = true;
5240 }
5241
5242 if (cpu->host_phys_bits) {
5243 /* The user asked for us to use the host physical bits */
5244 cpu->phys_bits = host_phys_bits;
5245 if (cpu->host_phys_bits_limit &&
5246 cpu->phys_bits > cpu->host_phys_bits_limit) {
5247 cpu->phys_bits = cpu->host_phys_bits_limit;
5248 }
5249 }
5250
5251 if (cpu->phys_bits &&
5252 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
5253 cpu->phys_bits < 32)) {
5254 error_setg(errp, "phys-bits should be between 32 and %u "
5255 " (but is %u)",
5256 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
5257 return;
5258 }
5259 } else {
5260 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
5261 error_setg(errp, "TCG only supports phys-bits=%u",
5262 TCG_PHYS_ADDR_BITS);
5263 return;
5264 }
5265 }
5266 /* 0 means it was not explicitly set by the user (or by machine
5267 * compat_props or by the host code above). In this case, the default
5268 * is the value used by TCG (40).
5269 */
5270 if (cpu->phys_bits == 0) {
5271 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
5272 }
5273 } else {
5274 /* For 32 bit systems don't use the user set value, but keep
5275 * phys_bits consistent with what we tell the guest.
5276 */
5277 if (cpu->phys_bits != 0) {
5278 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
5279 return;
5280 }
5281
5282 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
5283 cpu->phys_bits = 36;
5284 } else {
5285 cpu->phys_bits = 32;
5286 }
5287 }
5288
5289 /* Cache information initialization */
5290 if (!cpu->legacy_cache) {
5291 if (!xcc->model || !xcc->model->cpudef->cache_info) {
5292 char *name = x86_cpu_class_get_model_name(xcc);
5293 error_setg(errp,
5294 "CPU model '%s' doesn't support legacy-cache=off", name);
5295 g_free(name);
5296 return;
5297 }
5298 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
5299 *xcc->model->cpudef->cache_info;
5300 } else {
5301 /* Build legacy cache information */
5302 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
5303 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache;
5304 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2;
5305 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache;
5306
5307 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache;
5308 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache;
5309 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache;
5310 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache;
5311
5312 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd;
5313 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd;
5314 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd;
5315 env->cache_info_amd.l3_cache = &legacy_l3_cache;
5316 }
5317
5318
5319 cpu_exec_realizefn(cs, &local_err);
5320 if (local_err != NULL) {
5321 error_propagate(errp, local_err);
5322 return;
5323 }
5324
5325 #ifndef CONFIG_USER_ONLY
5326 MachineState *ms = MACHINE(qdev_get_machine());
5327 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
5328
5329 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) {
5330 x86_cpu_apic_create(cpu, &local_err);
5331 if (local_err != NULL) {
5332 goto out;
5333 }
5334 }
5335 #endif
5336
5337 mce_init(cpu);
5338
5339 #ifndef CONFIG_USER_ONLY
5340 if (tcg_enabled()) {
5341 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
5342 cpu->cpu_as_root = g_new(MemoryRegion, 1);
5343
5344 /* Outer container... */
5345 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
5346 memory_region_set_enabled(cpu->cpu_as_root, true);
5347
5348 /* ... with two regions inside: normal system memory with low
5349 * priority, and...
5350 */
5351 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
5352 get_system_memory(), 0, ~0ull);
5353 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
5354 memory_region_set_enabled(cpu->cpu_as_mem, true);
5355
5356 cs->num_ases = 2;
5357 cpu_address_space_init(cs, 0, "cpu-memory", cs->memory);
5358 cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root);
5359
5360 /* ... SMRAM with higher priority, linked from /machine/smram. */
5361 cpu->machine_done.notify = x86_cpu_machine_done;
5362 qemu_add_machine_init_done_notifier(&cpu->machine_done);
5363 }
5364 #endif
5365
5366 qemu_init_vcpu(cs);
5367
5368 /*
5369 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
5370 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
5371 * based on inputs (sockets,cores,threads), it is still better to give
5372 * users a warning.
5373 *
5374 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
5375 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
5376 */
5377 if (IS_AMD_CPU(env) &&
5378 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) &&
5379 cs->nr_threads > 1 && !ht_warned) {
5380 warn_report("This family of AMD CPU doesn't support "
5381 "hyperthreading(%d)",
5382 cs->nr_threads);
5383 error_printf("Please configure -smp options properly"
5384 " or try enabling topoext feature.\n");
5385 ht_warned = true;
5386 }
5387
5388 x86_cpu_apic_realize(cpu, &local_err);
5389 if (local_err != NULL) {
5390 goto out;
5391 }
5392 cpu_reset(cs);
5393
5394 xcc->parent_realize(dev, &local_err);
5395
5396 out:
5397 if (local_err != NULL) {
5398 error_propagate(errp, local_err);
5399 return;
5400 }
5401 }
5402
5403 static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
5404 {
5405 X86CPU *cpu = X86_CPU(dev);
5406 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
5407 Error *local_err = NULL;
5408
5409 #ifndef CONFIG_USER_ONLY
5410 cpu_remove_sync(CPU(dev));
5411 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
5412 #endif
5413
5414 if (cpu->apic_state) {
5415 object_unparent(OBJECT(cpu->apic_state));
5416 cpu->apic_state = NULL;
5417 }
5418
5419 xcc->parent_unrealize(dev, &local_err);
5420 if (local_err != NULL) {
5421 error_propagate(errp, local_err);
5422 return;
5423 }
5424 }
5425
5426 typedef struct BitProperty {
5427 FeatureWord w;
5428 uint32_t mask;
5429 } BitProperty;
5430
5431 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
5432 void *opaque, Error **errp)
5433 {
5434 X86CPU *cpu = X86_CPU(obj);
5435 BitProperty *fp = opaque;
5436 uint32_t f = cpu->env.features[fp->w];
5437 bool value = (f & fp->mask) == fp->mask;
5438 visit_type_bool(v, name, &value, errp);
5439 }
5440
5441 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
5442 void *opaque, Error **errp)
5443 {
5444 DeviceState *dev = DEVICE(obj);
5445 X86CPU *cpu = X86_CPU(obj);
5446 BitProperty *fp = opaque;
5447 Error *local_err = NULL;
5448 bool value;
5449
5450 if (dev->realized) {
5451 qdev_prop_set_after_realize(dev, name, errp);
5452 return;
5453 }
5454
5455 visit_type_bool(v, name, &value, &local_err);
5456 if (local_err) {
5457 error_propagate(errp, local_err);
5458 return;
5459 }
5460
5461 if (value) {
5462 cpu->env.features[fp->w] |= fp->mask;
5463 } else {
5464 cpu->env.features[fp->w] &= ~fp->mask;
5465 }
5466 cpu->env.user_features[fp->w] |= fp->mask;
5467 }
5468
5469 static void x86_cpu_release_bit_prop(Object *obj, const char *name,
5470 void *opaque)
5471 {
5472 BitProperty *prop = opaque;
5473 g_free(prop);
5474 }
5475
5476 /* Register a boolean property to get/set a single bit in a uint32_t field.
5477 *
5478 * The same property name can be registered multiple times to make it affect
5479 * multiple bits in the same FeatureWord. In that case, the getter will return
5480 * true only if all bits are set.
5481 */
5482 static void x86_cpu_register_bit_prop(X86CPU *cpu,
5483 const char *prop_name,
5484 FeatureWord w,
5485 int bitnr)
5486 {
5487 BitProperty *fp;
5488 ObjectProperty *op;
5489 uint32_t mask = (1UL << bitnr);
5490
5491 op = object_property_find(OBJECT(cpu), prop_name, NULL);
5492 if (op) {
5493 fp = op->opaque;
5494 assert(fp->w == w);
5495 fp->mask |= mask;
5496 } else {
5497 fp = g_new0(BitProperty, 1);
5498 fp->w = w;
5499 fp->mask = mask;
5500 object_property_add(OBJECT(cpu), prop_name, "bool",
5501 x86_cpu_get_bit_prop,
5502 x86_cpu_set_bit_prop,
5503 x86_cpu_release_bit_prop, fp, &error_abort);
5504 }
5505 }
5506
5507 static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
5508 FeatureWord w,
5509 int bitnr)
5510 {
5511 FeatureWordInfo *fi = &feature_word_info[w];
5512 const char *name = fi->feat_names[bitnr];
5513
5514 if (!name) {
5515 return;
5516 }
5517
5518 /* Property names should use "-" instead of "_".
5519 * Old names containing underscores are registered as aliases
5520 * using object_property_add_alias()
5521 */
5522 assert(!strchr(name, '_'));
5523 /* aliases don't use "|" delimiters anymore, they are registered
5524 * manually using object_property_add_alias() */
5525 assert(!strchr(name, '|'));
5526 x86_cpu_register_bit_prop(cpu, name, w, bitnr);
5527 }
5528
5529 static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
5530 {
5531 X86CPU *cpu = X86_CPU(cs);
5532 CPUX86State *env = &cpu->env;
5533 GuestPanicInformation *panic_info = NULL;
5534
5535 if (env->features[FEAT_HYPERV_EDX] & HV_GUEST_CRASH_MSR_AVAILABLE) {
5536 panic_info = g_malloc0(sizeof(GuestPanicInformation));
5537
5538 panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V;
5539
5540 assert(HV_CRASH_PARAMS >= 5);
5541 panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0];
5542 panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1];
5543 panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2];
5544 panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3];
5545 panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4];
5546 }
5547
5548 return panic_info;
5549 }
5550 static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
5551 const char *name, void *opaque,
5552 Error **errp)
5553 {
5554 CPUState *cs = CPU(obj);
5555 GuestPanicInformation *panic_info;
5556
5557 if (!cs->crash_occurred) {
5558 error_setg(errp, "No crash occured");
5559 return;
5560 }
5561
5562 panic_info = x86_cpu_get_crash_info(cs);
5563 if (panic_info == NULL) {
5564 error_setg(errp, "No crash information");
5565 return;
5566 }
5567
5568 visit_type_GuestPanicInformation(v, "crash-information", &panic_info,
5569 errp);
5570 qapi_free_GuestPanicInformation(panic_info);
5571 }
5572
5573 static void x86_cpu_initfn(Object *obj)
5574 {
5575 X86CPU *cpu = X86_CPU(obj);
5576 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
5577 CPUX86State *env = &cpu->env;
5578 FeatureWord w;
5579
5580 env->nr_dies = 1;
5581 cpu_set_cpustate_pointers(cpu);
5582
5583 object_property_add(obj, "family", "int",
5584 x86_cpuid_version_get_family,
5585 x86_cpuid_version_set_family, NULL, NULL, NULL);
5586 object_property_add(obj, "model", "int",
5587 x86_cpuid_version_get_model,
5588 x86_cpuid_version_set_model, NULL, NULL, NULL);
5589 object_property_add(obj, "stepping", "int",
5590 x86_cpuid_version_get_stepping,
5591 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
5592 object_property_add_str(obj, "vendor",
5593 x86_cpuid_get_vendor,
5594 x86_cpuid_set_vendor, NULL);
5595 object_property_add_str(obj, "model-id",
5596 x86_cpuid_get_model_id,
5597 x86_cpuid_set_model_id, NULL);
5598 object_property_add(obj, "tsc-frequency", "int",
5599 x86_cpuid_get_tsc_freq,
5600 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
5601 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
5602 x86_cpu_get_feature_words,
5603 NULL, NULL, (void *)env->features, NULL);
5604 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
5605 x86_cpu_get_feature_words,
5606 NULL, NULL, (void *)cpu->filtered_features, NULL);
5607 /*
5608 * The "unavailable-features" property has the same semantics as
5609 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions"
5610 * QMP command: they list the features that would have prevented the
5611 * CPU from running if the "enforce" flag was set.
5612 */
5613 object_property_add(obj, "unavailable-features", "strList",
5614 x86_cpu_get_unavailable_features,
5615 NULL, NULL, NULL, &error_abort);
5616
5617 object_property_add(obj, "crash-information", "GuestPanicInformation",
5618 x86_cpu_get_crash_info_qom, NULL, NULL, NULL, NULL);
5619
5620 for (w = 0; w < FEATURE_WORDS; w++) {
5621 int bitnr;
5622
5623 for (bitnr = 0; bitnr < 32; bitnr++) {
5624 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
5625 }
5626 }
5627
5628 object_property_add_alias(obj, "sse3", obj, "pni", &error_abort);
5629 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq", &error_abort);
5630 object_property_add_alias(obj, "sse4-1", obj, "sse4.1", &error_abort);
5631 object_property_add_alias(obj, "sse4-2", obj, "sse4.2", &error_abort);
5632 object_property_add_alias(obj, "xd", obj, "nx", &error_abort);
5633 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt", &error_abort);
5634 object_property_add_alias(obj, "i64", obj, "lm", &error_abort);
5635
5636 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl", &error_abort);
5637 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust", &error_abort);
5638 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt", &error_abort);
5639 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm", &error_abort);
5640 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy", &error_abort);
5641 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr", &error_abort);
5642 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core", &error_abort);
5643 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb", &error_abort);
5644 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay", &error_abort);
5645 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu", &error_abort);
5646 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf", &error_abort);
5647 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time", &error_abort);
5648 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi", &error_abort);
5649 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt", &error_abort);
5650 object_property_add_alias(obj, "svm_lock", obj, "svm-lock", &error_abort);
5651 object_property_add_alias(obj, "nrip_save", obj, "nrip-save", &error_abort);
5652 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale", &error_abort);
5653 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean", &error_abort);
5654 object_property_add_alias(obj, "pause_filter", obj, "pause-filter", &error_abort);
5655 object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort);
5656 object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort);
5657
5658 if (xcc->model) {
5659 x86_cpu_load_model(cpu, xcc->model, &error_abort);
5660 }
5661 }
5662
5663 static int64_t x86_cpu_get_arch_id(CPUState *cs)
5664 {
5665 X86CPU *cpu = X86_CPU(cs);
5666
5667 return cpu->apic_id;
5668 }
5669
5670 static bool x86_cpu_get_paging_enabled(const CPUState *cs)
5671 {
5672 X86CPU *cpu = X86_CPU(cs);
5673
5674 return cpu->env.cr[0] & CR0_PG_MASK;
5675 }
5676
5677 static void x86_cpu_set_pc(CPUState *cs, vaddr value)
5678 {
5679 X86CPU *cpu = X86_CPU(cs);
5680
5681 cpu->env.eip = value;
5682 }
5683
5684 static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
5685 {
5686 X86CPU *cpu = X86_CPU(cs);
5687
5688 cpu->env.eip = tb->pc - tb->cs_base;
5689 }
5690
5691 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
5692 {
5693 X86CPU *cpu = X86_CPU(cs);
5694 CPUX86State *env = &cpu->env;
5695
5696 #if !defined(CONFIG_USER_ONLY)
5697 if (interrupt_request & CPU_INTERRUPT_POLL) {
5698 return CPU_INTERRUPT_POLL;
5699 }
5700 #endif
5701 if (interrupt_request & CPU_INTERRUPT_SIPI) {
5702 return CPU_INTERRUPT_SIPI;
5703 }
5704
5705 if (env->hflags2 & HF2_GIF_MASK) {
5706 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
5707 !(env->hflags & HF_SMM_MASK)) {
5708 return CPU_INTERRUPT_SMI;
5709 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
5710 !(env->hflags2 & HF2_NMI_MASK)) {
5711 return CPU_INTERRUPT_NMI;
5712 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
5713 return CPU_INTERRUPT_MCE;
5714 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
5715 (((env->hflags2 & HF2_VINTR_MASK) &&
5716 (env->hflags2 & HF2_HIF_MASK)) ||
5717 (!(env->hflags2 & HF2_VINTR_MASK) &&
5718 (env->eflags & IF_MASK &&
5719 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
5720 return CPU_INTERRUPT_HARD;
5721 #if !defined(CONFIG_USER_ONLY)
5722 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
5723 (env->eflags & IF_MASK) &&
5724 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
5725 return CPU_INTERRUPT_VIRQ;
5726 #endif
5727 }
5728 }
5729
5730 return 0;
5731 }
5732
5733 static bool x86_cpu_has_work(CPUState *cs)
5734 {
5735 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
5736 }
5737
5738 static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
5739 {
5740 X86CPU *cpu = X86_CPU(cs);
5741 CPUX86State *env = &cpu->env;
5742
5743 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
5744 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
5745 : bfd_mach_i386_i8086);
5746 info->print_insn = print_insn_i386;
5747
5748 info->cap_arch = CS_ARCH_X86;
5749 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
5750 : env->hflags & HF_CS32_MASK ? CS_MODE_32
5751 : CS_MODE_16);
5752 info->cap_insn_unit = 1;
5753 info->cap_insn_split = 8;
5754 }
5755
5756 void x86_update_hflags(CPUX86State *env)
5757 {
5758 uint32_t hflags;
5759 #define HFLAG_COPY_MASK \
5760 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
5761 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
5762 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
5763 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
5764
5765 hflags = env->hflags & HFLAG_COPY_MASK;
5766 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
5767 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
5768 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
5769 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
5770 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
5771
5772 if (env->cr[4] & CR4_OSFXSR_MASK) {
5773 hflags |= HF_OSFXSR_MASK;
5774 }
5775
5776 if (env->efer & MSR_EFER_LMA) {
5777 hflags |= HF_LMA_MASK;
5778 }
5779
5780 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
5781 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
5782 } else {
5783 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
5784 (DESC_B_SHIFT - HF_CS32_SHIFT);
5785 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
5786 (DESC_B_SHIFT - HF_SS32_SHIFT);
5787 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
5788 !(hflags & HF_CS32_MASK)) {
5789 hflags |= HF_ADDSEG_MASK;
5790 } else {
5791 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
5792 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
5793 }
5794 }
5795 env->hflags = hflags;
5796 }
5797
5798 static Property x86_cpu_properties[] = {
5799 #ifdef CONFIG_USER_ONLY
5800 /* apic_id = 0 by default for *-user, see commit 9886e834 */
5801 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
5802 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
5803 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
5804 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0),
5805 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
5806 #else
5807 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
5808 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
5809 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
5810 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1),
5811 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
5812 #endif
5813 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
5814 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
5815
5816 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts,
5817 HYPERV_SPINLOCK_NEVER_RETRY),
5818 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features,
5819 HYPERV_FEAT_RELAXED, 0),
5820 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features,
5821 HYPERV_FEAT_VAPIC, 0),
5822 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features,
5823 HYPERV_FEAT_TIME, 0),
5824 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features,
5825 HYPERV_FEAT_CRASH, 0),
5826 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features,
5827 HYPERV_FEAT_RESET, 0),
5828 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features,
5829 HYPERV_FEAT_VPINDEX, 0),
5830 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features,
5831 HYPERV_FEAT_RUNTIME, 0),
5832 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features,
5833 HYPERV_FEAT_SYNIC, 0),
5834 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features,
5835 HYPERV_FEAT_STIMER, 0),
5836 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features,
5837 HYPERV_FEAT_FREQUENCIES, 0),
5838 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features,
5839 HYPERV_FEAT_REENLIGHTENMENT, 0),
5840 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features,
5841 HYPERV_FEAT_TLBFLUSH, 0),
5842 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features,
5843 HYPERV_FEAT_EVMCS, 0),
5844 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features,
5845 HYPERV_FEAT_IPI, 0),
5846 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features,
5847 HYPERV_FEAT_STIMER_DIRECT, 0),
5848 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false),
5849
5850 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
5851 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
5852 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false),
5853 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
5854 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
5855 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
5856 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0),
5857 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
5858 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
5859 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
5860 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
5861 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
5862 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
5863 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
5864 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
5865 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
5866 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
5867 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
5868 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
5869 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
5870 false),
5871 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
5872 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
5873 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
5874 true),
5875 /*
5876 * lecacy_cache defaults to true unless the CPU model provides its
5877 * own cache information (see x86_cpu_load_def()).
5878 */
5879 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
5880
5881 /*
5882 * From "Requirements for Implementing the Microsoft
5883 * Hypervisor Interface":
5884 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
5885 *
5886 * "Starting with Windows Server 2012 and Windows 8, if
5887 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
5888 * the hypervisor imposes no specific limit to the number of VPs.
5889 * In this case, Windows Server 2012 guest VMs may use more than
5890 * 64 VPs, up to the maximum supported number of processors applicable
5891 * to the specific Windows version being used."
5892 */
5893 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
5894 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only,
5895 false),
5896 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level,
5897 true),
5898 DEFINE_PROP_END_OF_LIST()
5899 };
5900
5901 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
5902 {
5903 X86CPUClass *xcc = X86_CPU_CLASS(oc);
5904 CPUClass *cc = CPU_CLASS(oc);
5905 DeviceClass *dc = DEVICE_CLASS(oc);
5906
5907 device_class_set_parent_realize(dc, x86_cpu_realizefn,
5908 &xcc->parent_realize);
5909 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
5910 &xcc->parent_unrealize);
5911 dc->props = x86_cpu_properties;
5912
5913 xcc->parent_reset = cc->reset;
5914 cc->reset = x86_cpu_reset;
5915 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
5916
5917 cc->class_by_name = x86_cpu_class_by_name;
5918 cc->parse_features = x86_cpu_parse_featurestr;
5919 cc->has_work = x86_cpu_has_work;
5920 #ifdef CONFIG_TCG
5921 cc->do_interrupt = x86_cpu_do_interrupt;
5922 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
5923 #endif
5924 cc->dump_state = x86_cpu_dump_state;
5925 cc->get_crash_info = x86_cpu_get_crash_info;
5926 cc->set_pc = x86_cpu_set_pc;
5927 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5928 cc->gdb_read_register = x86_cpu_gdb_read_register;
5929 cc->gdb_write_register = x86_cpu_gdb_write_register;
5930 cc->get_arch_id = x86_cpu_get_arch_id;
5931 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
5932 #ifndef CONFIG_USER_ONLY
5933 cc->asidx_from_attrs = x86_asidx_from_attrs;
5934 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
5935 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
5936 cc->write_elf64_note = x86_cpu_write_elf64_note;
5937 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
5938 cc->write_elf32_note = x86_cpu_write_elf32_note;
5939 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
5940 cc->vmsd = &vmstate_x86_cpu;
5941 #endif
5942 cc->gdb_arch_name = x86_gdb_arch_name;
5943 #ifdef TARGET_X86_64
5944 cc->gdb_core_xml_file = "i386-64bit.xml";
5945 cc->gdb_num_core_regs = 66;
5946 #else
5947 cc->gdb_core_xml_file = "i386-32bit.xml";
5948 cc->gdb_num_core_regs = 50;
5949 #endif
5950 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
5951 cc->debug_excp_handler = breakpoint_handler;
5952 #endif
5953 cc->cpu_exec_enter = x86_cpu_exec_enter;
5954 cc->cpu_exec_exit = x86_cpu_exec_exit;
5955 #ifdef CONFIG_TCG
5956 cc->tcg_initialize = tcg_x86_init;
5957 cc->tlb_fill = x86_cpu_tlb_fill;
5958 #endif
5959 cc->disas_set_info = x86_disas_set_info;
5960
5961 dc->user_creatable = true;
5962 }
5963
5964 static const TypeInfo x86_cpu_type_info = {
5965 .name = TYPE_X86_CPU,
5966 .parent = TYPE_CPU,
5967 .instance_size = sizeof(X86CPU),
5968 .instance_init = x86_cpu_initfn,
5969 .abstract = true,
5970 .class_size = sizeof(X86CPUClass),
5971 .class_init = x86_cpu_common_class_init,
5972 };
5973
5974
5975 /* "base" CPU model, used by query-cpu-model-expansion */
5976 static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
5977 {
5978 X86CPUClass *xcc = X86_CPU_CLASS(oc);
5979
5980 xcc->static_model = true;
5981 xcc->migration_safe = true;
5982 xcc->model_description = "base CPU model type with no features enabled";
5983 xcc->ordering = 8;
5984 }
5985
5986 static const TypeInfo x86_base_cpu_type_info = {
5987 .name = X86_CPU_TYPE_NAME("base"),
5988 .parent = TYPE_X86_CPU,
5989 .class_init = x86_cpu_base_class_init,
5990 };
5991
5992 static void x86_cpu_register_types(void)
5993 {
5994 int i;
5995
5996 type_register_static(&x86_cpu_type_info);
5997 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
5998 x86_register_cpudef_types(&builtin_x86_defs[i]);
5999 }
6000 type_register_static(&max_x86_cpu_type_info);
6001 type_register_static(&x86_base_cpu_type_info);
6002 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
6003 type_register_static(&host_x86_cpu_type_info);
6004 #endif
6005 }
6006
6007 type_init(x86_cpu_register_types)
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