2 * i386 CPUID helper functions
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu/units.h"
22 #include "qemu/cutils.h"
23 #include "qemu/bitops.h"
24 #include "qemu/qemu-print.h"
27 #include "exec/exec-all.h"
28 #include "sysemu/kvm.h"
29 #include "sysemu/hvf.h"
30 #include "sysemu/cpus.h"
34 #include "qemu/error-report.h"
35 #include "qemu/module.h"
36 #include "qemu/option.h"
37 #include "qemu/config-file.h"
38 #include "qapi/error.h"
39 #include "qapi/qapi-visit-machine.h"
40 #include "qapi/qapi-visit-run-state.h"
41 #include "qapi/qmp/qdict.h"
42 #include "qapi/qmp/qerror.h"
43 #include "qapi/visitor.h"
44 #include "qom/qom-qobject.h"
45 #include "sysemu/arch_init.h"
46 #include "qapi/qapi-commands-machine-target.h"
48 #include "standard-headers/asm-x86/kvm_para.h"
50 #include "sysemu/sysemu.h"
51 #include "sysemu/tcg.h"
52 #include "hw/qdev-properties.h"
53 #include "hw/i386/topology.h"
54 #ifndef CONFIG_USER_ONLY
55 #include "exec/address-spaces.h"
57 #include "hw/xen/xen.h"
58 #include "hw/i386/apic_internal.h"
59 #include "hw/boards.h"
62 #include "disas/capstone.h"
64 /* Helpers for building CPUID[2] descriptors: */
66 struct CPUID2CacheDescriptorInfo
{
75 * Known CPUID 2 cache descriptors.
76 * From Intel SDM Volume 2A, CPUID instruction
78 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors
[] = {
79 [0x06] = { .level
= 1, .type
= INSTRUCTION_CACHE
, .size
= 8 * KiB
,
80 .associativity
= 4, .line_size
= 32, },
81 [0x08] = { .level
= 1, .type
= INSTRUCTION_CACHE
, .size
= 16 * KiB
,
82 .associativity
= 4, .line_size
= 32, },
83 [0x09] = { .level
= 1, .type
= INSTRUCTION_CACHE
, .size
= 32 * KiB
,
84 .associativity
= 4, .line_size
= 64, },
85 [0x0A] = { .level
= 1, .type
= DATA_CACHE
, .size
= 8 * KiB
,
86 .associativity
= 2, .line_size
= 32, },
87 [0x0C] = { .level
= 1, .type
= DATA_CACHE
, .size
= 16 * KiB
,
88 .associativity
= 4, .line_size
= 32, },
89 [0x0D] = { .level
= 1, .type
= DATA_CACHE
, .size
= 16 * KiB
,
90 .associativity
= 4, .line_size
= 64, },
91 [0x0E] = { .level
= 1, .type
= DATA_CACHE
, .size
= 24 * KiB
,
92 .associativity
= 6, .line_size
= 64, },
93 [0x1D] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 128 * KiB
,
94 .associativity
= 2, .line_size
= 64, },
95 [0x21] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 256 * KiB
,
96 .associativity
= 8, .line_size
= 64, },
97 /* lines per sector is not supported cpuid2_cache_descriptor(),
98 * so descriptors 0x22, 0x23 are not included
100 [0x24] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 1 * MiB
,
101 .associativity
= 16, .line_size
= 64, },
102 /* lines per sector is not supported cpuid2_cache_descriptor(),
103 * so descriptors 0x25, 0x20 are not included
105 [0x2C] = { .level
= 1, .type
= DATA_CACHE
, .size
= 32 * KiB
,
106 .associativity
= 8, .line_size
= 64, },
107 [0x30] = { .level
= 1, .type
= INSTRUCTION_CACHE
, .size
= 32 * KiB
,
108 .associativity
= 8, .line_size
= 64, },
109 [0x41] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 128 * KiB
,
110 .associativity
= 4, .line_size
= 32, },
111 [0x42] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 256 * KiB
,
112 .associativity
= 4, .line_size
= 32, },
113 [0x43] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 512 * KiB
,
114 .associativity
= 4, .line_size
= 32, },
115 [0x44] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 1 * MiB
,
116 .associativity
= 4, .line_size
= 32, },
117 [0x45] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 2 * MiB
,
118 .associativity
= 4, .line_size
= 32, },
119 [0x46] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 4 * MiB
,
120 .associativity
= 4, .line_size
= 64, },
121 [0x47] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 8 * MiB
,
122 .associativity
= 8, .line_size
= 64, },
123 [0x48] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 3 * MiB
,
124 .associativity
= 12, .line_size
= 64, },
125 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
126 [0x4A] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 6 * MiB
,
127 .associativity
= 12, .line_size
= 64, },
128 [0x4B] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 8 * MiB
,
129 .associativity
= 16, .line_size
= 64, },
130 [0x4C] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 12 * MiB
,
131 .associativity
= 12, .line_size
= 64, },
132 [0x4D] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 16 * MiB
,
133 .associativity
= 16, .line_size
= 64, },
134 [0x4E] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 6 * MiB
,
135 .associativity
= 24, .line_size
= 64, },
136 [0x60] = { .level
= 1, .type
= DATA_CACHE
, .size
= 16 * KiB
,
137 .associativity
= 8, .line_size
= 64, },
138 [0x66] = { .level
= 1, .type
= DATA_CACHE
, .size
= 8 * KiB
,
139 .associativity
= 4, .line_size
= 64, },
140 [0x67] = { .level
= 1, .type
= DATA_CACHE
, .size
= 16 * KiB
,
141 .associativity
= 4, .line_size
= 64, },
142 [0x68] = { .level
= 1, .type
= DATA_CACHE
, .size
= 32 * KiB
,
143 .associativity
= 4, .line_size
= 64, },
144 [0x78] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 1 * MiB
,
145 .associativity
= 4, .line_size
= 64, },
146 /* lines per sector is not supported cpuid2_cache_descriptor(),
147 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
149 [0x7D] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 2 * MiB
,
150 .associativity
= 8, .line_size
= 64, },
151 [0x7F] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 512 * KiB
,
152 .associativity
= 2, .line_size
= 64, },
153 [0x80] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 512 * KiB
,
154 .associativity
= 8, .line_size
= 64, },
155 [0x82] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 256 * KiB
,
156 .associativity
= 8, .line_size
= 32, },
157 [0x83] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 512 * KiB
,
158 .associativity
= 8, .line_size
= 32, },
159 [0x84] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 1 * MiB
,
160 .associativity
= 8, .line_size
= 32, },
161 [0x85] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 2 * MiB
,
162 .associativity
= 8, .line_size
= 32, },
163 [0x86] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 512 * KiB
,
164 .associativity
= 4, .line_size
= 64, },
165 [0x87] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 1 * MiB
,
166 .associativity
= 8, .line_size
= 64, },
167 [0xD0] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 512 * KiB
,
168 .associativity
= 4, .line_size
= 64, },
169 [0xD1] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 1 * MiB
,
170 .associativity
= 4, .line_size
= 64, },
171 [0xD2] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 2 * MiB
,
172 .associativity
= 4, .line_size
= 64, },
173 [0xD6] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 1 * MiB
,
174 .associativity
= 8, .line_size
= 64, },
175 [0xD7] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 2 * MiB
,
176 .associativity
= 8, .line_size
= 64, },
177 [0xD8] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 4 * MiB
,
178 .associativity
= 8, .line_size
= 64, },
179 [0xDC] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 1.5 * MiB
,
180 .associativity
= 12, .line_size
= 64, },
181 [0xDD] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 3 * MiB
,
182 .associativity
= 12, .line_size
= 64, },
183 [0xDE] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 6 * MiB
,
184 .associativity
= 12, .line_size
= 64, },
185 [0xE2] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 2 * MiB
,
186 .associativity
= 16, .line_size
= 64, },
187 [0xE3] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 4 * MiB
,
188 .associativity
= 16, .line_size
= 64, },
189 [0xE4] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 8 * MiB
,
190 .associativity
= 16, .line_size
= 64, },
191 [0xEA] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 12 * MiB
,
192 .associativity
= 24, .line_size
= 64, },
193 [0xEB] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 18 * MiB
,
194 .associativity
= 24, .line_size
= 64, },
195 [0xEC] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 24 * MiB
,
196 .associativity
= 24, .line_size
= 64, },
200 * "CPUID leaf 2 does not report cache descriptor information,
201 * use CPUID leaf 4 to query cache parameters"
203 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
206 * Return a CPUID 2 cache descriptor for a given cache.
207 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
209 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo
*cache
)
213 assert(cache
->size
> 0);
214 assert(cache
->level
> 0);
215 assert(cache
->line_size
> 0);
216 assert(cache
->associativity
> 0);
217 for (i
= 0; i
< ARRAY_SIZE(cpuid2_cache_descriptors
); i
++) {
218 struct CPUID2CacheDescriptorInfo
*d
= &cpuid2_cache_descriptors
[i
];
219 if (d
->level
== cache
->level
&& d
->type
== cache
->type
&&
220 d
->size
== cache
->size
&& d
->line_size
== cache
->line_size
&&
221 d
->associativity
== cache
->associativity
) {
226 return CACHE_DESCRIPTOR_UNAVAILABLE
;
229 /* CPUID Leaf 4 constants: */
232 #define CACHE_TYPE_D 1
233 #define CACHE_TYPE_I 2
234 #define CACHE_TYPE_UNIFIED 3
236 #define CACHE_LEVEL(l) (l << 5)
238 #define CACHE_SELF_INIT_LEVEL (1 << 8)
241 #define CACHE_NO_INVD_SHARING (1 << 0)
242 #define CACHE_INCLUSIVE (1 << 1)
243 #define CACHE_COMPLEX_IDX (1 << 2)
245 /* Encode CacheType for CPUID[4].EAX */
246 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
247 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
248 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
249 0 /* Invalid value */)
252 /* Encode cache info for CPUID[4] */
253 static void encode_cache_cpuid4(CPUCacheInfo
*cache
,
254 int num_apic_ids
, int num_cores
,
255 uint32_t *eax
, uint32_t *ebx
,
256 uint32_t *ecx
, uint32_t *edx
)
258 assert(cache
->size
== cache
->line_size
* cache
->associativity
*
259 cache
->partitions
* cache
->sets
);
261 assert(num_apic_ids
> 0);
262 *eax
= CACHE_TYPE(cache
->type
) |
263 CACHE_LEVEL(cache
->level
) |
264 (cache
->self_init
? CACHE_SELF_INIT_LEVEL
: 0) |
265 ((num_cores
- 1) << 26) |
266 ((num_apic_ids
- 1) << 14);
268 assert(cache
->line_size
> 0);
269 assert(cache
->partitions
> 0);
270 assert(cache
->associativity
> 0);
271 /* We don't implement fully-associative caches */
272 assert(cache
->associativity
< cache
->sets
);
273 *ebx
= (cache
->line_size
- 1) |
274 ((cache
->partitions
- 1) << 12) |
275 ((cache
->associativity
- 1) << 22);
277 assert(cache
->sets
> 0);
278 *ecx
= cache
->sets
- 1;
280 *edx
= (cache
->no_invd_sharing
? CACHE_NO_INVD_SHARING
: 0) |
281 (cache
->inclusive
? CACHE_INCLUSIVE
: 0) |
282 (cache
->complex_indexing
? CACHE_COMPLEX_IDX
: 0);
285 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
286 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo
*cache
)
288 assert(cache
->size
% 1024 == 0);
289 assert(cache
->lines_per_tag
> 0);
290 assert(cache
->associativity
> 0);
291 assert(cache
->line_size
> 0);
292 return ((cache
->size
/ 1024) << 24) | (cache
->associativity
<< 16) |
293 (cache
->lines_per_tag
<< 8) | (cache
->line_size
);
296 #define ASSOC_FULL 0xFF
298 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
299 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
309 a == ASSOC_FULL ? 0xF : \
310 0 /* invalid value */)
313 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
316 static void encode_cache_cpuid80000006(CPUCacheInfo
*l2
,
318 uint32_t *ecx
, uint32_t *edx
)
320 assert(l2
->size
% 1024 == 0);
321 assert(l2
->associativity
> 0);
322 assert(l2
->lines_per_tag
> 0);
323 assert(l2
->line_size
> 0);
324 *ecx
= ((l2
->size
/ 1024) << 16) |
325 (AMD_ENC_ASSOC(l2
->associativity
) << 12) |
326 (l2
->lines_per_tag
<< 8) | (l2
->line_size
);
329 assert(l3
->size
% (512 * 1024) == 0);
330 assert(l3
->associativity
> 0);
331 assert(l3
->lines_per_tag
> 0);
332 assert(l3
->line_size
> 0);
333 *edx
= ((l3
->size
/ (512 * 1024)) << 18) |
334 (AMD_ENC_ASSOC(l3
->associativity
) << 12) |
335 (l3
->lines_per_tag
<< 8) | (l3
->line_size
);
342 * Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E
343 * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3.
344 * Define the constants to build the cpu topology. Right now, TOPOEXT
345 * feature is enabled only on EPYC. So, these constants are based on
346 * EPYC supported configurations. We may need to handle the cases if
347 * these values change in future.
349 /* Maximum core complexes in a node */
351 /* Maximum cores in a core complex */
352 #define MAX_CORES_IN_CCX 4
353 /* Maximum cores in a node */
354 #define MAX_CORES_IN_NODE 8
355 /* Maximum nodes in a socket */
356 #define MAX_NODES_PER_SOCKET 4
359 * Figure out the number of nodes required to build this config.
360 * Max cores in a node is 8
362 static int nodes_in_socket(int nr_cores
)
366 nodes
= DIV_ROUND_UP(nr_cores
, MAX_CORES_IN_NODE
);
368 /* Hardware does not support config with 3 nodes, return 4 in that case */
369 return (nodes
== 3) ? 4 : nodes
;
373 * Decide the number of cores in a core complex with the given nr_cores using
374 * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and
375 * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible
376 * L3 cache is shared across all cores in a core complex. So, this will also
377 * tell us how many cores are sharing the L3 cache.
379 static int cores_in_core_complex(int nr_cores
)
383 /* Check if we can fit all the cores in one core complex */
384 if (nr_cores
<= MAX_CORES_IN_CCX
) {
387 /* Get the number of nodes required to build this config */
388 nodes
= nodes_in_socket(nr_cores
);
391 * Divide the cores accros all the core complexes
392 * Return rounded up value
394 return DIV_ROUND_UP(nr_cores
, nodes
* MAX_CCX
);
397 /* Encode cache info for CPUID[8000001D] */
398 static void encode_cache_cpuid8000001d(CPUCacheInfo
*cache
, CPUState
*cs
,
399 uint32_t *eax
, uint32_t *ebx
,
400 uint32_t *ecx
, uint32_t *edx
)
403 assert(cache
->size
== cache
->line_size
* cache
->associativity
*
404 cache
->partitions
* cache
->sets
);
406 *eax
= CACHE_TYPE(cache
->type
) | CACHE_LEVEL(cache
->level
) |
407 (cache
->self_init
? CACHE_SELF_INIT_LEVEL
: 0);
409 /* L3 is shared among multiple cores */
410 if (cache
->level
== 3) {
411 l3_cores
= cores_in_core_complex(cs
->nr_cores
);
412 *eax
|= ((l3_cores
* cs
->nr_threads
) - 1) << 14;
414 *eax
|= ((cs
->nr_threads
- 1) << 14);
417 assert(cache
->line_size
> 0);
418 assert(cache
->partitions
> 0);
419 assert(cache
->associativity
> 0);
420 /* We don't implement fully-associative caches */
421 assert(cache
->associativity
< cache
->sets
);
422 *ebx
= (cache
->line_size
- 1) |
423 ((cache
->partitions
- 1) << 12) |
424 ((cache
->associativity
- 1) << 22);
426 assert(cache
->sets
> 0);
427 *ecx
= cache
->sets
- 1;
429 *edx
= (cache
->no_invd_sharing
? CACHE_NO_INVD_SHARING
: 0) |
430 (cache
->inclusive
? CACHE_INCLUSIVE
: 0) |
431 (cache
->complex_indexing
? CACHE_COMPLEX_IDX
: 0);
434 /* Data structure to hold the configuration info for a given core index */
435 struct core_topology
{
436 /* core complex id of the current core index */
439 * Adjusted core index for this core in the topology
440 * This can be 0,1,2,3 with max 4 cores in a core complex
443 /* Node id for this core index */
445 /* Number of nodes in this config */
450 * Build the configuration closely match the EPYC hardware. Using the EPYC
451 * hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE)
452 * right now. This could change in future.
453 * nr_cores : Total number of cores in the config
454 * core_id : Core index of the current CPU
455 * topo : Data structure to hold all the config info for this core index
457 static void build_core_topology(int nr_cores
, int core_id
,
458 struct core_topology
*topo
)
460 int nodes
, cores_in_ccx
;
462 /* First get the number of nodes required */
463 nodes
= nodes_in_socket(nr_cores
);
465 cores_in_ccx
= cores_in_core_complex(nr_cores
);
467 topo
->node_id
= core_id
/ (cores_in_ccx
* MAX_CCX
);
468 topo
->ccx_id
= (core_id
% (cores_in_ccx
* MAX_CCX
)) / cores_in_ccx
;
469 topo
->core_id
= core_id
% cores_in_ccx
;
470 topo
->num_nodes
= nodes
;
473 /* Encode cache info for CPUID[8000001E] */
474 static void encode_topo_cpuid8000001e(CPUState
*cs
, X86CPU
*cpu
,
475 uint32_t *eax
, uint32_t *ebx
,
476 uint32_t *ecx
, uint32_t *edx
)
478 struct core_topology topo
= {0};
482 build_core_topology(cs
->nr_cores
, cpu
->core_id
, &topo
);
485 * CPUID_Fn8000001E_EBX
487 * 15:8 Threads per core (The number of threads per core is
488 * Threads per core + 1)
489 * 7:0 Core id (see bit decoding below)
499 if (cs
->nr_threads
- 1) {
500 *ebx
= ((cs
->nr_threads
- 1) << 8) | (topo
.node_id
<< 3) |
501 (topo
.ccx_id
<< 2) | topo
.core_id
;
503 *ebx
= (topo
.node_id
<< 4) | (topo
.ccx_id
<< 3) | topo
.core_id
;
506 * CPUID_Fn8000001E_ECX
508 * 10:8 Nodes per processor (Nodes per processor is number of nodes + 1)
509 * 7:0 Node id (see bit decoding below)
513 if (topo
.num_nodes
<= 4) {
514 *ecx
= ((topo
.num_nodes
- 1) << 8) | (cpu
->socket_id
<< 2) |
518 * Node id fix up. Actual hardware supports up to 4 nodes. But with
519 * more than 32 cores, we may end up with more than 4 nodes.
520 * Node id is a combination of socket id and node id. Only requirement
521 * here is that this number should be unique accross the system.
522 * Shift the socket id to accommodate more nodes. We dont expect both
523 * socket id and node id to be big number at the same time. This is not
524 * an ideal config but we need to to support it. Max nodes we can have
525 * is 32 (255/8) with 8 cores per node and 255 max cores. We only need
526 * 5 bits for nodes. Find the left most set bit to represent the total
527 * number of nodes. find_last_bit returns last set bit(0 based). Left
528 * shift(+1) the socket id to represent all the nodes.
530 nodes
= topo
.num_nodes
- 1;
531 shift
= find_last_bit(&nodes
, 8);
532 *ecx
= ((topo
.num_nodes
- 1) << 8) | (cpu
->socket_id
<< (shift
+ 1)) |
539 * Definitions of the hardcoded cache entries we expose:
540 * These are legacy cache values. If there is a need to change any
541 * of these values please use builtin_x86_defs
545 static CPUCacheInfo legacy_l1d_cache
= {
554 .no_invd_sharing
= true,
557 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
558 static CPUCacheInfo legacy_l1d_cache_amd
= {
568 .no_invd_sharing
= true,
571 /* L1 instruction cache: */
572 static CPUCacheInfo legacy_l1i_cache
= {
573 .type
= INSTRUCTION_CACHE
,
581 .no_invd_sharing
= true,
584 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
585 static CPUCacheInfo legacy_l1i_cache_amd
= {
586 .type
= INSTRUCTION_CACHE
,
595 .no_invd_sharing
= true,
598 /* Level 2 unified cache: */
599 static CPUCacheInfo legacy_l2_cache
= {
600 .type
= UNIFIED_CACHE
,
608 .no_invd_sharing
= true,
611 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
612 static CPUCacheInfo legacy_l2_cache_cpuid2
= {
613 .type
= UNIFIED_CACHE
,
621 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
622 static CPUCacheInfo legacy_l2_cache_amd
= {
623 .type
= UNIFIED_CACHE
,
633 /* Level 3 unified cache: */
634 static CPUCacheInfo legacy_l3_cache
= {
635 .type
= UNIFIED_CACHE
,
645 .complex_indexing
= true,
648 /* TLB definitions: */
650 #define L1_DTLB_2M_ASSOC 1
651 #define L1_DTLB_2M_ENTRIES 255
652 #define L1_DTLB_4K_ASSOC 1
653 #define L1_DTLB_4K_ENTRIES 255
655 #define L1_ITLB_2M_ASSOC 1
656 #define L1_ITLB_2M_ENTRIES 255
657 #define L1_ITLB_4K_ASSOC 1
658 #define L1_ITLB_4K_ENTRIES 255
660 #define L2_DTLB_2M_ASSOC 0 /* disabled */
661 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
662 #define L2_DTLB_4K_ASSOC 4
663 #define L2_DTLB_4K_ENTRIES 512
665 #define L2_ITLB_2M_ASSOC 0 /* disabled */
666 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
667 #define L2_ITLB_4K_ASSOC 4
668 #define L2_ITLB_4K_ENTRIES 512
670 /* CPUID Leaf 0x14 constants: */
671 #define INTEL_PT_MAX_SUBLEAF 0x1
673 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
674 * MSR can be accessed;
675 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
676 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
677 * of Intel PT MSRs across warm reset;
678 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
680 #define INTEL_PT_MINIMAL_EBX 0xf
682 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
683 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
685 * bit[01]: ToPA tables can hold any number of output entries, up to the
686 * maximum allowed by the MaskOrTableOffset field of
687 * IA32_RTIT_OUTPUT_MASK_PTRS;
688 * bit[02]: Support Single-Range Output scheme;
690 #define INTEL_PT_MINIMAL_ECX 0x7
691 /* generated packets which contain IP payloads have LIP values */
692 #define INTEL_PT_IP_LIP (1 << 31)
693 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
694 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
695 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
696 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
697 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
699 static void x86_cpu_vendor_words2str(char *dst
, uint32_t vendor1
,
700 uint32_t vendor2
, uint32_t vendor3
)
703 for (i
= 0; i
< 4; i
++) {
704 dst
[i
] = vendor1
>> (8 * i
);
705 dst
[i
+ 4] = vendor2
>> (8 * i
);
706 dst
[i
+ 8] = vendor3
>> (8 * i
);
708 dst
[CPUID_VENDOR_SZ
] = '\0';
711 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
712 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
713 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
714 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
715 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
716 CPUID_PSE36 | CPUID_FXSR)
717 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
718 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
719 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
720 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
721 CPUID_PAE | CPUID_SEP | CPUID_APIC)
723 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
724 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
725 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
726 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
727 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
728 /* partly implemented:
729 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
731 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
732 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
733 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
734 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
735 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
736 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \
739 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
740 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
741 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
742 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
746 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
748 #define TCG_EXT2_X86_64_FEATURES 0
751 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
752 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
753 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
754 TCG_EXT2_X86_64_FEATURES)
755 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
756 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
757 #define TCG_EXT4_FEATURES 0
758 #define TCG_SVM_FEATURES CPUID_SVM_NPT
759 #define TCG_KVM_FEATURES 0
760 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
761 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
762 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
763 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
766 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
767 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
768 CPUID_7_0_EBX_RDSEED */
769 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \
770 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
772 #define TCG_7_0_EDX_FEATURES 0
773 #define TCG_APM_FEATURES 0
774 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
775 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
777 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
779 typedef enum FeatureWordType
{
784 typedef struct FeatureWordInfo
{
785 FeatureWordType type
;
786 /* feature flags names are taken from "Intel Processor Identification and
787 * the CPUID Instruction" and AMD's "CPUID Specification".
788 * In cases of disagreement between feature naming conventions,
789 * aliases may be added.
791 const char *feat_names
[32];
793 /* If type==CPUID_FEATURE_WORD */
795 uint32_t eax
; /* Input EAX for CPUID */
796 bool needs_ecx
; /* CPUID instruction uses ECX as input */
797 uint32_t ecx
; /* Input ECX value for CPUID */
798 int reg
; /* output register (R_* constant) */
800 /* If type==MSR_FEATURE_WORD */
803 struct { /*CPUID that enumerate this MSR*/
804 FeatureWord cpuid_class
;
809 uint32_t tcg_features
; /* Feature flags supported by TCG */
810 uint32_t unmigratable_flags
; /* Feature flags known to be unmigratable */
811 uint32_t migratable_flags
; /* Feature flags known to be migratable */
812 /* Features that shouldn't be auto-enabled by "-cpu host" */
813 uint32_t no_autoenable_flags
;
816 static FeatureWordInfo feature_word_info
[FEATURE_WORDS
] = {
818 .type
= CPUID_FEATURE_WORD
,
820 "fpu", "vme", "de", "pse",
821 "tsc", "msr", "pae", "mce",
822 "cx8", "apic", NULL
, "sep",
823 "mtrr", "pge", "mca", "cmov",
824 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
825 NULL
, "ds" /* Intel dts */, "acpi", "mmx",
826 "fxsr", "sse", "sse2", "ss",
827 "ht" /* Intel htt */, "tm", "ia64", "pbe",
829 .cpuid
= {.eax
= 1, .reg
= R_EDX
, },
830 .tcg_features
= TCG_FEATURES
,
833 .type
= CPUID_FEATURE_WORD
,
835 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
836 "ds-cpl", "vmx", "smx", "est",
837 "tm2", "ssse3", "cid", NULL
,
838 "fma", "cx16", "xtpr", "pdcm",
839 NULL
, "pcid", "dca", "sse4.1",
840 "sse4.2", "x2apic", "movbe", "popcnt",
841 "tsc-deadline", "aes", "xsave", NULL
/* osxsave */,
842 "avx", "f16c", "rdrand", "hypervisor",
844 .cpuid
= { .eax
= 1, .reg
= R_ECX
, },
845 .tcg_features
= TCG_EXT_FEATURES
,
847 /* Feature names that are already defined on feature_name[] but
848 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
849 * names on feat_names below. They are copied automatically
850 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
852 [FEAT_8000_0001_EDX
] = {
853 .type
= CPUID_FEATURE_WORD
,
855 NULL
/* fpu */, NULL
/* vme */, NULL
/* de */, NULL
/* pse */,
856 NULL
/* tsc */, NULL
/* msr */, NULL
/* pae */, NULL
/* mce */,
857 NULL
/* cx8 */, NULL
/* apic */, NULL
, "syscall",
858 NULL
/* mtrr */, NULL
/* pge */, NULL
/* mca */, NULL
/* cmov */,
859 NULL
/* pat */, NULL
/* pse36 */, NULL
, NULL
/* Linux mp */,
860 "nx", NULL
, "mmxext", NULL
/* mmx */,
861 NULL
/* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
862 NULL
, "lm", "3dnowext", "3dnow",
864 .cpuid
= { .eax
= 0x80000001, .reg
= R_EDX
, },
865 .tcg_features
= TCG_EXT2_FEATURES
,
867 [FEAT_8000_0001_ECX
] = {
868 .type
= CPUID_FEATURE_WORD
,
870 "lahf-lm", "cmp-legacy", "svm", "extapic",
871 "cr8legacy", "abm", "sse4a", "misalignsse",
872 "3dnowprefetch", "osvw", "ibs", "xop",
873 "skinit", "wdt", NULL
, "lwp",
874 "fma4", "tce", NULL
, "nodeid-msr",
875 NULL
, "tbm", "topoext", "perfctr-core",
876 "perfctr-nb", NULL
, NULL
, NULL
,
877 NULL
, NULL
, NULL
, NULL
,
879 .cpuid
= { .eax
= 0x80000001, .reg
= R_ECX
, },
880 .tcg_features
= TCG_EXT3_FEATURES
,
882 * TOPOEXT is always allowed but can't be enabled blindly by
883 * "-cpu host", as it requires consistent cache topology info
884 * to be provided so it doesn't confuse guests.
886 .no_autoenable_flags
= CPUID_EXT3_TOPOEXT
,
888 [FEAT_C000_0001_EDX
] = {
889 .type
= CPUID_FEATURE_WORD
,
891 NULL
, NULL
, "xstore", "xstore-en",
892 NULL
, NULL
, "xcrypt", "xcrypt-en",
893 "ace2", "ace2-en", "phe", "phe-en",
894 "pmm", "pmm-en", NULL
, NULL
,
895 NULL
, NULL
, NULL
, NULL
,
896 NULL
, NULL
, NULL
, NULL
,
897 NULL
, NULL
, NULL
, NULL
,
898 NULL
, NULL
, NULL
, NULL
,
900 .cpuid
= { .eax
= 0xC0000001, .reg
= R_EDX
, },
901 .tcg_features
= TCG_EXT4_FEATURES
,
904 .type
= CPUID_FEATURE_WORD
,
906 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
907 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
908 NULL
, "kvm-pv-tlb-flush", NULL
, "kvm-pv-ipi",
909 NULL
, NULL
, NULL
, NULL
,
910 NULL
, NULL
, NULL
, NULL
,
911 NULL
, NULL
, NULL
, NULL
,
912 "kvmclock-stable-bit", NULL
, NULL
, NULL
,
913 NULL
, NULL
, NULL
, NULL
,
915 .cpuid
= { .eax
= KVM_CPUID_FEATURES
, .reg
= R_EAX
, },
916 .tcg_features
= TCG_KVM_FEATURES
,
919 .type
= CPUID_FEATURE_WORD
,
921 "kvm-hint-dedicated", NULL
, NULL
, NULL
,
922 NULL
, NULL
, NULL
, NULL
,
923 NULL
, NULL
, NULL
, NULL
,
924 NULL
, NULL
, NULL
, NULL
,
925 NULL
, NULL
, NULL
, NULL
,
926 NULL
, NULL
, NULL
, NULL
,
927 NULL
, NULL
, NULL
, NULL
,
928 NULL
, NULL
, NULL
, NULL
,
930 .cpuid
= { .eax
= KVM_CPUID_FEATURES
, .reg
= R_EDX
, },
931 .tcg_features
= TCG_KVM_FEATURES
,
933 * KVM hints aren't auto-enabled by -cpu host, they need to be
934 * explicitly enabled in the command-line.
936 .no_autoenable_flags
= ~0U,
939 * .feat_names are commented out for Hyper-V enlightenments because we
940 * don't want to have two different ways for enabling them on QEMU command
941 * line. Some features (e.g. "hyperv_time", "hyperv_vapic", ...) require
942 * enabling several feature bits simultaneously, exposing these bits
943 * individually may just confuse guests.
945 [FEAT_HYPERV_EAX
] = {
946 .type
= CPUID_FEATURE_WORD
,
948 NULL
/* hv_msr_vp_runtime_access */, NULL
/* hv_msr_time_refcount_access */,
949 NULL
/* hv_msr_synic_access */, NULL
/* hv_msr_stimer_access */,
950 NULL
/* hv_msr_apic_access */, NULL
/* hv_msr_hypercall_access */,
951 NULL
/* hv_vpindex_access */, NULL
/* hv_msr_reset_access */,
952 NULL
/* hv_msr_stats_access */, NULL
/* hv_reftsc_access */,
953 NULL
/* hv_msr_idle_access */, NULL
/* hv_msr_frequency_access */,
954 NULL
/* hv_msr_debug_access */, NULL
/* hv_msr_reenlightenment_access */,
956 NULL
, NULL
, NULL
, NULL
,
957 NULL
, NULL
, NULL
, NULL
,
958 NULL
, NULL
, NULL
, NULL
,
959 NULL
, NULL
, NULL
, NULL
,
961 .cpuid
= { .eax
= 0x40000003, .reg
= R_EAX
, },
963 [FEAT_HYPERV_EBX
] = {
964 .type
= CPUID_FEATURE_WORD
,
966 NULL
/* hv_create_partitions */, NULL
/* hv_access_partition_id */,
967 NULL
/* hv_access_memory_pool */, NULL
/* hv_adjust_message_buffers */,
968 NULL
/* hv_post_messages */, NULL
/* hv_signal_events */,
969 NULL
/* hv_create_port */, NULL
/* hv_connect_port */,
970 NULL
/* hv_access_stats */, NULL
, NULL
, NULL
/* hv_debugging */,
971 NULL
/* hv_cpu_power_management */, NULL
/* hv_configure_profiler */,
973 NULL
, NULL
, NULL
, NULL
,
974 NULL
, NULL
, NULL
, NULL
,
975 NULL
, NULL
, NULL
, NULL
,
976 NULL
, NULL
, NULL
, NULL
,
978 .cpuid
= { .eax
= 0x40000003, .reg
= R_EBX
, },
980 [FEAT_HYPERV_EDX
] = {
981 .type
= CPUID_FEATURE_WORD
,
983 NULL
/* hv_mwait */, NULL
/* hv_guest_debugging */,
984 NULL
/* hv_perf_monitor */, NULL
/* hv_cpu_dynamic_part */,
985 NULL
/* hv_hypercall_params_xmm */, NULL
/* hv_guest_idle_state */,
987 NULL
, NULL
, NULL
/* hv_guest_crash_msr */, NULL
,
988 NULL
, NULL
, NULL
, NULL
,
989 NULL
, NULL
, NULL
, NULL
,
990 NULL
, NULL
, NULL
, NULL
,
991 NULL
, NULL
, NULL
, NULL
,
992 NULL
, NULL
, NULL
, NULL
,
994 .cpuid
= { .eax
= 0x40000003, .reg
= R_EDX
, },
996 [FEAT_HV_RECOMM_EAX
] = {
997 .type
= CPUID_FEATURE_WORD
,
999 NULL
/* hv_recommend_pv_as_switch */,
1000 NULL
/* hv_recommend_pv_tlbflush_local */,
1001 NULL
/* hv_recommend_pv_tlbflush_remote */,
1002 NULL
/* hv_recommend_msr_apic_access */,
1003 NULL
/* hv_recommend_msr_reset */,
1004 NULL
/* hv_recommend_relaxed_timing */,
1005 NULL
/* hv_recommend_dma_remapping */,
1006 NULL
/* hv_recommend_int_remapping */,
1007 NULL
/* hv_recommend_x2apic_msrs */,
1008 NULL
/* hv_recommend_autoeoi_deprecation */,
1009 NULL
/* hv_recommend_pv_ipi */,
1010 NULL
/* hv_recommend_ex_hypercalls */,
1011 NULL
/* hv_hypervisor_is_nested */,
1012 NULL
/* hv_recommend_int_mbec */,
1013 NULL
/* hv_recommend_evmcs */,
1015 NULL
, NULL
, NULL
, NULL
,
1016 NULL
, NULL
, NULL
, NULL
,
1017 NULL
, NULL
, NULL
, NULL
,
1018 NULL
, NULL
, NULL
, NULL
,
1020 .cpuid
= { .eax
= 0x40000004, .reg
= R_EAX
, },
1022 [FEAT_HV_NESTED_EAX
] = {
1023 .type
= CPUID_FEATURE_WORD
,
1024 .cpuid
= { .eax
= 0x4000000A, .reg
= R_EAX
, },
1027 .type
= CPUID_FEATURE_WORD
,
1029 "npt", "lbrv", "svm-lock", "nrip-save",
1030 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
1031 NULL
, NULL
, "pause-filter", NULL
,
1032 "pfthreshold", NULL
, NULL
, NULL
,
1033 NULL
, NULL
, NULL
, NULL
,
1034 NULL
, NULL
, NULL
, NULL
,
1035 NULL
, NULL
, NULL
, NULL
,
1036 NULL
, NULL
, NULL
, NULL
,
1038 .cpuid
= { .eax
= 0x8000000A, .reg
= R_EDX
, },
1039 .tcg_features
= TCG_SVM_FEATURES
,
1042 .type
= CPUID_FEATURE_WORD
,
1044 "fsgsbase", "tsc-adjust", NULL
, "bmi1",
1045 "hle", "avx2", NULL
, "smep",
1046 "bmi2", "erms", "invpcid", "rtm",
1047 NULL
, NULL
, "mpx", NULL
,
1048 "avx512f", "avx512dq", "rdseed", "adx",
1049 "smap", "avx512ifma", "pcommit", "clflushopt",
1050 "clwb", "intel-pt", "avx512pf", "avx512er",
1051 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
1055 .needs_ecx
= true, .ecx
= 0,
1058 .tcg_features
= TCG_7_0_EBX_FEATURES
,
1061 .type
= CPUID_FEATURE_WORD
,
1063 NULL
, "avx512vbmi", "umip", "pku",
1064 NULL
/* ospke */, NULL
, "avx512vbmi2", NULL
,
1065 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
1066 "avx512bitalg", NULL
, "avx512-vpopcntdq", NULL
,
1067 "la57", NULL
, NULL
, NULL
,
1068 NULL
, NULL
, "rdpid", NULL
,
1069 NULL
, "cldemote", NULL
, "movdiri",
1070 "movdir64b", NULL
, NULL
, NULL
,
1074 .needs_ecx
= true, .ecx
= 0,
1077 .tcg_features
= TCG_7_0_ECX_FEATURES
,
1080 .type
= CPUID_FEATURE_WORD
,
1082 NULL
, NULL
, "avx512-4vnniw", "avx512-4fmaps",
1083 NULL
, NULL
, NULL
, NULL
,
1084 NULL
, NULL
, "md-clear", NULL
,
1085 NULL
, NULL
, NULL
, NULL
,
1086 NULL
, NULL
, NULL
, NULL
,
1087 NULL
, NULL
, NULL
, NULL
,
1088 NULL
, NULL
, "spec-ctrl", "stibp",
1089 NULL
, "arch-capabilities", "core-capability", "ssbd",
1093 .needs_ecx
= true, .ecx
= 0,
1096 .tcg_features
= TCG_7_0_EDX_FEATURES
,
1098 [FEAT_8000_0007_EDX
] = {
1099 .type
= CPUID_FEATURE_WORD
,
1101 NULL
, NULL
, NULL
, NULL
,
1102 NULL
, NULL
, NULL
, NULL
,
1103 "invtsc", NULL
, NULL
, NULL
,
1104 NULL
, NULL
, NULL
, NULL
,
1105 NULL
, NULL
, NULL
, NULL
,
1106 NULL
, NULL
, NULL
, NULL
,
1107 NULL
, NULL
, NULL
, NULL
,
1108 NULL
, NULL
, NULL
, NULL
,
1110 .cpuid
= { .eax
= 0x80000007, .reg
= R_EDX
, },
1111 .tcg_features
= TCG_APM_FEATURES
,
1112 .unmigratable_flags
= CPUID_APM_INVTSC
,
1114 [FEAT_8000_0008_EBX
] = {
1115 .type
= CPUID_FEATURE_WORD
,
1117 NULL
, NULL
, NULL
, NULL
,
1118 NULL
, NULL
, NULL
, NULL
,
1119 NULL
, "wbnoinvd", NULL
, NULL
,
1120 "ibpb", NULL
, NULL
, NULL
,
1121 NULL
, NULL
, NULL
, NULL
,
1122 NULL
, NULL
, NULL
, NULL
,
1123 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL
,
1124 NULL
, NULL
, NULL
, NULL
,
1126 .cpuid
= { .eax
= 0x80000008, .reg
= R_EBX
, },
1128 .unmigratable_flags
= 0,
1131 .type
= CPUID_FEATURE_WORD
,
1133 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
1134 NULL
, NULL
, NULL
, NULL
,
1135 NULL
, NULL
, NULL
, NULL
,
1136 NULL
, NULL
, NULL
, NULL
,
1137 NULL
, NULL
, NULL
, NULL
,
1138 NULL
, NULL
, NULL
, NULL
,
1139 NULL
, NULL
, NULL
, NULL
,
1140 NULL
, NULL
, NULL
, NULL
,
1144 .needs_ecx
= true, .ecx
= 1,
1147 .tcg_features
= TCG_XSAVE_FEATURES
,
1150 .type
= CPUID_FEATURE_WORD
,
1152 NULL
, NULL
, "arat", NULL
,
1153 NULL
, NULL
, NULL
, NULL
,
1154 NULL
, NULL
, NULL
, NULL
,
1155 NULL
, NULL
, NULL
, NULL
,
1156 NULL
, NULL
, NULL
, NULL
,
1157 NULL
, NULL
, NULL
, NULL
,
1158 NULL
, NULL
, NULL
, NULL
,
1159 NULL
, NULL
, NULL
, NULL
,
1161 .cpuid
= { .eax
= 6, .reg
= R_EAX
, },
1162 .tcg_features
= TCG_6_EAX_FEATURES
,
1164 [FEAT_XSAVE_COMP_LO
] = {
1165 .type
= CPUID_FEATURE_WORD
,
1168 .needs_ecx
= true, .ecx
= 0,
1171 .tcg_features
= ~0U,
1172 .migratable_flags
= XSTATE_FP_MASK
| XSTATE_SSE_MASK
|
1173 XSTATE_YMM_MASK
| XSTATE_BNDREGS_MASK
| XSTATE_BNDCSR_MASK
|
1174 XSTATE_OPMASK_MASK
| XSTATE_ZMM_Hi256_MASK
| XSTATE_Hi16_ZMM_MASK
|
1177 [FEAT_XSAVE_COMP_HI
] = {
1178 .type
= CPUID_FEATURE_WORD
,
1181 .needs_ecx
= true, .ecx
= 0,
1184 .tcg_features
= ~0U,
1186 /*Below are MSR exposed features*/
1187 [FEAT_ARCH_CAPABILITIES
] = {
1188 .type
= MSR_FEATURE_WORD
,
1190 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
1191 "ssb-no", "mds-no", NULL
, NULL
,
1192 NULL
, NULL
, NULL
, NULL
,
1193 NULL
, NULL
, NULL
, NULL
,
1194 NULL
, NULL
, NULL
, NULL
,
1195 NULL
, NULL
, NULL
, NULL
,
1196 NULL
, NULL
, NULL
, NULL
,
1197 NULL
, NULL
, NULL
, NULL
,
1200 .index
= MSR_IA32_ARCH_CAPABILITIES
,
1203 CPUID_7_0_EDX_ARCH_CAPABILITIES
1207 [FEAT_CORE_CAPABILITY
] = {
1208 .type
= MSR_FEATURE_WORD
,
1210 NULL
, NULL
, NULL
, NULL
,
1211 NULL
, "split-lock-detect", NULL
, NULL
,
1212 NULL
, NULL
, NULL
, NULL
,
1213 NULL
, NULL
, NULL
, NULL
,
1214 NULL
, NULL
, NULL
, NULL
,
1215 NULL
, NULL
, NULL
, NULL
,
1216 NULL
, NULL
, NULL
, NULL
,
1217 NULL
, NULL
, NULL
, NULL
,
1220 .index
= MSR_IA32_CORE_CAPABILITY
,
1223 CPUID_7_0_EDX_CORE_CAPABILITY
,
1229 typedef struct X86RegisterInfo32
{
1230 /* Name of register */
1232 /* QAPI enum value register */
1233 X86CPURegister32 qapi_enum
;
1234 } X86RegisterInfo32
;
1236 #define REGISTER(reg) \
1237 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
1238 static const X86RegisterInfo32 x86_reg_info_32
[CPU_NB_REGS32
] = {
1250 typedef struct ExtSaveArea
{
1251 uint32_t feature
, bits
;
1252 uint32_t offset
, size
;
1255 static const ExtSaveArea x86_ext_save_areas
[] = {
1257 /* x87 FP state component is always enabled if XSAVE is supported */
1258 .feature
= FEAT_1_ECX
, .bits
= CPUID_EXT_XSAVE
,
1259 /* x87 state is in the legacy region of the XSAVE area */
1261 .size
= sizeof(X86LegacyXSaveArea
) + sizeof(X86XSaveHeader
),
1263 [XSTATE_SSE_BIT
] = {
1264 /* SSE state component is always enabled if XSAVE is supported */
1265 .feature
= FEAT_1_ECX
, .bits
= CPUID_EXT_XSAVE
,
1266 /* SSE state is in the legacy region of the XSAVE area */
1268 .size
= sizeof(X86LegacyXSaveArea
) + sizeof(X86XSaveHeader
),
1271 { .feature
= FEAT_1_ECX
, .bits
= CPUID_EXT_AVX
,
1272 .offset
= offsetof(X86XSaveArea
, avx_state
),
1273 .size
= sizeof(XSaveAVX
) },
1274 [XSTATE_BNDREGS_BIT
] =
1275 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_MPX
,
1276 .offset
= offsetof(X86XSaveArea
, bndreg_state
),
1277 .size
= sizeof(XSaveBNDREG
) },
1278 [XSTATE_BNDCSR_BIT
] =
1279 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_MPX
,
1280 .offset
= offsetof(X86XSaveArea
, bndcsr_state
),
1281 .size
= sizeof(XSaveBNDCSR
) },
1282 [XSTATE_OPMASK_BIT
] =
1283 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
1284 .offset
= offsetof(X86XSaveArea
, opmask_state
),
1285 .size
= sizeof(XSaveOpmask
) },
1286 [XSTATE_ZMM_Hi256_BIT
] =
1287 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
1288 .offset
= offsetof(X86XSaveArea
, zmm_hi256_state
),
1289 .size
= sizeof(XSaveZMM_Hi256
) },
1290 [XSTATE_Hi16_ZMM_BIT
] =
1291 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
1292 .offset
= offsetof(X86XSaveArea
, hi16_zmm_state
),
1293 .size
= sizeof(XSaveHi16_ZMM
) },
1295 { .feature
= FEAT_7_0_ECX
, .bits
= CPUID_7_0_ECX_PKU
,
1296 .offset
= offsetof(X86XSaveArea
, pkru_state
),
1297 .size
= sizeof(XSavePKRU
) },
1300 static uint32_t xsave_area_size(uint64_t mask
)
1305 for (i
= 0; i
< ARRAY_SIZE(x86_ext_save_areas
); i
++) {
1306 const ExtSaveArea
*esa
= &x86_ext_save_areas
[i
];
1307 if ((mask
>> i
) & 1) {
1308 ret
= MAX(ret
, esa
->offset
+ esa
->size
);
1314 static inline bool accel_uses_host_cpuid(void)
1316 return kvm_enabled() || hvf_enabled();
1319 static inline uint64_t x86_cpu_xsave_components(X86CPU
*cpu
)
1321 return ((uint64_t)cpu
->env
.features
[FEAT_XSAVE_COMP_HI
]) << 32 |
1322 cpu
->env
.features
[FEAT_XSAVE_COMP_LO
];
1325 const char *get_register_name_32(unsigned int reg
)
1327 if (reg
>= CPU_NB_REGS32
) {
1330 return x86_reg_info_32
[reg
].name
;
1334 * Returns the set of feature flags that are supported and migratable by
1335 * QEMU, for a given FeatureWord.
1337 static uint32_t x86_cpu_get_migratable_flags(FeatureWord w
)
1339 FeatureWordInfo
*wi
= &feature_word_info
[w
];
1343 for (i
= 0; i
< 32; i
++) {
1344 uint32_t f
= 1U << i
;
1346 /* If the feature name is known, it is implicitly considered migratable,
1347 * unless it is explicitly set in unmigratable_flags */
1348 if ((wi
->migratable_flags
& f
) ||
1349 (wi
->feat_names
[i
] && !(wi
->unmigratable_flags
& f
))) {
1356 void host_cpuid(uint32_t function
, uint32_t count
,
1357 uint32_t *eax
, uint32_t *ebx
, uint32_t *ecx
, uint32_t *edx
)
1362 asm volatile("cpuid"
1363 : "=a"(vec
[0]), "=b"(vec
[1]),
1364 "=c"(vec
[2]), "=d"(vec
[3])
1365 : "0"(function
), "c"(count
) : "cc");
1366 #elif defined(__i386__)
1367 asm volatile("pusha \n\t"
1369 "mov %%eax, 0(%2) \n\t"
1370 "mov %%ebx, 4(%2) \n\t"
1371 "mov %%ecx, 8(%2) \n\t"
1372 "mov %%edx, 12(%2) \n\t"
1374 : : "a"(function
), "c"(count
), "S"(vec
)
1390 void host_vendor_fms(char *vendor
, int *family
, int *model
, int *stepping
)
1392 uint32_t eax
, ebx
, ecx
, edx
;
1394 host_cpuid(0x0, 0, &eax
, &ebx
, &ecx
, &edx
);
1395 x86_cpu_vendor_words2str(vendor
, ebx
, edx
, ecx
);
1397 host_cpuid(0x1, 0, &eax
, &ebx
, &ecx
, &edx
);
1399 *family
= ((eax
>> 8) & 0x0F) + ((eax
>> 20) & 0xFF);
1402 *model
= ((eax
>> 4) & 0x0F) | ((eax
& 0xF0000) >> 12);
1405 *stepping
= eax
& 0x0F;
1409 /* CPU class name definitions: */
1411 /* Return type name for a given CPU model name
1412 * Caller is responsible for freeing the returned string.
1414 static char *x86_cpu_type_name(const char *model_name
)
1416 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name
);
1419 static ObjectClass
*x86_cpu_class_by_name(const char *cpu_model
)
1422 char *typename
= x86_cpu_type_name(cpu_model
);
1423 oc
= object_class_by_name(typename
);
1428 static char *x86_cpu_class_get_model_name(X86CPUClass
*cc
)
1430 const char *class_name
= object_class_get_name(OBJECT_CLASS(cc
));
1431 assert(g_str_has_suffix(class_name
, X86_CPU_TYPE_SUFFIX
));
1432 return g_strndup(class_name
,
1433 strlen(class_name
) - strlen(X86_CPU_TYPE_SUFFIX
));
1436 struct X86CPUDefinition
{
1440 /* vendor is zero-terminated, 12 character ASCII string */
1441 char vendor
[CPUID_VENDOR_SZ
+ 1];
1445 FeatureWordArray features
;
1446 const char *model_id
;
1447 CPUCaches
*cache_info
;
1450 static CPUCaches epyc_cache_info
= {
1451 .l1d_cache
= &(CPUCacheInfo
) {
1461 .no_invd_sharing
= true,
1463 .l1i_cache
= &(CPUCacheInfo
) {
1464 .type
= INSTRUCTION_CACHE
,
1473 .no_invd_sharing
= true,
1475 .l2_cache
= &(CPUCacheInfo
) {
1476 .type
= UNIFIED_CACHE
,
1485 .l3_cache
= &(CPUCacheInfo
) {
1486 .type
= UNIFIED_CACHE
,
1490 .associativity
= 16,
1496 .complex_indexing
= true,
1500 static X86CPUDefinition builtin_x86_defs
[] = {
1504 .vendor
= CPUID_VENDOR_AMD
,
1508 .features
[FEAT_1_EDX
] =
1510 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
1512 .features
[FEAT_1_ECX
] =
1513 CPUID_EXT_SSE3
| CPUID_EXT_CX16
,
1514 .features
[FEAT_8000_0001_EDX
] =
1515 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
1516 .features
[FEAT_8000_0001_ECX
] =
1517 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
,
1518 .xlevel
= 0x8000000A,
1519 .model_id
= "QEMU Virtual CPU version " QEMU_HW_VERSION
,
1524 .vendor
= CPUID_VENDOR_AMD
,
1528 /* Missing: CPUID_HT */
1529 .features
[FEAT_1_EDX
] =
1531 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
1532 CPUID_PSE36
| CPUID_VME
,
1533 .features
[FEAT_1_ECX
] =
1534 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_CX16
|
1536 .features
[FEAT_8000_0001_EDX
] =
1537 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
|
1538 CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
| CPUID_EXT2_MMXEXT
|
1539 CPUID_EXT2_FFXSR
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
,
1540 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1542 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1543 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
1544 .features
[FEAT_8000_0001_ECX
] =
1545 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
|
1546 CPUID_EXT3_ABM
| CPUID_EXT3_SSE4A
,
1547 /* Missing: CPUID_SVM_LBRV */
1548 .features
[FEAT_SVM
] =
1550 .xlevel
= 0x8000001A,
1551 .model_id
= "AMD Phenom(tm) 9550 Quad-Core Processor"
1556 .vendor
= CPUID_VENDOR_INTEL
,
1560 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1561 .features
[FEAT_1_EDX
] =
1563 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
1564 CPUID_PSE36
| CPUID_VME
| CPUID_ACPI
| CPUID_SS
,
1565 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
1566 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
1567 .features
[FEAT_1_ECX
] =
1568 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
1570 .features
[FEAT_8000_0001_EDX
] =
1571 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
1572 .features
[FEAT_8000_0001_ECX
] =
1574 .xlevel
= 0x80000008,
1575 .model_id
= "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
1580 .vendor
= CPUID_VENDOR_INTEL
,
1584 /* Missing: CPUID_HT */
1585 .features
[FEAT_1_EDX
] =
1586 PPRO_FEATURES
| CPUID_VME
|
1587 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
1589 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
1590 .features
[FEAT_1_ECX
] =
1591 CPUID_EXT_SSE3
| CPUID_EXT_CX16
,
1592 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
1593 .features
[FEAT_8000_0001_EDX
] =
1594 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
1595 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1596 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
1597 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1598 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
1599 .features
[FEAT_8000_0001_ECX
] =
1601 .xlevel
= 0x80000008,
1602 .model_id
= "Common KVM processor"
1607 .vendor
= CPUID_VENDOR_INTEL
,
1611 .features
[FEAT_1_EDX
] =
1613 .features
[FEAT_1_ECX
] =
1615 .xlevel
= 0x80000004,
1616 .model_id
= "QEMU Virtual CPU version " QEMU_HW_VERSION
,
1621 .vendor
= CPUID_VENDOR_INTEL
,
1625 .features
[FEAT_1_EDX
] =
1626 PPRO_FEATURES
| CPUID_VME
|
1627 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_PSE36
,
1628 .features
[FEAT_1_ECX
] =
1630 .features
[FEAT_8000_0001_ECX
] =
1632 .xlevel
= 0x80000008,
1633 .model_id
= "Common 32-bit KVM processor"
1638 .vendor
= CPUID_VENDOR_INTEL
,
1642 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1643 .features
[FEAT_1_EDX
] =
1644 PPRO_FEATURES
| CPUID_VME
|
1645 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_ACPI
|
1647 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
1648 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
1649 .features
[FEAT_1_ECX
] =
1650 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
,
1651 .features
[FEAT_8000_0001_EDX
] =
1653 .xlevel
= 0x80000008,
1654 .model_id
= "Genuine Intel(R) CPU T2600 @ 2.16GHz",
1659 .vendor
= CPUID_VENDOR_INTEL
,
1663 .features
[FEAT_1_EDX
] =
1671 .vendor
= CPUID_VENDOR_INTEL
,
1675 .features
[FEAT_1_EDX
] =
1683 .vendor
= CPUID_VENDOR_INTEL
,
1687 .features
[FEAT_1_EDX
] =
1695 .vendor
= CPUID_VENDOR_INTEL
,
1699 .features
[FEAT_1_EDX
] =
1707 .vendor
= CPUID_VENDOR_AMD
,
1711 .features
[FEAT_1_EDX
] =
1712 PPRO_FEATURES
| CPUID_PSE36
| CPUID_VME
| CPUID_MTRR
|
1714 .features
[FEAT_8000_0001_EDX
] =
1715 CPUID_EXT2_MMXEXT
| CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
,
1716 .xlevel
= 0x80000008,
1717 .model_id
= "QEMU Virtual CPU version " QEMU_HW_VERSION
,
1722 .vendor
= CPUID_VENDOR_INTEL
,
1726 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1727 .features
[FEAT_1_EDX
] =
1729 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_VME
|
1730 CPUID_ACPI
| CPUID_SS
,
1731 /* Some CPUs got no CPUID_SEP */
1732 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
1734 .features
[FEAT_1_ECX
] =
1735 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
1737 .features
[FEAT_8000_0001_EDX
] =
1739 .features
[FEAT_8000_0001_ECX
] =
1741 .xlevel
= 0x80000008,
1742 .model_id
= "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
1747 .vendor
= CPUID_VENDOR_INTEL
,
1751 .features
[FEAT_1_EDX
] =
1752 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1753 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1754 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1755 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1756 CPUID_DE
| CPUID_FP87
,
1757 .features
[FEAT_1_ECX
] =
1758 CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
1759 .features
[FEAT_8000_0001_EDX
] =
1760 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
1761 .features
[FEAT_8000_0001_ECX
] =
1763 .xlevel
= 0x80000008,
1764 .model_id
= "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
1769 .vendor
= CPUID_VENDOR_INTEL
,
1773 .features
[FEAT_1_EDX
] =
1774 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1775 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1776 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1777 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1778 CPUID_DE
| CPUID_FP87
,
1779 .features
[FEAT_1_ECX
] =
1780 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1782 .features
[FEAT_8000_0001_EDX
] =
1783 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
1784 .features
[FEAT_8000_0001_ECX
] =
1786 .xlevel
= 0x80000008,
1787 .model_id
= "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1792 .vendor
= CPUID_VENDOR_INTEL
,
1796 .features
[FEAT_1_EDX
] =
1797 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1798 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1799 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1800 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1801 CPUID_DE
| CPUID_FP87
,
1802 .features
[FEAT_1_ECX
] =
1803 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1804 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
1805 .features
[FEAT_8000_0001_EDX
] =
1806 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
1807 .features
[FEAT_8000_0001_ECX
] =
1809 .xlevel
= 0x80000008,
1810 .model_id
= "Intel Core i7 9xx (Nehalem Class Core i7)",
1813 .name
= "Nehalem-IBRS",
1815 .vendor
= CPUID_VENDOR_INTEL
,
1819 .features
[FEAT_1_EDX
] =
1820 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1821 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1822 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1823 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1824 CPUID_DE
| CPUID_FP87
,
1825 .features
[FEAT_1_ECX
] =
1826 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1827 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
1828 .features
[FEAT_7_0_EDX
] =
1829 CPUID_7_0_EDX_SPEC_CTRL
,
1830 .features
[FEAT_8000_0001_EDX
] =
1831 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
1832 .features
[FEAT_8000_0001_ECX
] =
1834 .xlevel
= 0x80000008,
1835 .model_id
= "Intel Core i7 9xx (Nehalem Core i7, IBRS update)",
1840 .vendor
= CPUID_VENDOR_INTEL
,
1844 .features
[FEAT_1_EDX
] =
1845 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1846 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1847 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1848 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1849 CPUID_DE
| CPUID_FP87
,
1850 .features
[FEAT_1_ECX
] =
1851 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
1852 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1853 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
1854 .features
[FEAT_8000_0001_EDX
] =
1855 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
1856 .features
[FEAT_8000_0001_ECX
] =
1858 .features
[FEAT_6_EAX
] =
1860 .xlevel
= 0x80000008,
1861 .model_id
= "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1864 .name
= "Westmere-IBRS",
1866 .vendor
= CPUID_VENDOR_INTEL
,
1870 .features
[FEAT_1_EDX
] =
1871 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1872 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1873 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1874 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1875 CPUID_DE
| CPUID_FP87
,
1876 .features
[FEAT_1_ECX
] =
1877 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
1878 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1879 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
1880 .features
[FEAT_8000_0001_EDX
] =
1881 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
1882 .features
[FEAT_8000_0001_ECX
] =
1884 .features
[FEAT_7_0_EDX
] =
1885 CPUID_7_0_EDX_SPEC_CTRL
,
1886 .features
[FEAT_6_EAX
] =
1888 .xlevel
= 0x80000008,
1889 .model_id
= "Westmere E56xx/L56xx/X56xx (IBRS update)",
1892 .name
= "SandyBridge",
1894 .vendor
= CPUID_VENDOR_INTEL
,
1898 .features
[FEAT_1_EDX
] =
1899 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1900 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1901 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1902 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1903 CPUID_DE
| CPUID_FP87
,
1904 .features
[FEAT_1_ECX
] =
1905 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1906 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
1907 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1908 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
1910 .features
[FEAT_8000_0001_EDX
] =
1911 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1913 .features
[FEAT_8000_0001_ECX
] =
1915 .features
[FEAT_XSAVE
] =
1916 CPUID_XSAVE_XSAVEOPT
,
1917 .features
[FEAT_6_EAX
] =
1919 .xlevel
= 0x80000008,
1920 .model_id
= "Intel Xeon E312xx (Sandy Bridge)",
1923 .name
= "SandyBridge-IBRS",
1925 .vendor
= CPUID_VENDOR_INTEL
,
1929 .features
[FEAT_1_EDX
] =
1930 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1931 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1932 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1933 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1934 CPUID_DE
| CPUID_FP87
,
1935 .features
[FEAT_1_ECX
] =
1936 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1937 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
1938 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1939 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
1941 .features
[FEAT_8000_0001_EDX
] =
1942 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1944 .features
[FEAT_8000_0001_ECX
] =
1946 .features
[FEAT_7_0_EDX
] =
1947 CPUID_7_0_EDX_SPEC_CTRL
,
1948 .features
[FEAT_XSAVE
] =
1949 CPUID_XSAVE_XSAVEOPT
,
1950 .features
[FEAT_6_EAX
] =
1952 .xlevel
= 0x80000008,
1953 .model_id
= "Intel Xeon E312xx (Sandy Bridge, IBRS update)",
1956 .name
= "IvyBridge",
1958 .vendor
= CPUID_VENDOR_INTEL
,
1962 .features
[FEAT_1_EDX
] =
1963 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1964 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1965 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1966 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1967 CPUID_DE
| CPUID_FP87
,
1968 .features
[FEAT_1_ECX
] =
1969 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1970 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
1971 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1972 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
1973 CPUID_EXT_SSE3
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1974 .features
[FEAT_7_0_EBX
] =
1975 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_SMEP
|
1977 .features
[FEAT_8000_0001_EDX
] =
1978 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1980 .features
[FEAT_8000_0001_ECX
] =
1982 .features
[FEAT_XSAVE
] =
1983 CPUID_XSAVE_XSAVEOPT
,
1984 .features
[FEAT_6_EAX
] =
1986 .xlevel
= 0x80000008,
1987 .model_id
= "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1990 .name
= "IvyBridge-IBRS",
1992 .vendor
= CPUID_VENDOR_INTEL
,
1996 .features
[FEAT_1_EDX
] =
1997 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1998 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1999 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2000 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2001 CPUID_DE
| CPUID_FP87
,
2002 .features
[FEAT_1_ECX
] =
2003 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2004 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
2005 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
2006 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
2007 CPUID_EXT_SSE3
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2008 .features
[FEAT_7_0_EBX
] =
2009 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_SMEP
|
2011 .features
[FEAT_8000_0001_EDX
] =
2012 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
2014 .features
[FEAT_8000_0001_ECX
] =
2016 .features
[FEAT_7_0_EDX
] =
2017 CPUID_7_0_EDX_SPEC_CTRL
,
2018 .features
[FEAT_XSAVE
] =
2019 CPUID_XSAVE_XSAVEOPT
,
2020 .features
[FEAT_6_EAX
] =
2022 .xlevel
= 0x80000008,
2023 .model_id
= "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)",
2026 .name
= "Haswell-noTSX",
2028 .vendor
= CPUID_VENDOR_INTEL
,
2032 .features
[FEAT_1_EDX
] =
2033 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2034 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2035 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2036 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2037 CPUID_DE
| CPUID_FP87
,
2038 .features
[FEAT_1_ECX
] =
2039 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2040 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2041 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2042 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2043 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2044 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2045 .features
[FEAT_8000_0001_EDX
] =
2046 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
2048 .features
[FEAT_8000_0001_ECX
] =
2049 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
,
2050 .features
[FEAT_7_0_EBX
] =
2051 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2052 CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2053 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
,
2054 .features
[FEAT_XSAVE
] =
2055 CPUID_XSAVE_XSAVEOPT
,
2056 .features
[FEAT_6_EAX
] =
2058 .xlevel
= 0x80000008,
2059 .model_id
= "Intel Core Processor (Haswell, no TSX)",
2062 .name
= "Haswell-noTSX-IBRS",
2064 .vendor
= CPUID_VENDOR_INTEL
,
2068 .features
[FEAT_1_EDX
] =
2069 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2070 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2071 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2072 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2073 CPUID_DE
| CPUID_FP87
,
2074 .features
[FEAT_1_ECX
] =
2075 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2076 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2077 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2078 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2079 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2080 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2081 .features
[FEAT_8000_0001_EDX
] =
2082 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
2084 .features
[FEAT_8000_0001_ECX
] =
2085 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
,
2086 .features
[FEAT_7_0_EDX
] =
2087 CPUID_7_0_EDX_SPEC_CTRL
,
2088 .features
[FEAT_7_0_EBX
] =
2089 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2090 CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2091 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
,
2092 .features
[FEAT_XSAVE
] =
2093 CPUID_XSAVE_XSAVEOPT
,
2094 .features
[FEAT_6_EAX
] =
2096 .xlevel
= 0x80000008,
2097 .model_id
= "Intel Core Processor (Haswell, no TSX, IBRS)",
2102 .vendor
= CPUID_VENDOR_INTEL
,
2106 .features
[FEAT_1_EDX
] =
2107 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2108 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2109 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2110 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2111 CPUID_DE
| CPUID_FP87
,
2112 .features
[FEAT_1_ECX
] =
2113 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2114 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2115 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2116 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2117 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2118 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2119 .features
[FEAT_8000_0001_EDX
] =
2120 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
2122 .features
[FEAT_8000_0001_ECX
] =
2123 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
,
2124 .features
[FEAT_7_0_EBX
] =
2125 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2126 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2127 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
2129 .features
[FEAT_XSAVE
] =
2130 CPUID_XSAVE_XSAVEOPT
,
2131 .features
[FEAT_6_EAX
] =
2133 .xlevel
= 0x80000008,
2134 .model_id
= "Intel Core Processor (Haswell)",
2137 .name
= "Haswell-IBRS",
2139 .vendor
= CPUID_VENDOR_INTEL
,
2143 .features
[FEAT_1_EDX
] =
2144 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2145 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2146 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2147 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2148 CPUID_DE
| CPUID_FP87
,
2149 .features
[FEAT_1_ECX
] =
2150 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2151 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2152 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2153 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2154 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2155 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2156 .features
[FEAT_8000_0001_EDX
] =
2157 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
2159 .features
[FEAT_8000_0001_ECX
] =
2160 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
,
2161 .features
[FEAT_7_0_EDX
] =
2162 CPUID_7_0_EDX_SPEC_CTRL
,
2163 .features
[FEAT_7_0_EBX
] =
2164 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2165 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2166 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
2168 .features
[FEAT_XSAVE
] =
2169 CPUID_XSAVE_XSAVEOPT
,
2170 .features
[FEAT_6_EAX
] =
2172 .xlevel
= 0x80000008,
2173 .model_id
= "Intel Core Processor (Haswell, IBRS)",
2176 .name
= "Broadwell-noTSX",
2178 .vendor
= CPUID_VENDOR_INTEL
,
2182 .features
[FEAT_1_EDX
] =
2183 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2184 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2185 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2186 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2187 CPUID_DE
| CPUID_FP87
,
2188 .features
[FEAT_1_ECX
] =
2189 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2190 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2191 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2192 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2193 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2194 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2195 .features
[FEAT_8000_0001_EDX
] =
2196 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
2198 .features
[FEAT_8000_0001_ECX
] =
2199 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
2200 .features
[FEAT_7_0_EBX
] =
2201 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2202 CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2203 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
2204 CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
2206 .features
[FEAT_XSAVE
] =
2207 CPUID_XSAVE_XSAVEOPT
,
2208 .features
[FEAT_6_EAX
] =
2210 .xlevel
= 0x80000008,
2211 .model_id
= "Intel Core Processor (Broadwell, no TSX)",
2214 .name
= "Broadwell-noTSX-IBRS",
2216 .vendor
= CPUID_VENDOR_INTEL
,
2220 .features
[FEAT_1_EDX
] =
2221 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2222 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2223 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2224 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2225 CPUID_DE
| CPUID_FP87
,
2226 .features
[FEAT_1_ECX
] =
2227 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2228 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2229 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2230 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2231 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2232 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2233 .features
[FEAT_8000_0001_EDX
] =
2234 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
2236 .features
[FEAT_8000_0001_ECX
] =
2237 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
2238 .features
[FEAT_7_0_EDX
] =
2239 CPUID_7_0_EDX_SPEC_CTRL
,
2240 .features
[FEAT_7_0_EBX
] =
2241 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2242 CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2243 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
2244 CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
2246 .features
[FEAT_XSAVE
] =
2247 CPUID_XSAVE_XSAVEOPT
,
2248 .features
[FEAT_6_EAX
] =
2250 .xlevel
= 0x80000008,
2251 .model_id
= "Intel Core Processor (Broadwell, no TSX, IBRS)",
2254 .name
= "Broadwell",
2256 .vendor
= CPUID_VENDOR_INTEL
,
2260 .features
[FEAT_1_EDX
] =
2261 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2262 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2263 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2264 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2265 CPUID_DE
| CPUID_FP87
,
2266 .features
[FEAT_1_ECX
] =
2267 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2268 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2269 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2270 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2271 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2272 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2273 .features
[FEAT_8000_0001_EDX
] =
2274 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
2276 .features
[FEAT_8000_0001_ECX
] =
2277 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
2278 .features
[FEAT_7_0_EBX
] =
2279 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2280 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2281 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
2282 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
2284 .features
[FEAT_XSAVE
] =
2285 CPUID_XSAVE_XSAVEOPT
,
2286 .features
[FEAT_6_EAX
] =
2288 .xlevel
= 0x80000008,
2289 .model_id
= "Intel Core Processor (Broadwell)",
2292 .name
= "Broadwell-IBRS",
2294 .vendor
= CPUID_VENDOR_INTEL
,
2298 .features
[FEAT_1_EDX
] =
2299 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2300 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2301 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2302 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2303 CPUID_DE
| CPUID_FP87
,
2304 .features
[FEAT_1_ECX
] =
2305 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2306 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2307 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2308 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2309 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2310 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2311 .features
[FEAT_8000_0001_EDX
] =
2312 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
2314 .features
[FEAT_8000_0001_ECX
] =
2315 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
2316 .features
[FEAT_7_0_EDX
] =
2317 CPUID_7_0_EDX_SPEC_CTRL
,
2318 .features
[FEAT_7_0_EBX
] =
2319 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2320 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2321 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
2322 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
2324 .features
[FEAT_XSAVE
] =
2325 CPUID_XSAVE_XSAVEOPT
,
2326 .features
[FEAT_6_EAX
] =
2328 .xlevel
= 0x80000008,
2329 .model_id
= "Intel Core Processor (Broadwell, IBRS)",
2332 .name
= "Skylake-Client",
2334 .vendor
= CPUID_VENDOR_INTEL
,
2338 .features
[FEAT_1_EDX
] =
2339 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2340 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2341 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2342 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2343 CPUID_DE
| CPUID_FP87
,
2344 .features
[FEAT_1_ECX
] =
2345 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2346 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2347 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2348 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2349 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2350 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2351 .features
[FEAT_8000_0001_EDX
] =
2352 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
2354 .features
[FEAT_8000_0001_ECX
] =
2355 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
2356 .features
[FEAT_7_0_EBX
] =
2357 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2358 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2359 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
2360 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
2362 /* Missing: XSAVES (not supported by some Linux versions,
2363 * including v4.1 to v4.12).
2364 * KVM doesn't yet expose any XSAVES state save component,
2365 * and the only one defined in Skylake (processor tracing)
2366 * probably will block migration anyway.
2368 .features
[FEAT_XSAVE
] =
2369 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
2370 CPUID_XSAVE_XGETBV1
,
2371 .features
[FEAT_6_EAX
] =
2373 .xlevel
= 0x80000008,
2374 .model_id
= "Intel Core Processor (Skylake)",
2377 .name
= "Skylake-Client-IBRS",
2379 .vendor
= CPUID_VENDOR_INTEL
,
2383 .features
[FEAT_1_EDX
] =
2384 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2385 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2386 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2387 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2388 CPUID_DE
| CPUID_FP87
,
2389 .features
[FEAT_1_ECX
] =
2390 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2391 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2392 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2393 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2394 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2395 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2396 .features
[FEAT_8000_0001_EDX
] =
2397 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
2399 .features
[FEAT_8000_0001_ECX
] =
2400 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
2401 .features
[FEAT_7_0_EDX
] =
2402 CPUID_7_0_EDX_SPEC_CTRL
,
2403 .features
[FEAT_7_0_EBX
] =
2404 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2405 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2406 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
2407 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
2409 /* Missing: XSAVES (not supported by some Linux versions,
2410 * including v4.1 to v4.12).
2411 * KVM doesn't yet expose any XSAVES state save component,
2412 * and the only one defined in Skylake (processor tracing)
2413 * probably will block migration anyway.
2415 .features
[FEAT_XSAVE
] =
2416 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
2417 CPUID_XSAVE_XGETBV1
,
2418 .features
[FEAT_6_EAX
] =
2420 .xlevel
= 0x80000008,
2421 .model_id
= "Intel Core Processor (Skylake, IBRS)",
2424 .name
= "Skylake-Server",
2426 .vendor
= CPUID_VENDOR_INTEL
,
2430 .features
[FEAT_1_EDX
] =
2431 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2432 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2433 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2434 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2435 CPUID_DE
| CPUID_FP87
,
2436 .features
[FEAT_1_ECX
] =
2437 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2438 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2439 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2440 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2441 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2442 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2443 .features
[FEAT_8000_0001_EDX
] =
2444 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
|
2445 CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
2446 .features
[FEAT_8000_0001_ECX
] =
2447 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
2448 .features
[FEAT_7_0_EBX
] =
2449 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2450 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2451 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
2452 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
2453 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLWB
|
2454 CPUID_7_0_EBX_AVX512F
| CPUID_7_0_EBX_AVX512DQ
|
2455 CPUID_7_0_EBX_AVX512BW
| CPUID_7_0_EBX_AVX512CD
|
2456 CPUID_7_0_EBX_AVX512VL
| CPUID_7_0_EBX_CLFLUSHOPT
,
2457 .features
[FEAT_7_0_ECX
] =
2459 /* Missing: XSAVES (not supported by some Linux versions,
2460 * including v4.1 to v4.12).
2461 * KVM doesn't yet expose any XSAVES state save component,
2462 * and the only one defined in Skylake (processor tracing)
2463 * probably will block migration anyway.
2465 .features
[FEAT_XSAVE
] =
2466 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
2467 CPUID_XSAVE_XGETBV1
,
2468 .features
[FEAT_6_EAX
] =
2470 .xlevel
= 0x80000008,
2471 .model_id
= "Intel Xeon Processor (Skylake)",
2474 .name
= "Skylake-Server-IBRS",
2476 .vendor
= CPUID_VENDOR_INTEL
,
2480 .features
[FEAT_1_EDX
] =
2481 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2482 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2483 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2484 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2485 CPUID_DE
| CPUID_FP87
,
2486 .features
[FEAT_1_ECX
] =
2487 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2488 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2489 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2490 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2491 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2492 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2493 .features
[FEAT_8000_0001_EDX
] =
2494 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
|
2495 CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
2496 .features
[FEAT_8000_0001_ECX
] =
2497 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
2498 .features
[FEAT_7_0_EDX
] =
2499 CPUID_7_0_EDX_SPEC_CTRL
,
2500 .features
[FEAT_7_0_EBX
] =
2501 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2502 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2503 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
2504 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
2505 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLWB
|
2506 CPUID_7_0_EBX_AVX512F
| CPUID_7_0_EBX_AVX512DQ
|
2507 CPUID_7_0_EBX_AVX512BW
| CPUID_7_0_EBX_AVX512CD
|
2508 CPUID_7_0_EBX_AVX512VL
,
2509 .features
[FEAT_7_0_ECX
] =
2511 /* Missing: XSAVES (not supported by some Linux versions,
2512 * including v4.1 to v4.12).
2513 * KVM doesn't yet expose any XSAVES state save component,
2514 * and the only one defined in Skylake (processor tracing)
2515 * probably will block migration anyway.
2517 .features
[FEAT_XSAVE
] =
2518 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
2519 CPUID_XSAVE_XGETBV1
,
2520 .features
[FEAT_6_EAX
] =
2522 .xlevel
= 0x80000008,
2523 .model_id
= "Intel Xeon Processor (Skylake, IBRS)",
2526 .name
= "Cascadelake-Server",
2528 .vendor
= CPUID_VENDOR_INTEL
,
2532 .features
[FEAT_1_EDX
] =
2533 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2534 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2535 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2536 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2537 CPUID_DE
| CPUID_FP87
,
2538 .features
[FEAT_1_ECX
] =
2539 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2540 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2541 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2542 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2543 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2544 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2545 .features
[FEAT_8000_0001_EDX
] =
2546 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
|
2547 CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
2548 .features
[FEAT_8000_0001_ECX
] =
2549 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
2550 .features
[FEAT_7_0_EBX
] =
2551 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2552 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2553 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
2554 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
2555 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLWB
|
2556 CPUID_7_0_EBX_AVX512F
| CPUID_7_0_EBX_AVX512DQ
|
2557 CPUID_7_0_EBX_AVX512BW
| CPUID_7_0_EBX_AVX512CD
|
2558 CPUID_7_0_EBX_AVX512VL
| CPUID_7_0_EBX_CLFLUSHOPT
,
2559 .features
[FEAT_7_0_ECX
] =
2561 CPUID_7_0_ECX_AVX512VNNI
,
2562 .features
[FEAT_7_0_EDX
] =
2563 CPUID_7_0_EDX_SPEC_CTRL
| CPUID_7_0_EDX_SPEC_CTRL_SSBD
,
2564 /* Missing: XSAVES (not supported by some Linux versions,
2565 * including v4.1 to v4.12).
2566 * KVM doesn't yet expose any XSAVES state save component,
2567 * and the only one defined in Skylake (processor tracing)
2568 * probably will block migration anyway.
2570 .features
[FEAT_XSAVE
] =
2571 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
2572 CPUID_XSAVE_XGETBV1
,
2573 .features
[FEAT_6_EAX
] =
2575 .xlevel
= 0x80000008,
2576 .model_id
= "Intel Xeon Processor (Cascadelake)",
2579 .name
= "Icelake-Client",
2581 .vendor
= CPUID_VENDOR_INTEL
,
2585 .features
[FEAT_1_EDX
] =
2586 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2587 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2588 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2589 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2590 CPUID_DE
| CPUID_FP87
,
2591 .features
[FEAT_1_ECX
] =
2592 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2593 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2594 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2595 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2596 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2597 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2598 .features
[FEAT_8000_0001_EDX
] =
2599 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
2601 .features
[FEAT_8000_0001_ECX
] =
2602 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
2603 .features
[FEAT_8000_0008_EBX
] =
2604 CPUID_8000_0008_EBX_WBNOINVD
,
2605 .features
[FEAT_7_0_EBX
] =
2606 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2607 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2608 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
2609 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
2611 .features
[FEAT_7_0_ECX
] =
2612 CPUID_7_0_ECX_VBMI
| CPUID_7_0_ECX_UMIP
| CPUID_7_0_ECX_PKU
|
2613 CPUID_7_0_ECX_VBMI2
| CPUID_7_0_ECX_GFNI
|
2614 CPUID_7_0_ECX_VAES
| CPUID_7_0_ECX_VPCLMULQDQ
|
2615 CPUID_7_0_ECX_AVX512VNNI
| CPUID_7_0_ECX_AVX512BITALG
|
2616 CPUID_7_0_ECX_AVX512_VPOPCNTDQ
,
2617 .features
[FEAT_7_0_EDX
] =
2618 CPUID_7_0_EDX_SPEC_CTRL
| CPUID_7_0_EDX_SPEC_CTRL_SSBD
,
2619 /* Missing: XSAVES (not supported by some Linux versions,
2620 * including v4.1 to v4.12).
2621 * KVM doesn't yet expose any XSAVES state save component,
2622 * and the only one defined in Skylake (processor tracing)
2623 * probably will block migration anyway.
2625 .features
[FEAT_XSAVE
] =
2626 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
2627 CPUID_XSAVE_XGETBV1
,
2628 .features
[FEAT_6_EAX
] =
2630 .xlevel
= 0x80000008,
2631 .model_id
= "Intel Core Processor (Icelake)",
2634 .name
= "Icelake-Server",
2636 .vendor
= CPUID_VENDOR_INTEL
,
2640 .features
[FEAT_1_EDX
] =
2641 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2642 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2643 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2644 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2645 CPUID_DE
| CPUID_FP87
,
2646 .features
[FEAT_1_ECX
] =
2647 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2648 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2649 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2650 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2651 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2652 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2653 .features
[FEAT_8000_0001_EDX
] =
2654 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
|
2655 CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
2656 .features
[FEAT_8000_0001_ECX
] =
2657 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
2658 .features
[FEAT_8000_0008_EBX
] =
2659 CPUID_8000_0008_EBX_WBNOINVD
,
2660 .features
[FEAT_7_0_EBX
] =
2661 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2662 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2663 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
2664 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
2665 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLWB
|
2666 CPUID_7_0_EBX_AVX512F
| CPUID_7_0_EBX_AVX512DQ
|
2667 CPUID_7_0_EBX_AVX512BW
| CPUID_7_0_EBX_AVX512CD
|
2668 CPUID_7_0_EBX_AVX512VL
| CPUID_7_0_EBX_CLFLUSHOPT
,
2669 .features
[FEAT_7_0_ECX
] =
2670 CPUID_7_0_ECX_VBMI
| CPUID_7_0_ECX_UMIP
| CPUID_7_0_ECX_PKU
|
2671 CPUID_7_0_ECX_VBMI2
| CPUID_7_0_ECX_GFNI
|
2672 CPUID_7_0_ECX_VAES
| CPUID_7_0_ECX_VPCLMULQDQ
|
2673 CPUID_7_0_ECX_AVX512VNNI
| CPUID_7_0_ECX_AVX512BITALG
|
2674 CPUID_7_0_ECX_AVX512_VPOPCNTDQ
| CPUID_7_0_ECX_LA57
,
2675 .features
[FEAT_7_0_EDX
] =
2676 CPUID_7_0_EDX_SPEC_CTRL
| CPUID_7_0_EDX_SPEC_CTRL_SSBD
,
2677 /* Missing: XSAVES (not supported by some Linux versions,
2678 * including v4.1 to v4.12).
2679 * KVM doesn't yet expose any XSAVES state save component,
2680 * and the only one defined in Skylake (processor tracing)
2681 * probably will block migration anyway.
2683 .features
[FEAT_XSAVE
] =
2684 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
2685 CPUID_XSAVE_XGETBV1
,
2686 .features
[FEAT_6_EAX
] =
2688 .xlevel
= 0x80000008,
2689 .model_id
= "Intel Xeon Processor (Icelake)",
2692 .name
= "SnowRidge-Server",
2694 .vendor
= CPUID_VENDOR_INTEL
,
2698 .features
[FEAT_1_EDX
] =
2699 /* missing: CPUID_PN CPUID_IA64 */
2700 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
2701 CPUID_FP87
| CPUID_VME
| CPUID_DE
| CPUID_PSE
|
2702 CPUID_TSC
| CPUID_MSR
| CPUID_PAE
| CPUID_MCE
|
2703 CPUID_CX8
| CPUID_APIC
| CPUID_SEP
|
2704 CPUID_MTRR
| CPUID_PGE
| CPUID_MCA
| CPUID_CMOV
|
2705 CPUID_PAT
| CPUID_PSE36
| CPUID_CLFLUSH
|
2707 CPUID_FXSR
| CPUID_SSE
| CPUID_SSE2
,
2708 .features
[FEAT_1_ECX
] =
2709 CPUID_EXT_SSE3
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_MONITOR
|
2714 CPUID_EXT_SSE42
| CPUID_EXT_X2APIC
| CPUID_EXT_MOVBE
|
2716 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_AES
| CPUID_EXT_XSAVE
|
2718 .features
[FEAT_8000_0001_EDX
] =
2719 CPUID_EXT2_SYSCALL
|
2721 CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
|
2723 .features
[FEAT_8000_0001_ECX
] =
2724 CPUID_EXT3_LAHF_LM
|
2725 CPUID_EXT3_3DNOWPREFETCH
,
2726 .features
[FEAT_7_0_EBX
] =
2727 CPUID_7_0_EBX_FSGSBASE
|
2728 CPUID_7_0_EBX_SMEP
|
2729 CPUID_7_0_EBX_ERMS
|
2730 CPUID_7_0_EBX_MPX
| /* missing bits 13, 15 */
2731 CPUID_7_0_EBX_RDSEED
|
2732 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLFLUSHOPT
|
2733 CPUID_7_0_EBX_CLWB
|
2734 CPUID_7_0_EBX_SHA_NI
,
2735 .features
[FEAT_7_0_ECX
] =
2736 CPUID_7_0_ECX_UMIP
|
2738 CPUID_7_0_ECX_GFNI
|
2739 CPUID_7_0_ECX_MOVDIRI
| CPUID_7_0_ECX_CLDEMOTE
|
2740 CPUID_7_0_ECX_MOVDIR64B
,
2741 .features
[FEAT_7_0_EDX
] =
2742 CPUID_7_0_EDX_SPEC_CTRL
|
2743 CPUID_7_0_EDX_ARCH_CAPABILITIES
| CPUID_7_0_EDX_SPEC_CTRL_SSBD
|
2744 CPUID_7_0_EDX_CORE_CAPABILITY
,
2745 .features
[FEAT_CORE_CAPABILITY
] =
2746 MSR_CORE_CAP_SPLIT_LOCK_DETECT
,
2748 * Missing: XSAVES (not supported by some Linux versions,
2749 * including v4.1 to v4.12).
2750 * KVM doesn't yet expose any XSAVES state save component,
2751 * and the only one defined in Skylake (processor tracing)
2752 * probably will block migration anyway.
2754 .features
[FEAT_XSAVE
] =
2755 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
2756 CPUID_XSAVE_XGETBV1
,
2757 .features
[FEAT_6_EAX
] =
2759 .xlevel
= 0x80000008,
2760 .model_id
= "Intel Atom Processor (SnowRidge)",
2763 .name
= "KnightsMill",
2765 .vendor
= CPUID_VENDOR_INTEL
,
2769 .features
[FEAT_1_EDX
] =
2770 CPUID_VME
| CPUID_SS
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
|
2771 CPUID_MMX
| CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
|
2772 CPUID_MCA
| CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
|
2773 CPUID_CX8
| CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
|
2774 CPUID_PSE
| CPUID_DE
| CPUID_FP87
,
2775 .features
[FEAT_1_ECX
] =
2776 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2777 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2778 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2779 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2780 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2781 CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2782 .features
[FEAT_8000_0001_EDX
] =
2783 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
|
2784 CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
2785 .features
[FEAT_8000_0001_ECX
] =
2786 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
2787 .features
[FEAT_7_0_EBX
] =
2788 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
| CPUID_7_0_EBX_AVX2
|
2789 CPUID_7_0_EBX_SMEP
| CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
|
2790 CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
| CPUID_7_0_EBX_AVX512F
|
2791 CPUID_7_0_EBX_AVX512CD
| CPUID_7_0_EBX_AVX512PF
|
2792 CPUID_7_0_EBX_AVX512ER
,
2793 .features
[FEAT_7_0_ECX
] =
2794 CPUID_7_0_ECX_AVX512_VPOPCNTDQ
,
2795 .features
[FEAT_7_0_EDX
] =
2796 CPUID_7_0_EDX_AVX512_4VNNIW
| CPUID_7_0_EDX_AVX512_4FMAPS
,
2797 .features
[FEAT_XSAVE
] =
2798 CPUID_XSAVE_XSAVEOPT
,
2799 .features
[FEAT_6_EAX
] =
2801 .xlevel
= 0x80000008,
2802 .model_id
= "Intel Xeon Phi Processor (Knights Mill)",
2805 .name
= "Opteron_G1",
2807 .vendor
= CPUID_VENDOR_AMD
,
2811 .features
[FEAT_1_EDX
] =
2812 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2813 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2814 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2815 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2816 CPUID_DE
| CPUID_FP87
,
2817 .features
[FEAT_1_ECX
] =
2819 .features
[FEAT_8000_0001_EDX
] =
2820 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
2821 .xlevel
= 0x80000008,
2822 .model_id
= "AMD Opteron 240 (Gen 1 Class Opteron)",
2825 .name
= "Opteron_G2",
2827 .vendor
= CPUID_VENDOR_AMD
,
2831 .features
[FEAT_1_EDX
] =
2832 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2833 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2834 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2835 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2836 CPUID_DE
| CPUID_FP87
,
2837 .features
[FEAT_1_ECX
] =
2838 CPUID_EXT_CX16
| CPUID_EXT_SSE3
,
2839 .features
[FEAT_8000_0001_EDX
] =
2840 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
2841 .features
[FEAT_8000_0001_ECX
] =
2842 CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
2843 .xlevel
= 0x80000008,
2844 .model_id
= "AMD Opteron 22xx (Gen 2 Class Opteron)",
2847 .name
= "Opteron_G3",
2849 .vendor
= CPUID_VENDOR_AMD
,
2853 .features
[FEAT_1_EDX
] =
2854 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2855 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2856 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2857 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2858 CPUID_DE
| CPUID_FP87
,
2859 .features
[FEAT_1_ECX
] =
2860 CPUID_EXT_POPCNT
| CPUID_EXT_CX16
| CPUID_EXT_MONITOR
|
2862 .features
[FEAT_8000_0001_EDX
] =
2863 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
|
2865 .features
[FEAT_8000_0001_ECX
] =
2866 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
|
2867 CPUID_EXT3_ABM
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
2868 .xlevel
= 0x80000008,
2869 .model_id
= "AMD Opteron 23xx (Gen 3 Class Opteron)",
2872 .name
= "Opteron_G4",
2874 .vendor
= CPUID_VENDOR_AMD
,
2878 .features
[FEAT_1_EDX
] =
2879 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2880 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2881 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2882 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2883 CPUID_DE
| CPUID_FP87
,
2884 .features
[FEAT_1_ECX
] =
2885 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2886 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
2887 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
2889 .features
[FEAT_8000_0001_EDX
] =
2890 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_NX
|
2891 CPUID_EXT2_SYSCALL
| CPUID_EXT2_RDTSCP
,
2892 .features
[FEAT_8000_0001_ECX
] =
2893 CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
2894 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
2895 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
2897 .features
[FEAT_SVM
] =
2898 CPUID_SVM_NPT
| CPUID_SVM_NRIPSAVE
,
2900 .xlevel
= 0x8000001A,
2901 .model_id
= "AMD Opteron 62xx class CPU",
2904 .name
= "Opteron_G5",
2906 .vendor
= CPUID_VENDOR_AMD
,
2910 .features
[FEAT_1_EDX
] =
2911 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2912 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2913 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2914 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2915 CPUID_DE
| CPUID_FP87
,
2916 .features
[FEAT_1_ECX
] =
2917 CPUID_EXT_F16C
| CPUID_EXT_AVX
| CPUID_EXT_XSAVE
|
2918 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
2919 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_FMA
|
2920 CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
2921 .features
[FEAT_8000_0001_EDX
] =
2922 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_NX
|
2923 CPUID_EXT2_SYSCALL
| CPUID_EXT2_RDTSCP
,
2924 .features
[FEAT_8000_0001_ECX
] =
2925 CPUID_EXT3_TBM
| CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
2926 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
2927 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
2929 .features
[FEAT_SVM
] =
2930 CPUID_SVM_NPT
| CPUID_SVM_NRIPSAVE
,
2932 .xlevel
= 0x8000001A,
2933 .model_id
= "AMD Opteron 63xx class CPU",
2938 .vendor
= CPUID_VENDOR_AMD
,
2942 .features
[FEAT_1_EDX
] =
2943 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
| CPUID_CLFLUSH
|
2944 CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
| CPUID_PGE
|
2945 CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
| CPUID_MCE
|
2946 CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
| CPUID_DE
|
2947 CPUID_VME
| CPUID_FP87
,
2948 .features
[FEAT_1_ECX
] =
2949 CPUID_EXT_RDRAND
| CPUID_EXT_F16C
| CPUID_EXT_AVX
|
2950 CPUID_EXT_XSAVE
| CPUID_EXT_AES
| CPUID_EXT_POPCNT
|
2951 CPUID_EXT_MOVBE
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
2952 CPUID_EXT_CX16
| CPUID_EXT_FMA
| CPUID_EXT_SSSE3
|
2953 CPUID_EXT_MONITOR
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
2954 .features
[FEAT_8000_0001_EDX
] =
2955 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_PDPE1GB
|
2956 CPUID_EXT2_FFXSR
| CPUID_EXT2_MMXEXT
| CPUID_EXT2_NX
|
2958 .features
[FEAT_8000_0001_ECX
] =
2959 CPUID_EXT3_OSVW
| CPUID_EXT3_3DNOWPREFETCH
|
2960 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
|
2961 CPUID_EXT3_CR8LEG
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
|
2963 .features
[FEAT_7_0_EBX
] =
2964 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
| CPUID_7_0_EBX_AVX2
|
2965 CPUID_7_0_EBX_SMEP
| CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_RDSEED
|
2966 CPUID_7_0_EBX_ADX
| CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLFLUSHOPT
|
2967 CPUID_7_0_EBX_SHA_NI
,
2968 /* Missing: XSAVES (not supported by some Linux versions,
2969 * including v4.1 to v4.12).
2970 * KVM doesn't yet expose any XSAVES state save component.
2972 .features
[FEAT_XSAVE
] =
2973 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
2974 CPUID_XSAVE_XGETBV1
,
2975 .features
[FEAT_6_EAX
] =
2977 .features
[FEAT_SVM
] =
2978 CPUID_SVM_NPT
| CPUID_SVM_NRIPSAVE
,
2979 .xlevel
= 0x8000001E,
2980 .model_id
= "AMD EPYC Processor",
2981 .cache_info
= &epyc_cache_info
,
2984 .name
= "EPYC-IBPB",
2986 .vendor
= CPUID_VENDOR_AMD
,
2990 .features
[FEAT_1_EDX
] =
2991 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
| CPUID_CLFLUSH
|
2992 CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
| CPUID_PGE
|
2993 CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
| CPUID_MCE
|
2994 CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
| CPUID_DE
|
2995 CPUID_VME
| CPUID_FP87
,
2996 .features
[FEAT_1_ECX
] =
2997 CPUID_EXT_RDRAND
| CPUID_EXT_F16C
| CPUID_EXT_AVX
|
2998 CPUID_EXT_XSAVE
| CPUID_EXT_AES
| CPUID_EXT_POPCNT
|
2999 CPUID_EXT_MOVBE
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
3000 CPUID_EXT_CX16
| CPUID_EXT_FMA
| CPUID_EXT_SSSE3
|
3001 CPUID_EXT_MONITOR
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
3002 .features
[FEAT_8000_0001_EDX
] =
3003 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_PDPE1GB
|
3004 CPUID_EXT2_FFXSR
| CPUID_EXT2_MMXEXT
| CPUID_EXT2_NX
|
3006 .features
[FEAT_8000_0001_ECX
] =
3007 CPUID_EXT3_OSVW
| CPUID_EXT3_3DNOWPREFETCH
|
3008 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
|
3009 CPUID_EXT3_CR8LEG
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
|
3011 .features
[FEAT_8000_0008_EBX
] =
3012 CPUID_8000_0008_EBX_IBPB
,
3013 .features
[FEAT_7_0_EBX
] =
3014 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
| CPUID_7_0_EBX_AVX2
|
3015 CPUID_7_0_EBX_SMEP
| CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_RDSEED
|
3016 CPUID_7_0_EBX_ADX
| CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLFLUSHOPT
|
3017 CPUID_7_0_EBX_SHA_NI
,
3018 /* Missing: XSAVES (not supported by some Linux versions,
3019 * including v4.1 to v4.12).
3020 * KVM doesn't yet expose any XSAVES state save component.
3022 .features
[FEAT_XSAVE
] =
3023 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
3024 CPUID_XSAVE_XGETBV1
,
3025 .features
[FEAT_6_EAX
] =
3027 .features
[FEAT_SVM
] =
3028 CPUID_SVM_NPT
| CPUID_SVM_NRIPSAVE
,
3029 .xlevel
= 0x8000001E,
3030 .model_id
= "AMD EPYC Processor (with IBPB)",
3031 .cache_info
= &epyc_cache_info
,
3036 .vendor
= CPUID_VENDOR_HYGON
,
3040 .features
[FEAT_1_EDX
] =
3041 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
| CPUID_CLFLUSH
|
3042 CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
| CPUID_PGE
|
3043 CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
| CPUID_MCE
|
3044 CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
| CPUID_DE
|
3045 CPUID_VME
| CPUID_FP87
,
3046 .features
[FEAT_1_ECX
] =
3047 CPUID_EXT_RDRAND
| CPUID_EXT_F16C
| CPUID_EXT_AVX
|
3048 CPUID_EXT_XSAVE
| CPUID_EXT_POPCNT
|
3049 CPUID_EXT_MOVBE
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
3050 CPUID_EXT_CX16
| CPUID_EXT_FMA
| CPUID_EXT_SSSE3
|
3051 CPUID_EXT_MONITOR
| CPUID_EXT_SSE3
,
3052 .features
[FEAT_8000_0001_EDX
] =
3053 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_PDPE1GB
|
3054 CPUID_EXT2_FFXSR
| CPUID_EXT2_MMXEXT
| CPUID_EXT2_NX
|
3056 .features
[FEAT_8000_0001_ECX
] =
3057 CPUID_EXT3_OSVW
| CPUID_EXT3_3DNOWPREFETCH
|
3058 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
|
3059 CPUID_EXT3_CR8LEG
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
|
3061 .features
[FEAT_8000_0008_EBX
] =
3062 CPUID_8000_0008_EBX_IBPB
,
3063 .features
[FEAT_7_0_EBX
] =
3064 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
| CPUID_7_0_EBX_AVX2
|
3065 CPUID_7_0_EBX_SMEP
| CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_RDSEED
|
3066 CPUID_7_0_EBX_ADX
| CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLFLUSHOPT
,
3068 * Missing: XSAVES (not supported by some Linux versions,
3069 * including v4.1 to v4.12).
3070 * KVM doesn't yet expose any XSAVES state save component.
3072 .features
[FEAT_XSAVE
] =
3073 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
3074 CPUID_XSAVE_XGETBV1
,
3075 .features
[FEAT_6_EAX
] =
3077 .features
[FEAT_SVM
] =
3078 CPUID_SVM_NPT
| CPUID_SVM_NRIPSAVE
,
3079 .xlevel
= 0x8000001E,
3080 .model_id
= "Hygon Dhyana Processor",
3081 .cache_info
= &epyc_cache_info
,
3085 typedef struct PropValue
{
3086 const char *prop
, *value
;
3089 /* KVM-specific features that are automatically added/removed
3090 * from all CPU models when KVM is enabled.
3092 static PropValue kvm_default_props
[] = {
3093 { "kvmclock", "on" },
3094 { "kvm-nopiodelay", "on" },
3095 { "kvm-asyncpf", "on" },
3096 { "kvm-steal-time", "on" },
3097 { "kvm-pv-eoi", "on" },
3098 { "kvmclock-stable-bit", "on" },
3101 { "monitor", "off" },
3106 /* TCG-specific defaults that override all CPU models when using TCG
3108 static PropValue tcg_default_props
[] = {
3114 void x86_cpu_change_kvm_default(const char *prop
, const char *value
)
3117 for (pv
= kvm_default_props
; pv
->prop
; pv
++) {
3118 if (!strcmp(pv
->prop
, prop
)) {
3124 /* It is valid to call this function only for properties that
3125 * are already present in the kvm_default_props table.
3130 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w
,
3131 bool migratable_only
);
3133 static bool lmce_supported(void)
3135 uint64_t mce_cap
= 0;
3138 if (kvm_ioctl(kvm_state
, KVM_X86_GET_MCE_CAP_SUPPORTED
, &mce_cap
) < 0) {
3143 return !!(mce_cap
& MCG_LMCE_P
);
3146 #define CPUID_MODEL_ID_SZ 48
3149 * cpu_x86_fill_model_id:
3150 * Get CPUID model ID string from host CPU.
3152 * @str should have at least CPUID_MODEL_ID_SZ bytes
3154 * The function does NOT add a null terminator to the string
3157 static int cpu_x86_fill_model_id(char *str
)
3159 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
3162 for (i
= 0; i
< 3; i
++) {
3163 host_cpuid(0x80000002 + i
, 0, &eax
, &ebx
, &ecx
, &edx
);
3164 memcpy(str
+ i
* 16 + 0, &eax
, 4);
3165 memcpy(str
+ i
* 16 + 4, &ebx
, 4);
3166 memcpy(str
+ i
* 16 + 8, &ecx
, 4);
3167 memcpy(str
+ i
* 16 + 12, &edx
, 4);
3172 static Property max_x86_cpu_properties
[] = {
3173 DEFINE_PROP_BOOL("migratable", X86CPU
, migratable
, true),
3174 DEFINE_PROP_BOOL("host-cache-info", X86CPU
, cache_info_passthrough
, false),
3175 DEFINE_PROP_END_OF_LIST()
3178 static void max_x86_cpu_class_init(ObjectClass
*oc
, void *data
)
3180 DeviceClass
*dc
= DEVICE_CLASS(oc
);
3181 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
3185 xcc
->model_description
=
3186 "Enables all features supported by the accelerator in the current host";
3188 dc
->props
= max_x86_cpu_properties
;
3191 static void x86_cpu_load_def(X86CPU
*cpu
, X86CPUDefinition
*def
, Error
**errp
);
3193 static void max_x86_cpu_initfn(Object
*obj
)
3195 X86CPU
*cpu
= X86_CPU(obj
);
3196 CPUX86State
*env
= &cpu
->env
;
3197 KVMState
*s
= kvm_state
;
3199 /* We can't fill the features array here because we don't know yet if
3200 * "migratable" is true or false.
3202 cpu
->max_features
= true;
3204 if (accel_uses_host_cpuid()) {
3205 char vendor
[CPUID_VENDOR_SZ
+ 1] = { 0 };
3206 char model_id
[CPUID_MODEL_ID_SZ
+ 1] = { 0 };
3207 int family
, model
, stepping
;
3209 host_vendor_fms(vendor
, &family
, &model
, &stepping
);
3210 cpu_x86_fill_model_id(model_id
);
3212 object_property_set_str(OBJECT(cpu
), vendor
, "vendor", &error_abort
);
3213 object_property_set_int(OBJECT(cpu
), family
, "family", &error_abort
);
3214 object_property_set_int(OBJECT(cpu
), model
, "model", &error_abort
);
3215 object_property_set_int(OBJECT(cpu
), stepping
, "stepping",
3217 object_property_set_str(OBJECT(cpu
), model_id
, "model-id",
3220 if (kvm_enabled()) {
3221 env
->cpuid_min_level
=
3222 kvm_arch_get_supported_cpuid(s
, 0x0, 0, R_EAX
);
3223 env
->cpuid_min_xlevel
=
3224 kvm_arch_get_supported_cpuid(s
, 0x80000000, 0, R_EAX
);
3225 env
->cpuid_min_xlevel2
=
3226 kvm_arch_get_supported_cpuid(s
, 0xC0000000, 0, R_EAX
);
3228 env
->cpuid_min_level
=
3229 hvf_get_supported_cpuid(0x0, 0, R_EAX
);
3230 env
->cpuid_min_xlevel
=
3231 hvf_get_supported_cpuid(0x80000000, 0, R_EAX
);
3232 env
->cpuid_min_xlevel2
=
3233 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX
);
3236 if (lmce_supported()) {
3237 object_property_set_bool(OBJECT(cpu
), true, "lmce", &error_abort
);
3240 object_property_set_str(OBJECT(cpu
), CPUID_VENDOR_AMD
,
3241 "vendor", &error_abort
);
3242 object_property_set_int(OBJECT(cpu
), 6, "family", &error_abort
);
3243 object_property_set_int(OBJECT(cpu
), 6, "model", &error_abort
);
3244 object_property_set_int(OBJECT(cpu
), 3, "stepping", &error_abort
);
3245 object_property_set_str(OBJECT(cpu
),
3246 "QEMU TCG CPU version " QEMU_HW_VERSION
,
3247 "model-id", &error_abort
);
3250 object_property_set_bool(OBJECT(cpu
), true, "pmu", &error_abort
);
3253 static const TypeInfo max_x86_cpu_type_info
= {
3254 .name
= X86_CPU_TYPE_NAME("max"),
3255 .parent
= TYPE_X86_CPU
,
3256 .instance_init
= max_x86_cpu_initfn
,
3257 .class_init
= max_x86_cpu_class_init
,
3260 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
3261 static void host_x86_cpu_class_init(ObjectClass
*oc
, void *data
)
3263 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
3265 xcc
->host_cpuid_required
= true;
3268 #if defined(CONFIG_KVM)
3269 xcc
->model_description
=
3270 "KVM processor with all supported host features ";
3271 #elif defined(CONFIG_HVF)
3272 xcc
->model_description
=
3273 "HVF processor with all supported host features ";
3277 static const TypeInfo host_x86_cpu_type_info
= {
3278 .name
= X86_CPU_TYPE_NAME("host"),
3279 .parent
= X86_CPU_TYPE_NAME("max"),
3280 .class_init
= host_x86_cpu_class_init
,
3285 static char *feature_word_description(FeatureWordInfo
*f
, uint32_t bit
)
3287 assert(f
->type
== CPUID_FEATURE_WORD
|| f
->type
== MSR_FEATURE_WORD
);
3290 case CPUID_FEATURE_WORD
:
3292 const char *reg
= get_register_name_32(f
->cpuid
.reg
);
3294 return g_strdup_printf("CPUID.%02XH:%s",
3297 case MSR_FEATURE_WORD
:
3298 return g_strdup_printf("MSR(%02XH)",
3305 static void report_unavailable_features(FeatureWord w
, uint32_t mask
)
3307 FeatureWordInfo
*f
= &feature_word_info
[w
];
3309 char *feat_word_str
;
3311 for (i
= 0; i
< 32; ++i
) {
3312 if ((1UL << i
) & mask
) {
3313 feat_word_str
= feature_word_description(f
, i
);
3314 warn_report("%s doesn't support requested feature: %s%s%s [bit %d]",
3315 accel_uses_host_cpuid() ? "host" : "TCG",
3317 f
->feat_names
[i
] ? "." : "",
3318 f
->feat_names
[i
] ? f
->feat_names
[i
] : "", i
);
3319 g_free(feat_word_str
);
3324 static void x86_cpuid_version_get_family(Object
*obj
, Visitor
*v
,
3325 const char *name
, void *opaque
,
3328 X86CPU
*cpu
= X86_CPU(obj
);
3329 CPUX86State
*env
= &cpu
->env
;
3332 value
= (env
->cpuid_version
>> 8) & 0xf;
3334 value
+= (env
->cpuid_version
>> 20) & 0xff;
3336 visit_type_int(v
, name
, &value
, errp
);
3339 static void x86_cpuid_version_set_family(Object
*obj
, Visitor
*v
,
3340 const char *name
, void *opaque
,
3343 X86CPU
*cpu
= X86_CPU(obj
);
3344 CPUX86State
*env
= &cpu
->env
;
3345 const int64_t min
= 0;
3346 const int64_t max
= 0xff + 0xf;
3347 Error
*local_err
= NULL
;
3350 visit_type_int(v
, name
, &value
, &local_err
);
3352 error_propagate(errp
, local_err
);
3355 if (value
< min
|| value
> max
) {
3356 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
3357 name
? name
: "null", value
, min
, max
);
3361 env
->cpuid_version
&= ~0xff00f00;
3363 env
->cpuid_version
|= 0xf00 | ((value
- 0x0f) << 20);
3365 env
->cpuid_version
|= value
<< 8;
3369 static void x86_cpuid_version_get_model(Object
*obj
, Visitor
*v
,
3370 const char *name
, void *opaque
,
3373 X86CPU
*cpu
= X86_CPU(obj
);
3374 CPUX86State
*env
= &cpu
->env
;
3377 value
= (env
->cpuid_version
>> 4) & 0xf;
3378 value
|= ((env
->cpuid_version
>> 16) & 0xf) << 4;
3379 visit_type_int(v
, name
, &value
, errp
);
3382 static void x86_cpuid_version_set_model(Object
*obj
, Visitor
*v
,
3383 const char *name
, void *opaque
,
3386 X86CPU
*cpu
= X86_CPU(obj
);
3387 CPUX86State
*env
= &cpu
->env
;
3388 const int64_t min
= 0;
3389 const int64_t max
= 0xff;
3390 Error
*local_err
= NULL
;
3393 visit_type_int(v
, name
, &value
, &local_err
);
3395 error_propagate(errp
, local_err
);
3398 if (value
< min
|| value
> max
) {
3399 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
3400 name
? name
: "null", value
, min
, max
);
3404 env
->cpuid_version
&= ~0xf00f0;
3405 env
->cpuid_version
|= ((value
& 0xf) << 4) | ((value
>> 4) << 16);
3408 static void x86_cpuid_version_get_stepping(Object
*obj
, Visitor
*v
,
3409 const char *name
, void *opaque
,
3412 X86CPU
*cpu
= X86_CPU(obj
);
3413 CPUX86State
*env
= &cpu
->env
;
3416 value
= env
->cpuid_version
& 0xf;
3417 visit_type_int(v
, name
, &value
, errp
);
3420 static void x86_cpuid_version_set_stepping(Object
*obj
, Visitor
*v
,
3421 const char *name
, void *opaque
,
3424 X86CPU
*cpu
= X86_CPU(obj
);
3425 CPUX86State
*env
= &cpu
->env
;
3426 const int64_t min
= 0;
3427 const int64_t max
= 0xf;
3428 Error
*local_err
= NULL
;
3431 visit_type_int(v
, name
, &value
, &local_err
);
3433 error_propagate(errp
, local_err
);
3436 if (value
< min
|| value
> max
) {
3437 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
3438 name
? name
: "null", value
, min
, max
);
3442 env
->cpuid_version
&= ~0xf;
3443 env
->cpuid_version
|= value
& 0xf;
3446 static char *x86_cpuid_get_vendor(Object
*obj
, Error
**errp
)
3448 X86CPU
*cpu
= X86_CPU(obj
);
3449 CPUX86State
*env
= &cpu
->env
;
3452 value
= g_malloc(CPUID_VENDOR_SZ
+ 1);
3453 x86_cpu_vendor_words2str(value
, env
->cpuid_vendor1
, env
->cpuid_vendor2
,
3454 env
->cpuid_vendor3
);
3458 static void x86_cpuid_set_vendor(Object
*obj
, const char *value
,
3461 X86CPU
*cpu
= X86_CPU(obj
);
3462 CPUX86State
*env
= &cpu
->env
;
3465 if (strlen(value
) != CPUID_VENDOR_SZ
) {
3466 error_setg(errp
, QERR_PROPERTY_VALUE_BAD
, "", "vendor", value
);
3470 env
->cpuid_vendor1
= 0;
3471 env
->cpuid_vendor2
= 0;
3472 env
->cpuid_vendor3
= 0;
3473 for (i
= 0; i
< 4; i
++) {
3474 env
->cpuid_vendor1
|= ((uint8_t)value
[i
]) << (8 * i
);
3475 env
->cpuid_vendor2
|= ((uint8_t)value
[i
+ 4]) << (8 * i
);
3476 env
->cpuid_vendor3
|= ((uint8_t)value
[i
+ 8]) << (8 * i
);
3480 static char *x86_cpuid_get_model_id(Object
*obj
, Error
**errp
)
3482 X86CPU
*cpu
= X86_CPU(obj
);
3483 CPUX86State
*env
= &cpu
->env
;
3487 value
= g_malloc(48 + 1);
3488 for (i
= 0; i
< 48; i
++) {
3489 value
[i
] = env
->cpuid_model
[i
>> 2] >> (8 * (i
& 3));
3495 static void x86_cpuid_set_model_id(Object
*obj
, const char *model_id
,
3498 X86CPU
*cpu
= X86_CPU(obj
);
3499 CPUX86State
*env
= &cpu
->env
;
3502 if (model_id
== NULL
) {
3505 len
= strlen(model_id
);
3506 memset(env
->cpuid_model
, 0, 48);
3507 for (i
= 0; i
< 48; i
++) {
3511 c
= (uint8_t)model_id
[i
];
3513 env
->cpuid_model
[i
>> 2] |= c
<< (8 * (i
& 3));
3517 static void x86_cpuid_get_tsc_freq(Object
*obj
, Visitor
*v
, const char *name
,
3518 void *opaque
, Error
**errp
)
3520 X86CPU
*cpu
= X86_CPU(obj
);
3523 value
= cpu
->env
.tsc_khz
* 1000;
3524 visit_type_int(v
, name
, &value
, errp
);
3527 static void x86_cpuid_set_tsc_freq(Object
*obj
, Visitor
*v
, const char *name
,
3528 void *opaque
, Error
**errp
)
3530 X86CPU
*cpu
= X86_CPU(obj
);
3531 const int64_t min
= 0;
3532 const int64_t max
= INT64_MAX
;
3533 Error
*local_err
= NULL
;
3536 visit_type_int(v
, name
, &value
, &local_err
);
3538 error_propagate(errp
, local_err
);
3541 if (value
< min
|| value
> max
) {
3542 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
3543 name
? name
: "null", value
, min
, max
);
3547 cpu
->env
.tsc_khz
= cpu
->env
.user_tsc_khz
= value
/ 1000;
3550 /* Generic getter for "feature-words" and "filtered-features" properties */
3551 static void x86_cpu_get_feature_words(Object
*obj
, Visitor
*v
,
3552 const char *name
, void *opaque
,
3555 uint32_t *array
= (uint32_t *)opaque
;
3557 X86CPUFeatureWordInfo word_infos
[FEATURE_WORDS
] = { };
3558 X86CPUFeatureWordInfoList list_entries
[FEATURE_WORDS
] = { };
3559 X86CPUFeatureWordInfoList
*list
= NULL
;
3561 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
3562 FeatureWordInfo
*wi
= &feature_word_info
[w
];
3564 * We didn't have MSR features when "feature-words" was
3565 * introduced. Therefore skipped other type entries.
3567 if (wi
->type
!= CPUID_FEATURE_WORD
) {
3570 X86CPUFeatureWordInfo
*qwi
= &word_infos
[w
];
3571 qwi
->cpuid_input_eax
= wi
->cpuid
.eax
;
3572 qwi
->has_cpuid_input_ecx
= wi
->cpuid
.needs_ecx
;
3573 qwi
->cpuid_input_ecx
= wi
->cpuid
.ecx
;
3574 qwi
->cpuid_register
= x86_reg_info_32
[wi
->cpuid
.reg
].qapi_enum
;
3575 qwi
->features
= array
[w
];
3577 /* List will be in reverse order, but order shouldn't matter */
3578 list_entries
[w
].next
= list
;
3579 list_entries
[w
].value
= &word_infos
[w
];
3580 list
= &list_entries
[w
];
3583 visit_type_X86CPUFeatureWordInfoList(v
, "feature-words", &list
, errp
);
3586 /* Convert all '_' in a feature string option name to '-', to make feature
3587 * name conform to QOM property naming rule, which uses '-' instead of '_'.
3589 static inline void feat2prop(char *s
)
3591 while ((s
= strchr(s
, '_'))) {
3596 /* Return the feature property name for a feature flag bit */
3597 static const char *x86_cpu_feature_name(FeatureWord w
, int bitnr
)
3599 /* XSAVE components are automatically enabled by other features,
3600 * so return the original feature name instead
3602 if (w
== FEAT_XSAVE_COMP_LO
|| w
== FEAT_XSAVE_COMP_HI
) {
3603 int comp
= (w
== FEAT_XSAVE_COMP_HI
) ? bitnr
+ 32 : bitnr
;
3605 if (comp
< ARRAY_SIZE(x86_ext_save_areas
) &&
3606 x86_ext_save_areas
[comp
].bits
) {
3607 w
= x86_ext_save_areas
[comp
].feature
;
3608 bitnr
= ctz32(x86_ext_save_areas
[comp
].bits
);
3613 assert(w
< FEATURE_WORDS
);
3614 return feature_word_info
[w
].feat_names
[bitnr
];
3617 /* Compatibily hack to maintain legacy +-feat semantic,
3618 * where +-feat overwrites any feature set by
3619 * feat=on|feat even if the later is parsed after +-feat
3620 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
3622 static GList
*plus_features
, *minus_features
;
3624 static gint
compare_string(gconstpointer a
, gconstpointer b
)
3626 return g_strcmp0(a
, b
);
3629 /* Parse "+feature,-feature,feature=foo" CPU feature string
3631 static void x86_cpu_parse_featurestr(const char *typename
, char *features
,
3634 char *featurestr
; /* Single 'key=value" string being parsed */
3635 static bool cpu_globals_initialized
;
3636 bool ambiguous
= false;
3638 if (cpu_globals_initialized
) {
3641 cpu_globals_initialized
= true;
3647 for (featurestr
= strtok(features
, ",");
3649 featurestr
= strtok(NULL
, ",")) {
3651 const char *val
= NULL
;
3654 GlobalProperty
*prop
;
3656 /* Compatibility syntax: */
3657 if (featurestr
[0] == '+') {
3658 plus_features
= g_list_append(plus_features
,
3659 g_strdup(featurestr
+ 1));
3661 } else if (featurestr
[0] == '-') {
3662 minus_features
= g_list_append(minus_features
,
3663 g_strdup(featurestr
+ 1));
3667 eq
= strchr(featurestr
, '=');
3675 feat2prop(featurestr
);
3678 if (g_list_find_custom(plus_features
, name
, compare_string
)) {
3679 warn_report("Ambiguous CPU model string. "
3680 "Don't mix both \"+%s\" and \"%s=%s\"",
3684 if (g_list_find_custom(minus_features
, name
, compare_string
)) {
3685 warn_report("Ambiguous CPU model string. "
3686 "Don't mix both \"-%s\" and \"%s=%s\"",
3692 if (!strcmp(name
, "tsc-freq")) {
3696 ret
= qemu_strtosz_metric(val
, NULL
, &tsc_freq
);
3697 if (ret
< 0 || tsc_freq
> INT64_MAX
) {
3698 error_setg(errp
, "bad numerical value %s", val
);
3701 snprintf(num
, sizeof(num
), "%" PRId64
, tsc_freq
);
3703 name
= "tsc-frequency";
3706 prop
= g_new0(typeof(*prop
), 1);
3707 prop
->driver
= typename
;
3708 prop
->property
= g_strdup(name
);
3709 prop
->value
= g_strdup(val
);
3710 qdev_prop_register_global(prop
);
3714 warn_report("Compatibility of ambiguous CPU model "
3715 "strings won't be kept on future QEMU versions");
3719 static void x86_cpu_expand_features(X86CPU
*cpu
, Error
**errp
);
3720 static int x86_cpu_filter_features(X86CPU
*cpu
);
3722 /* Build a list with the name of all features on a feature word array */
3723 static void x86_cpu_list_feature_names(FeatureWordArray features
,
3724 strList
**feat_names
)
3727 strList
**next
= feat_names
;
3729 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
3730 uint32_t filtered
= features
[w
];
3732 for (i
= 0; i
< 32; i
++) {
3733 if (filtered
& (1UL << i
)) {
3734 strList
*new = g_new0(strList
, 1);
3735 new->value
= g_strdup(x86_cpu_feature_name(w
, i
));
3743 static void x86_cpu_get_unavailable_features(Object
*obj
, Visitor
*v
,
3744 const char *name
, void *opaque
,
3747 X86CPU
*xc
= X86_CPU(obj
);
3748 strList
*result
= NULL
;
3750 x86_cpu_list_feature_names(xc
->filtered_features
, &result
);
3751 visit_type_strList(v
, "unavailable-features", &result
, errp
);
3754 /* Check for missing features that may prevent the CPU class from
3755 * running using the current machine and accelerator.
3757 static void x86_cpu_class_check_missing_features(X86CPUClass
*xcc
,
3758 strList
**missing_feats
)
3762 strList
**next
= missing_feats
;
3764 if (xcc
->host_cpuid_required
&& !accel_uses_host_cpuid()) {
3765 strList
*new = g_new0(strList
, 1);
3766 new->value
= g_strdup("kvm");
3767 *missing_feats
= new;
3771 xc
= X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc
))));
3773 x86_cpu_expand_features(xc
, &err
);
3775 /* Errors at x86_cpu_expand_features should never happen,
3776 * but in case it does, just report the model as not
3777 * runnable at all using the "type" property.
3779 strList
*new = g_new0(strList
, 1);
3780 new->value
= g_strdup("type");
3785 x86_cpu_filter_features(xc
);
3787 x86_cpu_list_feature_names(xc
->filtered_features
, next
);
3789 object_unref(OBJECT(xc
));
3792 /* Print all cpuid feature names in featureset
3794 static void listflags(GList
*features
)
3799 for (tmp
= features
; tmp
; tmp
= tmp
->next
) {
3800 const char *name
= tmp
->data
;
3801 if ((len
+ strlen(name
) + 1) >= 75) {
3805 qemu_printf("%s%s", len
== 0 ? " " : " ", name
);
3806 len
+= strlen(name
) + 1;
3811 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
3812 static gint
x86_cpu_list_compare(gconstpointer a
, gconstpointer b
)
3814 ObjectClass
*class_a
= (ObjectClass
*)a
;
3815 ObjectClass
*class_b
= (ObjectClass
*)b
;
3816 X86CPUClass
*cc_a
= X86_CPU_CLASS(class_a
);
3817 X86CPUClass
*cc_b
= X86_CPU_CLASS(class_b
);
3818 char *name_a
, *name_b
;
3821 if (cc_a
->ordering
!= cc_b
->ordering
) {
3822 ret
= cc_a
->ordering
- cc_b
->ordering
;
3824 name_a
= x86_cpu_class_get_model_name(cc_a
);
3825 name_b
= x86_cpu_class_get_model_name(cc_b
);
3826 ret
= strcmp(name_a
, name_b
);
3833 static GSList
*get_sorted_cpu_model_list(void)
3835 GSList
*list
= object_class_get_list(TYPE_X86_CPU
, false);
3836 list
= g_slist_sort(list
, x86_cpu_list_compare
);
3840 static void x86_cpu_list_entry(gpointer data
, gpointer user_data
)
3842 ObjectClass
*oc
= data
;
3843 X86CPUClass
*cc
= X86_CPU_CLASS(oc
);
3844 char *name
= x86_cpu_class_get_model_name(cc
);
3845 const char *desc
= cc
->model_description
;
3846 if (!desc
&& cc
->cpu_def
) {
3847 desc
= cc
->cpu_def
->model_id
;
3850 qemu_printf("x86 %-20s %-48s\n", name
, desc
);
3854 /* list available CPU models and flags */
3855 void x86_cpu_list(void)
3859 GList
*names
= NULL
;
3861 qemu_printf("Available CPUs:\n");
3862 list
= get_sorted_cpu_model_list();
3863 g_slist_foreach(list
, x86_cpu_list_entry
, NULL
);
3867 for (i
= 0; i
< ARRAY_SIZE(feature_word_info
); i
++) {
3868 FeatureWordInfo
*fw
= &feature_word_info
[i
];
3869 for (j
= 0; j
< 32; j
++) {
3870 if (fw
->feat_names
[j
]) {
3871 names
= g_list_append(names
, (gpointer
)fw
->feat_names
[j
]);
3876 names
= g_list_sort(names
, (GCompareFunc
)strcmp
);
3878 qemu_printf("\nRecognized CPUID flags:\n");
3884 static void x86_cpu_definition_entry(gpointer data
, gpointer user_data
)
3886 ObjectClass
*oc
= data
;
3887 X86CPUClass
*cc
= X86_CPU_CLASS(oc
);
3888 CpuDefinitionInfoList
**cpu_list
= user_data
;
3889 CpuDefinitionInfoList
*entry
;
3890 CpuDefinitionInfo
*info
;
3892 info
= g_malloc0(sizeof(*info
));
3893 info
->name
= x86_cpu_class_get_model_name(cc
);
3894 x86_cpu_class_check_missing_features(cc
, &info
->unavailable_features
);
3895 info
->has_unavailable_features
= true;
3896 info
->q_typename
= g_strdup(object_class_get_name(oc
));
3897 info
->migration_safe
= cc
->migration_safe
;
3898 info
->has_migration_safe
= true;
3899 info
->q_static
= cc
->static_model
;
3901 entry
= g_malloc0(sizeof(*entry
));
3902 entry
->value
= info
;
3903 entry
->next
= *cpu_list
;
3907 CpuDefinitionInfoList
*qmp_query_cpu_definitions(Error
**errp
)
3909 CpuDefinitionInfoList
*cpu_list
= NULL
;
3910 GSList
*list
= get_sorted_cpu_model_list();
3911 g_slist_foreach(list
, x86_cpu_definition_entry
, &cpu_list
);
3916 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w
,
3917 bool migratable_only
)
3919 FeatureWordInfo
*wi
= &feature_word_info
[w
];
3922 if (kvm_enabled()) {
3924 case CPUID_FEATURE_WORD
:
3925 r
= kvm_arch_get_supported_cpuid(kvm_state
, wi
->cpuid
.eax
,
3929 case MSR_FEATURE_WORD
:
3930 r
= kvm_arch_get_supported_msr_feature(kvm_state
,
3934 } else if (hvf_enabled()) {
3935 if (wi
->type
!= CPUID_FEATURE_WORD
) {
3938 r
= hvf_get_supported_cpuid(wi
->cpuid
.eax
,
3941 } else if (tcg_enabled()) {
3942 r
= wi
->tcg_features
;
3946 if (migratable_only
) {
3947 r
&= x86_cpu_get_migratable_flags(w
);
3952 static void x86_cpu_report_filtered_features(X86CPU
*cpu
)
3956 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
3957 report_unavailable_features(w
, cpu
->filtered_features
[w
]);
3961 static void x86_cpu_apply_props(X86CPU
*cpu
, PropValue
*props
)
3964 for (pv
= props
; pv
->prop
; pv
++) {
3968 object_property_parse(OBJECT(cpu
), pv
->value
, pv
->prop
,
3973 /* Load data from X86CPUDefinition into a X86CPU object
3975 static void x86_cpu_load_def(X86CPU
*cpu
, X86CPUDefinition
*def
, Error
**errp
)
3977 CPUX86State
*env
= &cpu
->env
;
3979 char host_vendor
[CPUID_VENDOR_SZ
+ 1];
3982 /*NOTE: any property set by this function should be returned by
3983 * x86_cpu_static_props(), so static expansion of
3984 * query-cpu-model-expansion is always complete.
3987 /* CPU models only set _minimum_ values for level/xlevel: */
3988 object_property_set_uint(OBJECT(cpu
), def
->level
, "min-level", errp
);
3989 object_property_set_uint(OBJECT(cpu
), def
->xlevel
, "min-xlevel", errp
);
3991 object_property_set_int(OBJECT(cpu
), def
->family
, "family", errp
);
3992 object_property_set_int(OBJECT(cpu
), def
->model
, "model", errp
);
3993 object_property_set_int(OBJECT(cpu
), def
->stepping
, "stepping", errp
);
3994 object_property_set_str(OBJECT(cpu
), def
->model_id
, "model-id", errp
);
3995 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
3996 env
->features
[w
] = def
->features
[w
];
3999 /* legacy-cache defaults to 'off' if CPU model provides cache info */
4000 cpu
->legacy_cache
= !def
->cache_info
;
4002 /* Special cases not set in the X86CPUDefinition structs: */
4003 /* TODO: in-kernel irqchip for hvf */
4004 if (kvm_enabled()) {
4005 if (!kvm_irqchip_in_kernel()) {
4006 x86_cpu_change_kvm_default("x2apic", "off");
4009 x86_cpu_apply_props(cpu
, kvm_default_props
);
4010 } else if (tcg_enabled()) {
4011 x86_cpu_apply_props(cpu
, tcg_default_props
);
4014 env
->features
[FEAT_1_ECX
] |= CPUID_EXT_HYPERVISOR
;
4016 /* sysenter isn't supported in compatibility mode on AMD,
4017 * syscall isn't supported in compatibility mode on Intel.
4018 * Normally we advertise the actual CPU vendor, but you can
4019 * override this using the 'vendor' property if you want to use
4020 * KVM's sysenter/syscall emulation in compatibility mode and
4021 * when doing cross vendor migration
4023 vendor
= def
->vendor
;
4024 if (accel_uses_host_cpuid()) {
4025 uint32_t ebx
= 0, ecx
= 0, edx
= 0;
4026 host_cpuid(0, 0, NULL
, &ebx
, &ecx
, &edx
);
4027 x86_cpu_vendor_words2str(host_vendor
, ebx
, edx
, ecx
);
4028 vendor
= host_vendor
;
4031 object_property_set_str(OBJECT(cpu
), vendor
, "vendor", errp
);
4035 #ifndef CONFIG_USER_ONLY
4036 /* Return a QDict containing keys for all properties that can be included
4037 * in static expansion of CPU models. All properties set by x86_cpu_load_def()
4038 * must be included in the dictionary.
4040 static QDict
*x86_cpu_static_props(void)
4044 static const char *props
[] = {
4062 for (i
= 0; props
[i
]; i
++) {
4063 qdict_put_null(d
, props
[i
]);
4066 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
4067 FeatureWordInfo
*fi
= &feature_word_info
[w
];
4069 for (bit
= 0; bit
< 32; bit
++) {
4070 if (!fi
->feat_names
[bit
]) {
4073 qdict_put_null(d
, fi
->feat_names
[bit
]);
4080 /* Add an entry to @props dict, with the value for property. */
4081 static void x86_cpu_expand_prop(X86CPU
*cpu
, QDict
*props
, const char *prop
)
4083 QObject
*value
= object_property_get_qobject(OBJECT(cpu
), prop
,
4086 qdict_put_obj(props
, prop
, value
);
4089 /* Convert CPU model data from X86CPU object to a property dictionary
4090 * that can recreate exactly the same CPU model.
4092 static void x86_cpu_to_dict(X86CPU
*cpu
, QDict
*props
)
4094 QDict
*sprops
= x86_cpu_static_props();
4095 const QDictEntry
*e
;
4097 for (e
= qdict_first(sprops
); e
; e
= qdict_next(sprops
, e
)) {
4098 const char *prop
= qdict_entry_key(e
);
4099 x86_cpu_expand_prop(cpu
, props
, prop
);
4103 /* Convert CPU model data from X86CPU object to a property dictionary
4104 * that can recreate exactly the same CPU model, including every
4105 * writeable QOM property.
4107 static void x86_cpu_to_dict_full(X86CPU
*cpu
, QDict
*props
)
4109 ObjectPropertyIterator iter
;
4110 ObjectProperty
*prop
;
4112 object_property_iter_init(&iter
, OBJECT(cpu
));
4113 while ((prop
= object_property_iter_next(&iter
))) {
4114 /* skip read-only or write-only properties */
4115 if (!prop
->get
|| !prop
->set
) {
4119 /* "hotplugged" is the only property that is configurable
4120 * on the command-line but will be set differently on CPUs
4121 * created using "-cpu ... -smp ..." and by CPUs created
4122 * on the fly by x86_cpu_from_model() for querying. Skip it.
4124 if (!strcmp(prop
->name
, "hotplugged")) {
4127 x86_cpu_expand_prop(cpu
, props
, prop
->name
);
4131 static void object_apply_props(Object
*obj
, QDict
*props
, Error
**errp
)
4133 const QDictEntry
*prop
;
4136 for (prop
= qdict_first(props
); prop
; prop
= qdict_next(props
, prop
)) {
4137 object_property_set_qobject(obj
, qdict_entry_value(prop
),
4138 qdict_entry_key(prop
), &err
);
4144 error_propagate(errp
, err
);
4147 /* Create X86CPU object according to model+props specification */
4148 static X86CPU
*x86_cpu_from_model(const char *model
, QDict
*props
, Error
**errp
)
4154 xcc
= X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU
, model
));
4156 error_setg(&err
, "CPU model '%s' not found", model
);
4160 xc
= X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc
))));
4162 object_apply_props(OBJECT(xc
), props
, &err
);
4168 x86_cpu_expand_features(xc
, &err
);
4175 error_propagate(errp
, err
);
4176 object_unref(OBJECT(xc
));
4182 CpuModelExpansionInfo
*
4183 qmp_query_cpu_model_expansion(CpuModelExpansionType type
,
4184 CpuModelInfo
*model
,
4189 CpuModelExpansionInfo
*ret
= g_new0(CpuModelExpansionInfo
, 1);
4190 QDict
*props
= NULL
;
4191 const char *base_name
;
4193 xc
= x86_cpu_from_model(model
->name
,
4195 qobject_to(QDict
, model
->props
) :
4201 props
= qdict_new();
4202 ret
->model
= g_new0(CpuModelInfo
, 1);
4203 ret
->model
->props
= QOBJECT(props
);
4204 ret
->model
->has_props
= true;
4207 case CPU_MODEL_EXPANSION_TYPE_STATIC
:
4208 /* Static expansion will be based on "base" only */
4210 x86_cpu_to_dict(xc
, props
);
4212 case CPU_MODEL_EXPANSION_TYPE_FULL
:
4213 /* As we don't return every single property, full expansion needs
4214 * to keep the original model name+props, and add extra
4215 * properties on top of that.
4217 base_name
= model
->name
;
4218 x86_cpu_to_dict_full(xc
, props
);
4221 error_setg(&err
, "Unsupported expansion type");
4225 x86_cpu_to_dict(xc
, props
);
4227 ret
->model
->name
= g_strdup(base_name
);
4230 object_unref(OBJECT(xc
));
4232 error_propagate(errp
, err
);
4233 qapi_free_CpuModelExpansionInfo(ret
);
4238 #endif /* !CONFIG_USER_ONLY */
4240 static gchar
*x86_gdb_arch_name(CPUState
*cs
)
4242 #ifdef TARGET_X86_64
4243 return g_strdup("i386:x86-64");
4245 return g_strdup("i386");
4249 static void x86_cpu_cpudef_class_init(ObjectClass
*oc
, void *data
)
4251 X86CPUDefinition
*cpudef
= data
;
4252 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
4254 xcc
->cpu_def
= cpudef
;
4255 xcc
->migration_safe
= true;
4258 static void x86_register_cpudef_type(X86CPUDefinition
*def
)
4260 char *typename
= x86_cpu_type_name(def
->name
);
4263 .parent
= TYPE_X86_CPU
,
4264 .class_init
= x86_cpu_cpudef_class_init
,
4268 /* AMD aliases are handled at runtime based on CPUID vendor, so
4269 * they shouldn't be set on the CPU model table.
4271 assert(!(def
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_AMD_ALIASES
));
4272 /* catch mistakes instead of silently truncating model_id when too long */
4273 assert(def
->model_id
&& strlen(def
->model_id
) <= 48);
4280 #if !defined(CONFIG_USER_ONLY)
4282 void cpu_clear_apic_feature(CPUX86State
*env
)
4284 env
->features
[FEAT_1_EDX
] &= ~CPUID_APIC
;
4287 #endif /* !CONFIG_USER_ONLY */
4289 void cpu_x86_cpuid(CPUX86State
*env
, uint32_t index
, uint32_t count
,
4290 uint32_t *eax
, uint32_t *ebx
,
4291 uint32_t *ecx
, uint32_t *edx
)
4293 X86CPU
*cpu
= env_archcpu(env
);
4294 CPUState
*cs
= env_cpu(env
);
4295 uint32_t die_offset
;
4297 uint32_t signature
[3];
4299 /* Calculate & apply limits for different index ranges */
4300 if (index
>= 0xC0000000) {
4301 limit
= env
->cpuid_xlevel2
;
4302 } else if (index
>= 0x80000000) {
4303 limit
= env
->cpuid_xlevel
;
4304 } else if (index
>= 0x40000000) {
4307 limit
= env
->cpuid_level
;
4310 if (index
> limit
) {
4311 /* Intel documentation states that invalid EAX input will
4312 * return the same information as EAX=cpuid_level
4313 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
4315 index
= env
->cpuid_level
;
4320 *eax
= env
->cpuid_level
;
4321 *ebx
= env
->cpuid_vendor1
;
4322 *edx
= env
->cpuid_vendor2
;
4323 *ecx
= env
->cpuid_vendor3
;
4326 *eax
= env
->cpuid_version
;
4327 *ebx
= (cpu
->apic_id
<< 24) |
4328 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
4329 *ecx
= env
->features
[FEAT_1_ECX
];
4330 if ((*ecx
& CPUID_EXT_XSAVE
) && (env
->cr
[4] & CR4_OSXSAVE_MASK
)) {
4331 *ecx
|= CPUID_EXT_OSXSAVE
;
4333 *edx
= env
->features
[FEAT_1_EDX
];
4334 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
4335 *ebx
|= (cs
->nr_cores
* cs
->nr_threads
) << 16;
4340 /* cache info: needed for Pentium Pro compatibility */
4341 if (cpu
->cache_info_passthrough
) {
4342 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
4345 *eax
= 1; /* Number of CPUID[EAX=2] calls required */
4347 if (!cpu
->enable_l3_cache
) {
4350 *ecx
= cpuid2_cache_descriptor(env
->cache_info_cpuid2
.l3_cache
);
4352 *edx
= (cpuid2_cache_descriptor(env
->cache_info_cpuid2
.l1d_cache
) << 16) |
4353 (cpuid2_cache_descriptor(env
->cache_info_cpuid2
.l1i_cache
) << 8) |
4354 (cpuid2_cache_descriptor(env
->cache_info_cpuid2
.l2_cache
));
4357 /* cache info: needed for Core compatibility */
4358 if (cpu
->cache_info_passthrough
) {
4359 host_cpuid(index
, count
, eax
, ebx
, ecx
, edx
);
4360 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
4361 *eax
&= ~0xFC000000;
4362 if ((*eax
& 31) && cs
->nr_cores
> 1) {
4363 *eax
|= (cs
->nr_cores
- 1) << 26;
4368 case 0: /* L1 dcache info */
4369 encode_cache_cpuid4(env
->cache_info_cpuid4
.l1d_cache
,
4371 eax
, ebx
, ecx
, edx
);
4373 case 1: /* L1 icache info */
4374 encode_cache_cpuid4(env
->cache_info_cpuid4
.l1i_cache
,
4376 eax
, ebx
, ecx
, edx
);
4378 case 2: /* L2 cache info */
4379 encode_cache_cpuid4(env
->cache_info_cpuid4
.l2_cache
,
4380 cs
->nr_threads
, cs
->nr_cores
,
4381 eax
, ebx
, ecx
, edx
);
4383 case 3: /* L3 cache info */
4384 die_offset
= apicid_die_offset(env
->nr_dies
,
4385 cs
->nr_cores
, cs
->nr_threads
);
4386 if (cpu
->enable_l3_cache
) {
4387 encode_cache_cpuid4(env
->cache_info_cpuid4
.l3_cache
,
4388 (1 << die_offset
), cs
->nr_cores
,
4389 eax
, ebx
, ecx
, edx
);
4393 default: /* end of info */
4394 *eax
= *ebx
= *ecx
= *edx
= 0;
4400 /* MONITOR/MWAIT Leaf */
4401 *eax
= cpu
->mwait
.eax
; /* Smallest monitor-line size in bytes */
4402 *ebx
= cpu
->mwait
.ebx
; /* Largest monitor-line size in bytes */
4403 *ecx
= cpu
->mwait
.ecx
; /* flags */
4404 *edx
= cpu
->mwait
.edx
; /* mwait substates */
4407 /* Thermal and Power Leaf */
4408 *eax
= env
->features
[FEAT_6_EAX
];
4414 /* Structured Extended Feature Flags Enumeration Leaf */
4416 *eax
= 0; /* Maximum ECX value for sub-leaves */
4417 *ebx
= env
->features
[FEAT_7_0_EBX
]; /* Feature flags */
4418 *ecx
= env
->features
[FEAT_7_0_ECX
]; /* Feature flags */
4419 if ((*ecx
& CPUID_7_0_ECX_PKU
) && env
->cr
[4] & CR4_PKE_MASK
) {
4420 *ecx
|= CPUID_7_0_ECX_OSPKE
;
4422 *edx
= env
->features
[FEAT_7_0_EDX
]; /* Feature flags */
4431 /* Direct Cache Access Information Leaf */
4432 *eax
= 0; /* Bits 0-31 in DCA_CAP MSR */
4438 /* Architectural Performance Monitoring Leaf */
4439 if (kvm_enabled() && cpu
->enable_pmu
) {
4440 KVMState
*s
= cs
->kvm_state
;
4442 *eax
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EAX
);
4443 *ebx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EBX
);
4444 *ecx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_ECX
);
4445 *edx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EDX
);
4446 } else if (hvf_enabled() && cpu
->enable_pmu
) {
4447 *eax
= hvf_get_supported_cpuid(0xA, count
, R_EAX
);
4448 *ebx
= hvf_get_supported_cpuid(0xA, count
, R_EBX
);
4449 *ecx
= hvf_get_supported_cpuid(0xA, count
, R_ECX
);
4450 *edx
= hvf_get_supported_cpuid(0xA, count
, R_EDX
);
4459 /* Extended Topology Enumeration Leaf */
4460 if (!cpu
->enable_cpuid_0xb
) {
4461 *eax
= *ebx
= *ecx
= *edx
= 0;
4465 *ecx
= count
& 0xff;
4466 *edx
= cpu
->apic_id
;
4470 *eax
= apicid_core_offset(env
->nr_dies
,
4471 cs
->nr_cores
, cs
->nr_threads
);
4472 *ebx
= cs
->nr_threads
;
4473 *ecx
|= CPUID_TOPOLOGY_LEVEL_SMT
;
4476 *eax
= apicid_pkg_offset(env
->nr_dies
,
4477 cs
->nr_cores
, cs
->nr_threads
);
4478 *ebx
= cs
->nr_cores
* cs
->nr_threads
;
4479 *ecx
|= CPUID_TOPOLOGY_LEVEL_CORE
;
4484 *ecx
|= CPUID_TOPOLOGY_LEVEL_INVALID
;
4487 assert(!(*eax
& ~0x1f));
4488 *ebx
&= 0xffff; /* The count doesn't need to be reliable. */
4491 /* V2 Extended Topology Enumeration Leaf */
4492 if (env
->nr_dies
< 2) {
4493 *eax
= *ebx
= *ecx
= *edx
= 0;
4497 *ecx
= count
& 0xff;
4498 *edx
= cpu
->apic_id
;
4501 *eax
= apicid_core_offset(env
->nr_dies
, cs
->nr_cores
,
4503 *ebx
= cs
->nr_threads
;
4504 *ecx
|= CPUID_TOPOLOGY_LEVEL_SMT
;
4507 *eax
= apicid_die_offset(env
->nr_dies
, cs
->nr_cores
,
4509 *ebx
= cs
->nr_cores
* cs
->nr_threads
;
4510 *ecx
|= CPUID_TOPOLOGY_LEVEL_CORE
;
4513 *eax
= apicid_pkg_offset(env
->nr_dies
, cs
->nr_cores
,
4515 *ebx
= env
->nr_dies
* cs
->nr_cores
* cs
->nr_threads
;
4516 *ecx
|= CPUID_TOPOLOGY_LEVEL_DIE
;
4521 *ecx
|= CPUID_TOPOLOGY_LEVEL_INVALID
;
4523 assert(!(*eax
& ~0x1f));
4524 *ebx
&= 0xffff; /* The count doesn't need to be reliable. */
4527 /* Processor Extended State */
4532 if (!(env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
)) {
4537 *ecx
= xsave_area_size(x86_cpu_xsave_components(cpu
));
4538 *eax
= env
->features
[FEAT_XSAVE_COMP_LO
];
4539 *edx
= env
->features
[FEAT_XSAVE_COMP_HI
];
4540 *ebx
= xsave_area_size(env
->xcr0
);
4541 } else if (count
== 1) {
4542 *eax
= env
->features
[FEAT_XSAVE
];
4543 } else if (count
< ARRAY_SIZE(x86_ext_save_areas
)) {
4544 if ((x86_cpu_xsave_components(cpu
) >> count
) & 1) {
4545 const ExtSaveArea
*esa
= &x86_ext_save_areas
[count
];
4553 /* Intel Processor Trace Enumeration */
4558 if (!(env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_INTEL_PT
) ||
4564 *eax
= INTEL_PT_MAX_SUBLEAF
;
4565 *ebx
= INTEL_PT_MINIMAL_EBX
;
4566 *ecx
= INTEL_PT_MINIMAL_ECX
;
4567 } else if (count
== 1) {
4568 *eax
= INTEL_PT_MTC_BITMAP
| INTEL_PT_ADDR_RANGES_NUM
;
4569 *ebx
= INTEL_PT_PSB_BITMAP
| INTEL_PT_CYCLE_BITMAP
;
4575 * CPUID code in kvm_arch_init_vcpu() ignores stuff
4576 * set here, but we restrict to TCG none the less.
4578 if (tcg_enabled() && cpu
->expose_tcg
) {
4579 memcpy(signature
, "TCGTCGTCGTCG", 12);
4581 *ebx
= signature
[0];
4582 *ecx
= signature
[1];
4583 *edx
= signature
[2];
4598 *eax
= env
->cpuid_xlevel
;
4599 *ebx
= env
->cpuid_vendor1
;
4600 *edx
= env
->cpuid_vendor2
;
4601 *ecx
= env
->cpuid_vendor3
;
4604 *eax
= env
->cpuid_version
;
4606 *ecx
= env
->features
[FEAT_8000_0001_ECX
];
4607 *edx
= env
->features
[FEAT_8000_0001_EDX
];
4609 /* The Linux kernel checks for the CMPLegacy bit and
4610 * discards multiple thread information if it is set.
4611 * So don't set it here for Intel to make Linux guests happy.
4613 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
4614 if (env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
||
4615 env
->cpuid_vendor2
!= CPUID_VENDOR_INTEL_2
||
4616 env
->cpuid_vendor3
!= CPUID_VENDOR_INTEL_3
) {
4617 *ecx
|= 1 << 1; /* CmpLegacy bit */
4624 *eax
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 0];
4625 *ebx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 1];
4626 *ecx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 2];
4627 *edx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 3];
4630 /* cache info (L1 cache) */
4631 if (cpu
->cache_info_passthrough
) {
4632 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
4635 *eax
= (L1_DTLB_2M_ASSOC
<< 24) | (L1_DTLB_2M_ENTRIES
<< 16) | \
4636 (L1_ITLB_2M_ASSOC
<< 8) | (L1_ITLB_2M_ENTRIES
);
4637 *ebx
= (L1_DTLB_4K_ASSOC
<< 24) | (L1_DTLB_4K_ENTRIES
<< 16) | \
4638 (L1_ITLB_4K_ASSOC
<< 8) | (L1_ITLB_4K_ENTRIES
);
4639 *ecx
= encode_cache_cpuid80000005(env
->cache_info_amd
.l1d_cache
);
4640 *edx
= encode_cache_cpuid80000005(env
->cache_info_amd
.l1i_cache
);
4643 /* cache info (L2 cache) */
4644 if (cpu
->cache_info_passthrough
) {
4645 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
4648 *eax
= (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC
) << 28) | \
4649 (L2_DTLB_2M_ENTRIES
<< 16) | \
4650 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC
) << 12) | \
4651 (L2_ITLB_2M_ENTRIES
);
4652 *ebx
= (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC
) << 28) | \
4653 (L2_DTLB_4K_ENTRIES
<< 16) | \
4654 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC
) << 12) | \
4655 (L2_ITLB_4K_ENTRIES
);
4656 encode_cache_cpuid80000006(env
->cache_info_amd
.l2_cache
,
4657 cpu
->enable_l3_cache
?
4658 env
->cache_info_amd
.l3_cache
: NULL
,
4665 *edx
= env
->features
[FEAT_8000_0007_EDX
];
4668 /* virtual & phys address size in low 2 bytes. */
4669 if (env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
) {
4670 /* 64 bit processor */
4671 *eax
= cpu
->phys_bits
; /* configurable physical bits */
4672 if (env
->features
[FEAT_7_0_ECX
] & CPUID_7_0_ECX_LA57
) {
4673 *eax
|= 0x00003900; /* 57 bits virtual */
4675 *eax
|= 0x00003000; /* 48 bits virtual */
4678 *eax
= cpu
->phys_bits
;
4680 *ebx
= env
->features
[FEAT_8000_0008_EBX
];
4683 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
4684 *ecx
|= (cs
->nr_cores
* cs
->nr_threads
) - 1;
4688 if (env
->features
[FEAT_8000_0001_ECX
] & CPUID_EXT3_SVM
) {
4689 *eax
= 0x00000001; /* SVM Revision */
4690 *ebx
= 0x00000010; /* nr of ASIDs */
4692 *edx
= env
->features
[FEAT_SVM
]; /* optional features */
4702 if (cpu
->cache_info_passthrough
) {
4703 host_cpuid(index
, count
, eax
, ebx
, ecx
, edx
);
4707 case 0: /* L1 dcache info */
4708 encode_cache_cpuid8000001d(env
->cache_info_amd
.l1d_cache
, cs
,
4709 eax
, ebx
, ecx
, edx
);
4711 case 1: /* L1 icache info */
4712 encode_cache_cpuid8000001d(env
->cache_info_amd
.l1i_cache
, cs
,
4713 eax
, ebx
, ecx
, edx
);
4715 case 2: /* L2 cache info */
4716 encode_cache_cpuid8000001d(env
->cache_info_amd
.l2_cache
, cs
,
4717 eax
, ebx
, ecx
, edx
);
4719 case 3: /* L3 cache info */
4720 encode_cache_cpuid8000001d(env
->cache_info_amd
.l3_cache
, cs
,
4721 eax
, ebx
, ecx
, edx
);
4723 default: /* end of info */
4724 *eax
= *ebx
= *ecx
= *edx
= 0;
4729 assert(cpu
->core_id
<= 255);
4730 encode_topo_cpuid8000001e(cs
, cpu
,
4731 eax
, ebx
, ecx
, edx
);
4734 *eax
= env
->cpuid_xlevel2
;
4740 /* Support for VIA CPU's CPUID instruction */
4741 *eax
= env
->cpuid_version
;
4744 *edx
= env
->features
[FEAT_C000_0001_EDX
];
4749 /* Reserved for the future, and now filled with zero */
4756 *eax
= sev_enabled() ? 0x2 : 0;
4757 *ebx
= sev_get_cbit_position();
4758 *ebx
|= sev_get_reduced_phys_bits() << 6;
4763 /* reserved values: zero */
4772 /* CPUClass::reset() */
4773 static void x86_cpu_reset(CPUState
*s
)
4775 X86CPU
*cpu
= X86_CPU(s
);
4776 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(cpu
);
4777 CPUX86State
*env
= &cpu
->env
;
4782 xcc
->parent_reset(s
);
4784 memset(env
, 0, offsetof(CPUX86State
, end_reset_fields
));
4786 env
->old_exception
= -1;
4788 /* init to reset state */
4790 env
->hflags2
|= HF2_GIF_MASK
;
4792 cpu_x86_update_cr0(env
, 0x60000010);
4793 env
->a20_mask
= ~0x0;
4794 env
->smbase
= 0x30000;
4795 env
->msr_smi_count
= 0;
4797 env
->idt
.limit
= 0xffff;
4798 env
->gdt
.limit
= 0xffff;
4799 env
->ldt
.limit
= 0xffff;
4800 env
->ldt
.flags
= DESC_P_MASK
| (2 << DESC_TYPE_SHIFT
);
4801 env
->tr
.limit
= 0xffff;
4802 env
->tr
.flags
= DESC_P_MASK
| (11 << DESC_TYPE_SHIFT
);
4804 cpu_x86_load_seg_cache(env
, R_CS
, 0xf000, 0xffff0000, 0xffff,
4805 DESC_P_MASK
| DESC_S_MASK
| DESC_CS_MASK
|
4806 DESC_R_MASK
| DESC_A_MASK
);
4807 cpu_x86_load_seg_cache(env
, R_DS
, 0, 0, 0xffff,
4808 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
4810 cpu_x86_load_seg_cache(env
, R_ES
, 0, 0, 0xffff,
4811 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
4813 cpu_x86_load_seg_cache(env
, R_SS
, 0, 0, 0xffff,
4814 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
4816 cpu_x86_load_seg_cache(env
, R_FS
, 0, 0, 0xffff,
4817 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
4819 cpu_x86_load_seg_cache(env
, R_GS
, 0, 0, 0xffff,
4820 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
4824 env
->regs
[R_EDX
] = env
->cpuid_version
;
4829 for (i
= 0; i
< 8; i
++) {
4832 cpu_set_fpuc(env
, 0x37f);
4834 env
->mxcsr
= 0x1f80;
4835 /* All units are in INIT state. */
4838 env
->pat
= 0x0007040600070406ULL
;
4839 env
->msr_ia32_misc_enable
= MSR_IA32_MISC_ENABLE_DEFAULT
;
4840 if (env
->features
[FEAT_1_ECX
] & CPUID_EXT_MONITOR
) {
4841 env
->msr_ia32_misc_enable
|= MSR_IA32_MISC_ENABLE_MWAIT
;
4844 memset(env
->dr
, 0, sizeof(env
->dr
));
4845 env
->dr
[6] = DR6_FIXED_1
;
4846 env
->dr
[7] = DR7_FIXED_1
;
4847 cpu_breakpoint_remove_all(s
, BP_CPU
);
4848 cpu_watchpoint_remove_all(s
, BP_CPU
);
4851 xcr0
= XSTATE_FP_MASK
;
4853 #ifdef CONFIG_USER_ONLY
4854 /* Enable all the features for user-mode. */
4855 if (env
->features
[FEAT_1_EDX
] & CPUID_SSE
) {
4856 xcr0
|= XSTATE_SSE_MASK
;
4858 for (i
= 2; i
< ARRAY_SIZE(x86_ext_save_areas
); i
++) {
4859 const ExtSaveArea
*esa
= &x86_ext_save_areas
[i
];
4860 if (env
->features
[esa
->feature
] & esa
->bits
) {
4865 if (env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
) {
4866 cr4
|= CR4_OSFXSR_MASK
| CR4_OSXSAVE_MASK
;
4868 if (env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_FSGSBASE
) {
4869 cr4
|= CR4_FSGSBASE_MASK
;
4874 cpu_x86_update_cr4(env
, cr4
);
4877 * SDM 11.11.5 requires:
4878 * - IA32_MTRR_DEF_TYPE MSR.E = 0
4879 * - IA32_MTRR_PHYSMASKn.V = 0
4880 * All other bits are undefined. For simplification, zero it all.
4882 env
->mtrr_deftype
= 0;
4883 memset(env
->mtrr_var
, 0, sizeof(env
->mtrr_var
));
4884 memset(env
->mtrr_fixed
, 0, sizeof(env
->mtrr_fixed
));
4886 env
->interrupt_injected
= -1;
4887 env
->exception_nr
= -1;
4888 env
->exception_pending
= 0;
4889 env
->exception_injected
= 0;
4890 env
->exception_has_payload
= false;
4891 env
->exception_payload
= 0;
4892 env
->nmi_injected
= false;
4893 #if !defined(CONFIG_USER_ONLY)
4894 /* We hard-wire the BSP to the first CPU. */
4895 apic_designate_bsp(cpu
->apic_state
, s
->cpu_index
== 0);
4897 s
->halted
= !cpu_is_bsp(cpu
);
4899 if (kvm_enabled()) {
4900 kvm_arch_reset_vcpu(cpu
);
4902 else if (hvf_enabled()) {
4908 #ifndef CONFIG_USER_ONLY
4909 bool cpu_is_bsp(X86CPU
*cpu
)
4911 return cpu_get_apic_base(cpu
->apic_state
) & MSR_IA32_APICBASE_BSP
;
4914 /* TODO: remove me, when reset over QOM tree is implemented */
4915 static void x86_cpu_machine_reset_cb(void *opaque
)
4917 X86CPU
*cpu
= opaque
;
4918 cpu_reset(CPU(cpu
));
4922 static void mce_init(X86CPU
*cpu
)
4924 CPUX86State
*cenv
= &cpu
->env
;
4927 if (((cenv
->cpuid_version
>> 8) & 0xf) >= 6
4928 && (cenv
->features
[FEAT_1_EDX
] & (CPUID_MCE
| CPUID_MCA
)) ==
4929 (CPUID_MCE
| CPUID_MCA
)) {
4930 cenv
->mcg_cap
= MCE_CAP_DEF
| MCE_BANKS_DEF
|
4931 (cpu
->enable_lmce
? MCG_LMCE_P
: 0);
4932 cenv
->mcg_ctl
= ~(uint64_t)0;
4933 for (bank
= 0; bank
< MCE_BANKS_DEF
; bank
++) {
4934 cenv
->mce_banks
[bank
* 4] = ~(uint64_t)0;
4939 #ifndef CONFIG_USER_ONLY
4940 APICCommonClass
*apic_get_class(void)
4942 const char *apic_type
= "apic";
4944 /* TODO: in-kernel irqchip for hvf */
4945 if (kvm_apic_in_kernel()) {
4946 apic_type
= "kvm-apic";
4947 } else if (xen_enabled()) {
4948 apic_type
= "xen-apic";
4951 return APIC_COMMON_CLASS(object_class_by_name(apic_type
));
4954 static void x86_cpu_apic_create(X86CPU
*cpu
, Error
**errp
)
4956 APICCommonState
*apic
;
4957 ObjectClass
*apic_class
= OBJECT_CLASS(apic_get_class());
4959 cpu
->apic_state
= DEVICE(object_new(object_class_get_name(apic_class
)));
4961 object_property_add_child(OBJECT(cpu
), "lapic",
4962 OBJECT(cpu
->apic_state
), &error_abort
);
4963 object_unref(OBJECT(cpu
->apic_state
));
4965 qdev_prop_set_uint32(cpu
->apic_state
, "id", cpu
->apic_id
);
4966 /* TODO: convert to link<> */
4967 apic
= APIC_COMMON(cpu
->apic_state
);
4969 apic
->apicbase
= APIC_DEFAULT_ADDRESS
| MSR_IA32_APICBASE_ENABLE
;
4972 static void x86_cpu_apic_realize(X86CPU
*cpu
, Error
**errp
)
4974 APICCommonState
*apic
;
4975 static bool apic_mmio_map_once
;
4977 if (cpu
->apic_state
== NULL
) {
4980 object_property_set_bool(OBJECT(cpu
->apic_state
), true, "realized",
4983 /* Map APIC MMIO area */
4984 apic
= APIC_COMMON(cpu
->apic_state
);
4985 if (!apic_mmio_map_once
) {
4986 memory_region_add_subregion_overlap(get_system_memory(),
4988 MSR_IA32_APICBASE_BASE
,
4991 apic_mmio_map_once
= true;
4995 static void x86_cpu_machine_done(Notifier
*n
, void *unused
)
4997 X86CPU
*cpu
= container_of(n
, X86CPU
, machine_done
);
4998 MemoryRegion
*smram
=
4999 (MemoryRegion
*) object_resolve_path("/machine/smram", NULL
);
5002 cpu
->smram
= g_new(MemoryRegion
, 1);
5003 memory_region_init_alias(cpu
->smram
, OBJECT(cpu
), "smram",
5004 smram
, 0, 1ull << 32);
5005 memory_region_set_enabled(cpu
->smram
, true);
5006 memory_region_add_subregion_overlap(cpu
->cpu_as_root
, 0, cpu
->smram
, 1);
5010 static void x86_cpu_apic_realize(X86CPU
*cpu
, Error
**errp
)
5015 /* Note: Only safe for use on x86(-64) hosts */
5016 static uint32_t x86_host_phys_bits(void)
5019 uint32_t host_phys_bits
;
5021 host_cpuid(0x80000000, 0, &eax
, NULL
, NULL
, NULL
);
5022 if (eax
>= 0x80000008) {
5023 host_cpuid(0x80000008, 0, &eax
, NULL
, NULL
, NULL
);
5024 /* Note: According to AMD doc 25481 rev 2.34 they have a field
5025 * at 23:16 that can specify a maximum physical address bits for
5026 * the guest that can override this value; but I've not seen
5027 * anything with that set.
5029 host_phys_bits
= eax
& 0xff;
5031 /* It's an odd 64 bit machine that doesn't have the leaf for
5032 * physical address bits; fall back to 36 that's most older
5035 host_phys_bits
= 36;
5038 return host_phys_bits
;
5041 static void x86_cpu_adjust_level(X86CPU
*cpu
, uint32_t *min
, uint32_t value
)
5048 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
5049 static void x86_cpu_adjust_feat_level(X86CPU
*cpu
, FeatureWord w
)
5051 CPUX86State
*env
= &cpu
->env
;
5052 FeatureWordInfo
*fi
= &feature_word_info
[w
];
5053 uint32_t eax
= fi
->cpuid
.eax
;
5054 uint32_t region
= eax
& 0xF0000000;
5056 assert(feature_word_info
[w
].type
== CPUID_FEATURE_WORD
);
5057 if (!env
->features
[w
]) {
5063 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_level
, eax
);
5066 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel
, eax
);
5069 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel2
, eax
);
5074 /* Calculate XSAVE components based on the configured CPU feature flags */
5075 static void x86_cpu_enable_xsave_components(X86CPU
*cpu
)
5077 CPUX86State
*env
= &cpu
->env
;
5081 if (!(env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
)) {
5086 for (i
= 0; i
< ARRAY_SIZE(x86_ext_save_areas
); i
++) {
5087 const ExtSaveArea
*esa
= &x86_ext_save_areas
[i
];
5088 if (env
->features
[esa
->feature
] & esa
->bits
) {
5089 mask
|= (1ULL << i
);
5093 env
->features
[FEAT_XSAVE_COMP_LO
] = mask
;
5094 env
->features
[FEAT_XSAVE_COMP_HI
] = mask
>> 32;
5097 /***** Steps involved on loading and filtering CPUID data
5099 * When initializing and realizing a CPU object, the steps
5100 * involved in setting up CPUID data are:
5102 * 1) Loading CPU model definition (X86CPUDefinition). This is
5103 * implemented by x86_cpu_load_def() and should be completely
5104 * transparent, as it is done automatically by instance_init.
5105 * No code should need to look at X86CPUDefinition structs
5106 * outside instance_init.
5108 * 2) CPU expansion. This is done by realize before CPUID
5109 * filtering, and will make sure host/accelerator data is
5110 * loaded for CPU models that depend on host capabilities
5111 * (e.g. "host"). Done by x86_cpu_expand_features().
5113 * 3) CPUID filtering. This initializes extra data related to
5114 * CPUID, and checks if the host supports all capabilities
5115 * required by the CPU. Runnability of a CPU model is
5116 * determined at this step. Done by x86_cpu_filter_features().
5118 * Some operations don't require all steps to be performed.
5121 * - CPU instance creation (instance_init) will run only CPU
5122 * model loading. CPU expansion can't run at instance_init-time
5123 * because host/accelerator data may be not available yet.
5124 * - CPU realization will perform both CPU model expansion and CPUID
5125 * filtering, and return an error in case one of them fails.
5126 * - query-cpu-definitions needs to run all 3 steps. It needs
5127 * to run CPUID filtering, as the 'unavailable-features'
5128 * field is set based on the filtering results.
5129 * - The query-cpu-model-expansion QMP command only needs to run
5130 * CPU model loading and CPU expansion. It should not filter
5131 * any CPUID data based on host capabilities.
5134 /* Expand CPU configuration data, based on configured features
5135 * and host/accelerator capabilities when appropriate.
5137 static void x86_cpu_expand_features(X86CPU
*cpu
, Error
**errp
)
5139 CPUX86State
*env
= &cpu
->env
;
5142 Error
*local_err
= NULL
;
5144 /*TODO: Now cpu->max_features doesn't overwrite features
5145 * set using QOM properties, and we can convert
5146 * plus_features & minus_features to global properties
5147 * inside x86_cpu_parse_featurestr() too.
5149 if (cpu
->max_features
) {
5150 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
5151 /* Override only features that weren't set explicitly
5155 x86_cpu_get_supported_feature_word(w
, cpu
->migratable
) &
5156 ~env
->user_features
[w
] & \
5157 ~feature_word_info
[w
].no_autoenable_flags
;
5161 for (l
= plus_features
; l
; l
= l
->next
) {
5162 const char *prop
= l
->data
;
5163 object_property_set_bool(OBJECT(cpu
), true, prop
, &local_err
);
5169 for (l
= minus_features
; l
; l
= l
->next
) {
5170 const char *prop
= l
->data
;
5171 object_property_set_bool(OBJECT(cpu
), false, prop
, &local_err
);
5177 if (!kvm_enabled() || !cpu
->expose_kvm
) {
5178 env
->features
[FEAT_KVM
] = 0;
5181 x86_cpu_enable_xsave_components(cpu
);
5183 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
5184 x86_cpu_adjust_feat_level(cpu
, FEAT_7_0_EBX
);
5185 if (cpu
->full_cpuid_auto_level
) {
5186 x86_cpu_adjust_feat_level(cpu
, FEAT_1_EDX
);
5187 x86_cpu_adjust_feat_level(cpu
, FEAT_1_ECX
);
5188 x86_cpu_adjust_feat_level(cpu
, FEAT_6_EAX
);
5189 x86_cpu_adjust_feat_level(cpu
, FEAT_7_0_ECX
);
5190 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0001_EDX
);
5191 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0001_ECX
);
5192 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0007_EDX
);
5193 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0008_EBX
);
5194 x86_cpu_adjust_feat_level(cpu
, FEAT_C000_0001_EDX
);
5195 x86_cpu_adjust_feat_level(cpu
, FEAT_SVM
);
5196 x86_cpu_adjust_feat_level(cpu
, FEAT_XSAVE
);
5198 /* Intel Processor Trace requires CPUID[0x14] */
5199 if ((env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_INTEL_PT
) &&
5200 kvm_enabled() && cpu
->intel_pt_auto_level
) {
5201 x86_cpu_adjust_level(cpu
, &cpu
->env
.cpuid_min_level
, 0x14);
5204 /* CPU topology with multi-dies support requires CPUID[0x1F] */
5205 if (env
->nr_dies
> 1) {
5206 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_level
, 0x1F);
5209 /* SVM requires CPUID[0x8000000A] */
5210 if (env
->features
[FEAT_8000_0001_ECX
] & CPUID_EXT3_SVM
) {
5211 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel
, 0x8000000A);
5214 /* SEV requires CPUID[0x8000001F] */
5215 if (sev_enabled()) {
5216 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel
, 0x8000001F);
5220 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
5221 if (env
->cpuid_level
== UINT32_MAX
) {
5222 env
->cpuid_level
= env
->cpuid_min_level
;
5224 if (env
->cpuid_xlevel
== UINT32_MAX
) {
5225 env
->cpuid_xlevel
= env
->cpuid_min_xlevel
;
5227 if (env
->cpuid_xlevel2
== UINT32_MAX
) {
5228 env
->cpuid_xlevel2
= env
->cpuid_min_xlevel2
;
5232 if (local_err
!= NULL
) {
5233 error_propagate(errp
, local_err
);
5238 * Finishes initialization of CPUID data, filters CPU feature
5239 * words based on host availability of each feature.
5241 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
5243 static int x86_cpu_filter_features(X86CPU
*cpu
)
5245 CPUX86State
*env
= &cpu
->env
;
5249 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
5250 uint32_t host_feat
=
5251 x86_cpu_get_supported_feature_word(w
, false);
5252 uint32_t requested_features
= env
->features
[w
];
5253 env
->features
[w
] &= host_feat
;
5254 cpu
->filtered_features
[w
] = requested_features
& ~env
->features
[w
];
5255 if (cpu
->filtered_features
[w
]) {
5260 if ((env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_INTEL_PT
) &&
5262 KVMState
*s
= CPU(cpu
)->kvm_state
;
5263 uint32_t eax_0
= kvm_arch_get_supported_cpuid(s
, 0x14, 0, R_EAX
);
5264 uint32_t ebx_0
= kvm_arch_get_supported_cpuid(s
, 0x14, 0, R_EBX
);
5265 uint32_t ecx_0
= kvm_arch_get_supported_cpuid(s
, 0x14, 0, R_ECX
);
5266 uint32_t eax_1
= kvm_arch_get_supported_cpuid(s
, 0x14, 1, R_EAX
);
5267 uint32_t ebx_1
= kvm_arch_get_supported_cpuid(s
, 0x14, 1, R_EBX
);
5270 ((ebx_0
& INTEL_PT_MINIMAL_EBX
) != INTEL_PT_MINIMAL_EBX
) ||
5271 ((ecx_0
& INTEL_PT_MINIMAL_ECX
) != INTEL_PT_MINIMAL_ECX
) ||
5272 ((eax_1
& INTEL_PT_MTC_BITMAP
) != INTEL_PT_MTC_BITMAP
) ||
5273 ((eax_1
& INTEL_PT_ADDR_RANGES_NUM_MASK
) <
5274 INTEL_PT_ADDR_RANGES_NUM
) ||
5275 ((ebx_1
& (INTEL_PT_PSB_BITMAP
| INTEL_PT_CYCLE_BITMAP
)) !=
5276 (INTEL_PT_PSB_BITMAP
| INTEL_PT_CYCLE_BITMAP
)) ||
5277 (ecx_0
& INTEL_PT_IP_LIP
)) {
5279 * Processor Trace capabilities aren't configurable, so if the
5280 * host can't emulate the capabilities we report on
5281 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
5283 env
->features
[FEAT_7_0_EBX
] &= ~CPUID_7_0_EBX_INTEL_PT
;
5284 cpu
->filtered_features
[FEAT_7_0_EBX
] |= CPUID_7_0_EBX_INTEL_PT
;
5292 static void x86_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
5294 CPUState
*cs
= CPU(dev
);
5295 X86CPU
*cpu
= X86_CPU(dev
);
5296 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(dev
);
5297 CPUX86State
*env
= &cpu
->env
;
5298 Error
*local_err
= NULL
;
5299 static bool ht_warned
;
5301 if (xcc
->host_cpuid_required
) {
5302 if (!accel_uses_host_cpuid()) {
5303 char *name
= x86_cpu_class_get_model_name(xcc
);
5304 error_setg(&local_err
, "CPU model '%s' requires KVM", name
);
5309 if (enable_cpu_pm
) {
5310 host_cpuid(5, 0, &cpu
->mwait
.eax
, &cpu
->mwait
.ebx
,
5311 &cpu
->mwait
.ecx
, &cpu
->mwait
.edx
);
5312 env
->features
[FEAT_1_ECX
] |= CPUID_EXT_MONITOR
;
5316 /* mwait extended info: needed for Core compatibility */
5317 /* We always wake on interrupt even if host does not have the capability */
5318 cpu
->mwait
.ecx
|= CPUID_MWAIT_EMX
| CPUID_MWAIT_IBE
;
5320 if (cpu
->apic_id
== UNASSIGNED_APIC_ID
) {
5321 error_setg(errp
, "apic-id property was not initialized properly");
5325 x86_cpu_expand_features(cpu
, &local_err
);
5330 if (x86_cpu_filter_features(cpu
) &&
5331 (cpu
->check_cpuid
|| cpu
->enforce_cpuid
)) {
5332 x86_cpu_report_filtered_features(cpu
);
5333 if (cpu
->enforce_cpuid
) {
5334 error_setg(&local_err
,
5335 accel_uses_host_cpuid() ?
5336 "Host doesn't support requested features" :
5337 "TCG doesn't support requested features");
5342 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
5345 if (IS_AMD_CPU(env
)) {
5346 env
->features
[FEAT_8000_0001_EDX
] &= ~CPUID_EXT2_AMD_ALIASES
;
5347 env
->features
[FEAT_8000_0001_EDX
] |= (env
->features
[FEAT_1_EDX
]
5348 & CPUID_EXT2_AMD_ALIASES
);
5351 /* For 64bit systems think about the number of physical bits to present.
5352 * ideally this should be the same as the host; anything other than matching
5353 * the host can cause incorrect guest behaviour.
5354 * QEMU used to pick the magic value of 40 bits that corresponds to
5355 * consumer AMD devices but nothing else.
5357 if (env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
) {
5358 if (accel_uses_host_cpuid()) {
5359 uint32_t host_phys_bits
= x86_host_phys_bits();
5362 /* Print a warning if the user set it to a value that's not the
5365 if (cpu
->phys_bits
!= host_phys_bits
&& cpu
->phys_bits
!= 0 &&
5367 warn_report("Host physical bits (%u)"
5368 " does not match phys-bits property (%u)",
5369 host_phys_bits
, cpu
->phys_bits
);
5373 if (cpu
->host_phys_bits
) {
5374 /* The user asked for us to use the host physical bits */
5375 cpu
->phys_bits
= host_phys_bits
;
5376 if (cpu
->host_phys_bits_limit
&&
5377 cpu
->phys_bits
> cpu
->host_phys_bits_limit
) {
5378 cpu
->phys_bits
= cpu
->host_phys_bits_limit
;
5382 if (cpu
->phys_bits
&&
5383 (cpu
->phys_bits
> TARGET_PHYS_ADDR_SPACE_BITS
||
5384 cpu
->phys_bits
< 32)) {
5385 error_setg(errp
, "phys-bits should be between 32 and %u "
5387 TARGET_PHYS_ADDR_SPACE_BITS
, cpu
->phys_bits
);
5391 if (cpu
->phys_bits
&& cpu
->phys_bits
!= TCG_PHYS_ADDR_BITS
) {
5392 error_setg(errp
, "TCG only supports phys-bits=%u",
5393 TCG_PHYS_ADDR_BITS
);
5397 /* 0 means it was not explicitly set by the user (or by machine
5398 * compat_props or by the host code above). In this case, the default
5399 * is the value used by TCG (40).
5401 if (cpu
->phys_bits
== 0) {
5402 cpu
->phys_bits
= TCG_PHYS_ADDR_BITS
;
5405 /* For 32 bit systems don't use the user set value, but keep
5406 * phys_bits consistent with what we tell the guest.
5408 if (cpu
->phys_bits
!= 0) {
5409 error_setg(errp
, "phys-bits is not user-configurable in 32 bit");
5413 if (env
->features
[FEAT_1_EDX
] & CPUID_PSE36
) {
5414 cpu
->phys_bits
= 36;
5416 cpu
->phys_bits
= 32;
5420 /* Cache information initialization */
5421 if (!cpu
->legacy_cache
) {
5422 if (!xcc
->cpu_def
|| !xcc
->cpu_def
->cache_info
) {
5423 char *name
= x86_cpu_class_get_model_name(xcc
);
5425 "CPU model '%s' doesn't support legacy-cache=off", name
);
5429 env
->cache_info_cpuid2
= env
->cache_info_cpuid4
= env
->cache_info_amd
=
5430 *xcc
->cpu_def
->cache_info
;
5432 /* Build legacy cache information */
5433 env
->cache_info_cpuid2
.l1d_cache
= &legacy_l1d_cache
;
5434 env
->cache_info_cpuid2
.l1i_cache
= &legacy_l1i_cache
;
5435 env
->cache_info_cpuid2
.l2_cache
= &legacy_l2_cache_cpuid2
;
5436 env
->cache_info_cpuid2
.l3_cache
= &legacy_l3_cache
;
5438 env
->cache_info_cpuid4
.l1d_cache
= &legacy_l1d_cache
;
5439 env
->cache_info_cpuid4
.l1i_cache
= &legacy_l1i_cache
;
5440 env
->cache_info_cpuid4
.l2_cache
= &legacy_l2_cache
;
5441 env
->cache_info_cpuid4
.l3_cache
= &legacy_l3_cache
;
5443 env
->cache_info_amd
.l1d_cache
= &legacy_l1d_cache_amd
;
5444 env
->cache_info_amd
.l1i_cache
= &legacy_l1i_cache_amd
;
5445 env
->cache_info_amd
.l2_cache
= &legacy_l2_cache_amd
;
5446 env
->cache_info_amd
.l3_cache
= &legacy_l3_cache
;
5450 cpu_exec_realizefn(cs
, &local_err
);
5451 if (local_err
!= NULL
) {
5452 error_propagate(errp
, local_err
);
5456 #ifndef CONFIG_USER_ONLY
5457 MachineState
*ms
= MACHINE(qdev_get_machine());
5458 qemu_register_reset(x86_cpu_machine_reset_cb
, cpu
);
5460 if (cpu
->env
.features
[FEAT_1_EDX
] & CPUID_APIC
|| ms
->smp
.cpus
> 1) {
5461 x86_cpu_apic_create(cpu
, &local_err
);
5462 if (local_err
!= NULL
) {
5470 #ifndef CONFIG_USER_ONLY
5471 if (tcg_enabled()) {
5472 cpu
->cpu_as_mem
= g_new(MemoryRegion
, 1);
5473 cpu
->cpu_as_root
= g_new(MemoryRegion
, 1);
5475 /* Outer container... */
5476 memory_region_init(cpu
->cpu_as_root
, OBJECT(cpu
), "memory", ~0ull);
5477 memory_region_set_enabled(cpu
->cpu_as_root
, true);
5479 /* ... with two regions inside: normal system memory with low
5482 memory_region_init_alias(cpu
->cpu_as_mem
, OBJECT(cpu
), "memory",
5483 get_system_memory(), 0, ~0ull);
5484 memory_region_add_subregion_overlap(cpu
->cpu_as_root
, 0, cpu
->cpu_as_mem
, 0);
5485 memory_region_set_enabled(cpu
->cpu_as_mem
, true);
5488 cpu_address_space_init(cs
, 0, "cpu-memory", cs
->memory
);
5489 cpu_address_space_init(cs
, 1, "cpu-smm", cpu
->cpu_as_root
);
5491 /* ... SMRAM with higher priority, linked from /machine/smram. */
5492 cpu
->machine_done
.notify
= x86_cpu_machine_done
;
5493 qemu_add_machine_init_done_notifier(&cpu
->machine_done
);
5500 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
5501 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
5502 * based on inputs (sockets,cores,threads), it is still better to give
5505 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
5506 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
5508 if (IS_AMD_CPU(env
) &&
5509 !(env
->features
[FEAT_8000_0001_ECX
] & CPUID_EXT3_TOPOEXT
) &&
5510 cs
->nr_threads
> 1 && !ht_warned
) {
5511 warn_report("This family of AMD CPU doesn't support "
5512 "hyperthreading(%d)",
5514 error_printf("Please configure -smp options properly"
5515 " or try enabling topoext feature.\n");
5519 x86_cpu_apic_realize(cpu
, &local_err
);
5520 if (local_err
!= NULL
) {
5525 xcc
->parent_realize(dev
, &local_err
);
5528 if (local_err
!= NULL
) {
5529 error_propagate(errp
, local_err
);
5534 static void x86_cpu_unrealizefn(DeviceState
*dev
, Error
**errp
)
5536 X86CPU
*cpu
= X86_CPU(dev
);
5537 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(dev
);
5538 Error
*local_err
= NULL
;
5540 #ifndef CONFIG_USER_ONLY
5541 cpu_remove_sync(CPU(dev
));
5542 qemu_unregister_reset(x86_cpu_machine_reset_cb
, dev
);
5545 if (cpu
->apic_state
) {
5546 object_unparent(OBJECT(cpu
->apic_state
));
5547 cpu
->apic_state
= NULL
;
5550 xcc
->parent_unrealize(dev
, &local_err
);
5551 if (local_err
!= NULL
) {
5552 error_propagate(errp
, local_err
);
5557 typedef struct BitProperty
{
5562 static void x86_cpu_get_bit_prop(Object
*obj
, Visitor
*v
, const char *name
,
5563 void *opaque
, Error
**errp
)
5565 X86CPU
*cpu
= X86_CPU(obj
);
5566 BitProperty
*fp
= opaque
;
5567 uint32_t f
= cpu
->env
.features
[fp
->w
];
5568 bool value
= (f
& fp
->mask
) == fp
->mask
;
5569 visit_type_bool(v
, name
, &value
, errp
);
5572 static void x86_cpu_set_bit_prop(Object
*obj
, Visitor
*v
, const char *name
,
5573 void *opaque
, Error
**errp
)
5575 DeviceState
*dev
= DEVICE(obj
);
5576 X86CPU
*cpu
= X86_CPU(obj
);
5577 BitProperty
*fp
= opaque
;
5578 Error
*local_err
= NULL
;
5581 if (dev
->realized
) {
5582 qdev_prop_set_after_realize(dev
, name
, errp
);
5586 visit_type_bool(v
, name
, &value
, &local_err
);
5588 error_propagate(errp
, local_err
);
5593 cpu
->env
.features
[fp
->w
] |= fp
->mask
;
5595 cpu
->env
.features
[fp
->w
] &= ~fp
->mask
;
5597 cpu
->env
.user_features
[fp
->w
] |= fp
->mask
;
5600 static void x86_cpu_release_bit_prop(Object
*obj
, const char *name
,
5603 BitProperty
*prop
= opaque
;
5607 /* Register a boolean property to get/set a single bit in a uint32_t field.
5609 * The same property name can be registered multiple times to make it affect
5610 * multiple bits in the same FeatureWord. In that case, the getter will return
5611 * true only if all bits are set.
5613 static void x86_cpu_register_bit_prop(X86CPU
*cpu
,
5614 const char *prop_name
,
5620 uint32_t mask
= (1UL << bitnr
);
5622 op
= object_property_find(OBJECT(cpu
), prop_name
, NULL
);
5628 fp
= g_new0(BitProperty
, 1);
5631 object_property_add(OBJECT(cpu
), prop_name
, "bool",
5632 x86_cpu_get_bit_prop
,
5633 x86_cpu_set_bit_prop
,
5634 x86_cpu_release_bit_prop
, fp
, &error_abort
);
5638 static void x86_cpu_register_feature_bit_props(X86CPU
*cpu
,
5642 FeatureWordInfo
*fi
= &feature_word_info
[w
];
5643 const char *name
= fi
->feat_names
[bitnr
];
5649 /* Property names should use "-" instead of "_".
5650 * Old names containing underscores are registered as aliases
5651 * using object_property_add_alias()
5653 assert(!strchr(name
, '_'));
5654 /* aliases don't use "|" delimiters anymore, they are registered
5655 * manually using object_property_add_alias() */
5656 assert(!strchr(name
, '|'));
5657 x86_cpu_register_bit_prop(cpu
, name
, w
, bitnr
);
5660 static GuestPanicInformation
*x86_cpu_get_crash_info(CPUState
*cs
)
5662 X86CPU
*cpu
= X86_CPU(cs
);
5663 CPUX86State
*env
= &cpu
->env
;
5664 GuestPanicInformation
*panic_info
= NULL
;
5666 if (env
->features
[FEAT_HYPERV_EDX
] & HV_GUEST_CRASH_MSR_AVAILABLE
) {
5667 panic_info
= g_malloc0(sizeof(GuestPanicInformation
));
5669 panic_info
->type
= GUEST_PANIC_INFORMATION_TYPE_HYPER_V
;
5671 assert(HV_CRASH_PARAMS
>= 5);
5672 panic_info
->u
.hyper_v
.arg1
= env
->msr_hv_crash_params
[0];
5673 panic_info
->u
.hyper_v
.arg2
= env
->msr_hv_crash_params
[1];
5674 panic_info
->u
.hyper_v
.arg3
= env
->msr_hv_crash_params
[2];
5675 panic_info
->u
.hyper_v
.arg4
= env
->msr_hv_crash_params
[3];
5676 panic_info
->u
.hyper_v
.arg5
= env
->msr_hv_crash_params
[4];
5681 static void x86_cpu_get_crash_info_qom(Object
*obj
, Visitor
*v
,
5682 const char *name
, void *opaque
,
5685 CPUState
*cs
= CPU(obj
);
5686 GuestPanicInformation
*panic_info
;
5688 if (!cs
->crash_occurred
) {
5689 error_setg(errp
, "No crash occured");
5693 panic_info
= x86_cpu_get_crash_info(cs
);
5694 if (panic_info
== NULL
) {
5695 error_setg(errp
, "No crash information");
5699 visit_type_GuestPanicInformation(v
, "crash-information", &panic_info
,
5701 qapi_free_GuestPanicInformation(panic_info
);
5704 static void x86_cpu_initfn(Object
*obj
)
5706 X86CPU
*cpu
= X86_CPU(obj
);
5707 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(obj
);
5708 CPUX86State
*env
= &cpu
->env
;
5712 cpu_set_cpustate_pointers(cpu
);
5714 object_property_add(obj
, "family", "int",
5715 x86_cpuid_version_get_family
,
5716 x86_cpuid_version_set_family
, NULL
, NULL
, NULL
);
5717 object_property_add(obj
, "model", "int",
5718 x86_cpuid_version_get_model
,
5719 x86_cpuid_version_set_model
, NULL
, NULL
, NULL
);
5720 object_property_add(obj
, "stepping", "int",
5721 x86_cpuid_version_get_stepping
,
5722 x86_cpuid_version_set_stepping
, NULL
, NULL
, NULL
);
5723 object_property_add_str(obj
, "vendor",
5724 x86_cpuid_get_vendor
,
5725 x86_cpuid_set_vendor
, NULL
);
5726 object_property_add_str(obj
, "model-id",
5727 x86_cpuid_get_model_id
,
5728 x86_cpuid_set_model_id
, NULL
);
5729 object_property_add(obj
, "tsc-frequency", "int",
5730 x86_cpuid_get_tsc_freq
,
5731 x86_cpuid_set_tsc_freq
, NULL
, NULL
, NULL
);
5732 object_property_add(obj
, "feature-words", "X86CPUFeatureWordInfo",
5733 x86_cpu_get_feature_words
,
5734 NULL
, NULL
, (void *)env
->features
, NULL
);
5735 object_property_add(obj
, "filtered-features", "X86CPUFeatureWordInfo",
5736 x86_cpu_get_feature_words
,
5737 NULL
, NULL
, (void *)cpu
->filtered_features
, NULL
);
5739 * The "unavailable-features" property has the same semantics as
5740 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions"
5741 * QMP command: they list the features that would have prevented the
5742 * CPU from running if the "enforce" flag was set.
5744 object_property_add(obj
, "unavailable-features", "strList",
5745 x86_cpu_get_unavailable_features
,
5746 NULL
, NULL
, NULL
, &error_abort
);
5748 object_property_add(obj
, "crash-information", "GuestPanicInformation",
5749 x86_cpu_get_crash_info_qom
, NULL
, NULL
, NULL
, NULL
);
5751 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
5754 for (bitnr
= 0; bitnr
< 32; bitnr
++) {
5755 x86_cpu_register_feature_bit_props(cpu
, w
, bitnr
);
5759 object_property_add_alias(obj
, "sse3", obj
, "pni", &error_abort
);
5760 object_property_add_alias(obj
, "pclmuldq", obj
, "pclmulqdq", &error_abort
);
5761 object_property_add_alias(obj
, "sse4-1", obj
, "sse4.1", &error_abort
);
5762 object_property_add_alias(obj
, "sse4-2", obj
, "sse4.2", &error_abort
);
5763 object_property_add_alias(obj
, "xd", obj
, "nx", &error_abort
);
5764 object_property_add_alias(obj
, "ffxsr", obj
, "fxsr-opt", &error_abort
);
5765 object_property_add_alias(obj
, "i64", obj
, "lm", &error_abort
);
5767 object_property_add_alias(obj
, "ds_cpl", obj
, "ds-cpl", &error_abort
);
5768 object_property_add_alias(obj
, "tsc_adjust", obj
, "tsc-adjust", &error_abort
);
5769 object_property_add_alias(obj
, "fxsr_opt", obj
, "fxsr-opt", &error_abort
);
5770 object_property_add_alias(obj
, "lahf_lm", obj
, "lahf-lm", &error_abort
);
5771 object_property_add_alias(obj
, "cmp_legacy", obj
, "cmp-legacy", &error_abort
);
5772 object_property_add_alias(obj
, "nodeid_msr", obj
, "nodeid-msr", &error_abort
);
5773 object_property_add_alias(obj
, "perfctr_core", obj
, "perfctr-core", &error_abort
);
5774 object_property_add_alias(obj
, "perfctr_nb", obj
, "perfctr-nb", &error_abort
);
5775 object_property_add_alias(obj
, "kvm_nopiodelay", obj
, "kvm-nopiodelay", &error_abort
);
5776 object_property_add_alias(obj
, "kvm_mmu", obj
, "kvm-mmu", &error_abort
);
5777 object_property_add_alias(obj
, "kvm_asyncpf", obj
, "kvm-asyncpf", &error_abort
);
5778 object_property_add_alias(obj
, "kvm_steal_time", obj
, "kvm-steal-time", &error_abort
);
5779 object_property_add_alias(obj
, "kvm_pv_eoi", obj
, "kvm-pv-eoi", &error_abort
);
5780 object_property_add_alias(obj
, "kvm_pv_unhalt", obj
, "kvm-pv-unhalt", &error_abort
);
5781 object_property_add_alias(obj
, "svm_lock", obj
, "svm-lock", &error_abort
);
5782 object_property_add_alias(obj
, "nrip_save", obj
, "nrip-save", &error_abort
);
5783 object_property_add_alias(obj
, "tsc_scale", obj
, "tsc-scale", &error_abort
);
5784 object_property_add_alias(obj
, "vmcb_clean", obj
, "vmcb-clean", &error_abort
);
5785 object_property_add_alias(obj
, "pause_filter", obj
, "pause-filter", &error_abort
);
5786 object_property_add_alias(obj
, "sse4_1", obj
, "sse4.1", &error_abort
);
5787 object_property_add_alias(obj
, "sse4_2", obj
, "sse4.2", &error_abort
);
5790 x86_cpu_load_def(cpu
, xcc
->cpu_def
, &error_abort
);
5794 static int64_t x86_cpu_get_arch_id(CPUState
*cs
)
5796 X86CPU
*cpu
= X86_CPU(cs
);
5798 return cpu
->apic_id
;
5801 static bool x86_cpu_get_paging_enabled(const CPUState
*cs
)
5803 X86CPU
*cpu
= X86_CPU(cs
);
5805 return cpu
->env
.cr
[0] & CR0_PG_MASK
;
5808 static void x86_cpu_set_pc(CPUState
*cs
, vaddr value
)
5810 X86CPU
*cpu
= X86_CPU(cs
);
5812 cpu
->env
.eip
= value
;
5815 static void x86_cpu_synchronize_from_tb(CPUState
*cs
, TranslationBlock
*tb
)
5817 X86CPU
*cpu
= X86_CPU(cs
);
5819 cpu
->env
.eip
= tb
->pc
- tb
->cs_base
;
5822 int x86_cpu_pending_interrupt(CPUState
*cs
, int interrupt_request
)
5824 X86CPU
*cpu
= X86_CPU(cs
);
5825 CPUX86State
*env
= &cpu
->env
;
5827 #if !defined(CONFIG_USER_ONLY)
5828 if (interrupt_request
& CPU_INTERRUPT_POLL
) {
5829 return CPU_INTERRUPT_POLL
;
5832 if (interrupt_request
& CPU_INTERRUPT_SIPI
) {
5833 return CPU_INTERRUPT_SIPI
;
5836 if (env
->hflags2
& HF2_GIF_MASK
) {
5837 if ((interrupt_request
& CPU_INTERRUPT_SMI
) &&
5838 !(env
->hflags
& HF_SMM_MASK
)) {
5839 return CPU_INTERRUPT_SMI
;
5840 } else if ((interrupt_request
& CPU_INTERRUPT_NMI
) &&
5841 !(env
->hflags2
& HF2_NMI_MASK
)) {
5842 return CPU_INTERRUPT_NMI
;
5843 } else if (interrupt_request
& CPU_INTERRUPT_MCE
) {
5844 return CPU_INTERRUPT_MCE
;
5845 } else if ((interrupt_request
& CPU_INTERRUPT_HARD
) &&
5846 (((env
->hflags2
& HF2_VINTR_MASK
) &&
5847 (env
->hflags2
& HF2_HIF_MASK
)) ||
5848 (!(env
->hflags2
& HF2_VINTR_MASK
) &&
5849 (env
->eflags
& IF_MASK
&&
5850 !(env
->hflags
& HF_INHIBIT_IRQ_MASK
))))) {
5851 return CPU_INTERRUPT_HARD
;
5852 #if !defined(CONFIG_USER_ONLY)
5853 } else if ((interrupt_request
& CPU_INTERRUPT_VIRQ
) &&
5854 (env
->eflags
& IF_MASK
) &&
5855 !(env
->hflags
& HF_INHIBIT_IRQ_MASK
)) {
5856 return CPU_INTERRUPT_VIRQ
;
5864 static bool x86_cpu_has_work(CPUState
*cs
)
5866 return x86_cpu_pending_interrupt(cs
, cs
->interrupt_request
) != 0;
5869 static void x86_disas_set_info(CPUState
*cs
, disassemble_info
*info
)
5871 X86CPU
*cpu
= X86_CPU(cs
);
5872 CPUX86State
*env
= &cpu
->env
;
5874 info
->mach
= (env
->hflags
& HF_CS64_MASK
? bfd_mach_x86_64
5875 : env
->hflags
& HF_CS32_MASK
? bfd_mach_i386_i386
5876 : bfd_mach_i386_i8086
);
5877 info
->print_insn
= print_insn_i386
;
5879 info
->cap_arch
= CS_ARCH_X86
;
5880 info
->cap_mode
= (env
->hflags
& HF_CS64_MASK
? CS_MODE_64
5881 : env
->hflags
& HF_CS32_MASK
? CS_MODE_32
5883 info
->cap_insn_unit
= 1;
5884 info
->cap_insn_split
= 8;
5887 void x86_update_hflags(CPUX86State
*env
)
5890 #define HFLAG_COPY_MASK \
5891 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
5892 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
5893 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
5894 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
5896 hflags
= env
->hflags
& HFLAG_COPY_MASK
;
5897 hflags
|= (env
->segs
[R_SS
].flags
>> DESC_DPL_SHIFT
) & HF_CPL_MASK
;
5898 hflags
|= (env
->cr
[0] & CR0_PE_MASK
) << (HF_PE_SHIFT
- CR0_PE_SHIFT
);
5899 hflags
|= (env
->cr
[0] << (HF_MP_SHIFT
- CR0_MP_SHIFT
)) &
5900 (HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
);
5901 hflags
|= (env
->eflags
& (HF_TF_MASK
| HF_VM_MASK
| HF_IOPL_MASK
));
5903 if (env
->cr
[4] & CR4_OSFXSR_MASK
) {
5904 hflags
|= HF_OSFXSR_MASK
;
5907 if (env
->efer
& MSR_EFER_LMA
) {
5908 hflags
|= HF_LMA_MASK
;
5911 if ((hflags
& HF_LMA_MASK
) && (env
->segs
[R_CS
].flags
& DESC_L_MASK
)) {
5912 hflags
|= HF_CS32_MASK
| HF_SS32_MASK
| HF_CS64_MASK
;
5914 hflags
|= (env
->segs
[R_CS
].flags
& DESC_B_MASK
) >>
5915 (DESC_B_SHIFT
- HF_CS32_SHIFT
);
5916 hflags
|= (env
->segs
[R_SS
].flags
& DESC_B_MASK
) >>
5917 (DESC_B_SHIFT
- HF_SS32_SHIFT
);
5918 if (!(env
->cr
[0] & CR0_PE_MASK
) || (env
->eflags
& VM_MASK
) ||
5919 !(hflags
& HF_CS32_MASK
)) {
5920 hflags
|= HF_ADDSEG_MASK
;
5922 hflags
|= ((env
->segs
[R_DS
].base
| env
->segs
[R_ES
].base
|
5923 env
->segs
[R_SS
].base
) != 0) << HF_ADDSEG_SHIFT
;
5926 env
->hflags
= hflags
;
5929 static Property x86_cpu_properties
[] = {
5930 #ifdef CONFIG_USER_ONLY
5931 /* apic_id = 0 by default for *-user, see commit 9886e834 */
5932 DEFINE_PROP_UINT32("apic-id", X86CPU
, apic_id
, 0),
5933 DEFINE_PROP_INT32("thread-id", X86CPU
, thread_id
, 0),
5934 DEFINE_PROP_INT32("core-id", X86CPU
, core_id
, 0),
5935 DEFINE_PROP_INT32("die-id", X86CPU
, die_id
, 0),
5936 DEFINE_PROP_INT32("socket-id", X86CPU
, socket_id
, 0),
5938 DEFINE_PROP_UINT32("apic-id", X86CPU
, apic_id
, UNASSIGNED_APIC_ID
),
5939 DEFINE_PROP_INT32("thread-id", X86CPU
, thread_id
, -1),
5940 DEFINE_PROP_INT32("core-id", X86CPU
, core_id
, -1),
5941 DEFINE_PROP_INT32("die-id", X86CPU
, die_id
, -1),
5942 DEFINE_PROP_INT32("socket-id", X86CPU
, socket_id
, -1),
5944 DEFINE_PROP_INT32("node-id", X86CPU
, node_id
, CPU_UNSET_NUMA_NODE_ID
),
5945 DEFINE_PROP_BOOL("pmu", X86CPU
, enable_pmu
, false),
5947 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU
, hyperv_spinlock_attempts
,
5948 HYPERV_SPINLOCK_NEVER_RETRY
),
5949 DEFINE_PROP_BIT64("hv-relaxed", X86CPU
, hyperv_features
,
5950 HYPERV_FEAT_RELAXED
, 0),
5951 DEFINE_PROP_BIT64("hv-vapic", X86CPU
, hyperv_features
,
5952 HYPERV_FEAT_VAPIC
, 0),
5953 DEFINE_PROP_BIT64("hv-time", X86CPU
, hyperv_features
,
5954 HYPERV_FEAT_TIME
, 0),
5955 DEFINE_PROP_BIT64("hv-crash", X86CPU
, hyperv_features
,
5956 HYPERV_FEAT_CRASH
, 0),
5957 DEFINE_PROP_BIT64("hv-reset", X86CPU
, hyperv_features
,
5958 HYPERV_FEAT_RESET
, 0),
5959 DEFINE_PROP_BIT64("hv-vpindex", X86CPU
, hyperv_features
,
5960 HYPERV_FEAT_VPINDEX
, 0),
5961 DEFINE_PROP_BIT64("hv-runtime", X86CPU
, hyperv_features
,
5962 HYPERV_FEAT_RUNTIME
, 0),
5963 DEFINE_PROP_BIT64("hv-synic", X86CPU
, hyperv_features
,
5964 HYPERV_FEAT_SYNIC
, 0),
5965 DEFINE_PROP_BIT64("hv-stimer", X86CPU
, hyperv_features
,
5966 HYPERV_FEAT_STIMER
, 0),
5967 DEFINE_PROP_BIT64("hv-frequencies", X86CPU
, hyperv_features
,
5968 HYPERV_FEAT_FREQUENCIES
, 0),
5969 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU
, hyperv_features
,
5970 HYPERV_FEAT_REENLIGHTENMENT
, 0),
5971 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU
, hyperv_features
,
5972 HYPERV_FEAT_TLBFLUSH
, 0),
5973 DEFINE_PROP_BIT64("hv-evmcs", X86CPU
, hyperv_features
,
5974 HYPERV_FEAT_EVMCS
, 0),
5975 DEFINE_PROP_BIT64("hv-ipi", X86CPU
, hyperv_features
,
5976 HYPERV_FEAT_IPI
, 0),
5977 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU
, hyperv_features
,
5978 HYPERV_FEAT_STIMER_DIRECT
, 0),
5979 DEFINE_PROP_BOOL("hv-passthrough", X86CPU
, hyperv_passthrough
, false),
5981 DEFINE_PROP_BOOL("check", X86CPU
, check_cpuid
, true),
5982 DEFINE_PROP_BOOL("enforce", X86CPU
, enforce_cpuid
, false),
5983 DEFINE_PROP_BOOL("kvm", X86CPU
, expose_kvm
, true),
5984 DEFINE_PROP_UINT32("phys-bits", X86CPU
, phys_bits
, 0),
5985 DEFINE_PROP_BOOL("host-phys-bits", X86CPU
, host_phys_bits
, false),
5986 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU
, host_phys_bits_limit
, 0),
5987 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU
, fill_mtrr_mask
, true),
5988 DEFINE_PROP_UINT32("level", X86CPU
, env
.cpuid_level
, UINT32_MAX
),
5989 DEFINE_PROP_UINT32("xlevel", X86CPU
, env
.cpuid_xlevel
, UINT32_MAX
),
5990 DEFINE_PROP_UINT32("xlevel2", X86CPU
, env
.cpuid_xlevel2
, UINT32_MAX
),
5991 DEFINE_PROP_UINT32("min-level", X86CPU
, env
.cpuid_min_level
, 0),
5992 DEFINE_PROP_UINT32("min-xlevel", X86CPU
, env
.cpuid_min_xlevel
, 0),
5993 DEFINE_PROP_UINT32("min-xlevel2", X86CPU
, env
.cpuid_min_xlevel2
, 0),
5994 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU
, full_cpuid_auto_level
, true),
5995 DEFINE_PROP_STRING("hv-vendor-id", X86CPU
, hyperv_vendor_id
),
5996 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU
, enable_cpuid_0xb
, true),
5997 DEFINE_PROP_BOOL("lmce", X86CPU
, enable_lmce
, false),
5998 DEFINE_PROP_BOOL("l3-cache", X86CPU
, enable_l3_cache
, true),
5999 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU
, kvm_no_smi_migration
,
6001 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU
, vmware_cpuid_freq
, true),
6002 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU
, expose_tcg
, true),
6003 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU
, migrate_smi_count
,
6006 * lecacy_cache defaults to true unless the CPU model provides its
6007 * own cache information (see x86_cpu_load_def()).
6009 DEFINE_PROP_BOOL("legacy-cache", X86CPU
, legacy_cache
, true),
6012 * From "Requirements for Implementing the Microsoft
6013 * Hypervisor Interface":
6014 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
6016 * "Starting with Windows Server 2012 and Windows 8, if
6017 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
6018 * the hypervisor imposes no specific limit to the number of VPs.
6019 * In this case, Windows Server 2012 guest VMs may use more than
6020 * 64 VPs, up to the maximum supported number of processors applicable
6021 * to the specific Windows version being used."
6023 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU
, hv_max_vps
, -1),
6024 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU
, hyperv_synic_kvm_only
,
6026 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU
, intel_pt_auto_level
,
6028 DEFINE_PROP_END_OF_LIST()
6031 static void x86_cpu_common_class_init(ObjectClass
*oc
, void *data
)
6033 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
6034 CPUClass
*cc
= CPU_CLASS(oc
);
6035 DeviceClass
*dc
= DEVICE_CLASS(oc
);
6037 device_class_set_parent_realize(dc
, x86_cpu_realizefn
,
6038 &xcc
->parent_realize
);
6039 device_class_set_parent_unrealize(dc
, x86_cpu_unrealizefn
,
6040 &xcc
->parent_unrealize
);
6041 dc
->props
= x86_cpu_properties
;
6043 xcc
->parent_reset
= cc
->reset
;
6044 cc
->reset
= x86_cpu_reset
;
6045 cc
->reset_dump_flags
= CPU_DUMP_FPU
| CPU_DUMP_CCOP
;
6047 cc
->class_by_name
= x86_cpu_class_by_name
;
6048 cc
->parse_features
= x86_cpu_parse_featurestr
;
6049 cc
->has_work
= x86_cpu_has_work
;
6051 cc
->do_interrupt
= x86_cpu_do_interrupt
;
6052 cc
->cpu_exec_interrupt
= x86_cpu_exec_interrupt
;
6054 cc
->dump_state
= x86_cpu_dump_state
;
6055 cc
->get_crash_info
= x86_cpu_get_crash_info
;
6056 cc
->set_pc
= x86_cpu_set_pc
;
6057 cc
->synchronize_from_tb
= x86_cpu_synchronize_from_tb
;
6058 cc
->gdb_read_register
= x86_cpu_gdb_read_register
;
6059 cc
->gdb_write_register
= x86_cpu_gdb_write_register
;
6060 cc
->get_arch_id
= x86_cpu_get_arch_id
;
6061 cc
->get_paging_enabled
= x86_cpu_get_paging_enabled
;
6062 #ifndef CONFIG_USER_ONLY
6063 cc
->asidx_from_attrs
= x86_asidx_from_attrs
;
6064 cc
->get_memory_mapping
= x86_cpu_get_memory_mapping
;
6065 cc
->get_phys_page_debug
= x86_cpu_get_phys_page_debug
;
6066 cc
->write_elf64_note
= x86_cpu_write_elf64_note
;
6067 cc
->write_elf64_qemunote
= x86_cpu_write_elf64_qemunote
;
6068 cc
->write_elf32_note
= x86_cpu_write_elf32_note
;
6069 cc
->write_elf32_qemunote
= x86_cpu_write_elf32_qemunote
;
6070 cc
->vmsd
= &vmstate_x86_cpu
;
6072 cc
->gdb_arch_name
= x86_gdb_arch_name
;
6073 #ifdef TARGET_X86_64
6074 cc
->gdb_core_xml_file
= "i386-64bit.xml";
6075 cc
->gdb_num_core_regs
= 66;
6077 cc
->gdb_core_xml_file
= "i386-32bit.xml";
6078 cc
->gdb_num_core_regs
= 50;
6080 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
6081 cc
->debug_excp_handler
= breakpoint_handler
;
6083 cc
->cpu_exec_enter
= x86_cpu_exec_enter
;
6084 cc
->cpu_exec_exit
= x86_cpu_exec_exit
;
6086 cc
->tcg_initialize
= tcg_x86_init
;
6087 cc
->tlb_fill
= x86_cpu_tlb_fill
;
6089 cc
->disas_set_info
= x86_disas_set_info
;
6091 dc
->user_creatable
= true;
6094 static const TypeInfo x86_cpu_type_info
= {
6095 .name
= TYPE_X86_CPU
,
6097 .instance_size
= sizeof(X86CPU
),
6098 .instance_init
= x86_cpu_initfn
,
6100 .class_size
= sizeof(X86CPUClass
),
6101 .class_init
= x86_cpu_common_class_init
,
6105 /* "base" CPU model, used by query-cpu-model-expansion */
6106 static void x86_cpu_base_class_init(ObjectClass
*oc
, void *data
)
6108 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
6110 xcc
->static_model
= true;
6111 xcc
->migration_safe
= true;
6112 xcc
->model_description
= "base CPU model type with no features enabled";
6116 static const TypeInfo x86_base_cpu_type_info
= {
6117 .name
= X86_CPU_TYPE_NAME("base"),
6118 .parent
= TYPE_X86_CPU
,
6119 .class_init
= x86_cpu_base_class_init
,
6122 static void x86_cpu_register_types(void)
6126 type_register_static(&x86_cpu_type_info
);
6127 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); i
++) {
6128 x86_register_cpudef_type(&builtin_x86_defs
[i
]);
6130 type_register_static(&max_x86_cpu_type_info
);
6131 type_register_static(&x86_base_cpu_type_info
);
6132 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
6133 type_register_static(&host_x86_cpu_type_info
);
6137 type_init(x86_cpu_register_types
)