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cpu: add CPU_RESOLVING_TYPE macro
[mirror_qemu.git] / target / ppc / cpu.h
1 /*
2 * PowerPC emulation cpu definitions for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef PPC_CPU_H
21 #define PPC_CPU_H
22
23 #include "qemu-common.h"
24 #include "qemu/int128.h"
25
26 //#define PPC_EMULATE_32BITS_HYPV
27
28 #if defined (TARGET_PPC64)
29 /* PowerPC 64 definitions */
30 #define TARGET_LONG_BITS 64
31 #define TARGET_PAGE_BITS 12
32
33 #define TCG_GUEST_DEFAULT_MO 0
34
35 /* Note that the official physical address space bits is 62-M where M
36 is implementation dependent. I've not looked up M for the set of
37 cpus we emulate at the system level. */
38 #define TARGET_PHYS_ADDR_SPACE_BITS 62
39
40 /* Note that the PPC environment architecture talks about 80 bit virtual
41 addresses, with segmentation. Obviously that's not all visible to a
42 single process, which is all we're concerned with here. */
43 #ifdef TARGET_ABI32
44 # define TARGET_VIRT_ADDR_SPACE_BITS 32
45 #else
46 # define TARGET_VIRT_ADDR_SPACE_BITS 64
47 #endif
48
49 #define TARGET_PAGE_BITS_64K 16
50 #define TARGET_PAGE_BITS_16M 24
51
52 #else /* defined (TARGET_PPC64) */
53 /* PowerPC 32 definitions */
54 #define TARGET_LONG_BITS 32
55
56 #if defined(TARGET_PPCEMB)
57 /* Specific definitions for PowerPC embedded */
58 /* BookE have 36 bits physical address space */
59 #if defined(CONFIG_USER_ONLY)
60 /* It looks like a lot of Linux programs assume page size
61 * is 4kB long. This is evil, but we have to deal with it...
62 */
63 #define TARGET_PAGE_BITS 12
64 #else /* defined(CONFIG_USER_ONLY) */
65 /* Pages can be 1 kB small */
66 #define TARGET_PAGE_BITS 10
67 #endif /* defined(CONFIG_USER_ONLY) */
68 #else /* defined(TARGET_PPCEMB) */
69 /* "standard" PowerPC 32 definitions */
70 #define TARGET_PAGE_BITS 12
71 #endif /* defined(TARGET_PPCEMB) */
72
73 #define TARGET_PHYS_ADDR_SPACE_BITS 36
74 #define TARGET_VIRT_ADDR_SPACE_BITS 32
75
76 #endif /* defined (TARGET_PPC64) */
77
78 #define CPUArchState struct CPUPPCState
79
80 #include "exec/cpu-defs.h"
81 #include "cpu-qom.h"
82
83 #if defined (TARGET_PPC64)
84 #define PPC_ELF_MACHINE EM_PPC64
85 #else
86 #define PPC_ELF_MACHINE EM_PPC
87 #endif
88
89 #define PPC_BIT(bit) (0x8000000000000000UL >> (bit))
90 #define PPC_BIT32(bit) (0x80000000UL >> (bit))
91 #define PPC_BIT8(bit) (0x80UL >> (bit))
92 #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
93 #define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
94 PPC_BIT32(bs))
95 #define PPC_BITMASK8(bs, be) ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(bs))
96
97 #if HOST_LONG_BITS == 32
98 # define MASK_TO_LSH(m) (__builtin_ffsll(m) - 1)
99 #elif HOST_LONG_BITS == 64
100 # define MASK_TO_LSH(m) (__builtin_ffsl(m) - 1)
101 #else
102 # error Unknown sizeof long
103 #endif
104
105 #define GETFIELD(m, v) (((v) & (m)) >> MASK_TO_LSH(m))
106 #define SETFIELD(m, v, val) \
107 (((v) & ~(m)) | ((((typeof(v))(val)) << MASK_TO_LSH(m)) & (m)))
108
109 /*****************************************************************************/
110 /* Exception vectors definitions */
111 enum {
112 POWERPC_EXCP_NONE = -1,
113 /* The 64 first entries are used by the PowerPC embedded specification */
114 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
115 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
116 POWERPC_EXCP_DSI = 2, /* Data storage exception */
117 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
118 POWERPC_EXCP_EXTERNAL = 4, /* External input */
119 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
120 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
121 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
122 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
123 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
124 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
125 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
126 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
127 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
128 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
129 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
130 /* Vectors 16 to 31 are reserved */
131 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
132 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
133 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
134 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
135 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
136 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
137 POWERPC_EXCP_GDOORI = 38, /* Embedded guest doorbell interrupt */
138 POWERPC_EXCP_GDOORCI = 39, /* Embedded guest doorbell critical interrupt*/
139 POWERPC_EXCP_HYPPRIV = 41, /* Embedded hypervisor priv instruction */
140 /* Vectors 42 to 63 are reserved */
141 /* Exceptions defined in the PowerPC server specification */
142 POWERPC_EXCP_RESET = 64, /* System reset exception */
143 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
144 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
145 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
146 POWERPC_EXCP_TRACE = 68, /* Trace exception */
147 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
148 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
149 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
150 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
151 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
152 /* 40x specific exceptions */
153 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
154 /* 601 specific exceptions */
155 POWERPC_EXCP_IO = 75, /* IO error exception */
156 POWERPC_EXCP_RUNM = 76, /* Run mode exception */
157 /* 602 specific exceptions */
158 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
159 /* 602/603 specific exceptions */
160 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
161 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
162 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
163 /* Exceptions available on most PowerPC */
164 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
165 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
166 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
167 POWERPC_EXCP_SMI = 84, /* System management interrupt */
168 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
169 /* 7xx/74xx specific exceptions */
170 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
171 /* 74xx specific exceptions */
172 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
173 /* 970FX specific exceptions */
174 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
175 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
176 /* Freescale embedded cores specific exceptions */
177 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
178 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
179 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
180 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
181 /* VSX Unavailable (Power ISA 2.06 and later) */
182 POWERPC_EXCP_VSXU = 94, /* VSX Unavailable */
183 POWERPC_EXCP_FU = 95, /* Facility Unavailable */
184 /* Additional ISA 2.06 and later server exceptions */
185 POWERPC_EXCP_HV_EMU = 96, /* HV emulation assistance */
186 POWERPC_EXCP_HV_MAINT = 97, /* HMI */
187 POWERPC_EXCP_HV_FU = 98, /* Hypervisor Facility unavailable */
188 /* Server doorbell variants */
189 POWERPC_EXCP_SDOOR = 99,
190 POWERPC_EXCP_SDOOR_HV = 100,
191 /* EOL */
192 POWERPC_EXCP_NB = 101,
193 /* QEMU exceptions: used internally during code translation */
194 POWERPC_EXCP_STOP = 0x200, /* stop translation */
195 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
196 /* QEMU exceptions: special cases we want to stop translation */
197 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
198 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
199 POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */
200 };
201
202 /* Exceptions error codes */
203 enum {
204 /* Exception subtypes for POWERPC_EXCP_ALIGN */
205 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
206 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
207 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
208 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
209 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
210 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
211 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
212 /* FP exceptions */
213 POWERPC_EXCP_FP = 0x10,
214 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
215 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
216 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
217 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
218 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
219 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
220 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
221 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
222 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
223 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
224 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
225 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
226 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
227 /* Invalid instruction */
228 POWERPC_EXCP_INVAL = 0x20,
229 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
230 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
231 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
232 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
233 /* Privileged instruction */
234 POWERPC_EXCP_PRIV = 0x30,
235 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
236 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
237 /* Trap */
238 POWERPC_EXCP_TRAP = 0x40,
239 };
240
241 #define PPC_INPUT(env) (env->bus_model)
242
243 /*****************************************************************************/
244 typedef struct opc_handler_t opc_handler_t;
245
246 /*****************************************************************************/
247 /* Types used to describe some PowerPC registers etc. */
248 typedef struct DisasContext DisasContext;
249 typedef struct ppc_spr_t ppc_spr_t;
250 typedef union ppc_avr_t ppc_avr_t;
251 typedef union ppc_tlb_t ppc_tlb_t;
252 typedef struct ppc_hash_pte64 ppc_hash_pte64_t;
253
254 /* SPR access micro-ops generations callbacks */
255 struct ppc_spr_t {
256 void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
257 void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
258 #if !defined(CONFIG_USER_ONLY)
259 void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
260 void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
261 void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
262 void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
263 #endif
264 const char *name;
265 target_ulong default_value;
266 #ifdef CONFIG_KVM
267 /* We (ab)use the fact that all the SPRs will have ids for the
268 * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
269 * don't sync this */
270 uint64_t one_reg_id;
271 #endif
272 };
273
274 /* Altivec registers (128 bits) */
275 union ppc_avr_t {
276 float32 f[4];
277 uint8_t u8[16];
278 uint16_t u16[8];
279 uint32_t u32[4];
280 int8_t s8[16];
281 int16_t s16[8];
282 int32_t s32[4];
283 uint64_t u64[2];
284 int64_t s64[2];
285 #ifdef CONFIG_INT128
286 __uint128_t u128;
287 #endif
288 Int128 s128;
289 };
290
291 #if !defined(CONFIG_USER_ONLY)
292 /* Software TLB cache */
293 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
294 struct ppc6xx_tlb_t {
295 target_ulong pte0;
296 target_ulong pte1;
297 target_ulong EPN;
298 };
299
300 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
301 struct ppcemb_tlb_t {
302 uint64_t RPN;
303 target_ulong EPN;
304 target_ulong PID;
305 target_ulong size;
306 uint32_t prot;
307 uint32_t attr; /* Storage attributes */
308 };
309
310 typedef struct ppcmas_tlb_t {
311 uint32_t mas8;
312 uint32_t mas1;
313 uint64_t mas2;
314 uint64_t mas7_3;
315 } ppcmas_tlb_t;
316
317 union ppc_tlb_t {
318 ppc6xx_tlb_t *tlb6;
319 ppcemb_tlb_t *tlbe;
320 ppcmas_tlb_t *tlbm;
321 };
322
323 /* possible TLB variants */
324 #define TLB_NONE 0
325 #define TLB_6XX 1
326 #define TLB_EMB 2
327 #define TLB_MAS 3
328 #endif
329
330 typedef struct ppc_slb_t ppc_slb_t;
331 struct ppc_slb_t {
332 uint64_t esid;
333 uint64_t vsid;
334 const struct ppc_one_seg_page_size *sps;
335 };
336
337 #define MAX_SLB_ENTRIES 64
338 #define SEGMENT_SHIFT_256M 28
339 #define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
340
341 #define SEGMENT_SHIFT_1T 40
342 #define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
343
344
345 /*****************************************************************************/
346 /* Machine state register bits definition */
347 #define MSR_SF 63 /* Sixty-four-bit mode hflags */
348 #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
349 #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
350 #define MSR_SHV 60 /* hypervisor state hflags */
351 #define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */
352 #define MSR_TS1 33
353 #define MSR_TM 32 /* Transactional Memory Available (Book3s) */
354 #define MSR_CM 31 /* Computation mode for BookE hflags */
355 #define MSR_ICM 30 /* Interrupt computation mode for BookE */
356 #define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
357 #define MSR_GS 28 /* guest state for BookE */
358 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
359 #define MSR_VR 25 /* altivec available x hflags */
360 #define MSR_SPE 25 /* SPE enable for BookE x hflags */
361 #define MSR_AP 23 /* Access privilege state on 602 hflags */
362 #define MSR_VSX 23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
363 #define MSR_SA 22 /* Supervisor access mode on 602 hflags */
364 #define MSR_KEY 19 /* key bit on 603e */
365 #define MSR_POW 18 /* Power management */
366 #define MSR_TGPR 17 /* TGPR usage on 602/603 x */
367 #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
368 #define MSR_ILE 16 /* Interrupt little-endian mode */
369 #define MSR_EE 15 /* External interrupt enable */
370 #define MSR_PR 14 /* Problem state hflags */
371 #define MSR_FP 13 /* Floating point available hflags */
372 #define MSR_ME 12 /* Machine check interrupt enable */
373 #define MSR_FE0 11 /* Floating point exception mode 0 hflags */
374 #define MSR_SE 10 /* Single-step trace enable x hflags */
375 #define MSR_DWE 10 /* Debug wait enable on 405 x */
376 #define MSR_UBLE 10 /* User BTB lock enable on e500 x */
377 #define MSR_BE 9 /* Branch trace enable x hflags */
378 #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
379 #define MSR_FE1 8 /* Floating point exception mode 1 hflags */
380 #define MSR_AL 7 /* AL bit on POWER */
381 #define MSR_EP 6 /* Exception prefix on 601 */
382 #define MSR_IR 5 /* Instruction relocate */
383 #define MSR_DR 4 /* Data relocate */
384 #define MSR_IS 5 /* Instruction address space (BookE) */
385 #define MSR_DS 4 /* Data address space (BookE) */
386 #define MSR_PE 3 /* Protection enable on 403 */
387 #define MSR_PX 2 /* Protection exclusive on 403 x */
388 #define MSR_PMM 2 /* Performance monitor mark on POWER x */
389 #define MSR_RI 1 /* Recoverable interrupt 1 */
390 #define MSR_LE 0 /* Little-endian mode 1 hflags */
391
392 /* LPCR bits */
393 #define LPCR_VPM0 PPC_BIT(0)
394 #define LPCR_VPM1 PPC_BIT(1)
395 #define LPCR_ISL PPC_BIT(2)
396 #define LPCR_KBV PPC_BIT(3)
397 #define LPCR_DPFD_SHIFT (63 - 11)
398 #define LPCR_DPFD (0x7ull << LPCR_DPFD_SHIFT)
399 #define LPCR_VRMASD_SHIFT (63 - 16)
400 #define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT)
401 /* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */
402 #define LPCR_PECE_U_SHIFT (63 - 19)
403 #define LPCR_PECE_U_MASK (0x7ull << LPCR_PECE_U_SHIFT)
404 #define LPCR_HVEE PPC_BIT(17) /* Hypervisor Virt Exit Enable */
405 #define LPCR_RMLS_SHIFT (63 - 37)
406 #define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT)
407 #define LPCR_ILE PPC_BIT(38)
408 #define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */
409 #define LPCR_AIL (3ull << LPCR_AIL_SHIFT)
410 #define LPCR_UPRT PPC_BIT(41) /* Use Process Table */
411 #define LPCR_EVIRT PPC_BIT(42) /* Enhanced Virtualisation */
412 #define LPCR_ONL PPC_BIT(45)
413 #define LPCR_LD PPC_BIT(46) /* Large Decrementer */
414 #define LPCR_P7_PECE0 PPC_BIT(49)
415 #define LPCR_P7_PECE1 PPC_BIT(50)
416 #define LPCR_P7_PECE2 PPC_BIT(51)
417 #define LPCR_P8_PECE0 PPC_BIT(47)
418 #define LPCR_P8_PECE1 PPC_BIT(48)
419 #define LPCR_P8_PECE2 PPC_BIT(49)
420 #define LPCR_P8_PECE3 PPC_BIT(50)
421 #define LPCR_P8_PECE4 PPC_BIT(51)
422 /* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */
423 #define LPCR_PECE_L_SHIFT (63 - 51)
424 #define LPCR_PECE_L_MASK (0x1full << LPCR_PECE_L_SHIFT)
425 #define LPCR_PDEE PPC_BIT(47) /* Privileged Doorbell Exit EN */
426 #define LPCR_HDEE PPC_BIT(48) /* Hyperv Doorbell Exit Enable */
427 #define LPCR_EEE PPC_BIT(49) /* External Exit Enable */
428 #define LPCR_DEE PPC_BIT(50) /* Decrementer Exit Enable */
429 #define LPCR_OEE PPC_BIT(51) /* Other Exit Enable */
430 #define LPCR_MER PPC_BIT(52)
431 #define LPCR_GTSE PPC_BIT(53) /* Guest Translation Shootdown */
432 #define LPCR_TC PPC_BIT(54)
433 #define LPCR_HEIC PPC_BIT(59) /* HV Extern Interrupt Control */
434 #define LPCR_LPES0 PPC_BIT(60)
435 #define LPCR_LPES1 PPC_BIT(61)
436 #define LPCR_RMI PPC_BIT(62)
437 #define LPCR_HVICE PPC_BIT(62) /* HV Virtualisation Int Enable */
438 #define LPCR_HDICE PPC_BIT(63)
439
440 #define msr_sf ((env->msr >> MSR_SF) & 1)
441 #define msr_isf ((env->msr >> MSR_ISF) & 1)
442 #define msr_shv ((env->msr >> MSR_SHV) & 1)
443 #define msr_cm ((env->msr >> MSR_CM) & 1)
444 #define msr_icm ((env->msr >> MSR_ICM) & 1)
445 #define msr_thv ((env->msr >> MSR_THV) & 1)
446 #define msr_gs ((env->msr >> MSR_GS) & 1)
447 #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
448 #define msr_vr ((env->msr >> MSR_VR) & 1)
449 #define msr_spe ((env->msr >> MSR_SPE) & 1)
450 #define msr_ap ((env->msr >> MSR_AP) & 1)
451 #define msr_vsx ((env->msr >> MSR_VSX) & 1)
452 #define msr_sa ((env->msr >> MSR_SA) & 1)
453 #define msr_key ((env->msr >> MSR_KEY) & 1)
454 #define msr_pow ((env->msr >> MSR_POW) & 1)
455 #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
456 #define msr_ce ((env->msr >> MSR_CE) & 1)
457 #define msr_ile ((env->msr >> MSR_ILE) & 1)
458 #define msr_ee ((env->msr >> MSR_EE) & 1)
459 #define msr_pr ((env->msr >> MSR_PR) & 1)
460 #define msr_fp ((env->msr >> MSR_FP) & 1)
461 #define msr_me ((env->msr >> MSR_ME) & 1)
462 #define msr_fe0 ((env->msr >> MSR_FE0) & 1)
463 #define msr_se ((env->msr >> MSR_SE) & 1)
464 #define msr_dwe ((env->msr >> MSR_DWE) & 1)
465 #define msr_uble ((env->msr >> MSR_UBLE) & 1)
466 #define msr_be ((env->msr >> MSR_BE) & 1)
467 #define msr_de ((env->msr >> MSR_DE) & 1)
468 #define msr_fe1 ((env->msr >> MSR_FE1) & 1)
469 #define msr_al ((env->msr >> MSR_AL) & 1)
470 #define msr_ep ((env->msr >> MSR_EP) & 1)
471 #define msr_ir ((env->msr >> MSR_IR) & 1)
472 #define msr_dr ((env->msr >> MSR_DR) & 1)
473 #define msr_is ((env->msr >> MSR_IS) & 1)
474 #define msr_ds ((env->msr >> MSR_DS) & 1)
475 #define msr_pe ((env->msr >> MSR_PE) & 1)
476 #define msr_px ((env->msr >> MSR_PX) & 1)
477 #define msr_pmm ((env->msr >> MSR_PMM) & 1)
478 #define msr_ri ((env->msr >> MSR_RI) & 1)
479 #define msr_le ((env->msr >> MSR_LE) & 1)
480 #define msr_ts ((env->msr >> MSR_TS1) & 3)
481 #define msr_tm ((env->msr >> MSR_TM) & 1)
482
483 /* Hypervisor bit is more specific */
484 #if defined(TARGET_PPC64)
485 #define MSR_HVB (1ULL << MSR_SHV)
486 #define msr_hv msr_shv
487 #else
488 #if defined(PPC_EMULATE_32BITS_HYPV)
489 #define MSR_HVB (1ULL << MSR_THV)
490 #define msr_hv msr_thv
491 #else
492 #define MSR_HVB (0ULL)
493 #define msr_hv (0)
494 #endif
495 #endif
496
497 /* DSISR */
498 #define DSISR_NOPTE 0x40000000
499 /* Not permitted by access authority of encoded access authority */
500 #define DSISR_PROTFAULT 0x08000000
501 #define DSISR_ISSTORE 0x02000000
502 /* Not permitted by virtual page class key protection */
503 #define DSISR_AMR 0x00200000
504 /* Unsupported Radix Tree Configuration */
505 #define DSISR_R_BADCONFIG 0x00080000
506
507 /* SRR1 error code fields */
508
509 #define SRR1_NOPTE DSISR_NOPTE
510 /* Not permitted due to no-execute or guard bit set */
511 #define SRR1_NOEXEC_GUARD 0x10000000
512 #define SRR1_PROTFAULT DSISR_PROTFAULT
513 #define SRR1_IAMR DSISR_AMR
514
515 /* Facility Status and Control (FSCR) bits */
516 #define FSCR_EBB (63 - 56) /* Event-Based Branch Facility */
517 #define FSCR_TAR (63 - 55) /* Target Address Register */
518 /* Interrupt cause mask and position in FSCR. HFSCR has the same format */
519 #define FSCR_IC_MASK (0xFFULL)
520 #define FSCR_IC_POS (63 - 7)
521 #define FSCR_IC_DSCR_SPR3 2
522 #define FSCR_IC_PMU 3
523 #define FSCR_IC_BHRB 4
524 #define FSCR_IC_TM 5
525 #define FSCR_IC_EBB 7
526 #define FSCR_IC_TAR 8
527
528 /* Exception state register bits definition */
529 #define ESR_PIL PPC_BIT(36) /* Illegal Instruction */
530 #define ESR_PPR PPC_BIT(37) /* Privileged Instruction */
531 #define ESR_PTR PPC_BIT(38) /* Trap */
532 #define ESR_FP PPC_BIT(39) /* Floating-Point Operation */
533 #define ESR_ST PPC_BIT(40) /* Store Operation */
534 #define ESR_AP PPC_BIT(44) /* Auxiliary Processor Operation */
535 #define ESR_PUO PPC_BIT(45) /* Unimplemented Operation */
536 #define ESR_BO PPC_BIT(46) /* Byte Ordering */
537 #define ESR_PIE PPC_BIT(47) /* Imprecise exception */
538 #define ESR_DATA PPC_BIT(53) /* Data Access (Embedded page table) */
539 #define ESR_TLBI PPC_BIT(54) /* TLB Ineligible (Embedded page table) */
540 #define ESR_PT PPC_BIT(55) /* Page Table (Embedded page table) */
541 #define ESR_SPV PPC_BIT(56) /* SPE/VMX operation */
542 #define ESR_EPID PPC_BIT(57) /* External Process ID operation */
543 #define ESR_VLEMI PPC_BIT(58) /* VLE operation */
544 #define ESR_MIF PPC_BIT(62) /* Misaligned instruction (VLE) */
545
546 /* Transaction EXception And Summary Register bits */
547 #define TEXASR_FAILURE_PERSISTENT (63 - 7)
548 #define TEXASR_DISALLOWED (63 - 8)
549 #define TEXASR_NESTING_OVERFLOW (63 - 9)
550 #define TEXASR_FOOTPRINT_OVERFLOW (63 - 10)
551 #define TEXASR_SELF_INDUCED_CONFLICT (63 - 11)
552 #define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12)
553 #define TEXASR_TRANSACTION_CONFLICT (63 - 13)
554 #define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
555 #define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15)
556 #define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16)
557 #define TEXASR_ABORT (63 - 31)
558 #define TEXASR_SUSPENDED (63 - 32)
559 #define TEXASR_PRIVILEGE_HV (63 - 34)
560 #define TEXASR_PRIVILEGE_PR (63 - 35)
561 #define TEXASR_FAILURE_SUMMARY (63 - 36)
562 #define TEXASR_TFIAR_EXACT (63 - 37)
563 #define TEXASR_ROT (63 - 38)
564 #define TEXASR_TRANSACTION_LEVEL (63 - 52) /* 12 bits */
565
566 enum {
567 POWERPC_FLAG_NONE = 0x00000000,
568 /* Flag for MSR bit 25 signification (VRE/SPE) */
569 POWERPC_FLAG_SPE = 0x00000001,
570 POWERPC_FLAG_VRE = 0x00000002,
571 /* Flag for MSR bit 17 signification (TGPR/CE) */
572 POWERPC_FLAG_TGPR = 0x00000004,
573 POWERPC_FLAG_CE = 0x00000008,
574 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
575 POWERPC_FLAG_SE = 0x00000010,
576 POWERPC_FLAG_DWE = 0x00000020,
577 POWERPC_FLAG_UBLE = 0x00000040,
578 /* Flag for MSR bit 9 signification (BE/DE) */
579 POWERPC_FLAG_BE = 0x00000080,
580 POWERPC_FLAG_DE = 0x00000100,
581 /* Flag for MSR bit 2 signification (PX/PMM) */
582 POWERPC_FLAG_PX = 0x00000200,
583 POWERPC_FLAG_PMM = 0x00000400,
584 /* Flag for special features */
585 /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
586 POWERPC_FLAG_RTC_CLK = 0x00010000,
587 POWERPC_FLAG_BUS_CLK = 0x00020000,
588 /* Has CFAR */
589 POWERPC_FLAG_CFAR = 0x00040000,
590 /* Has VSX */
591 POWERPC_FLAG_VSX = 0x00080000,
592 /* Has Transaction Memory (ISA 2.07) */
593 POWERPC_FLAG_TM = 0x00100000,
594 };
595
596 /*****************************************************************************/
597 /* Floating point status and control register */
598 #define FPSCR_FX 31 /* Floating-point exception summary */
599 #define FPSCR_FEX 30 /* Floating-point enabled exception summary */
600 #define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
601 #define FPSCR_OX 28 /* Floating-point overflow exception */
602 #define FPSCR_UX 27 /* Floating-point underflow exception */
603 #define FPSCR_ZX 26 /* Floating-point zero divide exception */
604 #define FPSCR_XX 25 /* Floating-point inexact exception */
605 #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
606 #define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
607 #define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
608 #define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
609 #define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
610 #define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
611 #define FPSCR_FR 18 /* Floating-point fraction rounded */
612 #define FPSCR_FI 17 /* Floating-point fraction inexact */
613 #define FPSCR_C 16 /* Floating-point result class descriptor */
614 #define FPSCR_FL 15 /* Floating-point less than or negative */
615 #define FPSCR_FG 14 /* Floating-point greater than or negative */
616 #define FPSCR_FE 13 /* Floating-point equal or zero */
617 #define FPSCR_FU 12 /* Floating-point unordered or NaN */
618 #define FPSCR_FPCC 12 /* Floating-point condition code */
619 #define FPSCR_FPRF 12 /* Floating-point result flags */
620 #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
621 #define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
622 #define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
623 #define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
624 #define FPSCR_OE 6 /* Floating-point overflow exception enable */
625 #define FPSCR_UE 5 /* Floating-point undeflow exception enable */
626 #define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
627 #define FPSCR_XE 3 /* Floating-point inexact exception enable */
628 #define FPSCR_NI 2 /* Floating-point non-IEEE mode */
629 #define FPSCR_RN1 1
630 #define FPSCR_RN 0 /* Floating-point rounding control */
631 #define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
632 #define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
633 #define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
634 #define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
635 #define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
636 #define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
637 #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
638 #define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
639 #define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
640 #define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
641 #define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
642 #define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
643 #define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
644 #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
645 #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
646 #define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
647 #define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
648 #define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
649 #define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
650 #define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
651 #define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
652 #define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
653 #define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
654 /* Invalid operation exception summary */
655 #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
656 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
657 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
658 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
659 (1 << FPSCR_VXCVI)))
660 /* exception summary */
661 #define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
662 /* enabled exception summary */
663 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
664 0x1F)
665
666 #define FP_FX (1ull << FPSCR_FX)
667 #define FP_FEX (1ull << FPSCR_FEX)
668 #define FP_VX (1ull << FPSCR_VX)
669 #define FP_OX (1ull << FPSCR_OX)
670 #define FP_UX (1ull << FPSCR_UX)
671 #define FP_ZX (1ull << FPSCR_ZX)
672 #define FP_XX (1ull << FPSCR_XX)
673 #define FP_VXSNAN (1ull << FPSCR_VXSNAN)
674 #define FP_VXISI (1ull << FPSCR_VXISI)
675 #define FP_VXIDI (1ull << FPSCR_VXIDI)
676 #define FP_VXZDZ (1ull << FPSCR_VXZDZ)
677 #define FP_VXIMZ (1ull << FPSCR_VXIMZ)
678 #define FP_VXVC (1ull << FPSCR_VXVC)
679 #define FP_FR (1ull << FSPCR_FR)
680 #define FP_FI (1ull << FPSCR_FI)
681 #define FP_C (1ull << FPSCR_C)
682 #define FP_FL (1ull << FPSCR_FL)
683 #define FP_FG (1ull << FPSCR_FG)
684 #define FP_FE (1ull << FPSCR_FE)
685 #define FP_FU (1ull << FPSCR_FU)
686 #define FP_FPCC (FP_FL | FP_FG | FP_FE | FP_FU)
687 #define FP_FPRF (FP_C | FP_FL | FP_FG | FP_FE | FP_FU)
688 #define FP_VXSOFT (1ull << FPSCR_VXSOFT)
689 #define FP_VXSQRT (1ull << FPSCR_VXSQRT)
690 #define FP_VXCVI (1ull << FPSCR_VXCVI)
691 #define FP_VE (1ull << FPSCR_VE)
692 #define FP_OE (1ull << FPSCR_OE)
693 #define FP_UE (1ull << FPSCR_UE)
694 #define FP_ZE (1ull << FPSCR_ZE)
695 #define FP_XE (1ull << FPSCR_XE)
696 #define FP_NI (1ull << FPSCR_NI)
697 #define FP_RN1 (1ull << FPSCR_RN1)
698 #define FP_RN (1ull << FPSCR_RN)
699
700 /* the exception bits which can be cleared by mcrfs - includes FX */
701 #define FP_EX_CLEAR_BITS (FP_FX | FP_OX | FP_UX | FP_ZX | \
702 FP_XX | FP_VXSNAN | FP_VXISI | FP_VXIDI | \
703 FP_VXZDZ | FP_VXIMZ | FP_VXVC | FP_VXSOFT | \
704 FP_VXSQRT | FP_VXCVI)
705
706 /*****************************************************************************/
707 /* Vector status and control register */
708 #define VSCR_NJ 16 /* Vector non-java */
709 #define VSCR_SAT 0 /* Vector saturation */
710 #define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
711 #define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
712
713 /*****************************************************************************/
714 /* BookE e500 MMU registers */
715
716 #define MAS0_NV_SHIFT 0
717 #define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
718
719 #define MAS0_WQ_SHIFT 12
720 #define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
721 /* Write TLB entry regardless of reservation */
722 #define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
723 /* Write TLB entry only already in use */
724 #define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
725 /* Clear TLB entry */
726 #define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
727
728 #define MAS0_HES_SHIFT 14
729 #define MAS0_HES (1 << MAS0_HES_SHIFT)
730
731 #define MAS0_ESEL_SHIFT 16
732 #define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
733
734 #define MAS0_TLBSEL_SHIFT 28
735 #define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
736 #define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
737 #define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
738 #define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
739 #define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
740
741 #define MAS0_ATSEL_SHIFT 31
742 #define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
743 #define MAS0_ATSEL_TLB 0
744 #define MAS0_ATSEL_LRAT MAS0_ATSEL
745
746 #define MAS1_TSIZE_SHIFT 7
747 #define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT)
748
749 #define MAS1_TS_SHIFT 12
750 #define MAS1_TS (1 << MAS1_TS_SHIFT)
751
752 #define MAS1_IND_SHIFT 13
753 #define MAS1_IND (1 << MAS1_IND_SHIFT)
754
755 #define MAS1_TID_SHIFT 16
756 #define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
757
758 #define MAS1_IPROT_SHIFT 30
759 #define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
760
761 #define MAS1_VALID_SHIFT 31
762 #define MAS1_VALID 0x80000000
763
764 #define MAS2_EPN_SHIFT 12
765 #define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT)
766
767 #define MAS2_ACM_SHIFT 6
768 #define MAS2_ACM (1 << MAS2_ACM_SHIFT)
769
770 #define MAS2_VLE_SHIFT 5
771 #define MAS2_VLE (1 << MAS2_VLE_SHIFT)
772
773 #define MAS2_W_SHIFT 4
774 #define MAS2_W (1 << MAS2_W_SHIFT)
775
776 #define MAS2_I_SHIFT 3
777 #define MAS2_I (1 << MAS2_I_SHIFT)
778
779 #define MAS2_M_SHIFT 2
780 #define MAS2_M (1 << MAS2_M_SHIFT)
781
782 #define MAS2_G_SHIFT 1
783 #define MAS2_G (1 << MAS2_G_SHIFT)
784
785 #define MAS2_E_SHIFT 0
786 #define MAS2_E (1 << MAS2_E_SHIFT)
787
788 #define MAS3_RPN_SHIFT 12
789 #define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
790
791 #define MAS3_U0 0x00000200
792 #define MAS3_U1 0x00000100
793 #define MAS3_U2 0x00000080
794 #define MAS3_U3 0x00000040
795 #define MAS3_UX 0x00000020
796 #define MAS3_SX 0x00000010
797 #define MAS3_UW 0x00000008
798 #define MAS3_SW 0x00000004
799 #define MAS3_UR 0x00000002
800 #define MAS3_SR 0x00000001
801 #define MAS3_SPSIZE_SHIFT 1
802 #define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
803
804 #define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
805 #define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
806 #define MAS4_TIDSELD_MASK 0x00030000
807 #define MAS4_TIDSELD_PID0 0x00000000
808 #define MAS4_TIDSELD_PID1 0x00010000
809 #define MAS4_TIDSELD_PID2 0x00020000
810 #define MAS4_TIDSELD_PIDZ 0x00030000
811 #define MAS4_INDD 0x00008000 /* Default IND */
812 #define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
813 #define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
814 #define MAS4_ACMD 0x00000040
815 #define MAS4_VLED 0x00000020
816 #define MAS4_WD 0x00000010
817 #define MAS4_ID 0x00000008
818 #define MAS4_MD 0x00000004
819 #define MAS4_GD 0x00000002
820 #define MAS4_ED 0x00000001
821 #define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
822 #define MAS4_WIMGED_SHIFT 0
823
824 #define MAS5_SGS 0x80000000
825 #define MAS5_SLPID_MASK 0x00000fff
826
827 #define MAS6_SPID0 0x3fff0000
828 #define MAS6_SPID1 0x00007ffe
829 #define MAS6_ISIZE(x) MAS1_TSIZE(x)
830 #define MAS6_SAS 0x00000001
831 #define MAS6_SPID MAS6_SPID0
832 #define MAS6_SIND 0x00000002 /* Indirect page */
833 #define MAS6_SIND_SHIFT 1
834 #define MAS6_SPID_MASK 0x3fff0000
835 #define MAS6_SPID_SHIFT 16
836 #define MAS6_ISIZE_MASK 0x00000f80
837 #define MAS6_ISIZE_SHIFT 7
838
839 #define MAS7_RPN 0xffffffff
840
841 #define MAS8_TGS 0x80000000
842 #define MAS8_VF 0x40000000
843 #define MAS8_TLBPID 0x00000fff
844
845 /* Bit definitions for MMUCFG */
846 #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
847 #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
848 #define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
849 #define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
850 #define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
851 #define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
852 #define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
853 #define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
854 #define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
855
856 /* Bit definitions for MMUCSR0 */
857 #define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
858 #define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
859 #define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
860 #define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
861 #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
862 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
863 #define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
864 #define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
865 #define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
866 #define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
867
868 /* TLBnCFG encoding */
869 #define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
870 #define TLBnCFG_HES 0x00002000 /* HW select supported */
871 #define TLBnCFG_AVAIL 0x00004000 /* variable page size */
872 #define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
873 #define TLBnCFG_GTWE 0x00010000 /* Guest can write */
874 #define TLBnCFG_IND 0x00020000 /* IND entries supported */
875 #define TLBnCFG_PT 0x00040000 /* Can load from page table */
876 #define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
877 #define TLBnCFG_MINSIZE_SHIFT 20
878 #define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
879 #define TLBnCFG_MAXSIZE_SHIFT 16
880 #define TLBnCFG_ASSOC 0xff000000 /* Associativity */
881 #define TLBnCFG_ASSOC_SHIFT 24
882
883 /* TLBnPS encoding */
884 #define TLBnPS_4K 0x00000004
885 #define TLBnPS_8K 0x00000008
886 #define TLBnPS_16K 0x00000010
887 #define TLBnPS_32K 0x00000020
888 #define TLBnPS_64K 0x00000040
889 #define TLBnPS_128K 0x00000080
890 #define TLBnPS_256K 0x00000100
891 #define TLBnPS_512K 0x00000200
892 #define TLBnPS_1M 0x00000400
893 #define TLBnPS_2M 0x00000800
894 #define TLBnPS_4M 0x00001000
895 #define TLBnPS_8M 0x00002000
896 #define TLBnPS_16M 0x00004000
897 #define TLBnPS_32M 0x00008000
898 #define TLBnPS_64M 0x00010000
899 #define TLBnPS_128M 0x00020000
900 #define TLBnPS_256M 0x00040000
901 #define TLBnPS_512M 0x00080000
902 #define TLBnPS_1G 0x00100000
903 #define TLBnPS_2G 0x00200000
904 #define TLBnPS_4G 0x00400000
905 #define TLBnPS_8G 0x00800000
906 #define TLBnPS_16G 0x01000000
907 #define TLBnPS_32G 0x02000000
908 #define TLBnPS_64G 0x04000000
909 #define TLBnPS_128G 0x08000000
910 #define TLBnPS_256G 0x10000000
911
912 /* tlbilx action encoding */
913 #define TLBILX_T_ALL 0
914 #define TLBILX_T_TID 1
915 #define TLBILX_T_FULLMATCH 3
916 #define TLBILX_T_CLASS0 4
917 #define TLBILX_T_CLASS1 5
918 #define TLBILX_T_CLASS2 6
919 #define TLBILX_T_CLASS3 7
920
921 /* BookE 2.06 helper defines */
922
923 #define BOOKE206_FLUSH_TLB0 (1 << 0)
924 #define BOOKE206_FLUSH_TLB1 (1 << 1)
925 #define BOOKE206_FLUSH_TLB2 (1 << 2)
926 #define BOOKE206_FLUSH_TLB3 (1 << 3)
927
928 /* number of possible TLBs */
929 #define BOOKE206_MAX_TLBN 4
930
931 /*****************************************************************************/
932 /* Server and Embedded Processor Control */
933
934 #define DBELL_TYPE_SHIFT 27
935 #define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT)
936 #define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT)
937 #define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT)
938 #define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT)
939 #define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT)
940 #define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT)
941
942 #define DBELL_TYPE_DBELL_SERVER (0x05 << DBELL_TYPE_SHIFT)
943
944 #define DBELL_BRDCAST PPC_BIT(37)
945 #define DBELL_LPIDTAG_SHIFT 14
946 #define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT)
947 #define DBELL_PIRTAG_MASK 0x3fff
948
949 #define DBELL_PROCIDTAG_MASK PPC_BITMASK(44, 63)
950
951 /*****************************************************************************/
952 /* Segment page size information, used by recent hash MMUs
953 * The format of this structure mirrors kvm_ppc_smmu_info
954 */
955
956 #define PPC_PAGE_SIZES_MAX_SZ 8
957
958 struct ppc_one_page_size {
959 uint32_t page_shift; /* Page shift (or 0) */
960 uint32_t pte_enc; /* Encoding in the HPTE (>>12) */
961 };
962
963 struct ppc_one_seg_page_size {
964 uint32_t page_shift; /* Base page shift of segment (or 0) */
965 uint32_t slb_enc; /* SLB encoding for BookS */
966 struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ];
967 };
968
969 struct ppc_segment_page_sizes {
970 struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
971 };
972
973 struct ppc_radix_page_info {
974 uint32_t count;
975 uint32_t entries[PPC_PAGE_SIZES_MAX_SZ];
976 };
977
978 /*****************************************************************************/
979 /* The whole PowerPC CPU context */
980 #define NB_MMU_MODES 8
981
982 #define PPC_CPU_OPCODES_LEN 0x40
983 #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
984
985 struct CPUPPCState {
986 /* First are the most commonly used resources
987 * during translated code execution
988 */
989 /* general purpose registers */
990 target_ulong gpr[32];
991 /* Storage for GPR MSB, used by the SPE extension */
992 target_ulong gprh[32];
993 /* LR */
994 target_ulong lr;
995 /* CTR */
996 target_ulong ctr;
997 /* condition register */
998 uint32_t crf[8];
999 #if defined(TARGET_PPC64)
1000 /* CFAR */
1001 target_ulong cfar;
1002 #endif
1003 /* XER (with SO, OV, CA split out) */
1004 target_ulong xer;
1005 target_ulong so;
1006 target_ulong ov;
1007 target_ulong ca;
1008 target_ulong ov32;
1009 target_ulong ca32;
1010 /* Reservation address */
1011 target_ulong reserve_addr;
1012 /* Reservation value */
1013 target_ulong reserve_val;
1014 target_ulong reserve_val2;
1015 /* Reservation store address */
1016 target_ulong reserve_ea;
1017 /* Reserved store source register and size */
1018 target_ulong reserve_info;
1019
1020 /* Those ones are used in supervisor mode only */
1021 /* machine state register */
1022 target_ulong msr;
1023 /* temporary general purpose registers */
1024 target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
1025
1026 /* Floating point execution context */
1027 float_status fp_status;
1028 /* floating point registers */
1029 float64 fpr[32];
1030 /* floating point status and control register */
1031 target_ulong fpscr;
1032
1033 /* Next instruction pointer */
1034 target_ulong nip;
1035
1036 int access_type; /* when a memory exception occurs, the access
1037 type is stored here */
1038
1039 CPU_COMMON
1040
1041 /* MMU context - only relevant for full system emulation */
1042 #if !defined(CONFIG_USER_ONLY)
1043 #if defined(TARGET_PPC64)
1044 /* PowerPC 64 SLB area */
1045 ppc_slb_t slb[MAX_SLB_ENTRIES];
1046 int32_t slb_nr;
1047 /* tcg TLB needs flush (deferred slb inval instruction typically) */
1048 #endif
1049 /* segment registers */
1050 target_ulong sr[32];
1051 /* BATs */
1052 uint32_t nb_BATs;
1053 target_ulong DBAT[2][8];
1054 target_ulong IBAT[2][8];
1055 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
1056 int32_t nb_tlb; /* Total number of TLB */
1057 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
1058 int nb_ways; /* Number of ways in the TLB set */
1059 int last_way; /* Last used way used to allocate TLB in a LRU way */
1060 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
1061 int nb_pids; /* Number of available PID registers */
1062 int tlb_type; /* Type of TLB we're dealing with */
1063 ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
1064 /* 403 dedicated access protection registers */
1065 target_ulong pb[4];
1066 bool tlb_dirty; /* Set to non-zero when modifying TLB */
1067 bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
1068 uint32_t tlb_need_flush; /* Delayed flush needed */
1069 #define TLB_NEED_LOCAL_FLUSH 0x1
1070 #define TLB_NEED_GLOBAL_FLUSH 0x2
1071 #endif
1072
1073 /* Other registers */
1074 /* Special purpose registers */
1075 target_ulong spr[1024];
1076 ppc_spr_t spr_cb[1024];
1077 /* Altivec registers */
1078 ppc_avr_t avr[32];
1079 uint32_t vscr;
1080 /* VSX registers */
1081 uint64_t vsr[32];
1082 /* SPE registers */
1083 uint64_t spe_acc;
1084 uint32_t spe_fscr;
1085 /* SPE and Altivec can share a status since they will never be used
1086 * simultaneously */
1087 float_status vec_status;
1088
1089 /* Internal devices resources */
1090 /* Time base and decrementer */
1091 ppc_tb_t *tb_env;
1092 /* Device control registers */
1093 ppc_dcr_t *dcr_env;
1094
1095 int dcache_line_size;
1096 int icache_line_size;
1097
1098 /* Those resources are used during exception processing */
1099 /* CPU model definition */
1100 target_ulong msr_mask;
1101 powerpc_mmu_t mmu_model;
1102 powerpc_excp_t excp_model;
1103 powerpc_input_t bus_model;
1104 int bfd_mach;
1105 uint32_t flags;
1106 uint64_t insns_flags;
1107 uint64_t insns_flags2;
1108 #if defined(TARGET_PPC64)
1109 struct ppc_segment_page_sizes sps;
1110 ppc_slb_t vrma_slb;
1111 target_ulong rmls;
1112 bool ci_large_pages;
1113 #endif
1114
1115 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1116 uint64_t vpa_addr;
1117 uint64_t slb_shadow_addr, slb_shadow_size;
1118 uint64_t dtl_addr, dtl_size;
1119 #endif /* TARGET_PPC64 */
1120
1121 int error_code;
1122 uint32_t pending_interrupts;
1123 #if !defined(CONFIG_USER_ONLY)
1124 /* This is the IRQ controller, which is implementation dependent
1125 * and only relevant when emulating a complete machine.
1126 */
1127 uint32_t irq_input_state;
1128 void **irq_inputs;
1129 /* Exception vectors */
1130 target_ulong excp_vectors[POWERPC_EXCP_NB];
1131 target_ulong excp_prefix;
1132 target_ulong ivor_mask;
1133 target_ulong ivpr_mask;
1134 target_ulong hreset_vector;
1135 hwaddr mpic_iack;
1136 /* true when the external proxy facility mode is enabled */
1137 bool mpic_proxy;
1138 /* set when the processor has an HV mode, thus HV priv
1139 * instructions and SPRs are diallowed if MSR:HV is 0
1140 */
1141 bool has_hv_mode;
1142 /* On P7/P8, set when in PM state, we need to handle resume
1143 * in a special way (such as routing some resume causes to
1144 * 0x100), so flag this here.
1145 */
1146 bool in_pm_state;
1147 #endif
1148
1149 /* Those resources are used only during code translation */
1150 /* opcode handlers */
1151 opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
1152
1153 /* Those resources are used only in QEMU core */
1154 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
1155 target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
1156 int immu_idx; /* precomputed MMU index to speed up insn access */
1157 int dmmu_idx; /* precomputed MMU index to speed up data accesses */
1158
1159 /* Power management */
1160 int (*check_pow)(CPUPPCState *env);
1161
1162 #if !defined(CONFIG_USER_ONLY)
1163 void *load_info; /* Holds boot loading state. */
1164 #endif
1165
1166 /* booke timers */
1167
1168 /* Specifies bit locations of the Time Base used to signal a fixed timer
1169 * exception on a transition from 0 to 1. (watchdog or fixed-interval timer)
1170 *
1171 * 0 selects the least significant bit.
1172 * 63 selects the most significant bit.
1173 */
1174 uint8_t fit_period[4];
1175 uint8_t wdt_period[4];
1176
1177 /* Transactional memory state */
1178 target_ulong tm_gpr[32];
1179 ppc_avr_t tm_vsr[64];
1180 uint64_t tm_cr;
1181 uint64_t tm_lr;
1182 uint64_t tm_ctr;
1183 uint64_t tm_fpscr;
1184 uint64_t tm_amr;
1185 uint64_t tm_ppr;
1186 uint64_t tm_vrsave;
1187 uint32_t tm_vscr;
1188 uint64_t tm_dscr;
1189 uint64_t tm_tar;
1190 };
1191
1192 #define SET_FIT_PERIOD(a_, b_, c_, d_) \
1193 do { \
1194 env->fit_period[0] = (a_); \
1195 env->fit_period[1] = (b_); \
1196 env->fit_period[2] = (c_); \
1197 env->fit_period[3] = (d_); \
1198 } while (0)
1199
1200 #define SET_WDT_PERIOD(a_, b_, c_, d_) \
1201 do { \
1202 env->wdt_period[0] = (a_); \
1203 env->wdt_period[1] = (b_); \
1204 env->wdt_period[2] = (c_); \
1205 env->wdt_period[3] = (d_); \
1206 } while (0)
1207
1208 typedef struct PPCVirtualHypervisor PPCVirtualHypervisor;
1209 typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
1210
1211 /**
1212 * PowerPCCPU:
1213 * @env: #CPUPPCState
1214 * @vcpu_id: vCPU identifier given to KVM
1215 * @compat_pvr: Current logical PVR, zero if in "raw" mode
1216 *
1217 * A PowerPC CPU.
1218 */
1219 struct PowerPCCPU {
1220 /*< private >*/
1221 CPUState parent_obj;
1222 /*< public >*/
1223
1224 CPUPPCState env;
1225 int vcpu_id;
1226 uint32_t compat_pvr;
1227 PPCVirtualHypervisor *vhyp;
1228 Object *intc;
1229 int32_t node_id; /* NUMA node this CPU belongs to */
1230
1231 /* Fields related to migration compatibility hacks */
1232 bool pre_2_8_migration;
1233 target_ulong mig_msr_mask;
1234 uint64_t mig_insns_flags;
1235 uint64_t mig_insns_flags2;
1236 uint32_t mig_nb_BATs;
1237 bool pre_2_10_migration;
1238 };
1239
1240 static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env)
1241 {
1242 return container_of(env, PowerPCCPU, env);
1243 }
1244
1245 #define ENV_GET_CPU(e) CPU(ppc_env_get_cpu(e))
1246
1247 #define ENV_OFFSET offsetof(PowerPCCPU, env)
1248
1249 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
1250 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
1251 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc);
1252
1253 struct PPCVirtualHypervisor {
1254 Object parent;
1255 };
1256
1257 struct PPCVirtualHypervisorClass {
1258 InterfaceClass parent;
1259 void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1260 hwaddr (*hpt_mask)(PPCVirtualHypervisor *vhyp);
1261 const ppc_hash_pte64_t *(*map_hptes)(PPCVirtualHypervisor *vhyp,
1262 hwaddr ptex, int n);
1263 void (*unmap_hptes)(PPCVirtualHypervisor *vhyp,
1264 const ppc_hash_pte64_t *hptes,
1265 hwaddr ptex, int n);
1266 void (*store_hpte)(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1267 uint64_t pte0, uint64_t pte1);
1268 uint64_t (*get_patbe)(PPCVirtualHypervisor *vhyp);
1269 target_ulong (*encode_hpt_for_kvm_pr)(PPCVirtualHypervisor *vhyp);
1270 };
1271
1272 #define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor"
1273 #define PPC_VIRTUAL_HYPERVISOR(obj) \
1274 OBJECT_CHECK(PPCVirtualHypervisor, (obj), TYPE_PPC_VIRTUAL_HYPERVISOR)
1275 #define PPC_VIRTUAL_HYPERVISOR_CLASS(klass) \
1276 OBJECT_CLASS_CHECK(PPCVirtualHypervisorClass, (klass), \
1277 TYPE_PPC_VIRTUAL_HYPERVISOR)
1278 #define PPC_VIRTUAL_HYPERVISOR_GET_CLASS(obj) \
1279 OBJECT_GET_CLASS(PPCVirtualHypervisorClass, (obj), \
1280 TYPE_PPC_VIRTUAL_HYPERVISOR)
1281
1282 void ppc_cpu_do_interrupt(CPUState *cpu);
1283 bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
1284 void ppc_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
1285 int flags);
1286 void ppc_cpu_dump_statistics(CPUState *cpu, FILE *f,
1287 fprintf_function cpu_fprintf, int flags);
1288 hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
1289 int ppc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
1290 int ppc_cpu_gdb_read_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1291 int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1292 int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1293 int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1294 int cpuid, void *opaque);
1295 int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1296 int cpuid, void *opaque);
1297 #ifndef CONFIG_USER_ONLY
1298 void ppc_cpu_do_system_reset(CPUState *cs);
1299 extern const struct VMStateDescription vmstate_ppc_cpu;
1300 #endif
1301
1302 /*****************************************************************************/
1303 void ppc_translate_init(void);
1304 /* you can call this signal handler from your SIGBUS and SIGSEGV
1305 signal handlers to inform the virtual CPU of exceptions. non zero
1306 is returned if the signal was handled by the virtual CPU. */
1307 int cpu_ppc_signal_handler (int host_signum, void *pinfo,
1308 void *puc);
1309 #if defined(CONFIG_USER_ONLY)
1310 int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
1311 int mmu_idx);
1312 #endif
1313
1314 #if !defined(CONFIG_USER_ONLY)
1315 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
1316 #endif /* !defined(CONFIG_USER_ONLY) */
1317 void ppc_store_msr (CPUPPCState *env, target_ulong value);
1318
1319 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
1320 #if defined(TARGET_PPC64)
1321 #endif
1322
1323 /* Time-base and decrementer management */
1324 #ifndef NO_CPU_IO_DEFS
1325 uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
1326 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
1327 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
1328 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
1329 uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
1330 uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
1331 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
1332 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
1333 bool ppc_decr_clear_on_delivery(CPUPPCState *env);
1334 uint32_t cpu_ppc_load_decr (CPUPPCState *env);
1335 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
1336 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
1337 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
1338 uint64_t cpu_ppc_load_purr (CPUPPCState *env);
1339 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
1340 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
1341 #if !defined(CONFIG_USER_ONLY)
1342 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
1343 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
1344 target_ulong load_40x_pit (CPUPPCState *env);
1345 void store_40x_pit (CPUPPCState *env, target_ulong val);
1346 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
1347 void store_40x_sler (CPUPPCState *env, uint32_t val);
1348 void store_booke_tcr (CPUPPCState *env, target_ulong val);
1349 void store_booke_tsr (CPUPPCState *env, target_ulong val);
1350 void ppc_tlb_invalidate_all (CPUPPCState *env);
1351 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
1352 void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp);
1353 #endif
1354 #endif
1355
1356 void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
1357
1358 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1359 {
1360 uint64_t gprv;
1361
1362 gprv = env->gpr[gprn];
1363 if (env->flags & POWERPC_FLAG_SPE) {
1364 /* If the CPU implements the SPE extension, we have to get the
1365 * high bits of the GPR from the gprh storage area
1366 */
1367 gprv &= 0xFFFFFFFFULL;
1368 gprv |= (uint64_t)env->gprh[gprn] << 32;
1369 }
1370
1371 return gprv;
1372 }
1373
1374 /* Device control registers */
1375 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1376 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1377
1378 #define cpu_init(cpu_model) cpu_generic_init(TYPE_POWERPC_CPU, cpu_model)
1379
1380 #define POWERPC_CPU_TYPE_SUFFIX "-" TYPE_POWERPC_CPU
1381 #define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX
1382 #define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU
1383
1384 #define cpu_signal_handler cpu_ppc_signal_handler
1385 #define cpu_list ppc_cpu_list
1386
1387 /* MMU modes definitions */
1388 #define MMU_USER_IDX 0
1389 static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
1390 {
1391 return ifetch ? env->immu_idx : env->dmmu_idx;
1392 }
1393
1394 /* Compatibility modes */
1395 #if defined(TARGET_PPC64)
1396 bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr,
1397 uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1398 void ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp);
1399 #if !defined(CONFIG_USER_ONLY)
1400 void ppc_set_compat_all(uint32_t compat_pvr, Error **errp);
1401 #endif
1402 int ppc_compat_max_vthreads(PowerPCCPU *cpu);
1403 void ppc_compat_add_property(Object *obj, const char *name,
1404 uint32_t *compat_pvr, const char *basedesc,
1405 Error **errp);
1406 #endif /* defined(TARGET_PPC64) */
1407
1408 #include "exec/cpu-all.h"
1409
1410 /*****************************************************************************/
1411 /* CRF definitions */
1412 #define CRF_LT_BIT 3
1413 #define CRF_GT_BIT 2
1414 #define CRF_EQ_BIT 1
1415 #define CRF_SO_BIT 0
1416 #define CRF_LT (1 << CRF_LT_BIT)
1417 #define CRF_GT (1 << CRF_GT_BIT)
1418 #define CRF_EQ (1 << CRF_EQ_BIT)
1419 #define CRF_SO (1 << CRF_SO_BIT)
1420 /* For SPE extensions */
1421 #define CRF_CH (1 << CRF_LT_BIT)
1422 #define CRF_CL (1 << CRF_GT_BIT)
1423 #define CRF_CH_OR_CL (1 << CRF_EQ_BIT)
1424 #define CRF_CH_AND_CL (1 << CRF_SO_BIT)
1425
1426 /* XER definitions */
1427 #define XER_SO 31
1428 #define XER_OV 30
1429 #define XER_CA 29
1430 #define XER_OV32 19
1431 #define XER_CA32 18
1432 #define XER_CMP 8
1433 #define XER_BC 0
1434 #define xer_so (env->so)
1435 #define xer_ov (env->ov)
1436 #define xer_ca (env->ca)
1437 #define xer_ov32 (env->ov)
1438 #define xer_ca32 (env->ca)
1439 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1440 #define xer_bc ((env->xer >> XER_BC) & 0x7F)
1441
1442 /* SPR definitions */
1443 #define SPR_MQ (0x000)
1444 #define SPR_XER (0x001)
1445 #define SPR_601_VRTCU (0x004)
1446 #define SPR_601_VRTCL (0x005)
1447 #define SPR_601_UDECR (0x006)
1448 #define SPR_LR (0x008)
1449 #define SPR_CTR (0x009)
1450 #define SPR_UAMR (0x00D)
1451 #define SPR_DSCR (0x011)
1452 #define SPR_DSISR (0x012)
1453 #define SPR_DAR (0x013) /* DAE for PowerPC 601 */
1454 #define SPR_601_RTCU (0x014)
1455 #define SPR_601_RTCL (0x015)
1456 #define SPR_DECR (0x016)
1457 #define SPR_SDR1 (0x019)
1458 #define SPR_SRR0 (0x01A)
1459 #define SPR_SRR1 (0x01B)
1460 #define SPR_CFAR (0x01C)
1461 #define SPR_AMR (0x01D)
1462 #define SPR_ACOP (0x01F)
1463 #define SPR_BOOKE_PID (0x030)
1464 #define SPR_BOOKS_PID (0x030)
1465 #define SPR_BOOKE_DECAR (0x036)
1466 #define SPR_BOOKE_CSRR0 (0x03A)
1467 #define SPR_BOOKE_CSRR1 (0x03B)
1468 #define SPR_BOOKE_DEAR (0x03D)
1469 #define SPR_IAMR (0x03D)
1470 #define SPR_BOOKE_ESR (0x03E)
1471 #define SPR_BOOKE_IVPR (0x03F)
1472 #define SPR_MPC_EIE (0x050)
1473 #define SPR_MPC_EID (0x051)
1474 #define SPR_MPC_NRI (0x052)
1475 #define SPR_TFHAR (0x080)
1476 #define SPR_TFIAR (0x081)
1477 #define SPR_TEXASR (0x082)
1478 #define SPR_TEXASRU (0x083)
1479 #define SPR_UCTRL (0x088)
1480 #define SPR_TIDR (0x090)
1481 #define SPR_MPC_CMPA (0x090)
1482 #define SPR_MPC_CMPB (0x091)
1483 #define SPR_MPC_CMPC (0x092)
1484 #define SPR_MPC_CMPD (0x093)
1485 #define SPR_MPC_ECR (0x094)
1486 #define SPR_MPC_DER (0x095)
1487 #define SPR_MPC_COUNTA (0x096)
1488 #define SPR_MPC_COUNTB (0x097)
1489 #define SPR_CTRL (0x098)
1490 #define SPR_MPC_CMPE (0x098)
1491 #define SPR_MPC_CMPF (0x099)
1492 #define SPR_FSCR (0x099)
1493 #define SPR_MPC_CMPG (0x09A)
1494 #define SPR_MPC_CMPH (0x09B)
1495 #define SPR_MPC_LCTRL1 (0x09C)
1496 #define SPR_MPC_LCTRL2 (0x09D)
1497 #define SPR_UAMOR (0x09D)
1498 #define SPR_MPC_ICTRL (0x09E)
1499 #define SPR_MPC_BAR (0x09F)
1500 #define SPR_PSPB (0x09F)
1501 #define SPR_DAWR (0x0B4)
1502 #define SPR_RPR (0x0BA)
1503 #define SPR_CIABR (0x0BB)
1504 #define SPR_DAWRX (0x0BC)
1505 #define SPR_HFSCR (0x0BE)
1506 #define SPR_VRSAVE (0x100)
1507 #define SPR_USPRG0 (0x100)
1508 #define SPR_USPRG1 (0x101)
1509 #define SPR_USPRG2 (0x102)
1510 #define SPR_USPRG3 (0x103)
1511 #define SPR_USPRG4 (0x104)
1512 #define SPR_USPRG5 (0x105)
1513 #define SPR_USPRG6 (0x106)
1514 #define SPR_USPRG7 (0x107)
1515 #define SPR_VTBL (0x10C)
1516 #define SPR_VTBU (0x10D)
1517 #define SPR_SPRG0 (0x110)
1518 #define SPR_SPRG1 (0x111)
1519 #define SPR_SPRG2 (0x112)
1520 #define SPR_SPRG3 (0x113)
1521 #define SPR_SPRG4 (0x114)
1522 #define SPR_SCOMC (0x114)
1523 #define SPR_SPRG5 (0x115)
1524 #define SPR_SCOMD (0x115)
1525 #define SPR_SPRG6 (0x116)
1526 #define SPR_SPRG7 (0x117)
1527 #define SPR_ASR (0x118)
1528 #define SPR_EAR (0x11A)
1529 #define SPR_TBL (0x11C)
1530 #define SPR_TBU (0x11D)
1531 #define SPR_TBU40 (0x11E)
1532 #define SPR_SVR (0x11E)
1533 #define SPR_BOOKE_PIR (0x11E)
1534 #define SPR_PVR (0x11F)
1535 #define SPR_HSPRG0 (0x130)
1536 #define SPR_BOOKE_DBSR (0x130)
1537 #define SPR_HSPRG1 (0x131)
1538 #define SPR_HDSISR (0x132)
1539 #define SPR_HDAR (0x133)
1540 #define SPR_BOOKE_EPCR (0x133)
1541 #define SPR_SPURR (0x134)
1542 #define SPR_BOOKE_DBCR0 (0x134)
1543 #define SPR_IBCR (0x135)
1544 #define SPR_PURR (0x135)
1545 #define SPR_BOOKE_DBCR1 (0x135)
1546 #define SPR_DBCR (0x136)
1547 #define SPR_HDEC (0x136)
1548 #define SPR_BOOKE_DBCR2 (0x136)
1549 #define SPR_HIOR (0x137)
1550 #define SPR_MBAR (0x137)
1551 #define SPR_RMOR (0x138)
1552 #define SPR_BOOKE_IAC1 (0x138)
1553 #define SPR_HRMOR (0x139)
1554 #define SPR_BOOKE_IAC2 (0x139)
1555 #define SPR_HSRR0 (0x13A)
1556 #define SPR_BOOKE_IAC3 (0x13A)
1557 #define SPR_HSRR1 (0x13B)
1558 #define SPR_BOOKE_IAC4 (0x13B)
1559 #define SPR_BOOKE_DAC1 (0x13C)
1560 #define SPR_MMCRH (0x13C)
1561 #define SPR_DABR2 (0x13D)
1562 #define SPR_BOOKE_DAC2 (0x13D)
1563 #define SPR_TFMR (0x13D)
1564 #define SPR_BOOKE_DVC1 (0x13E)
1565 #define SPR_LPCR (0x13E)
1566 #define SPR_BOOKE_DVC2 (0x13F)
1567 #define SPR_LPIDR (0x13F)
1568 #define SPR_BOOKE_TSR (0x150)
1569 #define SPR_HMER (0x150)
1570 #define SPR_HMEER (0x151)
1571 #define SPR_PCR (0x152)
1572 #define SPR_BOOKE_LPIDR (0x152)
1573 #define SPR_BOOKE_TCR (0x154)
1574 #define SPR_BOOKE_TLB0PS (0x158)
1575 #define SPR_BOOKE_TLB1PS (0x159)
1576 #define SPR_BOOKE_TLB2PS (0x15A)
1577 #define SPR_BOOKE_TLB3PS (0x15B)
1578 #define SPR_AMOR (0x15D)
1579 #define SPR_BOOKE_MAS7_MAS3 (0x174)
1580 #define SPR_BOOKE_IVOR0 (0x190)
1581 #define SPR_BOOKE_IVOR1 (0x191)
1582 #define SPR_BOOKE_IVOR2 (0x192)
1583 #define SPR_BOOKE_IVOR3 (0x193)
1584 #define SPR_BOOKE_IVOR4 (0x194)
1585 #define SPR_BOOKE_IVOR5 (0x195)
1586 #define SPR_BOOKE_IVOR6 (0x196)
1587 #define SPR_BOOKE_IVOR7 (0x197)
1588 #define SPR_BOOKE_IVOR8 (0x198)
1589 #define SPR_BOOKE_IVOR9 (0x199)
1590 #define SPR_BOOKE_IVOR10 (0x19A)
1591 #define SPR_BOOKE_IVOR11 (0x19B)
1592 #define SPR_BOOKE_IVOR12 (0x19C)
1593 #define SPR_BOOKE_IVOR13 (0x19D)
1594 #define SPR_BOOKE_IVOR14 (0x19E)
1595 #define SPR_BOOKE_IVOR15 (0x19F)
1596 #define SPR_BOOKE_IVOR38 (0x1B0)
1597 #define SPR_BOOKE_IVOR39 (0x1B1)
1598 #define SPR_BOOKE_IVOR40 (0x1B2)
1599 #define SPR_BOOKE_IVOR41 (0x1B3)
1600 #define SPR_BOOKE_IVOR42 (0x1B4)
1601 #define SPR_BOOKE_GIVOR2 (0x1B8)
1602 #define SPR_BOOKE_GIVOR3 (0x1B9)
1603 #define SPR_BOOKE_GIVOR4 (0x1BA)
1604 #define SPR_BOOKE_GIVOR8 (0x1BB)
1605 #define SPR_BOOKE_GIVOR13 (0x1BC)
1606 #define SPR_BOOKE_GIVOR14 (0x1BD)
1607 #define SPR_TIR (0x1BE)
1608 #define SPR_BOOKE_SPEFSCR (0x200)
1609 #define SPR_Exxx_BBEAR (0x201)
1610 #define SPR_Exxx_BBTAR (0x202)
1611 #define SPR_Exxx_L1CFG0 (0x203)
1612 #define SPR_Exxx_L1CFG1 (0x204)
1613 #define SPR_Exxx_NPIDR (0x205)
1614 #define SPR_ATBL (0x20E)
1615 #define SPR_ATBU (0x20F)
1616 #define SPR_IBAT0U (0x210)
1617 #define SPR_BOOKE_IVOR32 (0x210)
1618 #define SPR_RCPU_MI_GRA (0x210)
1619 #define SPR_IBAT0L (0x211)
1620 #define SPR_BOOKE_IVOR33 (0x211)
1621 #define SPR_IBAT1U (0x212)
1622 #define SPR_BOOKE_IVOR34 (0x212)
1623 #define SPR_IBAT1L (0x213)
1624 #define SPR_BOOKE_IVOR35 (0x213)
1625 #define SPR_IBAT2U (0x214)
1626 #define SPR_BOOKE_IVOR36 (0x214)
1627 #define SPR_IBAT2L (0x215)
1628 #define SPR_BOOKE_IVOR37 (0x215)
1629 #define SPR_IBAT3U (0x216)
1630 #define SPR_IBAT3L (0x217)
1631 #define SPR_DBAT0U (0x218)
1632 #define SPR_RCPU_L2U_GRA (0x218)
1633 #define SPR_DBAT0L (0x219)
1634 #define SPR_DBAT1U (0x21A)
1635 #define SPR_DBAT1L (0x21B)
1636 #define SPR_DBAT2U (0x21C)
1637 #define SPR_DBAT2L (0x21D)
1638 #define SPR_DBAT3U (0x21E)
1639 #define SPR_DBAT3L (0x21F)
1640 #define SPR_IBAT4U (0x230)
1641 #define SPR_RPCU_BBCMCR (0x230)
1642 #define SPR_MPC_IC_CST (0x230)
1643 #define SPR_Exxx_CTXCR (0x230)
1644 #define SPR_IBAT4L (0x231)
1645 #define SPR_MPC_IC_ADR (0x231)
1646 #define SPR_Exxx_DBCR3 (0x231)
1647 #define SPR_IBAT5U (0x232)
1648 #define SPR_MPC_IC_DAT (0x232)
1649 #define SPR_Exxx_DBCNT (0x232)
1650 #define SPR_IBAT5L (0x233)
1651 #define SPR_IBAT6U (0x234)
1652 #define SPR_IBAT6L (0x235)
1653 #define SPR_IBAT7U (0x236)
1654 #define SPR_IBAT7L (0x237)
1655 #define SPR_DBAT4U (0x238)
1656 #define SPR_RCPU_L2U_MCR (0x238)
1657 #define SPR_MPC_DC_CST (0x238)
1658 #define SPR_Exxx_ALTCTXCR (0x238)
1659 #define SPR_DBAT4L (0x239)
1660 #define SPR_MPC_DC_ADR (0x239)
1661 #define SPR_DBAT5U (0x23A)
1662 #define SPR_BOOKE_MCSRR0 (0x23A)
1663 #define SPR_MPC_DC_DAT (0x23A)
1664 #define SPR_DBAT5L (0x23B)
1665 #define SPR_BOOKE_MCSRR1 (0x23B)
1666 #define SPR_DBAT6U (0x23C)
1667 #define SPR_BOOKE_MCSR (0x23C)
1668 #define SPR_DBAT6L (0x23D)
1669 #define SPR_Exxx_MCAR (0x23D)
1670 #define SPR_DBAT7U (0x23E)
1671 #define SPR_BOOKE_DSRR0 (0x23E)
1672 #define SPR_DBAT7L (0x23F)
1673 #define SPR_BOOKE_DSRR1 (0x23F)
1674 #define SPR_BOOKE_SPRG8 (0x25C)
1675 #define SPR_BOOKE_SPRG9 (0x25D)
1676 #define SPR_BOOKE_MAS0 (0x270)
1677 #define SPR_BOOKE_MAS1 (0x271)
1678 #define SPR_BOOKE_MAS2 (0x272)
1679 #define SPR_BOOKE_MAS3 (0x273)
1680 #define SPR_BOOKE_MAS4 (0x274)
1681 #define SPR_BOOKE_MAS5 (0x275)
1682 #define SPR_BOOKE_MAS6 (0x276)
1683 #define SPR_BOOKE_PID1 (0x279)
1684 #define SPR_BOOKE_PID2 (0x27A)
1685 #define SPR_MPC_DPDR (0x280)
1686 #define SPR_MPC_IMMR (0x288)
1687 #define SPR_BOOKE_TLB0CFG (0x2B0)
1688 #define SPR_BOOKE_TLB1CFG (0x2B1)
1689 #define SPR_BOOKE_TLB2CFG (0x2B2)
1690 #define SPR_BOOKE_TLB3CFG (0x2B3)
1691 #define SPR_BOOKE_EPR (0x2BE)
1692 #define SPR_PERF0 (0x300)
1693 #define SPR_RCPU_MI_RBA0 (0x300)
1694 #define SPR_MPC_MI_CTR (0x300)
1695 #define SPR_POWER_USIER (0x300)
1696 #define SPR_PERF1 (0x301)
1697 #define SPR_RCPU_MI_RBA1 (0x301)
1698 #define SPR_POWER_UMMCR2 (0x301)
1699 #define SPR_PERF2 (0x302)
1700 #define SPR_RCPU_MI_RBA2 (0x302)
1701 #define SPR_MPC_MI_AP (0x302)
1702 #define SPR_POWER_UMMCRA (0x302)
1703 #define SPR_PERF3 (0x303)
1704 #define SPR_RCPU_MI_RBA3 (0x303)
1705 #define SPR_MPC_MI_EPN (0x303)
1706 #define SPR_POWER_UPMC1 (0x303)
1707 #define SPR_PERF4 (0x304)
1708 #define SPR_POWER_UPMC2 (0x304)
1709 #define SPR_PERF5 (0x305)
1710 #define SPR_MPC_MI_TWC (0x305)
1711 #define SPR_POWER_UPMC3 (0x305)
1712 #define SPR_PERF6 (0x306)
1713 #define SPR_MPC_MI_RPN (0x306)
1714 #define SPR_POWER_UPMC4 (0x306)
1715 #define SPR_PERF7 (0x307)
1716 #define SPR_POWER_UPMC5 (0x307)
1717 #define SPR_PERF8 (0x308)
1718 #define SPR_RCPU_L2U_RBA0 (0x308)
1719 #define SPR_MPC_MD_CTR (0x308)
1720 #define SPR_POWER_UPMC6 (0x308)
1721 #define SPR_PERF9 (0x309)
1722 #define SPR_RCPU_L2U_RBA1 (0x309)
1723 #define SPR_MPC_MD_CASID (0x309)
1724 #define SPR_970_UPMC7 (0X309)
1725 #define SPR_PERFA (0x30A)
1726 #define SPR_RCPU_L2U_RBA2 (0x30A)
1727 #define SPR_MPC_MD_AP (0x30A)
1728 #define SPR_970_UPMC8 (0X30A)
1729 #define SPR_PERFB (0x30B)
1730 #define SPR_RCPU_L2U_RBA3 (0x30B)
1731 #define SPR_MPC_MD_EPN (0x30B)
1732 #define SPR_POWER_UMMCR0 (0X30B)
1733 #define SPR_PERFC (0x30C)
1734 #define SPR_MPC_MD_TWB (0x30C)
1735 #define SPR_POWER_USIAR (0X30C)
1736 #define SPR_PERFD (0x30D)
1737 #define SPR_MPC_MD_TWC (0x30D)
1738 #define SPR_POWER_USDAR (0X30D)
1739 #define SPR_PERFE (0x30E)
1740 #define SPR_MPC_MD_RPN (0x30E)
1741 #define SPR_POWER_UMMCR1 (0X30E)
1742 #define SPR_PERFF (0x30F)
1743 #define SPR_MPC_MD_TW (0x30F)
1744 #define SPR_UPERF0 (0x310)
1745 #define SPR_POWER_SIER (0x310)
1746 #define SPR_UPERF1 (0x311)
1747 #define SPR_POWER_MMCR2 (0x311)
1748 #define SPR_UPERF2 (0x312)
1749 #define SPR_POWER_MMCRA (0X312)
1750 #define SPR_UPERF3 (0x313)
1751 #define SPR_POWER_PMC1 (0X313)
1752 #define SPR_UPERF4 (0x314)
1753 #define SPR_POWER_PMC2 (0X314)
1754 #define SPR_UPERF5 (0x315)
1755 #define SPR_POWER_PMC3 (0X315)
1756 #define SPR_UPERF6 (0x316)
1757 #define SPR_POWER_PMC4 (0X316)
1758 #define SPR_UPERF7 (0x317)
1759 #define SPR_POWER_PMC5 (0X317)
1760 #define SPR_UPERF8 (0x318)
1761 #define SPR_POWER_PMC6 (0X318)
1762 #define SPR_UPERF9 (0x319)
1763 #define SPR_970_PMC7 (0X319)
1764 #define SPR_UPERFA (0x31A)
1765 #define SPR_970_PMC8 (0X31A)
1766 #define SPR_UPERFB (0x31B)
1767 #define SPR_POWER_MMCR0 (0X31B)
1768 #define SPR_UPERFC (0x31C)
1769 #define SPR_POWER_SIAR (0X31C)
1770 #define SPR_UPERFD (0x31D)
1771 #define SPR_POWER_SDAR (0X31D)
1772 #define SPR_UPERFE (0x31E)
1773 #define SPR_POWER_MMCR1 (0X31E)
1774 #define SPR_UPERFF (0x31F)
1775 #define SPR_RCPU_MI_RA0 (0x320)
1776 #define SPR_MPC_MI_DBCAM (0x320)
1777 #define SPR_BESCRS (0x320)
1778 #define SPR_RCPU_MI_RA1 (0x321)
1779 #define SPR_MPC_MI_DBRAM0 (0x321)
1780 #define SPR_BESCRSU (0x321)
1781 #define SPR_RCPU_MI_RA2 (0x322)
1782 #define SPR_MPC_MI_DBRAM1 (0x322)
1783 #define SPR_BESCRR (0x322)
1784 #define SPR_RCPU_MI_RA3 (0x323)
1785 #define SPR_BESCRRU (0x323)
1786 #define SPR_EBBHR (0x324)
1787 #define SPR_EBBRR (0x325)
1788 #define SPR_BESCR (0x326)
1789 #define SPR_RCPU_L2U_RA0 (0x328)
1790 #define SPR_MPC_MD_DBCAM (0x328)
1791 #define SPR_RCPU_L2U_RA1 (0x329)
1792 #define SPR_MPC_MD_DBRAM0 (0x329)
1793 #define SPR_RCPU_L2U_RA2 (0x32A)
1794 #define SPR_MPC_MD_DBRAM1 (0x32A)
1795 #define SPR_RCPU_L2U_RA3 (0x32B)
1796 #define SPR_TAR (0x32F)
1797 #define SPR_IC (0x350)
1798 #define SPR_VTB (0x351)
1799 #define SPR_MMCRC (0x353)
1800 #define SPR_PSSCR (0x357)
1801 #define SPR_440_INV0 (0x370)
1802 #define SPR_440_INV1 (0x371)
1803 #define SPR_440_INV2 (0x372)
1804 #define SPR_440_INV3 (0x373)
1805 #define SPR_440_ITV0 (0x374)
1806 #define SPR_440_ITV1 (0x375)
1807 #define SPR_440_ITV2 (0x376)
1808 #define SPR_440_ITV3 (0x377)
1809 #define SPR_440_CCR1 (0x378)
1810 #define SPR_TACR (0x378)
1811 #define SPR_TCSCR (0x379)
1812 #define SPR_CSIGR (0x37a)
1813 #define SPR_DCRIPR (0x37B)
1814 #define SPR_POWER_SPMC1 (0x37C)
1815 #define SPR_POWER_SPMC2 (0x37D)
1816 #define SPR_POWER_MMCRS (0x37E)
1817 #define SPR_WORT (0x37F)
1818 #define SPR_PPR (0x380)
1819 #define SPR_750_GQR0 (0x390)
1820 #define SPR_440_DNV0 (0x390)
1821 #define SPR_750_GQR1 (0x391)
1822 #define SPR_440_DNV1 (0x391)
1823 #define SPR_750_GQR2 (0x392)
1824 #define SPR_440_DNV2 (0x392)
1825 #define SPR_750_GQR3 (0x393)
1826 #define SPR_440_DNV3 (0x393)
1827 #define SPR_750_GQR4 (0x394)
1828 #define SPR_440_DTV0 (0x394)
1829 #define SPR_750_GQR5 (0x395)
1830 #define SPR_440_DTV1 (0x395)
1831 #define SPR_750_GQR6 (0x396)
1832 #define SPR_440_DTV2 (0x396)
1833 #define SPR_750_GQR7 (0x397)
1834 #define SPR_440_DTV3 (0x397)
1835 #define SPR_750_THRM4 (0x398)
1836 #define SPR_750CL_HID2 (0x398)
1837 #define SPR_440_DVLIM (0x398)
1838 #define SPR_750_WPAR (0x399)
1839 #define SPR_440_IVLIM (0x399)
1840 #define SPR_TSCR (0x399)
1841 #define SPR_750_DMAU (0x39A)
1842 #define SPR_750_DMAL (0x39B)
1843 #define SPR_440_RSTCFG (0x39B)
1844 #define SPR_BOOKE_DCDBTRL (0x39C)
1845 #define SPR_BOOKE_DCDBTRH (0x39D)
1846 #define SPR_BOOKE_ICDBTRL (0x39E)
1847 #define SPR_BOOKE_ICDBTRH (0x39F)
1848 #define SPR_74XX_UMMCR2 (0x3A0)
1849 #define SPR_7XX_UPMC5 (0x3A1)
1850 #define SPR_7XX_UPMC6 (0x3A2)
1851 #define SPR_UBAMR (0x3A7)
1852 #define SPR_7XX_UMMCR0 (0x3A8)
1853 #define SPR_7XX_UPMC1 (0x3A9)
1854 #define SPR_7XX_UPMC2 (0x3AA)
1855 #define SPR_7XX_USIAR (0x3AB)
1856 #define SPR_7XX_UMMCR1 (0x3AC)
1857 #define SPR_7XX_UPMC3 (0x3AD)
1858 #define SPR_7XX_UPMC4 (0x3AE)
1859 #define SPR_USDA (0x3AF)
1860 #define SPR_40x_ZPR (0x3B0)
1861 #define SPR_BOOKE_MAS7 (0x3B0)
1862 #define SPR_74XX_MMCR2 (0x3B0)
1863 #define SPR_7XX_PMC5 (0x3B1)
1864 #define SPR_40x_PID (0x3B1)
1865 #define SPR_7XX_PMC6 (0x3B2)
1866 #define SPR_440_MMUCR (0x3B2)
1867 #define SPR_4xx_CCR0 (0x3B3)
1868 #define SPR_BOOKE_EPLC (0x3B3)
1869 #define SPR_405_IAC3 (0x3B4)
1870 #define SPR_BOOKE_EPSC (0x3B4)
1871 #define SPR_405_IAC4 (0x3B5)
1872 #define SPR_405_DVC1 (0x3B6)
1873 #define SPR_405_DVC2 (0x3B7)
1874 #define SPR_BAMR (0x3B7)
1875 #define SPR_7XX_MMCR0 (0x3B8)
1876 #define SPR_7XX_PMC1 (0x3B9)
1877 #define SPR_40x_SGR (0x3B9)
1878 #define SPR_7XX_PMC2 (0x3BA)
1879 #define SPR_40x_DCWR (0x3BA)
1880 #define SPR_7XX_SIAR (0x3BB)
1881 #define SPR_405_SLER (0x3BB)
1882 #define SPR_7XX_MMCR1 (0x3BC)
1883 #define SPR_405_SU0R (0x3BC)
1884 #define SPR_401_SKR (0x3BC)
1885 #define SPR_7XX_PMC3 (0x3BD)
1886 #define SPR_405_DBCR1 (0x3BD)
1887 #define SPR_7XX_PMC4 (0x3BE)
1888 #define SPR_SDA (0x3BF)
1889 #define SPR_403_VTBL (0x3CC)
1890 #define SPR_403_VTBU (0x3CD)
1891 #define SPR_DMISS (0x3D0)
1892 #define SPR_DCMP (0x3D1)
1893 #define SPR_HASH1 (0x3D2)
1894 #define SPR_HASH2 (0x3D3)
1895 #define SPR_BOOKE_ICDBDR (0x3D3)
1896 #define SPR_TLBMISS (0x3D4)
1897 #define SPR_IMISS (0x3D4)
1898 #define SPR_40x_ESR (0x3D4)
1899 #define SPR_PTEHI (0x3D5)
1900 #define SPR_ICMP (0x3D5)
1901 #define SPR_40x_DEAR (0x3D5)
1902 #define SPR_PTELO (0x3D6)
1903 #define SPR_RPA (0x3D6)
1904 #define SPR_40x_EVPR (0x3D6)
1905 #define SPR_L3PM (0x3D7)
1906 #define SPR_403_CDBCR (0x3D7)
1907 #define SPR_L3ITCR0 (0x3D8)
1908 #define SPR_TCR (0x3D8)
1909 #define SPR_40x_TSR (0x3D8)
1910 #define SPR_IBR (0x3DA)
1911 #define SPR_40x_TCR (0x3DA)
1912 #define SPR_ESASRR (0x3DB)
1913 #define SPR_40x_PIT (0x3DB)
1914 #define SPR_403_TBL (0x3DC)
1915 #define SPR_403_TBU (0x3DD)
1916 #define SPR_SEBR (0x3DE)
1917 #define SPR_40x_SRR2 (0x3DE)
1918 #define SPR_SER (0x3DF)
1919 #define SPR_40x_SRR3 (0x3DF)
1920 #define SPR_L3OHCR (0x3E8)
1921 #define SPR_L3ITCR1 (0x3E9)
1922 #define SPR_L3ITCR2 (0x3EA)
1923 #define SPR_L3ITCR3 (0x3EB)
1924 #define SPR_HID0 (0x3F0)
1925 #define SPR_40x_DBSR (0x3F0)
1926 #define SPR_HID1 (0x3F1)
1927 #define SPR_IABR (0x3F2)
1928 #define SPR_40x_DBCR0 (0x3F2)
1929 #define SPR_601_HID2 (0x3F2)
1930 #define SPR_Exxx_L1CSR0 (0x3F2)
1931 #define SPR_ICTRL (0x3F3)
1932 #define SPR_HID2 (0x3F3)
1933 #define SPR_750CL_HID4 (0x3F3)
1934 #define SPR_Exxx_L1CSR1 (0x3F3)
1935 #define SPR_440_DBDR (0x3F3)
1936 #define SPR_LDSTDB (0x3F4)
1937 #define SPR_750_TDCL (0x3F4)
1938 #define SPR_40x_IAC1 (0x3F4)
1939 #define SPR_MMUCSR0 (0x3F4)
1940 #define SPR_970_HID4 (0x3F4)
1941 #define SPR_DABR (0x3F5)
1942 #define DABR_MASK (~(target_ulong)0x7)
1943 #define SPR_Exxx_BUCSR (0x3F5)
1944 #define SPR_40x_IAC2 (0x3F5)
1945 #define SPR_601_HID5 (0x3F5)
1946 #define SPR_40x_DAC1 (0x3F6)
1947 #define SPR_MSSCR0 (0x3F6)
1948 #define SPR_970_HID5 (0x3F6)
1949 #define SPR_MSSSR0 (0x3F7)
1950 #define SPR_MSSCR1 (0x3F7)
1951 #define SPR_DABRX (0x3F7)
1952 #define SPR_40x_DAC2 (0x3F7)
1953 #define SPR_MMUCFG (0x3F7)
1954 #define SPR_LDSTCR (0x3F8)
1955 #define SPR_L2PMCR (0x3F8)
1956 #define SPR_750FX_HID2 (0x3F8)
1957 #define SPR_Exxx_L1FINV0 (0x3F8)
1958 #define SPR_L2CR (0x3F9)
1959 #define SPR_L3CR (0x3FA)
1960 #define SPR_750_TDCH (0x3FA)
1961 #define SPR_IABR2 (0x3FA)
1962 #define SPR_40x_DCCR (0x3FA)
1963 #define SPR_ICTC (0x3FB)
1964 #define SPR_40x_ICCR (0x3FB)
1965 #define SPR_THRM1 (0x3FC)
1966 #define SPR_403_PBL1 (0x3FC)
1967 #define SPR_SP (0x3FD)
1968 #define SPR_THRM2 (0x3FD)
1969 #define SPR_403_PBU1 (0x3FD)
1970 #define SPR_604_HID13 (0x3FD)
1971 #define SPR_LT (0x3FE)
1972 #define SPR_THRM3 (0x3FE)
1973 #define SPR_RCPU_FPECR (0x3FE)
1974 #define SPR_403_PBL2 (0x3FE)
1975 #define SPR_PIR (0x3FF)
1976 #define SPR_403_PBU2 (0x3FF)
1977 #define SPR_601_HID15 (0x3FF)
1978 #define SPR_604_HID15 (0x3FF)
1979 #define SPR_E500_SVR (0x3FF)
1980
1981 /* Disable MAS Interrupt Updates for Hypervisor */
1982 #define EPCR_DMIUH (1 << 22)
1983 /* Disable Guest TLB Management Instructions */
1984 #define EPCR_DGTMI (1 << 23)
1985 /* Guest Interrupt Computation Mode */
1986 #define EPCR_GICM (1 << 24)
1987 /* Interrupt Computation Mode */
1988 #define EPCR_ICM (1 << 25)
1989 /* Disable Embedded Hypervisor Debug */
1990 #define EPCR_DUVD (1 << 26)
1991 /* Instruction Storage Interrupt Directed to Guest State */
1992 #define EPCR_ISIGS (1 << 27)
1993 /* Data Storage Interrupt Directed to Guest State */
1994 #define EPCR_DSIGS (1 << 28)
1995 /* Instruction TLB Error Interrupt Directed to Guest State */
1996 #define EPCR_ITLBGS (1 << 29)
1997 /* Data TLB Error Interrupt Directed to Guest State */
1998 #define EPCR_DTLBGS (1 << 30)
1999 /* External Input Interrupt Directed to Guest State */
2000 #define EPCR_EXTGS (1 << 31)
2001
2002 #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
2003 #define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */
2004 #define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */
2005 #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
2006 #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
2007
2008 #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
2009 #define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */
2010 #define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */
2011 #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
2012 #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
2013
2014 /* HID0 bits */
2015 #define HID0_DEEPNAP (1 << 24) /* pre-2.06 */
2016 #define HID0_DOZE (1 << 23) /* pre-2.06 */
2017 #define HID0_NAP (1 << 22) /* pre-2.06 */
2018 #define HID0_HILE PPC_BIT(19) /* POWER8 */
2019 #define HID0_POWER9_HILE PPC_BIT(4)
2020
2021 /*****************************************************************************/
2022 /* PowerPC Instructions types definitions */
2023 enum {
2024 PPC_NONE = 0x0000000000000000ULL,
2025 /* PowerPC base instructions set */
2026 PPC_INSNS_BASE = 0x0000000000000001ULL,
2027 /* integer operations instructions */
2028 #define PPC_INTEGER PPC_INSNS_BASE
2029 /* flow control instructions */
2030 #define PPC_FLOW PPC_INSNS_BASE
2031 /* virtual memory instructions */
2032 #define PPC_MEM PPC_INSNS_BASE
2033 /* ld/st with reservation instructions */
2034 #define PPC_RES PPC_INSNS_BASE
2035 /* spr/msr access instructions */
2036 #define PPC_MISC PPC_INSNS_BASE
2037 /* Deprecated instruction sets */
2038 /* Original POWER instruction set */
2039 PPC_POWER = 0x0000000000000002ULL,
2040 /* POWER2 instruction set extension */
2041 PPC_POWER2 = 0x0000000000000004ULL,
2042 /* Power RTC support */
2043 PPC_POWER_RTC = 0x0000000000000008ULL,
2044 /* Power-to-PowerPC bridge (601) */
2045 PPC_POWER_BR = 0x0000000000000010ULL,
2046 /* 64 bits PowerPC instruction set */
2047 PPC_64B = 0x0000000000000020ULL,
2048 /* New 64 bits extensions (PowerPC 2.0x) */
2049 PPC_64BX = 0x0000000000000040ULL,
2050 /* 64 bits hypervisor extensions */
2051 PPC_64H = 0x0000000000000080ULL,
2052 /* New wait instruction (PowerPC 2.0x) */
2053 PPC_WAIT = 0x0000000000000100ULL,
2054 /* Time base mftb instruction */
2055 PPC_MFTB = 0x0000000000000200ULL,
2056
2057 /* Fixed-point unit extensions */
2058 /* PowerPC 602 specific */
2059 PPC_602_SPEC = 0x0000000000000400ULL,
2060 /* isel instruction */
2061 PPC_ISEL = 0x0000000000000800ULL,
2062 /* popcntb instruction */
2063 PPC_POPCNTB = 0x0000000000001000ULL,
2064 /* string load / store */
2065 PPC_STRING = 0x0000000000002000ULL,
2066 /* real mode cache inhibited load / store */
2067 PPC_CILDST = 0x0000000000004000ULL,
2068
2069 /* Floating-point unit extensions */
2070 /* Optional floating point instructions */
2071 PPC_FLOAT = 0x0000000000010000ULL,
2072 /* New floating-point extensions (PowerPC 2.0x) */
2073 PPC_FLOAT_EXT = 0x0000000000020000ULL,
2074 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
2075 PPC_FLOAT_FRES = 0x0000000000080000ULL,
2076 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
2077 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
2078 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
2079 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
2080
2081 /* Vector/SIMD extensions */
2082 /* Altivec support */
2083 PPC_ALTIVEC = 0x0000000001000000ULL,
2084 /* PowerPC 2.03 SPE extension */
2085 PPC_SPE = 0x0000000002000000ULL,
2086 /* PowerPC 2.03 SPE single-precision floating-point extension */
2087 PPC_SPE_SINGLE = 0x0000000004000000ULL,
2088 /* PowerPC 2.03 SPE double-precision floating-point extension */
2089 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
2090
2091 /* Optional memory control instructions */
2092 PPC_MEM_TLBIA = 0x0000000010000000ULL,
2093 PPC_MEM_TLBIE = 0x0000000020000000ULL,
2094 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
2095 /* sync instruction */
2096 PPC_MEM_SYNC = 0x0000000080000000ULL,
2097 /* eieio instruction */
2098 PPC_MEM_EIEIO = 0x0000000100000000ULL,
2099
2100 /* Cache control instructions */
2101 PPC_CACHE = 0x0000000200000000ULL,
2102 /* icbi instruction */
2103 PPC_CACHE_ICBI = 0x0000000400000000ULL,
2104 /* dcbz instruction */
2105 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
2106 /* dcba instruction */
2107 PPC_CACHE_DCBA = 0x0000002000000000ULL,
2108 /* Freescale cache locking instructions */
2109 PPC_CACHE_LOCK = 0x0000004000000000ULL,
2110
2111 /* MMU related extensions */
2112 /* external control instructions */
2113 PPC_EXTERN = 0x0000010000000000ULL,
2114 /* segment register access instructions */
2115 PPC_SEGMENT = 0x0000020000000000ULL,
2116 /* PowerPC 6xx TLB management instructions */
2117 PPC_6xx_TLB = 0x0000040000000000ULL,
2118 /* PowerPC 74xx TLB management instructions */
2119 PPC_74xx_TLB = 0x0000080000000000ULL,
2120 /* PowerPC 40x TLB management instructions */
2121 PPC_40x_TLB = 0x0000100000000000ULL,
2122 /* segment register access instructions for PowerPC 64 "bridge" */
2123 PPC_SEGMENT_64B = 0x0000200000000000ULL,
2124 /* SLB management */
2125 PPC_SLBI = 0x0000400000000000ULL,
2126
2127 /* Embedded PowerPC dedicated instructions */
2128 PPC_WRTEE = 0x0001000000000000ULL,
2129 /* PowerPC 40x exception model */
2130 PPC_40x_EXCP = 0x0002000000000000ULL,
2131 /* PowerPC 405 Mac instructions */
2132 PPC_405_MAC = 0x0004000000000000ULL,
2133 /* PowerPC 440 specific instructions */
2134 PPC_440_SPEC = 0x0008000000000000ULL,
2135 /* BookE (embedded) PowerPC specification */
2136 PPC_BOOKE = 0x0010000000000000ULL,
2137 /* mfapidi instruction */
2138 PPC_MFAPIDI = 0x0020000000000000ULL,
2139 /* tlbiva instruction */
2140 PPC_TLBIVA = 0x0040000000000000ULL,
2141 /* tlbivax instruction */
2142 PPC_TLBIVAX = 0x0080000000000000ULL,
2143 /* PowerPC 4xx dedicated instructions */
2144 PPC_4xx_COMMON = 0x0100000000000000ULL,
2145 /* PowerPC 40x ibct instructions */
2146 PPC_40x_ICBT = 0x0200000000000000ULL,
2147 /* rfmci is not implemented in all BookE PowerPC */
2148 PPC_RFMCI = 0x0400000000000000ULL,
2149 /* rfdi instruction */
2150 PPC_RFDI = 0x0800000000000000ULL,
2151 /* DCR accesses */
2152 PPC_DCR = 0x1000000000000000ULL,
2153 /* DCR extended accesse */
2154 PPC_DCRX = 0x2000000000000000ULL,
2155 /* user-mode DCR access, implemented in PowerPC 460 */
2156 PPC_DCRUX = 0x4000000000000000ULL,
2157 /* popcntw and popcntd instructions */
2158 PPC_POPCNTWD = 0x8000000000000000ULL,
2159
2160 #define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
2161 | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
2162 | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
2163 | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
2164 | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
2165 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
2166 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
2167 | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
2168 | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
2169 | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
2170 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
2171 | PPC_MEM_SYNC | PPC_MEM_EIEIO \
2172 | PPC_CACHE | PPC_CACHE_ICBI \
2173 | PPC_CACHE_DCBZ \
2174 | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
2175 | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
2176 | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
2177 | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
2178 | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
2179 | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
2180 | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
2181 | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
2182 | PPC_POPCNTWD | PPC_CILDST)
2183
2184 /* extended type values */
2185
2186 /* BookE 2.06 PowerPC specification */
2187 PPC2_BOOKE206 = 0x0000000000000001ULL,
2188 /* VSX (extensions to Altivec / VMX) */
2189 PPC2_VSX = 0x0000000000000002ULL,
2190 /* Decimal Floating Point (DFP) */
2191 PPC2_DFP = 0x0000000000000004ULL,
2192 /* Embedded.Processor Control */
2193 PPC2_PRCNTL = 0x0000000000000008ULL,
2194 /* Byte-reversed, indexed, double-word load and store */
2195 PPC2_DBRX = 0x0000000000000010ULL,
2196 /* Book I 2.05 PowerPC specification */
2197 PPC2_ISA205 = 0x0000000000000020ULL,
2198 /* VSX additions in ISA 2.07 */
2199 PPC2_VSX207 = 0x0000000000000040ULL,
2200 /* ISA 2.06B bpermd */
2201 PPC2_PERM_ISA206 = 0x0000000000000080ULL,
2202 /* ISA 2.06B divide extended variants */
2203 PPC2_DIVE_ISA206 = 0x0000000000000100ULL,
2204 /* ISA 2.06B larx/stcx. instructions */
2205 PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
2206 /* ISA 2.06B floating point integer conversion */
2207 PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
2208 /* ISA 2.06B floating point test instructions */
2209 PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
2210 /* ISA 2.07 bctar instruction */
2211 PPC2_BCTAR_ISA207 = 0x0000000000001000ULL,
2212 /* ISA 2.07 load/store quadword */
2213 PPC2_LSQ_ISA207 = 0x0000000000002000ULL,
2214 /* ISA 2.07 Altivec */
2215 PPC2_ALTIVEC_207 = 0x0000000000004000ULL,
2216 /* PowerISA 2.07 Book3s specification */
2217 PPC2_ISA207S = 0x0000000000008000ULL,
2218 /* Double precision floating point conversion for signed integer 64 */
2219 PPC2_FP_CVT_S64 = 0x0000000000010000ULL,
2220 /* Transactional Memory (ISA 2.07, Book II) */
2221 PPC2_TM = 0x0000000000020000ULL,
2222 /* Server PM instructgions (ISA 2.06, Book III) */
2223 PPC2_PM_ISA206 = 0x0000000000040000ULL,
2224 /* POWER ISA 3.0 */
2225 PPC2_ISA300 = 0x0000000000080000ULL,
2226
2227 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
2228 PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
2229 PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
2230 PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
2231 PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
2232 PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
2233 PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
2234 PPC2_ISA300)
2235 };
2236
2237 /*****************************************************************************/
2238 /* Memory access type :
2239 * may be needed for precise access rights control and precise exceptions.
2240 */
2241 enum {
2242 /* 1 bit to define user level / supervisor access */
2243 ACCESS_USER = 0x00,
2244 ACCESS_SUPER = 0x01,
2245 /* Type of instruction that generated the access */
2246 ACCESS_CODE = 0x10, /* Code fetch access */
2247 ACCESS_INT = 0x20, /* Integer load/store access */
2248 ACCESS_FLOAT = 0x30, /* floating point load/store access */
2249 ACCESS_RES = 0x40, /* load/store with reservation */
2250 ACCESS_EXT = 0x50, /* external access */
2251 ACCESS_CACHE = 0x60, /* Cache manipulation */
2252 };
2253
2254 /* Hardware interruption sources:
2255 * all those exception can be raised simulteaneously
2256 */
2257 /* Input pins definitions */
2258 enum {
2259 /* 6xx bus input pins */
2260 PPC6xx_INPUT_HRESET = 0,
2261 PPC6xx_INPUT_SRESET = 1,
2262 PPC6xx_INPUT_CKSTP_IN = 2,
2263 PPC6xx_INPUT_MCP = 3,
2264 PPC6xx_INPUT_SMI = 4,
2265 PPC6xx_INPUT_INT = 5,
2266 PPC6xx_INPUT_TBEN = 6,
2267 PPC6xx_INPUT_WAKEUP = 7,
2268 PPC6xx_INPUT_NB,
2269 };
2270
2271 enum {
2272 /* Embedded PowerPC input pins */
2273 PPCBookE_INPUT_HRESET = 0,
2274 PPCBookE_INPUT_SRESET = 1,
2275 PPCBookE_INPUT_CKSTP_IN = 2,
2276 PPCBookE_INPUT_MCP = 3,
2277 PPCBookE_INPUT_SMI = 4,
2278 PPCBookE_INPUT_INT = 5,
2279 PPCBookE_INPUT_CINT = 6,
2280 PPCBookE_INPUT_NB,
2281 };
2282
2283 enum {
2284 /* PowerPC E500 input pins */
2285 PPCE500_INPUT_RESET_CORE = 0,
2286 PPCE500_INPUT_MCK = 1,
2287 PPCE500_INPUT_CINT = 3,
2288 PPCE500_INPUT_INT = 4,
2289 PPCE500_INPUT_DEBUG = 6,
2290 PPCE500_INPUT_NB,
2291 };
2292
2293 enum {
2294 /* PowerPC 40x input pins */
2295 PPC40x_INPUT_RESET_CORE = 0,
2296 PPC40x_INPUT_RESET_CHIP = 1,
2297 PPC40x_INPUT_RESET_SYS = 2,
2298 PPC40x_INPUT_CINT = 3,
2299 PPC40x_INPUT_INT = 4,
2300 PPC40x_INPUT_HALT = 5,
2301 PPC40x_INPUT_DEBUG = 6,
2302 PPC40x_INPUT_NB,
2303 };
2304
2305 enum {
2306 /* RCPU input pins */
2307 PPCRCPU_INPUT_PORESET = 0,
2308 PPCRCPU_INPUT_HRESET = 1,
2309 PPCRCPU_INPUT_SRESET = 2,
2310 PPCRCPU_INPUT_IRQ0 = 3,
2311 PPCRCPU_INPUT_IRQ1 = 4,
2312 PPCRCPU_INPUT_IRQ2 = 5,
2313 PPCRCPU_INPUT_IRQ3 = 6,
2314 PPCRCPU_INPUT_IRQ4 = 7,
2315 PPCRCPU_INPUT_IRQ5 = 8,
2316 PPCRCPU_INPUT_IRQ6 = 9,
2317 PPCRCPU_INPUT_IRQ7 = 10,
2318 PPCRCPU_INPUT_NB,
2319 };
2320
2321 #if defined(TARGET_PPC64)
2322 enum {
2323 /* PowerPC 970 input pins */
2324 PPC970_INPUT_HRESET = 0,
2325 PPC970_INPUT_SRESET = 1,
2326 PPC970_INPUT_CKSTP = 2,
2327 PPC970_INPUT_TBEN = 3,
2328 PPC970_INPUT_MCP = 4,
2329 PPC970_INPUT_INT = 5,
2330 PPC970_INPUT_THINT = 6,
2331 PPC970_INPUT_NB,
2332 };
2333
2334 enum {
2335 /* POWER7 input pins */
2336 POWER7_INPUT_INT = 0,
2337 /* POWER7 probably has other inputs, but we don't care about them
2338 * for any existing machine. We can wire these up when we need
2339 * them */
2340 POWER7_INPUT_NB,
2341 };
2342 #endif
2343
2344 /* Hardware exceptions definitions */
2345 enum {
2346 /* External hardware exception sources */
2347 PPC_INTERRUPT_RESET = 0, /* Reset exception */
2348 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
2349 PPC_INTERRUPT_MCK, /* Machine check exception */
2350 PPC_INTERRUPT_EXT, /* External interrupt */
2351 PPC_INTERRUPT_SMI, /* System management interrupt */
2352 PPC_INTERRUPT_CEXT, /* Critical external interrupt */
2353 PPC_INTERRUPT_DEBUG, /* External debug exception */
2354 PPC_INTERRUPT_THERM, /* Thermal exception */
2355 /* Internal hardware exception sources */
2356 PPC_INTERRUPT_DECR, /* Decrementer exception */
2357 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
2358 PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
2359 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
2360 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
2361 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
2362 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
2363 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
2364 PPC_INTERRUPT_HMI, /* Hypervisor Maintainance interrupt */
2365 PPC_INTERRUPT_HDOORBELL, /* Hypervisor Doorbell interrupt */
2366 };
2367
2368 /* Processor Compatibility mask (PCR) */
2369 enum {
2370 PCR_COMPAT_2_05 = PPC_BIT(62),
2371 PCR_COMPAT_2_06 = PPC_BIT(61),
2372 PCR_COMPAT_2_07 = PPC_BIT(60),
2373 PCR_COMPAT_3_00 = PPC_BIT(59),
2374 PCR_VEC_DIS = PPC_BIT(0), /* Vec. disable (bit NA since POWER8) */
2375 PCR_VSX_DIS = PPC_BIT(1), /* VSX disable (bit NA since POWER8) */
2376 PCR_TM_DIS = PPC_BIT(2), /* Trans. memory disable (POWER8) */
2377 };
2378
2379 /* HMER/HMEER */
2380 enum {
2381 HMER_MALFUNCTION_ALERT = PPC_BIT(0),
2382 HMER_PROC_RECV_DONE = PPC_BIT(2),
2383 HMER_PROC_RECV_ERROR_MASKED = PPC_BIT(3),
2384 HMER_TFAC_ERROR = PPC_BIT(4),
2385 HMER_TFMR_PARITY_ERROR = PPC_BIT(5),
2386 HMER_XSCOM_FAIL = PPC_BIT(8),
2387 HMER_XSCOM_DONE = PPC_BIT(9),
2388 HMER_PROC_RECV_AGAIN = PPC_BIT(11),
2389 HMER_WARN_RISE = PPC_BIT(14),
2390 HMER_WARN_FALL = PPC_BIT(15),
2391 HMER_SCOM_FIR_HMI = PPC_BIT(16),
2392 HMER_TRIG_FIR_HMI = PPC_BIT(17),
2393 HMER_HYP_RESOURCE_ERR = PPC_BIT(20),
2394 HMER_XSCOM_STATUS_MASK = PPC_BITMASK(21, 23),
2395 };
2396
2397 /* Alternate Interrupt Location (AIL) */
2398 enum {
2399 AIL_NONE = 0,
2400 AIL_RESERVED = 1,
2401 AIL_0001_8000 = 2,
2402 AIL_C000_0000_0000_4000 = 3,
2403 };
2404
2405 /*****************************************************************************/
2406
2407 #define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300))
2408 target_ulong cpu_read_xer(CPUPPCState *env);
2409 void cpu_write_xer(CPUPPCState *env, target_ulong xer);
2410
2411 static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2412 target_ulong *cs_base, uint32_t *flags)
2413 {
2414 *pc = env->nip;
2415 *cs_base = 0;
2416 *flags = env->hflags;
2417 }
2418
2419 void QEMU_NORETURN raise_exception(CPUPPCState *env, uint32_t exception);
2420 void QEMU_NORETURN raise_exception_ra(CPUPPCState *env, uint32_t exception,
2421 uintptr_t raddr);
2422 void QEMU_NORETURN raise_exception_err(CPUPPCState *env, uint32_t exception,
2423 uint32_t error_code);
2424 void QEMU_NORETURN raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
2425 uint32_t error_code, uintptr_t raddr);
2426
2427 #if !defined(CONFIG_USER_ONLY)
2428 static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2429 {
2430 uintptr_t tlbml = (uintptr_t)tlbm;
2431 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2432
2433 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2434 }
2435
2436 static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2437 {
2438 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2439 int r = tlbncfg & TLBnCFG_N_ENTRY;
2440 return r;
2441 }
2442
2443 static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2444 {
2445 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2446 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2447 return r;
2448 }
2449
2450 static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2451 {
2452 int id = booke206_tlbm_id(env, tlbm);
2453 int end = 0;
2454 int i;
2455
2456 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2457 end += booke206_tlb_size(env, i);
2458 if (id < end) {
2459 return i;
2460 }
2461 }
2462
2463 cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id);
2464 return 0;
2465 }
2466
2467 static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2468 {
2469 int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2470 int tlbid = booke206_tlbm_id(env, tlb);
2471 return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2472 }
2473
2474 static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2475 target_ulong ea, int way)
2476 {
2477 int r;
2478 uint32_t ways = booke206_tlb_ways(env, tlbn);
2479 int ways_bits = ctz32(ways);
2480 int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
2481 int i;
2482
2483 way &= ways - 1;
2484 ea >>= MAS2_EPN_SHIFT;
2485 ea &= (1 << (tlb_bits - ways_bits)) - 1;
2486 r = (ea << ways_bits) | way;
2487
2488 if (r >= booke206_tlb_size(env, tlbn)) {
2489 return NULL;
2490 }
2491
2492 /* bump up to tlbn index */
2493 for (i = 0; i < tlbn; i++) {
2494 r += booke206_tlb_size(env, i);
2495 }
2496
2497 return &env->tlb.tlbm[r];
2498 }
2499
2500 /* returns bitmap of supported page sizes for a given TLB */
2501 static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2502 {
2503 uint32_t ret = 0;
2504
2505 if ((env->spr[SPR_MMUCFG] & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
2506 /* MAV2 */
2507 ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2508 } else {
2509 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2510 uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2511 uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2512 int i;
2513 for (i = min; i <= max; i++) {
2514 ret |= (1 << (i << 1));
2515 }
2516 }
2517
2518 return ret;
2519 }
2520
2521 static inline void booke206_fixed_size_tlbn(CPUPPCState *env, const int tlbn,
2522 ppcmas_tlb_t *tlb)
2523 {
2524 uint8_t i;
2525 int32_t tsize = -1;
2526
2527 for (i = 0; i < 32; i++) {
2528 if ((env->spr[SPR_BOOKE_TLB0PS + tlbn]) & (1ULL << i)) {
2529 if (tsize == -1) {
2530 tsize = i;
2531 } else {
2532 return;
2533 }
2534 }
2535 }
2536
2537 /* TLBnPS unimplemented? Odd.. */
2538 assert(tsize != -1);
2539 tlb->mas1 &= ~MAS1_TSIZE_MASK;
2540 tlb->mas1 |= ((uint32_t)tsize) << MAS1_TSIZE_SHIFT;
2541 }
2542
2543 #endif
2544
2545 static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2546 {
2547 if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2548 return msr & (1ULL << MSR_CM);
2549 }
2550
2551 return msr & (1ULL << MSR_SF);
2552 }
2553
2554 /**
2555 * Check whether register rx is in the range between start and
2556 * start + nregs (as needed by the LSWX and LSWI instructions)
2557 */
2558 static inline bool lsw_reg_in_range(int start, int nregs, int rx)
2559 {
2560 return (start + nregs <= 32 && rx >= start && rx < start + nregs) ||
2561 (start + nregs > 32 && (rx >= start || rx < start + nregs - 32));
2562 }
2563
2564 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
2565
2566 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
2567 #endif /* PPC_CPU_H */
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