2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Andrzej Zaborowski
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "tcg-be-ldst.h"
28 int arm_arch
= __ARM_ARCH
;
30 #ifndef use_idiv_instructions
31 bool use_idiv_instructions
;
34 /* ??? Ought to think about changing CONFIG_SOFTMMU to always defined. */
36 # define USING_SOFTMMU 1
38 # define USING_SOFTMMU 0
41 #ifdef CONFIG_DEBUG_TCG
42 static const char * const tcg_target_reg_names
[TCG_TARGET_NB_REGS
] = {
62 static const int tcg_target_reg_alloc_order
[] = {
80 static const int tcg_target_call_iarg_regs
[4] = {
81 TCG_REG_R0
, TCG_REG_R1
, TCG_REG_R2
, TCG_REG_R3
83 static const int tcg_target_call_oarg_regs
[2] = {
84 TCG_REG_R0
, TCG_REG_R1
87 #define TCG_REG_TMP TCG_REG_R12
89 static inline void reloc_pc24(tcg_insn_unit
*code_ptr
, tcg_insn_unit
*target
)
91 ptrdiff_t offset
= (tcg_ptr_byte_diff(target
, code_ptr
) - 8) >> 2;
92 *code_ptr
= (*code_ptr
& ~0xffffff) | (offset
& 0xffffff);
95 static inline void reloc_pc24_atomic(tcg_insn_unit
*code_ptr
, tcg_insn_unit
*target
)
97 ptrdiff_t offset
= (tcg_ptr_byte_diff(target
, code_ptr
) - 8) >> 2;
98 tcg_insn_unit insn
= atomic_read(code_ptr
);
99 tcg_debug_assert(offset
== sextract32(offset
, 0, 24));
100 atomic_set(code_ptr
, deposit32(insn
, 0, 24, offset
));
103 static void patch_reloc(tcg_insn_unit
*code_ptr
, int type
,
104 intptr_t value
, intptr_t addend
)
106 tcg_debug_assert(type
== R_ARM_PC24
);
107 tcg_debug_assert(addend
== 0);
108 reloc_pc24(code_ptr
, (tcg_insn_unit
*)value
);
111 #define TCG_CT_CONST_ARM 0x100
112 #define TCG_CT_CONST_INV 0x200
113 #define TCG_CT_CONST_NEG 0x400
114 #define TCG_CT_CONST_ZERO 0x800
116 /* parse target specific constraints */
117 static const char *target_parse_constraint(TCGArgConstraint
*ct
,
118 const char *ct_str
, TCGType type
)
122 ct
->ct
|= TCG_CT_CONST_ARM
;
125 ct
->ct
|= TCG_CT_CONST_INV
;
127 case 'N': /* The gcc constraint letter is L, already used here. */
128 ct
->ct
|= TCG_CT_CONST_NEG
;
131 ct
->ct
|= TCG_CT_CONST_ZERO
;
135 ct
->ct
|= TCG_CT_REG
;
136 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
139 /* qemu_ld address */
141 ct
->ct
|= TCG_CT_REG
;
142 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
143 #ifdef CONFIG_SOFTMMU
144 /* r0-r2,lr will be overwritten when reading the tlb entry,
145 so don't use these. */
146 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R0
);
147 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R1
);
148 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R2
);
149 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R14
);
153 /* qemu_st address & data */
155 ct
->ct
|= TCG_CT_REG
;
156 tcg_regset_set32(ct
->u
.regs
, 0, (1 << TCG_TARGET_NB_REGS
) - 1);
157 /* r0-r2 will be overwritten when reading the tlb entry (softmmu only)
158 and r0-r1 doing the byte swapping, so don't use these. */
159 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R0
);
160 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R1
);
161 #if defined(CONFIG_SOFTMMU)
162 /* Avoid clashes with registers being used for helper args */
163 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R2
);
164 #if TARGET_LONG_BITS == 64
165 /* Avoid clashes with registers being used for helper args */
166 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R3
);
168 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_R14
);
178 static inline uint32_t rotl(uint32_t val
, int n
)
180 return (val
<< n
) | (val
>> (32 - n
));
183 /* ARM immediates for ALU instructions are made of an unsigned 8-bit
184 right-rotated by an even amount between 0 and 30. */
185 static inline int encode_imm(uint32_t imm
)
189 /* simple case, only lower bits */
190 if ((imm
& ~0xff) == 0)
192 /* then try a simple even shift */
193 shift
= ctz32(imm
) & ~1;
194 if (((imm
>> shift
) & ~0xff) == 0)
196 /* now try harder with rotations */
197 if ((rotl(imm
, 2) & ~0xff) == 0)
199 if ((rotl(imm
, 4) & ~0xff) == 0)
201 if ((rotl(imm
, 6) & ~0xff) == 0)
203 /* imm can't be encoded */
207 static inline int check_fit_imm(uint32_t imm
)
209 return encode_imm(imm
) >= 0;
212 /* Test if a constant matches the constraint.
213 * TODO: define constraints for:
215 * ldr/str offset: between -0xfff and 0xfff
216 * ldrh/strh offset: between -0xff and 0xff
217 * mov operand2: values represented with x << (2 * y), x < 0x100
218 * add, sub, eor...: ditto
220 static inline int tcg_target_const_match(tcg_target_long val
, TCGType type
,
221 const TCGArgConstraint
*arg_ct
)
225 if (ct
& TCG_CT_CONST
) {
227 } else if ((ct
& TCG_CT_CONST_ARM
) && check_fit_imm(val
)) {
229 } else if ((ct
& TCG_CT_CONST_INV
) && check_fit_imm(~val
)) {
231 } else if ((ct
& TCG_CT_CONST_NEG
) && check_fit_imm(-val
)) {
233 } else if ((ct
& TCG_CT_CONST_ZERO
) && val
== 0) {
240 #define TO_CPSR (1 << 20)
243 ARITH_AND
= 0x0 << 21,
244 ARITH_EOR
= 0x1 << 21,
245 ARITH_SUB
= 0x2 << 21,
246 ARITH_RSB
= 0x3 << 21,
247 ARITH_ADD
= 0x4 << 21,
248 ARITH_ADC
= 0x5 << 21,
249 ARITH_SBC
= 0x6 << 21,
250 ARITH_RSC
= 0x7 << 21,
251 ARITH_TST
= 0x8 << 21 | TO_CPSR
,
252 ARITH_CMP
= 0xa << 21 | TO_CPSR
,
253 ARITH_CMN
= 0xb << 21 | TO_CPSR
,
254 ARITH_ORR
= 0xc << 21,
255 ARITH_MOV
= 0xd << 21,
256 ARITH_BIC
= 0xe << 21,
257 ARITH_MVN
= 0xf << 21,
259 INSN_LDR_IMM
= 0x04100000,
260 INSN_LDR_REG
= 0x06100000,
261 INSN_STR_IMM
= 0x04000000,
262 INSN_STR_REG
= 0x06000000,
264 INSN_LDRH_IMM
= 0x005000b0,
265 INSN_LDRH_REG
= 0x001000b0,
266 INSN_LDRSH_IMM
= 0x005000f0,
267 INSN_LDRSH_REG
= 0x001000f0,
268 INSN_STRH_IMM
= 0x004000b0,
269 INSN_STRH_REG
= 0x000000b0,
271 INSN_LDRB_IMM
= 0x04500000,
272 INSN_LDRB_REG
= 0x06500000,
273 INSN_LDRSB_IMM
= 0x005000d0,
274 INSN_LDRSB_REG
= 0x001000d0,
275 INSN_STRB_IMM
= 0x04400000,
276 INSN_STRB_REG
= 0x06400000,
278 INSN_LDRD_IMM
= 0x004000d0,
279 INSN_LDRD_REG
= 0x000000d0,
280 INSN_STRD_IMM
= 0x004000f0,
281 INSN_STRD_REG
= 0x000000f0,
283 INSN_DMB_ISH
= 0x5bf07ff5,
284 INSN_DMB_MCR
= 0xba0f07ee,
288 #define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00)
289 #define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20)
290 #define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40)
291 #define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60)
292 #define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10)
293 #define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30)
294 #define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50)
295 #define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70)
297 enum arm_cond_code_e
{
300 COND_CS
= 0x2, /* Unsigned greater or equal */
301 COND_CC
= 0x3, /* Unsigned less than */
302 COND_MI
= 0x4, /* Negative */
303 COND_PL
= 0x5, /* Zero or greater */
304 COND_VS
= 0x6, /* Overflow */
305 COND_VC
= 0x7, /* No overflow */
306 COND_HI
= 0x8, /* Unsigned greater than */
307 COND_LS
= 0x9, /* Unsigned less or equal */
315 static const uint8_t tcg_cond_to_arm_cond
[] = {
316 [TCG_COND_EQ
] = COND_EQ
,
317 [TCG_COND_NE
] = COND_NE
,
318 [TCG_COND_LT
] = COND_LT
,
319 [TCG_COND_GE
] = COND_GE
,
320 [TCG_COND_LE
] = COND_LE
,
321 [TCG_COND_GT
] = COND_GT
,
323 [TCG_COND_LTU
] = COND_CC
,
324 [TCG_COND_GEU
] = COND_CS
,
325 [TCG_COND_LEU
] = COND_LS
,
326 [TCG_COND_GTU
] = COND_HI
,
329 static inline void tcg_out_bx(TCGContext
*s
, int cond
, int rn
)
331 tcg_out32(s
, (cond
<< 28) | 0x012fff10 | rn
);
334 static inline void tcg_out_b(TCGContext
*s
, int cond
, int32_t offset
)
336 tcg_out32(s
, (cond
<< 28) | 0x0a000000 |
337 (((offset
- 8) >> 2) & 0x00ffffff));
340 static inline void tcg_out_b_noaddr(TCGContext
*s
, int cond
)
342 /* We pay attention here to not modify the branch target by masking
343 the corresponding bytes. This ensure that caches and memory are
344 kept coherent during retranslation. */
345 tcg_out32(s
, deposit32(*s
->code_ptr
, 24, 8, (cond
<< 4) | 0x0a));
348 static inline void tcg_out_bl_noaddr(TCGContext
*s
, int cond
)
350 /* We pay attention here to not modify the branch target by masking
351 the corresponding bytes. This ensure that caches and memory are
352 kept coherent during retranslation. */
353 tcg_out32(s
, deposit32(*s
->code_ptr
, 24, 8, (cond
<< 4) | 0x0b));
356 static inline void tcg_out_bl(TCGContext
*s
, int cond
, int32_t offset
)
358 tcg_out32(s
, (cond
<< 28) | 0x0b000000 |
359 (((offset
- 8) >> 2) & 0x00ffffff));
362 static inline void tcg_out_blx(TCGContext
*s
, int cond
, int rn
)
364 tcg_out32(s
, (cond
<< 28) | 0x012fff30 | rn
);
367 static inline void tcg_out_blx_imm(TCGContext
*s
, int32_t offset
)
369 tcg_out32(s
, 0xfa000000 | ((offset
& 2) << 23) |
370 (((offset
- 8) >> 2) & 0x00ffffff));
373 static inline void tcg_out_dat_reg(TCGContext
*s
,
374 int cond
, int opc
, int rd
, int rn
, int rm
, int shift
)
376 tcg_out32(s
, (cond
<< 28) | (0 << 25) | opc
|
377 (rn
<< 16) | (rd
<< 12) | shift
| rm
);
380 static inline void tcg_out_nop(TCGContext
*s
)
382 if (use_armv7_instructions
) {
383 /* Architected nop introduced in v6k. */
384 /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this
385 also Just So Happened to do nothing on pre-v6k so that we
386 don't need to conditionalize it? */
387 tcg_out32(s
, 0xe320f000);
389 /* Prior to that the assembler uses mov r0, r0. */
390 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, 0, 0, 0, SHIFT_IMM_LSL(0));
394 static inline void tcg_out_mov_reg(TCGContext
*s
, int cond
, int rd
, int rm
)
396 /* Simple reg-reg move, optimising out the 'do nothing' case */
398 tcg_out_dat_reg(s
, cond
, ARITH_MOV
, rd
, 0, rm
, SHIFT_IMM_LSL(0));
402 static inline void tcg_out_dat_imm(TCGContext
*s
,
403 int cond
, int opc
, int rd
, int rn
, int im
)
405 tcg_out32(s
, (cond
<< 28) | (1 << 25) | opc
|
406 (rn
<< 16) | (rd
<< 12) | im
);
409 static void tcg_out_movi32(TCGContext
*s
, int cond
, int rd
, uint32_t arg
)
413 /* For armv7, make sure not to use movw+movt when mov/mvn would do.
414 Speed things up by only checking when movt would be required.
415 Prior to armv7, have one go at fully rotated immediates before
416 doing the decomposition thing below. */
417 if (!use_armv7_instructions
|| (arg
& 0xffff0000)) {
418 rot
= encode_imm(arg
);
420 tcg_out_dat_imm(s
, cond
, ARITH_MOV
, rd
, 0,
421 rotl(arg
, rot
) | (rot
<< 7));
424 rot
= encode_imm(~arg
);
426 tcg_out_dat_imm(s
, cond
, ARITH_MVN
, rd
, 0,
427 rotl(~arg
, rot
) | (rot
<< 7));
432 /* Use movw + movt. */
433 if (use_armv7_instructions
) {
435 tcg_out32(s
, (cond
<< 28) | 0x03000000 | (rd
<< 12)
436 | ((arg
<< 4) & 0x000f0000) | (arg
& 0xfff));
437 if (arg
& 0xffff0000) {
439 tcg_out32(s
, (cond
<< 28) | 0x03400000 | (rd
<< 12)
440 | ((arg
>> 12) & 0x000f0000) | ((arg
>> 16) & 0xfff));
445 /* TODO: This is very suboptimal, we can easily have a constant
446 pool somewhere after all the instructions. */
449 /* If we have lots of leading 1's, we can shorten the sequence by
450 beginning with mvn and then clearing higher bits with eor. */
451 if (clz32(~arg
) > clz32(arg
)) {
452 opc
= ARITH_MVN
, arg
= ~arg
;
455 int i
= ctz32(arg
) & ~1;
456 rot
= ((32 - i
) << 7) & 0xf00;
457 tcg_out_dat_imm(s
, cond
, opc
, rd
, rn
, ((arg
>> i
) & 0xff) | rot
);
465 static inline void tcg_out_dat_rI(TCGContext
*s
, int cond
, int opc
, TCGArg dst
,
466 TCGArg lhs
, TCGArg rhs
, int rhs_is_const
)
468 /* Emit either the reg,imm or reg,reg form of a data-processing insn.
469 * rhs must satisfy the "rI" constraint.
472 int rot
= encode_imm(rhs
);
473 tcg_debug_assert(rot
>= 0);
474 tcg_out_dat_imm(s
, cond
, opc
, dst
, lhs
, rotl(rhs
, rot
) | (rot
<< 7));
476 tcg_out_dat_reg(s
, cond
, opc
, dst
, lhs
, rhs
, SHIFT_IMM_LSL(0));
480 static void tcg_out_dat_rIK(TCGContext
*s
, int cond
, int opc
, int opinv
,
481 TCGReg dst
, TCGReg lhs
, TCGArg rhs
,
484 /* Emit either the reg,imm or reg,reg form of a data-processing insn.
485 * rhs must satisfy the "rIK" constraint.
488 int rot
= encode_imm(rhs
);
491 rot
= encode_imm(rhs
);
492 tcg_debug_assert(rot
>= 0);
495 tcg_out_dat_imm(s
, cond
, opc
, dst
, lhs
, rotl(rhs
, rot
) | (rot
<< 7));
497 tcg_out_dat_reg(s
, cond
, opc
, dst
, lhs
, rhs
, SHIFT_IMM_LSL(0));
501 static void tcg_out_dat_rIN(TCGContext
*s
, int cond
, int opc
, int opneg
,
502 TCGArg dst
, TCGArg lhs
, TCGArg rhs
,
505 /* Emit either the reg,imm or reg,reg form of a data-processing insn.
506 * rhs must satisfy the "rIN" constraint.
509 int rot
= encode_imm(rhs
);
512 rot
= encode_imm(rhs
);
513 tcg_debug_assert(rot
>= 0);
516 tcg_out_dat_imm(s
, cond
, opc
, dst
, lhs
, rotl(rhs
, rot
) | (rot
<< 7));
518 tcg_out_dat_reg(s
, cond
, opc
, dst
, lhs
, rhs
, SHIFT_IMM_LSL(0));
522 static inline void tcg_out_mul32(TCGContext
*s
, int cond
, TCGReg rd
,
523 TCGReg rn
, TCGReg rm
)
525 /* if ArchVersion() < 6 && d == n then UNPREDICTABLE; */
526 if (!use_armv6_instructions
&& rd
== rn
) {
528 /* rd == rn == rm; copy an input to tmp first. */
529 tcg_out_mov_reg(s
, cond
, TCG_REG_TMP
, rn
);
530 rm
= rn
= TCG_REG_TMP
;
537 tcg_out32(s
, (cond
<< 28) | 0x90 | (rd
<< 16) | (rm
<< 8) | rn
);
540 static inline void tcg_out_umull32(TCGContext
*s
, int cond
, TCGReg rd0
,
541 TCGReg rd1
, TCGReg rn
, TCGReg rm
)
543 /* if ArchVersion() < 6 && (dHi == n || dLo == n) then UNPREDICTABLE; */
544 if (!use_armv6_instructions
&& (rd0
== rn
|| rd1
== rn
)) {
545 if (rd0
== rm
|| rd1
== rm
) {
546 tcg_out_mov_reg(s
, cond
, TCG_REG_TMP
, rn
);
555 tcg_out32(s
, (cond
<< 28) | 0x00800090 |
556 (rd1
<< 16) | (rd0
<< 12) | (rm
<< 8) | rn
);
559 static inline void tcg_out_smull32(TCGContext
*s
, int cond
, TCGReg rd0
,
560 TCGReg rd1
, TCGReg rn
, TCGReg rm
)
562 /* if ArchVersion() < 6 && (dHi == n || dLo == n) then UNPREDICTABLE; */
563 if (!use_armv6_instructions
&& (rd0
== rn
|| rd1
== rn
)) {
564 if (rd0
== rm
|| rd1
== rm
) {
565 tcg_out_mov_reg(s
, cond
, TCG_REG_TMP
, rn
);
574 tcg_out32(s
, (cond
<< 28) | 0x00c00090 |
575 (rd1
<< 16) | (rd0
<< 12) | (rm
<< 8) | rn
);
578 static inline void tcg_out_sdiv(TCGContext
*s
, int cond
, int rd
, int rn
, int rm
)
580 tcg_out32(s
, 0x0710f010 | (cond
<< 28) | (rd
<< 16) | rn
| (rm
<< 8));
583 static inline void tcg_out_udiv(TCGContext
*s
, int cond
, int rd
, int rn
, int rm
)
585 tcg_out32(s
, 0x0730f010 | (cond
<< 28) | (rd
<< 16) | rn
| (rm
<< 8));
588 static inline void tcg_out_ext8s(TCGContext
*s
, int cond
,
591 if (use_armv6_instructions
) {
593 tcg_out32(s
, 0x06af0070 | (cond
<< 28) | (rd
<< 12) | rn
);
595 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
596 rd
, 0, rn
, SHIFT_IMM_LSL(24));
597 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
598 rd
, 0, rd
, SHIFT_IMM_ASR(24));
602 static inline void tcg_out_ext8u(TCGContext
*s
, int cond
,
605 tcg_out_dat_imm(s
, cond
, ARITH_AND
, rd
, rn
, 0xff);
608 static inline void tcg_out_ext16s(TCGContext
*s
, int cond
,
611 if (use_armv6_instructions
) {
613 tcg_out32(s
, 0x06bf0070 | (cond
<< 28) | (rd
<< 12) | rn
);
615 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
616 rd
, 0, rn
, SHIFT_IMM_LSL(16));
617 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
618 rd
, 0, rd
, SHIFT_IMM_ASR(16));
622 static inline void tcg_out_ext16u(TCGContext
*s
, int cond
,
625 if (use_armv6_instructions
) {
627 tcg_out32(s
, 0x06ff0070 | (cond
<< 28) | (rd
<< 12) | rn
);
629 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
630 rd
, 0, rn
, SHIFT_IMM_LSL(16));
631 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
632 rd
, 0, rd
, SHIFT_IMM_LSR(16));
636 static inline void tcg_out_bswap16s(TCGContext
*s
, int cond
, int rd
, int rn
)
638 if (use_armv6_instructions
) {
640 tcg_out32(s
, 0x06ff0fb0 | (cond
<< 28) | (rd
<< 12) | rn
);
642 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
643 TCG_REG_TMP
, 0, rn
, SHIFT_IMM_LSL(24));
644 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
645 TCG_REG_TMP
, 0, TCG_REG_TMP
, SHIFT_IMM_ASR(16));
646 tcg_out_dat_reg(s
, cond
, ARITH_ORR
,
647 rd
, TCG_REG_TMP
, rn
, SHIFT_IMM_LSR(8));
651 static inline void tcg_out_bswap16(TCGContext
*s
, int cond
, int rd
, int rn
)
653 if (use_armv6_instructions
) {
655 tcg_out32(s
, 0x06bf0fb0 | (cond
<< 28) | (rd
<< 12) | rn
);
657 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
658 TCG_REG_TMP
, 0, rn
, SHIFT_IMM_LSL(24));
659 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
660 TCG_REG_TMP
, 0, TCG_REG_TMP
, SHIFT_IMM_LSR(16));
661 tcg_out_dat_reg(s
, cond
, ARITH_ORR
,
662 rd
, TCG_REG_TMP
, rn
, SHIFT_IMM_LSR(8));
666 /* swap the two low bytes assuming that the two high input bytes and the
667 two high output bit can hold any value. */
668 static inline void tcg_out_bswap16st(TCGContext
*s
, int cond
, int rd
, int rn
)
670 if (use_armv6_instructions
) {
672 tcg_out32(s
, 0x06bf0fb0 | (cond
<< 28) | (rd
<< 12) | rn
);
674 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
675 TCG_REG_TMP
, 0, rn
, SHIFT_IMM_LSR(8));
676 tcg_out_dat_imm(s
, cond
, ARITH_AND
, TCG_REG_TMP
, TCG_REG_TMP
, 0xff);
677 tcg_out_dat_reg(s
, cond
, ARITH_ORR
,
678 rd
, TCG_REG_TMP
, rn
, SHIFT_IMM_LSL(8));
682 static inline void tcg_out_bswap32(TCGContext
*s
, int cond
, int rd
, int rn
)
684 if (use_armv6_instructions
) {
686 tcg_out32(s
, 0x06bf0f30 | (cond
<< 28) | (rd
<< 12) | rn
);
688 tcg_out_dat_reg(s
, cond
, ARITH_EOR
,
689 TCG_REG_TMP
, rn
, rn
, SHIFT_IMM_ROR(16));
690 tcg_out_dat_imm(s
, cond
, ARITH_BIC
,
691 TCG_REG_TMP
, TCG_REG_TMP
, 0xff | 0x800);
692 tcg_out_dat_reg(s
, cond
, ARITH_MOV
,
693 rd
, 0, rn
, SHIFT_IMM_ROR(8));
694 tcg_out_dat_reg(s
, cond
, ARITH_EOR
,
695 rd
, rd
, TCG_REG_TMP
, SHIFT_IMM_LSR(8));
699 static inline void tcg_out_deposit(TCGContext
*s
, int cond
, TCGReg rd
,
700 TCGArg a1
, int ofs
, int len
, bool const_a1
)
703 /* bfi becomes bfc with rn == 15. */
707 tcg_out32(s
, 0x07c00010 | (cond
<< 28) | (rd
<< 12) | a1
708 | (ofs
<< 7) | ((ofs
+ len
- 1) << 16));
711 static inline void tcg_out_extract(TCGContext
*s
, int cond
, TCGReg rd
,
712 TCGArg a1
, int ofs
, int len
)
715 tcg_out32(s
, 0x07e00050 | (cond
<< 28) | (rd
<< 12) | a1
716 | (ofs
<< 7) | ((len
- 1) << 16));
719 static inline void tcg_out_sextract(TCGContext
*s
, int cond
, TCGReg rd
,
720 TCGArg a1
, int ofs
, int len
)
723 tcg_out32(s
, 0x07a00050 | (cond
<< 28) | (rd
<< 12) | a1
724 | (ofs
<< 7) | ((len
- 1) << 16));
727 /* Note that this routine is used for both LDR and LDRH formats, so we do
728 not wish to include an immediate shift at this point. */
729 static void tcg_out_memop_r(TCGContext
*s
, int cond
, ARMInsn opc
, TCGReg rt
,
730 TCGReg rn
, TCGReg rm
, bool u
, bool p
, bool w
)
732 tcg_out32(s
, (cond
<< 28) | opc
| (u
<< 23) | (p
<< 24)
733 | (w
<< 21) | (rn
<< 16) | (rt
<< 12) | rm
);
736 static void tcg_out_memop_8(TCGContext
*s
, int cond
, ARMInsn opc
, TCGReg rt
,
737 TCGReg rn
, int imm8
, bool p
, bool w
)
744 tcg_out32(s
, (cond
<< 28) | opc
| (u
<< 23) | (p
<< 24) | (w
<< 21) |
745 (rn
<< 16) | (rt
<< 12) | ((imm8
& 0xf0) << 4) | (imm8
& 0xf));
748 static void tcg_out_memop_12(TCGContext
*s
, int cond
, ARMInsn opc
, TCGReg rt
,
749 TCGReg rn
, int imm12
, bool p
, bool w
)
756 tcg_out32(s
, (cond
<< 28) | opc
| (u
<< 23) | (p
<< 24) | (w
<< 21) |
757 (rn
<< 16) | (rt
<< 12) | imm12
);
760 static inline void tcg_out_ld32_12(TCGContext
*s
, int cond
, TCGReg rt
,
761 TCGReg rn
, int imm12
)
763 tcg_out_memop_12(s
, cond
, INSN_LDR_IMM
, rt
, rn
, imm12
, 1, 0);
766 static inline void tcg_out_st32_12(TCGContext
*s
, int cond
, TCGReg rt
,
767 TCGReg rn
, int imm12
)
769 tcg_out_memop_12(s
, cond
, INSN_STR_IMM
, rt
, rn
, imm12
, 1, 0);
772 static inline void tcg_out_ld32_r(TCGContext
*s
, int cond
, TCGReg rt
,
773 TCGReg rn
, TCGReg rm
)
775 tcg_out_memop_r(s
, cond
, INSN_LDR_REG
, rt
, rn
, rm
, 1, 1, 0);
778 static inline void tcg_out_st32_r(TCGContext
*s
, int cond
, TCGReg rt
,
779 TCGReg rn
, TCGReg rm
)
781 tcg_out_memop_r(s
, cond
, INSN_STR_REG
, rt
, rn
, rm
, 1, 1, 0);
784 static inline void tcg_out_ldrd_8(TCGContext
*s
, int cond
, TCGReg rt
,
787 tcg_out_memop_8(s
, cond
, INSN_LDRD_IMM
, rt
, rn
, imm8
, 1, 0);
790 static inline void tcg_out_ldrd_r(TCGContext
*s
, int cond
, TCGReg rt
,
791 TCGReg rn
, TCGReg rm
)
793 tcg_out_memop_r(s
, cond
, INSN_LDRD_REG
, rt
, rn
, rm
, 1, 1, 0);
796 static inline void tcg_out_strd_8(TCGContext
*s
, int cond
, TCGReg rt
,
799 tcg_out_memop_8(s
, cond
, INSN_STRD_IMM
, rt
, rn
, imm8
, 1, 0);
802 static inline void tcg_out_strd_r(TCGContext
*s
, int cond
, TCGReg rt
,
803 TCGReg rn
, TCGReg rm
)
805 tcg_out_memop_r(s
, cond
, INSN_STRD_REG
, rt
, rn
, rm
, 1, 1, 0);
808 /* Register pre-increment with base writeback. */
809 static inline void tcg_out_ld32_rwb(TCGContext
*s
, int cond
, TCGReg rt
,
810 TCGReg rn
, TCGReg rm
)
812 tcg_out_memop_r(s
, cond
, INSN_LDR_REG
, rt
, rn
, rm
, 1, 1, 1);
815 static inline void tcg_out_st32_rwb(TCGContext
*s
, int cond
, TCGReg rt
,
816 TCGReg rn
, TCGReg rm
)
818 tcg_out_memop_r(s
, cond
, INSN_STR_REG
, rt
, rn
, rm
, 1, 1, 1);
821 static inline void tcg_out_ld16u_8(TCGContext
*s
, int cond
, TCGReg rt
,
824 tcg_out_memop_8(s
, cond
, INSN_LDRH_IMM
, rt
, rn
, imm8
, 1, 0);
827 static inline void tcg_out_st16_8(TCGContext
*s
, int cond
, TCGReg rt
,
830 tcg_out_memop_8(s
, cond
, INSN_STRH_IMM
, rt
, rn
, imm8
, 1, 0);
833 static inline void tcg_out_ld16u_r(TCGContext
*s
, int cond
, TCGReg rt
,
834 TCGReg rn
, TCGReg rm
)
836 tcg_out_memop_r(s
, cond
, INSN_LDRH_REG
, rt
, rn
, rm
, 1, 1, 0);
839 static inline void tcg_out_st16_r(TCGContext
*s
, int cond
, TCGReg rt
,
840 TCGReg rn
, TCGReg rm
)
842 tcg_out_memop_r(s
, cond
, INSN_STRH_REG
, rt
, rn
, rm
, 1, 1, 0);
845 static inline void tcg_out_ld16s_8(TCGContext
*s
, int cond
, TCGReg rt
,
848 tcg_out_memop_8(s
, cond
, INSN_LDRSH_IMM
, rt
, rn
, imm8
, 1, 0);
851 static inline void tcg_out_ld16s_r(TCGContext
*s
, int cond
, TCGReg rt
,
852 TCGReg rn
, TCGReg rm
)
854 tcg_out_memop_r(s
, cond
, INSN_LDRSH_REG
, rt
, rn
, rm
, 1, 1, 0);
857 static inline void tcg_out_ld8_12(TCGContext
*s
, int cond
, TCGReg rt
,
858 TCGReg rn
, int imm12
)
860 tcg_out_memop_12(s
, cond
, INSN_LDRB_IMM
, rt
, rn
, imm12
, 1, 0);
863 static inline void tcg_out_st8_12(TCGContext
*s
, int cond
, TCGReg rt
,
864 TCGReg rn
, int imm12
)
866 tcg_out_memop_12(s
, cond
, INSN_STRB_IMM
, rt
, rn
, imm12
, 1, 0);
869 static inline void tcg_out_ld8_r(TCGContext
*s
, int cond
, TCGReg rt
,
870 TCGReg rn
, TCGReg rm
)
872 tcg_out_memop_r(s
, cond
, INSN_LDRB_REG
, rt
, rn
, rm
, 1, 1, 0);
875 static inline void tcg_out_st8_r(TCGContext
*s
, int cond
, TCGReg rt
,
876 TCGReg rn
, TCGReg rm
)
878 tcg_out_memop_r(s
, cond
, INSN_STRB_REG
, rt
, rn
, rm
, 1, 1, 0);
881 static inline void tcg_out_ld8s_8(TCGContext
*s
, int cond
, TCGReg rt
,
884 tcg_out_memop_8(s
, cond
, INSN_LDRSB_IMM
, rt
, rn
, imm8
, 1, 0);
887 static inline void tcg_out_ld8s_r(TCGContext
*s
, int cond
, TCGReg rt
,
888 TCGReg rn
, TCGReg rm
)
890 tcg_out_memop_r(s
, cond
, INSN_LDRSB_REG
, rt
, rn
, rm
, 1, 1, 0);
893 static inline void tcg_out_ld32u(TCGContext
*s
, int cond
,
894 int rd
, int rn
, int32_t offset
)
896 if (offset
> 0xfff || offset
< -0xfff) {
897 tcg_out_movi32(s
, cond
, TCG_REG_TMP
, offset
);
898 tcg_out_ld32_r(s
, cond
, rd
, rn
, TCG_REG_TMP
);
900 tcg_out_ld32_12(s
, cond
, rd
, rn
, offset
);
903 static inline void tcg_out_st32(TCGContext
*s
, int cond
,
904 int rd
, int rn
, int32_t offset
)
906 if (offset
> 0xfff || offset
< -0xfff) {
907 tcg_out_movi32(s
, cond
, TCG_REG_TMP
, offset
);
908 tcg_out_st32_r(s
, cond
, rd
, rn
, TCG_REG_TMP
);
910 tcg_out_st32_12(s
, cond
, rd
, rn
, offset
);
913 static inline void tcg_out_ld16u(TCGContext
*s
, int cond
,
914 int rd
, int rn
, int32_t offset
)
916 if (offset
> 0xff || offset
< -0xff) {
917 tcg_out_movi32(s
, cond
, TCG_REG_TMP
, offset
);
918 tcg_out_ld16u_r(s
, cond
, rd
, rn
, TCG_REG_TMP
);
920 tcg_out_ld16u_8(s
, cond
, rd
, rn
, offset
);
923 static inline void tcg_out_ld16s(TCGContext
*s
, int cond
,
924 int rd
, int rn
, int32_t offset
)
926 if (offset
> 0xff || offset
< -0xff) {
927 tcg_out_movi32(s
, cond
, TCG_REG_TMP
, offset
);
928 tcg_out_ld16s_r(s
, cond
, rd
, rn
, TCG_REG_TMP
);
930 tcg_out_ld16s_8(s
, cond
, rd
, rn
, offset
);
933 static inline void tcg_out_st16(TCGContext
*s
, int cond
,
934 int rd
, int rn
, int32_t offset
)
936 if (offset
> 0xff || offset
< -0xff) {
937 tcg_out_movi32(s
, cond
, TCG_REG_TMP
, offset
);
938 tcg_out_st16_r(s
, cond
, rd
, rn
, TCG_REG_TMP
);
940 tcg_out_st16_8(s
, cond
, rd
, rn
, offset
);
943 static inline void tcg_out_ld8u(TCGContext
*s
, int cond
,
944 int rd
, int rn
, int32_t offset
)
946 if (offset
> 0xfff || offset
< -0xfff) {
947 tcg_out_movi32(s
, cond
, TCG_REG_TMP
, offset
);
948 tcg_out_ld8_r(s
, cond
, rd
, rn
, TCG_REG_TMP
);
950 tcg_out_ld8_12(s
, cond
, rd
, rn
, offset
);
953 static inline void tcg_out_ld8s(TCGContext
*s
, int cond
,
954 int rd
, int rn
, int32_t offset
)
956 if (offset
> 0xff || offset
< -0xff) {
957 tcg_out_movi32(s
, cond
, TCG_REG_TMP
, offset
);
958 tcg_out_ld8s_r(s
, cond
, rd
, rn
, TCG_REG_TMP
);
960 tcg_out_ld8s_8(s
, cond
, rd
, rn
, offset
);
963 static inline void tcg_out_st8(TCGContext
*s
, int cond
,
964 int rd
, int rn
, int32_t offset
)
966 if (offset
> 0xfff || offset
< -0xfff) {
967 tcg_out_movi32(s
, cond
, TCG_REG_TMP
, offset
);
968 tcg_out_st8_r(s
, cond
, rd
, rn
, TCG_REG_TMP
);
970 tcg_out_st8_12(s
, cond
, rd
, rn
, offset
);
973 /* The _goto case is normally between TBs within the same code buffer, and
974 * with the code buffer limited to 16MB we wouldn't need the long case.
975 * But we also use it for the tail-call to the qemu_ld/st helpers, which does.
977 static inline void tcg_out_goto(TCGContext
*s
, int cond
, tcg_insn_unit
*addr
)
979 intptr_t addri
= (intptr_t)addr
;
980 ptrdiff_t disp
= tcg_pcrel_diff(s
, addr
);
982 if ((addri
& 1) == 0 && disp
- 8 < 0x01fffffd && disp
- 8 > -0x01fffffd) {
983 tcg_out_b(s
, cond
, disp
);
987 tcg_out_movi32(s
, cond
, TCG_REG_TMP
, addri
);
988 if (use_armv5t_instructions
) {
989 tcg_out_bx(s
, cond
, TCG_REG_TMP
);
994 tcg_out_mov_reg(s
, cond
, TCG_REG_PC
, TCG_REG_TMP
);
998 /* The call case is mostly used for helpers - so it's not unreasonable
999 * for them to be beyond branch range */
1000 static void tcg_out_call(TCGContext
*s
, tcg_insn_unit
*addr
)
1002 intptr_t addri
= (intptr_t)addr
;
1003 ptrdiff_t disp
= tcg_pcrel_diff(s
, addr
);
1005 if (disp
- 8 < 0x02000000 && disp
- 8 >= -0x02000000) {
1007 /* Use BLX if the target is in Thumb mode */
1008 if (!use_armv5t_instructions
) {
1011 tcg_out_blx_imm(s
, disp
);
1013 tcg_out_bl(s
, COND_AL
, disp
);
1015 } else if (use_armv7_instructions
) {
1016 tcg_out_movi32(s
, COND_AL
, TCG_REG_TMP
, addri
);
1017 tcg_out_blx(s
, COND_AL
, TCG_REG_TMP
);
1019 tcg_out_dat_imm(s
, COND_AL
, ARITH_ADD
, TCG_REG_R14
, TCG_REG_PC
, 4);
1020 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_PC
, -4);
1021 tcg_out32(s
, addri
);
1025 void arm_tb_set_jmp_target(uintptr_t jmp_addr
, uintptr_t addr
)
1027 tcg_insn_unit
*code_ptr
= (tcg_insn_unit
*)jmp_addr
;
1028 tcg_insn_unit
*target
= (tcg_insn_unit
*)addr
;
1030 /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
1031 reloc_pc24_atomic(code_ptr
, target
);
1032 flush_icache_range(jmp_addr
, jmp_addr
+ 4);
1035 static inline void tcg_out_goto_label(TCGContext
*s
, int cond
, TCGLabel
*l
)
1038 tcg_out_goto(s
, cond
, l
->u
.value_ptr
);
1040 tcg_out_reloc(s
, s
->code_ptr
, R_ARM_PC24
, l
, 0);
1041 tcg_out_b_noaddr(s
, cond
);
1045 static inline void tcg_out_mb(TCGContext
*s
, TCGArg a0
)
1047 if (use_armv7_instructions
) {
1048 tcg_out32(s
, INSN_DMB_ISH
);
1049 } else if (use_armv6_instructions
) {
1050 tcg_out32(s
, INSN_DMB_MCR
);
1054 #ifdef CONFIG_SOFTMMU
1055 /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
1056 * int mmu_idx, uintptr_t ra)
1058 static void * const qemu_ld_helpers
[16] = {
1059 [MO_UB
] = helper_ret_ldub_mmu
,
1060 [MO_SB
] = helper_ret_ldsb_mmu
,
1062 [MO_LEUW
] = helper_le_lduw_mmu
,
1063 [MO_LEUL
] = helper_le_ldul_mmu
,
1064 [MO_LEQ
] = helper_le_ldq_mmu
,
1065 [MO_LESW
] = helper_le_ldsw_mmu
,
1066 [MO_LESL
] = helper_le_ldul_mmu
,
1068 [MO_BEUW
] = helper_be_lduw_mmu
,
1069 [MO_BEUL
] = helper_be_ldul_mmu
,
1070 [MO_BEQ
] = helper_be_ldq_mmu
,
1071 [MO_BESW
] = helper_be_ldsw_mmu
,
1072 [MO_BESL
] = helper_be_ldul_mmu
,
1075 /* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
1076 * uintxx_t val, int mmu_idx, uintptr_t ra)
1078 static void * const qemu_st_helpers
[16] = {
1079 [MO_UB
] = helper_ret_stb_mmu
,
1080 [MO_LEUW
] = helper_le_stw_mmu
,
1081 [MO_LEUL
] = helper_le_stl_mmu
,
1082 [MO_LEQ
] = helper_le_stq_mmu
,
1083 [MO_BEUW
] = helper_be_stw_mmu
,
1084 [MO_BEUL
] = helper_be_stl_mmu
,
1085 [MO_BEQ
] = helper_be_stq_mmu
,
1088 /* Helper routines for marshalling helper function arguments into
1089 * the correct registers and stack.
1090 * argreg is where we want to put this argument, arg is the argument itself.
1091 * Return value is the updated argreg ready for the next call.
1092 * Note that argreg 0..3 is real registers, 4+ on stack.
1094 * We provide routines for arguments which are: immediate, 32 bit
1095 * value in register, 16 and 8 bit values in register (which must be zero
1096 * extended before use) and 64 bit value in a lo:hi register pair.
1098 #define DEFINE_TCG_OUT_ARG(NAME, ARGTYPE, MOV_ARG, EXT_ARG) \
1099 static TCGReg NAME(TCGContext *s, TCGReg argreg, ARGTYPE arg) \
1102 MOV_ARG(s, COND_AL, argreg, arg); \
1104 int ofs = (argreg - 4) * 4; \
1106 tcg_debug_assert(ofs + 4 <= TCG_STATIC_CALL_ARGS_SIZE); \
1107 tcg_out_st32_12(s, COND_AL, arg, TCG_REG_CALL_STACK, ofs); \
1109 return argreg + 1; \
1112 DEFINE_TCG_OUT_ARG(tcg_out_arg_imm32
, uint32_t, tcg_out_movi32
,
1113 (tcg_out_movi32(s
, COND_AL
, TCG_REG_TMP
, arg
), arg
= TCG_REG_TMP
))
1114 DEFINE_TCG_OUT_ARG(tcg_out_arg_reg8
, TCGReg
, tcg_out_ext8u
,
1115 (tcg_out_ext8u(s
, COND_AL
, TCG_REG_TMP
, arg
), arg
= TCG_REG_TMP
))
1116 DEFINE_TCG_OUT_ARG(tcg_out_arg_reg16
, TCGReg
, tcg_out_ext16u
,
1117 (tcg_out_ext16u(s
, COND_AL
, TCG_REG_TMP
, arg
), arg
= TCG_REG_TMP
))
1118 DEFINE_TCG_OUT_ARG(tcg_out_arg_reg32
, TCGReg
, tcg_out_mov_reg
, )
1120 static TCGReg
tcg_out_arg_reg64(TCGContext
*s
, TCGReg argreg
,
1121 TCGReg arglo
, TCGReg arghi
)
1123 /* 64 bit arguments must go in even/odd register pairs
1124 * and in 8-aligned stack slots.
1129 if (use_armv6_instructions
&& argreg
>= 4
1130 && (arglo
& 1) == 0 && arghi
== arglo
+ 1) {
1131 tcg_out_strd_8(s
, COND_AL
, arglo
,
1132 TCG_REG_CALL_STACK
, (argreg
- 4) * 4);
1135 argreg
= tcg_out_arg_reg32(s
, argreg
, arglo
);
1136 argreg
= tcg_out_arg_reg32(s
, argreg
, arghi
);
1141 #define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS)
1143 /* We're expecting to use an 8-bit immediate and to mask. */
1144 QEMU_BUILD_BUG_ON(CPU_TLB_BITS
> 8);
1146 /* We're expecting to use an 8-bit immediate add + 8-bit ldrd offset.
1147 Using the offset of the second entry in the last tlb table ensures
1148 that we can index all of the elements of the first entry. */
1149 QEMU_BUILD_BUG_ON(offsetof(CPUArchState
, tlb_table
[NB_MMU_MODES
- 1][1])
1152 /* Load and compare a TLB entry, leaving the flags set. Returns the register
1153 containing the addend of the tlb entry. Clobbers R0, R1, R2, TMP. */
1155 static TCGReg
tcg_out_tlb_read(TCGContext
*s
, TCGReg addrlo
, TCGReg addrhi
,
1156 TCGMemOp opc
, int mem_index
, bool is_load
)
1158 TCGReg base
= TCG_AREG0
;
1161 ? offsetof(CPUArchState
, tlb_table
[mem_index
][0].addr_read
)
1162 : offsetof(CPUArchState
, tlb_table
[mem_index
][0].addr_write
));
1163 int add_off
= offsetof(CPUArchState
, tlb_table
[mem_index
][0].addend
);
1164 unsigned s_bits
= opc
& MO_SIZE
;
1165 unsigned a_bits
= get_alignment_bits(opc
);
1167 /* Should generate something like the following:
1168 * shr tmp, addrlo, #TARGET_PAGE_BITS (1)
1169 * add r2, env, #high
1170 * and r0, tmp, #(CPU_TLB_SIZE - 1) (2)
1171 * add r2, r2, r0, lsl #CPU_TLB_ENTRY_BITS (3)
1172 * ldr r0, [r2, #cmp] (4)
1173 * tst addrlo, #s_mask
1174 * ldr r2, [r2, #add] (5)
1175 * cmpeq r0, tmp, lsl #TARGET_PAGE_BITS
1177 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, TCG_REG_TMP
,
1178 0, addrlo
, SHIFT_IMM_LSR(TARGET_PAGE_BITS
));
1180 /* We checked that the offset is contained within 16 bits above. */
1181 if (add_off
> 0xfff || (use_armv6_instructions
&& cmp_off
> 0xff)) {
1182 tcg_out_dat_imm(s
, COND_AL
, ARITH_ADD
, TCG_REG_R2
, base
,
1183 (24 << 7) | (cmp_off
>> 8));
1185 add_off
-= cmp_off
& 0xff00;
1189 tcg_out_dat_imm(s
, COND_AL
, ARITH_AND
,
1190 TCG_REG_R0
, TCG_REG_TMP
, CPU_TLB_SIZE
- 1);
1191 tcg_out_dat_reg(s
, COND_AL
, ARITH_ADD
, TCG_REG_R2
, base
,
1192 TCG_REG_R0
, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS
));
1194 /* Load the tlb comparator. Use ldrd if needed and available,
1195 but due to how the pointer needs setting up, ldm isn't useful.
1196 Base arm5 doesn't have ldrd, but armv5te does. */
1197 if (use_armv6_instructions
&& TARGET_LONG_BITS
== 64) {
1198 tcg_out_ldrd_8(s
, COND_AL
, TCG_REG_R0
, TCG_REG_R2
, cmp_off
);
1200 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_R0
, TCG_REG_R2
, cmp_off
);
1201 if (TARGET_LONG_BITS
== 64) {
1202 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_R1
, TCG_REG_R2
, cmp_off
+ 4);
1206 /* Check alignment. We don't support inline unaligned acceses,
1207 but we can easily support overalignment checks. */
1208 if (a_bits
< s_bits
) {
1212 tcg_out_dat_imm(s
, COND_AL
, ARITH_TST
, 0, addrlo
, (1 << a_bits
) - 1);
1215 /* Load the tlb addend. */
1216 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_R2
, TCG_REG_R2
, add_off
);
1218 tcg_out_dat_reg(s
, (s_bits
? COND_EQ
: COND_AL
), ARITH_CMP
, 0,
1219 TCG_REG_R0
, TCG_REG_TMP
, SHIFT_IMM_LSL(TARGET_PAGE_BITS
));
1221 if (TARGET_LONG_BITS
== 64) {
1222 tcg_out_dat_reg(s
, COND_EQ
, ARITH_CMP
, 0,
1223 TCG_REG_R1
, addrhi
, SHIFT_IMM_LSL(0));
1229 /* Record the context of a call to the out of line helper code for the slow
1230 path for a load or store, so that we can later generate the correct
1232 static void add_qemu_ldst_label(TCGContext
*s
, bool is_ld
, TCGMemOpIdx oi
,
1233 TCGReg datalo
, TCGReg datahi
, TCGReg addrlo
,
1234 TCGReg addrhi
, tcg_insn_unit
*raddr
,
1235 tcg_insn_unit
*label_ptr
)
1237 TCGLabelQemuLdst
*label
= new_ldst_label(s
);
1239 label
->is_ld
= is_ld
;
1241 label
->datalo_reg
= datalo
;
1242 label
->datahi_reg
= datahi
;
1243 label
->addrlo_reg
= addrlo
;
1244 label
->addrhi_reg
= addrhi
;
1245 label
->raddr
= raddr
;
1246 label
->label_ptr
[0] = label_ptr
;
1249 static void tcg_out_qemu_ld_slow_path(TCGContext
*s
, TCGLabelQemuLdst
*lb
)
1251 TCGReg argreg
, datalo
, datahi
;
1252 TCGMemOpIdx oi
= lb
->oi
;
1253 TCGMemOp opc
= get_memop(oi
);
1256 reloc_pc24(lb
->label_ptr
[0], s
->code_ptr
);
1258 argreg
= tcg_out_arg_reg32(s
, TCG_REG_R0
, TCG_AREG0
);
1259 if (TARGET_LONG_BITS
== 64) {
1260 argreg
= tcg_out_arg_reg64(s
, argreg
, lb
->addrlo_reg
, lb
->addrhi_reg
);
1262 argreg
= tcg_out_arg_reg32(s
, argreg
, lb
->addrlo_reg
);
1264 argreg
= tcg_out_arg_imm32(s
, argreg
, oi
);
1265 argreg
= tcg_out_arg_reg32(s
, argreg
, TCG_REG_R14
);
1267 /* For armv6 we can use the canonical unsigned helpers and minimize
1268 icache usage. For pre-armv6, use the signed helpers since we do
1269 not have a single insn sign-extend. */
1270 if (use_armv6_instructions
) {
1271 func
= qemu_ld_helpers
[opc
& (MO_BSWAP
| MO_SIZE
)];
1273 func
= qemu_ld_helpers
[opc
& (MO_BSWAP
| MO_SSIZE
)];
1274 if (opc
& MO_SIGN
) {
1278 tcg_out_call(s
, func
);
1280 datalo
= lb
->datalo_reg
;
1281 datahi
= lb
->datahi_reg
;
1282 switch (opc
& MO_SSIZE
) {
1284 tcg_out_ext8s(s
, COND_AL
, datalo
, TCG_REG_R0
);
1287 tcg_out_ext16s(s
, COND_AL
, datalo
, TCG_REG_R0
);
1290 tcg_out_mov_reg(s
, COND_AL
, datalo
, TCG_REG_R0
);
1293 if (datalo
!= TCG_REG_R1
) {
1294 tcg_out_mov_reg(s
, COND_AL
, datalo
, TCG_REG_R0
);
1295 tcg_out_mov_reg(s
, COND_AL
, datahi
, TCG_REG_R1
);
1296 } else if (datahi
!= TCG_REG_R0
) {
1297 tcg_out_mov_reg(s
, COND_AL
, datahi
, TCG_REG_R1
);
1298 tcg_out_mov_reg(s
, COND_AL
, datalo
, TCG_REG_R0
);
1300 tcg_out_mov_reg(s
, COND_AL
, TCG_REG_TMP
, TCG_REG_R0
);
1301 tcg_out_mov_reg(s
, COND_AL
, datahi
, TCG_REG_R1
);
1302 tcg_out_mov_reg(s
, COND_AL
, datalo
, TCG_REG_TMP
);
1307 tcg_out_goto(s
, COND_AL
, lb
->raddr
);
1310 static void tcg_out_qemu_st_slow_path(TCGContext
*s
, TCGLabelQemuLdst
*lb
)
1312 TCGReg argreg
, datalo
, datahi
;
1313 TCGMemOpIdx oi
= lb
->oi
;
1314 TCGMemOp opc
= get_memop(oi
);
1316 reloc_pc24(lb
->label_ptr
[0], s
->code_ptr
);
1318 argreg
= TCG_REG_R0
;
1319 argreg
= tcg_out_arg_reg32(s
, argreg
, TCG_AREG0
);
1320 if (TARGET_LONG_BITS
== 64) {
1321 argreg
= tcg_out_arg_reg64(s
, argreg
, lb
->addrlo_reg
, lb
->addrhi_reg
);
1323 argreg
= tcg_out_arg_reg32(s
, argreg
, lb
->addrlo_reg
);
1326 datalo
= lb
->datalo_reg
;
1327 datahi
= lb
->datahi_reg
;
1328 switch (opc
& MO_SIZE
) {
1330 argreg
= tcg_out_arg_reg8(s
, argreg
, datalo
);
1333 argreg
= tcg_out_arg_reg16(s
, argreg
, datalo
);
1337 argreg
= tcg_out_arg_reg32(s
, argreg
, datalo
);
1340 argreg
= tcg_out_arg_reg64(s
, argreg
, datalo
, datahi
);
1344 argreg
= tcg_out_arg_imm32(s
, argreg
, oi
);
1345 argreg
= tcg_out_arg_reg32(s
, argreg
, TCG_REG_R14
);
1347 /* Tail-call to the helper, which will return to the fast path. */
1348 tcg_out_goto(s
, COND_AL
, qemu_st_helpers
[opc
& (MO_BSWAP
| MO_SIZE
)]);
1350 #endif /* SOFTMMU */
1352 static inline void tcg_out_qemu_ld_index(TCGContext
*s
, TCGMemOp opc
,
1353 TCGReg datalo
, TCGReg datahi
,
1354 TCGReg addrlo
, TCGReg addend
)
1356 TCGMemOp bswap
= opc
& MO_BSWAP
;
1358 switch (opc
& MO_SSIZE
) {
1360 tcg_out_ld8_r(s
, COND_AL
, datalo
, addrlo
, addend
);
1363 tcg_out_ld8s_r(s
, COND_AL
, datalo
, addrlo
, addend
);
1366 tcg_out_ld16u_r(s
, COND_AL
, datalo
, addrlo
, addend
);
1368 tcg_out_bswap16(s
, COND_AL
, datalo
, datalo
);
1373 tcg_out_ld16u_r(s
, COND_AL
, datalo
, addrlo
, addend
);
1374 tcg_out_bswap16s(s
, COND_AL
, datalo
, datalo
);
1376 tcg_out_ld16s_r(s
, COND_AL
, datalo
, addrlo
, addend
);
1381 tcg_out_ld32_r(s
, COND_AL
, datalo
, addrlo
, addend
);
1383 tcg_out_bswap32(s
, COND_AL
, datalo
, datalo
);
1388 TCGReg dl
= (bswap
? datahi
: datalo
);
1389 TCGReg dh
= (bswap
? datalo
: datahi
);
1391 /* Avoid ldrd for user-only emulation, to handle unaligned. */
1392 if (USING_SOFTMMU
&& use_armv6_instructions
1393 && (dl
& 1) == 0 && dh
== dl
+ 1) {
1394 tcg_out_ldrd_r(s
, COND_AL
, dl
, addrlo
, addend
);
1395 } else if (dl
!= addend
) {
1396 tcg_out_ld32_rwb(s
, COND_AL
, dl
, addend
, addrlo
);
1397 tcg_out_ld32_12(s
, COND_AL
, dh
, addend
, 4);
1399 tcg_out_dat_reg(s
, COND_AL
, ARITH_ADD
, TCG_REG_TMP
,
1400 addend
, addrlo
, SHIFT_IMM_LSL(0));
1401 tcg_out_ld32_12(s
, COND_AL
, dl
, TCG_REG_TMP
, 0);
1402 tcg_out_ld32_12(s
, COND_AL
, dh
, TCG_REG_TMP
, 4);
1405 tcg_out_bswap32(s
, COND_AL
, dl
, dl
);
1406 tcg_out_bswap32(s
, COND_AL
, dh
, dh
);
1413 static inline void tcg_out_qemu_ld_direct(TCGContext
*s
, TCGMemOp opc
,
1414 TCGReg datalo
, TCGReg datahi
,
1417 TCGMemOp bswap
= opc
& MO_BSWAP
;
1419 switch (opc
& MO_SSIZE
) {
1421 tcg_out_ld8_12(s
, COND_AL
, datalo
, addrlo
, 0);
1424 tcg_out_ld8s_8(s
, COND_AL
, datalo
, addrlo
, 0);
1427 tcg_out_ld16u_8(s
, COND_AL
, datalo
, addrlo
, 0);
1429 tcg_out_bswap16(s
, COND_AL
, datalo
, datalo
);
1434 tcg_out_ld16u_8(s
, COND_AL
, datalo
, addrlo
, 0);
1435 tcg_out_bswap16s(s
, COND_AL
, datalo
, datalo
);
1437 tcg_out_ld16s_8(s
, COND_AL
, datalo
, addrlo
, 0);
1442 tcg_out_ld32_12(s
, COND_AL
, datalo
, addrlo
, 0);
1444 tcg_out_bswap32(s
, COND_AL
, datalo
, datalo
);
1449 TCGReg dl
= (bswap
? datahi
: datalo
);
1450 TCGReg dh
= (bswap
? datalo
: datahi
);
1452 /* Avoid ldrd for user-only emulation, to handle unaligned. */
1453 if (USING_SOFTMMU
&& use_armv6_instructions
1454 && (dl
& 1) == 0 && dh
== dl
+ 1) {
1455 tcg_out_ldrd_8(s
, COND_AL
, dl
, addrlo
, 0);
1456 } else if (dl
== addrlo
) {
1457 tcg_out_ld32_12(s
, COND_AL
, dh
, addrlo
, bswap
? 0 : 4);
1458 tcg_out_ld32_12(s
, COND_AL
, dl
, addrlo
, bswap
? 4 : 0);
1460 tcg_out_ld32_12(s
, COND_AL
, dl
, addrlo
, bswap
? 4 : 0);
1461 tcg_out_ld32_12(s
, COND_AL
, dh
, addrlo
, bswap
? 0 : 4);
1464 tcg_out_bswap32(s
, COND_AL
, dl
, dl
);
1465 tcg_out_bswap32(s
, COND_AL
, dh
, dh
);
1472 static void tcg_out_qemu_ld(TCGContext
*s
, const TCGArg
*args
, bool is64
)
1474 TCGReg addrlo
, datalo
, datahi
, addrhi
__attribute__((unused
));
1477 #ifdef CONFIG_SOFTMMU
1480 tcg_insn_unit
*label_ptr
;
1484 datahi
= (is64
? *args
++ : 0);
1486 addrhi
= (TARGET_LONG_BITS
== 64 ? *args
++ : 0);
1488 opc
= get_memop(oi
);
1490 #ifdef CONFIG_SOFTMMU
1491 mem_index
= get_mmuidx(oi
);
1492 addend
= tcg_out_tlb_read(s
, addrlo
, addrhi
, opc
, mem_index
, 1);
1494 /* This a conditional BL only to load a pointer within this opcode into LR
1495 for the slow path. We will not be using the value for a tail call. */
1496 label_ptr
= s
->code_ptr
;
1497 tcg_out_bl_noaddr(s
, COND_NE
);
1499 tcg_out_qemu_ld_index(s
, opc
, datalo
, datahi
, addrlo
, addend
);
1501 add_qemu_ldst_label(s
, true, oi
, datalo
, datahi
, addrlo
, addrhi
,
1502 s
->code_ptr
, label_ptr
);
1503 #else /* !CONFIG_SOFTMMU */
1505 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_TMP
, guest_base
);
1506 tcg_out_qemu_ld_index(s
, opc
, datalo
, datahi
, addrlo
, TCG_REG_TMP
);
1508 tcg_out_qemu_ld_direct(s
, opc
, datalo
, datahi
, addrlo
);
1513 static inline void tcg_out_qemu_st_index(TCGContext
*s
, int cond
, TCGMemOp opc
,
1514 TCGReg datalo
, TCGReg datahi
,
1515 TCGReg addrlo
, TCGReg addend
)
1517 TCGMemOp bswap
= opc
& MO_BSWAP
;
1519 switch (opc
& MO_SIZE
) {
1521 tcg_out_st8_r(s
, cond
, datalo
, addrlo
, addend
);
1525 tcg_out_bswap16st(s
, cond
, TCG_REG_R0
, datalo
);
1526 tcg_out_st16_r(s
, cond
, TCG_REG_R0
, addrlo
, addend
);
1528 tcg_out_st16_r(s
, cond
, datalo
, addrlo
, addend
);
1534 tcg_out_bswap32(s
, cond
, TCG_REG_R0
, datalo
);
1535 tcg_out_st32_r(s
, cond
, TCG_REG_R0
, addrlo
, addend
);
1537 tcg_out_st32_r(s
, cond
, datalo
, addrlo
, addend
);
1541 /* Avoid strd for user-only emulation, to handle unaligned. */
1543 tcg_out_bswap32(s
, cond
, TCG_REG_R0
, datahi
);
1544 tcg_out_st32_rwb(s
, cond
, TCG_REG_R0
, addend
, addrlo
);
1545 tcg_out_bswap32(s
, cond
, TCG_REG_R0
, datalo
);
1546 tcg_out_st32_12(s
, cond
, TCG_REG_R0
, addend
, 4);
1547 } else if (USING_SOFTMMU
&& use_armv6_instructions
1548 && (datalo
& 1) == 0 && datahi
== datalo
+ 1) {
1549 tcg_out_strd_r(s
, cond
, datalo
, addrlo
, addend
);
1551 tcg_out_st32_rwb(s
, cond
, datalo
, addend
, addrlo
);
1552 tcg_out_st32_12(s
, cond
, datahi
, addend
, 4);
1558 static inline void tcg_out_qemu_st_direct(TCGContext
*s
, TCGMemOp opc
,
1559 TCGReg datalo
, TCGReg datahi
,
1562 TCGMemOp bswap
= opc
& MO_BSWAP
;
1564 switch (opc
& MO_SIZE
) {
1566 tcg_out_st8_12(s
, COND_AL
, datalo
, addrlo
, 0);
1570 tcg_out_bswap16st(s
, COND_AL
, TCG_REG_R0
, datalo
);
1571 tcg_out_st16_8(s
, COND_AL
, TCG_REG_R0
, addrlo
, 0);
1573 tcg_out_st16_8(s
, COND_AL
, datalo
, addrlo
, 0);
1579 tcg_out_bswap32(s
, COND_AL
, TCG_REG_R0
, datalo
);
1580 tcg_out_st32_12(s
, COND_AL
, TCG_REG_R0
, addrlo
, 0);
1582 tcg_out_st32_12(s
, COND_AL
, datalo
, addrlo
, 0);
1586 /* Avoid strd for user-only emulation, to handle unaligned. */
1588 tcg_out_bswap32(s
, COND_AL
, TCG_REG_R0
, datahi
);
1589 tcg_out_st32_12(s
, COND_AL
, TCG_REG_R0
, addrlo
, 0);
1590 tcg_out_bswap32(s
, COND_AL
, TCG_REG_R0
, datalo
);
1591 tcg_out_st32_12(s
, COND_AL
, TCG_REG_R0
, addrlo
, 4);
1592 } else if (USING_SOFTMMU
&& use_armv6_instructions
1593 && (datalo
& 1) == 0 && datahi
== datalo
+ 1) {
1594 tcg_out_strd_8(s
, COND_AL
, datalo
, addrlo
, 0);
1596 tcg_out_st32_12(s
, COND_AL
, datalo
, addrlo
, 0);
1597 tcg_out_st32_12(s
, COND_AL
, datahi
, addrlo
, 4);
1603 static void tcg_out_qemu_st(TCGContext
*s
, const TCGArg
*args
, bool is64
)
1605 TCGReg addrlo
, datalo
, datahi
, addrhi
__attribute__((unused
));
1608 #ifdef CONFIG_SOFTMMU
1611 tcg_insn_unit
*label_ptr
;
1615 datahi
= (is64
? *args
++ : 0);
1617 addrhi
= (TARGET_LONG_BITS
== 64 ? *args
++ : 0);
1619 opc
= get_memop(oi
);
1621 #ifdef CONFIG_SOFTMMU
1622 mem_index
= get_mmuidx(oi
);
1623 addend
= tcg_out_tlb_read(s
, addrlo
, addrhi
, opc
, mem_index
, 0);
1625 tcg_out_qemu_st_index(s
, COND_EQ
, opc
, datalo
, datahi
, addrlo
, addend
);
1627 /* The conditional call must come last, as we're going to return here. */
1628 label_ptr
= s
->code_ptr
;
1629 tcg_out_bl_noaddr(s
, COND_NE
);
1631 add_qemu_ldst_label(s
, false, oi
, datalo
, datahi
, addrlo
, addrhi
,
1632 s
->code_ptr
, label_ptr
);
1633 #else /* !CONFIG_SOFTMMU */
1635 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_TMP
, guest_base
);
1636 tcg_out_qemu_st_index(s
, COND_AL
, opc
, datalo
,
1637 datahi
, addrlo
, TCG_REG_TMP
);
1639 tcg_out_qemu_st_direct(s
, opc
, datalo
, datahi
, addrlo
);
1644 static tcg_insn_unit
*tb_ret_addr
;
1646 static inline void tcg_out_op(TCGContext
*s
, TCGOpcode opc
,
1647 const TCGArg
*args
, const int *const_args
)
1649 TCGArg a0
, a1
, a2
, a3
, a4
, a5
;
1653 case INDEX_op_exit_tb
:
1654 tcg_out_movi32(s
, COND_AL
, TCG_REG_R0
, args
[0]);
1655 tcg_out_goto(s
, COND_AL
, tb_ret_addr
);
1657 case INDEX_op_goto_tb
:
1658 if (s
->tb_jmp_insn_offset
) {
1659 /* Direct jump method */
1660 s
->tb_jmp_insn_offset
[args
[0]] = tcg_current_code_size(s
);
1661 tcg_out_b_noaddr(s
, COND_AL
);
1663 /* Indirect jump method */
1664 intptr_t ptr
= (intptr_t)(s
->tb_jmp_target_addr
+ args
[0]);
1665 tcg_out_movi32(s
, COND_AL
, TCG_REG_R0
, ptr
& ~0xfff);
1666 tcg_out_ld32_12(s
, COND_AL
, TCG_REG_PC
, TCG_REG_R0
, ptr
& 0xfff);
1668 s
->tb_jmp_reset_offset
[args
[0]] = tcg_current_code_size(s
);
1671 tcg_out_goto_label(s
, COND_AL
, arg_label(args
[0]));
1674 case INDEX_op_ld8u_i32
:
1675 tcg_out_ld8u(s
, COND_AL
, args
[0], args
[1], args
[2]);
1677 case INDEX_op_ld8s_i32
:
1678 tcg_out_ld8s(s
, COND_AL
, args
[0], args
[1], args
[2]);
1680 case INDEX_op_ld16u_i32
:
1681 tcg_out_ld16u(s
, COND_AL
, args
[0], args
[1], args
[2]);
1683 case INDEX_op_ld16s_i32
:
1684 tcg_out_ld16s(s
, COND_AL
, args
[0], args
[1], args
[2]);
1686 case INDEX_op_ld_i32
:
1687 tcg_out_ld32u(s
, COND_AL
, args
[0], args
[1], args
[2]);
1689 case INDEX_op_st8_i32
:
1690 tcg_out_st8(s
, COND_AL
, args
[0], args
[1], args
[2]);
1692 case INDEX_op_st16_i32
:
1693 tcg_out_st16(s
, COND_AL
, args
[0], args
[1], args
[2]);
1695 case INDEX_op_st_i32
:
1696 tcg_out_st32(s
, COND_AL
, args
[0], args
[1], args
[2]);
1699 case INDEX_op_movcond_i32
:
1700 /* Constraints mean that v2 is always in the same register as dest,
1701 * so we only need to do "if condition passed, move v1 to dest".
1703 tcg_out_dat_rIN(s
, COND_AL
, ARITH_CMP
, ARITH_CMN
, 0,
1704 args
[1], args
[2], const_args
[2]);
1705 tcg_out_dat_rIK(s
, tcg_cond_to_arm_cond
[args
[5]], ARITH_MOV
,
1706 ARITH_MVN
, args
[0], 0, args
[3], const_args
[3]);
1708 case INDEX_op_add_i32
:
1709 tcg_out_dat_rIN(s
, COND_AL
, ARITH_ADD
, ARITH_SUB
,
1710 args
[0], args
[1], args
[2], const_args
[2]);
1712 case INDEX_op_sub_i32
:
1713 if (const_args
[1]) {
1714 if (const_args
[2]) {
1715 tcg_out_movi32(s
, COND_AL
, args
[0], args
[1] - args
[2]);
1717 tcg_out_dat_rI(s
, COND_AL
, ARITH_RSB
,
1718 args
[0], args
[2], args
[1], 1);
1721 tcg_out_dat_rIN(s
, COND_AL
, ARITH_SUB
, ARITH_ADD
,
1722 args
[0], args
[1], args
[2], const_args
[2]);
1725 case INDEX_op_and_i32
:
1726 tcg_out_dat_rIK(s
, COND_AL
, ARITH_AND
, ARITH_BIC
,
1727 args
[0], args
[1], args
[2], const_args
[2]);
1729 case INDEX_op_andc_i32
:
1730 tcg_out_dat_rIK(s
, COND_AL
, ARITH_BIC
, ARITH_AND
,
1731 args
[0], args
[1], args
[2], const_args
[2]);
1733 case INDEX_op_or_i32
:
1736 case INDEX_op_xor_i32
:
1740 tcg_out_dat_rI(s
, COND_AL
, c
, args
[0], args
[1], args
[2], const_args
[2]);
1742 case INDEX_op_add2_i32
:
1743 a0
= args
[0], a1
= args
[1], a2
= args
[2];
1744 a3
= args
[3], a4
= args
[4], a5
= args
[5];
1745 if (a0
== a3
|| (a0
== a5
&& !const_args
[5])) {
1748 tcg_out_dat_rIN(s
, COND_AL
, ARITH_ADD
| TO_CPSR
, ARITH_SUB
| TO_CPSR
,
1749 a0
, a2
, a4
, const_args
[4]);
1750 tcg_out_dat_rIK(s
, COND_AL
, ARITH_ADC
, ARITH_SBC
,
1751 a1
, a3
, a5
, const_args
[5]);
1752 tcg_out_mov_reg(s
, COND_AL
, args
[0], a0
);
1754 case INDEX_op_sub2_i32
:
1755 a0
= args
[0], a1
= args
[1], a2
= args
[2];
1756 a3
= args
[3], a4
= args
[4], a5
= args
[5];
1757 if ((a0
== a3
&& !const_args
[3]) || (a0
== a5
&& !const_args
[5])) {
1760 if (const_args
[2]) {
1761 if (const_args
[4]) {
1762 tcg_out_movi32(s
, COND_AL
, a0
, a4
);
1765 tcg_out_dat_rI(s
, COND_AL
, ARITH_RSB
| TO_CPSR
, a0
, a4
, a2
, 1);
1767 tcg_out_dat_rIN(s
, COND_AL
, ARITH_SUB
| TO_CPSR
,
1768 ARITH_ADD
| TO_CPSR
, a0
, a2
, a4
, const_args
[4]);
1770 if (const_args
[3]) {
1771 if (const_args
[5]) {
1772 tcg_out_movi32(s
, COND_AL
, a1
, a5
);
1775 tcg_out_dat_rI(s
, COND_AL
, ARITH_RSC
, a1
, a5
, a3
, 1);
1777 tcg_out_dat_rIK(s
, COND_AL
, ARITH_SBC
, ARITH_ADC
,
1778 a1
, a3
, a5
, const_args
[5]);
1780 tcg_out_mov_reg(s
, COND_AL
, args
[0], a0
);
1782 case INDEX_op_neg_i32
:
1783 tcg_out_dat_imm(s
, COND_AL
, ARITH_RSB
, args
[0], args
[1], 0);
1785 case INDEX_op_not_i32
:
1786 tcg_out_dat_reg(s
, COND_AL
,
1787 ARITH_MVN
, args
[0], 0, args
[1], SHIFT_IMM_LSL(0));
1789 case INDEX_op_mul_i32
:
1790 tcg_out_mul32(s
, COND_AL
, args
[0], args
[1], args
[2]);
1792 case INDEX_op_mulu2_i32
:
1793 tcg_out_umull32(s
, COND_AL
, args
[0], args
[1], args
[2], args
[3]);
1795 case INDEX_op_muls2_i32
:
1796 tcg_out_smull32(s
, COND_AL
, args
[0], args
[1], args
[2], args
[3]);
1798 /* XXX: Perhaps args[2] & 0x1f is wrong */
1799 case INDEX_op_shl_i32
:
1801 SHIFT_IMM_LSL(args
[2] & 0x1f) : SHIFT_REG_LSL(args
[2]);
1803 case INDEX_op_shr_i32
:
1804 c
= const_args
[2] ? (args
[2] & 0x1f) ? SHIFT_IMM_LSR(args
[2] & 0x1f) :
1805 SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args
[2]);
1807 case INDEX_op_sar_i32
:
1808 c
= const_args
[2] ? (args
[2] & 0x1f) ? SHIFT_IMM_ASR(args
[2] & 0x1f) :
1809 SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args
[2]);
1811 case INDEX_op_rotr_i32
:
1812 c
= const_args
[2] ? (args
[2] & 0x1f) ? SHIFT_IMM_ROR(args
[2] & 0x1f) :
1813 SHIFT_IMM_LSL(0) : SHIFT_REG_ROR(args
[2]);
1816 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, args
[0], 0, args
[1], c
);
1819 case INDEX_op_rotl_i32
:
1820 if (const_args
[2]) {
1821 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, args
[0], 0, args
[1],
1822 ((0x20 - args
[2]) & 0x1f) ?
1823 SHIFT_IMM_ROR((0x20 - args
[2]) & 0x1f) :
1826 tcg_out_dat_imm(s
, COND_AL
, ARITH_RSB
, TCG_REG_TMP
, args
[2], 0x20);
1827 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, args
[0], 0, args
[1],
1828 SHIFT_REG_ROR(TCG_REG_TMP
));
1832 case INDEX_op_brcond_i32
:
1833 tcg_out_dat_rIN(s
, COND_AL
, ARITH_CMP
, ARITH_CMN
, 0,
1834 args
[0], args
[1], const_args
[1]);
1835 tcg_out_goto_label(s
, tcg_cond_to_arm_cond
[args
[2]],
1836 arg_label(args
[3]));
1838 case INDEX_op_brcond2_i32
:
1839 /* The resulting conditions are:
1840 * TCG_COND_EQ --> a0 == a2 && a1 == a3,
1841 * TCG_COND_NE --> (a0 != a2 && a1 == a3) || a1 != a3,
1842 * TCG_COND_LT(U) --> (a0 < a2 && a1 == a3) || a1 < a3,
1843 * TCG_COND_GE(U) --> (a0 >= a2 && a1 == a3) || (a1 >= a3 && a1 != a3),
1844 * TCG_COND_LE(U) --> (a0 <= a2 && a1 == a3) || (a1 <= a3 && a1 != a3),
1845 * TCG_COND_GT(U) --> (a0 > a2 && a1 == a3) || a1 > a3,
1847 tcg_out_dat_rIN(s
, COND_AL
, ARITH_CMP
, ARITH_CMN
, 0,
1848 args
[1], args
[3], const_args
[3]);
1849 tcg_out_dat_rIN(s
, COND_EQ
, ARITH_CMP
, ARITH_CMN
, 0,
1850 args
[0], args
[2], const_args
[2]);
1851 tcg_out_goto_label(s
, tcg_cond_to_arm_cond
[args
[4]],
1852 arg_label(args
[5]));
1854 case INDEX_op_setcond_i32
:
1855 tcg_out_dat_rIN(s
, COND_AL
, ARITH_CMP
, ARITH_CMN
, 0,
1856 args
[1], args
[2], const_args
[2]);
1857 tcg_out_dat_imm(s
, tcg_cond_to_arm_cond
[args
[3]],
1858 ARITH_MOV
, args
[0], 0, 1);
1859 tcg_out_dat_imm(s
, tcg_cond_to_arm_cond
[tcg_invert_cond(args
[3])],
1860 ARITH_MOV
, args
[0], 0, 0);
1862 case INDEX_op_setcond2_i32
:
1863 /* See brcond2_i32 comment */
1864 tcg_out_dat_rIN(s
, COND_AL
, ARITH_CMP
, ARITH_CMN
, 0,
1865 args
[2], args
[4], const_args
[4]);
1866 tcg_out_dat_rIN(s
, COND_EQ
, ARITH_CMP
, ARITH_CMN
, 0,
1867 args
[1], args
[3], const_args
[3]);
1868 tcg_out_dat_imm(s
, tcg_cond_to_arm_cond
[args
[5]],
1869 ARITH_MOV
, args
[0], 0, 1);
1870 tcg_out_dat_imm(s
, tcg_cond_to_arm_cond
[tcg_invert_cond(args
[5])],
1871 ARITH_MOV
, args
[0], 0, 0);
1874 case INDEX_op_qemu_ld_i32
:
1875 tcg_out_qemu_ld(s
, args
, 0);
1877 case INDEX_op_qemu_ld_i64
:
1878 tcg_out_qemu_ld(s
, args
, 1);
1880 case INDEX_op_qemu_st_i32
:
1881 tcg_out_qemu_st(s
, args
, 0);
1883 case INDEX_op_qemu_st_i64
:
1884 tcg_out_qemu_st(s
, args
, 1);
1887 case INDEX_op_bswap16_i32
:
1888 tcg_out_bswap16(s
, COND_AL
, args
[0], args
[1]);
1890 case INDEX_op_bswap32_i32
:
1891 tcg_out_bswap32(s
, COND_AL
, args
[0], args
[1]);
1894 case INDEX_op_ext8s_i32
:
1895 tcg_out_ext8s(s
, COND_AL
, args
[0], args
[1]);
1897 case INDEX_op_ext16s_i32
:
1898 tcg_out_ext16s(s
, COND_AL
, args
[0], args
[1]);
1900 case INDEX_op_ext16u_i32
:
1901 tcg_out_ext16u(s
, COND_AL
, args
[0], args
[1]);
1904 case INDEX_op_deposit_i32
:
1905 tcg_out_deposit(s
, COND_AL
, args
[0], args
[2],
1906 args
[3], args
[4], const_args
[2]);
1908 case INDEX_op_extract_i32
:
1909 tcg_out_extract(s
, COND_AL
, args
[0], args
[1], args
[2], args
[3]);
1911 case INDEX_op_sextract_i32
:
1912 tcg_out_sextract(s
, COND_AL
, args
[0], args
[1], args
[2], args
[3]);
1915 case INDEX_op_div_i32
:
1916 tcg_out_sdiv(s
, COND_AL
, args
[0], args
[1], args
[2]);
1918 case INDEX_op_divu_i32
:
1919 tcg_out_udiv(s
, COND_AL
, args
[0], args
[1], args
[2]);
1923 tcg_out_mb(s
, args
[0]);
1926 case INDEX_op_mov_i32
: /* Always emitted via tcg_out_mov. */
1927 case INDEX_op_movi_i32
: /* Always emitted via tcg_out_movi. */
1928 case INDEX_op_call
: /* Always emitted via tcg_out_call. */
1934 static const TCGTargetOpDef arm_op_defs
[] = {
1935 { INDEX_op_exit_tb
, { } },
1936 { INDEX_op_goto_tb
, { } },
1937 { INDEX_op_br
, { } },
1939 { INDEX_op_ld8u_i32
, { "r", "r" } },
1940 { INDEX_op_ld8s_i32
, { "r", "r" } },
1941 { INDEX_op_ld16u_i32
, { "r", "r" } },
1942 { INDEX_op_ld16s_i32
, { "r", "r" } },
1943 { INDEX_op_ld_i32
, { "r", "r" } },
1944 { INDEX_op_st8_i32
, { "r", "r" } },
1945 { INDEX_op_st16_i32
, { "r", "r" } },
1946 { INDEX_op_st_i32
, { "r", "r" } },
1948 /* TODO: "r", "r", "ri" */
1949 { INDEX_op_add_i32
, { "r", "r", "rIN" } },
1950 { INDEX_op_sub_i32
, { "r", "rI", "rIN" } },
1951 { INDEX_op_mul_i32
, { "r", "r", "r" } },
1952 { INDEX_op_mulu2_i32
, { "r", "r", "r", "r" } },
1953 { INDEX_op_muls2_i32
, { "r", "r", "r", "r" } },
1954 { INDEX_op_and_i32
, { "r", "r", "rIK" } },
1955 { INDEX_op_andc_i32
, { "r", "r", "rIK" } },
1956 { INDEX_op_or_i32
, { "r", "r", "rI" } },
1957 { INDEX_op_xor_i32
, { "r", "r", "rI" } },
1958 { INDEX_op_neg_i32
, { "r", "r" } },
1959 { INDEX_op_not_i32
, { "r", "r" } },
1961 { INDEX_op_shl_i32
, { "r", "r", "ri" } },
1962 { INDEX_op_shr_i32
, { "r", "r", "ri" } },
1963 { INDEX_op_sar_i32
, { "r", "r", "ri" } },
1964 { INDEX_op_rotl_i32
, { "r", "r", "ri" } },
1965 { INDEX_op_rotr_i32
, { "r", "r", "ri" } },
1967 { INDEX_op_brcond_i32
, { "r", "rIN" } },
1968 { INDEX_op_setcond_i32
, { "r", "r", "rIN" } },
1969 { INDEX_op_movcond_i32
, { "r", "r", "rIN", "rIK", "0" } },
1971 { INDEX_op_add2_i32
, { "r", "r", "r", "r", "rIN", "rIK" } },
1972 { INDEX_op_sub2_i32
, { "r", "r", "rI", "rI", "rIN", "rIK" } },
1973 { INDEX_op_brcond2_i32
, { "r", "r", "rIN", "rIN" } },
1974 { INDEX_op_setcond2_i32
, { "r", "r", "r", "rIN", "rIN" } },
1976 #if TARGET_LONG_BITS == 32
1977 { INDEX_op_qemu_ld_i32
, { "r", "l" } },
1978 { INDEX_op_qemu_ld_i64
, { "r", "r", "l" } },
1979 { INDEX_op_qemu_st_i32
, { "s", "s" } },
1980 { INDEX_op_qemu_st_i64
, { "s", "s", "s" } },
1982 { INDEX_op_qemu_ld_i32
, { "r", "l", "l" } },
1983 { INDEX_op_qemu_ld_i64
, { "r", "r", "l", "l" } },
1984 { INDEX_op_qemu_st_i32
, { "s", "s", "s" } },
1985 { INDEX_op_qemu_st_i64
, { "s", "s", "s", "s" } },
1988 { INDEX_op_bswap16_i32
, { "r", "r" } },
1989 { INDEX_op_bswap32_i32
, { "r", "r" } },
1991 { INDEX_op_ext8s_i32
, { "r", "r" } },
1992 { INDEX_op_ext16s_i32
, { "r", "r" } },
1993 { INDEX_op_ext16u_i32
, { "r", "r" } },
1995 { INDEX_op_deposit_i32
, { "r", "0", "rZ" } },
1996 { INDEX_op_extract_i32
, { "r", "r" } },
1997 { INDEX_op_sextract_i32
, { "r", "r" } },
1999 { INDEX_op_div_i32
, { "r", "r", "r" } },
2000 { INDEX_op_divu_i32
, { "r", "r", "r" } },
2002 { INDEX_op_mb
, { } },
2006 static const TCGTargetOpDef
*tcg_target_op_def(TCGOpcode op
)
2008 int i
, n
= ARRAY_SIZE(arm_op_defs
);
2010 for (i
= 0; i
< n
; ++i
) {
2011 if (arm_op_defs
[i
].op
== op
) {
2012 return &arm_op_defs
[i
];
2018 static void tcg_target_init(TCGContext
*s
)
2020 /* Only probe for the platform and capabilities if we havn't already
2021 determined maximum values at compile time. */
2022 #ifndef use_idiv_instructions
2024 unsigned long hwcap
= qemu_getauxval(AT_HWCAP
);
2025 use_idiv_instructions
= (hwcap
& HWCAP_ARM_IDIVA
) != 0;
2028 if (__ARM_ARCH
< 7) {
2029 const char *pl
= (const char *)qemu_getauxval(AT_PLATFORM
);
2030 if (pl
!= NULL
&& pl
[0] == 'v' && pl
[1] >= '4' && pl
[1] <= '9') {
2031 arm_arch
= pl
[1] - '0';
2035 tcg_regset_set32(tcg_target_available_regs
[TCG_TYPE_I32
], 0, 0xffff);
2036 tcg_regset_set32(tcg_target_call_clobber_regs
, 0,
2041 (1 << TCG_REG_R12
) |
2042 (1 << TCG_REG_R14
));
2044 tcg_regset_clear(s
->reserved_regs
);
2045 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_CALL_STACK
);
2046 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_TMP
);
2047 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_PC
);
2050 static inline void tcg_out_ld(TCGContext
*s
, TCGType type
, TCGReg arg
,
2051 TCGReg arg1
, intptr_t arg2
)
2053 tcg_out_ld32u(s
, COND_AL
, arg
, arg1
, arg2
);
2056 static inline void tcg_out_st(TCGContext
*s
, TCGType type
, TCGReg arg
,
2057 TCGReg arg1
, intptr_t arg2
)
2059 tcg_out_st32(s
, COND_AL
, arg
, arg1
, arg2
);
2062 static inline bool tcg_out_sti(TCGContext
*s
, TCGType type
, TCGArg val
,
2063 TCGReg base
, intptr_t ofs
)
2068 static inline void tcg_out_mov(TCGContext
*s
, TCGType type
,
2069 TCGReg ret
, TCGReg arg
)
2071 tcg_out_dat_reg(s
, COND_AL
, ARITH_MOV
, ret
, 0, arg
, SHIFT_IMM_LSL(0));
2074 static inline void tcg_out_movi(TCGContext
*s
, TCGType type
,
2075 TCGReg ret
, tcg_target_long arg
)
2077 tcg_out_movi32(s
, COND_AL
, ret
, arg
);
2080 /* Compute frame size via macros, to share between tcg_target_qemu_prologue
2081 and tcg_register_jit. */
2083 #define PUSH_SIZE ((11 - 4 + 1 + 1) * sizeof(tcg_target_long))
2085 #define FRAME_SIZE \
2087 + TCG_STATIC_CALL_ARGS_SIZE \
2088 + CPU_TEMP_BUF_NLONGS * sizeof(long) \
2089 + TCG_TARGET_STACK_ALIGN - 1) \
2090 & -TCG_TARGET_STACK_ALIGN)
2092 static void tcg_target_qemu_prologue(TCGContext
*s
)
2096 /* Calling convention requires us to save r4-r11 and lr. */
2097 /* stmdb sp!, { r4 - r11, lr } */
2098 tcg_out32(s
, (COND_AL
<< 28) | 0x092d4ff0);
2100 /* Reserve callee argument and tcg temp space. */
2101 stack_addend
= FRAME_SIZE
- PUSH_SIZE
;
2103 tcg_out_dat_rI(s
, COND_AL
, ARITH_SUB
, TCG_REG_CALL_STACK
,
2104 TCG_REG_CALL_STACK
, stack_addend
, 1);
2105 tcg_set_frame(s
, TCG_REG_CALL_STACK
, TCG_STATIC_CALL_ARGS_SIZE
,
2106 CPU_TEMP_BUF_NLONGS
* sizeof(long));
2108 tcg_out_mov(s
, TCG_TYPE_PTR
, TCG_AREG0
, tcg_target_call_iarg_regs
[0]);
2110 tcg_out_bx(s
, COND_AL
, tcg_target_call_iarg_regs
[1]);
2111 tb_ret_addr
= s
->code_ptr
;
2113 /* Epilogue. We branch here via tb_ret_addr. */
2114 tcg_out_dat_rI(s
, COND_AL
, ARITH_ADD
, TCG_REG_CALL_STACK
,
2115 TCG_REG_CALL_STACK
, stack_addend
, 1);
2117 /* ldmia sp!, { r4 - r11, pc } */
2118 tcg_out32(s
, (COND_AL
<< 28) | 0x08bd8ff0);
2123 uint8_t fde_def_cfa
[4];
2124 uint8_t fde_reg_ofs
[18];
2127 #define ELF_HOST_MACHINE EM_ARM
2129 /* We're expecting a 2 byte uleb128 encoded value. */
2130 QEMU_BUILD_BUG_ON(FRAME_SIZE
>= (1 << 14));
2132 static const DebugFrame debug_frame
= {
2133 .h
.cie
.len
= sizeof(DebugFrameCIE
)-4, /* length after .len member */
2136 .h
.cie
.code_align
= 1,
2137 .h
.cie
.data_align
= 0x7c, /* sleb128 -4 */
2138 .h
.cie
.return_column
= 14,
2140 /* Total FDE size does not include the "len" member. */
2141 .h
.fde
.len
= sizeof(DebugFrame
) - offsetof(DebugFrame
, h
.fde
.cie_offset
),
2144 12, 13, /* DW_CFA_def_cfa sp, ... */
2145 (FRAME_SIZE
& 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2149 /* The following must match the stmdb in the prologue. */
2150 0x8e, 1, /* DW_CFA_offset, lr, -4 */
2151 0x8b, 2, /* DW_CFA_offset, r11, -8 */
2152 0x8a, 3, /* DW_CFA_offset, r10, -12 */
2153 0x89, 4, /* DW_CFA_offset, r9, -16 */
2154 0x88, 5, /* DW_CFA_offset, r8, -20 */
2155 0x87, 6, /* DW_CFA_offset, r7, -24 */
2156 0x86, 7, /* DW_CFA_offset, r6, -28 */
2157 0x85, 8, /* DW_CFA_offset, r5, -32 */
2158 0x84, 9, /* DW_CFA_offset, r4, -36 */
2162 void tcg_register_jit(void *buf
, size_t buf_size
)
2164 tcg_register_jit_int(buf
, buf_size
, &debug_frame
, sizeof(debug_frame
));