]> git.proxmox.com Git - mirror_qemu.git/blob - tcg/s390/tcg-target.inc.c
projects / mirror_qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
tcg/s390: Use constant pool for xori
[mirror_qemu.git] / tcg / s390 / tcg-target.inc.c
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2009 Ulrich Hecht <uli@suse.de>
5 * Copyright (c) 2009 Alexander Graf <agraf@suse.de>
6 * Copyright (c) 2010 Richard Henderson <rth@twiddle.net>
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27 /* We only support generating code for 64-bit mode. */
28 #if TCG_TARGET_REG_BITS != 64
29 #error "unsupported code generation mode"
30 #endif
31
32 #include "tcg-pool.inc.c"
33 #include "elf.h"
34
35 /* ??? The translation blocks produced by TCG are generally small enough to
36 be entirely reachable with a 16-bit displacement. Leaving the option for
37 a 32-bit displacement here Just In Case. */
38 #define USE_LONG_BRANCHES 0
39
40 #define TCG_CT_CONST_S16 0x100
41 #define TCG_CT_CONST_S32 0x200
42 #define TCG_CT_CONST_U31 0x400
43 #define TCG_CT_CONST_S33 0x800
44 #define TCG_CT_CONST_ZERO 0x1000
45
46 /* Several places within the instruction set 0 means "no register"
47 rather than TCG_REG_R0. */
48 #define TCG_REG_NONE 0
49
50 /* A scratch register that may be be used throughout the backend. */
51 #define TCG_TMP0 TCG_REG_R1
52
53 /* A scratch register that holds a pointer to the beginning of the TB.
54 We don't need this when we have pc-relative loads with the general
55 instructions extension facility. */
56 #define TCG_REG_TB TCG_REG_R12
57 #define USE_REG_TB (!(s390_facilities & FACILITY_GEN_INST_EXT))
58
59 #ifndef CONFIG_SOFTMMU
60 #define TCG_GUEST_BASE_REG TCG_REG_R13
61 #endif
62
63 /* All of the following instructions are prefixed with their instruction
64 format, and are defined as 8- or 16-bit quantities, even when the two
65 halves of the 16-bit quantity may appear 32 bits apart in the insn.
66 This makes it easy to copy the values from the tables in Appendix B. */
67 typedef enum S390Opcode {
68 RIL_AFI = 0xc209,
69 RIL_AGFI = 0xc208,
70 RIL_ALFI = 0xc20b,
71 RIL_ALGFI = 0xc20a,
72 RIL_BRASL = 0xc005,
73 RIL_BRCL = 0xc004,
74 RIL_CFI = 0xc20d,
75 RIL_CGFI = 0xc20c,
76 RIL_CLFI = 0xc20f,
77 RIL_CLGFI = 0xc20e,
78 RIL_IIHF = 0xc008,
79 RIL_IILF = 0xc009,
80 RIL_LARL = 0xc000,
81 RIL_LGFI = 0xc001,
82 RIL_LGRL = 0xc408,
83 RIL_LLIHF = 0xc00e,
84 RIL_LLILF = 0xc00f,
85 RIL_LRL = 0xc40d,
86 RIL_MSFI = 0xc201,
87 RIL_MSGFI = 0xc200,
88 RIL_NIHF = 0xc00a,
89 RIL_NILF = 0xc00b,
90 RIL_OIHF = 0xc00c,
91 RIL_OILF = 0xc00d,
92 RIL_SLFI = 0xc205,
93 RIL_SLGFI = 0xc204,
94 RIL_XIHF = 0xc006,
95 RIL_XILF = 0xc007,
96
97 RI_AGHI = 0xa70b,
98 RI_AHI = 0xa70a,
99 RI_BRC = 0xa704,
100 RI_IIHH = 0xa500,
101 RI_IIHL = 0xa501,
102 RI_IILH = 0xa502,
103 RI_IILL = 0xa503,
104 RI_LGHI = 0xa709,
105 RI_LLIHH = 0xa50c,
106 RI_LLIHL = 0xa50d,
107 RI_LLILH = 0xa50e,
108 RI_LLILL = 0xa50f,
109 RI_MGHI = 0xa70d,
110 RI_MHI = 0xa70c,
111 RI_NIHH = 0xa504,
112 RI_NIHL = 0xa505,
113 RI_NILH = 0xa506,
114 RI_NILL = 0xa507,
115 RI_OIHH = 0xa508,
116 RI_OIHL = 0xa509,
117 RI_OILH = 0xa50a,
118 RI_OILL = 0xa50b,
119
120 RIE_CGIJ = 0xec7c,
121 RIE_CGRJ = 0xec64,
122 RIE_CIJ = 0xec7e,
123 RIE_CLGRJ = 0xec65,
124 RIE_CLIJ = 0xec7f,
125 RIE_CLGIJ = 0xec7d,
126 RIE_CLRJ = 0xec77,
127 RIE_CRJ = 0xec76,
128 RIE_LOCGHI = 0xec46,
129 RIE_RISBG = 0xec55,
130
131 RRE_AGR = 0xb908,
132 RRE_ALGR = 0xb90a,
133 RRE_ALCR = 0xb998,
134 RRE_ALCGR = 0xb988,
135 RRE_CGR = 0xb920,
136 RRE_CLGR = 0xb921,
137 RRE_DLGR = 0xb987,
138 RRE_DLR = 0xb997,
139 RRE_DSGFR = 0xb91d,
140 RRE_DSGR = 0xb90d,
141 RRE_FLOGR = 0xb983,
142 RRE_LGBR = 0xb906,
143 RRE_LCGR = 0xb903,
144 RRE_LGFR = 0xb914,
145 RRE_LGHR = 0xb907,
146 RRE_LGR = 0xb904,
147 RRE_LLGCR = 0xb984,
148 RRE_LLGFR = 0xb916,
149 RRE_LLGHR = 0xb985,
150 RRE_LRVR = 0xb91f,
151 RRE_LRVGR = 0xb90f,
152 RRE_LTGR = 0xb902,
153 RRE_MLGR = 0xb986,
154 RRE_MSGR = 0xb90c,
155 RRE_MSR = 0xb252,
156 RRE_NGR = 0xb980,
157 RRE_OGR = 0xb981,
158 RRE_SGR = 0xb909,
159 RRE_SLGR = 0xb90b,
160 RRE_SLBR = 0xb999,
161 RRE_SLBGR = 0xb989,
162 RRE_XGR = 0xb982,
163
164 RRF_LOCR = 0xb9f2,
165 RRF_LOCGR = 0xb9e2,
166 RRF_NRK = 0xb9f4,
167 RRF_NGRK = 0xb9e4,
168 RRF_ORK = 0xb9f6,
169 RRF_OGRK = 0xb9e6,
170 RRF_SRK = 0xb9f9,
171 RRF_SGRK = 0xb9e9,
172 RRF_SLRK = 0xb9fb,
173 RRF_SLGRK = 0xb9eb,
174 RRF_XRK = 0xb9f7,
175 RRF_XGRK = 0xb9e7,
176
177 RR_AR = 0x1a,
178 RR_ALR = 0x1e,
179 RR_BASR = 0x0d,
180 RR_BCR = 0x07,
181 RR_CLR = 0x15,
182 RR_CR = 0x19,
183 RR_DR = 0x1d,
184 RR_LCR = 0x13,
185 RR_LR = 0x18,
186 RR_LTR = 0x12,
187 RR_NR = 0x14,
188 RR_OR = 0x16,
189 RR_SR = 0x1b,
190 RR_SLR = 0x1f,
191 RR_XR = 0x17,
192
193 RSY_RLL = 0xeb1d,
194 RSY_RLLG = 0xeb1c,
195 RSY_SLLG = 0xeb0d,
196 RSY_SLLK = 0xebdf,
197 RSY_SRAG = 0xeb0a,
198 RSY_SRAK = 0xebdc,
199 RSY_SRLG = 0xeb0c,
200 RSY_SRLK = 0xebde,
201
202 RS_SLL = 0x89,
203 RS_SRA = 0x8a,
204 RS_SRL = 0x88,
205
206 RXY_AG = 0xe308,
207 RXY_AY = 0xe35a,
208 RXY_CG = 0xe320,
209 RXY_CY = 0xe359,
210 RXY_LAY = 0xe371,
211 RXY_LB = 0xe376,
212 RXY_LG = 0xe304,
213 RXY_LGB = 0xe377,
214 RXY_LGF = 0xe314,
215 RXY_LGH = 0xe315,
216 RXY_LHY = 0xe378,
217 RXY_LLGC = 0xe390,
218 RXY_LLGF = 0xe316,
219 RXY_LLGH = 0xe391,
220 RXY_LMG = 0xeb04,
221 RXY_LRV = 0xe31e,
222 RXY_LRVG = 0xe30f,
223 RXY_LRVH = 0xe31f,
224 RXY_LY = 0xe358,
225 RXY_NG = 0xe380,
226 RXY_OG = 0xe381,
227 RXY_STCY = 0xe372,
228 RXY_STG = 0xe324,
229 RXY_STHY = 0xe370,
230 RXY_STMG = 0xeb24,
231 RXY_STRV = 0xe33e,
232 RXY_STRVG = 0xe32f,
233 RXY_STRVH = 0xe33f,
234 RXY_STY = 0xe350,
235 RXY_XG = 0xe382,
236
237 RX_A = 0x5a,
238 RX_C = 0x59,
239 RX_L = 0x58,
240 RX_LA = 0x41,
241 RX_LH = 0x48,
242 RX_ST = 0x50,
243 RX_STC = 0x42,
244 RX_STH = 0x40,
245
246 NOP = 0x0707,
247 } S390Opcode;
248
249 #ifdef CONFIG_DEBUG_TCG
250 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
251 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
252 "%r8", "%r9", "%r10" "%r11" "%r12" "%r13" "%r14" "%r15"
253 };
254 #endif
255
256 /* Since R6 is a potential argument register, choose it last of the
257 call-saved registers. Likewise prefer the call-clobbered registers
258 in reverse order to maximize the chance of avoiding the arguments. */
259 static const int tcg_target_reg_alloc_order[] = {
260 /* Call saved registers. */
261 TCG_REG_R13,
262 TCG_REG_R12,
263 TCG_REG_R11,
264 TCG_REG_R10,
265 TCG_REG_R9,
266 TCG_REG_R8,
267 TCG_REG_R7,
268 TCG_REG_R6,
269 /* Call clobbered registers. */
270 TCG_REG_R14,
271 TCG_REG_R0,
272 TCG_REG_R1,
273 /* Argument registers, in reverse order of allocation. */
274 TCG_REG_R5,
275 TCG_REG_R4,
276 TCG_REG_R3,
277 TCG_REG_R2,
278 };
279
280 static const int tcg_target_call_iarg_regs[] = {
281 TCG_REG_R2,
282 TCG_REG_R3,
283 TCG_REG_R4,
284 TCG_REG_R5,
285 TCG_REG_R6,
286 };
287
288 static const int tcg_target_call_oarg_regs[] = {
289 TCG_REG_R2,
290 };
291
292 #define S390_CC_EQ 8
293 #define S390_CC_LT 4
294 #define S390_CC_GT 2
295 #define S390_CC_OV 1
296 #define S390_CC_NE (S390_CC_LT | S390_CC_GT)
297 #define S390_CC_LE (S390_CC_LT | S390_CC_EQ)
298 #define S390_CC_GE (S390_CC_GT | S390_CC_EQ)
299 #define S390_CC_NEVER 0
300 #define S390_CC_ALWAYS 15
301
302 /* Condition codes that result from a COMPARE and COMPARE LOGICAL. */
303 static const uint8_t tcg_cond_to_s390_cond[] = {
304 [TCG_COND_EQ] = S390_CC_EQ,
305 [TCG_COND_NE] = S390_CC_NE,
306 [TCG_COND_LT] = S390_CC_LT,
307 [TCG_COND_LE] = S390_CC_LE,
308 [TCG_COND_GT] = S390_CC_GT,
309 [TCG_COND_GE] = S390_CC_GE,
310 [TCG_COND_LTU] = S390_CC_LT,
311 [TCG_COND_LEU] = S390_CC_LE,
312 [TCG_COND_GTU] = S390_CC_GT,
313 [TCG_COND_GEU] = S390_CC_GE,
314 };
315
316 /* Condition codes that result from a LOAD AND TEST. Here, we have no
317 unsigned instruction variation, however since the test is vs zero we
318 can re-map the outcomes appropriately. */
319 static const uint8_t tcg_cond_to_ltr_cond[] = {
320 [TCG_COND_EQ] = S390_CC_EQ,
321 [TCG_COND_NE] = S390_CC_NE,
322 [TCG_COND_LT] = S390_CC_LT,
323 [TCG_COND_LE] = S390_CC_LE,
324 [TCG_COND_GT] = S390_CC_GT,
325 [TCG_COND_GE] = S390_CC_GE,
326 [TCG_COND_LTU] = S390_CC_NEVER,
327 [TCG_COND_LEU] = S390_CC_EQ,
328 [TCG_COND_GTU] = S390_CC_NE,
329 [TCG_COND_GEU] = S390_CC_ALWAYS,
330 };
331
332 #ifdef CONFIG_SOFTMMU
333 static void * const qemu_ld_helpers[16] = {
334 [MO_UB] = helper_ret_ldub_mmu,
335 [MO_SB] = helper_ret_ldsb_mmu,
336 [MO_LEUW] = helper_le_lduw_mmu,
337 [MO_LESW] = helper_le_ldsw_mmu,
338 [MO_LEUL] = helper_le_ldul_mmu,
339 [MO_LESL] = helper_le_ldsl_mmu,
340 [MO_LEQ] = helper_le_ldq_mmu,
341 [MO_BEUW] = helper_be_lduw_mmu,
342 [MO_BESW] = helper_be_ldsw_mmu,
343 [MO_BEUL] = helper_be_ldul_mmu,
344 [MO_BESL] = helper_be_ldsl_mmu,
345 [MO_BEQ] = helper_be_ldq_mmu,
346 };
347
348 static void * const qemu_st_helpers[16] = {
349 [MO_UB] = helper_ret_stb_mmu,
350 [MO_LEUW] = helper_le_stw_mmu,
351 [MO_LEUL] = helper_le_stl_mmu,
352 [MO_LEQ] = helper_le_stq_mmu,
353 [MO_BEUW] = helper_be_stw_mmu,
354 [MO_BEUL] = helper_be_stl_mmu,
355 [MO_BEQ] = helper_be_stq_mmu,
356 };
357 #endif
358
359 static tcg_insn_unit *tb_ret_addr;
360 uint64_t s390_facilities;
361
362 static void patch_reloc(tcg_insn_unit *code_ptr, int type,
363 intptr_t value, intptr_t addend)
364 {
365 intptr_t pcrel2;
366 uint32_t old;
367
368 value += addend;
369 pcrel2 = (tcg_insn_unit *)value - code_ptr;
370
371 switch (type) {
372 case R_390_PC16DBL:
373 assert(pcrel2 == (int16_t)pcrel2);
374 tcg_patch16(code_ptr, pcrel2);
375 break;
376 case R_390_PC32DBL:
377 assert(pcrel2 == (int32_t)pcrel2);
378 tcg_patch32(code_ptr, pcrel2);
379 break;
380 case R_390_20:
381 assert(value == sextract64(value, 0, 20));
382 old = *(uint32_t *)code_ptr & 0xf00000ff;
383 old |= ((value & 0xfff) << 16) | ((value & 0xff000) >> 4);
384 tcg_patch32(code_ptr, old);
385 break;
386 default:
387 g_assert_not_reached();
388 }
389 }
390
391 /* parse target specific constraints */
392 static const char *target_parse_constraint(TCGArgConstraint *ct,
393 const char *ct_str, TCGType type)
394 {
395 switch (*ct_str++) {
396 case 'r': /* all registers */
397 ct->ct |= TCG_CT_REG;
398 tcg_regset_set32(ct->u.regs, 0, 0xffff);
399 break;
400 case 'L': /* qemu_ld/st constraint */
401 ct->ct |= TCG_CT_REG;
402 tcg_regset_set32(ct->u.regs, 0, 0xffff);
403 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R2);
404 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);
405 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
406 break;
407 case 'a': /* force R2 for division */
408 ct->ct |= TCG_CT_REG;
409 tcg_regset_clear(ct->u.regs);
410 tcg_regset_set_reg(ct->u.regs, TCG_REG_R2);
411 break;
412 case 'b': /* force R3 for division */
413 ct->ct |= TCG_CT_REG;
414 tcg_regset_clear(ct->u.regs);
415 tcg_regset_set_reg(ct->u.regs, TCG_REG_R3);
416 break;
417 case 'A':
418 ct->ct |= TCG_CT_CONST_S33;
419 break;
420 case 'I':
421 ct->ct |= TCG_CT_CONST_S16;
422 break;
423 case 'J':
424 ct->ct |= TCG_CT_CONST_S32;
425 break;
426 case 'C':
427 /* ??? We have no insight here into whether the comparison is
428 signed or unsigned. The COMPARE IMMEDIATE insn uses a 32-bit
429 signed immediate, and the COMPARE LOGICAL IMMEDIATE insn uses
430 a 32-bit unsigned immediate. If we were to use the (semi)
431 obvious "val == (int32_t)val" we would be enabling unsigned
432 comparisons vs very large numbers. The only solution is to
433 take the intersection of the ranges. */
434 /* ??? Another possible solution is to simply lie and allow all
435 constants here and force the out-of-range values into a temp
436 register in tgen_cmp when we have knowledge of the actual
437 comparison code in use. */
438 ct->ct |= TCG_CT_CONST_U31;
439 break;
440 case 'Z':
441 ct->ct |= TCG_CT_CONST_ZERO;
442 break;
443 default:
444 return NULL;
445 }
446 return ct_str;
447 }
448
449 /* Test if a constant matches the constraint. */
450 static int tcg_target_const_match(tcg_target_long val, TCGType type,
451 const TCGArgConstraint *arg_ct)
452 {
453 int ct = arg_ct->ct;
454
455 if (ct & TCG_CT_CONST) {
456 return 1;
457 }
458
459 if (type == TCG_TYPE_I32) {
460 val = (int32_t)val;
461 }
462
463 /* The following are mutually exclusive. */
464 if (ct & TCG_CT_CONST_S16) {
465 return val == (int16_t)val;
466 } else if (ct & TCG_CT_CONST_S32) {
467 return val == (int32_t)val;
468 } else if (ct & TCG_CT_CONST_S33) {
469 return val >= -0xffffffffll && val <= 0xffffffffll;
470 } else if (ct & TCG_CT_CONST_U31) {
471 return val >= 0 && val <= 0x7fffffff;
472 } else if (ct & TCG_CT_CONST_ZERO) {
473 return val == 0;
474 }
475
476 return 0;
477 }
478
479 /* Emit instructions according to the given instruction format. */
480
481 static void tcg_out_insn_RR(TCGContext *s, S390Opcode op, TCGReg r1, TCGReg r2)
482 {
483 tcg_out16(s, (op << 8) | (r1 << 4) | r2);
484 }
485
486 static void tcg_out_insn_RRE(TCGContext *s, S390Opcode op,
487 TCGReg r1, TCGReg r2)
488 {
489 tcg_out32(s, (op << 16) | (r1 << 4) | r2);
490 }
491
492 static void tcg_out_insn_RRF(TCGContext *s, S390Opcode op,
493 TCGReg r1, TCGReg r2, int m3)
494 {
495 tcg_out32(s, (op << 16) | (m3 << 12) | (r1 << 4) | r2);
496 }
497
498 static void tcg_out_insn_RI(TCGContext *s, S390Opcode op, TCGReg r1, int i2)
499 {
500 tcg_out32(s, (op << 16) | (r1 << 20) | (i2 & 0xffff));
501 }
502
503 static void tcg_out_insn_RIE(TCGContext *s, S390Opcode op, TCGReg r1,
504 int i2, int m3)
505 {
506 tcg_out16(s, (op & 0xff00) | (r1 << 4) | m3);
507 tcg_out32(s, (i2 << 16) | (op & 0xff));
508 }
509
510 static void tcg_out_insn_RIL(TCGContext *s, S390Opcode op, TCGReg r1, int i2)
511 {
512 tcg_out16(s, op | (r1 << 4));
513 tcg_out32(s, i2);
514 }
515
516 static void tcg_out_insn_RS(TCGContext *s, S390Opcode op, TCGReg r1,
517 TCGReg b2, TCGReg r3, int disp)
518 {
519 tcg_out32(s, (op << 24) | (r1 << 20) | (r3 << 16) | (b2 << 12)
520 | (disp & 0xfff));
521 }
522
523 static void tcg_out_insn_RSY(TCGContext *s, S390Opcode op, TCGReg r1,
524 TCGReg b2, TCGReg r3, int disp)
525 {
526 tcg_out16(s, (op & 0xff00) | (r1 << 4) | r3);
527 tcg_out32(s, (op & 0xff) | (b2 << 28)
528 | ((disp & 0xfff) << 16) | ((disp & 0xff000) >> 4));
529 }
530
531 #define tcg_out_insn_RX tcg_out_insn_RS
532 #define tcg_out_insn_RXY tcg_out_insn_RSY
533
534 /* Emit an opcode with "type-checking" of the format. */
535 #define tcg_out_insn(S, FMT, OP, ...) \
536 glue(tcg_out_insn_,FMT)(S, glue(glue(FMT,_),OP), ## __VA_ARGS__)
537
538
539 /* emit 64-bit shifts */
540 static void tcg_out_sh64(TCGContext* s, S390Opcode op, TCGReg dest,
541 TCGReg src, TCGReg sh_reg, int sh_imm)
542 {
543 tcg_out_insn_RSY(s, op, dest, sh_reg, src, sh_imm);
544 }
545
546 /* emit 32-bit shifts */
547 static void tcg_out_sh32(TCGContext* s, S390Opcode op, TCGReg dest,
548 TCGReg sh_reg, int sh_imm)
549 {
550 tcg_out_insn_RS(s, op, dest, sh_reg, 0, sh_imm);
551 }
552
553 static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg src)
554 {
555 if (src != dst) {
556 if (type == TCG_TYPE_I32) {
557 tcg_out_insn(s, RR, LR, dst, src);
558 } else {
559 tcg_out_insn(s, RRE, LGR, dst, src);
560 }
561 }
562 }
563
564 static const S390Opcode lli_insns[4] = {
565 RI_LLILL, RI_LLILH, RI_LLIHL, RI_LLIHH
566 };
567 static const S390Opcode ii_insns[4] = {
568 RI_IILL, RI_IILH, RI_IIHL, RI_IIHH
569 };
570
571 static bool maybe_out_small_movi(TCGContext *s, TCGType type,
572 TCGReg ret, tcg_target_long sval)
573 {
574 tcg_target_ulong uval = sval;
575 int i;
576
577 if (type == TCG_TYPE_I32) {
578 uval = (uint32_t)sval;
579 sval = (int32_t)sval;
580 }
581
582 /* Try all 32-bit insns that can load it in one go. */
583 if (sval >= -0x8000 && sval < 0x8000) {
584 tcg_out_insn(s, RI, LGHI, ret, sval);
585 return true;
586 }
587
588 for (i = 0; i < 4; i++) {
589 tcg_target_long mask = 0xffffull << i*16;
590 if ((uval & mask) == uval) {
591 tcg_out_insn_RI(s, lli_insns[i], ret, uval >> i*16);
592 return true;
593 }
594 }
595
596 return false;
597 }
598
599 /* load a register with an immediate value */
600 static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
601 tcg_target_long sval, bool in_prologue)
602 {
603 tcg_target_ulong uval;
604
605 /* Try all 32-bit insns that can load it in one go. */
606 if (maybe_out_small_movi(s, type, ret, sval)) {
607 return;
608 }
609
610 uval = sval;
611 if (type == TCG_TYPE_I32) {
612 uval = (uint32_t)sval;
613 sval = (int32_t)sval;
614 }
615
616 /* Try all 48-bit insns that can load it in one go. */
617 if (s390_facilities & FACILITY_EXT_IMM) {
618 if (sval == (int32_t)sval) {
619 tcg_out_insn(s, RIL, LGFI, ret, sval);
620 return;
621 }
622 if (uval <= 0xffffffff) {
623 tcg_out_insn(s, RIL, LLILF, ret, uval);
624 return;
625 }
626 if ((uval & 0xffffffff) == 0) {
627 tcg_out_insn(s, RIL, LLIHF, ret, uval >> 32);
628 return;
629 }
630 }
631
632 /* Try for PC-relative address load. For odd addresses,
633 attempt to use an offset from the start of the TB. */
634 if ((sval & 1) == 0) {
635 ptrdiff_t off = tcg_pcrel_diff(s, (void *)sval) >> 1;
636 if (off == (int32_t)off) {
637 tcg_out_insn(s, RIL, LARL, ret, off);
638 return;
639 }
640 } else if (USE_REG_TB && !in_prologue) {
641 ptrdiff_t off = sval - (uintptr_t)s->code_gen_ptr;
642 if (off == sextract64(off, 0, 20)) {
643 /* This is certain to be an address within TB, and therefore
644 OFF will be negative; don't try RX_LA. */
645 tcg_out_insn(s, RXY, LAY, ret, TCG_REG_TB, TCG_REG_NONE, off);
646 return;
647 }
648 }
649
650 /* A 32-bit unsigned value can be loaded in 2 insns. And given
651 that LLILL, LLIHL, LLILF above did not succeed, we know that
652 both insns are required. */
653 if (uval <= 0xffffffff) {
654 tcg_out_insn(s, RI, LLILL, ret, uval);
655 tcg_out_insn(s, RI, IILH, ret, uval >> 16);
656 return;
657 }
658
659 /* When allowed, stuff it in the constant pool. */
660 if (!in_prologue) {
661 if (USE_REG_TB) {
662 tcg_out_insn(s, RXY, LG, ret, TCG_REG_TB, TCG_REG_NONE, 0);
663 new_pool_label(s, sval, R_390_20, s->code_ptr - 2,
664 -(intptr_t)s->code_gen_ptr);
665 } else {
666 tcg_out_insn(s, RIL, LGRL, ret, 0);
667 new_pool_label(s, sval, R_390_PC32DBL, s->code_ptr - 2, 2);
668 }
669 return;
670 }
671
672 /* What's left is for the prologue, loading GUEST_BASE, and because
673 it failed to match above, is known to be a full 64-bit quantity.
674 We could try more than this, but it probably wouldn't pay off. */
675 if (s390_facilities & FACILITY_EXT_IMM) {
676 tcg_out_insn(s, RIL, LLILF, ret, uval);
677 tcg_out_insn(s, RIL, IIHF, ret, uval >> 32);
678 } else {
679 const S390Opcode *insns = lli_insns;
680 int i;
681
682 for (i = 0; i < 4; i++) {
683 uint16_t part = uval >> (16 * i);
684 if (part) {
685 tcg_out_insn_RI(s, insns[i], ret, part);
686 insns = ii_insns;
687 }
688 }
689 }
690 }
691
692 static void tcg_out_movi(TCGContext *s, TCGType type,
693 TCGReg ret, tcg_target_long sval)
694 {
695 tcg_out_movi_int(s, type, ret, sval, false);
696 }
697
698 /* Emit a load/store type instruction. Inputs are:
699 DATA: The register to be loaded or stored.
700 BASE+OFS: The effective address.
701 OPC_RX: If the operation has an RX format opcode (e.g. STC), otherwise 0.
702 OPC_RXY: The RXY format opcode for the operation (e.g. STCY). */
703
704 static void tcg_out_mem(TCGContext *s, S390Opcode opc_rx, S390Opcode opc_rxy,
705 TCGReg data, TCGReg base, TCGReg index,
706 tcg_target_long ofs)
707 {
708 if (ofs < -0x80000 || ofs >= 0x80000) {
709 /* Combine the low 20 bits of the offset with the actual load insn;
710 the high 44 bits must come from an immediate load. */
711 tcg_target_long low = ((ofs & 0xfffff) ^ 0x80000) - 0x80000;
712 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - low);
713 ofs = low;
714
715 /* If we were already given an index register, add it in. */
716 if (index != TCG_REG_NONE) {
717 tcg_out_insn(s, RRE, AGR, TCG_TMP0, index);
718 }
719 index = TCG_TMP0;
720 }
721
722 if (opc_rx && ofs >= 0 && ofs < 0x1000) {
723 tcg_out_insn_RX(s, opc_rx, data, base, index, ofs);
724 } else {
725 tcg_out_insn_RXY(s, opc_rxy, data, base, index, ofs);
726 }
727 }
728
729
730 /* load data without address translation or endianness conversion */
731 static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg data,
732 TCGReg base, intptr_t ofs)
733 {
734 if (type == TCG_TYPE_I32) {
735 tcg_out_mem(s, RX_L, RXY_LY, data, base, TCG_REG_NONE, ofs);
736 } else {
737 tcg_out_mem(s, 0, RXY_LG, data, base, TCG_REG_NONE, ofs);
738 }
739 }
740
741 static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg data,
742 TCGReg base, intptr_t ofs)
743 {
744 if (type == TCG_TYPE_I32) {
745 tcg_out_mem(s, RX_ST, RXY_STY, data, base, TCG_REG_NONE, ofs);
746 } else {
747 tcg_out_mem(s, 0, RXY_STG, data, base, TCG_REG_NONE, ofs);
748 }
749 }
750
751 static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
752 TCGReg base, intptr_t ofs)
753 {
754 return false;
755 }
756
757 /* load data from an absolute host address */
758 static void tcg_out_ld_abs(TCGContext *s, TCGType type, TCGReg dest, void *abs)
759 {
760 intptr_t addr = (intptr_t)abs;
761
762 if ((s390_facilities & FACILITY_GEN_INST_EXT) && !(addr & 1)) {
763 ptrdiff_t disp = tcg_pcrel_diff(s, abs) >> 1;
764 if (disp == (int32_t)disp) {
765 if (type == TCG_TYPE_I32) {
766 tcg_out_insn(s, RIL, LRL, dest, disp);
767 } else {
768 tcg_out_insn(s, RIL, LGRL, dest, disp);
769 }
770 return;
771 }
772 }
773 if (USE_REG_TB) {
774 ptrdiff_t disp = abs - (void *)s->code_gen_ptr;
775 if (disp == sextract64(disp, 0, 20)) {
776 tcg_out_ld(s, type, dest, TCG_REG_TB, disp);
777 return;
778 }
779 }
780
781 tcg_out_movi(s, TCG_TYPE_PTR, dest, addr & ~0xffff);
782 tcg_out_ld(s, type, dest, dest, addr & 0xffff);
783 }
784
785 static inline void tcg_out_risbg(TCGContext *s, TCGReg dest, TCGReg src,
786 int msb, int lsb, int ofs, int z)
787 {
788 /* Format RIE-f */
789 tcg_out16(s, (RIE_RISBG & 0xff00) | (dest << 4) | src);
790 tcg_out16(s, (msb << 8) | (z << 7) | lsb);
791 tcg_out16(s, (ofs << 8) | (RIE_RISBG & 0xff));
792 }
793
794 static void tgen_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
795 {
796 if (s390_facilities & FACILITY_EXT_IMM) {
797 tcg_out_insn(s, RRE, LGBR, dest, src);
798 return;
799 }
800
801 if (type == TCG_TYPE_I32) {
802 if (dest == src) {
803 tcg_out_sh32(s, RS_SLL, dest, TCG_REG_NONE, 24);
804 } else {
805 tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 24);
806 }
807 tcg_out_sh32(s, RS_SRA, dest, TCG_REG_NONE, 24);
808 } else {
809 tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 56);
810 tcg_out_sh64(s, RSY_SRAG, dest, dest, TCG_REG_NONE, 56);
811 }
812 }
813
814 static void tgen_ext8u(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
815 {
816 if (s390_facilities & FACILITY_EXT_IMM) {
817 tcg_out_insn(s, RRE, LLGCR, dest, src);
818 return;
819 }
820
821 if (dest == src) {
822 tcg_out_movi(s, type, TCG_TMP0, 0xff);
823 src = TCG_TMP0;
824 } else {
825 tcg_out_movi(s, type, dest, 0xff);
826 }
827 if (type == TCG_TYPE_I32) {
828 tcg_out_insn(s, RR, NR, dest, src);
829 } else {
830 tcg_out_insn(s, RRE, NGR, dest, src);
831 }
832 }
833
834 static void tgen_ext16s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
835 {
836 if (s390_facilities & FACILITY_EXT_IMM) {
837 tcg_out_insn(s, RRE, LGHR, dest, src);
838 return;
839 }
840
841 if (type == TCG_TYPE_I32) {
842 if (dest == src) {
843 tcg_out_sh32(s, RS_SLL, dest, TCG_REG_NONE, 16);
844 } else {
845 tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 16);
846 }
847 tcg_out_sh32(s, RS_SRA, dest, TCG_REG_NONE, 16);
848 } else {
849 tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 48);
850 tcg_out_sh64(s, RSY_SRAG, dest, dest, TCG_REG_NONE, 48);
851 }
852 }
853
854 static void tgen_ext16u(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
855 {
856 if (s390_facilities & FACILITY_EXT_IMM) {
857 tcg_out_insn(s, RRE, LLGHR, dest, src);
858 return;
859 }
860
861 if (dest == src) {
862 tcg_out_movi(s, type, TCG_TMP0, 0xffff);
863 src = TCG_TMP0;
864 } else {
865 tcg_out_movi(s, type, dest, 0xffff);
866 }
867 if (type == TCG_TYPE_I32) {
868 tcg_out_insn(s, RR, NR, dest, src);
869 } else {
870 tcg_out_insn(s, RRE, NGR, dest, src);
871 }
872 }
873
874 static inline void tgen_ext32s(TCGContext *s, TCGReg dest, TCGReg src)
875 {
876 tcg_out_insn(s, RRE, LGFR, dest, src);
877 }
878
879 static inline void tgen_ext32u(TCGContext *s, TCGReg dest, TCGReg src)
880 {
881 tcg_out_insn(s, RRE, LLGFR, dest, src);
882 }
883
884 /* Accept bit patterns like these:
885 0....01....1
886 1....10....0
887 1..10..01..1
888 0..01..10..0
889 Copied from gcc sources. */
890 static inline bool risbg_mask(uint64_t c)
891 {
892 uint64_t lsb;
893 /* We don't change the number of transitions by inverting,
894 so make sure we start with the LSB zero. */
895 if (c & 1) {
896 c = ~c;
897 }
898 /* Reject all zeros or all ones. */
899 if (c == 0) {
900 return false;
901 }
902 /* Find the first transition. */
903 lsb = c & -c;
904 /* Invert to look for a second transition. */
905 c = ~c;
906 /* Erase the first transition. */
907 c &= -lsb;
908 /* Find the second transition, if any. */
909 lsb = c & -c;
910 /* Match if all the bits are 1's, or if c is zero. */
911 return c == -lsb;
912 }
913
914 static void tgen_andi_risbg(TCGContext *s, TCGReg out, TCGReg in, uint64_t val)
915 {
916 int msb, lsb;
917 if ((val & 0x8000000000000001ull) == 0x8000000000000001ull) {
918 /* Achieve wraparound by swapping msb and lsb. */
919 msb = 64 - ctz64(~val);
920 lsb = clz64(~val) - 1;
921 } else {
922 msb = clz64(val);
923 lsb = 63 - ctz64(val);
924 }
925 tcg_out_risbg(s, out, in, msb, lsb, 0, 1);
926 }
927
928 static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)
929 {
930 static const S390Opcode ni_insns[4] = {
931 RI_NILL, RI_NILH, RI_NIHL, RI_NIHH
932 };
933 static const S390Opcode nif_insns[2] = {
934 RIL_NILF, RIL_NIHF
935 };
936 uint64_t valid = (type == TCG_TYPE_I32 ? 0xffffffffull : -1ull);
937 int i;
938
939 /* Look for the zero-extensions. */
940 if ((val & valid) == 0xffffffff) {
941 tgen_ext32u(s, dest, dest);
942 return;
943 }
944 if (s390_facilities & FACILITY_EXT_IMM) {
945 if ((val & valid) == 0xff) {
946 tgen_ext8u(s, TCG_TYPE_I64, dest, dest);
947 return;
948 }
949 if ((val & valid) == 0xffff) {
950 tgen_ext16u(s, TCG_TYPE_I64, dest, dest);
951 return;
952 }
953 }
954
955 /* Try all 32-bit insns that can perform it in one go. */
956 for (i = 0; i < 4; i++) {
957 tcg_target_ulong mask = ~(0xffffull << i*16);
958 if (((val | ~valid) & mask) == mask) {
959 tcg_out_insn_RI(s, ni_insns[i], dest, val >> i*16);
960 return;
961 }
962 }
963
964 /* Try all 48-bit insns that can perform it in one go. */
965 if (s390_facilities & FACILITY_EXT_IMM) {
966 for (i = 0; i < 2; i++) {
967 tcg_target_ulong mask = ~(0xffffffffull << i*32);
968 if (((val | ~valid) & mask) == mask) {
969 tcg_out_insn_RIL(s, nif_insns[i], dest, val >> i*32);
970 return;
971 }
972 }
973 }
974 if ((s390_facilities & FACILITY_GEN_INST_EXT) && risbg_mask(val)) {
975 tgen_andi_risbg(s, dest, dest, val);
976 return;
977 }
978
979 /* Use the constant pool if USE_REG_TB, but not for small constants. */
980 if (USE_REG_TB) {
981 if (!maybe_out_small_movi(s, type, TCG_TMP0, val)) {
982 tcg_out_insn(s, RXY, NG, dest, TCG_REG_TB, TCG_REG_NONE, 0);
983 new_pool_label(s, val & valid, R_390_20, s->code_ptr - 2,
984 -(intptr_t)s->code_gen_ptr);
985 return;
986 }
987 } else {
988 tcg_out_movi(s, type, TCG_TMP0, val);
989 }
990 if (type == TCG_TYPE_I32) {
991 tcg_out_insn(s, RR, NR, dest, TCG_TMP0);
992 } else {
993 tcg_out_insn(s, RRE, NGR, dest, TCG_TMP0);
994 }
995 }
996
997 static void tgen_ori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)
998 {
999 static const S390Opcode oi_insns[4] = {
1000 RI_OILL, RI_OILH, RI_OIHL, RI_OIHH
1001 };
1002 static const S390Opcode oif_insns[2] = {
1003 RIL_OILF, RIL_OIHF
1004 };
1005
1006 int i;
1007
1008 /* Look for no-op. */
1009 if (unlikely(val == 0)) {
1010 return;
1011 }
1012
1013 /* Try all 32-bit insns that can perform it in one go. */
1014 for (i = 0; i < 4; i++) {
1015 tcg_target_ulong mask = (0xffffull << i*16);
1016 if ((val & mask) != 0 && (val & ~mask) == 0) {
1017 tcg_out_insn_RI(s, oi_insns[i], dest, val >> i*16);
1018 return;
1019 }
1020 }
1021
1022 /* Try all 48-bit insns that can perform it in one go. */
1023 if (s390_facilities & FACILITY_EXT_IMM) {
1024 for (i = 0; i < 2; i++) {
1025 tcg_target_ulong mask = (0xffffffffull << i*32);
1026 if ((val & mask) != 0 && (val & ~mask) == 0) {
1027 tcg_out_insn_RIL(s, oif_insns[i], dest, val >> i*32);
1028 return;
1029 }
1030 }
1031 }
1032
1033 /* Use the constant pool if USE_REG_TB, but not for small constants. */
1034 if (maybe_out_small_movi(s, type, TCG_TMP0, val)) {
1035 if (type == TCG_TYPE_I32) {
1036 tcg_out_insn(s, RR, OR, dest, TCG_TMP0);
1037 } else {
1038 tcg_out_insn(s, RRE, OGR, dest, TCG_TMP0);
1039 }
1040 } else if (USE_REG_TB) {
1041 tcg_out_insn(s, RXY, OG, dest, TCG_REG_TB, TCG_REG_NONE, 0);
1042 new_pool_label(s, val, R_390_20, s->code_ptr - 2,
1043 -(intptr_t)s->code_gen_ptr);
1044 } else {
1045 /* Perform the OR via sequential modifications to the high and
1046 low parts. Do this via recursion to handle 16-bit vs 32-bit
1047 masks in each half. */
1048 tcg_debug_assert(s390_facilities & FACILITY_EXT_IMM);
1049 tgen_ori(s, type, dest, val & 0x00000000ffffffffull);
1050 tgen_ori(s, type, dest, val & 0xffffffff00000000ull);
1051 }
1052 }
1053
1054 static void tgen_xori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)
1055 {
1056 /* Try all 48-bit insns that can perform it in one go. */
1057 if (s390_facilities & FACILITY_EXT_IMM) {
1058 if ((val & 0xffffffff00000000ull) == 0) {
1059 tcg_out_insn(s, RIL, XILF, dest, val);
1060 return;
1061 }
1062 if ((val & 0x00000000ffffffffull) == 0) {
1063 tcg_out_insn(s, RIL, XIHF, dest, val >> 32);
1064 return;
1065 }
1066 }
1067
1068 /* Use the constant pool if USE_REG_TB, but not for small constants. */
1069 if (maybe_out_small_movi(s, type, TCG_TMP0, val)) {
1070 if (type == TCG_TYPE_I32) {
1071 tcg_out_insn(s, RR, XR, dest, TCG_TMP0);
1072 } else {
1073 tcg_out_insn(s, RRE, XGR, dest, TCG_TMP0);
1074 }
1075 } else if (USE_REG_TB) {
1076 tcg_out_insn(s, RXY, XG, dest, TCG_REG_TB, TCG_REG_NONE, 0);
1077 new_pool_label(s, val, R_390_20, s->code_ptr - 2,
1078 -(intptr_t)s->code_gen_ptr);
1079 } else {
1080 /* Perform the xor by parts. */
1081 tcg_debug_assert(s390_facilities & FACILITY_EXT_IMM);
1082 if (val & 0xffffffff) {
1083 tcg_out_insn(s, RIL, XILF, dest, val);
1084 }
1085 if (val > 0xffffffff) {
1086 tcg_out_insn(s, RIL, XIHF, dest, val >> 32);
1087 }
1088 }
1089 }
1090
1091 static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1,
1092 TCGArg c2, bool c2const, bool need_carry)
1093 {
1094 bool is_unsigned = is_unsigned_cond(c);
1095 if (c2const) {
1096 if (c2 == 0) {
1097 if (!(is_unsigned && need_carry)) {
1098 if (type == TCG_TYPE_I32) {
1099 tcg_out_insn(s, RR, LTR, r1, r1);
1100 } else {
1101 tcg_out_insn(s, RRE, LTGR, r1, r1);
1102 }
1103 return tcg_cond_to_ltr_cond[c];
1104 }
1105 /* If we only got here because of load-and-test,
1106 and we couldn't use that, then we need to load
1107 the constant into a register. */
1108 if (!(s390_facilities & FACILITY_EXT_IMM)) {
1109 c2 = TCG_TMP0;
1110 tcg_out_movi(s, type, c2, 0);
1111 goto do_reg;
1112 }
1113 }
1114 if (is_unsigned) {
1115 if (type == TCG_TYPE_I32) {
1116 tcg_out_insn(s, RIL, CLFI, r1, c2);
1117 } else {
1118 tcg_out_insn(s, RIL, CLGFI, r1, c2);
1119 }
1120 } else {
1121 if (type == TCG_TYPE_I32) {
1122 tcg_out_insn(s, RIL, CFI, r1, c2);
1123 } else {
1124 tcg_out_insn(s, RIL, CGFI, r1, c2);
1125 }
1126 }
1127 } else {
1128 do_reg:
1129 if (is_unsigned) {
1130 if (type == TCG_TYPE_I32) {
1131 tcg_out_insn(s, RR, CLR, r1, c2);
1132 } else {
1133 tcg_out_insn(s, RRE, CLGR, r1, c2);
1134 }
1135 } else {
1136 if (type == TCG_TYPE_I32) {
1137 tcg_out_insn(s, RR, CR, r1, c2);
1138 } else {
1139 tcg_out_insn(s, RRE, CGR, r1, c2);
1140 }
1141 }
1142 }
1143 return tcg_cond_to_s390_cond[c];
1144 }
1145
1146 static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond,
1147 TCGReg dest, TCGReg c1, TCGArg c2, int c2const)
1148 {
1149 int cc;
1150 bool have_loc;
1151
1152 /* With LOC2, we can always emit the minimum 3 insns. */
1153 if (s390_facilities & FACILITY_LOAD_ON_COND2) {
1154 /* Emit: d = 0, d = (cc ? 1 : d). */
1155 cc = tgen_cmp(s, type, cond, c1, c2, c2const, false);
1156 tcg_out_movi(s, TCG_TYPE_I64, dest, 0);
1157 tcg_out_insn(s, RIE, LOCGHI, dest, 1, cc);
1158 return;
1159 }
1160
1161 have_loc = (s390_facilities & FACILITY_LOAD_ON_COND) != 0;
1162
1163 /* For HAVE_LOC, only the paths through GTU/GT/LEU/LE are smaller. */
1164 restart:
1165 switch (cond) {
1166 case TCG_COND_NE:
1167 /* X != 0 is X > 0. */
1168 if (c2const && c2 == 0) {
1169 cond = TCG_COND_GTU;
1170 } else {
1171 break;
1172 }
1173 /* fallthru */
1174
1175 case TCG_COND_GTU:
1176 case TCG_COND_GT:
1177 /* The result of a compare has CC=2 for GT and CC=3 unused.
1178 ADD LOGICAL WITH CARRY considers (CC & 2) the carry bit. */
1179 tgen_cmp(s, type, cond, c1, c2, c2const, true);
1180 tcg_out_movi(s, type, dest, 0);
1181 tcg_out_insn(s, RRE, ALCGR, dest, dest);
1182 return;
1183
1184 case TCG_COND_EQ:
1185 /* X == 0 is X <= 0. */
1186 if (c2const && c2 == 0) {
1187 cond = TCG_COND_LEU;
1188 } else {
1189 break;
1190 }
1191 /* fallthru */
1192
1193 case TCG_COND_LEU:
1194 case TCG_COND_LE:
1195 /* As above, but we're looking for borrow, or !carry.
1196 The second insn computes d - d - borrow, or -1 for true
1197 and 0 for false. So we must mask to 1 bit afterward. */
1198 tgen_cmp(s, type, cond, c1, c2, c2const, true);
1199 tcg_out_insn(s, RRE, SLBGR, dest, dest);
1200 tgen_andi(s, type, dest, 1);
1201 return;
1202
1203 case TCG_COND_GEU:
1204 case TCG_COND_LTU:
1205 case TCG_COND_LT:
1206 case TCG_COND_GE:
1207 /* Swap operands so that we can use LEU/GTU/GT/LE. */
1208 if (c2const) {
1209 if (have_loc) {
1210 break;
1211 }
1212 tcg_out_movi(s, type, TCG_TMP0, c2);
1213 c2 = c1;
1214 c2const = 0;
1215 c1 = TCG_TMP0;
1216 } else {
1217 TCGReg t = c1;
1218 c1 = c2;
1219 c2 = t;
1220 }
1221 cond = tcg_swap_cond(cond);
1222 goto restart;
1223
1224 default:
1225 g_assert_not_reached();
1226 }
1227
1228 cc = tgen_cmp(s, type, cond, c1, c2, c2const, false);
1229 if (have_loc) {
1230 /* Emit: d = 0, t = 1, d = (cc ? t : d). */
1231 tcg_out_movi(s, TCG_TYPE_I64, dest, 0);
1232 tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 1);
1233 tcg_out_insn(s, RRF, LOCGR, dest, TCG_TMP0, cc);
1234 } else {
1235 /* Emit: d = 1; if (cc) goto over; d = 0; over: */
1236 tcg_out_movi(s, type, dest, 1);
1237 tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1);
1238 tcg_out_movi(s, type, dest, 0);
1239 }
1240 }
1241
1242 static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg dest,
1243 TCGReg c1, TCGArg c2, int c2const,
1244 TCGArg v3, int v3const)
1245 {
1246 int cc;
1247 if (s390_facilities & FACILITY_LOAD_ON_COND) {
1248 cc = tgen_cmp(s, type, c, c1, c2, c2const, false);
1249 if (v3const) {
1250 tcg_out_insn(s, RIE, LOCGHI, dest, v3, cc);
1251 } else {
1252 tcg_out_insn(s, RRF, LOCGR, dest, v3, cc);
1253 }
1254 } else {
1255 c = tcg_invert_cond(c);
1256 cc = tgen_cmp(s, type, c, c1, c2, c2const, false);
1257
1258 /* Emit: if (cc) goto over; dest = r3; over: */
1259 tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1);
1260 tcg_out_insn(s, RRE, LGR, dest, v3);
1261 }
1262 }
1263
1264 static void tgen_clz(TCGContext *s, TCGReg dest, TCGReg a1,
1265 TCGArg a2, int a2const)
1266 {
1267 /* Since this sets both R and R+1, we have no choice but to store the
1268 result into R0, allowing R1 == TCG_TMP0 to be clobbered as well. */
1269 QEMU_BUILD_BUG_ON(TCG_TMP0 != TCG_REG_R1);
1270 tcg_out_insn(s, RRE, FLOGR, TCG_REG_R0, a1);
1271
1272 if (a2const && a2 == 64) {
1273 tcg_out_mov(s, TCG_TYPE_I64, dest, TCG_REG_R0);
1274 } else {
1275 if (a2const) {
1276 tcg_out_movi(s, TCG_TYPE_I64, dest, a2);
1277 } else {
1278 tcg_out_mov(s, TCG_TYPE_I64, dest, a2);
1279 }
1280 if (s390_facilities & FACILITY_LOAD_ON_COND) {
1281 /* Emit: if (one bit found) dest = r0. */
1282 tcg_out_insn(s, RRF, LOCGR, dest, TCG_REG_R0, 2);
1283 } else {
1284 /* Emit: if (no one bit found) goto over; dest = r0; over: */
1285 tcg_out_insn(s, RI, BRC, 8, (4 + 4) >> 1);
1286 tcg_out_insn(s, RRE, LGR, dest, TCG_REG_R0);
1287 }
1288 }
1289 }
1290
1291 static void tgen_deposit(TCGContext *s, TCGReg dest, TCGReg src,
1292 int ofs, int len, int z)
1293 {
1294 int lsb = (63 - ofs);
1295 int msb = lsb - (len - 1);
1296 tcg_out_risbg(s, dest, src, msb, lsb, ofs, z);
1297 }
1298
1299 static void tgen_extract(TCGContext *s, TCGReg dest, TCGReg src,
1300 int ofs, int len)
1301 {
1302 tcg_out_risbg(s, dest, src, 64 - len, 63, 64 - ofs, 1);
1303 }
1304
1305 static void tgen_gotoi(TCGContext *s, int cc, tcg_insn_unit *dest)
1306 {
1307 ptrdiff_t off = dest - s->code_ptr;
1308 if (off == (int16_t)off) {
1309 tcg_out_insn(s, RI, BRC, cc, off);
1310 } else if (off == (int32_t)off) {
1311 tcg_out_insn(s, RIL, BRCL, cc, off);
1312 } else {
1313 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)dest);
1314 tcg_out_insn(s, RR, BCR, cc, TCG_TMP0);
1315 }
1316 }
1317
1318 static void tgen_branch(TCGContext *s, int cc, TCGLabel *l)
1319 {
1320 if (l->has_value) {
1321 tgen_gotoi(s, cc, l->u.value_ptr);
1322 } else if (USE_LONG_BRANCHES) {
1323 tcg_out16(s, RIL_BRCL | (cc << 4));
1324 tcg_out_reloc(s, s->code_ptr, R_390_PC32DBL, l, 2);
1325 s->code_ptr += 2;
1326 } else {
1327 tcg_out16(s, RI_BRC | (cc << 4));
1328 tcg_out_reloc(s, s->code_ptr, R_390_PC16DBL, l, 2);
1329 s->code_ptr += 1;
1330 }
1331 }
1332
1333 static void tgen_compare_branch(TCGContext *s, S390Opcode opc, int cc,
1334 TCGReg r1, TCGReg r2, TCGLabel *l)
1335 {
1336 intptr_t off;
1337
1338 if (l->has_value) {
1339 off = l->u.value_ptr - s->code_ptr;
1340 } else {
1341 /* We need to keep the offset unchanged for retranslation. */
1342 off = s->code_ptr[1];
1343 tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2);
1344 }
1345
1346 tcg_out16(s, (opc & 0xff00) | (r1 << 4) | r2);
1347 tcg_out16(s, off);
1348 tcg_out16(s, cc << 12 | (opc & 0xff));
1349 }
1350
1351 static void tgen_compare_imm_branch(TCGContext *s, S390Opcode opc, int cc,
1352 TCGReg r1, int i2, TCGLabel *l)
1353 {
1354 tcg_target_long off;
1355
1356 if (l->has_value) {
1357 off = l->u.value_ptr - s->code_ptr;
1358 } else {
1359 /* We need to keep the offset unchanged for retranslation. */
1360 off = s->code_ptr[1];
1361 tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, 2);
1362 }
1363
1364 tcg_out16(s, (opc & 0xff00) | (r1 << 4) | cc);
1365 tcg_out16(s, off);
1366 tcg_out16(s, (i2 << 8) | (opc & 0xff));
1367 }
1368
1369 static void tgen_brcond(TCGContext *s, TCGType type, TCGCond c,
1370 TCGReg r1, TCGArg c2, int c2const, TCGLabel *l)
1371 {
1372 int cc;
1373
1374 if (s390_facilities & FACILITY_GEN_INST_EXT) {
1375 bool is_unsigned = is_unsigned_cond(c);
1376 bool in_range;
1377 S390Opcode opc;
1378
1379 cc = tcg_cond_to_s390_cond[c];
1380
1381 if (!c2const) {
1382 opc = (type == TCG_TYPE_I32
1383 ? (is_unsigned ? RIE_CLRJ : RIE_CRJ)
1384 : (is_unsigned ? RIE_CLGRJ : RIE_CGRJ));
1385 tgen_compare_branch(s, opc, cc, r1, c2, l);
1386 return;
1387 }
1388
1389 /* COMPARE IMMEDIATE AND BRANCH RELATIVE has an 8-bit immediate field.
1390 If the immediate we've been given does not fit that range, we'll
1391 fall back to separate compare and branch instructions using the
1392 larger comparison range afforded by COMPARE IMMEDIATE. */
1393 if (type == TCG_TYPE_I32) {
1394 if (is_unsigned) {
1395 opc = RIE_CLIJ;
1396 in_range = (uint32_t)c2 == (uint8_t)c2;
1397 } else {
1398 opc = RIE_CIJ;
1399 in_range = (int32_t)c2 == (int8_t)c2;
1400 }
1401 } else {
1402 if (is_unsigned) {
1403 opc = RIE_CLGIJ;
1404 in_range = (uint64_t)c2 == (uint8_t)c2;
1405 } else {
1406 opc = RIE_CGIJ;
1407 in_range = (int64_t)c2 == (int8_t)c2;
1408 }
1409 }
1410 if (in_range) {
1411 tgen_compare_imm_branch(s, opc, cc, r1, c2, l);
1412 return;
1413 }
1414 }
1415
1416 cc = tgen_cmp(s, type, c, r1, c2, c2const, false);
1417 tgen_branch(s, cc, l);
1418 }
1419
1420 static void tcg_out_call(TCGContext *s, tcg_insn_unit *dest)
1421 {
1422 ptrdiff_t off = dest - s->code_ptr;
1423 if (off == (int32_t)off) {
1424 tcg_out_insn(s, RIL, BRASL, TCG_REG_R14, off);
1425 } else {
1426 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)dest);
1427 tcg_out_insn(s, RR, BASR, TCG_REG_R14, TCG_TMP0);
1428 }
1429 }
1430
1431 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp opc, TCGReg data,
1432 TCGReg base, TCGReg index, int disp)
1433 {
1434 switch (opc & (MO_SSIZE | MO_BSWAP)) {
1435 case MO_UB:
1436 tcg_out_insn(s, RXY, LLGC, data, base, index, disp);
1437 break;
1438 case MO_SB:
1439 tcg_out_insn(s, RXY, LGB, data, base, index, disp);
1440 break;
1441
1442 case MO_UW | MO_BSWAP:
1443 /* swapped unsigned halfword load with upper bits zeroed */
1444 tcg_out_insn(s, RXY, LRVH, data, base, index, disp);
1445 tgen_ext16u(s, TCG_TYPE_I64, data, data);
1446 break;
1447 case MO_UW:
1448 tcg_out_insn(s, RXY, LLGH, data, base, index, disp);
1449 break;
1450
1451 case MO_SW | MO_BSWAP:
1452 /* swapped sign-extended halfword load */
1453 tcg_out_insn(s, RXY, LRVH, data, base, index, disp);
1454 tgen_ext16s(s, TCG_TYPE_I64, data, data);
1455 break;
1456 case MO_SW:
1457 tcg_out_insn(s, RXY, LGH, data, base, index, disp);
1458 break;
1459
1460 case MO_UL | MO_BSWAP:
1461 /* swapped unsigned int load with upper bits zeroed */
1462 tcg_out_insn(s, RXY, LRV, data, base, index, disp);
1463 tgen_ext32u(s, data, data);
1464 break;
1465 case MO_UL:
1466 tcg_out_insn(s, RXY, LLGF, data, base, index, disp);
1467 break;
1468
1469 case MO_SL | MO_BSWAP:
1470 /* swapped sign-extended int load */
1471 tcg_out_insn(s, RXY, LRV, data, base, index, disp);
1472 tgen_ext32s(s, data, data);
1473 break;
1474 case MO_SL:
1475 tcg_out_insn(s, RXY, LGF, data, base, index, disp);
1476 break;
1477
1478 case MO_Q | MO_BSWAP:
1479 tcg_out_insn(s, RXY, LRVG, data, base, index, disp);
1480 break;
1481 case MO_Q:
1482 tcg_out_insn(s, RXY, LG, data, base, index, disp);
1483 break;
1484
1485 default:
1486 tcg_abort();
1487 }
1488 }
1489
1490 static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp opc, TCGReg data,
1491 TCGReg base, TCGReg index, int disp)
1492 {
1493 switch (opc & (MO_SIZE | MO_BSWAP)) {
1494 case MO_UB:
1495 if (disp >= 0 && disp < 0x1000) {
1496 tcg_out_insn(s, RX, STC, data, base, index, disp);
1497 } else {
1498 tcg_out_insn(s, RXY, STCY, data, base, index, disp);
1499 }
1500 break;
1501
1502 case MO_UW | MO_BSWAP:
1503 tcg_out_insn(s, RXY, STRVH, data, base, index, disp);
1504 break;
1505 case MO_UW:
1506 if (disp >= 0 && disp < 0x1000) {
1507 tcg_out_insn(s, RX, STH, data, base, index, disp);
1508 } else {
1509 tcg_out_insn(s, RXY, STHY, data, base, index, disp);
1510 }
1511 break;
1512
1513 case MO_UL | MO_BSWAP:
1514 tcg_out_insn(s, RXY, STRV, data, base, index, disp);
1515 break;
1516 case MO_UL:
1517 if (disp >= 0 && disp < 0x1000) {
1518 tcg_out_insn(s, RX, ST, data, base, index, disp);
1519 } else {
1520 tcg_out_insn(s, RXY, STY, data, base, index, disp);
1521 }
1522 break;
1523
1524 case MO_Q | MO_BSWAP:
1525 tcg_out_insn(s, RXY, STRVG, data, base, index, disp);
1526 break;
1527 case MO_Q:
1528 tcg_out_insn(s, RXY, STG, data, base, index, disp);
1529 break;
1530
1531 default:
1532 tcg_abort();
1533 }
1534 }
1535
1536 #if defined(CONFIG_SOFTMMU)
1537 #include "tcg-ldst.inc.c"
1538
1539 /* We're expecting to use a 20-bit signed offset on the tlb memory ops.
1540 Using the offset of the second entry in the last tlb table ensures
1541 that we can index all of the elements of the first entry. */
1542 QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table[NB_MMU_MODES - 1][1])
1543 > 0x7ffff);
1544
1545 /* Load and compare a TLB entry, leaving the flags set. Loads the TLB
1546 addend into R2. Returns a register with the santitized guest address. */
1547 static TCGReg tcg_out_tlb_read(TCGContext* s, TCGReg addr_reg, TCGMemOp opc,
1548 int mem_index, bool is_ld)
1549 {
1550 unsigned s_bits = opc & MO_SIZE;
1551 unsigned a_bits = get_alignment_bits(opc);
1552 unsigned s_mask = (1 << s_bits) - 1;
1553 unsigned a_mask = (1 << a_bits) - 1;
1554 int ofs, a_off;
1555 uint64_t tlb_mask;
1556
1557 /* For aligned accesses, we check the first byte and include the alignment
1558 bits within the address. For unaligned access, we check that we don't
1559 cross pages using the address of the last byte of the access. */
1560 a_off = (a_bits >= s_bits ? 0 : s_mask - a_mask);
1561 tlb_mask = (uint64_t)TARGET_PAGE_MASK | a_mask;
1562
1563 if (s390_facilities & FACILITY_GEN_INST_EXT) {
1564 tcg_out_risbg(s, TCG_REG_R2, addr_reg,
1565 64 - CPU_TLB_BITS - CPU_TLB_ENTRY_BITS,
1566 63 - CPU_TLB_ENTRY_BITS,
1567 64 + CPU_TLB_ENTRY_BITS - TARGET_PAGE_BITS, 1);
1568 if (a_off) {
1569 tcg_out_insn(s, RX, LA, TCG_REG_R3, addr_reg, TCG_REG_NONE, a_off);
1570 tgen_andi(s, TCG_TYPE_TL, TCG_REG_R3, tlb_mask);
1571 } else {
1572 tgen_andi_risbg(s, TCG_REG_R3, addr_reg, tlb_mask);
1573 }
1574 } else {
1575 tcg_out_sh64(s, RSY_SRLG, TCG_REG_R2, addr_reg, TCG_REG_NONE,
1576 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
1577 tcg_out_insn(s, RX, LA, TCG_REG_R3, addr_reg, TCG_REG_NONE, a_off);
1578 tgen_andi(s, TCG_TYPE_I64, TCG_REG_R2,
1579 (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
1580 tgen_andi(s, TCG_TYPE_TL, TCG_REG_R3, tlb_mask);
1581 }
1582
1583 if (is_ld) {
1584 ofs = offsetof(CPUArchState, tlb_table[mem_index][0].addr_read);
1585 } else {
1586 ofs = offsetof(CPUArchState, tlb_table[mem_index][0].addr_write);
1587 }
1588 if (TARGET_LONG_BITS == 32) {
1589 tcg_out_mem(s, RX_C, RXY_CY, TCG_REG_R3, TCG_REG_R2, TCG_AREG0, ofs);
1590 } else {
1591 tcg_out_mem(s, 0, RXY_CG, TCG_REG_R3, TCG_REG_R2, TCG_AREG0, ofs);
1592 }
1593
1594 ofs = offsetof(CPUArchState, tlb_table[mem_index][0].addend);
1595 tcg_out_mem(s, 0, RXY_LG, TCG_REG_R2, TCG_REG_R2, TCG_AREG0, ofs);
1596
1597 if (TARGET_LONG_BITS == 32) {
1598 tgen_ext32u(s, TCG_REG_R3, addr_reg);
1599 return TCG_REG_R3;
1600 }
1601 return addr_reg;
1602 }
1603
1604 static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
1605 TCGReg data, TCGReg addr,
1606 tcg_insn_unit *raddr, tcg_insn_unit *label_ptr)
1607 {
1608 TCGLabelQemuLdst *label = new_ldst_label(s);
1609
1610 label->is_ld = is_ld;
1611 label->oi = oi;
1612 label->datalo_reg = data;
1613 label->addrlo_reg = addr;
1614 label->raddr = raddr;
1615 label->label_ptr[0] = label_ptr;
1616 }
1617
1618 static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
1619 {
1620 TCGReg addr_reg = lb->addrlo_reg;
1621 TCGReg data_reg = lb->datalo_reg;
1622 TCGMemOpIdx oi = lb->oi;
1623 TCGMemOp opc = get_memop(oi);
1624
1625 patch_reloc(lb->label_ptr[0], R_390_PC16DBL, (intptr_t)s->code_ptr, 2);
1626
1627 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0);
1628 if (TARGET_LONG_BITS == 64) {
1629 tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R3, addr_reg);
1630 }
1631 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R4, oi);
1632 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R5, (uintptr_t)lb->raddr);
1633 tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)]);
1634 tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_R2);
1635
1636 tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr);
1637 }
1638
1639 static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
1640 {
1641 TCGReg addr_reg = lb->addrlo_reg;
1642 TCGReg data_reg = lb->datalo_reg;
1643 TCGMemOpIdx oi = lb->oi;
1644 TCGMemOp opc = get_memop(oi);
1645
1646 patch_reloc(lb->label_ptr[0], R_390_PC16DBL, (intptr_t)s->code_ptr, 2);
1647
1648 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0);
1649 if (TARGET_LONG_BITS == 64) {
1650 tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R3, addr_reg);
1651 }
1652 switch (opc & MO_SIZE) {
1653 case MO_UB:
1654 tgen_ext8u(s, TCG_TYPE_I64, TCG_REG_R4, data_reg);
1655 break;
1656 case MO_UW:
1657 tgen_ext16u(s, TCG_TYPE_I64, TCG_REG_R4, data_reg);
1658 break;
1659 case MO_UL:
1660 tgen_ext32u(s, TCG_REG_R4, data_reg);
1661 break;
1662 case MO_Q:
1663 tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R4, data_reg);
1664 break;
1665 default:
1666 tcg_abort();
1667 }
1668 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R5, oi);
1669 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R6, (uintptr_t)lb->raddr);
1670 tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
1671
1672 tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr);
1673 }
1674 #else
1675 static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg,
1676 TCGReg *index_reg, tcg_target_long *disp)
1677 {
1678 if (TARGET_LONG_BITS == 32) {
1679 tgen_ext32u(s, TCG_TMP0, *addr_reg);
1680 *addr_reg = TCG_TMP0;
1681 }
1682 if (guest_base < 0x80000) {
1683 *index_reg = TCG_REG_NONE;
1684 *disp = guest_base;
1685 } else {
1686 *index_reg = TCG_GUEST_BASE_REG;
1687 *disp = 0;
1688 }
1689 }
1690 #endif /* CONFIG_SOFTMMU */
1691
1692 static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
1693 TCGMemOpIdx oi)
1694 {
1695 TCGMemOp opc = get_memop(oi);
1696 #ifdef CONFIG_SOFTMMU
1697 unsigned mem_index = get_mmuidx(oi);
1698 tcg_insn_unit *label_ptr;
1699 TCGReg base_reg;
1700
1701 base_reg = tcg_out_tlb_read(s, addr_reg, opc, mem_index, 1);
1702
1703 /* We need to keep the offset unchanged for retranslation. */
1704 tcg_out16(s, RI_BRC | (S390_CC_NE << 4));
1705 label_ptr = s->code_ptr;
1706 s->code_ptr += 1;
1707
1708 tcg_out_qemu_ld_direct(s, opc, data_reg, base_reg, TCG_REG_R2, 0);
1709
1710 add_qemu_ldst_label(s, 1, oi, data_reg, addr_reg, s->code_ptr, label_ptr);
1711 #else
1712 TCGReg index_reg;
1713 tcg_target_long disp;
1714
1715 tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp);
1716 tcg_out_qemu_ld_direct(s, opc, data_reg, addr_reg, index_reg, disp);
1717 #endif
1718 }
1719
1720 static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
1721 TCGMemOpIdx oi)
1722 {
1723 TCGMemOp opc = get_memop(oi);
1724 #ifdef CONFIG_SOFTMMU
1725 unsigned mem_index = get_mmuidx(oi);
1726 tcg_insn_unit *label_ptr;
1727 TCGReg base_reg;
1728
1729 base_reg = tcg_out_tlb_read(s, addr_reg, opc, mem_index, 0);
1730
1731 /* We need to keep the offset unchanged for retranslation. */
1732 tcg_out16(s, RI_BRC | (S390_CC_NE << 4));
1733 label_ptr = s->code_ptr;
1734 s->code_ptr += 1;
1735
1736 tcg_out_qemu_st_direct(s, opc, data_reg, base_reg, TCG_REG_R2, 0);
1737
1738 add_qemu_ldst_label(s, 0, oi, data_reg, addr_reg, s->code_ptr, label_ptr);
1739 #else
1740 TCGReg index_reg;
1741 tcg_target_long disp;
1742
1743 tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp);
1744 tcg_out_qemu_st_direct(s, opc, data_reg, addr_reg, index_reg, disp);
1745 #endif
1746 }
1747
1748 # define OP_32_64(x) \
1749 case glue(glue(INDEX_op_,x),_i32): \
1750 case glue(glue(INDEX_op_,x),_i64)
1751
1752 static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
1753 const TCGArg *args, const int *const_args)
1754 {
1755 S390Opcode op, op2;
1756 TCGArg a0, a1, a2;
1757
1758 switch (opc) {
1759 case INDEX_op_exit_tb:
1760 /* Reuse the zeroing that exists for goto_ptr. */
1761 a0 = args[0];
1762 if (a0 == 0) {
1763 tgen_gotoi(s, S390_CC_ALWAYS, s->code_gen_epilogue);
1764 } else {
1765 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, a0);
1766 tgen_gotoi(s, S390_CC_ALWAYS, tb_ret_addr);
1767 }
1768 break;
1769
1770 case INDEX_op_goto_tb:
1771 a0 = args[0];
1772 if (s->tb_jmp_insn_offset) {
1773 /* branch displacement must be aligned for atomic patching;
1774 * see if we need to add extra nop before branch
1775 */
1776 if (!QEMU_PTR_IS_ALIGNED(s->code_ptr + 1, 4)) {
1777 tcg_out16(s, NOP);
1778 }
1779 tcg_debug_assert(!USE_REG_TB);
1780 tcg_out16(s, RIL_BRCL | (S390_CC_ALWAYS << 4));
1781 s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s);
1782 s->code_ptr += 2;
1783 } else {
1784 /* load address stored at s->tb_jmp_target_addr + a0 */
1785 tcg_out_ld_abs(s, TCG_TYPE_PTR, TCG_REG_TB,
1786 s->tb_jmp_target_addr + a0);
1787 /* and go there */
1788 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_TB);
1789 }
1790 s->tb_jmp_reset_offset[a0] = tcg_current_code_size(s);
1791
1792 /* For the unlinked path of goto_tb, we need to reset
1793 TCG_REG_TB to the beginning of this TB. */
1794 if (USE_REG_TB) {
1795 int ofs = -tcg_current_code_size(s);
1796 assert(ofs == (int16_t)ofs);
1797 tcg_out_insn(s, RI, AGHI, TCG_REG_TB, ofs);
1798 }
1799 break;
1800
1801 case INDEX_op_goto_ptr:
1802 a0 = args[0];
1803 if (USE_REG_TB) {
1804 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0);
1805 }
1806 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, a0);
1807 break;
1808
1809 OP_32_64(ld8u):
1810 /* ??? LLC (RXY format) is only present with the extended-immediate
1811 facility, whereas LLGC is always present. */
1812 tcg_out_mem(s, 0, RXY_LLGC, args[0], args[1], TCG_REG_NONE, args[2]);
1813 break;
1814
1815 OP_32_64(ld8s):
1816 /* ??? LB is no smaller than LGB, so no point to using it. */
1817 tcg_out_mem(s, 0, RXY_LGB, args[0], args[1], TCG_REG_NONE, args[2]);
1818 break;
1819
1820 OP_32_64(ld16u):
1821 /* ??? LLH (RXY format) is only present with the extended-immediate
1822 facility, whereas LLGH is always present. */
1823 tcg_out_mem(s, 0, RXY_LLGH, args[0], args[1], TCG_REG_NONE, args[2]);
1824 break;
1825
1826 case INDEX_op_ld16s_i32:
1827 tcg_out_mem(s, RX_LH, RXY_LHY, args[0], args[1], TCG_REG_NONE, args[2]);
1828 break;
1829
1830 case INDEX_op_ld_i32:
1831 tcg_out_ld(s, TCG_TYPE_I32, args[0], args[1], args[2]);
1832 break;
1833
1834 OP_32_64(st8):
1835 tcg_out_mem(s, RX_STC, RXY_STCY, args[0], args[1],
1836 TCG_REG_NONE, args[2]);
1837 break;
1838
1839 OP_32_64(st16):
1840 tcg_out_mem(s, RX_STH, RXY_STHY, args[0], args[1],
1841 TCG_REG_NONE, args[2]);
1842 break;
1843
1844 case INDEX_op_st_i32:
1845 tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]);
1846 break;
1847
1848 case INDEX_op_add_i32:
1849 a0 = args[0], a1 = args[1], a2 = (int32_t)args[2];
1850 if (const_args[2]) {
1851 do_addi_32:
1852 if (a0 == a1) {
1853 if (a2 == (int16_t)a2) {
1854 tcg_out_insn(s, RI, AHI, a0, a2);
1855 break;
1856 }
1857 if (s390_facilities & FACILITY_EXT_IMM) {
1858 tcg_out_insn(s, RIL, AFI, a0, a2);
1859 break;
1860 }
1861 }
1862 tcg_out_mem(s, RX_LA, RXY_LAY, a0, a1, TCG_REG_NONE, a2);
1863 } else if (a0 == a1) {
1864 tcg_out_insn(s, RR, AR, a0, a2);
1865 } else {
1866 tcg_out_insn(s, RX, LA, a0, a1, a2, 0);
1867 }
1868 break;
1869 case INDEX_op_sub_i32:
1870 a0 = args[0], a1 = args[1], a2 = (int32_t)args[2];
1871 if (const_args[2]) {
1872 a2 = -a2;
1873 goto do_addi_32;
1874 } else if (a0 == a1) {
1875 tcg_out_insn(s, RR, SR, a0, a2);
1876 } else {
1877 tcg_out_insn(s, RRF, SRK, a0, a1, a2);
1878 }
1879 break;
1880
1881 case INDEX_op_and_i32:
1882 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];
1883 if (const_args[2]) {
1884 tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
1885 tgen_andi(s, TCG_TYPE_I32, a0, a2);
1886 } else if (a0 == a1) {
1887 tcg_out_insn(s, RR, NR, a0, a2);
1888 } else {
1889 tcg_out_insn(s, RRF, NRK, a0, a1, a2);
1890 }
1891 break;
1892 case INDEX_op_or_i32:
1893 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];
1894 if (const_args[2]) {
1895 tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
1896 tgen_ori(s, TCG_TYPE_I32, a0, a2);
1897 } else if (a0 == a1) {
1898 tcg_out_insn(s, RR, OR, a0, a2);
1899 } else {
1900 tcg_out_insn(s, RRF, ORK, a0, a1, a2);
1901 }
1902 break;
1903 case INDEX_op_xor_i32:
1904 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];
1905 if (const_args[2]) {
1906 tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
1907 tgen_xori(s, TCG_TYPE_I32, a0, a2);
1908 } else if (a0 == a1) {
1909 tcg_out_insn(s, RR, XR, args[0], args[2]);
1910 } else {
1911 tcg_out_insn(s, RRF, XRK, a0, a1, a2);
1912 }
1913 break;
1914
1915 case INDEX_op_neg_i32:
1916 tcg_out_insn(s, RR, LCR, args[0], args[1]);
1917 break;
1918
1919 case INDEX_op_mul_i32:
1920 if (const_args[2]) {
1921 if ((int32_t)args[2] == (int16_t)args[2]) {
1922 tcg_out_insn(s, RI, MHI, args[0], args[2]);
1923 } else {
1924 tcg_out_insn(s, RIL, MSFI, args[0], args[2]);
1925 }
1926 } else {
1927 tcg_out_insn(s, RRE, MSR, args[0], args[2]);
1928 }
1929 break;
1930
1931 case INDEX_op_div2_i32:
1932 tcg_out_insn(s, RR, DR, TCG_REG_R2, args[4]);
1933 break;
1934 case INDEX_op_divu2_i32:
1935 tcg_out_insn(s, RRE, DLR, TCG_REG_R2, args[4]);
1936 break;
1937
1938 case INDEX_op_shl_i32:
1939 op = RS_SLL;
1940 op2 = RSY_SLLK;
1941 do_shift32:
1942 a0 = args[0], a1 = args[1], a2 = (int32_t)args[2];
1943 if (a0 == a1) {
1944 if (const_args[2]) {
1945 tcg_out_sh32(s, op, a0, TCG_REG_NONE, a2);
1946 } else {
1947 tcg_out_sh32(s, op, a0, a2, 0);
1948 }
1949 } else {
1950 /* Using tcg_out_sh64 here for the format; it is a 32-bit shift. */
1951 if (const_args[2]) {
1952 tcg_out_sh64(s, op2, a0, a1, TCG_REG_NONE, a2);
1953 } else {
1954 tcg_out_sh64(s, op2, a0, a1, a2, 0);
1955 }
1956 }
1957 break;
1958 case INDEX_op_shr_i32:
1959 op = RS_SRL;
1960 op2 = RSY_SRLK;
1961 goto do_shift32;
1962 case INDEX_op_sar_i32:
1963 op = RS_SRA;
1964 op2 = RSY_SRAK;
1965 goto do_shift32;
1966
1967 case INDEX_op_rotl_i32:
1968 /* ??? Using tcg_out_sh64 here for the format; it is a 32-bit rol. */
1969 if (const_args[2]) {
1970 tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_REG_NONE, args[2]);
1971 } else {
1972 tcg_out_sh64(s, RSY_RLL, args[0], args[1], args[2], 0);
1973 }
1974 break;
1975 case INDEX_op_rotr_i32:
1976 if (const_args[2]) {
1977 tcg_out_sh64(s, RSY_RLL, args[0], args[1],
1978 TCG_REG_NONE, (32 - args[2]) & 31);
1979 } else {
1980 tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]);
1981 tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_TMP0, 0);
1982 }
1983 break;
1984
1985 case INDEX_op_ext8s_i32:
1986 tgen_ext8s(s, TCG_TYPE_I32, args[0], args[1]);
1987 break;
1988 case INDEX_op_ext16s_i32:
1989 tgen_ext16s(s, TCG_TYPE_I32, args[0], args[1]);
1990 break;
1991 case INDEX_op_ext8u_i32:
1992 tgen_ext8u(s, TCG_TYPE_I32, args[0], args[1]);
1993 break;
1994 case INDEX_op_ext16u_i32:
1995 tgen_ext16u(s, TCG_TYPE_I32, args[0], args[1]);
1996 break;
1997
1998 OP_32_64(bswap16):
1999 /* The TCG bswap definition requires bits 0-47 already be zero.
2000 Thus we don't need the G-type insns to implement bswap16_i64. */
2001 tcg_out_insn(s, RRE, LRVR, args[0], args[1]);
2002 tcg_out_sh32(s, RS_SRL, args[0], TCG_REG_NONE, 16);
2003 break;
2004 OP_32_64(bswap32):
2005 tcg_out_insn(s, RRE, LRVR, args[0], args[1]);
2006 break;
2007
2008 case INDEX_op_add2_i32:
2009 if (const_args[4]) {
2010 tcg_out_insn(s, RIL, ALFI, args[0], args[4]);
2011 } else {
2012 tcg_out_insn(s, RR, ALR, args[0], args[4]);
2013 }
2014 tcg_out_insn(s, RRE, ALCR, args[1], args[5]);
2015 break;
2016 case INDEX_op_sub2_i32:
2017 if (const_args[4]) {
2018 tcg_out_insn(s, RIL, SLFI, args[0], args[4]);
2019 } else {
2020 tcg_out_insn(s, RR, SLR, args[0], args[4]);
2021 }
2022 tcg_out_insn(s, RRE, SLBR, args[1], args[5]);
2023 break;
2024
2025 case INDEX_op_br:
2026 tgen_branch(s, S390_CC_ALWAYS, arg_label(args[0]));
2027 break;
2028
2029 case INDEX_op_brcond_i32:
2030 tgen_brcond(s, TCG_TYPE_I32, args[2], args[0],
2031 args[1], const_args[1], arg_label(args[3]));
2032 break;
2033 case INDEX_op_setcond_i32:
2034 tgen_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1],
2035 args[2], const_args[2]);
2036 break;
2037 case INDEX_op_movcond_i32:
2038 tgen_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1],
2039 args[2], const_args[2], args[3], const_args[3]);
2040 break;
2041
2042 case INDEX_op_qemu_ld_i32:
2043 /* ??? Technically we can use a non-extending instruction. */
2044 case INDEX_op_qemu_ld_i64:
2045 tcg_out_qemu_ld(s, args[0], args[1], args[2]);
2046 break;
2047 case INDEX_op_qemu_st_i32:
2048 case INDEX_op_qemu_st_i64:
2049 tcg_out_qemu_st(s, args[0], args[1], args[2]);
2050 break;
2051
2052 case INDEX_op_ld16s_i64:
2053 tcg_out_mem(s, 0, RXY_LGH, args[0], args[1], TCG_REG_NONE, args[2]);
2054 break;
2055 case INDEX_op_ld32u_i64:
2056 tcg_out_mem(s, 0, RXY_LLGF, args[0], args[1], TCG_REG_NONE, args[2]);
2057 break;
2058 case INDEX_op_ld32s_i64:
2059 tcg_out_mem(s, 0, RXY_LGF, args[0], args[1], TCG_REG_NONE, args[2]);
2060 break;
2061 case INDEX_op_ld_i64:
2062 tcg_out_ld(s, TCG_TYPE_I64, args[0], args[1], args[2]);
2063 break;
2064
2065 case INDEX_op_st32_i64:
2066 tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]);
2067 break;
2068 case INDEX_op_st_i64:
2069 tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]);
2070 break;
2071
2072 case INDEX_op_add_i64:
2073 a0 = args[0], a1 = args[1], a2 = args[2];
2074 if (const_args[2]) {
2075 do_addi_64:
2076 if (a0 == a1) {
2077 if (a2 == (int16_t)a2) {
2078 tcg_out_insn(s, RI, AGHI, a0, a2);
2079 break;
2080 }
2081 if (s390_facilities & FACILITY_EXT_IMM) {
2082 if (a2 == (int32_t)a2) {
2083 tcg_out_insn(s, RIL, AGFI, a0, a2);
2084 break;
2085 } else if (a2 == (uint32_t)a2) {
2086 tcg_out_insn(s, RIL, ALGFI, a0, a2);
2087 break;
2088 } else if (-a2 == (uint32_t)-a2) {
2089 tcg_out_insn(s, RIL, SLGFI, a0, -a2);
2090 break;
2091 }
2092 }
2093 }
2094 tcg_out_mem(s, RX_LA, RXY_LAY, a0, a1, TCG_REG_NONE, a2);
2095 } else if (a0 == a1) {
2096 tcg_out_insn(s, RRE, AGR, a0, a2);
2097 } else {
2098 tcg_out_insn(s, RX, LA, a0, a1, a2, 0);
2099 }
2100 break;
2101 case INDEX_op_sub_i64:
2102 a0 = args[0], a1 = args[1], a2 = args[2];
2103 if (const_args[2]) {
2104 a2 = -a2;
2105 goto do_addi_64;
2106 } else if (a0 == a1) {
2107 tcg_out_insn(s, RRE, SGR, a0, a2);
2108 } else {
2109 tcg_out_insn(s, RRF, SGRK, a0, a1, a2);
2110 }
2111 break;
2112
2113 case INDEX_op_and_i64:
2114 a0 = args[0], a1 = args[1], a2 = args[2];
2115 if (const_args[2]) {
2116 tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
2117 tgen_andi(s, TCG_TYPE_I64, args[0], args[2]);
2118 } else if (a0 == a1) {
2119 tcg_out_insn(s, RRE, NGR, args[0], args[2]);
2120 } else {
2121 tcg_out_insn(s, RRF, NGRK, a0, a1, a2);
2122 }
2123 break;
2124 case INDEX_op_or_i64:
2125 a0 = args[0], a1 = args[1], a2 = args[2];
2126 if (const_args[2]) {
2127 tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
2128 tgen_ori(s, TCG_TYPE_I64, a0, a2);
2129 } else if (a0 == a1) {
2130 tcg_out_insn(s, RRE, OGR, a0, a2);
2131 } else {
2132 tcg_out_insn(s, RRF, OGRK, a0, a1, a2);
2133 }
2134 break;
2135 case INDEX_op_xor_i64:
2136 a0 = args[0], a1 = args[1], a2 = args[2];
2137 if (const_args[2]) {
2138 tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
2139 tgen_xori(s, TCG_TYPE_I64, a0, a2);
2140 } else if (a0 == a1) {
2141 tcg_out_insn(s, RRE, XGR, a0, a2);
2142 } else {
2143 tcg_out_insn(s, RRF, XGRK, a0, a1, a2);
2144 }
2145 break;
2146
2147 case INDEX_op_neg_i64:
2148 tcg_out_insn(s, RRE, LCGR, args[0], args[1]);
2149 break;
2150 case INDEX_op_bswap64_i64:
2151 tcg_out_insn(s, RRE, LRVGR, args[0], args[1]);
2152 break;
2153
2154 case INDEX_op_mul_i64:
2155 if (const_args[2]) {
2156 if (args[2] == (int16_t)args[2]) {
2157 tcg_out_insn(s, RI, MGHI, args[0], args[2]);
2158 } else {
2159 tcg_out_insn(s, RIL, MSGFI, args[0], args[2]);
2160 }
2161 } else {
2162 tcg_out_insn(s, RRE, MSGR, args[0], args[2]);
2163 }
2164 break;
2165
2166 case INDEX_op_div2_i64:
2167 /* ??? We get an unnecessary sign-extension of the dividend
2168 into R3 with this definition, but as we do in fact always
2169 produce both quotient and remainder using INDEX_op_div_i64
2170 instead requires jumping through even more hoops. */
2171 tcg_out_insn(s, RRE, DSGR, TCG_REG_R2, args[4]);
2172 break;
2173 case INDEX_op_divu2_i64:
2174 tcg_out_insn(s, RRE, DLGR, TCG_REG_R2, args[4]);
2175 break;
2176 case INDEX_op_mulu2_i64:
2177 tcg_out_insn(s, RRE, MLGR, TCG_REG_R2, args[3]);
2178 break;
2179
2180 case INDEX_op_shl_i64:
2181 op = RSY_SLLG;
2182 do_shift64:
2183 if (const_args[2]) {
2184 tcg_out_sh64(s, op, args[0], args[1], TCG_REG_NONE, args[2]);
2185 } else {
2186 tcg_out_sh64(s, op, args[0], args[1], args[2], 0);
2187 }
2188 break;
2189 case INDEX_op_shr_i64:
2190 op = RSY_SRLG;
2191 goto do_shift64;
2192 case INDEX_op_sar_i64:
2193 op = RSY_SRAG;
2194 goto do_shift64;
2195
2196 case INDEX_op_rotl_i64:
2197 if (const_args[2]) {
2198 tcg_out_sh64(s, RSY_RLLG, args[0], args[1],
2199 TCG_REG_NONE, args[2]);
2200 } else {
2201 tcg_out_sh64(s, RSY_RLLG, args[0], args[1], args[2], 0);
2202 }
2203 break;
2204 case INDEX_op_rotr_i64:
2205 if (const_args[2]) {
2206 tcg_out_sh64(s, RSY_RLLG, args[0], args[1],
2207 TCG_REG_NONE, (64 - args[2]) & 63);
2208 } else {
2209 /* We can use the smaller 32-bit negate because only the
2210 low 6 bits are examined for the rotate. */
2211 tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]);
2212 tcg_out_sh64(s, RSY_RLLG, args[0], args[1], TCG_TMP0, 0);
2213 }
2214 break;
2215
2216 case INDEX_op_ext8s_i64:
2217 tgen_ext8s(s, TCG_TYPE_I64, args[0], args[1]);
2218 break;
2219 case INDEX_op_ext16s_i64:
2220 tgen_ext16s(s, TCG_TYPE_I64, args[0], args[1]);
2221 break;
2222 case INDEX_op_ext_i32_i64:
2223 case INDEX_op_ext32s_i64:
2224 tgen_ext32s(s, args[0], args[1]);
2225 break;
2226 case INDEX_op_ext8u_i64:
2227 tgen_ext8u(s, TCG_TYPE_I64, args[0], args[1]);
2228 break;
2229 case INDEX_op_ext16u_i64:
2230 tgen_ext16u(s, TCG_TYPE_I64, args[0], args[1]);
2231 break;
2232 case INDEX_op_extu_i32_i64:
2233 case INDEX_op_ext32u_i64:
2234 tgen_ext32u(s, args[0], args[1]);
2235 break;
2236
2237 case INDEX_op_add2_i64:
2238 if (const_args[4]) {
2239 if ((int64_t)args[4] >= 0) {
2240 tcg_out_insn(s, RIL, ALGFI, args[0], args[4]);
2241 } else {
2242 tcg_out_insn(s, RIL, SLGFI, args[0], -args[4]);
2243 }
2244 } else {
2245 tcg_out_insn(s, RRE, ALGR, args[0], args[4]);
2246 }
2247 tcg_out_insn(s, RRE, ALCGR, args[1], args[5]);
2248 break;
2249 case INDEX_op_sub2_i64:
2250 if (const_args[4]) {
2251 if ((int64_t)args[4] >= 0) {
2252 tcg_out_insn(s, RIL, SLGFI, args[0], args[4]);
2253 } else {
2254 tcg_out_insn(s, RIL, ALGFI, args[0], -args[4]);
2255 }
2256 } else {
2257 tcg_out_insn(s, RRE, SLGR, args[0], args[4]);
2258 }
2259 tcg_out_insn(s, RRE, SLBGR, args[1], args[5]);
2260 break;
2261
2262 case INDEX_op_brcond_i64:
2263 tgen_brcond(s, TCG_TYPE_I64, args[2], args[0],
2264 args[1], const_args[1], arg_label(args[3]));
2265 break;
2266 case INDEX_op_setcond_i64:
2267 tgen_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1],
2268 args[2], const_args[2]);
2269 break;
2270 case INDEX_op_movcond_i64:
2271 tgen_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1],
2272 args[2], const_args[2], args[3], const_args[3]);
2273 break;
2274
2275 OP_32_64(deposit):
2276 a0 = args[0], a1 = args[1], a2 = args[2];
2277 if (const_args[1]) {
2278 tgen_deposit(s, a0, a2, args[3], args[4], 1);
2279 } else {
2280 /* Since we can't support "0Z" as a constraint, we allow a1 in
2281 any register. Fix things up as if a matching constraint. */
2282 if (a0 != a1) {
2283 TCGType type = (opc == INDEX_op_deposit_i64);
2284 if (a0 == a2) {
2285 tcg_out_mov(s, type, TCG_TMP0, a2);
2286 a2 = TCG_TMP0;
2287 }
2288 tcg_out_mov(s, type, a0, a1);
2289 }
2290 tgen_deposit(s, a0, a2, args[3], args[4], 0);
2291 }
2292 break;
2293
2294 OP_32_64(extract):
2295 tgen_extract(s, args[0], args[1], args[2], args[3]);
2296 break;
2297
2298 case INDEX_op_clz_i64:
2299 tgen_clz(s, args[0], args[1], args[2], const_args[2]);
2300 break;
2301
2302 case INDEX_op_mb:
2303 /* The host memory model is quite strong, we simply need to
2304 serialize the instruction stream. */
2305 if (args[0] & TCG_MO_ST_LD) {
2306 tcg_out_insn(s, RR, BCR,
2307 s390_facilities & FACILITY_FAST_BCR_SER ? 14 : 15, 0);
2308 }
2309 break;
2310
2311 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
2312 case INDEX_op_mov_i64:
2313 case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
2314 case INDEX_op_movi_i64:
2315 case INDEX_op_call: /* Always emitted via tcg_out_call. */
2316 default:
2317 tcg_abort();
2318 }
2319 }
2320
2321 static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
2322 {
2323 static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
2324 static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
2325 static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
2326 static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } };
2327 static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } };
2328 static const TCGTargetOpDef r_rC = { .args_ct_str = { "r", "rC" } };
2329 static const TCGTargetOpDef r_rZ = { .args_ct_str = { "r", "rZ" } };
2330 static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
2331 static const TCGTargetOpDef r_0_ri = { .args_ct_str = { "r", "0", "ri" } };
2332 static const TCGTargetOpDef r_0_rI = { .args_ct_str = { "r", "0", "rI" } };
2333 static const TCGTargetOpDef r_0_rJ = { .args_ct_str = { "r", "0", "rJ" } };
2334 static const TCGTargetOpDef a2_r
2335 = { .args_ct_str = { "r", "r", "0", "1", "r", "r" } };
2336 static const TCGTargetOpDef a2_ri
2337 = { .args_ct_str = { "r", "r", "0", "1", "ri", "r" } };
2338 static const TCGTargetOpDef a2_rA
2339 = { .args_ct_str = { "r", "r", "0", "1", "rA", "r" } };
2340
2341 switch (op) {
2342 case INDEX_op_goto_ptr:
2343 return &r;
2344
2345 case INDEX_op_ld8u_i32:
2346 case INDEX_op_ld8u_i64:
2347 case INDEX_op_ld8s_i32:
2348 case INDEX_op_ld8s_i64:
2349 case INDEX_op_ld16u_i32:
2350 case INDEX_op_ld16u_i64:
2351 case INDEX_op_ld16s_i32:
2352 case INDEX_op_ld16s_i64:
2353 case INDEX_op_ld_i32:
2354 case INDEX_op_ld32u_i64:
2355 case INDEX_op_ld32s_i64:
2356 case INDEX_op_ld_i64:
2357 case INDEX_op_st8_i32:
2358 case INDEX_op_st8_i64:
2359 case INDEX_op_st16_i32:
2360 case INDEX_op_st16_i64:
2361 case INDEX_op_st_i32:
2362 case INDEX_op_st32_i64:
2363 case INDEX_op_st_i64:
2364 return &r_r;
2365
2366 case INDEX_op_add_i32:
2367 case INDEX_op_add_i64:
2368 return &r_r_ri;
2369 case INDEX_op_sub_i32:
2370 case INDEX_op_sub_i64:
2371 case INDEX_op_and_i32:
2372 case INDEX_op_and_i64:
2373 case INDEX_op_or_i32:
2374 case INDEX_op_or_i64:
2375 case INDEX_op_xor_i32:
2376 case INDEX_op_xor_i64:
2377 return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri);
2378
2379 case INDEX_op_mul_i32:
2380 /* If we have the general-instruction-extensions, then we have
2381 MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we
2382 have only MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */
2383 return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_ri : &r_0_rI);
2384 case INDEX_op_mul_i64:
2385 return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_rI);
2386
2387 case INDEX_op_shl_i32:
2388 case INDEX_op_shr_i32:
2389 case INDEX_op_sar_i32:
2390 return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri);
2391
2392 case INDEX_op_shl_i64:
2393 case INDEX_op_shr_i64:
2394 case INDEX_op_sar_i64:
2395 return &r_r_ri;
2396
2397 case INDEX_op_rotl_i32:
2398 case INDEX_op_rotl_i64:
2399 case INDEX_op_rotr_i32:
2400 case INDEX_op_rotr_i64:
2401 return &r_r_ri;
2402
2403 case INDEX_op_brcond_i32:
2404 /* Without EXT_IMM, only the LOAD AND TEST insn is available. */
2405 return (s390_facilities & FACILITY_EXT_IMM ? &r_ri : &r_rZ);
2406 case INDEX_op_brcond_i64:
2407 return (s390_facilities & FACILITY_EXT_IMM ? &r_rC : &r_rZ);
2408
2409 case INDEX_op_bswap16_i32:
2410 case INDEX_op_bswap16_i64:
2411 case INDEX_op_bswap32_i32:
2412 case INDEX_op_bswap32_i64:
2413 case INDEX_op_bswap64_i64:
2414 case INDEX_op_neg_i32:
2415 case INDEX_op_neg_i64:
2416 case INDEX_op_ext8s_i32:
2417 case INDEX_op_ext8s_i64:
2418 case INDEX_op_ext8u_i32:
2419 case INDEX_op_ext8u_i64:
2420 case INDEX_op_ext16s_i32:
2421 case INDEX_op_ext16s_i64:
2422 case INDEX_op_ext16u_i32:
2423 case INDEX_op_ext16u_i64:
2424 case INDEX_op_ext32s_i64:
2425 case INDEX_op_ext32u_i64:
2426 case INDEX_op_ext_i32_i64:
2427 case INDEX_op_extu_i32_i64:
2428 case INDEX_op_extract_i32:
2429 case INDEX_op_extract_i64:
2430 return &r_r;
2431
2432 case INDEX_op_clz_i64:
2433 return &r_r_ri;
2434
2435 case INDEX_op_qemu_ld_i32:
2436 case INDEX_op_qemu_ld_i64:
2437 return &r_L;
2438 case INDEX_op_qemu_st_i64:
2439 case INDEX_op_qemu_st_i32:
2440 return &L_L;
2441
2442 case INDEX_op_deposit_i32:
2443 case INDEX_op_deposit_i64:
2444 {
2445 static const TCGTargetOpDef dep
2446 = { .args_ct_str = { "r", "rZ", "r" } };
2447 return &dep;
2448 }
2449 case INDEX_op_setcond_i32:
2450 case INDEX_op_setcond_i64:
2451 {
2452 /* Without EXT_IMM, only the LOAD AND TEST insn is available. */
2453 static const TCGTargetOpDef setc_z
2454 = { .args_ct_str = { "r", "r", "rZ" } };
2455 static const TCGTargetOpDef setc_c
2456 = { .args_ct_str = { "r", "r", "rC" } };
2457 return (s390_facilities & FACILITY_EXT_IMM ? &setc_c : &setc_z);
2458 }
2459 case INDEX_op_movcond_i32:
2460 case INDEX_op_movcond_i64:
2461 {
2462 /* Without EXT_IMM, only the LOAD AND TEST insn is available. */
2463 static const TCGTargetOpDef movc_z
2464 = { .args_ct_str = { "r", "r", "rZ", "r", "0" } };
2465 static const TCGTargetOpDef movc_c
2466 = { .args_ct_str = { "r", "r", "rC", "r", "0" } };
2467 static const TCGTargetOpDef movc_l
2468 = { .args_ct_str = { "r", "r", "rC", "rI", "0" } };
2469 return (s390_facilities & FACILITY_EXT_IMM
2470 ? (s390_facilities & FACILITY_LOAD_ON_COND2
2471 ? &movc_l : &movc_c)
2472 : &movc_z);
2473 }
2474 case INDEX_op_div2_i32:
2475 case INDEX_op_div2_i64:
2476 case INDEX_op_divu2_i32:
2477 case INDEX_op_divu2_i64:
2478 {
2479 static const TCGTargetOpDef div2
2480 = { .args_ct_str = { "b", "a", "0", "1", "r" } };
2481 return &div2;
2482 }
2483 case INDEX_op_mulu2_i64:
2484 {
2485 static const TCGTargetOpDef mul2
2486 = { .args_ct_str = { "b", "a", "0", "r" } };
2487 return &mul2;
2488 }
2489
2490 case INDEX_op_add2_i32:
2491 case INDEX_op_sub2_i32:
2492 return (s390_facilities & FACILITY_EXT_IMM ? &a2_ri : &a2_r);
2493 case INDEX_op_add2_i64:
2494 case INDEX_op_sub2_i64:
2495 return (s390_facilities & FACILITY_EXT_IMM ? &a2_rA : &a2_r);
2496
2497 default:
2498 break;
2499 }
2500 return NULL;
2501 }
2502
2503 static void query_s390_facilities(void)
2504 {
2505 unsigned long hwcap = qemu_getauxval(AT_HWCAP);
2506
2507 /* Is STORE FACILITY LIST EXTENDED available? Honestly, I believe this
2508 is present on all 64-bit systems, but let's check for it anyway. */
2509 if (hwcap & HWCAP_S390_STFLE) {
2510 register int r0 __asm__("0");
2511 register void *r1 __asm__("1");
2512
2513 /* stfle 0(%r1) */
2514 r1 = &s390_facilities;
2515 asm volatile(".word 0xb2b0,0x1000"
2516 : "=r"(r0) : "0"(0), "r"(r1) : "memory", "cc");
2517 }
2518 }
2519
2520 static void tcg_target_init(TCGContext *s)
2521 {
2522 query_s390_facilities();
2523
2524 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
2525 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff);
2526
2527 tcg_regset_clear(tcg_target_call_clobber_regs);
2528 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);
2529 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1);
2530 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2);
2531 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3);
2532 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4);
2533 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5);
2534 /* The r6 register is technically call-saved, but it's also a parameter
2535 register, so it can get killed by setup for the qemu_st helper. */
2536 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6);
2537 /* The return register can be considered call-clobbered. */
2538 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14);
2539
2540 tcg_regset_clear(s->reserved_regs);
2541 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0);
2542 /* XXX many insns can't be used with R0, so we better avoid it for now */
2543 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0);
2544 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
2545 if (USE_REG_TB) {
2546 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB);
2547 }
2548 }
2549
2550 #define FRAME_SIZE ((int)(TCG_TARGET_CALL_STACK_OFFSET \
2551 + TCG_STATIC_CALL_ARGS_SIZE \
2552 + CPU_TEMP_BUF_NLONGS * sizeof(long)))
2553
2554 static void tcg_target_qemu_prologue(TCGContext *s)
2555 {
2556 /* stmg %r6,%r15,48(%r15) (save registers) */
2557 tcg_out_insn(s, RXY, STMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15, 48);
2558
2559 /* aghi %r15,-frame_size */
2560 tcg_out_insn(s, RI, AGHI, TCG_REG_R15, -FRAME_SIZE);
2561
2562 tcg_set_frame(s, TCG_REG_CALL_STACK,
2563 TCG_STATIC_CALL_ARGS_SIZE + TCG_TARGET_CALL_STACK_OFFSET,
2564 CPU_TEMP_BUF_NLONGS * sizeof(long));
2565
2566 #ifndef CONFIG_SOFTMMU
2567 if (guest_base >= 0x80000) {
2568 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true);
2569 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2570 }
2571 #endif
2572
2573 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
2574 if (USE_REG_TB) {
2575 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB,
2576 tcg_target_call_iarg_regs[1]);
2577 }
2578
2579 /* br %r3 (go to TB) */
2580 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, tcg_target_call_iarg_regs[1]);
2581
2582 /*
2583 * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
2584 * and fall through to the rest of the epilogue.
2585 */
2586 s->code_gen_epilogue = s->code_ptr;
2587 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, 0);
2588
2589 /* TB epilogue */
2590 tb_ret_addr = s->code_ptr;
2591
2592 /* lmg %r6,%r15,fs+48(%r15) (restore registers) */
2593 tcg_out_insn(s, RXY, LMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15,
2594 FRAME_SIZE + 48);
2595
2596 /* br %r14 (return) */
2597 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_R14);
2598 }
2599
2600 static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
2601 {
2602 memset(p, 0x07, count * sizeof(tcg_insn_unit));
2603 }
2604
2605 typedef struct {
2606 DebugFrameHeader h;
2607 uint8_t fde_def_cfa[4];
2608 uint8_t fde_reg_ofs[18];
2609 } DebugFrame;
2610
2611 /* We're expecting a 2 byte uleb128 encoded value. */
2612 QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
2613
2614 #define ELF_HOST_MACHINE EM_S390
2615
2616 static const DebugFrame debug_frame = {
2617 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
2618 .h.cie.id = -1,
2619 .h.cie.version = 1,
2620 .h.cie.code_align = 1,
2621 .h.cie.data_align = 8, /* sleb128 8 */
2622 .h.cie.return_column = TCG_REG_R14,
2623
2624 /* Total FDE size does not include the "len" member. */
2625 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
2626
2627 .fde_def_cfa = {
2628 12, TCG_REG_CALL_STACK, /* DW_CFA_def_cfa %r15, ... */
2629 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2630 (FRAME_SIZE >> 7)
2631 },
2632 .fde_reg_ofs = {
2633 0x86, 6, /* DW_CFA_offset, %r6, 48 */
2634 0x87, 7, /* DW_CFA_offset, %r7, 56 */
2635 0x88, 8, /* DW_CFA_offset, %r8, 64 */
2636 0x89, 9, /* DW_CFA_offset, %r92, 72 */
2637 0x8a, 10, /* DW_CFA_offset, %r10, 80 */
2638 0x8b, 11, /* DW_CFA_offset, %r11, 88 */
2639 0x8c, 12, /* DW_CFA_offset, %r12, 96 */
2640 0x8d, 13, /* DW_CFA_offset, %r13, 104 */
2641 0x8e, 14, /* DW_CFA_offset, %r14, 112 */
2642 }
2643 };
2644
2645 void tcg_register_jit(void *buf, size_t buf_size)
2646 {
2647 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
2648 }
QEMU mirror