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Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20170906' into staging
[mirror_qemu.git] / tcg / s390 / tcg-target.inc.c
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2009 Ulrich Hecht <uli@suse.de>
5 * Copyright (c) 2009 Alexander Graf <agraf@suse.de>
6 * Copyright (c) 2010 Richard Henderson <rth@twiddle.net>
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27 #include "tcg-be-ldst.h"
28
29 /* We only support generating code for 64-bit mode. */
30 #if TCG_TARGET_REG_BITS != 64
31 #error "unsupported code generation mode"
32 #endif
33
34 #include "elf.h"
35
36 /* ??? The translation blocks produced by TCG are generally small enough to
37 be entirely reachable with a 16-bit displacement. Leaving the option for
38 a 32-bit displacement here Just In Case. */
39 #define USE_LONG_BRANCHES 0
40
41 #define TCG_CT_CONST_S16 0x100
42 #define TCG_CT_CONST_S32 0x200
43 #define TCG_CT_CONST_NN16 0x400
44 #define TCG_CT_CONST_NN32 0x800
45 #define TCG_CT_CONST_U31 0x1000
46 #define TCG_CT_CONST_S33 0x2000
47 #define TCG_CT_CONST_ZERO 0x4000
48
49 /* Several places within the instruction set 0 means "no register"
50 rather than TCG_REG_R0. */
51 #define TCG_REG_NONE 0
52
53 /* A scratch register that may be be used throughout the backend. */
54 #define TCG_TMP0 TCG_REG_R1
55
56 #ifndef CONFIG_SOFTMMU
57 #define TCG_GUEST_BASE_REG TCG_REG_R13
58 #endif
59
60 /* All of the following instructions are prefixed with their instruction
61 format, and are defined as 8- or 16-bit quantities, even when the two
62 halves of the 16-bit quantity may appear 32 bits apart in the insn.
63 This makes it easy to copy the values from the tables in Appendix B. */
64 typedef enum S390Opcode {
65 RIL_AFI = 0xc209,
66 RIL_AGFI = 0xc208,
67 RIL_ALFI = 0xc20b,
68 RIL_ALGFI = 0xc20a,
69 RIL_BRASL = 0xc005,
70 RIL_BRCL = 0xc004,
71 RIL_CFI = 0xc20d,
72 RIL_CGFI = 0xc20c,
73 RIL_CLFI = 0xc20f,
74 RIL_CLGFI = 0xc20e,
75 RIL_IIHF = 0xc008,
76 RIL_IILF = 0xc009,
77 RIL_LARL = 0xc000,
78 RIL_LGFI = 0xc001,
79 RIL_LGRL = 0xc408,
80 RIL_LLIHF = 0xc00e,
81 RIL_LLILF = 0xc00f,
82 RIL_LRL = 0xc40d,
83 RIL_MSFI = 0xc201,
84 RIL_MSGFI = 0xc200,
85 RIL_NIHF = 0xc00a,
86 RIL_NILF = 0xc00b,
87 RIL_OIHF = 0xc00c,
88 RIL_OILF = 0xc00d,
89 RIL_SLFI = 0xc205,
90 RIL_SLGFI = 0xc204,
91 RIL_XIHF = 0xc006,
92 RIL_XILF = 0xc007,
93
94 RI_AGHI = 0xa70b,
95 RI_AHI = 0xa70a,
96 RI_BRC = 0xa704,
97 RI_IIHH = 0xa500,
98 RI_IIHL = 0xa501,
99 RI_IILH = 0xa502,
100 RI_IILL = 0xa503,
101 RI_LGHI = 0xa709,
102 RI_LLIHH = 0xa50c,
103 RI_LLIHL = 0xa50d,
104 RI_LLILH = 0xa50e,
105 RI_LLILL = 0xa50f,
106 RI_MGHI = 0xa70d,
107 RI_MHI = 0xa70c,
108 RI_NIHH = 0xa504,
109 RI_NIHL = 0xa505,
110 RI_NILH = 0xa506,
111 RI_NILL = 0xa507,
112 RI_OIHH = 0xa508,
113 RI_OIHL = 0xa509,
114 RI_OILH = 0xa50a,
115 RI_OILL = 0xa50b,
116
117 RIE_CGIJ = 0xec7c,
118 RIE_CGRJ = 0xec64,
119 RIE_CIJ = 0xec7e,
120 RIE_CLGRJ = 0xec65,
121 RIE_CLIJ = 0xec7f,
122 RIE_CLGIJ = 0xec7d,
123 RIE_CLRJ = 0xec77,
124 RIE_CRJ = 0xec76,
125 RIE_LOCGHI = 0xec46,
126 RIE_RISBG = 0xec55,
127
128 RRE_AGR = 0xb908,
129 RRE_ALGR = 0xb90a,
130 RRE_ALCR = 0xb998,
131 RRE_ALCGR = 0xb988,
132 RRE_CGR = 0xb920,
133 RRE_CLGR = 0xb921,
134 RRE_DLGR = 0xb987,
135 RRE_DLR = 0xb997,
136 RRE_DSGFR = 0xb91d,
137 RRE_DSGR = 0xb90d,
138 RRE_FLOGR = 0xb983,
139 RRE_LGBR = 0xb906,
140 RRE_LCGR = 0xb903,
141 RRE_LGFR = 0xb914,
142 RRE_LGHR = 0xb907,
143 RRE_LGR = 0xb904,
144 RRE_LLGCR = 0xb984,
145 RRE_LLGFR = 0xb916,
146 RRE_LLGHR = 0xb985,
147 RRE_LRVR = 0xb91f,
148 RRE_LRVGR = 0xb90f,
149 RRE_LTGR = 0xb902,
150 RRE_MLGR = 0xb986,
151 RRE_MSGR = 0xb90c,
152 RRE_MSR = 0xb252,
153 RRE_NGR = 0xb980,
154 RRE_OGR = 0xb981,
155 RRE_SGR = 0xb909,
156 RRE_SLGR = 0xb90b,
157 RRE_SLBR = 0xb999,
158 RRE_SLBGR = 0xb989,
159 RRE_XGR = 0xb982,
160
161 RRF_LOCR = 0xb9f2,
162 RRF_LOCGR = 0xb9e2,
163 RRF_NRK = 0xb9f4,
164 RRF_NGRK = 0xb9e4,
165 RRF_ORK = 0xb9f6,
166 RRF_OGRK = 0xb9e6,
167 RRF_SRK = 0xb9f9,
168 RRF_SGRK = 0xb9e9,
169 RRF_SLRK = 0xb9fb,
170 RRF_SLGRK = 0xb9eb,
171 RRF_XRK = 0xb9f7,
172 RRF_XGRK = 0xb9e7,
173
174 RR_AR = 0x1a,
175 RR_ALR = 0x1e,
176 RR_BASR = 0x0d,
177 RR_BCR = 0x07,
178 RR_CLR = 0x15,
179 RR_CR = 0x19,
180 RR_DR = 0x1d,
181 RR_LCR = 0x13,
182 RR_LR = 0x18,
183 RR_LTR = 0x12,
184 RR_NR = 0x14,
185 RR_OR = 0x16,
186 RR_SR = 0x1b,
187 RR_SLR = 0x1f,
188 RR_XR = 0x17,
189
190 RSY_RLL = 0xeb1d,
191 RSY_RLLG = 0xeb1c,
192 RSY_SLLG = 0xeb0d,
193 RSY_SLLK = 0xebdf,
194 RSY_SRAG = 0xeb0a,
195 RSY_SRAK = 0xebdc,
196 RSY_SRLG = 0xeb0c,
197 RSY_SRLK = 0xebde,
198
199 RS_SLL = 0x89,
200 RS_SRA = 0x8a,
201 RS_SRL = 0x88,
202
203 RXY_AG = 0xe308,
204 RXY_AY = 0xe35a,
205 RXY_CG = 0xe320,
206 RXY_CY = 0xe359,
207 RXY_LAY = 0xe371,
208 RXY_LB = 0xe376,
209 RXY_LG = 0xe304,
210 RXY_LGB = 0xe377,
211 RXY_LGF = 0xe314,
212 RXY_LGH = 0xe315,
213 RXY_LHY = 0xe378,
214 RXY_LLGC = 0xe390,
215 RXY_LLGF = 0xe316,
216 RXY_LLGH = 0xe391,
217 RXY_LMG = 0xeb04,
218 RXY_LRV = 0xe31e,
219 RXY_LRVG = 0xe30f,
220 RXY_LRVH = 0xe31f,
221 RXY_LY = 0xe358,
222 RXY_STCY = 0xe372,
223 RXY_STG = 0xe324,
224 RXY_STHY = 0xe370,
225 RXY_STMG = 0xeb24,
226 RXY_STRV = 0xe33e,
227 RXY_STRVG = 0xe32f,
228 RXY_STRVH = 0xe33f,
229 RXY_STY = 0xe350,
230
231 RX_A = 0x5a,
232 RX_C = 0x59,
233 RX_L = 0x58,
234 RX_LA = 0x41,
235 RX_LH = 0x48,
236 RX_ST = 0x50,
237 RX_STC = 0x42,
238 RX_STH = 0x40,
239
240 NOP = 0x0707,
241 } S390Opcode;
242
243 #ifdef CONFIG_DEBUG_TCG
244 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
245 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
246 "%r8", "%r9", "%r10" "%r11" "%r12" "%r13" "%r14" "%r15"
247 };
248 #endif
249
250 /* Since R6 is a potential argument register, choose it last of the
251 call-saved registers. Likewise prefer the call-clobbered registers
252 in reverse order to maximize the chance of avoiding the arguments. */
253 static const int tcg_target_reg_alloc_order[] = {
254 /* Call saved registers. */
255 TCG_REG_R13,
256 TCG_REG_R12,
257 TCG_REG_R11,
258 TCG_REG_R10,
259 TCG_REG_R9,
260 TCG_REG_R8,
261 TCG_REG_R7,
262 TCG_REG_R6,
263 /* Call clobbered registers. */
264 TCG_REG_R14,
265 TCG_REG_R0,
266 TCG_REG_R1,
267 /* Argument registers, in reverse order of allocation. */
268 TCG_REG_R5,
269 TCG_REG_R4,
270 TCG_REG_R3,
271 TCG_REG_R2,
272 };
273
274 static const int tcg_target_call_iarg_regs[] = {
275 TCG_REG_R2,
276 TCG_REG_R3,
277 TCG_REG_R4,
278 TCG_REG_R5,
279 TCG_REG_R6,
280 };
281
282 static const int tcg_target_call_oarg_regs[] = {
283 TCG_REG_R2,
284 };
285
286 #define S390_CC_EQ 8
287 #define S390_CC_LT 4
288 #define S390_CC_GT 2
289 #define S390_CC_OV 1
290 #define S390_CC_NE (S390_CC_LT | S390_CC_GT)
291 #define S390_CC_LE (S390_CC_LT | S390_CC_EQ)
292 #define S390_CC_GE (S390_CC_GT | S390_CC_EQ)
293 #define S390_CC_NEVER 0
294 #define S390_CC_ALWAYS 15
295
296 /* Condition codes that result from a COMPARE and COMPARE LOGICAL. */
297 static const uint8_t tcg_cond_to_s390_cond[] = {
298 [TCG_COND_EQ] = S390_CC_EQ,
299 [TCG_COND_NE] = S390_CC_NE,
300 [TCG_COND_LT] = S390_CC_LT,
301 [TCG_COND_LE] = S390_CC_LE,
302 [TCG_COND_GT] = S390_CC_GT,
303 [TCG_COND_GE] = S390_CC_GE,
304 [TCG_COND_LTU] = S390_CC_LT,
305 [TCG_COND_LEU] = S390_CC_LE,
306 [TCG_COND_GTU] = S390_CC_GT,
307 [TCG_COND_GEU] = S390_CC_GE,
308 };
309
310 /* Condition codes that result from a LOAD AND TEST. Here, we have no
311 unsigned instruction variation, however since the test is vs zero we
312 can re-map the outcomes appropriately. */
313 static const uint8_t tcg_cond_to_ltr_cond[] = {
314 [TCG_COND_EQ] = S390_CC_EQ,
315 [TCG_COND_NE] = S390_CC_NE,
316 [TCG_COND_LT] = S390_CC_LT,
317 [TCG_COND_LE] = S390_CC_LE,
318 [TCG_COND_GT] = S390_CC_GT,
319 [TCG_COND_GE] = S390_CC_GE,
320 [TCG_COND_LTU] = S390_CC_NEVER,
321 [TCG_COND_LEU] = S390_CC_EQ,
322 [TCG_COND_GTU] = S390_CC_NE,
323 [TCG_COND_GEU] = S390_CC_ALWAYS,
324 };
325
326 #ifdef CONFIG_SOFTMMU
327 static void * const qemu_ld_helpers[16] = {
328 [MO_UB] = helper_ret_ldub_mmu,
329 [MO_SB] = helper_ret_ldsb_mmu,
330 [MO_LEUW] = helper_le_lduw_mmu,
331 [MO_LESW] = helper_le_ldsw_mmu,
332 [MO_LEUL] = helper_le_ldul_mmu,
333 [MO_LESL] = helper_le_ldsl_mmu,
334 [MO_LEQ] = helper_le_ldq_mmu,
335 [MO_BEUW] = helper_be_lduw_mmu,
336 [MO_BESW] = helper_be_ldsw_mmu,
337 [MO_BEUL] = helper_be_ldul_mmu,
338 [MO_BESL] = helper_be_ldsl_mmu,
339 [MO_BEQ] = helper_be_ldq_mmu,
340 };
341
342 static void * const qemu_st_helpers[16] = {
343 [MO_UB] = helper_ret_stb_mmu,
344 [MO_LEUW] = helper_le_stw_mmu,
345 [MO_LEUL] = helper_le_stl_mmu,
346 [MO_LEQ] = helper_le_stq_mmu,
347 [MO_BEUW] = helper_be_stw_mmu,
348 [MO_BEUL] = helper_be_stl_mmu,
349 [MO_BEQ] = helper_be_stq_mmu,
350 };
351 #endif
352
353 static tcg_insn_unit *tb_ret_addr;
354 uint64_t s390_facilities;
355
356 static void patch_reloc(tcg_insn_unit *code_ptr, int type,
357 intptr_t value, intptr_t addend)
358 {
359 intptr_t pcrel2 = (tcg_insn_unit *)value - (code_ptr - 1);
360 tcg_debug_assert(addend == -2);
361
362 switch (type) {
363 case R_390_PC16DBL:
364 tcg_debug_assert(pcrel2 == (int16_t)pcrel2);
365 tcg_patch16(code_ptr, pcrel2);
366 break;
367 case R_390_PC32DBL:
368 tcg_debug_assert(pcrel2 == (int32_t)pcrel2);
369 tcg_patch32(code_ptr, pcrel2);
370 break;
371 default:
372 tcg_abort();
373 break;
374 }
375 }
376
377 /* parse target specific constraints */
378 static const char *target_parse_constraint(TCGArgConstraint *ct,
379 const char *ct_str, TCGType type)
380 {
381 switch (*ct_str++) {
382 case 'r': /* all registers */
383 ct->ct |= TCG_CT_REG;
384 tcg_regset_set32(ct->u.regs, 0, 0xffff);
385 break;
386 case 'L': /* qemu_ld/st constraint */
387 ct->ct |= TCG_CT_REG;
388 tcg_regset_set32(ct->u.regs, 0, 0xffff);
389 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R2);
390 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);
391 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
392 break;
393 case 'a': /* force R2 for division */
394 ct->ct |= TCG_CT_REG;
395 tcg_regset_clear(ct->u.regs);
396 tcg_regset_set_reg(ct->u.regs, TCG_REG_R2);
397 break;
398 case 'b': /* force R3 for division */
399 ct->ct |= TCG_CT_REG;
400 tcg_regset_clear(ct->u.regs);
401 tcg_regset_set_reg(ct->u.regs, TCG_REG_R3);
402 break;
403 case 'A':
404 ct->ct |= TCG_CT_CONST_S33;
405 break;
406 case 'I':
407 ct->ct |= TCG_CT_CONST_S16;
408 break;
409 case 'J':
410 ct->ct |= TCG_CT_CONST_S32;
411 break;
412 case 'N':
413 ct->ct |= TCG_CT_CONST_NN16;
414 break;
415 case 'M':
416 ct->ct |= TCG_CT_CONST_NN32;
417 break;
418 case 'C':
419 /* ??? We have no insight here into whether the comparison is
420 signed or unsigned. The COMPARE IMMEDIATE insn uses a 32-bit
421 signed immediate, and the COMPARE LOGICAL IMMEDIATE insn uses
422 a 32-bit unsigned immediate. If we were to use the (semi)
423 obvious "val == (int32_t)val" we would be enabling unsigned
424 comparisons vs very large numbers. The only solution is to
425 take the intersection of the ranges. */
426 /* ??? Another possible solution is to simply lie and allow all
427 constants here and force the out-of-range values into a temp
428 register in tgen_cmp when we have knowledge of the actual
429 comparison code in use. */
430 ct->ct |= TCG_CT_CONST_U31;
431 break;
432 case 'Z':
433 ct->ct |= TCG_CT_CONST_ZERO;
434 break;
435 default:
436 return NULL;
437 }
438 return ct_str;
439 }
440
441 /* Test if a constant matches the constraint. */
442 static int tcg_target_const_match(tcg_target_long val, TCGType type,
443 const TCGArgConstraint *arg_ct)
444 {
445 int ct = arg_ct->ct;
446
447 if (ct & TCG_CT_CONST) {
448 return 1;
449 }
450
451 if (type == TCG_TYPE_I32) {
452 val = (int32_t)val;
453 }
454
455 /* The following are mutually exclusive. */
456 if (ct & TCG_CT_CONST_S16) {
457 return val == (int16_t)val;
458 } else if (ct & TCG_CT_CONST_S32) {
459 return val == (int32_t)val;
460 } else if (ct & TCG_CT_CONST_S33) {
461 return val >= -0xffffffffll && val <= 0xffffffffll;
462 } else if (ct & TCG_CT_CONST_NN16) {
463 return !(val < 0 && val == (int16_t)val);
464 } else if (ct & TCG_CT_CONST_NN32) {
465 return !(val < 0 && val == (int32_t)val);
466 } else if (ct & TCG_CT_CONST_U31) {
467 return val >= 0 && val <= 0x7fffffff;
468 } else if (ct & TCG_CT_CONST_ZERO) {
469 return val == 0;
470 }
471
472 return 0;
473 }
474
475 /* Emit instructions according to the given instruction format. */
476
477 static void tcg_out_insn_RR(TCGContext *s, S390Opcode op, TCGReg r1, TCGReg r2)
478 {
479 tcg_out16(s, (op << 8) | (r1 << 4) | r2);
480 }
481
482 static void tcg_out_insn_RRE(TCGContext *s, S390Opcode op,
483 TCGReg r1, TCGReg r2)
484 {
485 tcg_out32(s, (op << 16) | (r1 << 4) | r2);
486 }
487
488 static void tcg_out_insn_RRF(TCGContext *s, S390Opcode op,
489 TCGReg r1, TCGReg r2, int m3)
490 {
491 tcg_out32(s, (op << 16) | (m3 << 12) | (r1 << 4) | r2);
492 }
493
494 static void tcg_out_insn_RI(TCGContext *s, S390Opcode op, TCGReg r1, int i2)
495 {
496 tcg_out32(s, (op << 16) | (r1 << 20) | (i2 & 0xffff));
497 }
498
499 static void tcg_out_insn_RIE(TCGContext *s, S390Opcode op, TCGReg r1,
500 int i2, int m3)
501 {
502 tcg_out16(s, (op & 0xff00) | (r1 << 4) | m3);
503 tcg_out32(s, (i2 << 16) | (op & 0xff));
504 }
505
506 static void tcg_out_insn_RIL(TCGContext *s, S390Opcode op, TCGReg r1, int i2)
507 {
508 tcg_out16(s, op | (r1 << 4));
509 tcg_out32(s, i2);
510 }
511
512 static void tcg_out_insn_RS(TCGContext *s, S390Opcode op, TCGReg r1,
513 TCGReg b2, TCGReg r3, int disp)
514 {
515 tcg_out32(s, (op << 24) | (r1 << 20) | (r3 << 16) | (b2 << 12)
516 | (disp & 0xfff));
517 }
518
519 static void tcg_out_insn_RSY(TCGContext *s, S390Opcode op, TCGReg r1,
520 TCGReg b2, TCGReg r3, int disp)
521 {
522 tcg_out16(s, (op & 0xff00) | (r1 << 4) | r3);
523 tcg_out32(s, (op & 0xff) | (b2 << 28)
524 | ((disp & 0xfff) << 16) | ((disp & 0xff000) >> 4));
525 }
526
527 #define tcg_out_insn_RX tcg_out_insn_RS
528 #define tcg_out_insn_RXY tcg_out_insn_RSY
529
530 /* Emit an opcode with "type-checking" of the format. */
531 #define tcg_out_insn(S, FMT, OP, ...) \
532 glue(tcg_out_insn_,FMT)(S, glue(glue(FMT,_),OP), ## __VA_ARGS__)
533
534
535 /* emit 64-bit shifts */
536 static void tcg_out_sh64(TCGContext* s, S390Opcode op, TCGReg dest,
537 TCGReg src, TCGReg sh_reg, int sh_imm)
538 {
539 tcg_out_insn_RSY(s, op, dest, sh_reg, src, sh_imm);
540 }
541
542 /* emit 32-bit shifts */
543 static void tcg_out_sh32(TCGContext* s, S390Opcode op, TCGReg dest,
544 TCGReg sh_reg, int sh_imm)
545 {
546 tcg_out_insn_RS(s, op, dest, sh_reg, 0, sh_imm);
547 }
548
549 static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg src)
550 {
551 if (src != dst) {
552 if (type == TCG_TYPE_I32) {
553 tcg_out_insn(s, RR, LR, dst, src);
554 } else {
555 tcg_out_insn(s, RRE, LGR, dst, src);
556 }
557 }
558 }
559
560 /* load a register with an immediate value */
561 static void tcg_out_movi(TCGContext *s, TCGType type,
562 TCGReg ret, tcg_target_long sval)
563 {
564 static const S390Opcode lli_insns[4] = {
565 RI_LLILL, RI_LLILH, RI_LLIHL, RI_LLIHH
566 };
567
568 tcg_target_ulong uval = sval;
569 int i;
570
571 if (type == TCG_TYPE_I32) {
572 uval = (uint32_t)sval;
573 sval = (int32_t)sval;
574 }
575
576 /* Try all 32-bit insns that can load it in one go. */
577 if (sval >= -0x8000 && sval < 0x8000) {
578 tcg_out_insn(s, RI, LGHI, ret, sval);
579 return;
580 }
581
582 for (i = 0; i < 4; i++) {
583 tcg_target_long mask = 0xffffull << i*16;
584 if ((uval & mask) == uval) {
585 tcg_out_insn_RI(s, lli_insns[i], ret, uval >> i*16);
586 return;
587 }
588 }
589
590 /* Try all 48-bit insns that can load it in one go. */
591 if (s390_facilities & FACILITY_EXT_IMM) {
592 if (sval == (int32_t)sval) {
593 tcg_out_insn(s, RIL, LGFI, ret, sval);
594 return;
595 }
596 if (uval <= 0xffffffff) {
597 tcg_out_insn(s, RIL, LLILF, ret, uval);
598 return;
599 }
600 if ((uval & 0xffffffff) == 0) {
601 tcg_out_insn(s, RIL, LLIHF, ret, uval >> 31 >> 1);
602 return;
603 }
604 }
605
606 /* Try for PC-relative address load. */
607 if ((sval & 1) == 0) {
608 ptrdiff_t off = tcg_pcrel_diff(s, (void *)sval) >> 1;
609 if (off == (int32_t)off) {
610 tcg_out_insn(s, RIL, LARL, ret, off);
611 return;
612 }
613 }
614
615 /* If extended immediates are not present, then we may have to issue
616 several instructions to load the low 32 bits. */
617 if (!(s390_facilities & FACILITY_EXT_IMM)) {
618 /* A 32-bit unsigned value can be loaded in 2 insns. And given
619 that the lli_insns loop above did not succeed, we know that
620 both insns are required. */
621 if (uval <= 0xffffffff) {
622 tcg_out_insn(s, RI, LLILL, ret, uval);
623 tcg_out_insn(s, RI, IILH, ret, uval >> 16);
624 return;
625 }
626
627 /* If all high bits are set, the value can be loaded in 2 or 3 insns.
628 We first want to make sure that all the high bits get set. With
629 luck the low 16-bits can be considered negative to perform that for
630 free, otherwise we load an explicit -1. */
631 if (sval >> 31 >> 1 == -1) {
632 if (uval & 0x8000) {
633 tcg_out_insn(s, RI, LGHI, ret, uval);
634 } else {
635 tcg_out_insn(s, RI, LGHI, ret, -1);
636 tcg_out_insn(s, RI, IILL, ret, uval);
637 }
638 tcg_out_insn(s, RI, IILH, ret, uval >> 16);
639 return;
640 }
641 }
642
643 /* If we get here, both the high and low parts have non-zero bits. */
644
645 /* Recurse to load the lower 32-bits. */
646 tcg_out_movi(s, TCG_TYPE_I64, ret, uval & 0xffffffff);
647
648 /* Insert data into the high 32-bits. */
649 uval = uval >> 31 >> 1;
650 if (s390_facilities & FACILITY_EXT_IMM) {
651 if (uval < 0x10000) {
652 tcg_out_insn(s, RI, IIHL, ret, uval);
653 } else if ((uval & 0xffff) == 0) {
654 tcg_out_insn(s, RI, IIHH, ret, uval >> 16);
655 } else {
656 tcg_out_insn(s, RIL, IIHF, ret, uval);
657 }
658 } else {
659 if (uval & 0xffff) {
660 tcg_out_insn(s, RI, IIHL, ret, uval);
661 }
662 if (uval & 0xffff0000) {
663 tcg_out_insn(s, RI, IIHH, ret, uval >> 16);
664 }
665 }
666 }
667
668
669 /* Emit a load/store type instruction. Inputs are:
670 DATA: The register to be loaded or stored.
671 BASE+OFS: The effective address.
672 OPC_RX: If the operation has an RX format opcode (e.g. STC), otherwise 0.
673 OPC_RXY: The RXY format opcode for the operation (e.g. STCY). */
674
675 static void tcg_out_mem(TCGContext *s, S390Opcode opc_rx, S390Opcode opc_rxy,
676 TCGReg data, TCGReg base, TCGReg index,
677 tcg_target_long ofs)
678 {
679 if (ofs < -0x80000 || ofs >= 0x80000) {
680 /* Combine the low 20 bits of the offset with the actual load insn;
681 the high 44 bits must come from an immediate load. */
682 tcg_target_long low = ((ofs & 0xfffff) ^ 0x80000) - 0x80000;
683 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - low);
684 ofs = low;
685
686 /* If we were already given an index register, add it in. */
687 if (index != TCG_REG_NONE) {
688 tcg_out_insn(s, RRE, AGR, TCG_TMP0, index);
689 }
690 index = TCG_TMP0;
691 }
692
693 if (opc_rx && ofs >= 0 && ofs < 0x1000) {
694 tcg_out_insn_RX(s, opc_rx, data, base, index, ofs);
695 } else {
696 tcg_out_insn_RXY(s, opc_rxy, data, base, index, ofs);
697 }
698 }
699
700
701 /* load data without address translation or endianness conversion */
702 static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg data,
703 TCGReg base, intptr_t ofs)
704 {
705 if (type == TCG_TYPE_I32) {
706 tcg_out_mem(s, RX_L, RXY_LY, data, base, TCG_REG_NONE, ofs);
707 } else {
708 tcg_out_mem(s, 0, RXY_LG, data, base, TCG_REG_NONE, ofs);
709 }
710 }
711
712 static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg data,
713 TCGReg base, intptr_t ofs)
714 {
715 if (type == TCG_TYPE_I32) {
716 tcg_out_mem(s, RX_ST, RXY_STY, data, base, TCG_REG_NONE, ofs);
717 } else {
718 tcg_out_mem(s, 0, RXY_STG, data, base, TCG_REG_NONE, ofs);
719 }
720 }
721
722 static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
723 TCGReg base, intptr_t ofs)
724 {
725 return false;
726 }
727
728 /* load data from an absolute host address */
729 static void tcg_out_ld_abs(TCGContext *s, TCGType type, TCGReg dest, void *abs)
730 {
731 intptr_t addr = (intptr_t)abs;
732
733 if ((s390_facilities & FACILITY_GEN_INST_EXT) && !(addr & 1)) {
734 ptrdiff_t disp = tcg_pcrel_diff(s, abs) >> 1;
735 if (disp == (int32_t)disp) {
736 if (type == TCG_TYPE_I32) {
737 tcg_out_insn(s, RIL, LRL, dest, disp);
738 } else {
739 tcg_out_insn(s, RIL, LGRL, dest, disp);
740 }
741 return;
742 }
743 }
744
745 tcg_out_movi(s, TCG_TYPE_PTR, dest, addr & ~0xffff);
746 tcg_out_ld(s, type, dest, dest, addr & 0xffff);
747 }
748
749 static inline void tcg_out_risbg(TCGContext *s, TCGReg dest, TCGReg src,
750 int msb, int lsb, int ofs, int z)
751 {
752 /* Format RIE-f */
753 tcg_out16(s, (RIE_RISBG & 0xff00) | (dest << 4) | src);
754 tcg_out16(s, (msb << 8) | (z << 7) | lsb);
755 tcg_out16(s, (ofs << 8) | (RIE_RISBG & 0xff));
756 }
757
758 static void tgen_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
759 {
760 if (s390_facilities & FACILITY_EXT_IMM) {
761 tcg_out_insn(s, RRE, LGBR, dest, src);
762 return;
763 }
764
765 if (type == TCG_TYPE_I32) {
766 if (dest == src) {
767 tcg_out_sh32(s, RS_SLL, dest, TCG_REG_NONE, 24);
768 } else {
769 tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 24);
770 }
771 tcg_out_sh32(s, RS_SRA, dest, TCG_REG_NONE, 24);
772 } else {
773 tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 56);
774 tcg_out_sh64(s, RSY_SRAG, dest, dest, TCG_REG_NONE, 56);
775 }
776 }
777
778 static void tgen_ext8u(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
779 {
780 if (s390_facilities & FACILITY_EXT_IMM) {
781 tcg_out_insn(s, RRE, LLGCR, dest, src);
782 return;
783 }
784
785 if (dest == src) {
786 tcg_out_movi(s, type, TCG_TMP0, 0xff);
787 src = TCG_TMP0;
788 } else {
789 tcg_out_movi(s, type, dest, 0xff);
790 }
791 if (type == TCG_TYPE_I32) {
792 tcg_out_insn(s, RR, NR, dest, src);
793 } else {
794 tcg_out_insn(s, RRE, NGR, dest, src);
795 }
796 }
797
798 static void tgen_ext16s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
799 {
800 if (s390_facilities & FACILITY_EXT_IMM) {
801 tcg_out_insn(s, RRE, LGHR, dest, src);
802 return;
803 }
804
805 if (type == TCG_TYPE_I32) {
806 if (dest == src) {
807 tcg_out_sh32(s, RS_SLL, dest, TCG_REG_NONE, 16);
808 } else {
809 tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 16);
810 }
811 tcg_out_sh32(s, RS_SRA, dest, TCG_REG_NONE, 16);
812 } else {
813 tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 48);
814 tcg_out_sh64(s, RSY_SRAG, dest, dest, TCG_REG_NONE, 48);
815 }
816 }
817
818 static void tgen_ext16u(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
819 {
820 if (s390_facilities & FACILITY_EXT_IMM) {
821 tcg_out_insn(s, RRE, LLGHR, dest, src);
822 return;
823 }
824
825 if (dest == src) {
826 tcg_out_movi(s, type, TCG_TMP0, 0xffff);
827 src = TCG_TMP0;
828 } else {
829 tcg_out_movi(s, type, dest, 0xffff);
830 }
831 if (type == TCG_TYPE_I32) {
832 tcg_out_insn(s, RR, NR, dest, src);
833 } else {
834 tcg_out_insn(s, RRE, NGR, dest, src);
835 }
836 }
837
838 static inline void tgen_ext32s(TCGContext *s, TCGReg dest, TCGReg src)
839 {
840 tcg_out_insn(s, RRE, LGFR, dest, src);
841 }
842
843 static inline void tgen_ext32u(TCGContext *s, TCGReg dest, TCGReg src)
844 {
845 tcg_out_insn(s, RRE, LLGFR, dest, src);
846 }
847
848 /* Accept bit patterns like these:
849 0....01....1
850 1....10....0
851 1..10..01..1
852 0..01..10..0
853 Copied from gcc sources. */
854 static inline bool risbg_mask(uint64_t c)
855 {
856 uint64_t lsb;
857 /* We don't change the number of transitions by inverting,
858 so make sure we start with the LSB zero. */
859 if (c & 1) {
860 c = ~c;
861 }
862 /* Reject all zeros or all ones. */
863 if (c == 0) {
864 return false;
865 }
866 /* Find the first transition. */
867 lsb = c & -c;
868 /* Invert to look for a second transition. */
869 c = ~c;
870 /* Erase the first transition. */
871 c &= -lsb;
872 /* Find the second transition, if any. */
873 lsb = c & -c;
874 /* Match if all the bits are 1's, or if c is zero. */
875 return c == -lsb;
876 }
877
878 static void tgen_andi_risbg(TCGContext *s, TCGReg out, TCGReg in, uint64_t val)
879 {
880 int msb, lsb;
881 if ((val & 0x8000000000000001ull) == 0x8000000000000001ull) {
882 /* Achieve wraparound by swapping msb and lsb. */
883 msb = 64 - ctz64(~val);
884 lsb = clz64(~val) - 1;
885 } else {
886 msb = clz64(val);
887 lsb = 63 - ctz64(val);
888 }
889 tcg_out_risbg(s, out, in, msb, lsb, 0, 1);
890 }
891
892 static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)
893 {
894 static const S390Opcode ni_insns[4] = {
895 RI_NILL, RI_NILH, RI_NIHL, RI_NIHH
896 };
897 static const S390Opcode nif_insns[2] = {
898 RIL_NILF, RIL_NIHF
899 };
900 uint64_t valid = (type == TCG_TYPE_I32 ? 0xffffffffull : -1ull);
901 int i;
902
903 /* Look for the zero-extensions. */
904 if ((val & valid) == 0xffffffff) {
905 tgen_ext32u(s, dest, dest);
906 return;
907 }
908 if (s390_facilities & FACILITY_EXT_IMM) {
909 if ((val & valid) == 0xff) {
910 tgen_ext8u(s, TCG_TYPE_I64, dest, dest);
911 return;
912 }
913 if ((val & valid) == 0xffff) {
914 tgen_ext16u(s, TCG_TYPE_I64, dest, dest);
915 return;
916 }
917 }
918
919 /* Try all 32-bit insns that can perform it in one go. */
920 for (i = 0; i < 4; i++) {
921 tcg_target_ulong mask = ~(0xffffull << i*16);
922 if (((val | ~valid) & mask) == mask) {
923 tcg_out_insn_RI(s, ni_insns[i], dest, val >> i*16);
924 return;
925 }
926 }
927
928 /* Try all 48-bit insns that can perform it in one go. */
929 if (s390_facilities & FACILITY_EXT_IMM) {
930 for (i = 0; i < 2; i++) {
931 tcg_target_ulong mask = ~(0xffffffffull << i*32);
932 if (((val | ~valid) & mask) == mask) {
933 tcg_out_insn_RIL(s, nif_insns[i], dest, val >> i*32);
934 return;
935 }
936 }
937 }
938 if ((s390_facilities & FACILITY_GEN_INST_EXT) && risbg_mask(val)) {
939 tgen_andi_risbg(s, dest, dest, val);
940 return;
941 }
942
943 /* Fall back to loading the constant. */
944 tcg_out_movi(s, type, TCG_TMP0, val);
945 if (type == TCG_TYPE_I32) {
946 tcg_out_insn(s, RR, NR, dest, TCG_TMP0);
947 } else {
948 tcg_out_insn(s, RRE, NGR, dest, TCG_TMP0);
949 }
950 }
951
952 static void tgen64_ori(TCGContext *s, TCGReg dest, tcg_target_ulong val)
953 {
954 static const S390Opcode oi_insns[4] = {
955 RI_OILL, RI_OILH, RI_OIHL, RI_OIHH
956 };
957 static const S390Opcode nif_insns[2] = {
958 RIL_OILF, RIL_OIHF
959 };
960
961 int i;
962
963 /* Look for no-op. */
964 if (val == 0) {
965 return;
966 }
967
968 if (s390_facilities & FACILITY_EXT_IMM) {
969 /* Try all 32-bit insns that can perform it in one go. */
970 for (i = 0; i < 4; i++) {
971 tcg_target_ulong mask = (0xffffull << i*16);
972 if ((val & mask) != 0 && (val & ~mask) == 0) {
973 tcg_out_insn_RI(s, oi_insns[i], dest, val >> i*16);
974 return;
975 }
976 }
977
978 /* Try all 48-bit insns that can perform it in one go. */
979 for (i = 0; i < 2; i++) {
980 tcg_target_ulong mask = (0xffffffffull << i*32);
981 if ((val & mask) != 0 && (val & ~mask) == 0) {
982 tcg_out_insn_RIL(s, nif_insns[i], dest, val >> i*32);
983 return;
984 }
985 }
986
987 /* Perform the OR via sequential modifications to the high and
988 low parts. Do this via recursion to handle 16-bit vs 32-bit
989 masks in each half. */
990 tgen64_ori(s, dest, val & 0x00000000ffffffffull);
991 tgen64_ori(s, dest, val & 0xffffffff00000000ull);
992 } else {
993 /* With no extended-immediate facility, we don't need to be so
994 clever. Just iterate over the insns and mask in the constant. */
995 for (i = 0; i < 4; i++) {
996 tcg_target_ulong mask = (0xffffull << i*16);
997 if ((val & mask) != 0) {
998 tcg_out_insn_RI(s, oi_insns[i], dest, val >> i*16);
999 }
1000 }
1001 }
1002 }
1003
1004 static void tgen64_xori(TCGContext *s, TCGReg dest, tcg_target_ulong val)
1005 {
1006 /* Perform the xor by parts. */
1007 if (val & 0xffffffff) {
1008 tcg_out_insn(s, RIL, XILF, dest, val);
1009 }
1010 if (val > 0xffffffff) {
1011 tcg_out_insn(s, RIL, XIHF, dest, val >> 31 >> 1);
1012 }
1013 }
1014
1015 static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1,
1016 TCGArg c2, bool c2const, bool need_carry)
1017 {
1018 bool is_unsigned = is_unsigned_cond(c);
1019 if (c2const) {
1020 if (c2 == 0) {
1021 if (!(is_unsigned && need_carry)) {
1022 if (type == TCG_TYPE_I32) {
1023 tcg_out_insn(s, RR, LTR, r1, r1);
1024 } else {
1025 tcg_out_insn(s, RRE, LTGR, r1, r1);
1026 }
1027 return tcg_cond_to_ltr_cond[c];
1028 }
1029 /* If we only got here because of load-and-test,
1030 and we couldn't use that, then we need to load
1031 the constant into a register. */
1032 if (!(s390_facilities & FACILITY_EXT_IMM)) {
1033 c2 = TCG_TMP0;
1034 tcg_out_movi(s, type, c2, 0);
1035 goto do_reg;
1036 }
1037 }
1038 if (is_unsigned) {
1039 if (type == TCG_TYPE_I32) {
1040 tcg_out_insn(s, RIL, CLFI, r1, c2);
1041 } else {
1042 tcg_out_insn(s, RIL, CLGFI, r1, c2);
1043 }
1044 } else {
1045 if (type == TCG_TYPE_I32) {
1046 tcg_out_insn(s, RIL, CFI, r1, c2);
1047 } else {
1048 tcg_out_insn(s, RIL, CGFI, r1, c2);
1049 }
1050 }
1051 } else {
1052 do_reg:
1053 if (is_unsigned) {
1054 if (type == TCG_TYPE_I32) {
1055 tcg_out_insn(s, RR, CLR, r1, c2);
1056 } else {
1057 tcg_out_insn(s, RRE, CLGR, r1, c2);
1058 }
1059 } else {
1060 if (type == TCG_TYPE_I32) {
1061 tcg_out_insn(s, RR, CR, r1, c2);
1062 } else {
1063 tcg_out_insn(s, RRE, CGR, r1, c2);
1064 }
1065 }
1066 }
1067 return tcg_cond_to_s390_cond[c];
1068 }
1069
1070 static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond,
1071 TCGReg dest, TCGReg c1, TCGArg c2, int c2const)
1072 {
1073 int cc;
1074 bool have_loc;
1075
1076 /* With LOC2, we can always emit the minimum 3 insns. */
1077 if (s390_facilities & FACILITY_LOAD_ON_COND2) {
1078 /* Emit: d = 0, d = (cc ? 1 : d). */
1079 cc = tgen_cmp(s, type, cond, c1, c2, c2const, false);
1080 tcg_out_movi(s, TCG_TYPE_I64, dest, 0);
1081 tcg_out_insn(s, RIE, LOCGHI, dest, 1, cc);
1082 return;
1083 }
1084
1085 have_loc = (s390_facilities & FACILITY_LOAD_ON_COND) != 0;
1086
1087 /* For HAVE_LOC, only the paths through GTU/GT/LEU/LE are smaller. */
1088 restart:
1089 switch (cond) {
1090 case TCG_COND_NE:
1091 /* X != 0 is X > 0. */
1092 if (c2const && c2 == 0) {
1093 cond = TCG_COND_GTU;
1094 } else {
1095 break;
1096 }
1097 /* fallthru */
1098
1099 case TCG_COND_GTU:
1100 case TCG_COND_GT:
1101 /* The result of a compare has CC=2 for GT and CC=3 unused.
1102 ADD LOGICAL WITH CARRY considers (CC & 2) the carry bit. */
1103 tgen_cmp(s, type, cond, c1, c2, c2const, true);
1104 tcg_out_movi(s, type, dest, 0);
1105 tcg_out_insn(s, RRE, ALCGR, dest, dest);
1106 return;
1107
1108 case TCG_COND_EQ:
1109 /* X == 0 is X <= 0. */
1110 if (c2const && c2 == 0) {
1111 cond = TCG_COND_LEU;
1112 } else {
1113 break;
1114 }
1115 /* fallthru */
1116
1117 case TCG_COND_LEU:
1118 case TCG_COND_LE:
1119 /* As above, but we're looking for borrow, or !carry.
1120 The second insn computes d - d - borrow, or -1 for true
1121 and 0 for false. So we must mask to 1 bit afterward. */
1122 tgen_cmp(s, type, cond, c1, c2, c2const, true);
1123 tcg_out_insn(s, RRE, SLBGR, dest, dest);
1124 tgen_andi(s, type, dest, 1);
1125 return;
1126
1127 case TCG_COND_GEU:
1128 case TCG_COND_LTU:
1129 case TCG_COND_LT:
1130 case TCG_COND_GE:
1131 /* Swap operands so that we can use LEU/GTU/GT/LE. */
1132 if (c2const) {
1133 if (have_loc) {
1134 break;
1135 }
1136 tcg_out_movi(s, type, TCG_TMP0, c2);
1137 c2 = c1;
1138 c2const = 0;
1139 c1 = TCG_TMP0;
1140 } else {
1141 TCGReg t = c1;
1142 c1 = c2;
1143 c2 = t;
1144 }
1145 cond = tcg_swap_cond(cond);
1146 goto restart;
1147
1148 default:
1149 g_assert_not_reached();
1150 }
1151
1152 cc = tgen_cmp(s, type, cond, c1, c2, c2const, false);
1153 if (have_loc) {
1154 /* Emit: d = 0, t = 1, d = (cc ? t : d). */
1155 tcg_out_movi(s, TCG_TYPE_I64, dest, 0);
1156 tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 1);
1157 tcg_out_insn(s, RRF, LOCGR, dest, TCG_TMP0, cc);
1158 } else {
1159 /* Emit: d = 1; if (cc) goto over; d = 0; over: */
1160 tcg_out_movi(s, type, dest, 1);
1161 tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1);
1162 tcg_out_movi(s, type, dest, 0);
1163 }
1164 }
1165
1166 static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg dest,
1167 TCGReg c1, TCGArg c2, int c2const,
1168 TCGArg v3, int v3const)
1169 {
1170 int cc;
1171 if (s390_facilities & FACILITY_LOAD_ON_COND) {
1172 cc = tgen_cmp(s, type, c, c1, c2, c2const, false);
1173 if (v3const) {
1174 tcg_out_insn(s, RIE, LOCGHI, dest, v3, cc);
1175 } else {
1176 tcg_out_insn(s, RRF, LOCGR, dest, v3, cc);
1177 }
1178 } else {
1179 c = tcg_invert_cond(c);
1180 cc = tgen_cmp(s, type, c, c1, c2, c2const, false);
1181
1182 /* Emit: if (cc) goto over; dest = r3; over: */
1183 tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1);
1184 tcg_out_insn(s, RRE, LGR, dest, v3);
1185 }
1186 }
1187
1188 static void tgen_clz(TCGContext *s, TCGReg dest, TCGReg a1,
1189 TCGArg a2, int a2const)
1190 {
1191 /* Since this sets both R and R+1, we have no choice but to store the
1192 result into R0, allowing R1 == TCG_TMP0 to be clobbered as well. */
1193 QEMU_BUILD_BUG_ON(TCG_TMP0 != TCG_REG_R1);
1194 tcg_out_insn(s, RRE, FLOGR, TCG_REG_R0, a1);
1195
1196 if (a2const && a2 == 64) {
1197 tcg_out_mov(s, TCG_TYPE_I64, dest, TCG_REG_R0);
1198 } else {
1199 if (a2const) {
1200 tcg_out_movi(s, TCG_TYPE_I64, dest, a2);
1201 } else {
1202 tcg_out_mov(s, TCG_TYPE_I64, dest, a2);
1203 }
1204 if (s390_facilities & FACILITY_LOAD_ON_COND) {
1205 /* Emit: if (one bit found) dest = r0. */
1206 tcg_out_insn(s, RRF, LOCGR, dest, TCG_REG_R0, 2);
1207 } else {
1208 /* Emit: if (no one bit found) goto over; dest = r0; over: */
1209 tcg_out_insn(s, RI, BRC, 8, (4 + 4) >> 1);
1210 tcg_out_insn(s, RRE, LGR, dest, TCG_REG_R0);
1211 }
1212 }
1213 }
1214
1215 static void tgen_deposit(TCGContext *s, TCGReg dest, TCGReg src,
1216 int ofs, int len, int z)
1217 {
1218 int lsb = (63 - ofs);
1219 int msb = lsb - (len - 1);
1220 tcg_out_risbg(s, dest, src, msb, lsb, ofs, z);
1221 }
1222
1223 static void tgen_extract(TCGContext *s, TCGReg dest, TCGReg src,
1224 int ofs, int len)
1225 {
1226 tcg_out_risbg(s, dest, src, 64 - len, 63, 64 - ofs, 1);
1227 }
1228
1229 static void tgen_gotoi(TCGContext *s, int cc, tcg_insn_unit *dest)
1230 {
1231 ptrdiff_t off = dest - s->code_ptr;
1232 if (off == (int16_t)off) {
1233 tcg_out_insn(s, RI, BRC, cc, off);
1234 } else if (off == (int32_t)off) {
1235 tcg_out_insn(s, RIL, BRCL, cc, off);
1236 } else {
1237 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)dest);
1238 tcg_out_insn(s, RR, BCR, cc, TCG_TMP0);
1239 }
1240 }
1241
1242 static void tgen_branch(TCGContext *s, int cc, TCGLabel *l)
1243 {
1244 if (l->has_value) {
1245 tgen_gotoi(s, cc, l->u.value_ptr);
1246 } else if (USE_LONG_BRANCHES) {
1247 tcg_out16(s, RIL_BRCL | (cc << 4));
1248 tcg_out_reloc(s, s->code_ptr, R_390_PC32DBL, l, -2);
1249 s->code_ptr += 2;
1250 } else {
1251 tcg_out16(s, RI_BRC | (cc << 4));
1252 tcg_out_reloc(s, s->code_ptr, R_390_PC16DBL, l, -2);
1253 s->code_ptr += 1;
1254 }
1255 }
1256
1257 static void tgen_compare_branch(TCGContext *s, S390Opcode opc, int cc,
1258 TCGReg r1, TCGReg r2, TCGLabel *l)
1259 {
1260 intptr_t off;
1261
1262 if (l->has_value) {
1263 off = l->u.value_ptr - s->code_ptr;
1264 } else {
1265 /* We need to keep the offset unchanged for retranslation. */
1266 off = s->code_ptr[1];
1267 tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, -2);
1268 }
1269
1270 tcg_out16(s, (opc & 0xff00) | (r1 << 4) | r2);
1271 tcg_out16(s, off);
1272 tcg_out16(s, cc << 12 | (opc & 0xff));
1273 }
1274
1275 static void tgen_compare_imm_branch(TCGContext *s, S390Opcode opc, int cc,
1276 TCGReg r1, int i2, TCGLabel *l)
1277 {
1278 tcg_target_long off;
1279
1280 if (l->has_value) {
1281 off = l->u.value_ptr - s->code_ptr;
1282 } else {
1283 /* We need to keep the offset unchanged for retranslation. */
1284 off = s->code_ptr[1];
1285 tcg_out_reloc(s, s->code_ptr + 1, R_390_PC16DBL, l, -2);
1286 }
1287
1288 tcg_out16(s, (opc & 0xff00) | (r1 << 4) | cc);
1289 tcg_out16(s, off);
1290 tcg_out16(s, (i2 << 8) | (opc & 0xff));
1291 }
1292
1293 static void tgen_brcond(TCGContext *s, TCGType type, TCGCond c,
1294 TCGReg r1, TCGArg c2, int c2const, TCGLabel *l)
1295 {
1296 int cc;
1297
1298 if (s390_facilities & FACILITY_GEN_INST_EXT) {
1299 bool is_unsigned = is_unsigned_cond(c);
1300 bool in_range;
1301 S390Opcode opc;
1302
1303 cc = tcg_cond_to_s390_cond[c];
1304
1305 if (!c2const) {
1306 opc = (type == TCG_TYPE_I32
1307 ? (is_unsigned ? RIE_CLRJ : RIE_CRJ)
1308 : (is_unsigned ? RIE_CLGRJ : RIE_CGRJ));
1309 tgen_compare_branch(s, opc, cc, r1, c2, l);
1310 return;
1311 }
1312
1313 /* COMPARE IMMEDIATE AND BRANCH RELATIVE has an 8-bit immediate field.
1314 If the immediate we've been given does not fit that range, we'll
1315 fall back to separate compare and branch instructions using the
1316 larger comparison range afforded by COMPARE IMMEDIATE. */
1317 if (type == TCG_TYPE_I32) {
1318 if (is_unsigned) {
1319 opc = RIE_CLIJ;
1320 in_range = (uint32_t)c2 == (uint8_t)c2;
1321 } else {
1322 opc = RIE_CIJ;
1323 in_range = (int32_t)c2 == (int8_t)c2;
1324 }
1325 } else {
1326 if (is_unsigned) {
1327 opc = RIE_CLGIJ;
1328 in_range = (uint64_t)c2 == (uint8_t)c2;
1329 } else {
1330 opc = RIE_CGIJ;
1331 in_range = (int64_t)c2 == (int8_t)c2;
1332 }
1333 }
1334 if (in_range) {
1335 tgen_compare_imm_branch(s, opc, cc, r1, c2, l);
1336 return;
1337 }
1338 }
1339
1340 cc = tgen_cmp(s, type, c, r1, c2, c2const, false);
1341 tgen_branch(s, cc, l);
1342 }
1343
1344 static void tcg_out_call(TCGContext *s, tcg_insn_unit *dest)
1345 {
1346 ptrdiff_t off = dest - s->code_ptr;
1347 if (off == (int32_t)off) {
1348 tcg_out_insn(s, RIL, BRASL, TCG_REG_R14, off);
1349 } else {
1350 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)dest);
1351 tcg_out_insn(s, RR, BASR, TCG_REG_R14, TCG_TMP0);
1352 }
1353 }
1354
1355 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp opc, TCGReg data,
1356 TCGReg base, TCGReg index, int disp)
1357 {
1358 switch (opc & (MO_SSIZE | MO_BSWAP)) {
1359 case MO_UB:
1360 tcg_out_insn(s, RXY, LLGC, data, base, index, disp);
1361 break;
1362 case MO_SB:
1363 tcg_out_insn(s, RXY, LGB, data, base, index, disp);
1364 break;
1365
1366 case MO_UW | MO_BSWAP:
1367 /* swapped unsigned halfword load with upper bits zeroed */
1368 tcg_out_insn(s, RXY, LRVH, data, base, index, disp);
1369 tgen_ext16u(s, TCG_TYPE_I64, data, data);
1370 break;
1371 case MO_UW:
1372 tcg_out_insn(s, RXY, LLGH, data, base, index, disp);
1373 break;
1374
1375 case MO_SW | MO_BSWAP:
1376 /* swapped sign-extended halfword load */
1377 tcg_out_insn(s, RXY, LRVH, data, base, index, disp);
1378 tgen_ext16s(s, TCG_TYPE_I64, data, data);
1379 break;
1380 case MO_SW:
1381 tcg_out_insn(s, RXY, LGH, data, base, index, disp);
1382 break;
1383
1384 case MO_UL | MO_BSWAP:
1385 /* swapped unsigned int load with upper bits zeroed */
1386 tcg_out_insn(s, RXY, LRV, data, base, index, disp);
1387 tgen_ext32u(s, data, data);
1388 break;
1389 case MO_UL:
1390 tcg_out_insn(s, RXY, LLGF, data, base, index, disp);
1391 break;
1392
1393 case MO_SL | MO_BSWAP:
1394 /* swapped sign-extended int load */
1395 tcg_out_insn(s, RXY, LRV, data, base, index, disp);
1396 tgen_ext32s(s, data, data);
1397 break;
1398 case MO_SL:
1399 tcg_out_insn(s, RXY, LGF, data, base, index, disp);
1400 break;
1401
1402 case MO_Q | MO_BSWAP:
1403 tcg_out_insn(s, RXY, LRVG, data, base, index, disp);
1404 break;
1405 case MO_Q:
1406 tcg_out_insn(s, RXY, LG, data, base, index, disp);
1407 break;
1408
1409 default:
1410 tcg_abort();
1411 }
1412 }
1413
1414 static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp opc, TCGReg data,
1415 TCGReg base, TCGReg index, int disp)
1416 {
1417 switch (opc & (MO_SIZE | MO_BSWAP)) {
1418 case MO_UB:
1419 if (disp >= 0 && disp < 0x1000) {
1420 tcg_out_insn(s, RX, STC, data, base, index, disp);
1421 } else {
1422 tcg_out_insn(s, RXY, STCY, data, base, index, disp);
1423 }
1424 break;
1425
1426 case MO_UW | MO_BSWAP:
1427 tcg_out_insn(s, RXY, STRVH, data, base, index, disp);
1428 break;
1429 case MO_UW:
1430 if (disp >= 0 && disp < 0x1000) {
1431 tcg_out_insn(s, RX, STH, data, base, index, disp);
1432 } else {
1433 tcg_out_insn(s, RXY, STHY, data, base, index, disp);
1434 }
1435 break;
1436
1437 case MO_UL | MO_BSWAP:
1438 tcg_out_insn(s, RXY, STRV, data, base, index, disp);
1439 break;
1440 case MO_UL:
1441 if (disp >= 0 && disp < 0x1000) {
1442 tcg_out_insn(s, RX, ST, data, base, index, disp);
1443 } else {
1444 tcg_out_insn(s, RXY, STY, data, base, index, disp);
1445 }
1446 break;
1447
1448 case MO_Q | MO_BSWAP:
1449 tcg_out_insn(s, RXY, STRVG, data, base, index, disp);
1450 break;
1451 case MO_Q:
1452 tcg_out_insn(s, RXY, STG, data, base, index, disp);
1453 break;
1454
1455 default:
1456 tcg_abort();
1457 }
1458 }
1459
1460 #if defined(CONFIG_SOFTMMU)
1461 /* We're expecting to use a 20-bit signed offset on the tlb memory ops.
1462 Using the offset of the second entry in the last tlb table ensures
1463 that we can index all of the elements of the first entry. */
1464 QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table[NB_MMU_MODES - 1][1])
1465 > 0x7ffff);
1466
1467 /* Load and compare a TLB entry, leaving the flags set. Loads the TLB
1468 addend into R2. Returns a register with the santitized guest address. */
1469 static TCGReg tcg_out_tlb_read(TCGContext* s, TCGReg addr_reg, TCGMemOp opc,
1470 int mem_index, bool is_ld)
1471 {
1472 unsigned s_bits = opc & MO_SIZE;
1473 unsigned a_bits = get_alignment_bits(opc);
1474 unsigned s_mask = (1 << s_bits) - 1;
1475 unsigned a_mask = (1 << a_bits) - 1;
1476 int ofs, a_off;
1477 uint64_t tlb_mask;
1478
1479 /* For aligned accesses, we check the first byte and include the alignment
1480 bits within the address. For unaligned access, we check that we don't
1481 cross pages using the address of the last byte of the access. */
1482 a_off = (a_bits >= s_bits ? 0 : s_mask - a_mask);
1483 tlb_mask = (uint64_t)TARGET_PAGE_MASK | a_mask;
1484
1485 if (s390_facilities & FACILITY_GEN_INST_EXT) {
1486 tcg_out_risbg(s, TCG_REG_R2, addr_reg,
1487 64 - CPU_TLB_BITS - CPU_TLB_ENTRY_BITS,
1488 63 - CPU_TLB_ENTRY_BITS,
1489 64 + CPU_TLB_ENTRY_BITS - TARGET_PAGE_BITS, 1);
1490 if (a_off) {
1491 tcg_out_insn(s, RX, LA, TCG_REG_R3, addr_reg, TCG_REG_NONE, a_off);
1492 tgen_andi(s, TCG_TYPE_TL, TCG_REG_R3, tlb_mask);
1493 } else {
1494 tgen_andi_risbg(s, TCG_REG_R3, addr_reg, tlb_mask);
1495 }
1496 } else {
1497 tcg_out_sh64(s, RSY_SRLG, TCG_REG_R2, addr_reg, TCG_REG_NONE,
1498 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
1499 tcg_out_insn(s, RX, LA, TCG_REG_R3, addr_reg, TCG_REG_NONE, a_off);
1500 tgen_andi(s, TCG_TYPE_I64, TCG_REG_R2,
1501 (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
1502 tgen_andi(s, TCG_TYPE_TL, TCG_REG_R3, tlb_mask);
1503 }
1504
1505 if (is_ld) {
1506 ofs = offsetof(CPUArchState, tlb_table[mem_index][0].addr_read);
1507 } else {
1508 ofs = offsetof(CPUArchState, tlb_table[mem_index][0].addr_write);
1509 }
1510 if (TARGET_LONG_BITS == 32) {
1511 tcg_out_mem(s, RX_C, RXY_CY, TCG_REG_R3, TCG_REG_R2, TCG_AREG0, ofs);
1512 } else {
1513 tcg_out_mem(s, 0, RXY_CG, TCG_REG_R3, TCG_REG_R2, TCG_AREG0, ofs);
1514 }
1515
1516 ofs = offsetof(CPUArchState, tlb_table[mem_index][0].addend);
1517 tcg_out_mem(s, 0, RXY_LG, TCG_REG_R2, TCG_REG_R2, TCG_AREG0, ofs);
1518
1519 if (TARGET_LONG_BITS == 32) {
1520 tgen_ext32u(s, TCG_REG_R3, addr_reg);
1521 return TCG_REG_R3;
1522 }
1523 return addr_reg;
1524 }
1525
1526 static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
1527 TCGReg data, TCGReg addr,
1528 tcg_insn_unit *raddr, tcg_insn_unit *label_ptr)
1529 {
1530 TCGLabelQemuLdst *label = new_ldst_label(s);
1531
1532 label->is_ld = is_ld;
1533 label->oi = oi;
1534 label->datalo_reg = data;
1535 label->addrlo_reg = addr;
1536 label->raddr = raddr;
1537 label->label_ptr[0] = label_ptr;
1538 }
1539
1540 static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
1541 {
1542 TCGReg addr_reg = lb->addrlo_reg;
1543 TCGReg data_reg = lb->datalo_reg;
1544 TCGMemOpIdx oi = lb->oi;
1545 TCGMemOp opc = get_memop(oi);
1546
1547 patch_reloc(lb->label_ptr[0], R_390_PC16DBL, (intptr_t)s->code_ptr, -2);
1548
1549 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0);
1550 if (TARGET_LONG_BITS == 64) {
1551 tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R3, addr_reg);
1552 }
1553 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R4, oi);
1554 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R5, (uintptr_t)lb->raddr);
1555 tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)]);
1556 tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_R2);
1557
1558 tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr);
1559 }
1560
1561 static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
1562 {
1563 TCGReg addr_reg = lb->addrlo_reg;
1564 TCGReg data_reg = lb->datalo_reg;
1565 TCGMemOpIdx oi = lb->oi;
1566 TCGMemOp opc = get_memop(oi);
1567
1568 patch_reloc(lb->label_ptr[0], R_390_PC16DBL, (intptr_t)s->code_ptr, -2);
1569
1570 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0);
1571 if (TARGET_LONG_BITS == 64) {
1572 tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R3, addr_reg);
1573 }
1574 switch (opc & MO_SIZE) {
1575 case MO_UB:
1576 tgen_ext8u(s, TCG_TYPE_I64, TCG_REG_R4, data_reg);
1577 break;
1578 case MO_UW:
1579 tgen_ext16u(s, TCG_TYPE_I64, TCG_REG_R4, data_reg);
1580 break;
1581 case MO_UL:
1582 tgen_ext32u(s, TCG_REG_R4, data_reg);
1583 break;
1584 case MO_Q:
1585 tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R4, data_reg);
1586 break;
1587 default:
1588 tcg_abort();
1589 }
1590 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R5, oi);
1591 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R6, (uintptr_t)lb->raddr);
1592 tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
1593
1594 tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr);
1595 }
1596 #else
1597 static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg,
1598 TCGReg *index_reg, tcg_target_long *disp)
1599 {
1600 if (TARGET_LONG_BITS == 32) {
1601 tgen_ext32u(s, TCG_TMP0, *addr_reg);
1602 *addr_reg = TCG_TMP0;
1603 }
1604 if (guest_base < 0x80000) {
1605 *index_reg = TCG_REG_NONE;
1606 *disp = guest_base;
1607 } else {
1608 *index_reg = TCG_GUEST_BASE_REG;
1609 *disp = 0;
1610 }
1611 }
1612 #endif /* CONFIG_SOFTMMU */
1613
1614 static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
1615 TCGMemOpIdx oi)
1616 {
1617 TCGMemOp opc = get_memop(oi);
1618 #ifdef CONFIG_SOFTMMU
1619 unsigned mem_index = get_mmuidx(oi);
1620 tcg_insn_unit *label_ptr;
1621 TCGReg base_reg;
1622
1623 base_reg = tcg_out_tlb_read(s, addr_reg, opc, mem_index, 1);
1624
1625 /* We need to keep the offset unchanged for retranslation. */
1626 tcg_out16(s, RI_BRC | (S390_CC_NE << 4));
1627 label_ptr = s->code_ptr;
1628 s->code_ptr += 1;
1629
1630 tcg_out_qemu_ld_direct(s, opc, data_reg, base_reg, TCG_REG_R2, 0);
1631
1632 add_qemu_ldst_label(s, 1, oi, data_reg, addr_reg, s->code_ptr, label_ptr);
1633 #else
1634 TCGReg index_reg;
1635 tcg_target_long disp;
1636
1637 tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp);
1638 tcg_out_qemu_ld_direct(s, opc, data_reg, addr_reg, index_reg, disp);
1639 #endif
1640 }
1641
1642 static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
1643 TCGMemOpIdx oi)
1644 {
1645 TCGMemOp opc = get_memop(oi);
1646 #ifdef CONFIG_SOFTMMU
1647 unsigned mem_index = get_mmuidx(oi);
1648 tcg_insn_unit *label_ptr;
1649 TCGReg base_reg;
1650
1651 base_reg = tcg_out_tlb_read(s, addr_reg, opc, mem_index, 0);
1652
1653 /* We need to keep the offset unchanged for retranslation. */
1654 tcg_out16(s, RI_BRC | (S390_CC_NE << 4));
1655 label_ptr = s->code_ptr;
1656 s->code_ptr += 1;
1657
1658 tcg_out_qemu_st_direct(s, opc, data_reg, base_reg, TCG_REG_R2, 0);
1659
1660 add_qemu_ldst_label(s, 0, oi, data_reg, addr_reg, s->code_ptr, label_ptr);
1661 #else
1662 TCGReg index_reg;
1663 tcg_target_long disp;
1664
1665 tcg_prepare_user_ldst(s, &addr_reg, &index_reg, &disp);
1666 tcg_out_qemu_st_direct(s, opc, data_reg, addr_reg, index_reg, disp);
1667 #endif
1668 }
1669
1670 # define OP_32_64(x) \
1671 case glue(glue(INDEX_op_,x),_i32): \
1672 case glue(glue(INDEX_op_,x),_i64)
1673
1674 static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
1675 const TCGArg *args, const int *const_args)
1676 {
1677 S390Opcode op, op2;
1678 TCGArg a0, a1, a2;
1679
1680 switch (opc) {
1681 case INDEX_op_exit_tb:
1682 /* Reuse the zeroing that exists for goto_ptr. */
1683 a0 = args[0];
1684 if (a0 == 0) {
1685 tgen_gotoi(s, S390_CC_ALWAYS, s->code_gen_epilogue);
1686 } else {
1687 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, a0);
1688 tgen_gotoi(s, S390_CC_ALWAYS, tb_ret_addr);
1689 }
1690 break;
1691
1692 case INDEX_op_goto_tb:
1693 if (s->tb_jmp_insn_offset) {
1694 /* branch displacement must be aligned for atomic patching;
1695 * see if we need to add extra nop before branch
1696 */
1697 if (!QEMU_PTR_IS_ALIGNED(s->code_ptr + 1, 4)) {
1698 tcg_out16(s, NOP);
1699 }
1700 tcg_out16(s, RIL_BRCL | (S390_CC_ALWAYS << 4));
1701 s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s);
1702 s->code_ptr += 2;
1703 } else {
1704 /* load address stored at s->tb_jmp_target_addr + args[0] */
1705 tcg_out_ld_abs(s, TCG_TYPE_PTR, TCG_TMP0,
1706 s->tb_jmp_target_addr + args[0]);
1707 /* and go there */
1708 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_TMP0);
1709 }
1710 s->tb_jmp_reset_offset[args[0]] = tcg_current_code_size(s);
1711 break;
1712
1713 case INDEX_op_goto_ptr:
1714 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, args[0]);
1715 break;
1716
1717 OP_32_64(ld8u):
1718 /* ??? LLC (RXY format) is only present with the extended-immediate
1719 facility, whereas LLGC is always present. */
1720 tcg_out_mem(s, 0, RXY_LLGC, args[0], args[1], TCG_REG_NONE, args[2]);
1721 break;
1722
1723 OP_32_64(ld8s):
1724 /* ??? LB is no smaller than LGB, so no point to using it. */
1725 tcg_out_mem(s, 0, RXY_LGB, args[0], args[1], TCG_REG_NONE, args[2]);
1726 break;
1727
1728 OP_32_64(ld16u):
1729 /* ??? LLH (RXY format) is only present with the extended-immediate
1730 facility, whereas LLGH is always present. */
1731 tcg_out_mem(s, 0, RXY_LLGH, args[0], args[1], TCG_REG_NONE, args[2]);
1732 break;
1733
1734 case INDEX_op_ld16s_i32:
1735 tcg_out_mem(s, RX_LH, RXY_LHY, args[0], args[1], TCG_REG_NONE, args[2]);
1736 break;
1737
1738 case INDEX_op_ld_i32:
1739 tcg_out_ld(s, TCG_TYPE_I32, args[0], args[1], args[2]);
1740 break;
1741
1742 OP_32_64(st8):
1743 tcg_out_mem(s, RX_STC, RXY_STCY, args[0], args[1],
1744 TCG_REG_NONE, args[2]);
1745 break;
1746
1747 OP_32_64(st16):
1748 tcg_out_mem(s, RX_STH, RXY_STHY, args[0], args[1],
1749 TCG_REG_NONE, args[2]);
1750 break;
1751
1752 case INDEX_op_st_i32:
1753 tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]);
1754 break;
1755
1756 case INDEX_op_add_i32:
1757 a0 = args[0], a1 = args[1], a2 = (int32_t)args[2];
1758 if (const_args[2]) {
1759 do_addi_32:
1760 if (a0 == a1) {
1761 if (a2 == (int16_t)a2) {
1762 tcg_out_insn(s, RI, AHI, a0, a2);
1763 break;
1764 }
1765 if (s390_facilities & FACILITY_EXT_IMM) {
1766 tcg_out_insn(s, RIL, AFI, a0, a2);
1767 break;
1768 }
1769 }
1770 tcg_out_mem(s, RX_LA, RXY_LAY, a0, a1, TCG_REG_NONE, a2);
1771 } else if (a0 == a1) {
1772 tcg_out_insn(s, RR, AR, a0, a2);
1773 } else {
1774 tcg_out_insn(s, RX, LA, a0, a1, a2, 0);
1775 }
1776 break;
1777 case INDEX_op_sub_i32:
1778 a0 = args[0], a1 = args[1], a2 = (int32_t)args[2];
1779 if (const_args[2]) {
1780 a2 = -a2;
1781 goto do_addi_32;
1782 } else if (a0 == a1) {
1783 tcg_out_insn(s, RR, SR, a0, a2);
1784 } else {
1785 tcg_out_insn(s, RRF, SRK, a0, a1, a2);
1786 }
1787 break;
1788
1789 case INDEX_op_and_i32:
1790 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];
1791 if (const_args[2]) {
1792 tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
1793 tgen_andi(s, TCG_TYPE_I32, a0, a2);
1794 } else if (a0 == a1) {
1795 tcg_out_insn(s, RR, NR, a0, a2);
1796 } else {
1797 tcg_out_insn(s, RRF, NRK, a0, a1, a2);
1798 }
1799 break;
1800 case INDEX_op_or_i32:
1801 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];
1802 if (const_args[2]) {
1803 tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
1804 tgen64_ori(s, a0, a2);
1805 } else if (a0 == a1) {
1806 tcg_out_insn(s, RR, OR, a0, a2);
1807 } else {
1808 tcg_out_insn(s, RRF, ORK, a0, a1, a2);
1809 }
1810 break;
1811 case INDEX_op_xor_i32:
1812 a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];
1813 if (const_args[2]) {
1814 tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
1815 tgen64_xori(s, a0, a2);
1816 } else if (a0 == a1) {
1817 tcg_out_insn(s, RR, XR, args[0], args[2]);
1818 } else {
1819 tcg_out_insn(s, RRF, XRK, a0, a1, a2);
1820 }
1821 break;
1822
1823 case INDEX_op_neg_i32:
1824 tcg_out_insn(s, RR, LCR, args[0], args[1]);
1825 break;
1826
1827 case INDEX_op_mul_i32:
1828 if (const_args[2]) {
1829 if ((int32_t)args[2] == (int16_t)args[2]) {
1830 tcg_out_insn(s, RI, MHI, args[0], args[2]);
1831 } else {
1832 tcg_out_insn(s, RIL, MSFI, args[0], args[2]);
1833 }
1834 } else {
1835 tcg_out_insn(s, RRE, MSR, args[0], args[2]);
1836 }
1837 break;
1838
1839 case INDEX_op_div2_i32:
1840 tcg_out_insn(s, RR, DR, TCG_REG_R2, args[4]);
1841 break;
1842 case INDEX_op_divu2_i32:
1843 tcg_out_insn(s, RRE, DLR, TCG_REG_R2, args[4]);
1844 break;
1845
1846 case INDEX_op_shl_i32:
1847 op = RS_SLL;
1848 op2 = RSY_SLLK;
1849 do_shift32:
1850 a0 = args[0], a1 = args[1], a2 = (int32_t)args[2];
1851 if (a0 == a1) {
1852 if (const_args[2]) {
1853 tcg_out_sh32(s, op, a0, TCG_REG_NONE, a2);
1854 } else {
1855 tcg_out_sh32(s, op, a0, a2, 0);
1856 }
1857 } else {
1858 /* Using tcg_out_sh64 here for the format; it is a 32-bit shift. */
1859 if (const_args[2]) {
1860 tcg_out_sh64(s, op2, a0, a1, TCG_REG_NONE, a2);
1861 } else {
1862 tcg_out_sh64(s, op2, a0, a1, a2, 0);
1863 }
1864 }
1865 break;
1866 case INDEX_op_shr_i32:
1867 op = RS_SRL;
1868 op2 = RSY_SRLK;
1869 goto do_shift32;
1870 case INDEX_op_sar_i32:
1871 op = RS_SRA;
1872 op2 = RSY_SRAK;
1873 goto do_shift32;
1874
1875 case INDEX_op_rotl_i32:
1876 /* ??? Using tcg_out_sh64 here for the format; it is a 32-bit rol. */
1877 if (const_args[2]) {
1878 tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_REG_NONE, args[2]);
1879 } else {
1880 tcg_out_sh64(s, RSY_RLL, args[0], args[1], args[2], 0);
1881 }
1882 break;
1883 case INDEX_op_rotr_i32:
1884 if (const_args[2]) {
1885 tcg_out_sh64(s, RSY_RLL, args[0], args[1],
1886 TCG_REG_NONE, (32 - args[2]) & 31);
1887 } else {
1888 tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]);
1889 tcg_out_sh64(s, RSY_RLL, args[0], args[1], TCG_TMP0, 0);
1890 }
1891 break;
1892
1893 case INDEX_op_ext8s_i32:
1894 tgen_ext8s(s, TCG_TYPE_I32, args[0], args[1]);
1895 break;
1896 case INDEX_op_ext16s_i32:
1897 tgen_ext16s(s, TCG_TYPE_I32, args[0], args[1]);
1898 break;
1899 case INDEX_op_ext8u_i32:
1900 tgen_ext8u(s, TCG_TYPE_I32, args[0], args[1]);
1901 break;
1902 case INDEX_op_ext16u_i32:
1903 tgen_ext16u(s, TCG_TYPE_I32, args[0], args[1]);
1904 break;
1905
1906 OP_32_64(bswap16):
1907 /* The TCG bswap definition requires bits 0-47 already be zero.
1908 Thus we don't need the G-type insns to implement bswap16_i64. */
1909 tcg_out_insn(s, RRE, LRVR, args[0], args[1]);
1910 tcg_out_sh32(s, RS_SRL, args[0], TCG_REG_NONE, 16);
1911 break;
1912 OP_32_64(bswap32):
1913 tcg_out_insn(s, RRE, LRVR, args[0], args[1]);
1914 break;
1915
1916 case INDEX_op_add2_i32:
1917 if (const_args[4]) {
1918 tcg_out_insn(s, RIL, ALFI, args[0], args[4]);
1919 } else {
1920 tcg_out_insn(s, RR, ALR, args[0], args[4]);
1921 }
1922 tcg_out_insn(s, RRE, ALCR, args[1], args[5]);
1923 break;
1924 case INDEX_op_sub2_i32:
1925 if (const_args[4]) {
1926 tcg_out_insn(s, RIL, SLFI, args[0], args[4]);
1927 } else {
1928 tcg_out_insn(s, RR, SLR, args[0], args[4]);
1929 }
1930 tcg_out_insn(s, RRE, SLBR, args[1], args[5]);
1931 break;
1932
1933 case INDEX_op_br:
1934 tgen_branch(s, S390_CC_ALWAYS, arg_label(args[0]));
1935 break;
1936
1937 case INDEX_op_brcond_i32:
1938 tgen_brcond(s, TCG_TYPE_I32, args[2], args[0],
1939 args[1], const_args[1], arg_label(args[3]));
1940 break;
1941 case INDEX_op_setcond_i32:
1942 tgen_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1],
1943 args[2], const_args[2]);
1944 break;
1945 case INDEX_op_movcond_i32:
1946 tgen_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1],
1947 args[2], const_args[2], args[3], const_args[3]);
1948 break;
1949
1950 case INDEX_op_qemu_ld_i32:
1951 /* ??? Technically we can use a non-extending instruction. */
1952 case INDEX_op_qemu_ld_i64:
1953 tcg_out_qemu_ld(s, args[0], args[1], args[2]);
1954 break;
1955 case INDEX_op_qemu_st_i32:
1956 case INDEX_op_qemu_st_i64:
1957 tcg_out_qemu_st(s, args[0], args[1], args[2]);
1958 break;
1959
1960 case INDEX_op_ld16s_i64:
1961 tcg_out_mem(s, 0, RXY_LGH, args[0], args[1], TCG_REG_NONE, args[2]);
1962 break;
1963 case INDEX_op_ld32u_i64:
1964 tcg_out_mem(s, 0, RXY_LLGF, args[0], args[1], TCG_REG_NONE, args[2]);
1965 break;
1966 case INDEX_op_ld32s_i64:
1967 tcg_out_mem(s, 0, RXY_LGF, args[0], args[1], TCG_REG_NONE, args[2]);
1968 break;
1969 case INDEX_op_ld_i64:
1970 tcg_out_ld(s, TCG_TYPE_I64, args[0], args[1], args[2]);
1971 break;
1972
1973 case INDEX_op_st32_i64:
1974 tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]);
1975 break;
1976 case INDEX_op_st_i64:
1977 tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]);
1978 break;
1979
1980 case INDEX_op_add_i64:
1981 a0 = args[0], a1 = args[1], a2 = args[2];
1982 if (const_args[2]) {
1983 do_addi_64:
1984 if (a0 == a1) {
1985 if (a2 == (int16_t)a2) {
1986 tcg_out_insn(s, RI, AGHI, a0, a2);
1987 break;
1988 }
1989 if (s390_facilities & FACILITY_EXT_IMM) {
1990 if (a2 == (int32_t)a2) {
1991 tcg_out_insn(s, RIL, AGFI, a0, a2);
1992 break;
1993 } else if (a2 == (uint32_t)a2) {
1994 tcg_out_insn(s, RIL, ALGFI, a0, a2);
1995 break;
1996 } else if (-a2 == (uint32_t)-a2) {
1997 tcg_out_insn(s, RIL, SLGFI, a0, -a2);
1998 break;
1999 }
2000 }
2001 }
2002 tcg_out_mem(s, RX_LA, RXY_LAY, a0, a1, TCG_REG_NONE, a2);
2003 } else if (a0 == a1) {
2004 tcg_out_insn(s, RRE, AGR, a0, a2);
2005 } else {
2006 tcg_out_insn(s, RX, LA, a0, a1, a2, 0);
2007 }
2008 break;
2009 case INDEX_op_sub_i64:
2010 a0 = args[0], a1 = args[1], a2 = args[2];
2011 if (const_args[2]) {
2012 a2 = -a2;
2013 goto do_addi_64;
2014 } else if (a0 == a1) {
2015 tcg_out_insn(s, RRE, SGR, a0, a2);
2016 } else {
2017 tcg_out_insn(s, RRF, SGRK, a0, a1, a2);
2018 }
2019 break;
2020
2021 case INDEX_op_and_i64:
2022 a0 = args[0], a1 = args[1], a2 = args[2];
2023 if (const_args[2]) {
2024 tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
2025 tgen_andi(s, TCG_TYPE_I64, args[0], args[2]);
2026 } else if (a0 == a1) {
2027 tcg_out_insn(s, RRE, NGR, args[0], args[2]);
2028 } else {
2029 tcg_out_insn(s, RRF, NGRK, a0, a1, a2);
2030 }
2031 break;
2032 case INDEX_op_or_i64:
2033 a0 = args[0], a1 = args[1], a2 = args[2];
2034 if (const_args[2]) {
2035 tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
2036 tgen64_ori(s, a0, a2);
2037 } else if (a0 == a1) {
2038 tcg_out_insn(s, RRE, OGR, a0, a2);
2039 } else {
2040 tcg_out_insn(s, RRF, OGRK, a0, a1, a2);
2041 }
2042 break;
2043 case INDEX_op_xor_i64:
2044 a0 = args[0], a1 = args[1], a2 = args[2];
2045 if (const_args[2]) {
2046 tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
2047 tgen64_xori(s, a0, a2);
2048 } else if (a0 == a1) {
2049 tcg_out_insn(s, RRE, XGR, a0, a2);
2050 } else {
2051 tcg_out_insn(s, RRF, XGRK, a0, a1, a2);
2052 }
2053 break;
2054
2055 case INDEX_op_neg_i64:
2056 tcg_out_insn(s, RRE, LCGR, args[0], args[1]);
2057 break;
2058 case INDEX_op_bswap64_i64:
2059 tcg_out_insn(s, RRE, LRVGR, args[0], args[1]);
2060 break;
2061
2062 case INDEX_op_mul_i64:
2063 if (const_args[2]) {
2064 if (args[2] == (int16_t)args[2]) {
2065 tcg_out_insn(s, RI, MGHI, args[0], args[2]);
2066 } else {
2067 tcg_out_insn(s, RIL, MSGFI, args[0], args[2]);
2068 }
2069 } else {
2070 tcg_out_insn(s, RRE, MSGR, args[0], args[2]);
2071 }
2072 break;
2073
2074 case INDEX_op_div2_i64:
2075 /* ??? We get an unnecessary sign-extension of the dividend
2076 into R3 with this definition, but as we do in fact always
2077 produce both quotient and remainder using INDEX_op_div_i64
2078 instead requires jumping through even more hoops. */
2079 tcg_out_insn(s, RRE, DSGR, TCG_REG_R2, args[4]);
2080 break;
2081 case INDEX_op_divu2_i64:
2082 tcg_out_insn(s, RRE, DLGR, TCG_REG_R2, args[4]);
2083 break;
2084 case INDEX_op_mulu2_i64:
2085 tcg_out_insn(s, RRE, MLGR, TCG_REG_R2, args[3]);
2086 break;
2087
2088 case INDEX_op_shl_i64:
2089 op = RSY_SLLG;
2090 do_shift64:
2091 if (const_args[2]) {
2092 tcg_out_sh64(s, op, args[0], args[1], TCG_REG_NONE, args[2]);
2093 } else {
2094 tcg_out_sh64(s, op, args[0], args[1], args[2], 0);
2095 }
2096 break;
2097 case INDEX_op_shr_i64:
2098 op = RSY_SRLG;
2099 goto do_shift64;
2100 case INDEX_op_sar_i64:
2101 op = RSY_SRAG;
2102 goto do_shift64;
2103
2104 case INDEX_op_rotl_i64:
2105 if (const_args[2]) {
2106 tcg_out_sh64(s, RSY_RLLG, args[0], args[1],
2107 TCG_REG_NONE, args[2]);
2108 } else {
2109 tcg_out_sh64(s, RSY_RLLG, args[0], args[1], args[2], 0);
2110 }
2111 break;
2112 case INDEX_op_rotr_i64:
2113 if (const_args[2]) {
2114 tcg_out_sh64(s, RSY_RLLG, args[0], args[1],
2115 TCG_REG_NONE, (64 - args[2]) & 63);
2116 } else {
2117 /* We can use the smaller 32-bit negate because only the
2118 low 6 bits are examined for the rotate. */
2119 tcg_out_insn(s, RR, LCR, TCG_TMP0, args[2]);
2120 tcg_out_sh64(s, RSY_RLLG, args[0], args[1], TCG_TMP0, 0);
2121 }
2122 break;
2123
2124 case INDEX_op_ext8s_i64:
2125 tgen_ext8s(s, TCG_TYPE_I64, args[0], args[1]);
2126 break;
2127 case INDEX_op_ext16s_i64:
2128 tgen_ext16s(s, TCG_TYPE_I64, args[0], args[1]);
2129 break;
2130 case INDEX_op_ext_i32_i64:
2131 case INDEX_op_ext32s_i64:
2132 tgen_ext32s(s, args[0], args[1]);
2133 break;
2134 case INDEX_op_ext8u_i64:
2135 tgen_ext8u(s, TCG_TYPE_I64, args[0], args[1]);
2136 break;
2137 case INDEX_op_ext16u_i64:
2138 tgen_ext16u(s, TCG_TYPE_I64, args[0], args[1]);
2139 break;
2140 case INDEX_op_extu_i32_i64:
2141 case INDEX_op_ext32u_i64:
2142 tgen_ext32u(s, args[0], args[1]);
2143 break;
2144
2145 case INDEX_op_add2_i64:
2146 if (const_args[4]) {
2147 if ((int64_t)args[4] >= 0) {
2148 tcg_out_insn(s, RIL, ALGFI, args[0], args[4]);
2149 } else {
2150 tcg_out_insn(s, RIL, SLGFI, args[0], -args[4]);
2151 }
2152 } else {
2153 tcg_out_insn(s, RRE, ALGR, args[0], args[4]);
2154 }
2155 tcg_out_insn(s, RRE, ALCGR, args[1], args[5]);
2156 break;
2157 case INDEX_op_sub2_i64:
2158 if (const_args[4]) {
2159 if ((int64_t)args[4] >= 0) {
2160 tcg_out_insn(s, RIL, SLGFI, args[0], args[4]);
2161 } else {
2162 tcg_out_insn(s, RIL, ALGFI, args[0], -args[4]);
2163 }
2164 } else {
2165 tcg_out_insn(s, RRE, SLGR, args[0], args[4]);
2166 }
2167 tcg_out_insn(s, RRE, SLBGR, args[1], args[5]);
2168 break;
2169
2170 case INDEX_op_brcond_i64:
2171 tgen_brcond(s, TCG_TYPE_I64, args[2], args[0],
2172 args[1], const_args[1], arg_label(args[3]));
2173 break;
2174 case INDEX_op_setcond_i64:
2175 tgen_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1],
2176 args[2], const_args[2]);
2177 break;
2178 case INDEX_op_movcond_i64:
2179 tgen_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1],
2180 args[2], const_args[2], args[3], const_args[3]);
2181 break;
2182
2183 OP_32_64(deposit):
2184 a0 = args[0], a1 = args[1], a2 = args[2];
2185 if (const_args[1]) {
2186 tgen_deposit(s, a0, a2, args[3], args[4], 1);
2187 } else {
2188 /* Since we can't support "0Z" as a constraint, we allow a1 in
2189 any register. Fix things up as if a matching constraint. */
2190 if (a0 != a1) {
2191 TCGType type = (opc == INDEX_op_deposit_i64);
2192 if (a0 == a2) {
2193 tcg_out_mov(s, type, TCG_TMP0, a2);
2194 a2 = TCG_TMP0;
2195 }
2196 tcg_out_mov(s, type, a0, a1);
2197 }
2198 tgen_deposit(s, a0, a2, args[3], args[4], 0);
2199 }
2200 break;
2201
2202 OP_32_64(extract):
2203 tgen_extract(s, args[0], args[1], args[2], args[3]);
2204 break;
2205
2206 case INDEX_op_clz_i64:
2207 tgen_clz(s, args[0], args[1], args[2], const_args[2]);
2208 break;
2209
2210 case INDEX_op_mb:
2211 /* The host memory model is quite strong, we simply need to
2212 serialize the instruction stream. */
2213 if (args[0] & TCG_MO_ST_LD) {
2214 tcg_out_insn(s, RR, BCR,
2215 s390_facilities & FACILITY_FAST_BCR_SER ? 14 : 15, 0);
2216 }
2217 break;
2218
2219 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
2220 case INDEX_op_mov_i64:
2221 case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
2222 case INDEX_op_movi_i64:
2223 case INDEX_op_call: /* Always emitted via tcg_out_call. */
2224 default:
2225 tcg_abort();
2226 }
2227 }
2228
2229 static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
2230 {
2231 static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
2232 static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
2233 static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
2234 static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } };
2235 static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } };
2236 static const TCGTargetOpDef r_rC = { .args_ct_str = { "r", "rC" } };
2237 static const TCGTargetOpDef r_rZ = { .args_ct_str = { "r", "rZ" } };
2238 static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
2239 static const TCGTargetOpDef r_r_rM = { .args_ct_str = { "r", "r", "rM" } };
2240 static const TCGTargetOpDef r_0_r = { .args_ct_str = { "r", "0", "r" } };
2241 static const TCGTargetOpDef r_0_ri = { .args_ct_str = { "r", "0", "ri" } };
2242 static const TCGTargetOpDef r_0_rI = { .args_ct_str = { "r", "0", "rI" } };
2243 static const TCGTargetOpDef r_0_rJ = { .args_ct_str = { "r", "0", "rJ" } };
2244 static const TCGTargetOpDef r_0_rN = { .args_ct_str = { "r", "0", "rN" } };
2245 static const TCGTargetOpDef r_0_rM = { .args_ct_str = { "r", "0", "rM" } };
2246 static const TCGTargetOpDef a2_r
2247 = { .args_ct_str = { "r", "r", "0", "1", "r", "r" } };
2248 static const TCGTargetOpDef a2_ri
2249 = { .args_ct_str = { "r", "r", "0", "1", "ri", "r" } };
2250 static const TCGTargetOpDef a2_rA
2251 = { .args_ct_str = { "r", "r", "0", "1", "rA", "r" } };
2252
2253 switch (op) {
2254 case INDEX_op_goto_ptr:
2255 return &r;
2256
2257 case INDEX_op_ld8u_i32:
2258 case INDEX_op_ld8u_i64:
2259 case INDEX_op_ld8s_i32:
2260 case INDEX_op_ld8s_i64:
2261 case INDEX_op_ld16u_i32:
2262 case INDEX_op_ld16u_i64:
2263 case INDEX_op_ld16s_i32:
2264 case INDEX_op_ld16s_i64:
2265 case INDEX_op_ld_i32:
2266 case INDEX_op_ld32u_i64:
2267 case INDEX_op_ld32s_i64:
2268 case INDEX_op_ld_i64:
2269 case INDEX_op_st8_i32:
2270 case INDEX_op_st8_i64:
2271 case INDEX_op_st16_i32:
2272 case INDEX_op_st16_i64:
2273 case INDEX_op_st_i32:
2274 case INDEX_op_st32_i64:
2275 case INDEX_op_st_i64:
2276 return &r_r;
2277
2278 case INDEX_op_add_i32:
2279 case INDEX_op_add_i64:
2280 return &r_r_ri;
2281 case INDEX_op_sub_i32:
2282 case INDEX_op_sub_i64:
2283 return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri);
2284
2285 case INDEX_op_mul_i32:
2286 /* If we have the general-instruction-extensions, then we have
2287 MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we
2288 have only MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */
2289 return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_ri : &r_0_rI);
2290 case INDEX_op_mul_i64:
2291 return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_rI);
2292
2293 case INDEX_op_or_i32:
2294 /* The use of [iNM] constraints are optimization only, since a full
2295 64-bit immediate OR can always be performed with 4 sequential
2296 OI[LH][LH] instructions. By rejecting certain negative ranges,
2297 the immediate load plus the reg-reg OR is smaller. */
2298 return (s390_facilities & FACILITY_EXT_IMM
2299 ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri)
2300 : &r_0_rN);
2301 case INDEX_op_or_i64:
2302 return (s390_facilities & FACILITY_EXT_IMM
2303 ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_rM : &r_0_rM)
2304 : &r_0_rN);
2305
2306 case INDEX_op_xor_i32:
2307 /* Without EXT_IMM, no immediates are supported. Otherwise,
2308 rejecting certain negative ranges leads to smaller code. */
2309 return (s390_facilities & FACILITY_EXT_IMM
2310 ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri)
2311 : &r_0_r);
2312 case INDEX_op_xor_i64:
2313 return (s390_facilities & FACILITY_EXT_IMM
2314 ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_rM : &r_0_rM)
2315 : &r_0_r);
2316
2317 case INDEX_op_and_i32:
2318 case INDEX_op_and_i64:
2319 return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri);
2320
2321 case INDEX_op_shl_i32:
2322 case INDEX_op_shr_i32:
2323 case INDEX_op_sar_i32:
2324 return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri);
2325
2326 case INDEX_op_shl_i64:
2327 case INDEX_op_shr_i64:
2328 case INDEX_op_sar_i64:
2329 return &r_r_ri;
2330
2331 case INDEX_op_rotl_i32:
2332 case INDEX_op_rotl_i64:
2333 case INDEX_op_rotr_i32:
2334 case INDEX_op_rotr_i64:
2335 return &r_r_ri;
2336
2337 case INDEX_op_brcond_i32:
2338 /* Without EXT_IMM, only the LOAD AND TEST insn is available. */
2339 return (s390_facilities & FACILITY_EXT_IMM ? &r_ri : &r_rZ);
2340 case INDEX_op_brcond_i64:
2341 return (s390_facilities & FACILITY_EXT_IMM ? &r_rC : &r_rZ);
2342
2343 case INDEX_op_bswap16_i32:
2344 case INDEX_op_bswap16_i64:
2345 case INDEX_op_bswap32_i32:
2346 case INDEX_op_bswap32_i64:
2347 case INDEX_op_bswap64_i64:
2348 case INDEX_op_neg_i32:
2349 case INDEX_op_neg_i64:
2350 case INDEX_op_ext8s_i32:
2351 case INDEX_op_ext8s_i64:
2352 case INDEX_op_ext8u_i32:
2353 case INDEX_op_ext8u_i64:
2354 case INDEX_op_ext16s_i32:
2355 case INDEX_op_ext16s_i64:
2356 case INDEX_op_ext16u_i32:
2357 case INDEX_op_ext16u_i64:
2358 case INDEX_op_ext32s_i64:
2359 case INDEX_op_ext32u_i64:
2360 case INDEX_op_ext_i32_i64:
2361 case INDEX_op_extu_i32_i64:
2362 case INDEX_op_extract_i32:
2363 case INDEX_op_extract_i64:
2364 return &r_r;
2365
2366 case INDEX_op_clz_i64:
2367 return &r_r_ri;
2368
2369 case INDEX_op_qemu_ld_i32:
2370 case INDEX_op_qemu_ld_i64:
2371 return &r_L;
2372 case INDEX_op_qemu_st_i64:
2373 case INDEX_op_qemu_st_i32:
2374 return &L_L;
2375
2376 case INDEX_op_deposit_i32:
2377 case INDEX_op_deposit_i64:
2378 {
2379 static const TCGTargetOpDef dep
2380 = { .args_ct_str = { "r", "rZ", "r" } };
2381 return &dep;
2382 }
2383 case INDEX_op_setcond_i32:
2384 case INDEX_op_setcond_i64:
2385 {
2386 /* Without EXT_IMM, only the LOAD AND TEST insn is available. */
2387 static const TCGTargetOpDef setc_z
2388 = { .args_ct_str = { "r", "r", "rZ" } };
2389 static const TCGTargetOpDef setc_c
2390 = { .args_ct_str = { "r", "r", "rC" } };
2391 return (s390_facilities & FACILITY_EXT_IMM ? &setc_c : &setc_z);
2392 }
2393 case INDEX_op_movcond_i32:
2394 case INDEX_op_movcond_i64:
2395 {
2396 /* Without EXT_IMM, only the LOAD AND TEST insn is available. */
2397 static const TCGTargetOpDef movc_z
2398 = { .args_ct_str = { "r", "r", "rZ", "r", "0" } };
2399 static const TCGTargetOpDef movc_c
2400 = { .args_ct_str = { "r", "r", "rC", "r", "0" } };
2401 static const TCGTargetOpDef movc_l
2402 = { .args_ct_str = { "r", "r", "rC", "rI", "0" } };
2403 return (s390_facilities & FACILITY_EXT_IMM
2404 ? (s390_facilities & FACILITY_LOAD_ON_COND2
2405 ? &movc_l : &movc_c)
2406 : &movc_z);
2407 }
2408 case INDEX_op_div2_i32:
2409 case INDEX_op_div2_i64:
2410 case INDEX_op_divu2_i32:
2411 case INDEX_op_divu2_i64:
2412 {
2413 static const TCGTargetOpDef div2
2414 = { .args_ct_str = { "b", "a", "0", "1", "r" } };
2415 return &div2;
2416 }
2417 case INDEX_op_mulu2_i64:
2418 {
2419 static const TCGTargetOpDef mul2
2420 = { .args_ct_str = { "b", "a", "0", "r" } };
2421 return &mul2;
2422 }
2423
2424 case INDEX_op_add2_i32:
2425 case INDEX_op_sub2_i32:
2426 return (s390_facilities & FACILITY_EXT_IMM ? &a2_ri : &a2_r);
2427 case INDEX_op_add2_i64:
2428 case INDEX_op_sub2_i64:
2429 return (s390_facilities & FACILITY_EXT_IMM ? &a2_rA : &a2_r);
2430
2431 default:
2432 break;
2433 }
2434 return NULL;
2435 }
2436
2437 static void query_s390_facilities(void)
2438 {
2439 unsigned long hwcap = qemu_getauxval(AT_HWCAP);
2440
2441 /* Is STORE FACILITY LIST EXTENDED available? Honestly, I believe this
2442 is present on all 64-bit systems, but let's check for it anyway. */
2443 if (hwcap & HWCAP_S390_STFLE) {
2444 register int r0 __asm__("0");
2445 register void *r1 __asm__("1");
2446
2447 /* stfle 0(%r1) */
2448 r1 = &s390_facilities;
2449 asm volatile(".word 0xb2b0,0x1000"
2450 : "=r"(r0) : "0"(0), "r"(r1) : "memory", "cc");
2451 }
2452 }
2453
2454 static void tcg_target_init(TCGContext *s)
2455 {
2456 query_s390_facilities();
2457
2458 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
2459 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff);
2460
2461 tcg_regset_clear(tcg_target_call_clobber_regs);
2462 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);
2463 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1);
2464 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2);
2465 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3);
2466 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4);
2467 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5);
2468 /* The r6 register is technically call-saved, but it's also a parameter
2469 register, so it can get killed by setup for the qemu_st helper. */
2470 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6);
2471 /* The return register can be considered call-clobbered. */
2472 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14);
2473
2474 tcg_regset_clear(s->reserved_regs);
2475 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0);
2476 /* XXX many insns can't be used with R0, so we better avoid it for now */
2477 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0);
2478 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
2479 }
2480
2481 #define FRAME_SIZE ((int)(TCG_TARGET_CALL_STACK_OFFSET \
2482 + TCG_STATIC_CALL_ARGS_SIZE \
2483 + CPU_TEMP_BUF_NLONGS * sizeof(long)))
2484
2485 static void tcg_target_qemu_prologue(TCGContext *s)
2486 {
2487 /* stmg %r6,%r15,48(%r15) (save registers) */
2488 tcg_out_insn(s, RXY, STMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15, 48);
2489
2490 /* aghi %r15,-frame_size */
2491 tcg_out_insn(s, RI, AGHI, TCG_REG_R15, -FRAME_SIZE);
2492
2493 tcg_set_frame(s, TCG_REG_CALL_STACK,
2494 TCG_STATIC_CALL_ARGS_SIZE + TCG_TARGET_CALL_STACK_OFFSET,
2495 CPU_TEMP_BUF_NLONGS * sizeof(long));
2496
2497 #ifndef CONFIG_SOFTMMU
2498 if (guest_base >= 0x80000) {
2499 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
2500 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2501 }
2502 #endif
2503
2504 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
2505 /* br %r3 (go to TB) */
2506 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, tcg_target_call_iarg_regs[1]);
2507
2508 /*
2509 * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
2510 * and fall through to the rest of the epilogue.
2511 */
2512 s->code_gen_epilogue = s->code_ptr;
2513 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, 0);
2514
2515 /* TB epilogue */
2516 tb_ret_addr = s->code_ptr;
2517
2518 /* lmg %r6,%r15,fs+48(%r15) (restore registers) */
2519 tcg_out_insn(s, RXY, LMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15,
2520 FRAME_SIZE + 48);
2521
2522 /* br %r14 (return) */
2523 tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_R14);
2524 }
2525
2526 typedef struct {
2527 DebugFrameHeader h;
2528 uint8_t fde_def_cfa[4];
2529 uint8_t fde_reg_ofs[18];
2530 } DebugFrame;
2531
2532 /* We're expecting a 2 byte uleb128 encoded value. */
2533 QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
2534
2535 #define ELF_HOST_MACHINE EM_S390
2536
2537 static const DebugFrame debug_frame = {
2538 .h.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
2539 .h.cie.id = -1,
2540 .h.cie.version = 1,
2541 .h.cie.code_align = 1,
2542 .h.cie.data_align = 8, /* sleb128 8 */
2543 .h.cie.return_column = TCG_REG_R14,
2544
2545 /* Total FDE size does not include the "len" member. */
2546 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
2547
2548 .fde_def_cfa = {
2549 12, TCG_REG_CALL_STACK, /* DW_CFA_def_cfa %r15, ... */
2550 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2551 (FRAME_SIZE >> 7)
2552 },
2553 .fde_reg_ofs = {
2554 0x86, 6, /* DW_CFA_offset, %r6, 48 */
2555 0x87, 7, /* DW_CFA_offset, %r7, 56 */
2556 0x88, 8, /* DW_CFA_offset, %r8, 64 */
2557 0x89, 9, /* DW_CFA_offset, %r92, 72 */
2558 0x8a, 10, /* DW_CFA_offset, %r10, 80 */
2559 0x8b, 11, /* DW_CFA_offset, %r11, 88 */
2560 0x8c, 12, /* DW_CFA_offset, %r12, 96 */
2561 0x8d, 13, /* DW_CFA_offset, %r13, 104 */
2562 0x8e, 14, /* DW_CFA_offset, %r14, 112 */
2563 }
2564 };
2565
2566 void tcg_register_jit(void *buf, size_t buf_size)
2567 {
2568 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
2569 }
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