4 * Copyright (c) 2014 John Snow <jsnow@redhat.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
29 #include "libqos/libqos-pc.h"
30 #include "libqos/ahci.h"
31 #include "libqos/pci-pc.h"
33 #include "qemu-common.h"
34 #include "qapi/qmp/qdict.h"
35 #include "qemu/host-utils.h"
37 #include "hw/pci/pci_ids.h"
38 #include "hw/pci/pci_regs.h"
40 /* Test images sizes in MB */
41 #define TEST_IMAGE_SIZE_MB_LARGE (200 * 1024)
42 #define TEST_IMAGE_SIZE_MB_SMALL 64
45 static char tmp_path
[] = "/tmp/qtest.XXXXXX";
46 static char debug_path
[] = "/tmp/qtest-blkdebug.XXXXXX";
47 static char mig_socket
[] = "/tmp/qtest-migration.XXXXXX";
48 static bool ahci_pedantic
;
49 static const char *imgfmt
;
50 static unsigned test_image_size_mb
;
52 /*** Function Declarations ***/
53 static void ahci_test_port_spec(AHCIQState
*ahci
, uint8_t port
);
54 static void ahci_test_pci_spec(AHCIQState
*ahci
);
55 static void ahci_test_pci_caps(AHCIQState
*ahci
, uint16_t header
,
57 static void ahci_test_satacap(AHCIQState
*ahci
, uint8_t offset
);
58 static void ahci_test_msicap(AHCIQState
*ahci
, uint8_t offset
);
59 static void ahci_test_pmcap(AHCIQState
*ahci
, uint8_t offset
);
63 static uint64_t mb_to_sectors(uint64_t image_size_mb
)
65 return (image_size_mb
* 1024 * 1024) / AHCI_SECTOR_SIZE
;
68 static void string_bswap16(uint16_t *s
, size_t bytes
)
70 g_assert_cmphex((bytes
& 1), ==, 0);
80 * Verify that the transfer did not corrupt our state at all.
82 static void verify_state(AHCIQState
*ahci
, uint64_t hba_old
)
85 uint32_t ahci_fingerprint
;
87 AHCICommandHeader cmd
;
89 ahci_fingerprint
= qpci_config_readl(ahci
->dev
, PCI_VENDOR_ID
);
90 g_assert_cmphex(ahci_fingerprint
, ==, ahci
->fingerprint
);
92 /* If we haven't initialized, this is as much as can be validated. */
97 hba_base
= (uint64_t)qpci_config_readl(ahci
->dev
, PCI_BASE_ADDRESS_5
);
98 g_assert_cmphex(hba_base
, ==, hba_old
);
100 g_assert_cmphex(ahci_rreg(ahci
, AHCI_CAP
), ==, ahci
->cap
);
101 g_assert_cmphex(ahci_rreg(ahci
, AHCI_CAP2
), ==, ahci
->cap2
);
103 for (i
= 0; i
< 32; i
++) {
104 g_assert_cmphex(ahci_px_rreg(ahci
, i
, AHCI_PX_FB
), ==,
106 g_assert_cmphex(ahci_px_rreg(ahci
, i
, AHCI_PX_CLB
), ==,
108 for (j
= 0; j
< 32; j
++) {
109 ahci_get_command_header(ahci
, i
, j
, &cmd
);
110 g_assert_cmphex(cmd
.prdtl
, ==, ahci
->port
[i
].prdtl
[j
]);
111 g_assert_cmphex(cmd
.ctba
, ==, ahci
->port
[i
].ctba
[j
]);
116 static void ahci_migrate(AHCIQState
*from
, AHCIQState
*to
, const char *uri
)
118 QOSState
*tmp
= to
->parent
;
119 QPCIDevice
*dev
= to
->dev
;
120 char *uri_local
= NULL
;
124 uri_local
= g_strdup_printf("%s%s", "unix:", mig_socket
);
128 hba_old
= (uint64_t)qpci_config_readl(from
->dev
, PCI_BASE_ADDRESS_5
);
130 /* context will be 'to' after completion. */
131 migrate(from
->parent
, to
->parent
, uri
);
133 /* We'd like for the AHCIState objects to still point
134 * to information specific to its specific parent
135 * instance, but otherwise just inherit the new data. */
136 memcpy(to
, from
, sizeof(AHCIQState
));
142 memset(from
, 0x00, sizeof(AHCIQState
));
146 verify_state(to
, hba_old
);
150 /*** Test Setup & Teardown ***/
153 * Start a Q35 machine and bookmark a handle to the AHCI device.
155 static AHCIQState
*ahci_vboot(const char *cli
, va_list ap
)
159 s
= g_new0(AHCIQState
, 1);
160 s
->parent
= qtest_pc_vboot(cli
, ap
);
161 alloc_set_flags(s
->parent
->alloc
, ALLOC_LEAK_ASSERT
);
163 /* Verify that we have an AHCI device present. */
164 s
->dev
= get_ahci_device(&s
->fingerprint
);
170 * Start a Q35 machine and bookmark a handle to the AHCI device.
172 static AHCIQState
*ahci_boot(const char *cli
, ...)
179 s
= ahci_vboot(cli
, ap
);
182 cli
= "-drive if=none,id=drive0,file=%s,cache=writeback,serial=%s"
185 "-device ide-hd,drive=drive0 "
186 "-global ide-hd.ver=%s";
187 s
= ahci_boot(cli
, tmp_path
, "testdisk", imgfmt
, "version");
194 * Clean up the PCI device, then terminate the QEMU instance.
196 static void ahci_shutdown(AHCIQState
*ahci
)
198 QOSState
*qs
= ahci
->parent
;
201 ahci_clean_mem(ahci
);
202 free_ahci_device(ahci
->dev
);
208 * Boot and fully enable the HBA device.
209 * @see ahci_boot, ahci_pci_enable and ahci_hba_enable.
211 static AHCIQState
*ahci_boot_and_enable(const char *cli
, ...)
221 ahci
= ahci_vboot(cli
, ap
);
224 ahci
= ahci_boot(NULL
);
227 ahci_pci_enable(ahci
);
228 ahci_hba_enable(ahci
);
229 /* Initialize test device */
230 port
= ahci_port_select(ahci
);
231 ahci_port_clear(ahci
, port
);
232 if (is_atapi(ahci
, port
)) {
233 hello
= CMD_PACKET_ID
;
235 hello
= CMD_IDENTIFY
;
237 ahci_io(ahci
, port
, hello
, &buff
, sizeof(buff
), 0);
242 /*** Specification Adherence Tests ***/
245 * Implementation for test_pci_spec. Ensures PCI configuration space is sane.
247 static void ahci_test_pci_spec(AHCIQState
*ahci
)
253 /* Most of these bits should start cleared until we turn them on. */
254 data
= qpci_config_readw(ahci
->dev
, PCI_COMMAND
);
255 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_MEMORY
);
256 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_MASTER
);
257 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_SPECIAL
); /* Reserved */
258 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_VGA_PALETTE
); /* Reserved */
259 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_PARITY
);
260 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_WAIT
); /* Reserved */
261 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_SERR
);
262 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_FAST_BACK
);
263 ASSERT_BIT_CLEAR(data
, PCI_COMMAND_INTX_DISABLE
);
264 ASSERT_BIT_CLEAR(data
, 0xF800); /* Reserved */
266 data
= qpci_config_readw(ahci
->dev
, PCI_STATUS
);
267 ASSERT_BIT_CLEAR(data
, 0x01 | 0x02 | 0x04); /* Reserved */
268 ASSERT_BIT_CLEAR(data
, PCI_STATUS_INTERRUPT
);
269 ASSERT_BIT_SET(data
, PCI_STATUS_CAP_LIST
); /* must be set */
270 ASSERT_BIT_CLEAR(data
, PCI_STATUS_UDF
); /* Reserved */
271 ASSERT_BIT_CLEAR(data
, PCI_STATUS_PARITY
);
272 ASSERT_BIT_CLEAR(data
, PCI_STATUS_SIG_TARGET_ABORT
);
273 ASSERT_BIT_CLEAR(data
, PCI_STATUS_REC_TARGET_ABORT
);
274 ASSERT_BIT_CLEAR(data
, PCI_STATUS_REC_MASTER_ABORT
);
275 ASSERT_BIT_CLEAR(data
, PCI_STATUS_SIG_SYSTEM_ERROR
);
276 ASSERT_BIT_CLEAR(data
, PCI_STATUS_DETECTED_PARITY
);
278 /* RID occupies the low byte, CCs occupy the high three. */
279 datal
= qpci_config_readl(ahci
->dev
, PCI_CLASS_REVISION
);
281 /* AHCI 1.3 specifies that at-boot, the RID should reset to 0x00,
282 * Though in practice this is likely seldom true. */
283 ASSERT_BIT_CLEAR(datal
, 0xFF);
286 /* BCC *must* equal 0x01. */
287 g_assert_cmphex(PCI_BCC(datal
), ==, 0x01);
288 if (PCI_SCC(datal
) == 0x01) {
290 ASSERT_BIT_SET(0x80000000, datal
);
291 ASSERT_BIT_CLEAR(0x60000000, datal
);
292 } else if (PCI_SCC(datal
) == 0x04) {
294 g_assert_cmphex(PCI_PI(datal
), ==, 0);
295 } else if (PCI_SCC(datal
) == 0x06) {
297 g_assert_cmphex(PCI_PI(datal
), ==, 0x01);
299 g_assert_not_reached();
302 datab
= qpci_config_readb(ahci
->dev
, PCI_CACHE_LINE_SIZE
);
303 g_assert_cmphex(datab
, ==, 0);
305 datab
= qpci_config_readb(ahci
->dev
, PCI_LATENCY_TIMER
);
306 g_assert_cmphex(datab
, ==, 0);
308 /* Only the bottom 7 bits must be off. */
309 datab
= qpci_config_readb(ahci
->dev
, PCI_HEADER_TYPE
);
310 ASSERT_BIT_CLEAR(datab
, 0x7F);
312 /* BIST is optional, but the low 7 bits must always start off regardless. */
313 datab
= qpci_config_readb(ahci
->dev
, PCI_BIST
);
314 ASSERT_BIT_CLEAR(datab
, 0x7F);
316 /* BARS 0-4 do not have a boot spec, but ABAR/BAR5 must be clean. */
317 datal
= qpci_config_readl(ahci
->dev
, PCI_BASE_ADDRESS_5
);
318 g_assert_cmphex(datal
, ==, 0);
320 qpci_config_writel(ahci
->dev
, PCI_BASE_ADDRESS_5
, 0xFFFFFFFF);
321 datal
= qpci_config_readl(ahci
->dev
, PCI_BASE_ADDRESS_5
);
322 /* ABAR must be 32-bit, memory mapped, non-prefetchable and
323 * must be >= 512 bytes. To that end, bits 0-8 must be off. */
324 ASSERT_BIT_CLEAR(datal
, 0xFF);
326 /* Capability list MUST be present, */
327 datal
= qpci_config_readl(ahci
->dev
, PCI_CAPABILITY_LIST
);
328 /* But these bits are reserved. */
329 ASSERT_BIT_CLEAR(datal
, ~0xFF);
330 g_assert_cmphex(datal
, !=, 0);
332 /* Check specification adherence for capability extenstions. */
333 data
= qpci_config_readw(ahci
->dev
, datal
);
335 switch (ahci
->fingerprint
) {
336 case AHCI_INTEL_ICH9
:
337 /* Intel ICH9 Family Datasheet 14.1.19 p.550 */
338 g_assert_cmphex((data
& 0xFF), ==, PCI_CAP_ID_MSI
);
341 /* AHCI 1.3, Section 2.1.14 -- CAP must point to PMCAP. */
342 g_assert_cmphex((data
& 0xFF), ==, PCI_CAP_ID_PM
);
345 ahci_test_pci_caps(ahci
, data
, (uint8_t)datal
);
348 datal
= qpci_config_readl(ahci
->dev
, PCI_CAPABILITY_LIST
+ 4);
349 g_assert_cmphex(datal
, ==, 0);
351 /* IPIN might vary, but ILINE must be off. */
352 datab
= qpci_config_readb(ahci
->dev
, PCI_INTERRUPT_LINE
);
353 g_assert_cmphex(datab
, ==, 0);
357 * Test PCI capabilities for AHCI specification adherence.
359 static void ahci_test_pci_caps(AHCIQState
*ahci
, uint16_t header
,
362 uint8_t cid
= header
& 0xFF;
363 uint8_t next
= header
>> 8;
365 g_test_message("CID: %02x; next: %02x", cid
, next
);
369 ahci_test_pmcap(ahci
, offset
);
372 ahci_test_msicap(ahci
, offset
);
374 case PCI_CAP_ID_SATA
:
375 ahci_test_satacap(ahci
, offset
);
379 g_test_message("Unknown CAP 0x%02x", cid
);
383 ahci_test_pci_caps(ahci
, qpci_config_readw(ahci
->dev
, next
), next
);
388 * Test SATA PCI capabilitity for AHCI specification adherence.
390 static void ahci_test_satacap(AHCIQState
*ahci
, uint8_t offset
)
395 g_test_message("Verifying SATACAP");
397 /* Assert that the SATACAP version is 1.0, And reserved bits are empty. */
398 dataw
= qpci_config_readw(ahci
->dev
, offset
+ 2);
399 g_assert_cmphex(dataw
, ==, 0x10);
401 /* Grab the SATACR1 register. */
402 datal
= qpci_config_readw(ahci
->dev
, offset
+ 4);
404 switch (datal
& 0x0F) {
405 case 0x04: /* BAR0 */
406 case 0x05: /* BAR1 */
410 case 0x09: /* BAR5 */
411 case 0x0F: /* Immediately following SATACR1 in PCI config space. */
414 /* Invalid BARLOC for the Index Data Pair. */
415 g_assert_not_reached();
419 g_assert_cmphex((datal
>> 24), ==, 0x00);
423 * Test MSI PCI capability for AHCI specification adherence.
425 static void ahci_test_msicap(AHCIQState
*ahci
, uint8_t offset
)
430 g_test_message("Verifying MSICAP");
432 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_MSI_FLAGS
);
433 ASSERT_BIT_CLEAR(dataw
, PCI_MSI_FLAGS_ENABLE
);
434 ASSERT_BIT_CLEAR(dataw
, PCI_MSI_FLAGS_QSIZE
);
435 ASSERT_BIT_CLEAR(dataw
, PCI_MSI_FLAGS_RESERVED
);
437 datal
= qpci_config_readl(ahci
->dev
, offset
+ PCI_MSI_ADDRESS_LO
);
438 g_assert_cmphex(datal
, ==, 0);
440 if (dataw
& PCI_MSI_FLAGS_64BIT
) {
441 g_test_message("MSICAP is 64bit");
442 datal
= qpci_config_readl(ahci
->dev
, offset
+ PCI_MSI_ADDRESS_HI
);
443 g_assert_cmphex(datal
, ==, 0);
444 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_MSI_DATA_64
);
445 g_assert_cmphex(dataw
, ==, 0);
447 g_test_message("MSICAP is 32bit");
448 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_MSI_DATA_32
);
449 g_assert_cmphex(dataw
, ==, 0);
454 * Test Power Management PCI capability for AHCI specification adherence.
456 static void ahci_test_pmcap(AHCIQState
*ahci
, uint8_t offset
)
460 g_test_message("Verifying PMCAP");
462 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_PM_PMC
);
463 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CAP_PME_CLOCK
);
464 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CAP_RESERVED
);
465 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CAP_D1
);
466 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CAP_D2
);
468 dataw
= qpci_config_readw(ahci
->dev
, offset
+ PCI_PM_CTRL
);
469 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CTRL_STATE_MASK
);
470 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CTRL_RESERVED
);
471 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CTRL_DATA_SEL_MASK
);
472 ASSERT_BIT_CLEAR(dataw
, PCI_PM_CTRL_DATA_SCALE_MASK
);
475 static void ahci_test_hba_spec(AHCIQState
*ahci
)
483 g_assert(ahci
!= NULL
);
486 * Note that the AHCI spec does expect the BIOS to set up a few things:
487 * CAP.SSS - Support for staggered spin-up (t/f)
488 * CAP.SMPS - Support for mechanical presence switches (t/f)
489 * PI - Ports Implemented (1-32)
490 * PxCMD.HPCP - Hot Plug Capable Port
491 * PxCMD.MPSP - Mechanical Presence Switch Present
492 * PxCMD.CPD - Cold Presence Detection support
494 * Additional items are touched if CAP.SSS is on, see AHCI 10.1.1 p.97:
495 * Foreach Port Implemented:
496 * -PxCMD.ST, PxCMD.CR, PxCMD.FRE, PxCMD.FR, PxSCTL.DET are 0
497 * -PxCLB/U and PxFB/U are set to valid regions in memory
498 * -PxSUD is set to 1.
499 * -PxSSTS.DET is polled for presence; if detected, we continue:
500 * -PxSERR is cleared with 1's.
501 * -If PxTFD.STS.BSY, PxTFD.STS.DRQ, and PxTFD.STS.ERR are all zero,
502 * the device is ready.
505 /* 1 CAP - Capabilities Register */
506 ahci
->cap
= ahci_rreg(ahci
, AHCI_CAP
);
507 ASSERT_BIT_CLEAR(ahci
->cap
, AHCI_CAP_RESERVED
);
509 /* 2 GHC - Global Host Control */
510 reg
= ahci_rreg(ahci
, AHCI_GHC
);
511 ASSERT_BIT_CLEAR(reg
, AHCI_GHC_HR
);
512 ASSERT_BIT_CLEAR(reg
, AHCI_GHC_IE
);
513 ASSERT_BIT_CLEAR(reg
, AHCI_GHC_MRSM
);
514 if (BITSET(ahci
->cap
, AHCI_CAP_SAM
)) {
515 g_test_message("Supports AHCI-Only Mode: GHC_AE is Read-Only.");
516 ASSERT_BIT_SET(reg
, AHCI_GHC_AE
);
518 g_test_message("Supports AHCI/Legacy mix.");
519 ASSERT_BIT_CLEAR(reg
, AHCI_GHC_AE
);
522 /* 3 IS - Interrupt Status */
523 reg
= ahci_rreg(ahci
, AHCI_IS
);
524 g_assert_cmphex(reg
, ==, 0);
526 /* 4 PI - Ports Implemented */
527 ports
= ahci_rreg(ahci
, AHCI_PI
);
528 /* Ports Implemented must be non-zero. */
529 g_assert_cmphex(ports
, !=, 0);
530 /* Ports Implemented must be <= Number of Ports. */
531 nports_impl
= ctpopl(ports
);
532 g_assert_cmpuint(((AHCI_CAP_NP
& ahci
->cap
) + 1), >=, nports_impl
);
534 /* Ports must be within the proper range. Given a mapping of SIZE,
535 * 256 bytes are used for global HBA control, and the rest is used
536 * for ports data, at 0x80 bytes each. */
537 g_assert_cmphex(ahci
->barsize
, >, 0);
538 maxports
= (ahci
->barsize
- HBA_DATA_REGION_SIZE
) / HBA_PORT_DATA_SIZE
;
539 /* e.g, 30 ports for 4K of memory. (4096 - 256) / 128 = 30 */
540 g_assert_cmphex((reg
>> maxports
), ==, 0);
543 reg
= ahci_rreg(ahci
, AHCI_VS
);
545 case AHCI_VERSION_0_95
:
546 case AHCI_VERSION_1_0
:
547 case AHCI_VERSION_1_1
:
548 case AHCI_VERSION_1_2
:
549 case AHCI_VERSION_1_3
:
552 g_assert_not_reached();
555 /* 6 Command Completion Coalescing Control: depends on CAP.CCCS. */
556 reg
= ahci_rreg(ahci
, AHCI_CCCCTL
);
557 if (BITSET(ahci
->cap
, AHCI_CAP_CCCS
)) {
558 ASSERT_BIT_CLEAR(reg
, AHCI_CCCCTL_EN
);
559 ASSERT_BIT_CLEAR(reg
, AHCI_CCCCTL_RESERVED
);
560 ASSERT_BIT_SET(reg
, AHCI_CCCCTL_CC
);
561 ASSERT_BIT_SET(reg
, AHCI_CCCCTL_TV
);
563 g_assert_cmphex(reg
, ==, 0);
567 reg
= ahci_rreg(ahci
, AHCI_CCCPORTS
);
568 /* Must be zeroes initially regardless of CAP.CCCS */
569 g_assert_cmphex(reg
, ==, 0);
572 reg
= ahci_rreg(ahci
, AHCI_EMLOC
);
573 if (BITCLR(ahci
->cap
, AHCI_CAP_EMS
)) {
574 g_assert_cmphex(reg
, ==, 0);
578 reg
= ahci_rreg(ahci
, AHCI_EMCTL
);
579 if (BITSET(ahci
->cap
, AHCI_CAP_EMS
)) {
580 ASSERT_BIT_CLEAR(reg
, AHCI_EMCTL_STSMR
);
581 ASSERT_BIT_CLEAR(reg
, AHCI_EMCTL_CTLTM
);
582 ASSERT_BIT_CLEAR(reg
, AHCI_EMCTL_CTLRST
);
583 ASSERT_BIT_CLEAR(reg
, AHCI_EMCTL_RESERVED
);
585 g_assert_cmphex(reg
, ==, 0);
588 /* 10 CAP2 -- Capabilities Extended */
589 ahci
->cap2
= ahci_rreg(ahci
, AHCI_CAP2
);
590 ASSERT_BIT_CLEAR(ahci
->cap2
, AHCI_CAP2_RESERVED
);
592 /* 11 BOHC -- Bios/OS Handoff Control */
593 reg
= ahci_rreg(ahci
, AHCI_BOHC
);
594 g_assert_cmphex(reg
, ==, 0);
596 /* 12 -- 23: Reserved */
597 g_test_message("Verifying HBA reserved area is empty.");
598 for (i
= AHCI_RESERVED
; i
< AHCI_NVMHCI
; ++i
) {
599 reg
= ahci_rreg(ahci
, i
);
600 g_assert_cmphex(reg
, ==, 0);
603 /* 24 -- 39: NVMHCI */
604 if (BITCLR(ahci
->cap2
, AHCI_CAP2_NVMP
)) {
605 g_test_message("Verifying HBA/NVMHCI area is empty.");
606 for (i
= AHCI_NVMHCI
; i
< AHCI_VENDOR
; ++i
) {
607 reg
= ahci_rreg(ahci
, i
);
608 g_assert_cmphex(reg
, ==, 0);
612 /* 40 -- 63: Vendor */
613 g_test_message("Verifying HBA/Vendor area is empty.");
614 for (i
= AHCI_VENDOR
; i
< AHCI_PORTS
; ++i
) {
615 reg
= ahci_rreg(ahci
, i
);
616 g_assert_cmphex(reg
, ==, 0);
619 /* 64 -- XX: Port Space */
620 for (i
= 0; ports
|| (i
< maxports
); ports
>>= 1, ++i
) {
621 if (BITSET(ports
, 0x1)) {
622 g_test_message("Testing port %u for spec", i
);
623 ahci_test_port_spec(ahci
, i
);
626 uint16_t low
= AHCI_PORTS
+ (32 * i
);
627 uint16_t high
= AHCI_PORTS
+ (32 * (i
+ 1));
628 g_test_message("Asserting unimplemented port %u "
629 "(reg [%u-%u]) is empty.",
631 for (j
= low
; j
< high
; ++j
) {
632 reg
= ahci_rreg(ahci
, j
);
633 g_assert_cmphex(reg
, ==, 0);
640 * Test the memory space for one port for specification adherence.
642 static void ahci_test_port_spec(AHCIQState
*ahci
, uint8_t port
)
648 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_CLB
);
649 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CLB_RESERVED
);
652 if (BITCLR(ahci
->cap
, AHCI_CAP_S64A
)) {
653 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_CLBU
);
654 g_assert_cmphex(reg
, ==, 0);
658 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_FB
);
659 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FB_RESERVED
);
662 if (BITCLR(ahci
->cap
, AHCI_CAP_S64A
)) {
663 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_FBU
);
664 g_assert_cmphex(reg
, ==, 0);
668 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_IS
);
669 g_assert_cmphex(reg
, ==, 0);
672 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_IE
);
673 g_assert_cmphex(reg
, ==, 0);
676 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_CMD
);
677 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_FRE
);
678 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_RESERVED
);
679 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_CCS
);
680 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_FR
);
681 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_CR
);
682 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_PMA
); /* And RW only if CAP.SPM */
683 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_APSTE
); /* RW only if CAP2.APST */
684 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_ATAPI
);
685 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_DLAE
);
686 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_ALPE
); /* RW only if CAP.SALP */
687 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_ASP
); /* RW only if CAP.SALP */
688 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_ICC
);
689 /* If CPDetect support does not exist, CPState must be off. */
690 if (BITCLR(reg
, AHCI_PX_CMD_CPD
)) {
691 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_CPS
);
693 /* If MPSPresence is not set, MPSState must be off. */
694 if (BITCLR(reg
, AHCI_PX_CMD_MPSP
)) {
695 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_MPSS
);
697 /* If we do not support MPS, MPSS and MPSP must be off. */
698 if (BITCLR(ahci
->cap
, AHCI_CAP_SMPS
)) {
699 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_MPSS
);
700 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_MPSP
);
702 /* If, via CPD or MPSP we detect a drive, HPCP must be on. */
703 if (BITANY(reg
, AHCI_PX_CMD_CPD
| AHCI_PX_CMD_MPSP
)) {
704 ASSERT_BIT_SET(reg
, AHCI_PX_CMD_HPCP
);
706 /* HPCP and ESP cannot both be active. */
707 g_assert(!BITSET(reg
, AHCI_PX_CMD_HPCP
| AHCI_PX_CMD_ESP
));
708 /* If CAP.FBSS is not set, FBSCP must not be set. */
709 if (BITCLR(ahci
->cap
, AHCI_CAP_FBSS
)) {
710 ASSERT_BIT_CLEAR(reg
, AHCI_PX_CMD_FBSCP
);
714 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_RES1
);
715 g_assert_cmphex(reg
, ==, 0);
718 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_TFD
);
719 /* At boot, prior to an FIS being received, the TFD register should be 0x7F,
720 * which breaks down as follows, as seen in AHCI 1.3 sec 3.3.8, p. 27. */
721 ASSERT_BIT_SET(reg
, AHCI_PX_TFD_STS_ERR
);
722 ASSERT_BIT_SET(reg
, AHCI_PX_TFD_STS_CS1
);
723 ASSERT_BIT_SET(reg
, AHCI_PX_TFD_STS_DRQ
);
724 ASSERT_BIT_SET(reg
, AHCI_PX_TFD_STS_CS2
);
725 ASSERT_BIT_CLEAR(reg
, AHCI_PX_TFD_STS_BSY
);
726 ASSERT_BIT_CLEAR(reg
, AHCI_PX_TFD_ERR
);
727 ASSERT_BIT_CLEAR(reg
, AHCI_PX_TFD_RESERVED
);
730 /* Though AHCI specifies the boot value should be 0xFFFFFFFF,
731 * Even when GHC.ST is zero, the AHCI HBA may receive the initial
732 * D2H register FIS and update the signature asynchronously,
733 * so we cannot expect a value here. AHCI 1.3, sec 3.3.9, pp 27-28 */
735 /* (10) SSTS / SCR0: SStatus */
736 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SSTS
);
737 ASSERT_BIT_CLEAR(reg
, AHCI_PX_SSTS_RESERVED
);
738 /* Even though the register should be 0 at boot, it is asynchronous and
739 * prone to change, so we cannot test any well known value. */
741 /* (11) SCTL / SCR2: SControl */
742 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SCTL
);
743 g_assert_cmphex(reg
, ==, 0);
745 /* (12) SERR / SCR1: SError */
746 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SERR
);
747 g_assert_cmphex(reg
, ==, 0);
749 /* (13) SACT / SCR3: SActive */
750 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SACT
);
751 g_assert_cmphex(reg
, ==, 0);
754 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_CI
);
755 g_assert_cmphex(reg
, ==, 0);
758 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_SNTF
);
759 g_assert_cmphex(reg
, ==, 0);
762 reg
= ahci_px_rreg(ahci
, port
, AHCI_PX_FBS
);
763 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_EN
);
764 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_DEC
);
765 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_SDE
);
766 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_DEV
);
767 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_DWE
);
768 ASSERT_BIT_CLEAR(reg
, AHCI_PX_FBS_RESERVED
);
769 if (BITSET(ahci
->cap
, AHCI_CAP_FBSS
)) {
770 /* if Port-Multiplier FIS-based switching avail, ADO must >= 2 */
771 g_assert((reg
& AHCI_PX_FBS_ADO
) >> ctzl(AHCI_PX_FBS_ADO
) >= 2);
774 /* [17 -- 27] RESERVED */
775 for (i
= AHCI_PX_RES2
; i
< AHCI_PX_VS
; ++i
) {
776 reg
= ahci_px_rreg(ahci
, port
, i
);
777 g_assert_cmphex(reg
, ==, 0);
780 /* [28 -- 31] Vendor-Specific */
781 for (i
= AHCI_PX_VS
; i
< 32; ++i
) {
782 reg
= ahci_px_rreg(ahci
, port
, i
);
784 g_test_message("INFO: Vendor register %u non-empty", i
);
790 * Utilizing an initialized AHCI HBA, issue an IDENTIFY command to the first
791 * device we see, then read and check the response.
793 static void ahci_test_identify(AHCIQState
*ahci
)
799 const size_t buffsize
= 512;
801 g_assert(ahci
!= NULL
);
804 * This serves as a bit of a tutorial on AHCI device programming:
806 * (1) Create a data buffer for the IDENTIFY response to be sent to
807 * (2) Create a Command Table buffer, where we will store the
808 * command and PRDT (Physical Region Descriptor Table)
809 * (3) Construct an FIS host-to-device command structure, and write it to
810 * the top of the Command Table buffer.
811 * (4) Create one or more Physical Region Descriptors (PRDs) that describe
812 * a location in memory where data may be stored/retrieved.
813 * (5) Write these PRDTs to the bottom (offset 0x80) of the Command Table.
814 * (6) Each AHCI port has up to 32 command slots. Each slot contains a
815 * header that points to a Command Table buffer. Pick an unused slot
816 * and update it to point to the Command Table we have built.
817 * (7) Now: Command #n points to our Command Table, and our Command Table
818 * contains the FIS (that describes our command) and the PRDTL, which
819 * describes our buffer.
820 * (8) We inform the HBA via PxCI (Command Issue) that the command in slot
821 * #n is ready for processing.
824 /* Pick the first implemented and running port */
825 px
= ahci_port_select(ahci
);
826 g_test_message("Selected port %u for test", px
);
828 /* Clear out the FIS Receive area and any pending interrupts. */
829 ahci_port_clear(ahci
, px
);
831 /* "Read" 512 bytes using CMD_IDENTIFY into the host buffer. */
832 ahci_io(ahci
, px
, CMD_IDENTIFY
, &buff
, buffsize
, 0);
834 /* Check serial number/version in the buffer */
835 /* NB: IDENTIFY strings are packed in 16bit little endian chunks.
836 * Since we copy byte-for-byte in ahci-test, on both LE and BE, we need to
837 * unchunk this data. By contrast, ide-test copies 2 bytes at a time, and
838 * as a consequence, only needs to unchunk the data on LE machines. */
839 string_bswap16(&buff
[10], 20);
840 rc
= memcmp(&buff
[10], "testdisk ", 20);
841 g_assert_cmphex(rc
, ==, 0);
843 string_bswap16(&buff
[23], 8);
844 rc
= memcmp(&buff
[23], "version ", 8);
845 g_assert_cmphex(rc
, ==, 0);
847 sect_size
= le16_to_cpu(*((uint16_t *)(&buff
[5])));
848 g_assert_cmphex(sect_size
, ==, AHCI_SECTOR_SIZE
);
851 static void ahci_test_io_rw_simple(AHCIQState
*ahci
, unsigned bufsize
,
852 uint64_t sector
, uint8_t read_cmd
,
857 unsigned char *tx
= g_malloc(bufsize
);
858 unsigned char *rx
= g_malloc0(bufsize
);
860 g_assert(ahci
!= NULL
);
862 /* Pick the first running port and clear it. */
863 port
= ahci_port_select(ahci
);
864 ahci_port_clear(ahci
, port
);
866 /*** Create pattern and transfer to guest ***/
867 /* Data buffer in the guest */
868 ptr
= ahci_alloc(ahci
, bufsize
);
871 /* Write some indicative pattern to our buffer. */
872 generate_pattern(tx
, bufsize
, AHCI_SECTOR_SIZE
);
873 bufwrite(ptr
, tx
, bufsize
);
875 /* Write this buffer to disk, then read it back to the DMA buffer. */
876 ahci_guest_io(ahci
, port
, write_cmd
, ptr
, bufsize
, sector
);
877 qmemset(ptr
, 0x00, bufsize
);
878 ahci_guest_io(ahci
, port
, read_cmd
, ptr
, bufsize
, sector
);
880 /*** Read back the Data ***/
881 bufread(ptr
, rx
, bufsize
);
882 g_assert_cmphex(memcmp(tx
, rx
, bufsize
), ==, 0);
884 ahci_free(ahci
, ptr
);
889 static uint8_t ahci_test_nondata(AHCIQState
*ahci
, uint8_t ide_cmd
)
894 port
= ahci_port_select(ahci
);
895 ahci_port_clear(ahci
, port
);
897 ahci_io(ahci
, port
, ide_cmd
, NULL
, 0, 0);
902 static void ahci_test_flush(AHCIQState
*ahci
)
904 ahci_test_nondata(ahci
, CMD_FLUSH_CACHE
);
907 static void ahci_test_max(AHCIQState
*ahci
)
909 RegD2HFIS
*d2h
= g_malloc0(0x20);
913 uint64_t config_sect
= mb_to_sectors(test_image_size_mb
) - 1;
915 if (config_sect
> 0xFFFFFF) {
916 cmd
= CMD_READ_MAX_EXT
;
921 port
= ahci_test_nondata(ahci
, cmd
);
922 memread(ahci
->port
[port
].fb
+ 0x40, d2h
, 0x20);
923 nsect
= (uint64_t)d2h
->lba_hi
[2] << 40 |
924 (uint64_t)d2h
->lba_hi
[1] << 32 |
925 (uint64_t)d2h
->lba_hi
[0] << 24 |
926 (uint64_t)d2h
->lba_lo
[2] << 16 |
927 (uint64_t)d2h
->lba_lo
[1] << 8 |
928 (uint64_t)d2h
->lba_lo
[0];
930 g_assert_cmphex(nsect
, ==, config_sect
);
935 /******************************************************************************/
936 /* Test Interfaces */
937 /******************************************************************************/
940 * Basic sanity test to boot a machine, find an AHCI device, and shutdown.
942 static void test_sanity(void)
945 ahci
= ahci_boot(NULL
);
950 * Ensure that the PCI configuration space for the AHCI device is in-line with
951 * the AHCI 1.3 specification for initial values.
953 static void test_pci_spec(void)
956 ahci
= ahci_boot(NULL
);
957 ahci_test_pci_spec(ahci
);
962 * Engage the PCI AHCI device and sanity check the response.
963 * Perform additional PCI config space bringup for the HBA.
965 static void test_pci_enable(void)
968 ahci
= ahci_boot(NULL
);
969 ahci_pci_enable(ahci
);
974 * Investigate the memory mapped regions of the HBA,
975 * and test them for AHCI specification adherence.
977 static void test_hba_spec(void)
981 ahci
= ahci_boot(NULL
);
982 ahci_pci_enable(ahci
);
983 ahci_test_hba_spec(ahci
);
988 * Engage the HBA functionality of the AHCI PCI device,
989 * and bring it into a functional idle state.
991 static void test_hba_enable(void)
995 ahci
= ahci_boot(NULL
);
996 ahci_pci_enable(ahci
);
997 ahci_hba_enable(ahci
);
1002 * Bring up the device and issue an IDENTIFY command.
1003 * Inspect the state of the HBA device and the data returned.
1005 static void test_identify(void)
1009 ahci
= ahci_boot_and_enable(NULL
);
1010 ahci_test_identify(ahci
);
1011 ahci_shutdown(ahci
);
1015 * Fragmented DMA test: Perform a standard 4K DMA read/write
1016 * test, but make sure the physical regions are fragmented to
1017 * be very small, each just 32 bytes, to see how AHCI performs
1018 * with chunks defined to be much less than a sector.
1020 static void test_dma_fragmented(void)
1025 size_t bufsize
= 4096;
1026 unsigned char *tx
= g_malloc(bufsize
);
1027 unsigned char *rx
= g_malloc0(bufsize
);
1030 ahci
= ahci_boot_and_enable(NULL
);
1031 px
= ahci_port_select(ahci
);
1032 ahci_port_clear(ahci
, px
);
1034 /* create pattern */
1035 generate_pattern(tx
, bufsize
, AHCI_SECTOR_SIZE
);
1037 /* Create a DMA buffer in guest memory, and write our pattern to it. */
1038 ptr
= guest_alloc(ahci
->parent
->alloc
, bufsize
);
1040 bufwrite(ptr
, tx
, bufsize
);
1042 cmd
= ahci_command_create(CMD_WRITE_DMA
);
1043 ahci_command_adjust(cmd
, 0, ptr
, bufsize
, 32);
1044 ahci_command_commit(ahci
, cmd
, px
);
1045 ahci_command_issue(ahci
, cmd
);
1046 ahci_command_verify(ahci
, cmd
);
1047 ahci_command_free(cmd
);
1049 cmd
= ahci_command_create(CMD_READ_DMA
);
1050 ahci_command_adjust(cmd
, 0, ptr
, bufsize
, 32);
1051 ahci_command_commit(ahci
, cmd
, px
);
1052 ahci_command_issue(ahci
, cmd
);
1053 ahci_command_verify(ahci
, cmd
);
1054 ahci_command_free(cmd
);
1056 /* Read back the guest's receive buffer into local memory */
1057 bufread(ptr
, rx
, bufsize
);
1058 guest_free(ahci
->parent
->alloc
, ptr
);
1060 g_assert_cmphex(memcmp(tx
, rx
, bufsize
), ==, 0);
1062 ahci_shutdown(ahci
);
1069 * Write sector 1 with random data to make AHCI storage dirty
1070 * Needed for flush tests so that flushes actually go though the block layer
1072 static void make_dirty(AHCIQState
* ahci
, uint8_t port
)
1075 unsigned bufsize
= 512;
1077 ptr
= ahci_alloc(ahci
, bufsize
);
1080 ahci_guest_io(ahci
, port
, CMD_WRITE_DMA
, ptr
, bufsize
, 1);
1081 ahci_free(ahci
, ptr
);
1084 static void test_flush(void)
1089 ahci
= ahci_boot_and_enable(NULL
);
1091 port
= ahci_port_select(ahci
);
1092 ahci_port_clear(ahci
, port
);
1094 make_dirty(ahci
, port
);
1096 ahci_test_flush(ahci
);
1097 ahci_shutdown(ahci
);
1100 static void test_flush_retry(void)
1106 prepare_blkdebug_script(debug_path
, "flush_to_disk");
1107 ahci
= ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1108 "format=%s,cache=writeback,"
1109 "rerror=stop,werror=stop "
1111 "-device ide-hd,drive=drive0 ",
1115 port
= ahci_port_select(ahci
);
1116 ahci_port_clear(ahci
, port
);
1118 /* Issue write so that flush actually goes to disk */
1119 make_dirty(ahci
, port
);
1121 /* Issue Flush Command and wait for error */
1122 cmd
= ahci_guest_io_halt(ahci
, port
, CMD_FLUSH_CACHE
, 0, 0, 0);
1123 ahci_guest_io_resume(ahci
, cmd
);
1125 ahci_shutdown(ahci
);
1129 * Basic sanity test to boot a machine, find an AHCI device, and shutdown.
1131 static void test_migrate_sanity(void)
1133 AHCIQState
*src
, *dst
;
1134 char *uri
= g_strdup_printf("unix:%s", mig_socket
);
1136 src
= ahci_boot("-m 384 -M q35 "
1137 "-drive if=ide,file=%s,format=%s ", tmp_path
, imgfmt
);
1138 dst
= ahci_boot("-m 384 -M q35 "
1139 "-drive if=ide,file=%s,format=%s "
1140 "-incoming %s", tmp_path
, imgfmt
, uri
);
1142 ahci_migrate(src
, dst
, uri
);
1150 * Simple migration test: Write a pattern, migrate, then read.
1152 static void ahci_migrate_simple(uint8_t cmd_read
, uint8_t cmd_write
)
1154 AHCIQState
*src
, *dst
;
1156 size_t bufsize
= 4096;
1157 unsigned char *tx
= g_malloc(bufsize
);
1158 unsigned char *rx
= g_malloc0(bufsize
);
1159 char *uri
= g_strdup_printf("unix:%s", mig_socket
);
1161 src
= ahci_boot_and_enable("-m 384 -M q35 "
1162 "-drive if=ide,format=%s,file=%s ",
1164 dst
= ahci_boot("-m 384 -M q35 "
1165 "-drive if=ide,format=%s,file=%s "
1166 "-incoming %s", imgfmt
, tmp_path
, uri
);
1168 set_context(src
->parent
);
1171 px
= ahci_port_select(src
);
1172 ahci_port_clear(src
, px
);
1174 /* create pattern */
1175 generate_pattern(tx
, bufsize
, AHCI_SECTOR_SIZE
);
1177 /* Write, migrate, then read. */
1178 ahci_io(src
, px
, cmd_write
, tx
, bufsize
, 0);
1179 ahci_migrate(src
, dst
, uri
);
1180 ahci_io(dst
, px
, cmd_read
, rx
, bufsize
, 0);
1182 /* Verify pattern */
1183 g_assert_cmphex(memcmp(tx
, rx
, bufsize
), ==, 0);
1192 static void test_migrate_dma(void)
1194 ahci_migrate_simple(CMD_READ_DMA
, CMD_WRITE_DMA
);
1197 static void test_migrate_ncq(void)
1199 ahci_migrate_simple(READ_FPDMA_QUEUED
, WRITE_FPDMA_QUEUED
);
1203 * Halted IO Error Test
1205 * Simulate an error on first write, Try to write a pattern,
1206 * Confirm the VM has stopped, resume the VM, verify command
1207 * has completed, then read back the data and verify.
1209 static void ahci_halted_io_test(uint8_t cmd_read
, uint8_t cmd_write
)
1213 size_t bufsize
= 4096;
1214 unsigned char *tx
= g_malloc(bufsize
);
1215 unsigned char *rx
= g_malloc0(bufsize
);
1219 prepare_blkdebug_script(debug_path
, "write_aio");
1221 ahci
= ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1222 "format=%s,cache=writeback,"
1223 "rerror=stop,werror=stop "
1225 "-device ide-hd,drive=drive0 ",
1229 /* Initialize and prepare */
1230 port
= ahci_port_select(ahci
);
1231 ahci_port_clear(ahci
, port
);
1233 /* create DMA source buffer and write pattern */
1234 generate_pattern(tx
, bufsize
, AHCI_SECTOR_SIZE
);
1235 ptr
= ahci_alloc(ahci
, bufsize
);
1237 memwrite(ptr
, tx
, bufsize
);
1239 /* Attempt to write (and fail) */
1240 cmd
= ahci_guest_io_halt(ahci
, port
, cmd_write
,
1243 /* Attempt to resume the command */
1244 ahci_guest_io_resume(ahci
, cmd
);
1245 ahci_free(ahci
, ptr
);
1247 /* Read back and verify */
1248 ahci_io(ahci
, port
, cmd_read
, rx
, bufsize
, 0);
1249 g_assert_cmphex(memcmp(tx
, rx
, bufsize
), ==, 0);
1251 /* Cleanup and go home */
1252 ahci_shutdown(ahci
);
1257 static void test_halted_dma(void)
1259 ahci_halted_io_test(CMD_READ_DMA
, CMD_WRITE_DMA
);
1262 static void test_halted_ncq(void)
1264 ahci_halted_io_test(READ_FPDMA_QUEUED
, WRITE_FPDMA_QUEUED
);
1268 * IO Error Migration Test
1270 * Simulate an error on first write, Try to write a pattern,
1271 * Confirm the VM has stopped, migrate, resume the VM,
1272 * verify command has completed, then read back the data and verify.
1274 static void ahci_migrate_halted_io(uint8_t cmd_read
, uint8_t cmd_write
)
1276 AHCIQState
*src
, *dst
;
1278 size_t bufsize
= 4096;
1279 unsigned char *tx
= g_malloc(bufsize
);
1280 unsigned char *rx
= g_malloc0(bufsize
);
1283 char *uri
= g_strdup_printf("unix:%s", mig_socket
);
1285 prepare_blkdebug_script(debug_path
, "write_aio");
1287 src
= ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1288 "format=%s,cache=writeback,"
1289 "rerror=stop,werror=stop "
1291 "-device ide-hd,drive=drive0 ",
1295 dst
= ahci_boot("-drive file=%s,if=none,id=drive0,"
1296 "format=%s,cache=writeback,"
1297 "rerror=stop,werror=stop "
1299 "-device ide-hd,drive=drive0 "
1301 tmp_path
, imgfmt
, uri
);
1303 set_context(src
->parent
);
1305 /* Initialize and prepare */
1306 port
= ahci_port_select(src
);
1307 ahci_port_clear(src
, port
);
1308 generate_pattern(tx
, bufsize
, AHCI_SECTOR_SIZE
);
1310 /* create DMA source buffer and write pattern */
1311 ptr
= ahci_alloc(src
, bufsize
);
1313 memwrite(ptr
, tx
, bufsize
);
1315 /* Write, trigger the VM to stop, migrate, then resume. */
1316 cmd
= ahci_guest_io_halt(src
, port
, cmd_write
,
1318 ahci_migrate(src
, dst
, uri
);
1319 ahci_guest_io_resume(dst
, cmd
);
1320 ahci_free(dst
, ptr
);
1323 ahci_io(dst
, port
, cmd_read
, rx
, bufsize
, 0);
1325 /* Verify TX and RX are identical */
1326 g_assert_cmphex(memcmp(tx
, rx
, bufsize
), ==, 0);
1328 /* Cleanup and go home. */
1336 static void test_migrate_halted_dma(void)
1338 ahci_migrate_halted_io(CMD_READ_DMA
, CMD_WRITE_DMA
);
1341 static void test_migrate_halted_ncq(void)
1343 ahci_migrate_halted_io(READ_FPDMA_QUEUED
, WRITE_FPDMA_QUEUED
);
1347 * Migration test: Try to flush, migrate, then resume.
1349 static void test_flush_migrate(void)
1351 AHCIQState
*src
, *dst
;
1355 char *uri
= g_strdup_printf("unix:%s", mig_socket
);
1357 prepare_blkdebug_script(debug_path
, "flush_to_disk");
1359 src
= ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0,"
1360 "cache=writeback,rerror=stop,werror=stop,"
1363 "-device ide-hd,drive=drive0 ",
1364 debug_path
, tmp_path
, imgfmt
);
1365 dst
= ahci_boot("-drive file=%s,if=none,id=drive0,"
1366 "cache=writeback,rerror=stop,werror=stop,"
1369 "-device ide-hd,drive=drive0 "
1370 "-incoming %s", tmp_path
, imgfmt
, uri
);
1372 set_context(src
->parent
);
1374 px
= ahci_port_select(src
);
1375 ahci_port_clear(src
, px
);
1377 /* Dirty device so that flush reaches disk */
1378 make_dirty(src
, px
);
1380 /* Issue Flush Command */
1381 cmd
= ahci_command_create(CMD_FLUSH_CACHE
);
1382 ahci_command_commit(src
, cmd
, px
);
1383 ahci_command_issue_async(src
, cmd
);
1384 qmp_eventwait("STOP");
1387 ahci_migrate(src
, dst
, uri
);
1389 /* Complete the command */
1390 s
= "{'execute':'cont' }";
1392 qmp_eventwait("RESUME");
1393 ahci_command_wait(dst
, cmd
);
1394 ahci_command_verify(dst
, cmd
);
1396 ahci_command_free(cmd
);
1402 static void test_max(void)
1406 ahci
= ahci_boot_and_enable(NULL
);
1407 ahci_test_max(ahci
);
1408 ahci_shutdown(ahci
);
1411 static void test_reset(void)
1416 ahci
= ahci_boot(NULL
);
1417 ahci_test_pci_spec(ahci
);
1418 ahci_pci_enable(ahci
);
1420 for (i
= 0; i
< 2; i
++) {
1421 ahci_test_hba_spec(ahci
);
1422 ahci_hba_enable(ahci
);
1423 ahci_test_identify(ahci
);
1424 ahci_test_io_rw_simple(ahci
, 4096, 0,
1427 ahci_set(ahci
, AHCI_GHC
, AHCI_GHC_HR
);
1428 ahci_clean_mem(ahci
);
1431 ahci_shutdown(ahci
);
1434 static void test_ncq_simple(void)
1438 ahci
= ahci_boot_and_enable(NULL
);
1439 ahci_test_io_rw_simple(ahci
, 4096, 0,
1441 WRITE_FPDMA_QUEUED
);
1442 ahci_shutdown(ahci
);
1445 static int prepare_iso(size_t size
, unsigned char **buf
, char **name
)
1447 char cdrom_path
[] = "/tmp/qtest.iso.XXXXXX";
1448 unsigned char *patt
;
1450 int fd
= mkstemp(cdrom_path
);
1454 patt
= g_malloc(size
);
1456 /* Generate a pattern and build a CDROM image to read from */
1457 generate_pattern(patt
, size
, ATAPI_SECTOR_SIZE
);
1458 ret
= write(fd
, patt
, size
);
1459 g_assert(ret
== size
);
1461 *name
= g_strdup(cdrom_path
);
1466 static void remove_iso(int fd
, char *name
)
1473 static int ahci_cb_cmp_buff(AHCIQState
*ahci
, AHCICommand
*cmd
,
1474 const AHCIOpts
*opts
)
1476 unsigned char *tx
= opts
->opaque
;
1483 rx
= g_malloc0(opts
->size
);
1484 bufread(opts
->buffer
, rx
, opts
->size
);
1485 g_assert_cmphex(memcmp(tx
, rx
, opts
->size
), ==, 0);
1491 static void ahci_test_cdrom(int nsectors
, bool dma
, uint8_t cmd
,
1492 bool override_bcl
, uint16_t bcl
)
1499 .size
= (ATAPI_SECTOR_SIZE
* nsectors
),
1502 .post_cb
= ahci_cb_cmp_buff
,
1503 .set_bcl
= override_bcl
,
1506 uint64_t iso_size
= ATAPI_SECTOR_SIZE
* (nsectors
+ 1);
1508 /* Prepare ISO and fill 'tx' buffer */
1509 fd
= prepare_iso(iso_size
, &tx
, &iso
);
1512 /* Standard startup wonkery, but use ide-cd and our special iso file */
1513 ahci
= ahci_boot_and_enable("-drive if=none,id=drive0,file=%s,format=raw "
1515 "-device ide-cd,drive=drive0 ", iso
);
1517 /* Build & Send AHCI command */
1518 ahci_exec(ahci
, ahci_port_select(ahci
), cmd
, &opts
);
1522 ahci_shutdown(ahci
);
1523 remove_iso(fd
, iso
);
1526 static void ahci_test_cdrom_read10(int nsectors
, bool dma
)
1528 ahci_test_cdrom(nsectors
, dma
, CMD_ATAPI_READ_10
, false, 0);
1531 static void test_cdrom_dma(void)
1533 ahci_test_cdrom_read10(1, true);
1536 static void test_cdrom_dma_multi(void)
1538 ahci_test_cdrom_read10(3, true);
1541 static void test_cdrom_pio(void)
1543 ahci_test_cdrom_read10(1, false);
1546 static void test_cdrom_pio_multi(void)
1548 ahci_test_cdrom_read10(3, false);
1551 /* Regression test: Test that a READ_CD command with a BCL of 0 but a size of 0
1552 * completes as a NOP instead of erroring out. */
1553 static void test_atapi_bcl(void)
1555 ahci_test_cdrom(0, false, CMD_ATAPI_READ_CD
, true, 0);
1559 static void atapi_wait_tray(bool open
)
1561 QDict
*rsp
= qmp_eventwait_ref("DEVICE_TRAY_MOVED");
1562 QDict
*data
= qdict_get_qdict(rsp
, "data");
1564 g_assert(qdict_get_bool(data
, "tray-open"));
1566 g_assert(!qdict_get_bool(data
, "tray-open"));
1571 static void test_atapi_tray(void)
1577 uint8_t port
, sense
, asc
;
1578 uint64_t iso_size
= ATAPI_SECTOR_SIZE
;
1581 fd
= prepare_iso(iso_size
, &tx
, &iso
);
1582 ahci
= ahci_boot_and_enable("-blockdev node-name=drive0,driver=file,filename=%s "
1584 "-device ide-cd,id=cd0,drive=drive0 ", iso
);
1585 port
= ahci_port_select(ahci
);
1587 ahci_atapi_eject(ahci
, port
);
1588 atapi_wait_tray(true);
1590 ahci_atapi_load(ahci
, port
);
1591 atapi_wait_tray(false);
1594 qmp_async("{'execute': 'blockdev-open-tray', "
1595 "'arguments': {'id': 'cd0'}}");
1596 atapi_wait_tray(true);
1597 rsp
= qmp_receive();
1600 qmp_discard_response("{'execute': 'blockdev-remove-medium', "
1601 "'arguments': {'id': 'cd0'}}");
1603 /* Test the tray without a medium */
1604 ahci_atapi_load(ahci
, port
);
1605 atapi_wait_tray(false);
1607 ahci_atapi_eject(ahci
, port
);
1608 atapi_wait_tray(true);
1610 /* Re-insert media */
1611 qmp_discard_response("{'execute': 'blockdev-add', "
1612 "'arguments': {'node-name': 'node0', "
1614 "'file': { 'driver': 'file', "
1615 "'filename': %s }}}", iso
);
1616 qmp_discard_response("{'execute': 'blockdev-insert-medium',"
1617 "'arguments': { 'id': 'cd0', "
1618 "'node-name': 'node0' }}");
1620 /* Again, the event shows up first */
1621 qmp_async("{'execute': 'blockdev-close-tray', "
1622 "'arguments': {'id': 'cd0'}}");
1623 atapi_wait_tray(false);
1624 rsp
= qmp_receive();
1627 /* Now, to convince ATAPI we understand the media has changed... */
1628 ahci_atapi_test_ready(ahci
, port
, false, SENSE_NOT_READY
);
1629 ahci_atapi_get_sense(ahci
, port
, &sense
, &asc
);
1630 g_assert_cmpuint(sense
, ==, SENSE_NOT_READY
);
1631 g_assert_cmpuint(asc
, ==, ASC_MEDIUM_NOT_PRESENT
);
1633 ahci_atapi_test_ready(ahci
, port
, false, SENSE_UNIT_ATTENTION
);
1634 ahci_atapi_get_sense(ahci
, port
, &sense
, &asc
);
1635 g_assert_cmpuint(sense
, ==, SENSE_UNIT_ATTENTION
);
1636 g_assert_cmpuint(asc
, ==, ASC_MEDIUM_MAY_HAVE_CHANGED
);
1638 ahci_atapi_test_ready(ahci
, port
, true, SENSE_NO_SENSE
);
1639 ahci_atapi_get_sense(ahci
, port
, &sense
, &asc
);
1640 g_assert_cmpuint(sense
, ==, SENSE_NO_SENSE
);
1642 /* Final tray test. */
1643 ahci_atapi_eject(ahci
, port
);
1644 atapi_wait_tray(true);
1646 ahci_atapi_load(ahci
, port
);
1647 atapi_wait_tray(false);
1651 ahci_shutdown(ahci
);
1652 remove_iso(fd
, iso
);
1655 /******************************************************************************/
1656 /* AHCI I/O Test Matrix Definitions */
1660 LEN_SIMPLE
= LEN_BEGIN
,
1667 static const char *buff_len_str
[NUM_LENGTHS
] = { "simple", "double",
1671 ADDR_MODE_BEGIN
= 0,
1672 ADDR_MODE_LBA28
= ADDR_MODE_BEGIN
,
1677 static const char *addr_mode_str
[NUM_ADDR_MODES
] = { "lba28", "lba48" };
1681 MODE_PIO
= MODE_BEGIN
,
1686 static const char *io_mode_str
[NUM_MODES
] = { "pio", "dma" };
1697 OFFSET_ZERO
= OFFSET_BEGIN
,
1703 static const char *offset_str
[NUM_OFFSETS
] = { "zero", "low", "high" };
1705 typedef struct AHCIIOTestOptions
{
1706 enum BuffLen length
;
1707 enum AddrMode address_type
;
1708 enum IOMode io_type
;
1709 enum OffsetType offset
;
1710 } AHCIIOTestOptions
;
1712 static uint64_t offset_sector(enum OffsetType ofst
,
1713 enum AddrMode addr_type
,
1725 ceil
= (addr_type
== ADDR_MODE_LBA28
) ? 0xfffffff : 0xffffffffffff;
1726 ceil
= MIN(ceil
, mb_to_sectors(test_image_size_mb
) - 1);
1727 nsectors
= buffsize
/ AHCI_SECTOR_SIZE
;
1728 return ceil
- nsectors
+ 1;
1730 g_assert_not_reached();
1735 * Table of possible I/O ATA commands given a set of enumerations.
1737 static const uint8_t io_cmds
[NUM_MODES
][NUM_ADDR_MODES
][NUM_IO_OPS
] = {
1739 [ADDR_MODE_LBA28
] = {
1740 [IO_READ
] = CMD_READ_PIO
,
1741 [IO_WRITE
] = CMD_WRITE_PIO
},
1742 [ADDR_MODE_LBA48
] = {
1743 [IO_READ
] = CMD_READ_PIO_EXT
,
1744 [IO_WRITE
] = CMD_WRITE_PIO_EXT
}
1747 [ADDR_MODE_LBA28
] = {
1748 [IO_READ
] = CMD_READ_DMA
,
1749 [IO_WRITE
] = CMD_WRITE_DMA
},
1750 [ADDR_MODE_LBA48
] = {
1751 [IO_READ
] = CMD_READ_DMA_EXT
,
1752 [IO_WRITE
] = CMD_WRITE_DMA_EXT
}
1757 * Test a Read/Write pattern using various commands, addressing modes,
1758 * transfer modes, and buffer sizes.
1760 static void test_io_rw_interface(enum AddrMode lba48
, enum IOMode dma
,
1761 unsigned bufsize
, uint64_t sector
)
1765 ahci
= ahci_boot_and_enable(NULL
);
1766 ahci_test_io_rw_simple(ahci
, bufsize
, sector
,
1767 io_cmds
[dma
][lba48
][IO_READ
],
1768 io_cmds
[dma
][lba48
][IO_WRITE
]);
1769 ahci_shutdown(ahci
);
1773 * Demultiplex the test data and invoke the actual test routine.
1775 static void test_io_interface(gconstpointer opaque
)
1777 AHCIIOTestOptions
*opts
= (AHCIIOTestOptions
*)opaque
;
1781 switch (opts
->length
) {
1789 bufsize
= 4096 * 64;
1795 g_assert_not_reached();
1798 sector
= offset_sector(opts
->offset
, opts
->address_type
, bufsize
);
1799 test_io_rw_interface(opts
->address_type
, opts
->io_type
, bufsize
, sector
);
1804 static void create_ahci_io_test(enum IOMode type
, enum AddrMode addr
,
1805 enum BuffLen len
, enum OffsetType offset
)
1808 AHCIIOTestOptions
*opts
;
1810 opts
= g_new(AHCIIOTestOptions
, 1);
1812 opts
->address_type
= addr
;
1813 opts
->io_type
= type
;
1814 opts
->offset
= offset
;
1816 name
= g_strdup_printf("ahci/io/%s/%s/%s/%s",
1818 addr_mode_str
[addr
],
1820 offset_str
[offset
]);
1822 if ((addr
== ADDR_MODE_LBA48
) && (offset
== OFFSET_HIGH
) &&
1823 (mb_to_sectors(test_image_size_mb
) <= 0xFFFFFFF)) {
1824 g_test_message("%s: skipped; test image too small", name
);
1829 qtest_add_data_func(name
, opts
, test_io_interface
);
1833 /******************************************************************************/
1835 int main(int argc
, char **argv
)
1843 static struct option long_options
[] = {
1844 {"pedantic", no_argument
, 0, 'p' },
1848 /* Should be first to utilize g_test functionality, So we can see errors. */
1849 g_test_init(&argc
, &argv
, NULL
);
1852 c
= getopt_long(argc
, argv
, "", long_options
, NULL
);
1863 fprintf(stderr
, "Unrecognized ahci_test option.\n");
1864 g_assert_not_reached();
1868 /* Check architecture */
1869 arch
= qtest_get_arch();
1870 if (strcmp(arch
, "i386") && strcmp(arch
, "x86_64")) {
1871 g_test_message("Skipping test for non-x86");
1875 /* Create a temporary image */
1876 fd
= mkstemp(tmp_path
);
1878 if (have_qemu_img()) {
1880 test_image_size_mb
= TEST_IMAGE_SIZE_MB_LARGE
;
1881 mkqcow2(tmp_path
, TEST_IMAGE_SIZE_MB_LARGE
);
1883 g_test_message("QTEST_QEMU_IMG not set or qemu-img missing; "
1884 "skipping LBA48 high-sector tests");
1886 test_image_size_mb
= TEST_IMAGE_SIZE_MB_SMALL
;
1887 ret
= ftruncate(fd
, test_image_size_mb
* 1024 * 1024);
1892 /* Create temporary blkdebug instructions */
1893 fd
= mkstemp(debug_path
);
1897 /* Reserve a hollow file to use as a socket for migration tests */
1898 fd
= mkstemp(mig_socket
);
1903 qtest_add_func("/ahci/sanity", test_sanity
);
1904 qtest_add_func("/ahci/pci_spec", test_pci_spec
);
1905 qtest_add_func("/ahci/pci_enable", test_pci_enable
);
1906 qtest_add_func("/ahci/hba_spec", test_hba_spec
);
1907 qtest_add_func("/ahci/hba_enable", test_hba_enable
);
1908 qtest_add_func("/ahci/identify", test_identify
);
1910 for (i
= MODE_BEGIN
; i
< NUM_MODES
; i
++) {
1911 for (j
= ADDR_MODE_BEGIN
; j
< NUM_ADDR_MODES
; j
++) {
1912 for (k
= LEN_BEGIN
; k
< NUM_LENGTHS
; k
++) {
1913 for (m
= OFFSET_BEGIN
; m
< NUM_OFFSETS
; m
++) {
1914 create_ahci_io_test(i
, j
, k
, m
);
1920 qtest_add_func("/ahci/io/dma/lba28/fragmented", test_dma_fragmented
);
1922 qtest_add_func("/ahci/flush/simple", test_flush
);
1923 qtest_add_func("/ahci/flush/retry", test_flush_retry
);
1924 qtest_add_func("/ahci/flush/migrate", test_flush_migrate
);
1926 qtest_add_func("/ahci/migrate/sanity", test_migrate_sanity
);
1927 qtest_add_func("/ahci/migrate/dma/simple", test_migrate_dma
);
1928 qtest_add_func("/ahci/io/dma/lba28/retry", test_halted_dma
);
1929 qtest_add_func("/ahci/migrate/dma/halted", test_migrate_halted_dma
);
1931 qtest_add_func("/ahci/max", test_max
);
1932 qtest_add_func("/ahci/reset", test_reset
);
1934 qtest_add_func("/ahci/io/ncq/simple", test_ncq_simple
);
1935 qtest_add_func("/ahci/migrate/ncq/simple", test_migrate_ncq
);
1936 qtest_add_func("/ahci/io/ncq/retry", test_halted_ncq
);
1937 qtest_add_func("/ahci/migrate/ncq/halted", test_migrate_halted_ncq
);
1939 qtest_add_func("/ahci/cdrom/dma/single", test_cdrom_dma
);
1940 qtest_add_func("/ahci/cdrom/dma/multi", test_cdrom_dma_multi
);
1941 qtest_add_func("/ahci/cdrom/pio/single", test_cdrom_pio
);
1942 qtest_add_func("/ahci/cdrom/pio/multi", test_cdrom_pio_multi
);
1944 qtest_add_func("/ahci/cdrom/pio/bcl", test_atapi_bcl
);
1945 qtest_add_func("/ahci/cdrom/eject", test_atapi_tray
);