POWERPC_MMU_MPC8xx = 0x00000007,
/* BookE MMU model */
POWERPC_MMU_BOOKE = 0x00000008,
- /* BookE FSL MMU model */
- POWERPC_MMU_BOOKE_FSL = 0x00000009,
+ /* BookE 2.06 MMU model */
+ POWERPC_MMU_BOOKE206 = 0x00000009,
/* PowerPC 601 MMU model (specific BATs format) */
POWERPC_MMU_601 = 0x0000000A,
#if defined(TARGET_PPC64)
/* 970FX specific exceptions */
POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
- /* Freescale embeded cores specific exceptions */
+ /* Freescale embedded cores specific exceptions */
POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
#define MSR_CM 31 /* Computation mode for BookE hflags */
#define MSR_ICM 30 /* Interrupt computation mode for BookE */
#define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
+ #define MSR_GS 28 /* guest state for BookE */
#define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
#define MSR_VR 25 /* altivec available x hflags */
#define MSR_SPE 25 /* SPE enable for BookE x hflags */
#define msr_cm ((env->msr >> MSR_CM) & 1)
#define msr_icm ((env->msr >> MSR_ICM) & 1)
#define msr_thv ((env->msr >> MSR_THV) & 1)
+ #define msr_gs ((env->msr >> MSR_GS) & 1)
#define msr_ucle ((env->msr >> MSR_UCLE) & 1)
#define msr_vr ((env->msr >> MSR_VR) & 1)
#define msr_spe ((env->msr >> MSR_SPE) & 1)
#define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
#define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
+ /*****************************************************************************/
+ /* BookE e500 MMU registers */
+
+ #define MAS0_NV_SHIFT 0
+ #define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
+
+ #define MAS0_WQ_SHIFT 12
+ #define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
+ /* Write TLB entry regardless of reservation */
+ #define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
+ /* Write TLB entry only already in use */
+ #define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
+ /* Clear TLB entry */
+ #define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
+
+ #define MAS0_HES_SHIFT 14
+ #define MAS0_HES (1 << MAS0_HES_SHIFT)
+
+ #define MAS0_ESEL_SHIFT 16
+ #define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
+
+ #define MAS0_TLBSEL_SHIFT 28
+ #define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
+ #define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
+ #define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
+ #define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
+ #define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
+
+ #define MAS0_ATSEL_SHIFT 31
+ #define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
+ #define MAS0_ATSEL_TLB 0
+ #define MAS0_ATSEL_LRAT MAS0_ATSEL
+
+ #define MAS1_TSIZE_SHIFT 8
+ #define MAS1_TSIZE_MASK (0xf << MAS1_TSIZE_SHIFT)
+
+ #define MAS1_TS_SHIFT 12
+ #define MAS1_TS (1 << MAS1_TS_SHIFT)
+
+ #define MAS1_IND_SHIFT 13
+ #define MAS1_IND (1 << MAS1_IND_SHIFT)
+
+ #define MAS1_TID_SHIFT 16
+ #define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
+
+ #define MAS1_IPROT_SHIFT 30
+ #define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
+
+ #define MAS1_VALID_SHIFT 31
+ #define MAS1_VALID 0x80000000
+
+ #define MAS2_EPN_SHIFT 12
+ #define MAS2_EPN_MASK (0xfffff << MAS2_EPN_SHIFT)
+
+ #define MAS2_ACM_SHIFT 6
+ #define MAS2_ACM (1 << MAS2_ACM_SHIFT)
+
+ #define MAS2_VLE_SHIFT 5
+ #define MAS2_VLE (1 << MAS2_VLE_SHIFT)
+
+ #define MAS2_W_SHIFT 4
+ #define MAS2_W (1 << MAS2_W_SHIFT)
+
+ #define MAS2_I_SHIFT 3
+ #define MAS2_I (1 << MAS2_I_SHIFT)
+
+ #define MAS2_M_SHIFT 2
+ #define MAS2_M (1 << MAS2_M_SHIFT)
+
+ #define MAS2_G_SHIFT 1
+ #define MAS2_G (1 << MAS2_G_SHIFT)
+
+ #define MAS2_E_SHIFT 0
+ #define MAS2_E (1 << MAS2_E_SHIFT)
+
+ #define MAS3_RPN_SHIFT 12
+ #define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
+
+ #define MAS3_U0 0x00000200
+ #define MAS3_U1 0x00000100
+ #define MAS3_U2 0x00000080
+ #define MAS3_U3 0x00000040
+ #define MAS3_UX 0x00000020
+ #define MAS3_SX 0x00000010
+ #define MAS3_UW 0x00000008
+ #define MAS3_SW 0x00000004
+ #define MAS3_UR 0x00000002
+ #define MAS3_SR 0x00000001
+ #define MAS3_SPSIZE_SHIFT 1
+ #define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
+
+ #define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
+ #define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
+ #define MAS4_TIDSELD_MASK 0x00030000
+ #define MAS4_TIDSELD_PID0 0x00000000
+ #define MAS4_TIDSELD_PID1 0x00010000
+ #define MAS4_TIDSELD_PID2 0x00020000
+ #define MAS4_TIDSELD_PIDZ 0x00030000
+ #define MAS4_INDD 0x00008000 /* Default IND */
+ #define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
+ #define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
+ #define MAS4_ACMD 0x00000040
+ #define MAS4_VLED 0x00000020
+ #define MAS4_WD 0x00000010
+ #define MAS4_ID 0x00000008
+ #define MAS4_MD 0x00000004
+ #define MAS4_GD 0x00000002
+ #define MAS4_ED 0x00000001
+ #define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
+ #define MAS4_WIMGED_SHIFT 0
+
+ #define MAS5_SGS 0x80000000
+ #define MAS5_SLPID_MASK 0x00000fff
+
+ #define MAS6_SPID0 0x3fff0000
+ #define MAS6_SPID1 0x00007ffe
+ #define MAS6_ISIZE(x) MAS1_TSIZE(x)
+ #define MAS6_SAS 0x00000001
+ #define MAS6_SPID MAS6_SPID0
+ #define MAS6_SIND 0x00000002 /* Indirect page */
+ #define MAS6_SIND_SHIFT 1
+ #define MAS6_SPID_MASK 0x3fff0000
+ #define MAS6_SPID_SHIFT 16
+ #define MAS6_ISIZE_MASK 0x00000f80
+ #define MAS6_ISIZE_SHIFT 7
+
+ #define MAS7_RPN 0xffffffff
+
+ #define MAS8_TGS 0x80000000
+ #define MAS8_VF 0x40000000
+ #define MAS8_TLBPID 0x00000fff
+
+ /* Bit definitions for MMUCFG */
+ #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
+ #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
+ #define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
+ #define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
+ #define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
+ #define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
+ #define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
+ #define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
+ #define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
+
+ /* Bit definitions for MMUCSR0 */
+ #define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
+ #define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
+ #define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
+ #define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
+ #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
+ MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
+ #define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
+ #define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
+ #define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
+ #define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
+
+ /* TLBnCFG encoding */
+ #define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
+ #define TLBnCFG_HES 0x00002000 /* HW select supported */
+ #define TLBnCFG_AVAIL 0x00004000 /* variable page size */
+ #define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
+ #define TLBnCFG_GTWE 0x00010000 /* Guest can write */
+ #define TLBnCFG_IND 0x00020000 /* IND entries supported */
+ #define TLBnCFG_PT 0x00040000 /* Can load from page table */
+ #define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
+ #define TLBnCFG_MINSIZE_SHIFT 20
+ #define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
+ #define TLBnCFG_MAXSIZE_SHIFT 16
+ #define TLBnCFG_ASSOC 0xff000000 /* Associativity */
+ #define TLBnCFG_ASSOC_SHIFT 24
+
+ /* TLBnPS encoding */
+ #define TLBnPS_4K 0x00000004
+ #define TLBnPS_8K 0x00000008
+ #define TLBnPS_16K 0x00000010
+ #define TLBnPS_32K 0x00000020
+ #define TLBnPS_64K 0x00000040
+ #define TLBnPS_128K 0x00000080
+ #define TLBnPS_256K 0x00000100
+ #define TLBnPS_512K 0x00000200
+ #define TLBnPS_1M 0x00000400
+ #define TLBnPS_2M 0x00000800
+ #define TLBnPS_4M 0x00001000
+ #define TLBnPS_8M 0x00002000
+ #define TLBnPS_16M 0x00004000
+ #define TLBnPS_32M 0x00008000
+ #define TLBnPS_64M 0x00010000
+ #define TLBnPS_128M 0x00020000
+ #define TLBnPS_256M 0x00040000
+ #define TLBnPS_512M 0x00080000
+ #define TLBnPS_1G 0x00100000
+ #define TLBnPS_2G 0x00200000
+ #define TLBnPS_4G 0x00400000
+ #define TLBnPS_8G 0x00800000
+ #define TLBnPS_16G 0x01000000
+ #define TLBnPS_32G 0x02000000
+ #define TLBnPS_64G 0x04000000
+ #define TLBnPS_128G 0x08000000
+ #define TLBnPS_256G 0x10000000
+
+ /* tlbilx action encoding */
+ #define TLBILX_T_ALL 0
+ #define TLBILX_T_TID 1
+ #define TLBILX_T_FULLMATCH 3
+ #define TLBILX_T_CLASS0 4
+ #define TLBILX_T_CLASS1 5
+ #define TLBILX_T_CLASS2 6
+ #define TLBILX_T_CLASS3 7
+
+ /* BookE 2.06 helper defines */
+
+ #define BOOKE206_FLUSH_TLB0 (1 << 0)
+ #define BOOKE206_FLUSH_TLB1 (1 << 1)
+ #define BOOKE206_FLUSH_TLB2 (1 << 2)
+ #define BOOKE206_FLUSH_TLB3 (1 << 3)
+
+ /* number of possible TLBs */
+ #define BOOKE206_MAX_TLBN 4
+
/*****************************************************************************/
/* The whole PowerPC CPU context */
#define NB_MMU_MODES 3
int nb_BATs;
target_ulong DBAT[2][8];
target_ulong IBAT[2][8];
- /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
+ /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
int nb_tlb; /* Total number of TLB */
int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
int nb_ways; /* Number of ways in the TLB set */
int bfd_mach;
uint32_t flags;
uint64_t insns_flags;
+ uint64_t insns_flags2;
#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
target_phys_addr_t vpa;
void store_40x_sler (CPUPPCState *env, uint32_t val);
void store_booke_tcr (CPUPPCState *env, target_ulong val);
void store_booke_tsr (CPUPPCState *env, target_ulong val);
+ void booke206_flush_tlb(CPUState *env, int flags, const int check_iprot);
+ int ppcemb_tlb_check(CPUState *env, ppcemb_tlb_t *tlb,
+ target_phys_addr_t *raddrp, target_ulong address,
+ uint32_t pid, int ext, int i);
void ppc_tlb_invalidate_all (CPUPPCState *env);
void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
#if defined(TARGET_PPC64)
#define SPR_HSPRG1 (0x131)
#define SPR_HDSISR (0x132)
#define SPR_HDAR (0x133)
+ #define SPR_BOOKE_EPCR (0x133)
#define SPR_SPURR (0x134)
#define SPR_BOOKE_DBCR0 (0x134)
#define SPR_IBCR (0x135)
PPC_DCRUX = 0x4000000000000000ULL,
/* popcntw and popcntd instructions */
PPC_POPCNTWD = 0x8000000000000000ULL,
+
+ /* extended type values */
+
+ /* BookE 2.06 PowerPC specification */
+ PPC2_BOOKE206 = 0x0000000000000001ULL,
};
/*****************************************************************************/
#endif
}
+ #if !defined(CONFIG_USER_ONLY)
+ static inline int booke206_tlbe_id(CPUState *env, ppcemb_tlb_t *tlbe)
+ {
+ ulong tlbel = (ulong)tlbe;
+ ulong tlbl = (ulong)env->tlb;
+
+ return (tlbel - tlbl) / sizeof(env->tlb[0]);
+ }
+
+ static inline int booke206_tlb_size(CPUState *env, int tlbn)
+ {
+ uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
+ int r = tlbncfg & TLBnCFG_N_ENTRY;
+ return r;
+ }
+
+ static inline int booke206_tlb_ways(CPUState *env, int tlbn)
+ {
+ uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
+ int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
+ return r;
+ }
+
+ static inline int booke206_tlbe_to_tlbn(CPUState *env, ppcemb_tlb_t *tlbe)
+ {
+ int id = booke206_tlbe_id(env, tlbe);
+ int end = 0;
+ int i;
+
+ for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
+ end += booke206_tlb_size(env, i);
+ if (id < end) {
+ return i;
+ }
+ }
+
+ cpu_abort(env, "Unknown TLBe: %d\n", id);
+ return 0;
+ }
+
+ static inline int booke206_tlbe_to_way(CPUState *env, ppcemb_tlb_t *tlb)
+ {
+ int tlbn = booke206_tlbe_to_tlbn(env, tlb);
+ int tlbid = booke206_tlbe_id(env, tlb);
+ return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
+ }
+
+ static inline ppcemb_tlb_t *booke206_get_tlbe(CPUState *env, const int tlbn,
+ target_ulong ea, int way)
+ {
+ int r;
+ uint32_t ways = booke206_tlb_ways(env, tlbn);
+ int ways_bits = ffs(ways) - 1;
+ int tlb_bits = ffs(booke206_tlb_size(env, tlbn)) - 1;
+ int i;
+
+ way &= ways - 1;
+ ea >>= MAS2_EPN_SHIFT;
+ ea &= (1 << (tlb_bits - ways_bits)) - 1;
+ r = (ea << ways_bits) | way;
+
+ /* bump up to tlbn index */
+ for (i = 0; i < tlbn; i++) {
+ r += booke206_tlb_size(env, i);
+ }
+
+ return &env->tlb[r].tlbe;
+ }
+
+ #endif
+
extern void (*cpu_ppc_hypercall)(CPUState *);
#endif /* !defined (__CPU_PPC_H__) */
uint32_t pvr;
uint32_t svr;
uint64_t insns_flags;
+ uint64_t insns_flags2;
uint64_t msr_mask;
powerpc_mmu_t mmu_model;
powerpc_excp_t excp_model;
#endif
}
+ #if !defined(CONFIG_USER_ONLY)
+ static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
+ {
+ TCGv t0 = tcg_temp_new();
+
+ tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~256);
+ gen_store_spr(sprn, t0);
+ tcg_temp_free(t0);
+ }
+
+ static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
+ {
+ TCGv t0 = tcg_const_i32(sprn);
+ gen_helper_booke206_tlbflush(t0);
+ tcg_temp_free(t0);
+ }
+
+ static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
+ {
+ TCGv t0 = tcg_const_i32(sprn);
+ gen_helper_booke_setpid(t0, cpu_gpr[gprn]);
+ tcg_temp_free(t0);
+ }
+ #endif
+
static void gen_spr_usprgh (CPUPPCState *env)
{
spr_register(env, SPR_USPRG4, "USPRG4",
}
spr_register(env, SPR_BOOKE_PID, "PID",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_booke_pid,
0x00000000);
spr_register(env, SPR_BOOKE_TCR, "TCR",
SPR_NOACCESS, SPR_NOACCESS,
0x00000000);
}
- /* FSL storage control registers */
- static void gen_spr_BookE_FSL (CPUPPCState *env, uint32_t mas_mask)
+ static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
+ uint32_t maxsize, uint32_t flags,
+ uint32_t nentries)
+ {
+ return (assoc << TLBnCFG_ASSOC_SHIFT) |
+ (minsize << TLBnCFG_MINSIZE_SHIFT) |
+ (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
+ flags | nentries;
+ }
+
+ /* BookE 2.06 storage control registers */
+ static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
+ uint32_t *tlbncfg)
{
#if !defined(CONFIG_USER_ONLY)
const char *mas_names[8] = {
/* XXX : not implemented */
spr_register(env, SPR_BOOKE_PID1, "PID1",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_booke_pid,
0x00000000);
}
if (env->nb_pids > 2) {
/* XXX : not implemented */
spr_register(env, SPR_BOOKE_PID2, "PID2",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_booke_pid,
0x00000000);
}
/* XXX : not implemented */
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
0x00000000); /* TOFIX */
- /* XXX : not implemented */
- spr_register(env, SPR_MMUCSR0, "MMUCSR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000); /* TOFIX */
switch (env->nb_ways) {
case 4:
- /* XXX : not implemented */
spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
- 0x00000000); /* TOFIX */
+ tlbncfg[3]);
/* Fallthru */
case 3:
- /* XXX : not implemented */
spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
- 0x00000000); /* TOFIX */
+ tlbncfg[2]);
/* Fallthru */
case 2:
- /* XXX : not implemented */
spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
- 0x00000000); /* TOFIX */
+ tlbncfg[1]);
/* Fallthru */
case 1:
- /* XXX : not implemented */
spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
- 0x00000000); /* TOFIX */
+ tlbncfg[0]);
/* Fallthru */
case 0:
default:
break;
}
#endif
+
+ gen_spr_usprgh(env);
}
/* SPR specific to PowerPC 440 implementation */
PPC_CACHE_DCBZ | \
PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_4xx_COMMON | PPC_40x_EXCP)
+ #define POWERPC_INSNS2_401 (PPC_NONE)
#define POWERPC_MSRM_401 (0x00000000000FD201ULL)
#define POWERPC_MMU_401 (POWERPC_MMU_REAL)
#define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
PPC_4xx_COMMON | PPC_40x_EXCP)
+ #define POWERPC_INSNS2_401x2 (PPC_NONE)
#define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
#define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
#define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
PPC_4xx_COMMON | PPC_40x_EXCP)
+ #define POWERPC_INSNS2_401x3 (PPC_NONE)
#define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
#define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
#define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
PPC_4xx_COMMON | PPC_40x_EXCP)
+ #define POWERPC_INSNS2_IOP480 (PPC_NONE)
#define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
#define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
#define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
PPC_CACHE_DCBZ | \
PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_4xx_COMMON | PPC_40x_EXCP)
+ #define POWERPC_INSNS2_403 (PPC_NONE)
#define POWERPC_MSRM_403 (0x000000000007D00DULL)
#define POWERPC_MMU_403 (POWERPC_MMU_REAL)
#define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
PPC_4xx_COMMON | PPC_40x_EXCP)
+ #define POWERPC_INSNS2_403GCX (PPC_NONE)
#define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
#define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
#define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
+ #define POWERPC_INSNS2_405 (PPC_NONE)
#define POWERPC_MSRM_405 (0x000000000006E630ULL)
#define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
#define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
PPC_MEM_TLBSYNC | PPC_MFTB | \
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
PPC_440_SPEC)
+ #define POWERPC_INSNS2_440EP (PPC_NONE)
#define POWERPC_MSRM_440EP (0x000000000006D630ULL)
#define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
#define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | \
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
PPC_440_SPEC)
+ #define POWERPC_INSNS2_440GP (PPC_NONE)
#define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
#define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
#define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
PPC_MEM_TLBSYNC | PPC_MFTB | \
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
PPC_440_SPEC)
+ #define POWERPC_INSNS2_440x4 (PPC_NONE)
#define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
#define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
#define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
PPC_MEM_TLBSYNC | PPC_MFTB | \
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
PPC_440_SPEC)
+ #define POWERPC_INSNS2_440x5 (PPC_NONE)
#define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
#define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
#define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
PPC_MEM_TLBSYNC | PPC_TLBIVA | \
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
PPC_440_SPEC)
+ #define POWERPC_INSNS2_460 (PPC_NONE)
#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
#define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
#define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
PPC_MEM_TLBSYNC | PPC_TLBIVA | \
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
PPC_440_SPEC)
+ #define POWERPC_INSNS2_460F (PPC_NONE)
#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
#define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
#define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
PPC_MEM_EIEIO | PPC_MEM_SYNC | \
PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
PPC_MFTB)
+ #define POWERPC_INSNS2_MPC5xx (PPC_NONE)
#define POWERPC_MSRM_MPC5xx (0x000000000001FF43ULL)
#define POWERPC_MMU_MPC5xx (POWERPC_MMU_REAL)
#define POWERPC_EXCP_MPC5xx (POWERPC_EXCP_603)
#define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING | \
PPC_MEM_EIEIO | PPC_MEM_SYNC | \
PPC_CACHE_ICBI | PPC_MFTB)
+ #define POWERPC_INSNS2_MPC8xx (PPC_NONE)
#define POWERPC_MSRM_MPC8xx (0x000000000001F673ULL)
#define POWERPC_MMU_MPC8xx (POWERPC_MMU_MPC8xx)
#define POWERPC_EXCP_MPC8xx (POWERPC_EXCP_603)
PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
PPC_SEGMENT | PPC_EXTERN)
+ #define POWERPC_INSNS2_G2 (PPC_NONE)
#define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
#define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
//#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
PPC_SEGMENT | PPC_EXTERN)
+ #define POWERPC_INSNS2_G2LE (PPC_NONE)
#define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
#define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
#define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
PPC_BOOKE)
+ #define POWERPC_INSNS2_e200 (PPC_NONE)
#define POWERPC_MSRM_e200 (0x000000000606FF30ULL)
- #define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE_FSL)
+ #define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE206)
#define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE)
#define POWERPC_INPUT_e200 (PPC_FLAGS_INPUT_BookE)
#define POWERPC_BFDM_e200 (bfd_mach_ppc_860)
&spr_read_spefscr, &spr_write_spefscr,
0x00000000);
/* Memory management */
- gen_spr_BookE_FSL(env, 0x0000005D);
+ gen_spr_BookE206(env, 0x0000005D, NULL);
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
+ /* XXX : not implemented */
+ spr_register(env, SPR_MMUCSR0, "MMUCSR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000); /* TOFIX */
spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
PPC_SEGMENT | PPC_EXTERN)
+ #define POWERPC_INSNS2_e300 (PPC_NONE)
#define POWERPC_MSRM_e300 (0x000000000007FFF3ULL)
#define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx)
#define POWERPC_EXCP_e300 (POWERPC_EXCP_603)
PPC_WRTEE | PPC_RFDI | \
PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
- PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
- PPC_BOOKE)
+ PPC_MEM_TLBSYNC | PPC_TLBIVAX)
+ #define POWERPC_INSNS2_e500v1 (PPC2_BOOKE206)
#define POWERPC_MSRM_e500v1 (0x000000000606FF30ULL)
- #define POWERPC_MMU_e500v1 (POWERPC_MMU_BOOKE_FSL)
+ #define POWERPC_MMU_e500v1 (POWERPC_MMU_BOOKE206)
#define POWERPC_EXCP_e500v1 (POWERPC_EXCP_BOOKE)
#define POWERPC_INPUT_e500v1 (PPC_FLAGS_INPUT_BookE)
#define POWERPC_BFDM_e500v1 (bfd_mach_ppc_860)
POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
POWERPC_FLAG_BUS_CLK)
#define check_pow_e500v1 check_pow_hid0
- #define init_proc_e500v1 init_proc_e500
+ #define init_proc_e500v1 init_proc_e500v1
/* e500v2 core */
#define POWERPC_INSNS_e500v2 (PPC_INSNS_BASE | PPC_ISEL | \
PPC_WRTEE | PPC_RFDI | \
PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
- PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
- PPC_BOOKE)
+ PPC_MEM_TLBSYNC | PPC_TLBIVAX)
+ #define POWERPC_INSNS2_e500v2 (PPC2_BOOKE206)
#define POWERPC_MSRM_e500v2 (0x000000000606FF30ULL)
- #define POWERPC_MMU_e500v2 (POWERPC_MMU_BOOKE_FSL)
+ #define POWERPC_MMU_e500v2 (POWERPC_MMU_BOOKE206)
#define POWERPC_EXCP_e500v2 (POWERPC_EXCP_BOOKE)
#define POWERPC_INPUT_e500v2 (PPC_FLAGS_INPUT_BookE)
#define POWERPC_BFDM_e500v2 (bfd_mach_ppc_860)
POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
POWERPC_FLAG_BUS_CLK)
#define check_pow_e500v2 check_pow_hid0
- #define init_proc_e500v2 init_proc_e500
+ #define init_proc_e500v2 init_proc_e500v2
- static void init_proc_e500 (CPUPPCState *env)
+ static void init_proc_e500 (CPUPPCState *env, int version)
{
+ uint32_t tlbncfg[2];
+ #if !defined(CONFIG_USER_ONLY)
+ int i;
+ #endif
+
/* Time base */
gen_tbl(env);
- gen_spr_BookE(env, 0x0000000F0000FD7FULL);
+ /*
+ * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
+ * complain when accessing them.
+ * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
+ */
+ gen_spr_BookE(env, 0x0000000F0000FFFFULL);
/* Processor identification */
spr_register(env, SPR_BOOKE_PIR, "PIR",
SPR_NOACCESS, SPR_NOACCESS,
/* Memory management */
#if !defined(CONFIG_USER_ONLY)
env->nb_pids = 3;
+ env->nb_ways = 2;
+ env->id_tlbs = 0;
+ switch (version) {
+ case 1:
+ /* e500v1 */
+ tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
+ tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
+ break;
+ case 2:
+ /* e500v2 */
+ tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
+ tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
+ break;
+ default:
+ cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
+ }
#endif
- gen_spr_BookE_FSL(env, 0x0000005F);
+ gen_spr_BookE206(env, 0x000000DF, tlbncfg);
/* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
/* XXX : not implemented */
spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_e500_l1csr0,
0x00000000);
/* XXX : not implemented */
spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
+ spr_register(env, SPR_MMUCSR0, "MMUCSR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_booke206_mmucsr0,
+ 0x00000000);
+
#if !defined(CONFIG_USER_ONLY)
- env->nb_tlb = 64;
- env->nb_ways = 1;
- env->id_tlbs = 0;
+ env->nb_tlb = 0;
+ for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
+ env->nb_tlb += booke206_tlb_size(env, i);
+ }
#endif
+
init_excp_e200(env);
env->dcache_line_size = 32;
env->icache_line_size = 32;
ppce500_irq_init(env);
}
+ static void init_proc_e500v1(CPUPPCState *env)
+ {
+ init_proc_e500(env, 1);
+ }
+
+ static void init_proc_e500v2(CPUPPCState *env)
+ {
+ init_proc_e500(env, 2);
+ }
+
/* Non-embedded PowerPC */
/* POWER : same as 601, without mfmsr, mfsr */
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
PPC_SEGMENT | PPC_EXTERN)
+ #define POWERPC_INSNS2_601 (PPC_NONE)
#define POWERPC_MSRM_601 (0x000000000000FD70ULL)
#define POWERPC_MSRR_601 (0x0000000000001040ULL)
//#define POWERPC_MMU_601 (POWERPC_MMU_601)
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
PPC_SEGMENT | PPC_EXTERN)
+ #define POWERPC_INSNS2_601v (PPC_NONE)
#define POWERPC_MSRM_601v (0x000000000000FD70ULL)
#define POWERPC_MSRR_601v (0x0000000000001040ULL)
#define POWERPC_MMU_601v (POWERPC_MMU_601)
PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
PPC_SEGMENT | PPC_602_SPEC)
+ #define POWERPC_INSNS2_602 (PPC_NONE)
#define POWERPC_MSRM_602 (0x0000000000C7FF73ULL)
/* XXX: 602 MMU is quite specific. Should add a special case */
#define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
PPC_SEGMENT | PPC_EXTERN)
+ #define POWERPC_INSNS2_603 (PPC_NONE)
#define POWERPC_MSRM_603 (0x000000000007FF73ULL)
#define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
//#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
PPC_SEGMENT | PPC_EXTERN)
+ #define POWERPC_INSNS2_603E (PPC_NONE)
#define POWERPC_MSRM_603E (0x000000000007FF73ULL)
#define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
//#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
PPC_SEGMENT | PPC_EXTERN)
+ #define POWERPC_INSNS2_604 (PPC_NONE)
#define POWERPC_MSRM_604 (0x000000000005FF77ULL)
#define POWERPC_MMU_604 (POWERPC_MMU_32B)
//#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
PPC_SEGMENT | PPC_EXTERN)
+ #define POWERPC_INSNS2_604E (PPC_NONE)
#define POWERPC_MSRM_604E (0x000000000005FF77ULL)
#define POWERPC_MMU_604E (POWERPC_MMU_32B)
#define POWERPC_EXCP_604E (POWERPC_EXCP_604)
PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
PPC_SEGMENT | PPC_EXTERN)
+ #define POWERPC_INSNS2_740 (PPC_NONE)
#define POWERPC_MSRM_740 (0x000000000005FF77ULL)
#define POWERPC_MMU_740 (POWERPC_MMU_32B)
#define POWERPC_EXCP_740 (POWERPC_EXCP_7x0)
PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
PPC_SEGMENT | PPC_EXTERN)
+ #define POWERPC_INSNS2_750 (PPC_NONE)
#define POWERPC_MSRM_750 (0x000000000005FF77ULL)
#define POWERPC_MMU_750 (POWERPC_MMU_32B)
#define POWERPC_EXCP_750 (POWERPC_EXCP_7x0)
PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
PPC_SEGMENT | PPC_EXTERN)
+ #define POWERPC_INSNS2_750cl (PPC_NONE)
#define POWERPC_MSRM_750cl (0x000000000005FF77ULL)
#define POWERPC_MMU_750cl (POWERPC_MMU_32B)
#define POWERPC_EXCP_750cl (POWERPC_EXCP_7x0)
PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
PPC_SEGMENT | PPC_EXTERN)
+ #define POWERPC_INSNS2_750cx (PPC_NONE)
#define POWERPC_MSRM_750cx (0x000000000005FF77ULL)
#define POWERPC_MMU_750cx (POWERPC_MMU_32B)
#define POWERPC_EXCP_750cx (POWERPC_EXCP_7x0)
PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
PPC_SEGMENT | PPC_EXTERN)
+ #define POWERPC_INSNS2_750fx (PPC_NONE)
#define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
#define POWERPC_MMU_750fx (POWERPC_MMU_32B)
#define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
PPC_SEGMENT | PPC_EXTERN)
+ #define POWERPC_INSNS2_750gx (PPC_NONE)
#define POWERPC_MSRM_750gx (0x000000000005FF77ULL)
#define POWERPC_MMU_750gx (POWERPC_MMU_32B)
#define POWERPC_EXCP_750gx (POWERPC_EXCP_7x0)
PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
PPC_SEGMENT | PPC_EXTERN)
+ #define POWERPC_INSNS2_745 (PPC_NONE)
#define POWERPC_MSRM_745 (0x000000000005FF77ULL)
#define POWERPC_MMU_745 (POWERPC_MMU_SOFT_6xx)
#define POWERPC_EXCP_745 (POWERPC_EXCP_7x5)
PPC_MEM_SYNC | PPC_MEM_EIEIO | \
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
PPC_SEGMENT | PPC_EXTERN)
+ #define POWERPC_INSNS2_755 (PPC_NONE)
#define POWERPC_MSRM_755 (0x000000000005FF77ULL)
#define POWERPC_MMU_755 (POWERPC_MMU_SOFT_6xx)
#define POWERPC_EXCP_755 (POWERPC_EXCP_7x5)
PPC_MEM_TLBIA | \
PPC_SEGMENT | PPC_EXTERN | \
PPC_ALTIVEC)
+ #define POWERPC_INSNS2_7400 (PPC_NONE)
#define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
#define POWERPC_MMU_7400 (POWERPC_MMU_32B)
#define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
PPC_MEM_TLBIA | \
PPC_SEGMENT | PPC_EXTERN | \
PPC_ALTIVEC)
+ #define POWERPC_INSNS2_7410 (PPC_NONE)
#define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
#define POWERPC_MMU_7410 (POWERPC_MMU_32B)
#define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
PPC_MEM_TLBIA | PPC_74xx_TLB | \
PPC_SEGMENT | PPC_EXTERN | \
PPC_ALTIVEC)
+ #define POWERPC_INSNS2_7440 (PPC_NONE)
#define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
#define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
#define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
PPC_MEM_TLBIA | PPC_74xx_TLB | \
PPC_SEGMENT | PPC_EXTERN | \
PPC_ALTIVEC)
+ #define POWERPC_INSNS2_7450 (PPC_NONE)
#define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
#define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
#define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
PPC_MEM_TLBIA | PPC_74xx_TLB | \
PPC_SEGMENT | PPC_EXTERN | \
PPC_ALTIVEC)
+ #define POWERPC_INSNS2_7445 (PPC_NONE)
#define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
#define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
#define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
PPC_MEM_TLBIA | PPC_74xx_TLB | \
PPC_SEGMENT | PPC_EXTERN | \
PPC_ALTIVEC)
+ #define POWERPC_INSNS2_7455 (PPC_NONE)
#define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
#define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
#define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
PPC_MEM_TLBIA | PPC_74xx_TLB | \
PPC_SEGMENT | PPC_EXTERN | \
PPC_ALTIVEC)
+ #define POWERPC_INSNS2_7457 (PPC_NONE)
#define POWERPC_MSRM_7457 (0x000000000205FF77ULL)
#define POWERPC_MMU_7457 (POWERPC_MMU_SOFT_74xx)
#define POWERPC_EXCP_7457 (POWERPC_EXCP_74xx)
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
PPC_64B | PPC_ALTIVEC | \
PPC_SEGMENT_64B | PPC_SLBI)
+ #define POWERPC_INSNS2_970 (PPC_NONE)
#define POWERPC_MSRM_970 (0x900000000204FF36ULL)
#define POWERPC_MMU_970 (POWERPC_MMU_64B)
//#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
PPC_64B | PPC_ALTIVEC | \
PPC_SEGMENT_64B | PPC_SLBI)
+ #define POWERPC_INSNS2_970FX (PPC_NONE)
#define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
#define POWERPC_MMU_970FX (POWERPC_MMU_64B)
#define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
PPC_64B | PPC_ALTIVEC | \
PPC_SEGMENT_64B | PPC_SLBI)
+ #define POWERPC_INSNS2_970GX (PPC_NONE)
#define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
#define POWERPC_MMU_970GX (POWERPC_MMU_64B)
#define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
PPC_64B | PPC_ALTIVEC | \
PPC_SEGMENT_64B | PPC_SLBI)
+ #define POWERPC_INSNS2_970MP (PPC_NONE)
#define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
#define POWERPC_MMU_970MP (POWERPC_MMU_64B)
#define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
PPC_64B | PPC_ALTIVEC | \
PPC_SEGMENT_64B | PPC_SLBI | \
PPC_POPCNTB | PPC_POPCNTWD)
+ #define POWERPC_INSNS2_POWER7 (PPC_NONE)
#define POWERPC_MSRM_POWER7 (0x800000000204FF36ULL)
#define POWERPC_MMU_POWER7 (POWERPC_MMU_2_06)
#define POWERPC_EXCP_POWER7 (POWERPC_EXCP_POWER7)
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
PPC_SEGMENT | PPC_EXTERN | \
PPC_64B | PPC_SLBI)
+ #define POWERPC_INSNS2_620 (PPC_NONE)
#define POWERPC_MSRM_620 (0x800000000005FF77ULL)
//#define POWERPC_MMU_620 (POWERPC_MMU_620)
#define POWERPC_EXCP_620 (POWERPC_EXCP_970)
/* Default 32 bits PowerPC target will be 604 */
#define CPU_POWERPC_PPC32 CPU_POWERPC_604
#define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
+ #define POWERPC_INSNS2_PPC32 POWERPC_INSNS2_604
#define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
#define POWERPC_MMU_PPC32 POWERPC_MMU_604
#define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
/* Default 64 bits PowerPC target will be 970 FX */
#define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
#define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
+ #define POWERPC_INSNS2_PPC64 POWERPC_INSNS2_970FX
#define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
#define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
#define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
/* Default PowerPC target will be PowerPC 32 */
#if defined (TARGET_PPC64) && 0 // XXX: TODO
- #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
- #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
- #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
- #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
- #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
- #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
- #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
- #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
- #define check_pow_DEFAULT check_pow_PPC64
- #define init_proc_DEFAULT init_proc_PPC64
+ #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
+ #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
+ #define POWERPC_INSNS2_DEFAULT POWERPC_INSNS_PPC64
+ #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
+ #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
+ #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
+ #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
+ #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
+ #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
+ #define check_pow_DEFAULT check_pow_PPC64
+ #define init_proc_DEFAULT init_proc_PPC64
#else
- #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
- #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
- #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
- #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
- #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
- #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
- #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
- #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
- #define check_pow_DEFAULT check_pow_PPC32
- #define init_proc_DEFAULT init_proc_PPC32
+ #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
+ #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
+ #define POWERPC_INSNS2_DEFAULT POWERPC_INSNS_PPC32
+ #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
+ #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
+ #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
+ #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
+ #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
+ #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
+ #define check_pow_DEFAULT check_pow_PPC32
+ #define init_proc_DEFAULT init_proc_PPC32
#endif
/*****************************************************************************/
/* PowerPC CPU definitions */
#define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
{ \
- .name = _name, \
- .pvr = _pvr, \
- .svr = _svr, \
- .insns_flags = glue(POWERPC_INSNS_,_type), \
- .msr_mask = glue(POWERPC_MSRM_,_type), \
- .mmu_model = glue(POWERPC_MMU_,_type), \
- .excp_model = glue(POWERPC_EXCP_,_type), \
- .bus_model = glue(POWERPC_INPUT_,_type), \
- .bfd_mach = glue(POWERPC_BFDM_,_type), \
- .flags = glue(POWERPC_FLAG_,_type), \
- .init_proc = &glue(init_proc_,_type), \
- .check_pow = &glue(check_pow_,_type), \
+ .name = _name, \
+ .pvr = _pvr, \
+ .svr = _svr, \
+ .insns_flags = glue(POWERPC_INSNS_,_type), \
+ .insns_flags2 = glue(POWERPC_INSNS2_,_type), \
+ .msr_mask = glue(POWERPC_MSRM_,_type), \
+ .mmu_model = glue(POWERPC_MMU_,_type), \
+ .excp_model = glue(POWERPC_EXCP_,_type), \
+ .bus_model = glue(POWERPC_INPUT_,_type), \
+ .bfd_mach = glue(POWERPC_BFDM_,_type), \
+ .flags = glue(POWERPC_FLAG_,_type), \
+ .init_proc = &glue(init_proc_,_type), \
+ .check_pow = &glue(check_pow_,_type), \
}
#define POWERPC_DEF(_name, _pvr, _type) \
POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
};
/*****************************************************************************/
-/* Generic CPU instanciation routine */
+/* Generic CPU instantiation routine */
static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
{
#if !defined(CONFIG_USER_ONLY)
fill_new_table(env->opcodes, 0x40);
for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
- if ((opc->handler.type & def->insns_flags) != 0) {
+ if (((opc->handler.type & def->insns_flags) != 0) ||
+ ((opc->handler.type2 & def->insns_flags2) != 0)) {
if (register_insn(env->opcodes, opc) < 0) {
printf("*** ERROR initializing PowerPC instruction "
"0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
env->excp_model = def->excp_model;
env->bus_model = def->bus_model;
env->insns_flags = def->insns_flags;
+ env->insns_flags2 = def->insns_flags2;
env->flags = def->flags;
env->bfd_mach = def->bfd_mach;
env->check_pow = def->check_pow;
case POWERPC_MMU_BOOKE:
mmu_model = "PowerPC BookE";
break;
- case POWERPC_MMU_BOOKE_FSL:
- mmu_model = "PowerPC BookE FSL";
+ case POWERPC_MMU_BOOKE206:
+ mmu_model = "PowerPC BookE 2.06";
break;
case POWERPC_MMU_601:
mmu_model = "PowerPC 601";
projects / mirror_qemu.git / commitdiff