OR1KSIM_ETHOC_IRQ = 4,
};
+enum {
+ OR1KSIM_UART_COUNT = 4
+};
+
static const struct MemmapEntry {
hwaddr base;
hwaddr size;
[OR1KSIM_DRAM] = { 0x00000000, 0 },
[OR1KSIM_UART] = { 0x90000000, 0x100 },
[OR1KSIM_ETHOC] = { 0x92000000, 0x800 },
- [OR1KSIM_OMPIC] = { 0x98000000, 16 },
+ [OR1KSIM_OMPIC] = { 0x98000000, OR1KSIM_CPUS_MAX * 8 },
};
static struct openrisc_boot_info {
static void openrisc_sim_serial_init(Or1ksimState *state, hwaddr base,
hwaddr size, int num_cpus,
- OpenRISCCPU *cpus[], int irq_pin)
+ OpenRISCCPU *cpus[], int irq_pin,
+ int uart_idx)
{
void *fdt = state->fdt;
char *nodename;
qemu_irq serial_irq;
+ char alias[sizeof("uart0")];
int i;
if (num_cpus > 1) {
serial_irq = get_cpu_irq(cpus, 0, irq_pin);
}
serial_mm_init(get_system_memory(), base, 0, serial_irq, 115200,
- serial_hd(0), DEVICE_NATIVE_ENDIAN);
+ serial_hd(OR1KSIM_UART_COUNT - uart_idx - 1),
+ DEVICE_NATIVE_ENDIAN);
/* Add device tree node for serial. */
nodename = g_strdup_printf("/serial@%" HWADDR_PRIx, base);
/* The /chosen node is created during fdt creation. */
qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
- qemu_fdt_setprop_string(fdt, "/aliases", "uart0", nodename);
+ snprintf(alias, sizeof(alias), "uart%d", uart_idx);
+ qemu_fdt_setprop_string(fdt, "/aliases", alias, nodename);
g_free(nodename);
}
}
/* We put fdt right after the kernel and/or initrd. */
- fdt_addr = ROUND_UP(load_start, 4);
+ fdt_addr = TARGET_PAGE_ALIGN(load_start);
ret = fdt_pack(fdt);
/* Should only fail if we've built a corrupted tree */
if (smp_cpus > 1) {
openrisc_sim_ompic_init(state, or1ksim_memmap[OR1KSIM_OMPIC].base,
- or1ksim_memmap[OR1KSIM_UART].size,
+ or1ksim_memmap[OR1KSIM_OMPIC].size,
smp_cpus, cpus, OR1KSIM_OMPIC_IRQ);
}
- openrisc_sim_serial_init(state, or1ksim_memmap[OR1KSIM_UART].base,
- or1ksim_memmap[OR1KSIM_UART].size, smp_cpus, cpus,
- OR1KSIM_UART_IRQ);
+ for (n = 0; n < OR1KSIM_UART_COUNT; ++n)
+ openrisc_sim_serial_init(state, or1ksim_memmap[OR1KSIM_UART].base +
+ or1ksim_memmap[OR1KSIM_UART].size * n,
+ or1ksim_memmap[OR1KSIM_UART].size,
+ smp_cpus, cpus, OR1KSIM_UART_IRQ, n);
load_addr = openrisc_load_kernel(ram_size, kernel_filename);
if (load_addr > 0) {
#include "qapi/error.h"
#include "qemu/qemu-print.h"
#include "cpu.h"
+#include "exec/exec-all.h"
static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
{
cpu->env.dflag = 0;
}
+static void openrisc_cpu_synchronize_from_tb(CPUState *cs,
+ const TranslationBlock *tb)
+{
+ OpenRISCCPU *cpu = OPENRISC_CPU(cs);
+
+ cpu->env.pc = tb->pc;
+}
+
+
static bool openrisc_cpu_has_work(CPUState *cs)
{
return cs->interrupt_request & (CPU_INTERRUPT_HARD |
static const struct TCGCPUOps openrisc_tcg_ops = {
.initialize = openrisc_translate_init,
+ .synchronize_from_tb = openrisc_cpu_synchronize_from_tb,
#ifndef CONFIG_USER_ONLY
.tlb_fill = openrisc_cpu_tlb_fill,